PolarFire-SoC
Can you use the eFP6 on the icicle kit to debug a soft RV32 core running in the fabric while Linux runs on the MSS ? #470
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I have built a design for the ICICLE Kit that implements the BASE_DESIGN with MSS running the HSS using BootMode1; plus, a completely independent RV32 implementation in the fabric that is running out of TCM that is initialized by the system controller from the external SPI flash. Both the HSS and my RV32 BareMetal code are booting and running correctly; If I open the HSS code in Softconsole and launch a 'attach' via the eFP6, I can debug the HSS code while the RV32 continues to run in the fabric. But, if I try to open the RV32 code in Softconsole and 'attach' through the eFP6 to start a debug session, OpenOCD fails to connect. If I remove JP9 and connect a FP4 via the 10-pin header, I can debug the RV32 code just fine (and also the HSS code - one at a time of course). So, what am I missing ? Is there something about the eFP6 that is preventing the connection through UJTAG ? |
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I've also tried this with a fabric design that only includes the RV32 implementation (no MSS) - same result. |
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The efp6 doesn’t support the soft CPUs unfortunately, you will need to use a flashpro5, this is listed in the softconsole release notes in general what you’re suggesting of the soft cpu debug with Linux running is no issue |
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The efp6 doesn’t support the soft CPUs unfortunately, you will need to use a flashpro5, this is listed in the softconsole release notes
in general what you’re suggesting of the soft cpu debug with Linux running is no issue