{"payload":{"pageCount":10,"repositories":[{"type":"Public","name":"FlooNoC","owner":"pulp-platform","isFork":false,"description":"A Fast, Low-Overhead On-chip Network","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":3,"issueCount":10,"starsCount":122,"forksCount":19,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-28T20:41:42.191Z"}},{"type":"Public","name":"snitch_cluster","owner":"pulp-platform","isFork":false,"description":"An energy-efficient RISC-V floating-point compute cluster.","allTopics":[],"primaryLanguage":{"name":"C","color":"#555555"},"pullRequestCount":6,"issueCount":19,"starsCount":49,"forksCount":48,"license":"Apache License 2.0","participation":[4,3,0,0,0,3,1,0,0,2,1,0,0,0,1,4,0,0,1,7,5,4,5,1,7,0,1,1,0,1,0,0,6,2,2,0,0,3,0,4,2,3,2,6,2,2,2,5,0,0,0,3],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-28T11:38:14.061Z"}},{"type":"Public","name":"dyn_spm","owner":"pulp-platform","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":1,"starsCount":2,"forksCount":0,"license":"Other","participation":[0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-28T07:33:42.655Z"}},{"type":"Public","name":"croc","owner":"pulp-platform","isFork":false,"description":"A PULP SoC for education, easy to understand and extend with a full flow for a physical design.","allTopics":["asic","riscv","systemverilog","rtl-design"],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":0,"starsCount":10,"forksCount":2,"license":"Other","participation":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,12,8,0,1,13,0,1,0,1,7],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-27T16:56:23.880Z"}},{"type":"Public","name":"chimera","owner":"pulp-platform","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"Python","color":"#3572A5"},"pullRequestCount":3,"issueCount":9,"starsCount":7,"forksCount":1,"license":"Other","participation":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-27T16:31:21.461Z"}},{"type":"Public","name":"hwpe-stream","owner":"pulp-platform","isFork":false,"description":"IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":5,"issueCount":1,"starsCount":18,"forksCount":18,"license":"Other","participation":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,1,0,1,3,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-27T15:39:10.660Z"}},{"type":"Public","name":"cheshire","owner":"pulp-platform","isFork":false,"description":"A minimal Linux-capable 64-bit RISC-V SoC built around CVA6","allTopics":["asic","riscv","systemverilog","rtl-design","fpga","simulation"],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":20,"issueCount":5,"starsCount":184,"forksCount":39,"license":"Other","participation":[0,0,1,0,0,0,0,3,0,0,0,0,0,0,0,0,0,0,5,0,1,1,2,2,0,0,0,0,1,1,0,0,0,0,0,0,0,0,0,4,0,1,0,0,0,0,0,1,0,2,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-27T14:17:01.267Z"}},{"type":"Public","name":"hyperbus","owner":"pulp-platform","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":2,"issueCount":1,"starsCount":18,"forksCount":2,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-27T14:15:49.283Z"}},{"type":"Public","name":"cva6","owner":"pulp-platform","isFork":true,"description":"This is the fork of CVA6 intended for PULP development.","allTopics":[],"primaryLanguage":{"name":"Assembly","color":"#6E4C13"},"pullRequestCount":7,"issueCount":1,"starsCount":15,"forksCount":673,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-27T12:40:24.060Z"}},{"type":"Public","name":"astral","owner":"pulp-platform","isFork":true,"description":"A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features with a ready-to-use FPGA flow on multiple boards.","allTopics":["c","fpga","space","accelerator","riscv","systemverilog","multicore","safety-critical","heterogeneous-computing"],"primaryLanguage":{"name":"Tcl","color":"#e4cc98"},"pullRequestCount":6,"issueCount":0,"starsCount":4,"forksCount":13,"license":"Other","participation":[52,40,30,22,21,11,6,4,2,5,2,3,0,3,2,0,0,4,0,4,3,1,3,1,3,1,0,2,0,7,3,1,14,9,21,2,7,6,14,21,10,6,4,2,1,0,0,0,1,2,1,1],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-27T11:16:22.182Z"}},{"type":"Public","name":"cvfpu","owner":"pulp-platform","isFork":true,"description":"Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":4,"issueCount":0,"starsCount":12,"forksCount":113,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-27T09:53:38.739Z"}},{"type":"Public","name":"mempool","owner":"pulp-platform","isFork":false,"description":"A 256-RISC-V-core system with low-latency access into shared L1 memory.","allTopics":["asic","risc-v","manycore"],"primaryLanguage":{"name":"C","color":"#555555"},"pullRequestCount":7,"issueCount":3,"starsCount":266,"forksCount":44,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-27T09:09:43.755Z"}},{"type":"Public","name":"iDMA","owner":"pulp-platform","isFork":false,"description":"A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":8,"issueCount":7,"starsCount":87,"forksCount":26,"license":"Other","participation":[0,0,0,4,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,6,5,1,2,1,0,0,0,0,0,2,0,1,0,0,1,0,0,1,0,2,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-26T14:43:29.968Z"}},{"type":"Public","name":"common_cells","owner":"pulp-platform","isFork":false,"description":"Common SystemVerilog components","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":6,"issueCount":28,"starsCount":497,"forksCount":140,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-26T13:40:40.115Z"}},{"type":"Public","name":"register_interface","owner":"pulp-platform","isFork":false,"description":"Generic Register Interface (contains various adapters)","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":1,"starsCount":95,"forksCount":24,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-25T19:57:57.981Z"}},{"type":"Public","name":"pulp-linux","owner":"pulp-platform","isFork":false,"description":"Build GNU/Linux for various PULP/Cheshire-based systems.","allTopics":[],"primaryLanguage":{"name":"C","color":"#555555"},"pullRequestCount":0,"issueCount":4,"starsCount":3,"forksCount":0,"license":null,"participation":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,10,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-24T21:37:07.170Z"}},{"type":"Public","name":"ITA","owner":"pulp-platform","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":1,"issueCount":0,"starsCount":9,"forksCount":2,"license":"Other","participation":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,6],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-24T16:44:06.402Z"}},{"type":"Public","name":"ara","owner":"pulp-platform","isFork":false,"description":"The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core","allTopics":["asic","cpu","vector","riscv","ara","rvv","rv64gcv"],"primaryLanguage":{"name":"C","color":"#555555"},"pullRequestCount":10,"issueCount":55,"starsCount":356,"forksCount":126,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-19T12:28:17.487Z"}},{"type":"Public","name":"spatz","owner":"pulp-platform","isFork":false,"description":"Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.","allTopics":[],"primaryLanguage":{"name":"C","color":"#555555"},"pullRequestCount":1,"issueCount":1,"starsCount":67,"forksCount":15,"license":"Apache License 2.0","participation":[0,0,0,0,0,0,0,0,0,2,0,0,0,0,2,0,0,0,1,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-19T11:24:33.486Z"}},{"type":"Public","name":"hwpe-doc","owner":"pulp-platform","isFork":false,"description":"Specification and documentation for HWPEs","allTopics":[],"primaryLanguage":{"name":"Python","color":"#3572A5"},"pullRequestCount":0,"issueCount":2,"starsCount":7,"forksCount":2,"license":null,"participation":[0,0,0,0,0,0,0,0,5,0,0,0,0,0,0,3,0,0,0,0,0,0,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,3,0,0,1,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-17T20:25:06.043Z"}},{"type":"Public","name":"opentitan","owner":"pulp-platform","isFork":true,"description":"OpenTitan: Open source silicon root of trust","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":1,"issueCount":0,"starsCount":1,"forksCount":752,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-16T10:23:56.928Z"}},{"type":"Public","name":"pulp_cluster","owner":"pulp-platform","isFork":false,"description":"The multi-core cluster of a PULP system.","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":3,"issueCount":4,"starsCount":55,"forksCount":21,"license":"Other","participation":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,16,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-16T10:22:01.343Z"}},{"type":"Public","name":"obi","owner":"pulp-platform","isFork":false,"description":"OBI SystemVerilog synthesizable interconnect IPs for on-chip communication","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":3,"issueCount":0,"starsCount":9,"forksCount":1,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-16T09:02:46.453Z"}},{"type":"Public","name":"pulp-ethernet","owner":"pulp-platform","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":2,"issueCount":0,"starsCount":8,"forksCount":1,"license":"Other","participation":[0,0,0,0,0,0,0,0,6,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-12T11:37:28.298Z"}},{"type":"Public","name":"occamy","owner":"pulp-platform","isFork":false,"description":"A high-efficiency system-on-chip for floating-point compute workloads.","allTopics":[],"primaryLanguage":{"name":"Python","color":"#3572A5"},"pullRequestCount":0,"issueCount":7,"starsCount":15,"forksCount":11,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-12T09:50:40.146Z"}},{"type":"Public","name":"pulp-trainlib","owner":"pulp-platform","isFork":false,"description":"Floating-Point Optimized On-Device Learning Library for the PULP Platform.","allTopics":[],"primaryLanguage":{"name":"C","color":"#555555"},"pullRequestCount":3,"issueCount":4,"starsCount":25,"forksCount":15,"license":"Apache License 2.0","participation":[5,1,1,1,0,0,0,3,3,8,5,1,0,0,7,2,10,2,7,5,13,11,2,3,16,5,16,20,22,1,1,1,0,1,5,4,12,5,16,0,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-12T09:08:27.614Z"}},{"type":"Public","name":"pulp-actions","owner":"pulp-platform","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"Python","color":"#3572A5"},"pullRequestCount":0,"issueCount":1,"starsCount":7,"forksCount":3,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-11T15:27:18.342Z"}},{"type":"Public","name":"axi_llc","owner":"pulp-platform","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":8,"issueCount":2,"starsCount":18,"forksCount":15,"license":"Other","participation":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-10T17:12:09.912Z"}},{"type":"Public","name":"cheshire-ihp130-o","owner":"pulp-platform","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"Tcl","color":"#e4cc98"},"pullRequestCount":0,"issueCount":1,"starsCount":23,"forksCount":4,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-10T15:06:15.432Z"}},{"type":"Public","name":"axi_vga","owner":"pulp-platform","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":0,"starsCount":2,"forksCount":1,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-10T12:15:54.040Z"}}],"repositoryCount":291,"userInfo":null,"searchable":true,"definitions":[],"typeFilters":[{"id":"all","text":"All"},{"id":"public","text":"Public"},{"id":"source","text":"Sources"},{"id":"fork","text":"Forks"},{"id":"archived","text":"Archived"},{"id":"template","text":"Templates"}],"compactMode":false},"title":"pulp-platform repositories"}