Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Precomputed sine table improvements #333

Closed
wants to merge 3 commits into from
Closed

Precomputed sine table improvements #333

wants to merge 3 commits into from

Conversation

orottier
Copy link
Owner

No description provided.

@github-actions

This comment was marked as outdated.

Sign in to view
orottier added 2 commits July 19, 2023 13:04
@orottier
Precomputed sine table is a fixed length array
bda1b73 
This may help elide some bound checks at runtime
@orottier
Propagate fixed length of precomputed sine table to the AudioProcessors
029dc04 
This means #321 is obsolete anyway. We force pre-computation of the sine
table in control thread, and then pass a static array to the audio
processors. Hence the rendering is lock-free

Fixes #321
@orottier orottier force-pushed the feature/precomputed-sine-table branch from d37b047 to 029dc04 Compare July 19, 2023 15:32
@github-actions

This comment was marked as outdated.

Sign in to view
@orottier orottier force-pushed the feature/precomputed-sine-table branch from e64dbc1 to f309e39 Compare October 20, 2023 14:39
@orottier
Copy link
Owner Author

/bench

@github-actions
Copy link 

Benchmark result:


bench_ctor
  Instructions:             4570520 (-0.000875%)
  L1 Accesses:              6844154 (-0.001008%)
  L2 Accesses:                54321 (-0.011044%)
  RAM Accesses:               61621 (+0.014608%)
  Estimated Cycles:         9272494 (+0.002330%)

bench_sine
  Instructions:            71610297 (+0.682984%)
  L1 Accesses:            104446359 (+0.589640%)
  L2 Accesses:               264058 (-1.639723%)
  RAM Accesses:               63438 (+1.525166%)
  Estimated Cycles:       107986979 (+0.580824%)

bench_sine_gain
  Instructions:            76741975 (+0.630951%)
  L1 Accesses:            112208486 (+0.538292%)
  L2 Accesses:               277190 (+0.291986%)
  RAM Accesses:               63538 (+1.317132%)
  Estimated Cycles:       115818266 (+0.550178%)

bench_sine_gain_delay
  Instructions:           150990897 (+0.289949%)
  L1 Accesses:            212232571 (+0.234684%)
  L2 Accesses:               526196 (+6.088973%)
  RAM Accesses:               65143 (+1.295288%)
  Estimated Cycles:       217143556 (+0.312782%)

bench_buffer_src
  Instructions:            17682361 (-0.000633%)
  L1 Accesses:             25749502 (-0.003662%)
  L2 Accesses:                87026 (+0.865796%)
  RAM Accesses:              100772 (+0.009924%)
  Estimated Cycles:        29711652 (+0.010576%)

bench_buffer_src_delay
  Instructions:            90601610 (-0.053533%)
  L1 Accesses:            123929760 (-0.061195%)
  L2 Accesses:               163858 (-2.238530%)
  RAM Accesses:              100788 (-0.107041%)
  Estimated Cycles:       128276630 (-0.076670%)

bench_buffer_src_iir
  Instructions:            41867064 (+0.000361%)
  L1 Accesses:             60995532 (-0.000866%)
  L2 Accesses:                87649 (+0.861910%)
  RAM Accesses:              100861 (+0.010907%)
  Estimated Cycles:        64963912 (+0.005545%)

bench_buffer_src_biquad
  Instructions:            37946018 (-0.000590%)
  L1 Accesses:             53443734 (-0.009207%)
  L2 Accesses:               135273 (+3.460065%)
  RAM Accesses:              100994 (+0.017826%)
  Estimated Cycles:        57654889 (+0.031801%)

bench_stereo_positional
  Instructions:            45823358 (+0.042012%)
  L1 Accesses:             68739845 (+0.123735%)
  L2 Accesses:               288343 (-13.83358%)
  RAM Accesses:              101064 (+0.012865%)
  Estimated Cycles:        73718800 (-0.197733%)

bench_stereo_panning_automation
  Instructions:            32353719 (+0.006516%)
  L1 Accesses:             48523920 (+0.215202%)
  L2 Accesses:               148071 (+8.580333%)
  RAM Accesses:              102329 (+1.446416%)
  Estimated Cycles:        52845790 (+0.406160%)

bench_analyser_node
  Instructions:            39845964 (+0.000366%)
  L1 Accesses:             55852321 (+0.000430%)
  L2 Accesses:               179953 (-0.012779%)
  RAM Accesses:              101418 (+0.002958%)
  Estimated Cycles:        60301716 (+0.000381%)

bench_hrtf_panners
  Instructions:          1783089940 (-0.013642%)
  L1 Accesses:           2559195353 (-0.030759%)
  L2 Accesses:             26524211 (-0.416992%)
  RAM Accesses:              176318 (+0.622621%)
  Estimated Cycles:      2697987538 (-0.048330%)

@orottier orottier closed this Oct 27, 2023
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers
No reviews
Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
1 participant
@orottier