ECE241_Verilog

Lmao let's be serious now!

What is this repo about?

This repo contains verilog codes, modelsim simulations, logisim schematics and other resources for the course ECE241 taught at the University of Toronto. This repo is to help the current batch of ECE 2T3 and upcoming batches of ECE 241 because the online resources are very limited and hard to find.

The code was validated using Intel's Quartus Prime Software using the tcl scripts (provided in the "Supporting Files" Directory.

How to contribute?

Contributions are most welcome but please read the CONTRIBUTING.md before generating a pull request, it will prevent your pull request from being rejected and help us review it more easily.

Contents:

• 2-to-1 multiplexer (Our dear mux)

• 4-to-1 multiplexer

• 4 bit 2-to-1 multiplexer

• 7-to-1 multiplexer

• Full adder

• Ripple carry adder

• 7 - Segment Hex Display

• Gated D-Latch

• D-flipflops (8 types without enable)

• D-flipflop (with enable)

• Register - 1 bit

• Register - 4 bit

• Register - 8 bit

• Register - n bit - Parameterized

• Shift Register

• Shift Register - Parallel load

• Toggle - flipflop

• Counter - 4 bit

• Updown counter - Parameterized

• Async counter

• Address Decoder (Memory)

• 110 Sequence Detector - Finite State Machine

Schematics

D-Latch:

RS-Latch:

Positive Edge D-Flip Flop:

Negative Edge D-Flip Flop:

Eight Bit Register:

Four Bit Shift Registers:

Toggle Flip Flop (T-Flip Flop)

110 Sequence Detector (State Diagram)

Disclaimer: I do not own the files in the "Supporting files directory". They are open-source files made available to me by University of Toronto and can be found at: https://github.com/UofT-HPRC/fake_fpga/releases