From ff0b506d7f270885b808f8905fe9e9bcb21af305 Mon Sep 17 00:00:00 2001 From: 1dentity84 <1270798434@qq.com> Date: Tue, 24 Sep 2024 22:46:49 +0800 Subject: [PATCH] add news --- content/en/news/023.md | 11 +++++++++++ content/ja/news/023.md | 11 +++++++++++ content/ko/news/023.md | 11 +++++++++++ content/ru/news/023.md | 11 +++++++++++ content/zh/news/023.md | 12 ++++++++++++ 5 files changed, 56 insertions(+) create mode 100644 content/en/news/023.md create mode 100644 content/ja/news/023.md create mode 100644 content/ko/news/023.md create mode 100644 content/ru/news/023.md create mode 100644 content/zh/news/023.md diff --git a/content/en/news/023.md b/content/en/news/023.md new file mode 100644 index 0000000..21c2822 --- /dev/null +++ b/content/en/news/023.md @@ -0,0 +1,11 @@ ++++ +title = 'Box64 Now Provides Initial Support for RVV 1.0, with Up to 300% Performance Boost – Code is Now Open Source and Upstreamed' +date = 2024-09-24 + ++++ + +The Box64 RISC-V backend initially used scalar instructions to emulate MMX, SSE*, and other x86_64 vector extensions, achieving good compatibility with rv64gc. However, since emulating a single vector instruction often requires several dozen scalar instructions, the performance of Box64 suffers significantly when running x86_64 programs that heavily rely on vector instructions. + +Recently, engineers and interns from PLCT Lab have introduced initial support for RVV 1.0 in the Box64 RISC-V backend, submitting over 30 related PRs. This new support allows efficient translation of over 100 SSE instructions to RVV instructions. + +[Read the full article](https://mp.weixin.qq.com/s/HxPo3ONjdJ52-Dsls8hl0A) \ No newline at end of file diff --git a/content/ja/news/023.md b/content/ja/news/023.md new file mode 100644 index 0000000..21c2822 --- /dev/null +++ b/content/ja/news/023.md @@ -0,0 +1,11 @@ ++++ +title = 'Box64 Now Provides Initial Support for RVV 1.0, with Up to 300% Performance Boost – Code is Now Open Source and Upstreamed' +date = 2024-09-24 + ++++ + +The Box64 RISC-V backend initially used scalar instructions to emulate MMX, SSE*, and other x86_64 vector extensions, achieving good compatibility with rv64gc. However, since emulating a single vector instruction often requires several dozen scalar instructions, the performance of Box64 suffers significantly when running x86_64 programs that heavily rely on vector instructions. + +Recently, engineers and interns from PLCT Lab have introduced initial support for RVV 1.0 in the Box64 RISC-V backend, submitting over 30 related PRs. This new support allows efficient translation of over 100 SSE instructions to RVV instructions. + +[Read the full article](https://mp.weixin.qq.com/s/HxPo3ONjdJ52-Dsls8hl0A) \ No newline at end of file diff --git a/content/ko/news/023.md b/content/ko/news/023.md new file mode 100644 index 0000000..21c2822 --- /dev/null +++ b/content/ko/news/023.md @@ -0,0 +1,11 @@ ++++ +title = 'Box64 Now Provides Initial Support for RVV 1.0, with Up to 300% Performance Boost – Code is Now Open Source and Upstreamed' +date = 2024-09-24 + ++++ + +The Box64 RISC-V backend initially used scalar instructions to emulate MMX, SSE*, and other x86_64 vector extensions, achieving good compatibility with rv64gc. However, since emulating a single vector instruction often requires several dozen scalar instructions, the performance of Box64 suffers significantly when running x86_64 programs that heavily rely on vector instructions. + +Recently, engineers and interns from PLCT Lab have introduced initial support for RVV 1.0 in the Box64 RISC-V backend, submitting over 30 related PRs. This new support allows efficient translation of over 100 SSE instructions to RVV instructions. + +[Read the full article](https://mp.weixin.qq.com/s/HxPo3ONjdJ52-Dsls8hl0A) \ No newline at end of file diff --git a/content/ru/news/023.md b/content/ru/news/023.md new file mode 100644 index 0000000..21c2822 --- /dev/null +++ b/content/ru/news/023.md @@ -0,0 +1,11 @@ ++++ +title = 'Box64 Now Provides Initial Support for RVV 1.0, with Up to 300% Performance Boost – Code is Now Open Source and Upstreamed' +date = 2024-09-24 + ++++ + +The Box64 RISC-V backend initially used scalar instructions to emulate MMX, SSE*, and other x86_64 vector extensions, achieving good compatibility with rv64gc. However, since emulating a single vector instruction often requires several dozen scalar instructions, the performance of Box64 suffers significantly when running x86_64 programs that heavily rely on vector instructions. + +Recently, engineers and interns from PLCT Lab have introduced initial support for RVV 1.0 in the Box64 RISC-V backend, submitting over 30 related PRs. This new support allows efficient translation of over 100 SSE instructions to RVV instructions. + +[Read the full article](https://mp.weixin.qq.com/s/HxPo3ONjdJ52-Dsls8hl0A) \ No newline at end of file diff --git a/content/zh/news/023.md b/content/zh/news/023.md new file mode 100644 index 0000000..de260e3 --- /dev/null +++ b/content/zh/news/023.md @@ -0,0 +1,12 @@ ++++ +title = 'Box64 初步支持 RVV 1.0，最高300%性能提升，代码已开源并合入上游（upstream）' +date = 2024-09-24 + ++++ + +Box64 RISC-V 后端使用标量指令模拟实现了 MMX、SSE* 等 x86_64 向量扩展，实现了对于 rv64gc 的良好兼容性，但一条向量指令往往需要十几条甚至几十条标量指令才能模拟，因此，对于大量使用向量指令的 x86_64 程序，Box64 的性能损失相对较大。 + +近日，PLCT 实验室的工程师和实习生为 Box64 RISC-V 后端新增了初步的 RVV 1.0 支持，提交相关 PR 30 余个，目前已经支持了百余条 SSE 指令到 RVV 指令的高效翻译。 + +[阅读全文](https://mp.weixin.qq.com/s/HxPo3ONjdJ52-Dsls8hl0A) +