Add support for AMP to discovery kit

README.md

@@ -212,6 +212,7 @@ The following table details the available targets:
 | `MACHINE=icicle-kit-es-nand`| ICICLE-KIT-ES, Icicle Kit engineering samples with Winbond W25N01GV NAND flash memory boot|
 | `MACHINE=icicle-kit-es-nor` | ICICLE-KIT-ES, Icicle Kit engineering samples with Micron MT25QL256 NOR flash memory boot |
 | `MACHINE=mpfs-disco-kit`    | MPFS-DISCO-KIT, PolarFire SoC Discovery Kit                                               |
+| `MACHINE=mpfs-disco-kit-amp`| MPFS-DISCO-KIT, PolarFire SoC Discovery Kit in AMP mode                                   |
 | `MACHINE=mpfs-video-kit`    | MPFS250-VIDEO-KIT, PolarFire SoC Video Kit                                                |
 | `MACHINE=m100pfsevp`        | M100PFSEVP, Aries M100PFSEVP PolarFire SoC-FPGA Evaluation Platform                       |
 

meta-polarfire-soc-bsp/conf/machine/mpfs-disco-kit-amp.conf

@@ -0,0 +1,39 @@
+#@TYPE: Machine
+#@NAME: mpfs-disco-kit
+#@SOC: Polarfire SoC
+#@DESCRIPTION: Machine configuration for the Microchip Polarfire SoC, Discovery kit
+
+require include/mpfs-common.inc
+
+MACHINE_TYPE = "amp"
+
+RISCV_SBI_FDT ?=  "mpfs-disco-kit-context-a.dtb"
+KERNEL_DTC_FLAGS += "-@"
+KERNEL_DEVICETREE ?= "microchip/${RISCV_SBI_FDT}"
+
+UBOOT_CONFIG = "mpfs_discokit"
+UBOOT_CONFIG[mpfs_discokit] = "microchip_mpfs_discokit_amp_defconfig"
+
+## Generate a boot.scr file which should be included
+##  in the boot partition. It will try to load a kernel image from mmc
+UBOOT_ENV = "boot"
+UBOOT_ENV_SUFFIX = "scr"
+UBOOT_ENV_SIZE = "0x2000"
+
+## Select the YAML file used for building the HSS payload
+HSS_PAYLOAD = "amp"
+
+## Set this to "freertos" for a Linux + FreeRTOS demo or "bm" for a Linux + Bare Metal demo
+AMP_DEMO = "freertos"
+# AMP_DEMO = "bm"
+
+IMAGE_INSTALL:append = " polarfire-soc-amp-examples"
+
+IMAGE_BOOT_FILES ?= " \
+    fitImage \
+    boot.scr \
+    uboot.env \
+"
+
+WKS_FILE ?= "mpfs-rootfs.wks"
+

meta-polarfire-soc-bsp/recipes-bsp/u-boot/files/0001-riscv-Add-AMP-support-for-the-MPFS-Discovery-Kit-boa.patch

@@ -0,0 +1,273 @@
+From ad8e85f95d82c24bd4d087100b972c147aed2f8b Mon Sep 17 00:00:00 2001
+From: Pierre-Henry Moussay <ph.moussay.dev@gmail.com>
+Date: Tue, 7 May 2024 02:45:07 +0100
+Subject: [PATCH] riscv: Add AMP support for the MPFS Discovery Kit board
+
+Just a dedicated configuration and dts for the Discovery kit in AMP mode
+
+Signed-off-by: Pierre-Henry Moussay <ph.moussay.dev@gmail.com>
+---
+ arch/riscv/dts/Makefile                       |   3 +-
+ .../dts/microchip-mpfs-disco-kit-amp.dts      | 175 ++++++++++++++++++
+ configs/microchip_mpfs_discokit_amp_defconfig |  30 +++
+ configs/microchip_mpfs_discokit_defconfig     |   4 +-
+ 4 files changed, 209 insertions(+), 3 deletions(-)
+ create mode 100644 arch/riscv/dts/microchip-mpfs-disco-kit-amp.dts
+ create mode 100644 configs/microchip_mpfs_discokit_amp_defconfig
+
+diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
+index 287034676a..2613e1b457 100644
+--- a/arch/riscv/dts/Makefile
++++ b/arch/riscv/dts/Makefile
+@@ -6,7 +6,8 @@ dtb-$(CONFIG_TARGET_ARIES_M100PFSEVP) += mpfs-m100pfsevp.dtb
+ dtb-$(CONFIG_TARGET_BEAGLEBOARD_BEAGLEVFIRE) += mpfs-beaglev-fire.dtb
+ dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb \
+ microchip-mpfs-icicle-kit-amp.dtb microchip-mpfs-icicle-kit-qspi-nor.dtb
+-dtb-$(CONFIG_TARGET_MICROCHIP_DISCOKIT) += microchip-mpfs-disco-kit.dtb
++dtb-$(CONFIG_TARGET_MICROCHIP_DISCOKIT) += microchip-mpfs-disco-kit.dtb \
++microchip-mpfs-disco-kit-amp.dtb
+ dtb-$(CONFIG_TARGET_MICROCHIP_VIDEOKIT) += microchip-mpfs-video-kit.dtb
+ dtb-$(CONFIG_TARGET_SUNDANCEDSP_POLARBERRY) += mpfs-polarberry.dtb
+ dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
+diff --git a/arch/riscv/dts/microchip-mpfs-disco-kit-amp.dts b/arch/riscv/dts/microchip-mpfs-disco-kit-amp.dts
+new file mode 100644
+index 0000000000..1b68ec9d6c
+--- /dev/null
++++ b/arch/riscv/dts/microchip-mpfs-disco-kit-amp.dts
+@@ -0,0 +1,175 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (C) 2024 Microchip Technology Inc.
++ * Padmarao Begari <padmarao.begari@microchip.com>
++ */
++
++/dts-v1/;
++
++#include "microchip-mpfs.dtsi"
++
++/* Clock frequency (in Hz) of the rtcclk */
++#define RTCCLK_FREQ		1000000
++
++/ {
++	model = "Microchip PolarFire-SoC Discovery Kit";
++	compatible = "microchip,mpfs-disco-kit", "microchip,mpfs";
++
++	aliases {
++		serial4 = &uart4;
++		ethernet0 = &mac0;
++	};
++
++	chosen {
++		stdout-path = "serial4";
++	};
++
++	cpus {
++		timebase-frequency = <RTCCLK_FREQ>;
++	};
++
++	ddr_cached_low: memory@80000000 {
++		device_type = "memory";
++		reg = <0x0 0x80000000 0x0 0x40000000>;
++		label = "kernel";
++	};
++
++	ddr_non_cached_low: memory@c4000000 {
++		device_type = "memory";
++		reg = <0x0 0xc4000000 0x0 0x6000000>;
++		label = "non-cached-low";
++	};
++
++	ddr_cached_high: memory@1022000000 {
++		device_type = "memory";
++		reg = <0x10 0x22000000 0x0 0x1e000000>;
++		label = "cached-high";
++	};
++
++	ddr_non_cached_high: memory@1412000000 {
++		device_type = "memory";
++		reg = <0x14 0x12000000 0x0 0x10000000>;
++		label = "non-cached-high";
++	};
++
++	reserved-memory {
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++
++		hss: hss-buffer {
++			compatible = "shared-dma-pool";
++			reg = <0x10 0x3fc00000 0x0 0x400000>;
++			no-map;
++		};
++
++		dma_non_cached_low: non-cached-low-buffer {
++			compatible = "shared-dma-pool";
++			size = <0x0 0x4000000>;
++			no-map;
++			linux,dma-default;
++			alloc-ranges = <0x0 0xc4000000 0x0 0x4000000>;
++			dma-ranges = <0x0 0xc4000000 0x0 0xc4000000 0x0 0x4000000>;
++		};
++
++		dma_non_cached_high: non-cached-high-buffer {
++			compatible = "shared-dma-pool";
++			size = <0x0 0x10000000>;
++			no-map;
++			linux,dma-default;
++			alloc-ranges = <0x14 0x12000000 0x0 0x10000000>;
++			dma-ranges = <0x14 0x12000000 0x14 0x12000000 0x0 0x10000000>;
++		};
++
++		fabricbuf0ddrc: buffer@88000000 {
++			compatible = "shared-dma-pool";
++			reg = <0x0 0x88000000 0x0 0x2000000>;
++			no-map;
++		};
++
++		fabricbuf1ddrnc: buffer@c8000000 {
++			compatible = "shared-dma-pool";
++			reg = <0x0 0xc8000000 0x0 0x2000000>;
++			no-map;
++		};
++
++		fabricbuf2ddrncwcb: buffer@d8000000 {
++			compatible = "shared-dma-pool";
++			reg = <0x0 0xd8000000 0x0 0x2000000>;
++			no-map;
++		};
++
++		non_cached: region@84000000 {
++			reg = <0x0 0x84000000 0x0 0x4000000>;
++			no-map;
++		};
++	};
++
++	udmabuf0 {
++		compatible = "ikwzm,u-dma-buf";
++		device-name = "udmabuf-ddr-c0";
++		minor-number = <0>;
++		size = <0x0 0x2000000>;
++		memory-region = <&fabricbuf0ddrc>;
++		sync-mode = <3>;
++	};
++
++	udmabuf1 {
++		compatible = "ikwzm,u-dma-buf";
++		device-name = "udmabuf-ddr-nc0";
++		minor-number = <1>;
++		size = <0x0 0x2000000>;
++		memory-region = <&fabricbuf1ddrnc>;
++		sync-mode = <3>;
++	};
++
++	udmabuf2 {
++		compatible = "ikwzm,u-dma-buf";
++		device-name = "udmabuf-ddr-nc-wcb0";
++		minor-number = <2>;
++		size = <0x0 0x2000000>;
++		memory-region = <&fabricbuf2ddrncwcb>;
++		sync-mode = <3>;
++	};
++};
++
++&refclk {
++	clock-frequency = <125000000>;
++};
++
++&cpu4 {
++	status = "disabled"; // in use by context b
++};
++
++&uart4 {
++	status = "okay";
++};
++
++// in use by context b
++&uart0 {
++	status = "disabled";
++};
++
++&mmc {
++	status = "okay";
++	bus-width = <4>;
++	disable-wp;
++	cap-mmc-highspeed;
++	cap-sd-highspeed;
++	card-detect-delay = <200>;
++	mmc-ddr-1_8v;
++	mmc-hs200-1_8v;
++	sd-uhs-sdr12;
++	sd-uhs-sdr25;
++	sd-uhs-sdr50;
++	sd-uhs-sdr104;
++};
++
++&mac0 {
++	status = "okay";
++	phy-mode = "sgmii";
++	phy-handle = <&phy0>;
++	phy0: ethernet-phy@11 {
++		 reg = <11>;
++	};
++};
+diff --git a/configs/microchip_mpfs_discokit_amp_defconfig b/configs/microchip_mpfs_discokit_amp_defconfig
+new file mode 100644
+index 0000000000..dd16716667
+--- /dev/null
++++ b/configs/microchip_mpfs_discokit_amp_defconfig
+@@ -0,0 +1,30 @@
++CONFIG_RISCV=y
++CONFIG_SYS_MALLOC_LEN=0x800000
++CONFIG_SYS_MALLOC_F_LEN=0x2000
++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
++CONFIG_ENV_SIZE=0x2000
++CONFIG_DEFAULT_DEVICE_TREE="microchip-mpfs-disco-kit-amp"
++CONFIG_SYS_PROMPT="RISC-V # "
++CONFIG_SYS_LOAD_ADDR=0x80200000
++CONFIG_TARGET_MICROCHIP_DISCOKIT=y
++CONFIG_ARCH_RV64I=y
++CONFIG_RISCV_SMODE=y
++CONFIG_FIT=y
++CONFIG_DISTRO_DEFAULTS=y
++CONFIG_DISPLAY_CPUINFO=y
++CONFIG_DISPLAY_BOARDINFO=y
++CONFIG_SYS_CBSIZE=256
++CONFIG_SYS_PBSIZE=282
++CONFIG_SYS_BOOTM_LEN=0x4000000
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_BOOTP_SEND_HOSTNAME=y
++CONFIG_DM_MTD=y
++CONFIG_SYSRESET=y
++CONFIG_CMD_MTDPARTS=y
++CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:2m(payload),128k(env),119m(rootfs)"
++CONFIG_CMD_UBI=y
++CONFIG_CMD_UBIFS=y
++CONFIG_MTD_UBI_WL_THRESHOLD=4096
++CONFIG_MTD_UBI_BEB_LIMIT=20
++CONFIG_OF_LIBFDT_OVERLAY=y
+diff --git a/configs/microchip_mpfs_discokit_defconfig b/configs/microchip_mpfs_discokit_defconfig
+index 3496e14fc0..dd16716667 100644
+--- a/configs/microchip_mpfs_discokit_defconfig
++++ b/configs/microchip_mpfs_discokit_defconfig
+@@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
+ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
+ CONFIG_ENV_SIZE=0x2000
+-CONFIG_DEFAULT_DEVICE_TREE="microchip-mpfs-disco-kit"
++CONFIG_DEFAULT_DEVICE_TREE="microchip-mpfs-disco-kit-amp"
+ CONFIG_SYS_PROMPT="RISC-V # "
+ CONFIG_SYS_LOAD_ADDR=0x80200000
+ CONFIG_TARGET_MICROCHIP_DISCOKIT=y
+@@ -27,4 +27,4 @@ CONFIG_CMD_UBI=y
+ CONFIG_CMD_UBIFS=y
+ CONFIG_MTD_UBI_WL_THRESHOLD=4096
+ CONFIG_MTD_UBI_BEB_LIMIT=20
+-CONFIG_OF_LIBFDT_OVERLAY=y
+\ No newline at end of file
++CONFIG_OF_LIBFDT_OVERLAY=y
+
+base-commit: 049a256e42b72a65ac3329fbe3085b47bdf20cbc
+-- 
+2.30.2
+

meta-polarfire-soc-bsp/recipes-bsp/u-boot/files/mpfs-disco-kit-amp/amp.yaml

@@ -0,0 +1,29 @@
+#
+# HSS Payload Generator
+#
+
+# First, we can optionally set a name for our image, otherwise one will be created dynamically
+set-name: 'PolarFire-SoC-HSS::Linux + FreeRTOS AMP'
+
+#
+# Next, we'll define the entry point addresses for each hart, as follows:
+#
+hart-entry-points: {u54_1: '0x80200000', u54_2: '0x80200000', u54_3: '0x80200000', u54_4: '0x91C00000'}
+#
+# Finally, we'll define a payloads (source binary file) that will be placed at certain regions in memory
+# The payload section is defined with the keyword payloads, and then a number of individual
+# payload descriptors.
+#
+# Each payload has a name (path to its ELF/bin file), an owner-hart, and optionally 1-3 secondary-harts.
+#
+# Additionally, it has a privilege mode in which it will start execution.
+#  * Valid privilege modes are PRV_M, PRV_S and PRV_U.
+#
+#
+# In this case, we have two payloads, one for Linux context one and another one for FreeRTOS context
+#
+# Case only matters for the ELF path names, not the keywords.
+# 
+payloads:
+  u-boot.bin: {exec-addr: '0x80200000', owner-hart: u54_1, secondary-hart: u54_2, secondary-hart: u54_3, priv-mode: prv_s}
+  amp-application.elf: {exec-addr: '0x91C00000', owner-hart: u54_4, priv-mode: prv_m, skip-opensbi: true}

meta-polarfire-soc-bsp/recipes-bsp/u-boot/files/mpfs-disco-kit-amp/boot.cmd

@@ -0,0 +1,12 @@
+setenv fdt_high 0xffffffffffffffff
+setenv initrd_high 0xffffffffffffffff
+
+load mmc 0:${distro_bootpart} ${scriptaddr} fitImage
+bootm start ${scriptaddr};
+bootm loados ${scriptaddr};
+# Try to load a ramdisk if available inside fitImage
+bootm ramdisk;
+bootm prep;
+fdt set /soc/ethernet@20110000 mac-address ${discokit_mac_addr0};
+run design_overlays;
+bootm go;

meta-polarfire-soc-bsp/recipes-bsp/u-boot/files/mpfs-disco-kit-amp/mpfs-disco-kit-amp.cfg

@@ -0,0 +1,7 @@
+CONFIG_MPFS_PRIORITISE_QSPI_BOOT=n
+CONFIG_ENV_IS_NOWHERE=n
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_FAT_INTERFACE="mmc"
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
+CONFIG_ENV_FAT_FILE="uboot.env"
+