Merged mss-rtc source code version 2.2.100.

driver-examples/mss/mss-rtc/mpfs-rtc-interrupt/src/application/hart0/e51.c

@@ -1,9 +1,13 @@
 /*******************************************************************************
- * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
+ * Copyright 2019 Microchip FPGA Embedded Systems Solutions.
  *
  * SPDX-License-Identifier: MIT
  *
- * Application code running on E51
+ * @file e51.c
+ *
+ * @author Microchip FPGA Embedded Systems Solutions
+ *
+ * @brief Application code running on E51
  *
  * PolarFire SoC MSS RTC interrupt example project
  */

driver-examples/mss/mss-rtc/mpfs-rtc-interrupt/src/application/hart1/u54_1.c

@@ -1,11 +1,13 @@
 /*******************************************************************************
- * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
+ * Copyright 2019 Microchip FPGA Embedded Systems Solutions.
  *
  * SPDX-License-Identifier: MIT
  *
- * MPFS HAL Embedded Software example
+ * @file u54_1.c
  *
- * Application code running on U54_1
+ * @author Microchip FPGA Embedded Systems Solutions
+ *
+ * @brief Application code running on U54_1.
  */
 
 #include "mpfs_hal/mss_hal.h"

driver-examples/mss/mss-rtc/mpfs-rtc-interrupt/src/application/hart2/u54_2.c

@@ -1,11 +1,13 @@
 /*******************************************************************************
- * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
+ * Copyright 2019 Microchip FPGA Embedded Systems Solutions.
  *
  * SPDX-License-Identifier: MIT
  *
- * MPFS HAL Embedded Software example
+ * @file u54_2.c
  *
- * Application code running on U54_2
+ * @author Microchip FPGA Embedded Systems Solutions
+ *
+ * @brief Application code running on U54_2 
  */
 
 #include <stdio.h>

driver-examples/mss/mss-rtc/mpfs-rtc-interrupt/src/application/hart3/u54_3.c

@@ -1,11 +1,13 @@
 /*******************************************************************************
- * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
+ * Copyright 2019 Microchip FPGA Embedded Systems Solutions.
  *
  * SPDX-License-Identifier: MIT
  *
- * MPFS HAL Embedded Software example
+ * @file u54_3.c
  *
- * Application code running on U54_3
+ * @author Microchip FPGA Embedded Systems Solutions
+ *
+ * @brief Application code running on U54_3
  */
 
 #include <stdio.h>

driver-examples/mss/mss-rtc/mpfs-rtc-interrupt/src/application/hart4/u54_4.c

@@ -1,11 +1,13 @@
 /*******************************************************************************
- * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
+ * Copyright 2019 Microchip FPGA Embedded Systems Solutions.
  *
  * SPDX-License-Identifier: MIT
  *
- * MPFS HAL Embedded Software example
+ * @file u54_4.c
  *
- * Application code running on U54_4
+ * @author Microchip FPGA Embedded Systems Solutions
+ *
+ * @brief Application code running on U54_4
  */
 
 #include <stdio.h>

driver-examples/mss/mss-rtc/mpfs-rtc-interrupt/src/application/inc/common.h

@@ -1,7 +1,11 @@
 /*******************************************************************************
- * Copyright 2019-2021 Microchip FPGA Embedded Systems Solution.
+ * Copyright 2019 Microchip FPGA Embedded Systems Solution.
  *
  * SPDX-License-Identifier: MIT
+ *
+ * @file common.h
+ *
+ * @author Microchip FPGA Embedded Systems Solutions
  */
 
 #ifndef COMMON_H_

driver-examples/mss/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/platform_config/mpfs_hal_config/mss_sw_config.h

@@ -1,10 +1,13 @@
 /*******************************************************************************
- * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions.
+ * Copyright 2019 Microchip FPGA Embedded Systems Solutions.
  *
  * SPDX-License-Identifier: MIT
  *
- * MPFS HAL Embedded Software
+ * @file mss_sw_config.h
  *
+ * @author Microchip FPGA Embedded Systems Solutions
+ *
+ * @brief MPFS HAL Embedded Software
  */
 
 /*******************************************************************************

driver-examples/mss/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/platform_config_ddr/mpfs_hal_config/mss_sw_config.h

@@ -1,10 +1,13 @@
 /*******************************************************************************
- * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions.
+ * Copyright 2019 Microchip FPGA Embedded Systems Solutions.
  *
  * SPDX-License-Identifier: MIT
  *
- * MPFS HAL Embedded Software
+ * @file mss_sw_config.h
  *
+ * @author Microchip FPGA Embedded Systems Solutions
+ *
+ * @brief MPFS HAL Embedded Software
  */
 
 /*******************************************************************************

driver-examples/mss/mss-rtc/mpfs-rtc-interrupt/src/platform/drivers/mss/mss_mmuart/mss_uart.c

@@ -1,12 +1,15 @@
 /*******************************************************************************
- * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions.
+ * Copyright 2019 Microchip FPGA Embedded Systems Solutions.
  *
  * SPDX-License-Identifier: MIT
- * 
- * PolarFire SoC Microprocessor Subsystem MMUART bare metal software driver
- * implementation.
+ *
+ * @file mss_uart.c
+ * @author Microchip FPGA Embedded Systems Solutions
+ * @brief PolarFire SoC Microprocessor Subsystem (MSS) MMUART bare metal
+ * software driver implementation.
  *
  */
+
 #include "mpfs_hal/mss_hal.h"
 #include "mss_uart_regs.h"
 #include "mss_uart.h"
@@ -62,6 +65,7 @@ static uint32_t g_uart_axi_pos = 0x0u;
 #define FCR_TRIG_LEVEL_MASK             0xC0u
 
 #define IIRF_MASK                       0x0Fu
+#define IER_MASK                        0x0Du
 
 #define INVALID_INTERRUPT               0u
 #define INVALID_IRQ_HANDLER             ((mss_uart_irq_handler_t) 0)
@@ -350,19 +354,19 @@ MSS_UART_irq_tx
 {
     ASSERT(pbuff != ((uint8_t*)0));
     ASSERT(tx_size > 0u);
+    ASSERT(TX_COMPLETE == this_uart->tx_buff_size);
 
-    if ((tx_size > 0u) && (pbuff != ((uint8_t*)0)))
+    if ((tx_size > 0u) && 
+        (pbuff != ((uint8_t*)0)) &&
+        (TX_COMPLETE == this_uart->tx_buff_size))
     {
         /* Initialize the transmit info for the UART instance with the
          * arguments */
         this_uart->tx_buffer = pbuff;
         this_uart->tx_buff_size = tx_size;
         this_uart->tx_idx = 0u;
 
-        /* assign default handler for data transfer */
-        this_uart->tx_handler = default_tx_handler;
-
-        /* enables TX interrupt */
+        /* Enables TX interrupt */
         this_uart->hw_reg->IER |= ETBEI_MASK;
         enable_irq(this_uart);
     }
@@ -439,19 +443,20 @@ MSS_UART_enable_irq
 {
     ASSERT(MSS_UART_INVALID_IRQ > irq_mask);
 
-    enable_irq(this_uart);
-
     if (MSS_UART_INVALID_IRQ > irq_mask)
     {
         /* irq_mask encoding: 1- enable
          * bit 0 - Receive Data Available Interrupt
          * bit 1 - Transmitter Holding  Register Empty Interrupt
          * bit 2 - Receiver Line Status Interrupt
          * bit 3 - Modem Status Interrupt
+         * 
+         * The use of the IER_MASK macro is to prevent the THRE to be
+         * set at this point of the design flow and to lead to a break
+         * later on.
          */
         this_uart->hw_reg->IER |= ((uint8_t)(((uint32_t)irq_mask &
-                                                         (uint32_t)IIRF_MASK)));
-
+                                                         (uint32_t)IER_MASK)));
 
         /* 
          * bit 4 - Receiver time-out interrupt
@@ -493,15 +498,6 @@ MSS_UART_disable_irq
      */
     this_uart->hw_reg->IEM &= (uint8_t)(~(((uint32_t)irq_mask >> 4u) &
                                                         ((uint32_t)IIRF_MASK)));
-
-    if(1 == this_uart->local_irq_enabled)
-    {
-        __disable_local_irq((int8_t)MMUART0_E51_INT);
-    }
-    else
-    {
-        disable_irq(this_uart);
-    }
 }
 
 /***************************************************************************//**
@@ -752,19 +748,13 @@ MSS_UART_set_tx_handler
     mss_uart_irq_handler_t handler
 )
 {
-    ASSERT(handler != INVALID_IRQ_HANDLER);
-
-    if (handler != INVALID_IRQ_HANDLER)
+    if (handler != NULL_HANDLER)
     {
         this_uart->tx_handler = handler;
-
-        /* Make TX buffer info invalid */
-        this_uart->tx_buffer = (const uint8_t*)0;
-        this_uart->tx_buff_size = 0u;
-
-        /* Enable transmitter holding register Empty interrupt. */
-        this_uart->hw_reg->IER |= ETBEI_MASK;
-        enable_irq(this_uart);
+    }
+    else
+    {
+        this_uart->tx_handler = default_tx_handler;
     }
 }
 
@@ -1610,6 +1600,11 @@ uart_isr
             {
                 (*(this_uart->tx_handler))(this_uart);
             }
+            if (this_uart->tx_idx == this_uart->tx_buff_size)
+            {
+                MSS_UART_disable_irq(this_uart, MSS_UART_TBE_IRQ);
+                this_uart->tx_buff_size = TX_COMPLETE;
+            }
         }
         break;
 
@@ -1650,7 +1645,7 @@ uart_isr
             }
 
             /* NACK interrupt */
-            if (this_uart->hw_reg->IIM &ENACKI)
+            if (this_uart->hw_reg->IIM & ENACKI_MASK)
             {
                 ASSERT(NULL_HANDLER != this_uart->nack_handler);
 
@@ -1661,7 +1656,7 @@ uart_isr
             }
 
             /* PID parity error interrupt */
-            if (this_uart->hw_reg->IIM & EPID_PEI)
+            if (this_uart->hw_reg->IIM & EPID_PEI_MASK)
             {
                 ASSERT(NULL_HANDLER != this_uart->pid_pei_handler);
 
@@ -1672,7 +1667,7 @@ uart_isr
             }
 
             /* LIN break detection interrupt */
-            if (this_uart->hw_reg->IIM & ELINBI)
+            if (this_uart->hw_reg->IIM & ELINBI_MASK)
             {
                 ASSERT(NULL_HANDLER != this_uart->break_handler);
 
@@ -1683,7 +1678,7 @@ uart_isr
             }
 
             /* LIN Sync detection interrupt */
-            if (this_uart->hw_reg->IIM & ELINSI)
+            if (this_uart->hw_reg->IIM & ELINSI_MASK)
             {
                 ASSERT(NULL_HANDLER != this_uart->sync_handler);
 
@@ -1747,15 +1742,6 @@ default_tx_handler
                 ++this_uart->tx_idx;
             }
         }
-
-        /* Flag Tx as complete if all data has been pushed into the Tx FIFO. */
-        if (this_uart->tx_idx == this_uart->tx_buff_size)
-        {
-            this_uart->tx_buff_size = TX_COMPLETE;
-
-            /* disables TX interrupt */
-            this_uart->hw_reg->IER &= ~ETBEI_MASK;
-        }
     }
 }