Merged mss-mpfs-hal example projects tag 1.8.136.

polarfire-soc · Nov 6, 2021 · e1f62c0 · e1f62c0
2 parents 21f5fe1 + d2ff985
commit e1f62c0
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diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/.cproject b/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/.cproject
@@ -281,7 +281,7 @@
 
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+                            <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.addtools.createlisting.1565669341" name="Create extended listing" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.addtools.createlisting" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 
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@@ -437,7 +437,7 @@
 
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+                                <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createflash.choice.613969723" name="Output file format (-O)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createflash.choice" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createflash.choice.ihex" valueType="enumerated"/>
 
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@@ -757,15 +757,15 @@
 
             <storageModule moduleId="cdtBuildSystem" version="4.0.0">
 
-                <configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="${cross_rm} -rf" description="Payload is loaded by a bootlaoder ( mpfs-ddr-demo-program)" errorParsers="org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.GCCErrorParser" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.2097241311.1710962890.5397432.2031190079.410302868" name="icicle-kit-payload-u54-2" parent="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug" prebuildStep="${env_var:MACRO_PYTHON_BINARY_PATH_AND_EXECUTABLE} ../src/platform/soc_config_generator/mpfs_configuration_generator.py ../src/boards/icicle-kit-es/fpga_design/xml/ICICLE_MSS_eMMC_cfg.xml   ../src/boards/icicle-kit-es ">
+                <configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="${cross_rm} -rf" description="Payload is loaded by a bootloader( mpfs-ddr-demo-program)" errorParsers="org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.GCCErrorParser" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.2097241311.1710962890.5397432.2031190079.410302868" name="icicle-kit-payload-u54-2" parent="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug" prebuildStep="${env_var:MACRO_PYTHON_BINARY_PATH_AND_EXECUTABLE} ../src/platform/soc_config_generator/mpfs_configuration_generator.py ../src/boards/icicle-kit-es/fpga_design/xml/ICICLE_MSS_eMMC_cfg.xml   ../src/boards/icicle-kit-es ">
 
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@@ -905,7 +905,7 @@
 
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-                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src/platform/platform_config_reference/linker/mpfs-ddr-loaded-by-boot-loader.ld}&quot;"/>
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src/boards/icicle-kit-es/platform_config/linker/mpfs-ddr-loaded-by-boot-loader-u54-2.ld}&quot;"/>
 
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@@ -1161,7 +1161,7 @@
 
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-                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src/platform/platform_config_reference/linker/mpfs-ddr-loaded-by-boot-loader.ld}&quot;"/>
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src/boards/icicle-kit-es/platform_config/linker/mpfs-ddr-loaded-by-boot-loader-u54-3.ld}&quot;"/>
 
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@@ -1417,7 +1417,7 @@
 
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-                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src/platform/platform_config_reference/linker/mpfs-ddr-loaded-by-boot-loader.ld}&quot;"/>
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src/boards/icicle-kit-es/platform_config/linker/mpfs-ddr-loaded-by-boot-loader-u54-4.ld}&quot;"/>
 
                                 </option>
 
@@ -1761,17 +1761,27 @@
 
         </configuration>
 
+        <configuration configurationName="Icicle-kit-coremark-stack-in-scratchpad-debug"/>
+
         <configuration configurationName="Icicle-kit-debug">
 
             <resource resourceType="PROJECT" workspacePath="/mpfs-hal-coremark"/>
 
         </configuration>
 
+        <configuration configurationName="Icicle-kit-coremark-stack-in-lim-debug"/>
+
+        <configuration configurationName="icicle-kit-payload-u54-2"/>
+
         <configuration configurationName="Icicle-kit-payload-u54-1">
 
             <resource resourceType="PROJECT" workspacePath="/mpfs-hal-coremark"/>
 
         </configuration>
+
+        <configuration configurationName="icicle-kit-payload-u54-3"/>
+
+        <configuration configurationName="icicle-kit-payload-u54-4"/>
 
     </storageModule>
 

diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/README.md b/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/README.md
@@ -9,7 +9,11 @@ This example project runs the Cormark performace test.
 
 To use this example you will need to obtain the coremark source files from the
 Embedded Microprocessor Benchmark Consortium (EEMBC). These are placed in the 
-coremark directory
+coremark directory.
+This will be done automatically using gitsubmodule, once you clone the repo using 
+git and then run the git submodule command
+**git submodule update --init --recursive\n**
+
 
 To use this project you will need a UART terminal configured as below:
     - 115200 baud
@@ -430,8 +434,18 @@ Example 5
 
 
 
-## Loading the Payload binary
-
-When the project configuration <Icicle-kit-payload-u54-1> is selected, the resulting binary requires loading using a boot-loader.
+## Loading the Payload binary when using DDR
+
+When using the folloing build configurations a boot-loader progam must be used to load the binary or elf:
+    -    Icicle-kit-payload-u54-1
+	-    Icicle-kit-payload-u54-2
+	-    Icicle-kit-payload-u54-3
+	-    Icicle-kit-payload-u54-4
+
 The MPFS HAL DDR DEMO program bundled with this example can be used. Load the MPFS HAL DDR DEMO binary to envm and use the CLI menu to load the binary.
-
+For payload 2 to 4, the default load address of 0x80000000 will need to be changed to match the required load address 0x800A0000 for U54-2, 0x80140000 for U54-3 or 0x801E0000 for U54-4.
+
+The HSS can also be used. Please find the details here:
+[HSS payloads](https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/software-development/hss-payloads.md)
+The entry points for the yaml file need to match the entry point used in each elf. These are :
+{u54_1: '0x80000000', u54_2: '0x800A0000', u54_3: '0x80140000', u54_4: '0x801E0000'}
diff --git a/...fs-hal/mpfs-hal-coremark/src/boards/icicle-kit-es/fpga_design_config/fpga_design_config.h b/...fs-hal/mpfs-hal-coremark/src/boards/icicle-kit-es/fpga_design_config/fpga_design_config.h
@@ -35,10 +35,10 @@
 #define  LIBERO_SETTING_XML_VERSION_MAJOR                           0
 #define  LIBERO_SETTING_XML_VERSION_MINOR                           5
 #define  LIBERO_SETTING_XML_VERSION_PATCH                           3
-#define  LIBERO_SETTING_HEADER_GENERATOR_VERSION                    "0.6.3"
+#define  LIBERO_SETTING_HEADER_GENERATOR_VERSION                    "0.6.4"
 #define  LIBERO_SETTING_HEADER_GENERATOR_VERSION_MAJOR              0
 #define  LIBERO_SETTING_HEADER_GENERATOR_VERSION_MINOR              6
-#define  LIBERO_SETTING_HEADER_GENERATOR_VERSION_PATCH              3
+#define  LIBERO_SETTING_HEADER_GENERATOR_VERSION_PATCH              4
 
 #include "memory_map/hw_memory.h"
 #include "memory_map/hw_apb_split.h"
@@ -58,7 +58,9 @@
 #include "memory_map/hw_mpu_mmc.h"
 #include "memory_map/hw_mpu_scb.h"
 #include "memory_map/hw_mpu_trace.h"
+#include "memory_map/hw_nvm_map.h"
 #include "io/hw_mssio_mux.h"
+#include "io/hw_mssio_mux_alternate.h"
 #include "io/hw_hsio_mux.h"
 #include "sgmii/hw_sgmii_tip.h"
 #include "ddr/hw_ddr_options.h"