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MSS configuration: update to 2022.3 and osd(On-Screen-Display)
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Re-generated the MSS configuration file with the 2022.3 MSS configurator

Update required Libero version in Readme and TCL script.
Update TCL script with On-Screen-Display(OSD) feature.

The existing design released on the GitHub uses the name sev-kit.
This change replaces all such instances with the correct  name
"PolarFire SoC Video kit".

Signed-off-by: Vattipalli Praveen <praveen.kumar@microchip.com>
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praveenkumari30718 committed Mar 15, 2023
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2 changes: 1 addition & 1 deletion .gitignore
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
*.job
*.digest
*.patch
script_support/MSS_SEV/*
script_support/MSS_VIDEO_KIT/*
109 changes: 54 additions & 55 deletions MPFS_SEV_KIT_REFERENCE_DESIGN.tcl → MPFS_VIDEO_KIT_REFERENCE_DESIGN.tcl
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Original file line number Diff line number Diff line change
@@ -1,13 +1,12 @@
#
# // PFSoC SEV Kit H264 I frame Encoder demo Libero design
# // PFSoC VIDEO Kit H264 I frame Encoder demo Libero design
#
# // Check Libero version and path lenth to verify project can be created
#

if {[string compare [string range [get_libero_version] 0 end-3] "2022.2.0"]==0} {
puts "Libero v2022.2 detected."
if {[string compare [string range [get_libero_version] 0 end-4] "2022.3"]==0} {
puts "Libero v2022.3 detected."
} else {
error "Incorrect Libero version. Please use Libero v2022.2 to run these scripts."
error "Incorrect Libero version. Please use Libero v2022.3 to run these scripts."
}

if { [lindex $tcl_platform(os) 0] == "Windows" } {
Expand Down Expand Up @@ -48,8 +47,8 @@ set mss_config_loc "$install_loc/bin64/pfsoc_mss"
set local_dir [pwd]
set src_path ./script_support
set constraint_path ./script_support/constraint
set release_tag "2022.2"
set project_name "SEVPFSOC_H264"
set release_tag "2022.3"
set project_name "VKPFSOC_H264"
set project_dir "$local_dir/$project_name"

source ./script_support/additional_configurations/functions.tcl
Expand All @@ -68,51 +67,51 @@ new_project \
-linked_files_root_dir_env {} \
-hdl {VERILOG} \
-family {PolarFireSoC} \
-die {MPFS250T_ES} \
-die {MPFS250TS} \
-package {FCG1152} \
-speed {-1} \
-die_voltage {1.0} \
-part_range {EXT} \
-part_range {IND} \
-adv_options {IO_DEFT_STD:LVCMOS 1.8V} \
-adv_options {RESTRICTPROBEPINS:1} \
-adv_options {RESTRICTSPIPINS:0} \
-adv_options {SYSTEM_CONTROLLER_SUSPEND_MODE:0} \
-adv_options {TEMPR:EXT} \
-adv_options {VCCI_1.2_VOLTR:EXT} \
-adv_options {VCCI_1.5_VOLTR:EXT} \
-adv_options {VCCI_1.8_VOLTR:EXT} \
-adv_options {VCCI_2.5_VOLTR:EXT} \
-adv_options {VCCI_3.3_VOLTR:EXT} \
-adv_options {VOLTR:EXT}
-adv_options {TEMPR:IND} \
-adv_options {VCCI_1.2_VOLTR:IND} \
-adv_options {VCCI_1.5_VOLTR:IND} \
-adv_options {VCCI_1.8_VOLTR:IND} \
-adv_options {VCCI_2.5_VOLTR:IND} \
-adv_options {VCCI_3.3_VOLTR:IND} \
-adv_options {VOLTR:IND}

#
# // Download required cores
#

download_core -vlnv {Microsemi:SolutionCore:Bayer_Interpolation:4.2.0} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microsemi:SolutionCore:Bayer_Interpolation:4.4.0} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:CORERESET_PF:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:CORERXIODBITALIGN:2.2.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microsemi:SolutionCore:Gamma_Correction:4.2.0} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microsemi:SolutionCore:Image_Enhancement:4.3.0} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microsemi:SolutionCore:IMAGE_SCALER:4.0.0} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microsemi:SolutionCore:IMAGE_SCALER:4.1.0} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microsemi:SgCore:PFSOC_INIT_MONITOR:1.0.304} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Microsemi:SolutionCore:mipicsi2rxdecoderPF:4.4.0} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:SgCore:PF_CCC:2.2.214} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Microchip:SolutionCore:mipicsi2rxdecoderPF:4.7.0} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:SgCore:PF_CCC:2.2.220} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SgCore:PF_CLK_DIV:1.0.103} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SystemBuilder:PF_IOD_GENERIC_RX:2.1.109} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SystemBuilder:PF_IOD_GENERIC_RX:2.1.110} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SgCore:PF_OSC:1.0.102} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Microsemi:SolutionCore:RGBtoYCbCr:4.4.0} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:SgCore:PF_XCVR_REF_CLK:1.0.103} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Microsemi:SolutionCore:DDR_AXI4_ARBITER_PF:2.1.0} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microchip:SolutionCore:H264_Iframe_Encoder:1.3.0} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microchip:SolutionCore:H264_Iframe_Encoder:1.4.0} -location {www.microchip-ip.com/repositories/DirectCore}


#
# // Generate base design
#
exec $mss_config_loc -GENERATE -CONFIGURATION_FILE:$src_path/MSS_SEV/MSS_SEV.cfg -OUTPUT_DIR:${src_path}/MSS_SEV
import_mss_component -file "$src_path/MSS_SEV/MSS_SEV.cxz"
exec $mss_config_loc -GENERATE -CONFIGURATION_FILE:$src_path/MSS_VIDEO_KIT/MSS_VIDEO_KIT.cfg -OUTPUT_DIR:${src_path}/MSS_VIDEO_KIT
import_mss_component -file "$src_path/MSS_VIDEO_KIT/MSS_VIDEO_KIT.cxz"


#This Tcl file sources other Tcl files to build the design(on which recursive export is run) in a bottom-up fashion
Expand All @@ -122,7 +121,7 @@ source ${src_path}/hdl_source.tcl
build_design_hierarchy

#Sourcing the Tcl files in which HDL+ core definitions are created for HDL modules
source ${src_path}/components/video_fifo.tcl
source ${src_path}/components/video_fifo.tcl
source ${src_path}/components/apb3_if.tcl
source ${src_path}/components/H264/data_packer_h264.tcl
build_design_hierarchy
Expand Down Expand Up @@ -157,9 +156,9 @@ source ${src_path}/components/H264/H264_DDR_WRITE.tcl
source ${src_path}/components/H264/h264_top.tcl
source ${src_path}/components/video_processing.tcl
source ${src_path}/components/H264/Video_Pipeline.tcl
source ${src_path}/components/H264/SEVPFSOC_H264.tcl
source ${src_path}/components/H264/VKPFSOC_H264.tcl
build_design_hierarchy
set_root -module {SEVPFSOC_TOP::work}
set_root -module {VKPFSOC_TOP::work}
#
# // Derive timing constraints
#
Expand All @@ -170,9 +169,9 @@ derive_constraints_sdc

import_files \
-convert_EDN_to_HDL 0 \
-io_pdc "${constraint_path}/io/SEV_MAC.pdc" \
-io_pdc "${constraint_path}/io/SEV_MMUART0.pdc" \
-io_pdc "${constraint_path}/io/SEV_MMUART1.pdc" \
-io_pdc "${constraint_path}/io/VIDEO_KIT_MAC.pdc" \
-io_pdc "${constraint_path}/io/VIDEO_KIT_MMUART0.pdc" \
-io_pdc "${constraint_path}/io/VIDEO_KIT_MMUART1.pdc" \
-io_pdc "${constraint_path}/io/user.pdc" \

set_as_target -type {io_pdc} -file "${constraint_path}/io/user.pdc"
Expand All @@ -189,43 +188,43 @@ import_files -convert_EDN_to_HDL 0 -fp_pdc "${constraint_path}/fp/user.pdc"
import_files \
-convert_EDN_to_HDL 0 \
-sdc "${constraint_path}/user.sdc"
set_as_target -type {sdc} -file "${constraint_path}/user.sdc"
set_as_target -type {sdc} -file "${constraint_path}/user.sdc"
#
# // Associate imported constraints with the design flow
#
organize_tool_files -tool {SYNTHESIZE} \
-file "${project_dir}/constraint/SEVPFSOC_TOP_derived_constraints.sdc" \
-module {SEVPFSOC_TOP::work} \
-input_type {constraint}
-file "${project_dir}/constraint/VKPFSOC_TOP_derived_constraints.sdc" \
-module {VKPFSOC_TOP::work} \
-input_type {constraint}

organize_tool_files -tool {PLACEROUTE} \
-file "${project_dir}/constraint/io/SEV_MAC.pdc" \
-file "${project_dir}/constraint/io/SEV_MMUART0.pdc" \
-file "${project_dir}/constraint/io/SEV_MMUART1.pdc" \
-file "${project_dir}/constraint/io/VIDEO_KIT_MAC.pdc" \
-file "${project_dir}/constraint/io/VIDEO_KIT_MMUART0.pdc" \
-file "${project_dir}/constraint/io/VIDEO_KIT_MMUART1.pdc" \
-file "${project_dir}/constraint/io/user.pdc" \
-file "${project_dir}/constraint/SEVPFSOC_TOP_derived_constraints.sdc" \
-file "${project_dir}/constraint/VKPFSOC_TOP_derived_constraints.sdc" \
-file "${project_dir}/constraint/user.sdc" \
-file "${project_dir}/constraint/fp/user.pdc" \
-module {SEVPFSOC_TOP::work} \
-module {VKPFSOC_TOP::work} \
-input_type {constraint}

set_as_target -type {io_pdc} -file "${project_dir}/constraint/io/user.pdc"
save_project

organize_tool_files -tool {VERIFYTIMING} \
-file "${project_dir}/constraint/SEVPFSOC_TOP_derived_constraints.sdc" \
-file "${project_dir}/constraint/VKPFSOC_TOP_derived_constraints.sdc" \
-file "${project_dir}/constraint/user.sdc" \
-module {SEVPFSOC_TOP::work} \
-module {VKPFSOC_TOP::work} \
-input_type {constraint}

#
# // Run the design flow and add eNVM clients
# // Run the design flow and add eNVM clients
#
if {[info exists SYNTHESIZE]} {
run_tool -name {SYNTHESIZE}
}
configure_tool -name {VERIFYTIMING} -params {CONSTRAINTS_COVERAGE:1} -params {FORMAT:XML} -params {MAX_EXPANDED_PATHS_TIMING:1} -params {MAX_EXPANDED_PATHS_VIOLATION:0} -params {MAX_PARALLEL_PATHS_TIMING:1} -params {MAX_PARALLEL_PATHS_VIOLATION:1} -params {MAX_PATHS_INTERACTIVE_REPORT:1000} -params {MAX_PATHS_TIMING:5} -params {MAX_PATHS_VIOLATION:20} -params {MAX_TIMING_FAST_HV_LT:1} -params {MAX_TIMING_MULTI_CORNER:1} -params {MAX_TIMING_SLOW_LV_HT:1} -params {MAX_TIMING_SLOW_LV_LT:1} -params {MAX_TIMING_VIOLATIONS_FAST_HV_LT:1} -params {MAX_TIMING_VIOLATIONS_MULTI_CORNER:1} -params {MAX_TIMING_VIOLATIONS_SLOW_LV_HT:1} -params {MAX_TIMING_VIOLATIONS_SLOW_LV_LT:1} -params {MIN_TIMING_FAST_HV_LT:1} -params {MIN_TIMING_MULTI_CORNER:1} -params {MIN_TIMING_SLOW_LV_HT:1} -params {MIN_TIMING_SLOW_LV_LT:1} -params {MIN_TIMING_VIOLATIONS_FAST_HV_LT:1} -params {MIN_TIMING_VIOLATIONS_MULTI_CORNER:1} -params {MIN_TIMING_VIOLATIONS_SLOW_LV_HT:1} -params {MIN_TIMING_VIOLATIONS_SLOW_LV_LT:1} -params {SLACK_THRESHOLD_VIOLATION:0.0} -params {SMART_INTERACTIVE:1}
configure_tool -name {PLACEROUTE} -params {DELAY_ANALYSIS:MAX} -params {EFFORT_LEVEL:true} -params {GB_DEMOTION:true} -params {INCRPLACEANDROUTE:false} -params {IOREG_COMBINING:false} -params {MULTI_PASS_CRITERIA:VIOLATIONS} -params {MULTI_PASS_LAYOUT:false} -params {NUM_MULTI_PASSES:5} -params {PDPR:false} -params {RANDOM_SEED:0} -params {REPAIR_MIN_DELAY:false} -params {REPLICATION:true} -params {SLACK_CRITERIA:WORST_SLACK} -params {SPECIFIC_CLOCK:} -params {START_SEED_INDEX:1} -params {STOP_ON_FIRST_PASS:false} -params {TDPR:true}
}
configure_tool -name {VERIFYTIMING} -params {CONSTRAINTS_COVERAGE:1} -params {FORMAT:XML} -params {MAX_EXPANDED_PATHS_TIMING:1} -params {MAX_EXPANDED_PATHS_VIOLATION:0} -params {MAX_PARALLEL_PATHS_TIMING:1} -params {MAX_PARALLEL_PATHS_VIOLATION:1} -params {MAX_PATHS_INTERACTIVE_REPORT:1000} -params {MAX_PATHS_TIMING:5} -params {MAX_PATHS_VIOLATION:20} -params {MAX_TIMING_FAST_HV_LT:1} -params {MAX_TIMING_MULTI_CORNER:1} -params {MAX_TIMING_SLOW_LV_HT:1} -params {MAX_TIMING_SLOW_LV_LT:1} -params {MAX_TIMING_VIOLATIONS_FAST_HV_LT:1} -params {MAX_TIMING_VIOLATIONS_MULTI_CORNER:1} -params {MAX_TIMING_VIOLATIONS_SLOW_LV_HT:1} -params {MAX_TIMING_VIOLATIONS_SLOW_LV_LT:1} -params {MIN_TIMING_FAST_HV_LT:1} -params {MIN_TIMING_MULTI_CORNER:1} -params {MIN_TIMING_SLOW_LV_HT:1} -params {MIN_TIMING_SLOW_LV_LT:1} -params {MIN_TIMING_VIOLATIONS_FAST_HV_LT:1} -params {MIN_TIMING_VIOLATIONS_MULTI_CORNER:1} -params {MIN_TIMING_VIOLATIONS_SLOW_LV_HT:1} -params {MIN_TIMING_VIOLATIONS_SLOW_LV_LT:1} -params {SLACK_THRESHOLD_VIOLATION:0.0} -params {SMART_INTERACTIVE:1}
configure_tool -name {PLACEROUTE} -params {DELAY_ANALYSIS:MAX} -params {EFFORT_LEVEL:true} -params {GB_DEMOTION:true} -params {INCRPLACEANDROUTE:false} -params {IOREG_COMBINING:false} -params {MULTI_PASS_CRITERIA:VIOLATIONS} -params {MULTI_PASS_LAYOUT:false} -params {NUM_MULTI_PASSES:5} -params {PDPR:false} -params {RANDOM_SEED:0} -params {REPAIR_MIN_DELAY:false} -params {REPLICATION:true} -params {SLACK_CRITERIA:WORST_SLACK} -params {SPECIFIC_CLOCK:} -params {START_SEED_INDEX:1} -params {STOP_ON_FIRST_PASS:false} -params {TDPR:true}

if {[info exists PLACEROUTE]} {
run_tool -name {PLACEROUTE}
Expand All @@ -234,22 +233,22 @@ if {[info exists PLACEROUTE]} {
}

if {[info exists HSS_UPDATE]} {
if !{[file exists "./script_support/hss-envm-wrapper.mpfs-sev-kit.hex"]} {
if {[catch {exec wget https://github.com/polarfire-soc/hart-software-services/releases/latest/download/hss-envm-wrapper.mpfs-sev-kit.hex -P ./script_support/} issue]} {
if !{[file exists "./script_support/hss-envm-wrapper.mpfs-video-kit.hex"]} {
if {[catch {exec wget https://github.com/polarfire-soc/hart-software-services/releases/latest/download/hss-envm-wrapper.mpfs-video-kit.hex -P ./script_support/} issue]} {
}
}
create_eNVM_config "$local_dir/script_support/MSS_SEV/ENVM.cfg" "$local_dir/script_support/hss-envm-wrapper.mpfs-sev-kit.hex"

create_eNVM_config "$local_dir/script_support/MSS_VIDEO_KIT/ENVM.cfg" "$local_dir/script_support/hss-envm-wrapper.mpfs-video-kit.hex"
run_tool -name {GENERATEPROGRAMMINGDATA}
configure_envm -cfg_file {script_support/MSS_SEV/ENVM.cfg}
configure_envm -cfg_file {script_support/MSS_VIDEO_KIT/ENVM.cfg}
}

if {[info exists GENERATE_PROGRAMMING_DATA]} {
run_tool -name {GENERATEPROGRAMMINGDATA}
run_tool -name {GENERATEPROGRAMMINGDATA}
} elseif {[info exists PROGRAM]} {
run_tool -name {GENERATEPROGRAMMINGDATA}
run_tool -name {GENERATEPROGRAMMINGDATA}
run_tool -name {PROGRAMDEVICE}
} elseif {[info exists EXPORT_FPE]} {
} elseif {[info exists EXPORT_FPE]} {
if {[info exists HSS_UPDATE]} {
if {$EXPORT_FPE == 1} {
export_fpe_job $project_name $local_dir "ENVM FABRIC_SNVM"
Expand All @@ -265,4 +264,4 @@ if {[info exists GENERATE_PROGRAMMING_DATA]} {
}
}

save_project
save_project
16 changes: 8 additions & 8 deletions Readme.md
View file
Original file line number Diff line number Diff line change
@@ -1,12 +1,12 @@
# PolarFire&reg; SoC Sev Kit Reference Design Generation Tcl Scripts - Libero&reg; SoC v2022.2
# PolarFire&reg; SoC Video Kit Reference Design Generation Tcl Scripts - Libero&reg; SoC v2022.3

## Description

This repository can be used to generate a reference design for the PolarFire SoC Sev Kit. This reference design will have the same or extended functionality compared to the pre-programmed FPGA design on the Sev Kit.
This repository can be used to generate a reference design for the PolarFire SoC Video Kit. This reference design will have the same or extended functionality compared to the pre-programmed FPGA design on the Video Kit.

A Libero SoC Tcl script is provided to generate the reference design using Libero SoC along with device specific I/O constraints.

This repository supports Libero SoC v2022.2, which is available for download [here](https://www.microsemi.com/product-directory/design-resources/1750-libero-soc#downloads).
This repository supports Libero SoC v2022.3, which is available for download [here](https://www.microsemi.com/product-directory/design-resources/1750-libero-soc#downloads).

## Using the reference design generation Tcl script

Expand All @@ -15,9 +15,9 @@ This repository supports Libero SoC v2022.2, which is available for download [he
To generate the standard reference design which is capable of running the majority of bare metal example applications and run Linux&reg; the following flow can be used:

1. Clone or download the repository
2. Open Libero v2022.2
2. Open Libero v2022.3
3. Open the execute script dialog (CTRL + U)
4. Execute the "MPFS_SEV_KIT_REFERENCE_DESIGN.tcl" script
4. Execute the "MPFS_VIDEO_KIT_REFERENCE_DESIGN.tcl" script
5. Configure the design if required
6. Run the Libero SoC design flow to program a device

Expand All @@ -27,8 +27,8 @@ Once the script has completed the design can be configured further if needed and

## Board configuration

Setting up the jumpers on the SEV Kit, refer to the [SEV Kit user's guide](https://mi-v-ecosystem.github.io/redirects/boards-mpfs-sev-kit-sev-kit-user-guide).
The latest Linux images for the SEV Kit are available from the releases section of the [Meta PolarFire SoC Yocto BSP](https://mi-v-ecosystem.github.io/redirects/releases-meta-polarfire-soc-yocto-bsp) repository.
Setting up the jumpers on the PolarFire SoC Video Kit, refer to the [Video Kit user's guide](https://mi-v-ecosystem.github.io/redirects/boards-mpfs-sev-kit-sev-kit-user-guide).
The latest Linux images for the PolarFire SoC Video Kit are available from the releases section of the [Meta PolarFire SoC Yocto BSP](https://mi-v-ecosystem.github.io/redirects/releases-meta-polarfire-soc-yocto-bsp) repository.

## MSS Configuration

Expand All @@ -37,7 +37,7 @@ This software tool takes user inputs and generates an MSS configuration file (.x
The XML file is used by the PolarFire SoC Configuration Generator to generate configuration header files for bare metal applications.
The MSS component file can be imported into a Libero SoC design and used in the FPGA design flow.

A saved configuration for the PolarFire SoC MSS Configurator is available in the "script_support" folder and can be opened by the PolarFire SoC MSS Configurator. These configurations will match the MSS configuration used in the design and can be used to regenerate XML and a Libero component. For argument based designs, MSS configuration files will be generated in the script_support/MSS_SEV/[configuration name] directory when a design is generated.
A saved configuration for the PolarFire SoC MSS Configurator is available in the "script_support" folder and can be opened by the PolarFire SoC MSS Configurator. These configurations will match the MSS configuration used in the design and can be used to regenerate XML and a Libero component. For argument based designs, MSS configuration files will be generated in the script_support/MSS_VIDEO_KIT/[configuration name] directory when a design is generated.

## XML

Expand Down
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