From 5d304a34cccb6d65a518629b906fcad40c3b4c7a Mon Sep 17 00:00:00 2001 From: Vattipalli Praveen Date: Thu, 2 Mar 2023 12:57:32 +0530 Subject: [PATCH] MSS configuration: update to 2022.3 and osd(On-Screen-Display) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Re-generated the MSS configuration file with the 2022.3 MSS configurator Update required Libero version in Readme and TCL script. Update TCL script with On-Screen-Display(OSD) feature. The existing design released on the GitHub uses the name sev-kit. This change replaces all such instances with the correct  name "PolarFire SoC Video kit". Signed-off-by: Vattipalli Praveen --- .gitignore | 2 +- ...tcl => MPFS_VIDEO_KIT_REFERENCE_DESIGN.tcl | 109 +- Readme.md | 16 +- ..._mss_cfg.xml => MSS_VIDEO_KIT_mss_cfg.xml} | 14 +- .../MSS_VIDEO_KIT.cfg} | 3025 +++++++++-------- .../additional_configurations/functions.tcl | 140 +- .../components/Bayer_Interpolation_C0.tcl | 22 +- script_support/components/CAM_IOD_TIP_TOP.tcl | 446 +-- .../components/CLOCKS_AND_RESETS.tcl | 222 +- script_support/components/CORERESET.tcl | 12 +- script_support/components/CORERESET_PF_C1.tcl | 12 +- script_support/components/CORERESET_PF_C2.tcl | 12 +- script_support/components/CORERESET_PF_C5.tcl | 12 +- .../components/CORERXIODBITALIGN_C1.tcl | 20 +- script_support/components/CoreAPB3_C0.tcl | 84 +- .../components/DDR_AXI4_ARBITER_PF_C0.tcl | 24 +- .../components/Gamma_Correction_C0.tcl | 18 +- .../components/H264/FIC_CONVERTER.tcl | 140 +- .../components/H264/H264_DDR_WRITE.tcl | 226 +- .../H264/H264_Iframe_Encoder_C0.tcl | 16 +- .../components/H264/RGBtoYCbCr_C0.tcl | 20 +- .../{SEVPFSOC_H264.tcl => VKPFSOC_H264.tcl} | 498 +-- .../components/H264/Video_Pipeline.tcl | 445 +-- .../components/H264/data_packer_h264.tcl | 8 +- script_support/components/H264/h264_top.tcl | 354 +- script_support/components/IMAGE_SCALER_C0.tcl | 22 +- script_support/components/IMX334_IF_TOP.tcl | 253 +- script_support/components/INIT_MONITOR.tcl | 104 +- .../components/Image_Enhancement_C0.tcl | 20 +- script_support/components/PF_CCC_C0.tcl | 496 +-- script_support/components/PF_CCC_C2.tcl | 496 +-- script_support/components/PF_CLK_DIV_C0.tcl | 18 +- .../components/PF_IOD_GENERIC_RX_C0.tcl | 86 +- script_support/components/PF_OSC_C0.tcl | 24 +- .../components/PF_XCVR_REF_CLK_C0.tcl | 24 +- script_support/components/apb3_if.tcl | 26 +- .../components/mipicsi2rxdecoderPF_C0.tcl | 24 +- script_support/components/video_fifo.tcl | 8 +- .../components/video_processing.tcl | 288 +- script_support/constraint/fp/user.pdc | 10 +- .../io/{SEV_MAC.pdc => VIDEO_KIT_MAC.pdc} | 188 +- ...{SEV_MMUART0.pdc => VIDEO_KIT_MMUART0.pdc} | 122 +- ...{SEV_MMUART1.pdc => VIDEO_KIT_MMUART1.pdc} | 122 +- script_support/constraint/io/user.pdc | 381 +-- script_support/constraint/user.sdc | 32 +- script_support/hdl/CR_OSD.v | 682 ++++ script_support/hdl/H264/apb_wrapper.vhd | 904 ++--- script_support/hdl/H264/data_packer_h264.vhd | 437 +-- script_support/hdl/ddr_write_controller_enc.v | 524 +-- script_support/hdl/frame_controls_gen.v | 362 +- script_support/hdl/intensity_average.vhd | 240 +- script_support/hdl/ram2port.vhd | 190 +- script_support/hdl_source.tcl | 19 +- 53 files changed, 6384 insertions(+), 5615 deletions(-) rename MPFS_SEV_KIT_REFERENCE_DESIGN.tcl => MPFS_VIDEO_KIT_REFERENCE_DESIGN.tcl (77%) rename XML/{MSS_SEV_mss_cfg.xml => MSS_VIDEO_KIT_mss_cfg.xml} (99%) rename script_support/{MSS_SEV/MSS_SEV.cfg => MSS_VIDEO_KIT/MSS_VIDEO_KIT.cfg} (97%) rename script_support/components/H264/{SEVPFSOC_H264.tcl => VKPFSOC_H264.tcl} (98%) rename script_support/constraint/io/{SEV_MAC.pdc => VIDEO_KIT_MAC.pdc} (91%) rename script_support/constraint/io/{SEV_MMUART0.pdc => VIDEO_KIT_MMUART0.pdc} (87%) rename script_support/constraint/io/{SEV_MMUART1.pdc => VIDEO_KIT_MMUART1.pdc} (87%) create mode 100644 script_support/hdl/CR_OSD.v diff --git a/.gitignore b/.gitignore index dc06569..4a7fd91 100644 --- a/.gitignore +++ b/.gitignore @@ -1,4 +1,4 @@ *.job *.digest *.patch -script_support/MSS_SEV/* +script_support/MSS_VIDEO_KIT/* diff --git a/MPFS_SEV_KIT_REFERENCE_DESIGN.tcl b/MPFS_VIDEO_KIT_REFERENCE_DESIGN.tcl similarity index 77% rename from MPFS_SEV_KIT_REFERENCE_DESIGN.tcl rename to MPFS_VIDEO_KIT_REFERENCE_DESIGN.tcl index ebee8e2..534fd94 100644 --- a/MPFS_SEV_KIT_REFERENCE_DESIGN.tcl +++ b/MPFS_VIDEO_KIT_REFERENCE_DESIGN.tcl @@ -1,13 +1,12 @@ # -# // PFSoC SEV Kit H264 I frame Encoder demo Libero design +# // PFSoC VIDEO Kit H264 I frame Encoder demo Libero design # # // Check Libero version and path lenth to verify project can be created # - -if {[string compare [string range [get_libero_version] 0 end-3] "2022.2.0"]==0} { - puts "Libero v2022.2 detected." +if {[string compare [string range [get_libero_version] 0 end-4] "2022.3"]==0} { + puts "Libero v2022.3 detected." } else { - error "Incorrect Libero version. Please use Libero v2022.2 to run these scripts." + error "Incorrect Libero version. Please use Libero v2022.3 to run these scripts." } if { [lindex $tcl_platform(os) 0] == "Windows" } { @@ -48,8 +47,8 @@ set mss_config_loc "$install_loc/bin64/pfsoc_mss" set local_dir [pwd] set src_path ./script_support set constraint_path ./script_support/constraint -set release_tag "2022.2" -set project_name "SEVPFSOC_H264" +set release_tag "2022.3" +set project_name "VKPFSOC_H264" set project_dir "$local_dir/$project_name" source ./script_support/additional_configurations/functions.tcl @@ -68,51 +67,51 @@ new_project \ -linked_files_root_dir_env {} \ -hdl {VERILOG} \ -family {PolarFireSoC} \ - -die {MPFS250T_ES} \ + -die {MPFS250TS} \ -package {FCG1152} \ -speed {-1} \ -die_voltage {1.0} \ - -part_range {EXT} \ + -part_range {IND} \ -adv_options {IO_DEFT_STD:LVCMOS 1.8V} \ -adv_options {RESTRICTPROBEPINS:1} \ -adv_options {RESTRICTSPIPINS:0} \ -adv_options {SYSTEM_CONTROLLER_SUSPEND_MODE:0} \ - -adv_options {TEMPR:EXT} \ - -adv_options {VCCI_1.2_VOLTR:EXT} \ - -adv_options {VCCI_1.5_VOLTR:EXT} \ - -adv_options {VCCI_1.8_VOLTR:EXT} \ - -adv_options {VCCI_2.5_VOLTR:EXT} \ - -adv_options {VCCI_3.3_VOLTR:EXT} \ - -adv_options {VOLTR:EXT} + -adv_options {TEMPR:IND} \ + -adv_options {VCCI_1.2_VOLTR:IND} \ + -adv_options {VCCI_1.5_VOLTR:IND} \ + -adv_options {VCCI_1.8_VOLTR:IND} \ + -adv_options {VCCI_2.5_VOLTR:IND} \ + -adv_options {VCCI_3.3_VOLTR:IND} \ + -adv_options {VOLTR:IND} # # // Download required cores # -download_core -vlnv {Microsemi:SolutionCore:Bayer_Interpolation:4.2.0} -location {www.microchip-ip.com/repositories/DirectCore} +download_core -vlnv {Microsemi:SolutionCore:Bayer_Interpolation:4.4.0} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Actel:DirectCore:CORERESET_PF:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Actel:DirectCore:CORERXIODBITALIGN:2.2.100} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Microsemi:SolutionCore:Gamma_Correction:4.2.0} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Microsemi:SolutionCore:Image_Enhancement:4.3.0} -location {www.microchip-ip.com/repositories/DirectCore} -download_core -vlnv {Microsemi:SolutionCore:IMAGE_SCALER:4.0.0} -location {www.microchip-ip.com/repositories/DirectCore} +download_core -vlnv {Microsemi:SolutionCore:IMAGE_SCALER:4.1.0} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Microsemi:SgCore:PFSOC_INIT_MONITOR:1.0.304} -location {www.microchip-ip.com/repositories/SgCore} -download_core -vlnv {Microsemi:SolutionCore:mipicsi2rxdecoderPF:4.4.0} -location {www.microchip-ip.com/repositories/DirectCore} -download_core -vlnv {Actel:SgCore:PF_CCC:2.2.214} -location {www.microchip-ip.com/repositories/SgCore} +download_core -vlnv {Microchip:SolutionCore:mipicsi2rxdecoderPF:4.7.0} -location {www.microchip-ip.com/repositories/DirectCore} +download_core -vlnv {Actel:SgCore:PF_CCC:2.2.220} -location {www.microchip-ip.com/repositories/SgCore} download_core -vlnv {Actel:SgCore:PF_CLK_DIV:1.0.103} -location {www.microchip-ip.com/repositories/SgCore} -download_core -vlnv {Actel:SystemBuilder:PF_IOD_GENERIC_RX:2.1.109} -location {www.microchip-ip.com/repositories/SgCore} +download_core -vlnv {Actel:SystemBuilder:PF_IOD_GENERIC_RX:2.1.110} -location {www.microchip-ip.com/repositories/SgCore} download_core -vlnv {Actel:SgCore:PF_OSC:1.0.102} -location {www.microchip-ip.com/repositories/SgCore} download_core -vlnv {Microsemi:SolutionCore:RGBtoYCbCr:4.4.0} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Actel:SgCore:PF_XCVR_REF_CLK:1.0.103} -location {www.microchip-ip.com/repositories/SgCore} download_core -vlnv {Microsemi:SolutionCore:DDR_AXI4_ARBITER_PF:2.1.0} -location {www.microchip-ip.com/repositories/DirectCore} -download_core -vlnv {Microchip:SolutionCore:H264_Iframe_Encoder:1.3.0} -location {www.microchip-ip.com/repositories/DirectCore} +download_core -vlnv {Microchip:SolutionCore:H264_Iframe_Encoder:1.4.0} -location {www.microchip-ip.com/repositories/DirectCore} # # // Generate base design # -exec $mss_config_loc -GENERATE -CONFIGURATION_FILE:$src_path/MSS_SEV/MSS_SEV.cfg -OUTPUT_DIR:${src_path}/MSS_SEV -import_mss_component -file "$src_path/MSS_SEV/MSS_SEV.cxz" +exec $mss_config_loc -GENERATE -CONFIGURATION_FILE:$src_path/MSS_VIDEO_KIT/MSS_VIDEO_KIT.cfg -OUTPUT_DIR:${src_path}/MSS_VIDEO_KIT +import_mss_component -file "$src_path/MSS_VIDEO_KIT/MSS_VIDEO_KIT.cxz" #This Tcl file sources other Tcl files to build the design(on which recursive export is run) in a bottom-up fashion @@ -122,7 +121,7 @@ source ${src_path}/hdl_source.tcl build_design_hierarchy #Sourcing the Tcl files in which HDL+ core definitions are created for HDL modules -source ${src_path}/components/video_fifo.tcl +source ${src_path}/components/video_fifo.tcl source ${src_path}/components/apb3_if.tcl source ${src_path}/components/H264/data_packer_h264.tcl build_design_hierarchy @@ -157,9 +156,9 @@ source ${src_path}/components/H264/H264_DDR_WRITE.tcl source ${src_path}/components/H264/h264_top.tcl source ${src_path}/components/video_processing.tcl source ${src_path}/components/H264/Video_Pipeline.tcl -source ${src_path}/components/H264/SEVPFSOC_H264.tcl +source ${src_path}/components/H264/VKPFSOC_H264.tcl build_design_hierarchy -set_root -module {SEVPFSOC_TOP::work} +set_root -module {VKPFSOC_TOP::work} # # // Derive timing constraints # @@ -170,9 +169,9 @@ derive_constraints_sdc import_files \ -convert_EDN_to_HDL 0 \ - -io_pdc "${constraint_path}/io/SEV_MAC.pdc" \ - -io_pdc "${constraint_path}/io/SEV_MMUART0.pdc" \ - -io_pdc "${constraint_path}/io/SEV_MMUART1.pdc" \ + -io_pdc "${constraint_path}/io/VIDEO_KIT_MAC.pdc" \ + -io_pdc "${constraint_path}/io/VIDEO_KIT_MMUART0.pdc" \ + -io_pdc "${constraint_path}/io/VIDEO_KIT_MMUART1.pdc" \ -io_pdc "${constraint_path}/io/user.pdc" \ set_as_target -type {io_pdc} -file "${constraint_path}/io/user.pdc" @@ -189,43 +188,43 @@ import_files -convert_EDN_to_HDL 0 -fp_pdc "${constraint_path}/fp/user.pdc" import_files \ -convert_EDN_to_HDL 0 \ -sdc "${constraint_path}/user.sdc" -set_as_target -type {sdc} -file "${constraint_path}/user.sdc" +set_as_target -type {sdc} -file "${constraint_path}/user.sdc" # # // Associate imported constraints with the design flow # organize_tool_files -tool {SYNTHESIZE} \ - -file "${project_dir}/constraint/SEVPFSOC_TOP_derived_constraints.sdc" \ - -module {SEVPFSOC_TOP::work} \ - -input_type {constraint} - + -file "${project_dir}/constraint/VKPFSOC_TOP_derived_constraints.sdc" \ + -module {VKPFSOC_TOP::work} \ + -input_type {constraint} + organize_tool_files -tool {PLACEROUTE} \ - -file "${project_dir}/constraint/io/SEV_MAC.pdc" \ - -file "${project_dir}/constraint/io/SEV_MMUART0.pdc" \ - -file "${project_dir}/constraint/io/SEV_MMUART1.pdc" \ + -file "${project_dir}/constraint/io/VIDEO_KIT_MAC.pdc" \ + -file "${project_dir}/constraint/io/VIDEO_KIT_MMUART0.pdc" \ + -file "${project_dir}/constraint/io/VIDEO_KIT_MMUART1.pdc" \ -file "${project_dir}/constraint/io/user.pdc" \ - -file "${project_dir}/constraint/SEVPFSOC_TOP_derived_constraints.sdc" \ + -file "${project_dir}/constraint/VKPFSOC_TOP_derived_constraints.sdc" \ -file "${project_dir}/constraint/user.sdc" \ -file "${project_dir}/constraint/fp/user.pdc" \ - -module {SEVPFSOC_TOP::work} \ + -module {VKPFSOC_TOP::work} \ -input_type {constraint} set_as_target -type {io_pdc} -file "${project_dir}/constraint/io/user.pdc" save_project organize_tool_files -tool {VERIFYTIMING} \ - -file "${project_dir}/constraint/SEVPFSOC_TOP_derived_constraints.sdc" \ + -file "${project_dir}/constraint/VKPFSOC_TOP_derived_constraints.sdc" \ -file "${project_dir}/constraint/user.sdc" \ - -module {SEVPFSOC_TOP::work} \ + -module {VKPFSOC_TOP::work} \ -input_type {constraint} # -# // Run the design flow and add eNVM clients +# // Run the design flow and add eNVM clients # if {[info exists SYNTHESIZE]} { run_tool -name {SYNTHESIZE} -} -configure_tool -name {VERIFYTIMING} -params {CONSTRAINTS_COVERAGE:1} -params {FORMAT:XML} -params {MAX_EXPANDED_PATHS_TIMING:1} -params {MAX_EXPANDED_PATHS_VIOLATION:0} -params {MAX_PARALLEL_PATHS_TIMING:1} -params {MAX_PARALLEL_PATHS_VIOLATION:1} -params {MAX_PATHS_INTERACTIVE_REPORT:1000} -params {MAX_PATHS_TIMING:5} -params {MAX_PATHS_VIOLATION:20} -params {MAX_TIMING_FAST_HV_LT:1} -params {MAX_TIMING_MULTI_CORNER:1} -params {MAX_TIMING_SLOW_LV_HT:1} -params {MAX_TIMING_SLOW_LV_LT:1} -params {MAX_TIMING_VIOLATIONS_FAST_HV_LT:1} -params {MAX_TIMING_VIOLATIONS_MULTI_CORNER:1} -params {MAX_TIMING_VIOLATIONS_SLOW_LV_HT:1} -params {MAX_TIMING_VIOLATIONS_SLOW_LV_LT:1} -params {MIN_TIMING_FAST_HV_LT:1} -params {MIN_TIMING_MULTI_CORNER:1} -params {MIN_TIMING_SLOW_LV_HT:1} -params {MIN_TIMING_SLOW_LV_LT:1} -params {MIN_TIMING_VIOLATIONS_FAST_HV_LT:1} -params {MIN_TIMING_VIOLATIONS_MULTI_CORNER:1} -params {MIN_TIMING_VIOLATIONS_SLOW_LV_HT:1} -params {MIN_TIMING_VIOLATIONS_SLOW_LV_LT:1} -params {SLACK_THRESHOLD_VIOLATION:0.0} -params {SMART_INTERACTIVE:1} -configure_tool -name {PLACEROUTE} -params {DELAY_ANALYSIS:MAX} -params {EFFORT_LEVEL:true} -params {GB_DEMOTION:true} -params {INCRPLACEANDROUTE:false} -params {IOREG_COMBINING:false} -params {MULTI_PASS_CRITERIA:VIOLATIONS} -params {MULTI_PASS_LAYOUT:false} -params {NUM_MULTI_PASSES:5} -params {PDPR:false} -params {RANDOM_SEED:0} -params {REPAIR_MIN_DELAY:false} -params {REPLICATION:true} -params {SLACK_CRITERIA:WORST_SLACK} -params {SPECIFIC_CLOCK:} -params {START_SEED_INDEX:1} -params {STOP_ON_FIRST_PASS:false} -params {TDPR:true} +} +configure_tool -name {VERIFYTIMING} -params {CONSTRAINTS_COVERAGE:1} -params {FORMAT:XML} -params {MAX_EXPANDED_PATHS_TIMING:1} -params {MAX_EXPANDED_PATHS_VIOLATION:0} -params {MAX_PARALLEL_PATHS_TIMING:1} -params {MAX_PARALLEL_PATHS_VIOLATION:1} -params {MAX_PATHS_INTERACTIVE_REPORT:1000} -params {MAX_PATHS_TIMING:5} -params {MAX_PATHS_VIOLATION:20} -params {MAX_TIMING_FAST_HV_LT:1} -params {MAX_TIMING_MULTI_CORNER:1} -params {MAX_TIMING_SLOW_LV_HT:1} -params {MAX_TIMING_SLOW_LV_LT:1} -params {MAX_TIMING_VIOLATIONS_FAST_HV_LT:1} -params {MAX_TIMING_VIOLATIONS_MULTI_CORNER:1} -params {MAX_TIMING_VIOLATIONS_SLOW_LV_HT:1} -params {MAX_TIMING_VIOLATIONS_SLOW_LV_LT:1} -params {MIN_TIMING_FAST_HV_LT:1} -params {MIN_TIMING_MULTI_CORNER:1} -params {MIN_TIMING_SLOW_LV_HT:1} -params {MIN_TIMING_SLOW_LV_LT:1} -params {MIN_TIMING_VIOLATIONS_FAST_HV_LT:1} -params {MIN_TIMING_VIOLATIONS_MULTI_CORNER:1} -params {MIN_TIMING_VIOLATIONS_SLOW_LV_HT:1} -params {MIN_TIMING_VIOLATIONS_SLOW_LV_LT:1} -params {SLACK_THRESHOLD_VIOLATION:0.0} -params {SMART_INTERACTIVE:1} +configure_tool -name {PLACEROUTE} -params {DELAY_ANALYSIS:MAX} -params {EFFORT_LEVEL:true} -params {GB_DEMOTION:true} -params {INCRPLACEANDROUTE:false} -params {IOREG_COMBINING:false} -params {MULTI_PASS_CRITERIA:VIOLATIONS} -params {MULTI_PASS_LAYOUT:false} -params {NUM_MULTI_PASSES:5} -params {PDPR:false} -params {RANDOM_SEED:0} -params {REPAIR_MIN_DELAY:false} -params {REPLICATION:true} -params {SLACK_CRITERIA:WORST_SLACK} -params {SPECIFIC_CLOCK:} -params {START_SEED_INDEX:1} -params {STOP_ON_FIRST_PASS:false} -params {TDPR:true} if {[info exists PLACEROUTE]} { run_tool -name {PLACEROUTE} @@ -234,22 +233,22 @@ if {[info exists PLACEROUTE]} { } if {[info exists HSS_UPDATE]} { - if !{[file exists "./script_support/hss-envm-wrapper.mpfs-sev-kit.hex"]} { - if {[catch {exec wget https://github.com/polarfire-soc/hart-software-services/releases/latest/download/hss-envm-wrapper.mpfs-sev-kit.hex -P ./script_support/} issue]} { + if !{[file exists "./script_support/hss-envm-wrapper.mpfs-video-kit.hex"]} { + if {[catch {exec wget https://github.com/polarfire-soc/hart-software-services/releases/latest/download/hss-envm-wrapper.mpfs-video-kit.hex -P ./script_support/} issue]} { } } - - create_eNVM_config "$local_dir/script_support/MSS_SEV/ENVM.cfg" "$local_dir/script_support/hss-envm-wrapper.mpfs-sev-kit.hex" + + create_eNVM_config "$local_dir/script_support/MSS_VIDEO_KIT/ENVM.cfg" "$local_dir/script_support/hss-envm-wrapper.mpfs-video-kit.hex" run_tool -name {GENERATEPROGRAMMINGDATA} - configure_envm -cfg_file {script_support/MSS_SEV/ENVM.cfg} + configure_envm -cfg_file {script_support/MSS_VIDEO_KIT/ENVM.cfg} } if {[info exists GENERATE_PROGRAMMING_DATA]} { - run_tool -name {GENERATEPROGRAMMINGDATA} + run_tool -name {GENERATEPROGRAMMINGDATA} } elseif {[info exists PROGRAM]} { - run_tool -name {GENERATEPROGRAMMINGDATA} + run_tool -name {GENERATEPROGRAMMINGDATA} run_tool -name {PROGRAMDEVICE} -} elseif {[info exists EXPORT_FPE]} { +} elseif {[info exists EXPORT_FPE]} { if {[info exists HSS_UPDATE]} { if {$EXPORT_FPE == 1} { export_fpe_job $project_name $local_dir "ENVM FABRIC_SNVM" @@ -265,4 +264,4 @@ if {[info exists GENERATE_PROGRAMMING_DATA]} { } } -save_project \ No newline at end of file +save_project diff --git a/Readme.md b/Readme.md index 7d675b2..d3de077 100644 --- a/Readme.md +++ b/Readme.md @@ -1,12 +1,12 @@ -# PolarFire® SoC Sev Kit Reference Design Generation Tcl Scripts - Libero® SoC v2022.2 +# PolarFire® SoC Video Kit Reference Design Generation Tcl Scripts - Libero® SoC v2022.3 ## Description -This repository can be used to generate a reference design for the PolarFire SoC Sev Kit. This reference design will have the same or extended functionality compared to the pre-programmed FPGA design on the Sev Kit. +This repository can be used to generate a reference design for the PolarFire SoC Video Kit. This reference design will have the same or extended functionality compared to the pre-programmed FPGA design on the Video Kit. A Libero SoC Tcl script is provided to generate the reference design using Libero SoC along with device specific I/O constraints. -This repository supports Libero SoC v2022.2, which is available for download [here](https://www.microsemi.com/product-directory/design-resources/1750-libero-soc#downloads). +This repository supports Libero SoC v2022.3, which is available for download [here](https://www.microsemi.com/product-directory/design-resources/1750-libero-soc#downloads). ## Using the reference design generation Tcl script @@ -15,9 +15,9 @@ This repository supports Libero SoC v2022.2, which is available for download [he To generate the standard reference design which is capable of running the majority of bare metal example applications and run Linux® the following flow can be used: 1. Clone or download the repository -2. Open Libero v2022.2 +2. Open Libero v2022.3 3. Open the execute script dialog (CTRL + U) -4. Execute the "MPFS_SEV_KIT_REFERENCE_DESIGN.tcl" script +4. Execute the "MPFS_VIDEO_KIT_REFERENCE_DESIGN.tcl" script 5. Configure the design if required 6. Run the Libero SoC design flow to program a device @@ -27,8 +27,8 @@ Once the script has completed the design can be configured further if needed and ## Board configuration -Setting up the jumpers on the SEV Kit, refer to the [SEV Kit user's guide](https://mi-v-ecosystem.github.io/redirects/boards-mpfs-sev-kit-sev-kit-user-guide). -The latest Linux images for the SEV Kit are available from the releases section of the [Meta PolarFire SoC Yocto BSP](https://mi-v-ecosystem.github.io/redirects/releases-meta-polarfire-soc-yocto-bsp) repository. +Setting up the jumpers on the PolarFire SoC Video Kit, refer to the [Video Kit user's guide](https://mi-v-ecosystem.github.io/redirects/boards-mpfs-sev-kit-sev-kit-user-guide). +The latest Linux images for the PolarFire SoC Video Kit are available from the releases section of the [Meta PolarFire SoC Yocto BSP](https://mi-v-ecosystem.github.io/redirects/releases-meta-polarfire-soc-yocto-bsp) repository. ## MSS Configuration @@ -37,7 +37,7 @@ This software tool takes user inputs and generates an MSS configuration file (.x The XML file is used by the PolarFire SoC Configuration Generator to generate configuration header files for bare metal applications. The MSS component file can be imported into a Libero SoC design and used in the FPGA design flow. -A saved configuration for the PolarFire SoC MSS Configurator is available in the "script_support" folder and can be opened by the PolarFire SoC MSS Configurator. These configurations will match the MSS configuration used in the design and can be used to regenerate XML and a Libero component. For argument based designs, MSS configuration files will be generated in the script_support/MSS_SEV/[configuration name] directory when a design is generated. +A saved configuration for the PolarFire SoC MSS Configurator is available in the "script_support" folder and can be opened by the PolarFire SoC MSS Configurator. These configurations will match the MSS configuration used in the design and can be used to regenerate XML and a Libero component. For argument based designs, MSS configuration files will be generated in the script_support/MSS_VIDEO_KIT/[configuration name] directory when a design is generated. ## XML diff --git a/XML/MSS_SEV_mss_cfg.xml b/XML/MSS_VIDEO_KIT_mss_cfg.xml similarity index 99% rename from XML/MSS_SEV_mss_cfg.xml rename to XML/MSS_VIDEO_KIT_mss_cfg.xml index c5fb5cb..64243b6 100644 --- a/XML/MSS_SEV_mss_cfg.xml +++ b/XML/MSS_VIDEO_KIT_mss_cfg.xml @@ -1,10 +1,10 @@ - 2022.2 - MSS_SEV - MPFS250T_ES + 2022.3 + MSS_VIDEO_KIT + MPFS250TS FCG1152 - 08-25-2022_14:48:05 + 03-02-2023_12:55:15 0.6.5 @@ -1938,7 +1938,7 @@ 0x0 - 0x6 + 0x3 0x6 @@ -2289,7 +2289,7 @@ 0x1 - 0x1 + 0x6 @@ -3136,7 +3136,7 @@ 0x0 - 0x1 + 0x0 0x2 diff --git a/script_support/MSS_SEV/MSS_SEV.cfg b/script_support/MSS_VIDEO_KIT/MSS_VIDEO_KIT.cfg similarity index 97% rename from script_support/MSS_SEV/MSS_SEV.cfg rename to script_support/MSS_VIDEO_KIT/MSS_VIDEO_KIT.cfg index fa72df0..d9c4a70 100644 --- a/script_support/MSS_SEV/MSS_SEV.cfg +++ b/script_support/MSS_VIDEO_KIT/MSS_VIDEO_KIT.cfg @@ -1,1510 +1,1515 @@ -ALT_MSSIO_0_ATP_EN false -ALT_MSSIO_0_CLAMP_DIODE false -ALT_MSSIO_0_LPMD_IBUF false -ALT_MSSIO_0_LPMD_OBUF false -ALT_MSSIO_0_LP_PERSIST false -ALT_MSSIO_0_MD_IBUF true -ALT_MSSIO_0_OUT_DRIVE 8 -ALT_MSSIO_0_RES_PULL UP -ALT_MSSIO_0_SCHMITT_TRIGGER false -ALT_MSSIO_10_ATP_EN false -ALT_MSSIO_10_CLAMP_DIODE false -ALT_MSSIO_10_LPMD_IBUF false -ALT_MSSIO_10_LPMD_OBUF false -ALT_MSSIO_10_LP_PERSIST false -ALT_MSSIO_10_MD_IBUF true -ALT_MSSIO_10_OUT_DRIVE 8 -ALT_MSSIO_10_RES_PULL UP -ALT_MSSIO_10_SCHMITT_TRIGGER false -ALT_MSSIO_11_ATP_EN false -ALT_MSSIO_11_CLAMP_DIODE false -ALT_MSSIO_11_LPMD_IBUF false -ALT_MSSIO_11_LPMD_OBUF false -ALT_MSSIO_11_LP_PERSIST false -ALT_MSSIO_11_MD_IBUF true -ALT_MSSIO_11_OUT_DRIVE 8 -ALT_MSSIO_11_RES_PULL UP -ALT_MSSIO_11_SCHMITT_TRIGGER false -ALT_MSSIO_12_ATP_EN false -ALT_MSSIO_12_CLAMP_DIODE false -ALT_MSSIO_12_LPMD_IBUF false -ALT_MSSIO_12_LPMD_OBUF false -ALT_MSSIO_12_LP_PERSIST false -ALT_MSSIO_12_MD_IBUF true -ALT_MSSIO_12_OUT_DRIVE 8 -ALT_MSSIO_12_RES_PULL UP -ALT_MSSIO_12_SCHMITT_TRIGGER false -ALT_MSSIO_13_ATP_EN false -ALT_MSSIO_13_CLAMP_DIODE false -ALT_MSSIO_13_LPMD_IBUF false -ALT_MSSIO_13_LPMD_OBUF false -ALT_MSSIO_13_LP_PERSIST false -ALT_MSSIO_13_MD_IBUF true -ALT_MSSIO_13_OUT_DRIVE 8 -ALT_MSSIO_13_RES_PULL UP -ALT_MSSIO_13_SCHMITT_TRIGGER false -ALT_MSSIO_14_ATP_EN false -ALT_MSSIO_14_CLAMP_DIODE false -ALT_MSSIO_14_LPMD_IBUF false -ALT_MSSIO_14_LPMD_OBUF false -ALT_MSSIO_14_LP_PERSIST false -ALT_MSSIO_14_MD_IBUF true -ALT_MSSIO_14_OUT_DRIVE 8 -ALT_MSSIO_14_RES_PULL UP -ALT_MSSIO_14_SCHMITT_TRIGGER false -ALT_MSSIO_15_ATP_EN false -ALT_MSSIO_15_CLAMP_DIODE false -ALT_MSSIO_15_LPMD_IBUF false -ALT_MSSIO_15_LPMD_OBUF false -ALT_MSSIO_15_LP_PERSIST false -ALT_MSSIO_15_MD_IBUF true -ALT_MSSIO_15_OUT_DRIVE 8 -ALT_MSSIO_15_RES_PULL UP -ALT_MSSIO_15_SCHMITT_TRIGGER false -ALT_MSSIO_16_ATP_EN false -ALT_MSSIO_16_CLAMP_DIODE false -ALT_MSSIO_16_LPMD_IBUF false -ALT_MSSIO_16_LPMD_OBUF false -ALT_MSSIO_16_LP_PERSIST false -ALT_MSSIO_16_MD_IBUF true -ALT_MSSIO_16_OUT_DRIVE 8 -ALT_MSSIO_16_RES_PULL UP -ALT_MSSIO_16_SCHMITT_TRIGGER false -ALT_MSSIO_17_ATP_EN false -ALT_MSSIO_17_CLAMP_DIODE false -ALT_MSSIO_17_LPMD_IBUF false -ALT_MSSIO_17_LPMD_OBUF false -ALT_MSSIO_17_LP_PERSIST false -ALT_MSSIO_17_MD_IBUF true -ALT_MSSIO_17_OUT_DRIVE 8 -ALT_MSSIO_17_RES_PULL UP -ALT_MSSIO_17_SCHMITT_TRIGGER false -ALT_MSSIO_18_ATP_EN false -ALT_MSSIO_18_CLAMP_DIODE false -ALT_MSSIO_18_LPMD_IBUF false -ALT_MSSIO_18_LPMD_OBUF false -ALT_MSSIO_18_LP_PERSIST false -ALT_MSSIO_18_MD_IBUF true -ALT_MSSIO_18_OUT_DRIVE 8 -ALT_MSSIO_18_RES_PULL UP -ALT_MSSIO_18_SCHMITT_TRIGGER false -ALT_MSSIO_19_ATP_EN false -ALT_MSSIO_19_CLAMP_DIODE false -ALT_MSSIO_19_LPMD_IBUF false -ALT_MSSIO_19_LPMD_OBUF false -ALT_MSSIO_19_LP_PERSIST false -ALT_MSSIO_19_MD_IBUF true -ALT_MSSIO_19_OUT_DRIVE 8 -ALT_MSSIO_19_RES_PULL UP -ALT_MSSIO_19_SCHMITT_TRIGGER false -ALT_MSSIO_1_ATP_EN false -ALT_MSSIO_1_CLAMP_DIODE false -ALT_MSSIO_1_LPMD_IBUF false -ALT_MSSIO_1_LPMD_OBUF false -ALT_MSSIO_1_LP_PERSIST false -ALT_MSSIO_1_MD_IBUF true -ALT_MSSIO_1_OUT_DRIVE 8 -ALT_MSSIO_1_RES_PULL UP -ALT_MSSIO_1_SCHMITT_TRIGGER false -ALT_MSSIO_20_ATP_EN false -ALT_MSSIO_20_CLAMP_DIODE false -ALT_MSSIO_20_LPMD_IBUF false -ALT_MSSIO_20_LPMD_OBUF false -ALT_MSSIO_20_LP_PERSIST false -ALT_MSSIO_20_MD_IBUF true -ALT_MSSIO_20_OUT_DRIVE 8 -ALT_MSSIO_20_RES_PULL UP -ALT_MSSIO_20_SCHMITT_TRIGGER false -ALT_MSSIO_21_ATP_EN false -ALT_MSSIO_21_CLAMP_DIODE false -ALT_MSSIO_21_LPMD_IBUF false -ALT_MSSIO_21_LPMD_OBUF false -ALT_MSSIO_21_LP_PERSIST false -ALT_MSSIO_21_MD_IBUF true -ALT_MSSIO_21_OUT_DRIVE 8 -ALT_MSSIO_21_RES_PULL UP -ALT_MSSIO_21_SCHMITT_TRIGGER false -ALT_MSSIO_22_ATP_EN false -ALT_MSSIO_22_CLAMP_DIODE false -ALT_MSSIO_22_LPMD_IBUF false -ALT_MSSIO_22_LPMD_OBUF false -ALT_MSSIO_22_LP_PERSIST false -ALT_MSSIO_22_MD_IBUF true -ALT_MSSIO_22_OUT_DRIVE 8 -ALT_MSSIO_22_RES_PULL UP -ALT_MSSIO_22_SCHMITT_TRIGGER false -ALT_MSSIO_23_ATP_EN false -ALT_MSSIO_23_CLAMP_DIODE false -ALT_MSSIO_23_LPMD_IBUF false -ALT_MSSIO_23_LPMD_OBUF false -ALT_MSSIO_23_LP_PERSIST false -ALT_MSSIO_23_MD_IBUF true -ALT_MSSIO_23_OUT_DRIVE 8 -ALT_MSSIO_23_RES_PULL UP -ALT_MSSIO_23_SCHMITT_TRIGGER false -ALT_MSSIO_24_ATP_EN false -ALT_MSSIO_24_CLAMP_DIODE false -ALT_MSSIO_24_LPMD_IBUF false -ALT_MSSIO_24_LPMD_OBUF false -ALT_MSSIO_24_LP_PERSIST false -ALT_MSSIO_24_MD_IBUF true -ALT_MSSIO_24_OUT_DRIVE 8 -ALT_MSSIO_24_RES_PULL UP -ALT_MSSIO_24_SCHMITT_TRIGGER false -ALT_MSSIO_25_ATP_EN false -ALT_MSSIO_25_CLAMP_DIODE false -ALT_MSSIO_25_LPMD_IBUF false -ALT_MSSIO_25_LPMD_OBUF false -ALT_MSSIO_25_LP_PERSIST false -ALT_MSSIO_25_MD_IBUF true -ALT_MSSIO_25_OUT_DRIVE 8 -ALT_MSSIO_25_RES_PULL UP -ALT_MSSIO_25_SCHMITT_TRIGGER false -ALT_MSSIO_26_ATP_EN false -ALT_MSSIO_26_CLAMP_DIODE false -ALT_MSSIO_26_LPMD_IBUF false -ALT_MSSIO_26_LPMD_OBUF false -ALT_MSSIO_26_LP_PERSIST false -ALT_MSSIO_26_MD_IBUF true -ALT_MSSIO_26_OUT_DRIVE 8 -ALT_MSSIO_26_RES_PULL UP -ALT_MSSIO_26_SCHMITT_TRIGGER false -ALT_MSSIO_27_ATP_EN false -ALT_MSSIO_27_CLAMP_DIODE false -ALT_MSSIO_27_LPMD_IBUF false -ALT_MSSIO_27_LPMD_OBUF false -ALT_MSSIO_27_LP_PERSIST false -ALT_MSSIO_27_MD_IBUF true -ALT_MSSIO_27_OUT_DRIVE 8 -ALT_MSSIO_27_RES_PULL UP -ALT_MSSIO_27_SCHMITT_TRIGGER false -ALT_MSSIO_28_ATP_EN false -ALT_MSSIO_28_CLAMP_DIODE false -ALT_MSSIO_28_LPMD_IBUF false -ALT_MSSIO_28_LPMD_OBUF false -ALT_MSSIO_28_LP_PERSIST false -ALT_MSSIO_28_MD_IBUF true -ALT_MSSIO_28_OUT_DRIVE 8 -ALT_MSSIO_28_RES_PULL UP -ALT_MSSIO_28_SCHMITT_TRIGGER false -ALT_MSSIO_29_ATP_EN false -ALT_MSSIO_29_CLAMP_DIODE false -ALT_MSSIO_29_LPMD_IBUF false -ALT_MSSIO_29_LPMD_OBUF false -ALT_MSSIO_29_LP_PERSIST false -ALT_MSSIO_29_MD_IBUF true -ALT_MSSIO_29_OUT_DRIVE 8 -ALT_MSSIO_29_RES_PULL UP -ALT_MSSIO_29_SCHMITT_TRIGGER false -ALT_MSSIO_2_ATP_EN false -ALT_MSSIO_2_CLAMP_DIODE false -ALT_MSSIO_2_LPMD_IBUF false -ALT_MSSIO_2_LPMD_OBUF false -ALT_MSSIO_2_LP_PERSIST false -ALT_MSSIO_2_MD_IBUF true -ALT_MSSIO_2_OUT_DRIVE 8 -ALT_MSSIO_2_RES_PULL UP -ALT_MSSIO_2_SCHMITT_TRIGGER false -ALT_MSSIO_30_ATP_EN false -ALT_MSSIO_30_CLAMP_DIODE false -ALT_MSSIO_30_LPMD_IBUF false -ALT_MSSIO_30_LPMD_OBUF false -ALT_MSSIO_30_LP_PERSIST false -ALT_MSSIO_30_MD_IBUF true -ALT_MSSIO_30_OUT_DRIVE 8 -ALT_MSSIO_30_RES_PULL UP -ALT_MSSIO_30_SCHMITT_TRIGGER false -ALT_MSSIO_31_ATP_EN false -ALT_MSSIO_31_CLAMP_DIODE false -ALT_MSSIO_31_LPMD_IBUF false -ALT_MSSIO_31_LPMD_OBUF false -ALT_MSSIO_31_LP_PERSIST false -ALT_MSSIO_31_MD_IBUF true -ALT_MSSIO_31_OUT_DRIVE 8 -ALT_MSSIO_31_RES_PULL UP -ALT_MSSIO_31_SCHMITT_TRIGGER false -ALT_MSSIO_32_ATP_EN false -ALT_MSSIO_32_CLAMP_DIODE false -ALT_MSSIO_32_LPMD_IBUF false -ALT_MSSIO_32_LPMD_OBUF false -ALT_MSSIO_32_LP_PERSIST false -ALT_MSSIO_32_MD_IBUF true -ALT_MSSIO_32_OUT_DRIVE 8 -ALT_MSSIO_32_RES_PULL UP -ALT_MSSIO_32_SCHMITT_TRIGGER false -ALT_MSSIO_33_ATP_EN false -ALT_MSSIO_33_CLAMP_DIODE false -ALT_MSSIO_33_LPMD_IBUF false -ALT_MSSIO_33_LPMD_OBUF false -ALT_MSSIO_33_LP_PERSIST false -ALT_MSSIO_33_MD_IBUF true -ALT_MSSIO_33_OUT_DRIVE 8 -ALT_MSSIO_33_RES_PULL UP -ALT_MSSIO_33_SCHMITT_TRIGGER false -ALT_MSSIO_34_ATP_EN false -ALT_MSSIO_34_CLAMP_DIODE false -ALT_MSSIO_34_LPMD_IBUF false -ALT_MSSIO_34_LPMD_OBUF false -ALT_MSSIO_34_LP_PERSIST false -ALT_MSSIO_34_MD_IBUF true -ALT_MSSIO_34_OUT_DRIVE 8 -ALT_MSSIO_34_RES_PULL UP -ALT_MSSIO_34_SCHMITT_TRIGGER false -ALT_MSSIO_35_ATP_EN false -ALT_MSSIO_35_CLAMP_DIODE false -ALT_MSSIO_35_LPMD_IBUF false -ALT_MSSIO_35_LPMD_OBUF false -ALT_MSSIO_35_LP_PERSIST false -ALT_MSSIO_35_MD_IBUF true -ALT_MSSIO_35_OUT_DRIVE 8 -ALT_MSSIO_35_RES_PULL UP -ALT_MSSIO_35_SCHMITT_TRIGGER false -ALT_MSSIO_36_ATP_EN false -ALT_MSSIO_36_CLAMP_DIODE false -ALT_MSSIO_36_LPMD_IBUF false -ALT_MSSIO_36_LPMD_OBUF false -ALT_MSSIO_36_LP_PERSIST false -ALT_MSSIO_36_MD_IBUF true -ALT_MSSIO_36_OUT_DRIVE 8 -ALT_MSSIO_36_RES_PULL UP -ALT_MSSIO_36_SCHMITT_TRIGGER false -ALT_MSSIO_37_ATP_EN false -ALT_MSSIO_37_CLAMP_DIODE false -ALT_MSSIO_37_LPMD_IBUF false -ALT_MSSIO_37_LPMD_OBUF false -ALT_MSSIO_37_LP_PERSIST false -ALT_MSSIO_37_MD_IBUF true -ALT_MSSIO_37_OUT_DRIVE 8 -ALT_MSSIO_37_RES_PULL UP -ALT_MSSIO_37_SCHMITT_TRIGGER false -ALT_MSSIO_3_ATP_EN false -ALT_MSSIO_3_CLAMP_DIODE false -ALT_MSSIO_3_LPMD_IBUF false -ALT_MSSIO_3_LPMD_OBUF false -ALT_MSSIO_3_LP_PERSIST false -ALT_MSSIO_3_MD_IBUF true -ALT_MSSIO_3_OUT_DRIVE 8 -ALT_MSSIO_3_RES_PULL UP -ALT_MSSIO_3_SCHMITT_TRIGGER false -ALT_MSSIO_4_ATP_EN false -ALT_MSSIO_4_CLAMP_DIODE false -ALT_MSSIO_4_LPMD_IBUF false -ALT_MSSIO_4_LPMD_OBUF false -ALT_MSSIO_4_LP_PERSIST false -ALT_MSSIO_4_MD_IBUF true -ALT_MSSIO_4_OUT_DRIVE 8 -ALT_MSSIO_4_RES_PULL UP -ALT_MSSIO_4_SCHMITT_TRIGGER false -ALT_MSSIO_5_ATP_EN false -ALT_MSSIO_5_CLAMP_DIODE false -ALT_MSSIO_5_LPMD_IBUF false -ALT_MSSIO_5_LPMD_OBUF false -ALT_MSSIO_5_LP_PERSIST false -ALT_MSSIO_5_MD_IBUF true -ALT_MSSIO_5_OUT_DRIVE 8 -ALT_MSSIO_5_RES_PULL UP -ALT_MSSIO_5_SCHMITT_TRIGGER false -ALT_MSSIO_6_ATP_EN false -ALT_MSSIO_6_CLAMP_DIODE false -ALT_MSSIO_6_LPMD_IBUF false -ALT_MSSIO_6_LPMD_OBUF false -ALT_MSSIO_6_LP_PERSIST false -ALT_MSSIO_6_MD_IBUF true -ALT_MSSIO_6_OUT_DRIVE 8 -ALT_MSSIO_6_RES_PULL UP -ALT_MSSIO_6_SCHMITT_TRIGGER false -ALT_MSSIO_7_ATP_EN false -ALT_MSSIO_7_CLAMP_DIODE false -ALT_MSSIO_7_LPMD_IBUF false -ALT_MSSIO_7_LPMD_OBUF false -ALT_MSSIO_7_LP_PERSIST false -ALT_MSSIO_7_MD_IBUF true -ALT_MSSIO_7_OUT_DRIVE 8 -ALT_MSSIO_7_RES_PULL UP -ALT_MSSIO_7_SCHMITT_TRIGGER false -ALT_MSSIO_8_ATP_EN false -ALT_MSSIO_8_CLAMP_DIODE false -ALT_MSSIO_8_LPMD_IBUF false -ALT_MSSIO_8_LPMD_OBUF false -ALT_MSSIO_8_LP_PERSIST false -ALT_MSSIO_8_MD_IBUF true -ALT_MSSIO_8_OUT_DRIVE 8 -ALT_MSSIO_8_RES_PULL UP -ALT_MSSIO_8_SCHMITT_TRIGGER false -ALT_MSSIO_9_ATP_EN false -ALT_MSSIO_9_CLAMP_DIODE false -ALT_MSSIO_9_LPMD_IBUF false -ALT_MSSIO_9_LPMD_OBUF false -ALT_MSSIO_9_LP_PERSIST false -ALT_MSSIO_9_MD_IBUF true -ALT_MSSIO_9_OUT_DRIVE 8 -ALT_MSSIO_9_RES_PULL UP -ALT_MSSIO_9_SCHMITT_TRIGGER false -BANK2_VOLTAGE 3.3 -BANK4_VOLTAGE 1.8 -BANK5_VOLTAGE 3.3 -CAN_0 UNUSED -CAN_0_TX_EBL_N UNUSED -CAN_1 UNUSED -CAN_1_TX_EBL_N UNUSED -CAN_CLK_FREQ 80 -CAN_CLK_SOURCE MSS_PLL -CORE_UP UNUSED -CRYPTO UNUSED -CRYPTO_DLL_JITTER_TOLERANCE MEDIUM_LOW -CRYPTO_ENABLE_ALARM false -CRYPTO_ENABLE_BUSERROR false -CRYPTO_ENABLE_BUSY true -CRYPTO_ENABLE_COMPLETE false -CRYPTO_ENABLE_DLL_LOCK true -CRYPTO_ENABLE_MESH false -CRYPTO_ENABLE_STREAMING false -CRYPTO_MSS_CLK_FREQ 200 -CRYPTO_USE_EMBEDDED_DLL true -DDR3_ADDRESS_MIRROR false -DDR3_ADDRESS_ORDERING CHIP_ROW_BANK_COL -DDR3_BANK_ADDR_WIDTH 3 -DDR3_BURST_LENGTH 0 -DDR3_CAS_ADDITIVE_LATENCY 0 -DDR3_CAS_LATENCY 5 -DDR3_CAS_WRITE_LATENCY 5 -DDR3_CLOCK_DDR 666 -DDR3_COL_ADDR_WIDTH 11 -DDR3_CONTROLLER_ADD_CMD_DRIVE 34 -DDR3_CONTROLLER_CLK_DRIVE 34 -DDR3_CONTROLLER_DQS_DRIVE 34 -DDR3_CONTROLLER_DQS_ODT 60 -DDR3_CONTROLLER_DQ_DRIVE 34 -DDR3_CONTROLLER_DQ_ODT 120 -DDR3_DM_MODE DM -DDR3_DQDQS_TRAINING_OFFSET 1 -DDR3_ENABLE_ECC false -DDR3_ENABLE_LOOKAHEAD_PRECHARGE_ACTIVATE false -DDR3_MEMORY_FORMAT COMPONENT -DDR3_NB_CLKS 1 -DDR3_NB_RANKS 1 -DDR3_ODT_ENABLE_RD_RNK0_ODT0 false -DDR3_ODT_ENABLE_RD_RNK0_ODT1 false -DDR3_ODT_ENABLE_RD_RNK1_ODT0 false -DDR3_ODT_ENABLE_RD_RNK1_ODT1 false -DDR3_ODT_ENABLE_WR_RNK0_ODT0 false -DDR3_ODT_ENABLE_WR_RNK0_ODT1 false -DDR3_ODT_ENABLE_WR_RNK1_ODT0 false -DDR3_ODT_ENABLE_WR_RNK1_ODT1 false -DDR3_OUTPUT_DRIVE_STRENGTH RZQ6 -DDR3_PARTIAL_ARRAY_SELF_REFRESH FULL -DDR3_READ_BURST_TYPE SEQUENTIAL -DDR3_ROW_ADDR_WIDTH 13 -DDR3_RTT_NOM DISABLED -DDR3_RTT_WR OFF -DDR3_SELF_REFRESH_TEMPERATURE NORMAL -DDR3_TIMING_FAW 40 -DDR3_TIMING_RAS 35 -DDR3_TIMING_RC 47.5 -DDR3_TIMING_RCD 12.5 -DDR3_TIMING_REFI 7.8 -DDR3_TIMING_RFC 110 -DDR3_TIMING_RP 12.5 -DDR3_TIMING_RRD 6.25 -DDR3_TIMING_RTP 8 -DDR3_TIMING_WR 18 -DDR3_TIMING_WTR 4 -DDR3_WIDTH 32 -DDR3_ZQ_CALIB_PERIOD 200 -DDR3_ZQ_CALIB_TYPE 0 -DDR3_ZQ_CAL_INIT_TIME 512 -DDR3_ZQ_CAL_L_TIME 256 -DDR3_ZQ_CAL_S_TIME 64 -DDR4_ADDRESS_MIRROR false -DDR4_ADDRESS_ORDERING CHIP_ROW_BG_BANK_COL -DDR4_AUTO_SELF_REFRESH 3 -DDR4_BANK_ADDR_WIDTH 2 -DDR4_BANK_GROUP_ADDRESS_WIDTH 1 -DDR4_BURST_LENGTH 0 -DDR4_CAS_ADDITIVE_LATENCY 0 -DDR4_CAS_LATENCY 12 -DDR4_CAS_WRITE_LATENCY 11 -DDR4_CA_PARITY_LATENCY_MODE 0 -DDR4_CLOCK_DDR 800 -DDR4_COL_ADDR_WIDTH 10 -DDR4_CONTROLLER_ADD_CMD_DRIVE 34 -DDR4_CONTROLLER_CLK_DRIVE 48 -DDR4_CONTROLLER_DQS_DRIVE 48 -DDR4_CONTROLLER_DQS_ODT 120 -DDR4_CONTROLLER_DQ_DRIVE 48 -DDR4_CONTROLLER_DQ_ODT 120 -DDR4_DM_MODE DM -DDR4_DQDQS_TRAINING_OFFSET 1 -DDR4_ENABLE_ECC false -DDR4_ENABLE_LOOKAHEAD_PRECHARGE_ACTIVATE false -DDR4_ENABLE_PAR_ALERT false -DDR4_GRANULARITY_MODE 0 -DDR4_INTERNAL_VREF_MONITER 0 -DDR4_MEMORY_FORMAT COMPONENT -DDR4_NB_CLKS 1 -DDR4_NB_RANKS 1 -DDR4_ODT_ENABLE_RD_RNK0_ODT0 false -DDR4_ODT_ENABLE_RD_RNK0_ODT1 false -DDR4_ODT_ENABLE_RD_RNK1_ODT0 false -DDR4_ODT_ENABLE_RD_RNK1_ODT1 false -DDR4_ODT_ENABLE_WR_RNK0_ODT0 false -DDR4_ODT_ENABLE_WR_RNK0_ODT1 false -DDR4_ODT_ENABLE_WR_RNK1_ODT0 false -DDR4_ODT_ENABLE_WR_RNK1_ODT1 false -DDR4_OUTPUT_DRIVE_STRENGTH RZQ7 -DDR4_POWERDOWN_INPUT_BUFFER 1 -DDR4_READ_BURST_TYPE SEQUENTIAL -DDR4_READ_PREAMBLE 0 -DDR4_ROW_ADDR_WIDTH 15 -DDR4_RTT_NOM RZQ4 -DDR4_RTT_PARK 0 -DDR4_RTT_WR OFF -DDR4_SELF_REFRESH_ABORT_MODE 0 -DDR4_TEMPERATURE_REFRESH_MODE 0 -DDR4_TEMPERATURE_REFRESH_RANGE NORMAL -DDR4_TIMING_CCD_L 5 -DDR4_TIMING_CCD_S 4 -DDR4_TIMING_FAW 25 -DDR4_TIMING_RAS 35 -DDR4_TIMING_RC 50 -DDR4_TIMING_RCD 15 -DDR4_TIMING_REFI 7.8 -DDR4_TIMING_RFC 160 -DDR4_TIMING_RP 15 -DDR4_TIMING_RRD_L 5 -DDR4_TIMING_RRD_S 4 -DDR4_TIMING_RTP 7.5 -DDR4_TIMING_WR 15 -DDR4_TIMING_WTR_L 6 -DDR4_TIMING_WTR_S 2 -DDR4_VREF_CA 45 -DDR4_VREF_CALIB_ENABLE 1 -DDR4_VREF_CALIB_RANGE 1 -DDR4_VREF_CALIB_VALUE 64.5 -DDR4_VREF_DATA 65 -DDR4_WIDTH 32 -DDR4_WRITE_PREAMBLE 0 -DDR4_ZQ_CALIB_PERIOD 200 -DDR4_ZQ_CALIB_TYPE 0 -DDR4_ZQ_CAL_INIT_TIME 1024 -DDR4_ZQ_CAL_L_TIME 512 -DDR4_ZQ_CAL_S_TIME 128 -DDR_CACHED_32BIT_MEM_SIZE 32 -DDR_CACHED_32BIT_MEM_UNIT MB -DDR_CACHED_64BIT_MEM_SIZE 1888 -DDR_CACHED_64BIT_MEM_UNIT MB -DDR_NON_CACHED_32BIT_MEM_SIZE 128 -DDR_NON_CACHED_32BIT_MEM_UNIT MB -DDR_NON_CACHED_64BIT_MEM_SIZE 0 -DDR_NON_CACHED_64BIT_MEM_UNIT GB -DDR_REFCLK DEDICATED_IO -DDR_SDRAM_TYPE LPDDR4 -DIE MPFS250T_ES -EMMC MSSIO_B4 -EMMC_DATA_7_4 MSSIO_B4 -EMMC_SD_CLK_SOURCE MSS_PLL -EMMC_SD_SDIO_FREQ 200 -EMMC_SD_SWITCHING ENABLED_SD -EMMC_SPEED_MODE HIGH_SPEED_200 -ENABLE_FEEDBACK_PORTS false -EXPOSE_BOOT_STATUS_PORTS false -FF_IN_PROGRESS UNUSED -FIC_0_AXI4_INITIATOR_USED false -FIC_0_AXI4_TARGET_USED false -FIC_0_EMBEDDED_DLL_JITTER_RANGE LOW -FIC_0_EMBEDDED_DLL_USED false -FIC_1_AXI4_INITIATOR_USED false -FIC_1_AXI4_TARGET_USED true -FIC_1_EMBEDDED_DLL_JITTER_RANGE MEDIUM_LOW -FIC_1_EMBEDDED_DLL_USED true -FIC_2_AXI4_TARGET_USED false -FIC_2_EMBEDDED_DLL_JITTER_RANGE LOW -FIC_2_EMBEDDED_DLL_USED false -FIC_3_APB_INITIATOR_USED true -FIC_3_EMBEDDED_DLL_JITTER_RANGE LOW -FIC_3_EMBEDDED_DLL_USED false -FLASH_VALID UNUSED -FREQOUT UNUSED -G5C_IOOUT UNUSED -GPIO_0_0 UNUSED -GPIO_0_0_7_RESET_SOURCE MSS -GPIO_0_0_DIR IN -GPIO_0_1 UNUSED -GPIO_0_10 UNUSED -GPIO_0_10_DIR IN -GPIO_0_11 UNUSED -GPIO_0_11_DIR IN -GPIO_0_12 UNUSED -GPIO_0_12_DIR IN -GPIO_0_13 UNUSED -GPIO_0_13_DIR IN -GPIO_0_1_DIR IN -GPIO_0_2 UNUSED -GPIO_0_2_DIR IN -GPIO_0_3 UNUSED -GPIO_0_3_DIR IN -GPIO_0_4 UNUSED -GPIO_0_4_DIR IN -GPIO_0_5 UNUSED -GPIO_0_5_DIR IN -GPIO_0_6 UNUSED -GPIO_0_6_DIR IN -GPIO_0_7 UNUSED -GPIO_0_7_DIR IN -GPIO_0_8 UNUSED -GPIO_0_8_13_RESET_SOURCE MSS -GPIO_0_8_DIR IN -GPIO_0_9 UNUSED -GPIO_0_9_DIR IN -GPIO_1_0 UNUSED -GPIO_1_0_7_RESET_SOURCE MSS -GPIO_1_0_DIR IN -GPIO_1_1 UNUSED -GPIO_1_10 UNUSED -GPIO_1_10_DIR IN -GPIO_1_11 UNUSED -GPIO_1_11_DIR IN -GPIO_1_12 MSSIO_B2 -GPIO_1_12_DIR OUT -GPIO_1_13 UNUSED -GPIO_1_13_DIR IN -GPIO_1_14 UNUSED -GPIO_1_14_DIR IN -GPIO_1_15 UNUSED -GPIO_1_15_DIR IN -GPIO_1_16 MSSIO_B2 -GPIO_1_16_23_RESET_SOURCE MSS -GPIO_1_16_DIR OUT -GPIO_1_17 UNUSED -GPIO_1_17_DIR IN -GPIO_1_18 UNUSED -GPIO_1_18_DIR IN -GPIO_1_19 UNUSED -GPIO_1_19_DIR IN -GPIO_1_1_DIR IN -GPIO_1_2 UNUSED -GPIO_1_20 MSSIO_B2 -GPIO_1_20_DIR OUT -GPIO_1_21 UNUSED -GPIO_1_21_DIR IN -GPIO_1_22 UNUSED -GPIO_1_22_DIR IN -GPIO_1_23 MSSIO_B2 -GPIO_1_23_DIR OUT -GPIO_1_2_DIR IN -GPIO_1_3 UNUSED -GPIO_1_3_DIR IN -GPIO_1_4 UNUSED -GPIO_1_4_DIR IN -GPIO_1_5 UNUSED -GPIO_1_5_DIR IN -GPIO_1_6 UNUSED -GPIO_1_6_DIR IN -GPIO_1_7 UNUSED -GPIO_1_7_DIR IN -GPIO_1_8 UNUSED -GPIO_1_8_15_RESET_SOURCE MSS -GPIO_1_8_DIR IN -GPIO_1_9 UNUSED -GPIO_1_9_DIR IN -GPIO_2_0 UNUSED -GPIO_2_0_7_RESET_SOURCE MSS -GPIO_2_0_DIR IN -GPIO_2_1 FABRIC -GPIO_2_10 UNUSED -GPIO_2_10_DIR IN -GPIO_2_11 UNUSED -GPIO_2_11_DIR IN -GPIO_2_12 UNUSED -GPIO_2_12_DIR IN -GPIO_2_13 UNUSED -GPIO_2_13_DIR IN -GPIO_2_14 UNUSED -GPIO_2_14_DIR IN -GPIO_2_15 UNUSED -GPIO_2_15_DIR IN -GPIO_2_16 UNUSED -GPIO_2_16_23_RESET_SOURCE MSS -GPIO_2_16_DIR IN -GPIO_2_17 UNUSED -GPIO_2_17_DIR IN -GPIO_2_18 FABRIC -GPIO_2_18_DIR OUT -GPIO_2_19 FABRIC -GPIO_2_19_DIR OUT -GPIO_2_1_DIR OUT -GPIO_2_2 FABRIC -GPIO_2_20 UNUSED -GPIO_2_20_DIR IN -GPIO_2_21 UNUSED -GPIO_2_21_DIR IN -GPIO_2_22 UNUSED -GPIO_2_22_DIR IN -GPIO_2_23 UNUSED -GPIO_2_23_DIR IN -GPIO_2_24 UNUSED -GPIO_2_24_31_RESET_SOURCE MSS -GPIO_2_24_DIR IN -GPIO_2_25 FABRIC -GPIO_2_25_DIR IN -GPIO_2_26 UNUSED -GPIO_2_26_DIR IN -GPIO_2_27 UNUSED -GPIO_2_27_DIR IN -GPIO_2_28 UNUSED -GPIO_2_28_DIR IN -GPIO_2_29 UNUSED -GPIO_2_29_DIR IN -GPIO_2_2_DIR OUT -GPIO_2_3 FABRIC -GPIO_2_30 UNUSED -GPIO_2_30_DIR IN -GPIO_2_31 UNUSED -GPIO_2_31_DIR IN -GPIO_2_3_DIR OUT -GPIO_2_4 FABRIC -GPIO_2_4_DIR OUT -GPIO_2_5 UNUSED -GPIO_2_5_DIR IN -GPIO_2_6 UNUSED -GPIO_2_6_DIR IN -GPIO_2_7 UNUSED -GPIO_2_7_DIR IN -GPIO_2_8 FABRIC -GPIO_2_8_15_RESET_SOURCE MSS -GPIO_2_8_DIR OUT -GPIO_2_9 FABRIC -GPIO_2_9_DIR OUT -GPIO_INTERRUPT_FAB_CR_DATA 0x00000000 -I2C_0 FABRIC -I2C_0_BAUD_RATE_CLOCK FABRIC -I2C_0_SMBUS UNUSED -I2C_0_SPEED_MODE STANDARD -I2C_1 UNUSED -I2C_1_BAUD_RATE_CLOCK UNUSED -I2C_1_SMBUS UNUSED -I2C_1_SPEED_MODE STANDARD -INTERNAL_DEBUG false -INTERRUPT true -IO_REFCLK_FREQ 125 -JTAG_TRACE false -JTAG_TRACE_CONTROL_VIA_FABRIC false -L2CACHE_DMA_WAY0 true -L2CACHE_DMA_WAY1 true -L2CACHE_DMA_WAY10 false -L2CACHE_DMA_WAY11 false -L2CACHE_DMA_WAY12 false -L2CACHE_DMA_WAY13 false -L2CACHE_DMA_WAY14 false -L2CACHE_DMA_WAY15 false -L2CACHE_DMA_WAY2 true -L2CACHE_DMA_WAY3 true -L2CACHE_DMA_WAY4 true -L2CACHE_DMA_WAY5 true -L2CACHE_DMA_WAY6 true -L2CACHE_DMA_WAY7 true -L2CACHE_DMA_WAY8 false -L2CACHE_DMA_WAY9 false -L2CACHE_E51_D_WAY0 true -L2CACHE_E51_D_WAY1 true -L2CACHE_E51_D_WAY10 false -L2CACHE_E51_D_WAY11 false -L2CACHE_E51_D_WAY12 false -L2CACHE_E51_D_WAY13 false -L2CACHE_E51_D_WAY14 false -L2CACHE_E51_D_WAY15 false -L2CACHE_E51_D_WAY2 true -L2CACHE_E51_D_WAY3 true -L2CACHE_E51_D_WAY4 true -L2CACHE_E51_D_WAY5 true -L2CACHE_E51_D_WAY6 true -L2CACHE_E51_D_WAY7 true -L2CACHE_E51_D_WAY8 false -L2CACHE_E51_D_WAY9 false -L2CACHE_E51_I_WAY0 true -L2CACHE_E51_I_WAY1 true -L2CACHE_E51_I_WAY10 false -L2CACHE_E51_I_WAY11 false -L2CACHE_E51_I_WAY12 false -L2CACHE_E51_I_WAY13 false -L2CACHE_E51_I_WAY14 false -L2CACHE_E51_I_WAY15 false -L2CACHE_E51_I_WAY2 true -L2CACHE_E51_I_WAY3 true -L2CACHE_E51_I_WAY4 true -L2CACHE_E51_I_WAY5 true -L2CACHE_E51_I_WAY6 true -L2CACHE_E51_I_WAY7 true -L2CACHE_E51_I_WAY8 false -L2CACHE_E51_I_WAY9 false -L2CACHE_LIM_SIZE 4 -L2CACHE_PORT_0_WAY0 true -L2CACHE_PORT_0_WAY1 true -L2CACHE_PORT_0_WAY10 false -L2CACHE_PORT_0_WAY11 false -L2CACHE_PORT_0_WAY12 false -L2CACHE_PORT_0_WAY13 false -L2CACHE_PORT_0_WAY14 false -L2CACHE_PORT_0_WAY15 false -L2CACHE_PORT_0_WAY2 true -L2CACHE_PORT_0_WAY3 true -L2CACHE_PORT_0_WAY4 true -L2CACHE_PORT_0_WAY5 true -L2CACHE_PORT_0_WAY6 true -L2CACHE_PORT_0_WAY7 true -L2CACHE_PORT_0_WAY8 false -L2CACHE_PORT_0_WAY9 false -L2CACHE_PORT_1_WAY0 true -L2CACHE_PORT_1_WAY1 true -L2CACHE_PORT_1_WAY10 false -L2CACHE_PORT_1_WAY11 false -L2CACHE_PORT_1_WAY12 false -L2CACHE_PORT_1_WAY13 false -L2CACHE_PORT_1_WAY14 false -L2CACHE_PORT_1_WAY15 false -L2CACHE_PORT_1_WAY2 true -L2CACHE_PORT_1_WAY3 true -L2CACHE_PORT_1_WAY4 true -L2CACHE_PORT_1_WAY5 true -L2CACHE_PORT_1_WAY6 true -L2CACHE_PORT_1_WAY7 true -L2CACHE_PORT_1_WAY8 false -L2CACHE_PORT_1_WAY9 false -L2CACHE_PORT_2_WAY0 true -L2CACHE_PORT_2_WAY1 true -L2CACHE_PORT_2_WAY10 false -L2CACHE_PORT_2_WAY11 false -L2CACHE_PORT_2_WAY12 false -L2CACHE_PORT_2_WAY13 false -L2CACHE_PORT_2_WAY14 false -L2CACHE_PORT_2_WAY15 false -L2CACHE_PORT_2_WAY2 true -L2CACHE_PORT_2_WAY3 true -L2CACHE_PORT_2_WAY4 true -L2CACHE_PORT_2_WAY5 true -L2CACHE_PORT_2_WAY6 true -L2CACHE_PORT_2_WAY7 true -L2CACHE_PORT_2_WAY8 false -L2CACHE_PORT_2_WAY9 false -L2CACHE_PORT_3_WAY0 true -L2CACHE_PORT_3_WAY1 true -L2CACHE_PORT_3_WAY10 false -L2CACHE_PORT_3_WAY11 false -L2CACHE_PORT_3_WAY12 false -L2CACHE_PORT_3_WAY13 false -L2CACHE_PORT_3_WAY14 false -L2CACHE_PORT_3_WAY15 false -L2CACHE_PORT_3_WAY2 true -L2CACHE_PORT_3_WAY3 true -L2CACHE_PORT_3_WAY4 true -L2CACHE_PORT_3_WAY5 true -L2CACHE_PORT_3_WAY6 true -L2CACHE_PORT_3_WAY7 true -L2CACHE_PORT_3_WAY8 false -L2CACHE_PORT_3_WAY9 false -L2CACHE_SCRATCH_SIZE 4 -L2CACHE_U54_1_D_WAY0 true -L2CACHE_U54_1_D_WAY1 true -L2CACHE_U54_1_D_WAY10 false -L2CACHE_U54_1_D_WAY11 false -L2CACHE_U54_1_D_WAY12 false -L2CACHE_U54_1_D_WAY13 false -L2CACHE_U54_1_D_WAY14 false -L2CACHE_U54_1_D_WAY15 false -L2CACHE_U54_1_D_WAY2 true -L2CACHE_U54_1_D_WAY3 true -L2CACHE_U54_1_D_WAY4 true -L2CACHE_U54_1_D_WAY5 true -L2CACHE_U54_1_D_WAY6 true -L2CACHE_U54_1_D_WAY7 true -L2CACHE_U54_1_D_WAY8 false -L2CACHE_U54_1_D_WAY9 false -L2CACHE_U54_1_I_WAY0 true -L2CACHE_U54_1_I_WAY1 true -L2CACHE_U54_1_I_WAY10 false -L2CACHE_U54_1_I_WAY11 false -L2CACHE_U54_1_I_WAY12 false -L2CACHE_U54_1_I_WAY13 false -L2CACHE_U54_1_I_WAY14 false -L2CACHE_U54_1_I_WAY15 false -L2CACHE_U54_1_I_WAY2 true -L2CACHE_U54_1_I_WAY3 true -L2CACHE_U54_1_I_WAY4 true -L2CACHE_U54_1_I_WAY5 true -L2CACHE_U54_1_I_WAY6 true -L2CACHE_U54_1_I_WAY7 true -L2CACHE_U54_1_I_WAY8 false -L2CACHE_U54_1_I_WAY9 false -L2CACHE_U54_2_D_WAY0 true -L2CACHE_U54_2_D_WAY1 true -L2CACHE_U54_2_D_WAY10 false -L2CACHE_U54_2_D_WAY11 false -L2CACHE_U54_2_D_WAY12 false -L2CACHE_U54_2_D_WAY13 false -L2CACHE_U54_2_D_WAY14 false -L2CACHE_U54_2_D_WAY15 false -L2CACHE_U54_2_D_WAY2 true -L2CACHE_U54_2_D_WAY3 true -L2CACHE_U54_2_D_WAY4 true -L2CACHE_U54_2_D_WAY5 true -L2CACHE_U54_2_D_WAY6 true -L2CACHE_U54_2_D_WAY7 true -L2CACHE_U54_2_D_WAY8 false -L2CACHE_U54_2_D_WAY9 false -L2CACHE_U54_2_I_WAY0 true -L2CACHE_U54_2_I_WAY1 true -L2CACHE_U54_2_I_WAY10 false -L2CACHE_U54_2_I_WAY11 false -L2CACHE_U54_2_I_WAY12 false -L2CACHE_U54_2_I_WAY13 false -L2CACHE_U54_2_I_WAY14 false -L2CACHE_U54_2_I_WAY15 false -L2CACHE_U54_2_I_WAY2 true -L2CACHE_U54_2_I_WAY3 true -L2CACHE_U54_2_I_WAY4 true -L2CACHE_U54_2_I_WAY5 true -L2CACHE_U54_2_I_WAY6 true -L2CACHE_U54_2_I_WAY7 true -L2CACHE_U54_2_I_WAY8 false -L2CACHE_U54_2_I_WAY9 false -L2CACHE_U54_3_D_WAY0 true -L2CACHE_U54_3_D_WAY1 true -L2CACHE_U54_3_D_WAY10 false -L2CACHE_U54_3_D_WAY11 false -L2CACHE_U54_3_D_WAY12 false -L2CACHE_U54_3_D_WAY13 false -L2CACHE_U54_3_D_WAY14 false -L2CACHE_U54_3_D_WAY15 false -L2CACHE_U54_3_D_WAY2 true -L2CACHE_U54_3_D_WAY3 true -L2CACHE_U54_3_D_WAY4 true -L2CACHE_U54_3_D_WAY5 true -L2CACHE_U54_3_D_WAY6 true -L2CACHE_U54_3_D_WAY7 true -L2CACHE_U54_3_D_WAY8 false -L2CACHE_U54_3_D_WAY9 false -L2CACHE_U54_3_I_WAY0 true -L2CACHE_U54_3_I_WAY1 true -L2CACHE_U54_3_I_WAY10 false -L2CACHE_U54_3_I_WAY11 false -L2CACHE_U54_3_I_WAY12 false -L2CACHE_U54_3_I_WAY13 false -L2CACHE_U54_3_I_WAY14 false -L2CACHE_U54_3_I_WAY15 false -L2CACHE_U54_3_I_WAY2 true -L2CACHE_U54_3_I_WAY3 true -L2CACHE_U54_3_I_WAY4 true -L2CACHE_U54_3_I_WAY5 true -L2CACHE_U54_3_I_WAY6 true -L2CACHE_U54_3_I_WAY7 true -L2CACHE_U54_3_I_WAY8 false -L2CACHE_U54_3_I_WAY9 false -L2CACHE_U54_4_D_WAY0 true -L2CACHE_U54_4_D_WAY1 true -L2CACHE_U54_4_D_WAY10 false -L2CACHE_U54_4_D_WAY11 false -L2CACHE_U54_4_D_WAY12 false -L2CACHE_U54_4_D_WAY13 false -L2CACHE_U54_4_D_WAY14 false -L2CACHE_U54_4_D_WAY15 false -L2CACHE_U54_4_D_WAY2 true -L2CACHE_U54_4_D_WAY3 true -L2CACHE_U54_4_D_WAY4 true -L2CACHE_U54_4_D_WAY5 true -L2CACHE_U54_4_D_WAY6 true -L2CACHE_U54_4_D_WAY7 true -L2CACHE_U54_4_D_WAY8 false -L2CACHE_U54_4_D_WAY9 false -L2CACHE_U54_4_I_WAY0 true -L2CACHE_U54_4_I_WAY1 true -L2CACHE_U54_4_I_WAY10 false -L2CACHE_U54_4_I_WAY11 false -L2CACHE_U54_4_I_WAY12 false -L2CACHE_U54_4_I_WAY13 false -L2CACHE_U54_4_I_WAY14 false -L2CACHE_U54_4_I_WAY15 false -L2CACHE_U54_4_I_WAY2 true -L2CACHE_U54_4_I_WAY3 true -L2CACHE_U54_4_I_WAY4 true -L2CACHE_U54_4_I_WAY5 true -L2CACHE_U54_4_I_WAY6 true -L2CACHE_U54_4_I_WAY7 true -L2CACHE_U54_4_I_WAY8 false -L2CACHE_U54_4_I_WAY9 false -LOCK_DOWN_B2_IOS false -LOCK_DOWN_B4_IOS false -LOCK_DOWN_DDR_IOS false -LOCK_DOWN_SGMII_IOS false -LPDDR3_ADDRESS_ORDERING CHIP_ROW_BANK_COL -LPDDR3_BANK_ADDR_WIDTH 3 -LPDDR3_CLOCK_DDR 666 -LPDDR3_COL_ADDR_WIDTH 11 -LPDDR3_CONTROLLER_ADD_CMD_DRIVE 40 -LPDDR3_CONTROLLER_CLK_DRIVE 48 -LPDDR3_CONTROLLER_DQS_DRIVE 48 -LPDDR3_CONTROLLER_DQS_ODT 120 -LPDDR3_CONTROLLER_DQ_DRIVE 48 -LPDDR3_CONTROLLER_DQ_ODT 120 -LPDDR3_DATA_LATENCY RL10WL6 -LPDDR3_DM_MODE DM -LPDDR3_DQDQS_TRAINING_OFFSET 1 -LPDDR3_DQ_ODT DISABLE -LPDDR3_ENABLE_ECC false -LPDDR3_ENABLE_LOOKAHEAD_PRECHARGE_ACTIVATE false -LPDDR3_MEMORY_FORMAT COMPONENT -LPDDR3_ODT_ENABLE_RD_RNK0_ODT0 false -LPDDR3_ODT_ENABLE_WR_RNK0_ODT0 false -LPDDR3_OUTPUT_DRIVE_STRENGTH PDPU34P3 -LPDDR3_POWERDOWN_ODT 0 -LPDDR3_ROW_ADDR_WIDTH 14 -LPDDR3_TIMING_FAW 50 -LPDDR3_TIMING_MRR 4 -LPDDR3_TIMING_MRW 10 -LPDDR3_TIMING_RAS 42 -LPDDR3_TIMING_RC 57 -LPDDR3_TIMING_RCD 15 -LPDDR3_TIMING_REFI 3.9 -LPDDR3_TIMING_RFC 130 -LPDDR3_TIMING_RP 15 -LPDDR3_TIMING_RRD 10 -LPDDR3_TIMING_RTP 8 -LPDDR3_TIMING_WR 18 -LPDDR3_TIMING_WTR 4 -LPDDR3_WIDTH 32 -LPDDR3_ZQ_CALIB_PERIOD 200 -LPDDR3_ZQ_CALIB_TYPE 0 -LPDDR3_ZQ_CAL_INIT_TIME 1 -LPDDR3_ZQ_CAL_L_TIME 360 -LPDDR3_ZQ_CAL_R_TIME 50 -LPDDR3_ZQ_CAL_S_TIME 90 -LPDDR4_ADDRESS_ORDERING CHIP_ROW_BANK_COL -LPDDR4_BANK_ADDR_WIDTH 3 -LPDDR4_CA_ODT RZQ4 -LPDDR4_CLOCK_DDR 800 -LPDDR4_COL_ADDR_WIDTH 10 -LPDDR4_CONTROLLER_ADD_CMD_DRIVE 34 -LPDDR4_CONTROLLER_CLK_DRIVE 34 -LPDDR4_CONTROLLER_DQS_DRIVE 40 -LPDDR4_CONTROLLER_DQS_ODT 40 -LPDDR4_CONTROLLER_DQ_DRIVE 40 -LPDDR4_CONTROLLER_DQ_ODT 40 -LPDDR4_DM_MODE DM -LPDDR4_DQDQS_TRAINING_OFFSET 1 -LPDDR4_DQ_ODT RZQ2 -LPDDR4_DRIVE_STRENGTH RZQ6 -LPDDR4_ENABLE_ECC false -LPDDR4_ENABLE_LOOKAHEAD_PRECHARGE_ACTIVATE false -LPDDR4_MEMORY_FORMAT COMPONENT -LPDDR4_ODTE_CA 0 -LPDDR4_ODTE_CK 0 -LPDDR4_ODTE_CS 0 -LPDDR4_PULLUP_CAL VDDQ3 -LPDDR4_RD_POSTAMBLE CK0P5 -LPDDR4_RD_PREAMBLE STATIC -LPDDR4_READ_LATENCY RL14 -LPDDR4_ROW_ADDR_WIDTH 16 -LPDDR4_SELF_REFRESH_ABORT_MODE 0 -LPDDR4_SOC_ODT RZQ6 -LPDDR4_TIMING_FAW 40 -LPDDR4_TIMING_MRR 8 -LPDDR4_TIMING_MRW 10 -LPDDR4_TIMING_RAS 42 -LPDDR4_TIMING_RC 63 -LPDDR4_TIMING_RCD 18 -LPDDR4_TIMING_REFI 3.905 -LPDDR4_TIMING_RFC 380 -LPDDR4_TIMING_RP 21 -LPDDR4_TIMING_RRD 10 -LPDDR4_TIMING_RTP 10 -LPDDR4_TIMING_WR 18 -LPDDR4_TIMING_WTR 8 -LPDDR4_VREF_CA 50 -LPDDR4_VREF_CALIB_ENABLE 1 -LPDDR4_VREF_CALIB_RANGE 1 -LPDDR4_VREF_CALIB_VALUE 31.2 -LPDDR4_VREF_DATA 15 -LPDDR4_WIDTH 32 -LPDDR4_WRITE_LATENCY WL8 -LPDDR4_WR_POSTAMBLE CK0P5 -LPDDR4_ZQ_CALIB_PERIOD 200 -LPDDR4_ZQ_CAL_LATCH_TIME 30 -LPDDR4_ZQ_CAL_R_TIME 50 -LPDDR4_ZQ_CAL_TIME 1 -LP_STATE UNUSED -M2F_MONITOR UNUSED -MAC_0 SGMII_IO_B5 -MAC_0_MANAGEMENT MSSIO_B2_B -MAC_0_OTHER UNUSED -MAC_0_TSU UNUSED -MAC_1 SGMII_IO_B5 -MAC_1_MANAGEMENT UNUSED -MAC_1_OTHER UNUSED -MAC_1_TSU UNUSED -MAC_SGMII_REFCLK DEDICATED_IO -MAC_TSU_REFCLK DEDICATED_IO -MMUART_0 FABRIC -MMUART_0_MODE ASYNCHRONOUS -MMUART_0_MODEM UNUSED -MMUART_0_OTHER UNUSED -MMUART_1 FABRIC -MMUART_1_MODE ASYNCHRONOUS -MMUART_1_MODEM UNUSED -MMUART_1_OTHER UNUSED -MMUART_2 UNUSED -MMUART_3 UNUSED -MMUART_4 UNUSED -MODULE_NAME MSS_SEV -MSSIO_0_ATP_EN false -MSSIO_0_CLAMP_DIODE false -MSSIO_0_LPMD_IBUF false -MSSIO_0_LPMD_OBUF false -MSSIO_0_LP_PERSIST false -MSSIO_0_MD_IBUF true -MSSIO_0_OUT_DRIVE 8 -MSSIO_0_RES_PULL UP -MSSIO_0_SCHMITT_TRIGGER false -MSSIO_10_ATP_EN false -MSSIO_10_CLAMP_DIODE false -MSSIO_10_LPMD_IBUF false -MSSIO_10_LPMD_OBUF false -MSSIO_10_LP_PERSIST false -MSSIO_10_MD_IBUF true -MSSIO_10_OUT_DRIVE 8 -MSSIO_10_RES_PULL UP -MSSIO_10_SCHMITT_TRIGGER false -MSSIO_11_ATP_EN false -MSSIO_11_CLAMP_DIODE false -MSSIO_11_LPMD_IBUF false -MSSIO_11_LPMD_OBUF false -MSSIO_11_LP_PERSIST false -MSSIO_11_MD_IBUF true -MSSIO_11_OUT_DRIVE 8 -MSSIO_11_RES_PULL UP -MSSIO_11_SCHMITT_TRIGGER false -MSSIO_12_ATP_EN false -MSSIO_12_CLAMP_DIODE false -MSSIO_12_LPMD_IBUF false -MSSIO_12_LPMD_OBUF false -MSSIO_12_LP_PERSIST false -MSSIO_12_MD_IBUF true -MSSIO_12_OUT_DRIVE 8 -MSSIO_12_RES_PULL UP -MSSIO_12_SCHMITT_TRIGGER false -MSSIO_13_ATP_EN false -MSSIO_13_CLAMP_DIODE false -MSSIO_13_LPMD_IBUF false -MSSIO_13_LPMD_OBUF false -MSSIO_13_LP_PERSIST false -MSSIO_13_MD_IBUF true -MSSIO_13_OUT_DRIVE 8 -MSSIO_13_RES_PULL UP -MSSIO_13_SCHMITT_TRIGGER false -MSSIO_14_ATP_EN false -MSSIO_14_CLAMP_DIODE false -MSSIO_14_LPMD_IBUF false -MSSIO_14_LPMD_OBUF false -MSSIO_14_LP_PERSIST false -MSSIO_14_MD_IBUF true -MSSIO_14_OUT_DRIVE 8 -MSSIO_14_RES_PULL UP -MSSIO_14_SCHMITT_TRIGGER false -MSSIO_15_ATP_EN false -MSSIO_15_CLAMP_DIODE false -MSSIO_15_LPMD_IBUF false -MSSIO_15_LPMD_OBUF false -MSSIO_15_LP_PERSIST false -MSSIO_15_MD_IBUF true -MSSIO_15_OUT_DRIVE 8 -MSSIO_15_RES_PULL UP -MSSIO_15_SCHMITT_TRIGGER false -MSSIO_16_ATP_EN false -MSSIO_16_CLAMP_DIODE false -MSSIO_16_LPMD_IBUF false -MSSIO_16_LPMD_OBUF false -MSSIO_16_LP_PERSIST false -MSSIO_16_MD_IBUF true -MSSIO_16_OUT_DRIVE 8 -MSSIO_16_RES_PULL UP -MSSIO_16_SCHMITT_TRIGGER false -MSSIO_17_ATP_EN false -MSSIO_17_CLAMP_DIODE false -MSSIO_17_LPMD_IBUF false -MSSIO_17_LPMD_OBUF false -MSSIO_17_LP_PERSIST false -MSSIO_17_MD_IBUF true -MSSIO_17_OUT_DRIVE 8 -MSSIO_17_RES_PULL UP -MSSIO_17_SCHMITT_TRIGGER false -MSSIO_18_ATP_EN false -MSSIO_18_CLAMP_DIODE false -MSSIO_18_LPMD_IBUF false -MSSIO_18_LPMD_OBUF false -MSSIO_18_LP_PERSIST false -MSSIO_18_MD_IBUF true -MSSIO_18_OUT_DRIVE 8 -MSSIO_18_RES_PULL UP -MSSIO_18_SCHMITT_TRIGGER false -MSSIO_19_ATP_EN false -MSSIO_19_CLAMP_DIODE false -MSSIO_19_LPMD_IBUF false -MSSIO_19_LPMD_OBUF false -MSSIO_19_LP_PERSIST false -MSSIO_19_MD_IBUF true -MSSIO_19_OUT_DRIVE 8 -MSSIO_19_RES_PULL UP -MSSIO_19_SCHMITT_TRIGGER false -MSSIO_1_ATP_EN false -MSSIO_1_CLAMP_DIODE false -MSSIO_1_LPMD_IBUF false -MSSIO_1_LPMD_OBUF false -MSSIO_1_LP_PERSIST false -MSSIO_1_MD_IBUF true -MSSIO_1_OUT_DRIVE 8 -MSSIO_1_RES_PULL UP -MSSIO_1_SCHMITT_TRIGGER false -MSSIO_20_ATP_EN false -MSSIO_20_CLAMP_DIODE false -MSSIO_20_LPMD_IBUF false -MSSIO_20_LPMD_OBUF false -MSSIO_20_LP_PERSIST false -MSSIO_20_MD_IBUF true -MSSIO_20_OUT_DRIVE 8 -MSSIO_20_RES_PULL UP -MSSIO_20_SCHMITT_TRIGGER false -MSSIO_21_ATP_EN false -MSSIO_21_CLAMP_DIODE false -MSSIO_21_LPMD_IBUF false -MSSIO_21_LPMD_OBUF false -MSSIO_21_LP_PERSIST false -MSSIO_21_MD_IBUF true -MSSIO_21_OUT_DRIVE 8 -MSSIO_21_RES_PULL UP -MSSIO_21_SCHMITT_TRIGGER false -MSSIO_22_ATP_EN false -MSSIO_22_CLAMP_DIODE false -MSSIO_22_LPMD_IBUF false -MSSIO_22_LPMD_OBUF false -MSSIO_22_LP_PERSIST false -MSSIO_22_MD_IBUF true -MSSIO_22_OUT_DRIVE 8 -MSSIO_22_RES_PULL UP -MSSIO_22_SCHMITT_TRIGGER false -MSSIO_23_ATP_EN false -MSSIO_23_CLAMP_DIODE false -MSSIO_23_LPMD_IBUF false -MSSIO_23_LPMD_OBUF false -MSSIO_23_LP_PERSIST false -MSSIO_23_MD_IBUF true -MSSIO_23_OUT_DRIVE 8 -MSSIO_23_RES_PULL UP -MSSIO_23_SCHMITT_TRIGGER false -MSSIO_24_ATP_EN false -MSSIO_24_CLAMP_DIODE false -MSSIO_24_LPMD_IBUF false -MSSIO_24_LPMD_OBUF false -MSSIO_24_LP_PERSIST false -MSSIO_24_MD_IBUF true -MSSIO_24_OUT_DRIVE 8 -MSSIO_24_RES_PULL UP -MSSIO_24_SCHMITT_TRIGGER false -MSSIO_25_ATP_EN false -MSSIO_25_CLAMP_DIODE false -MSSIO_25_LPMD_IBUF false -MSSIO_25_LPMD_OBUF false -MSSIO_25_LP_PERSIST false -MSSIO_25_MD_IBUF true -MSSIO_25_OUT_DRIVE 8 -MSSIO_25_RES_PULL UP -MSSIO_25_SCHMITT_TRIGGER false -MSSIO_26_ATP_EN false -MSSIO_26_CLAMP_DIODE false -MSSIO_26_LPMD_IBUF false -MSSIO_26_LPMD_OBUF false -MSSIO_26_LP_PERSIST false -MSSIO_26_MD_IBUF true -MSSIO_26_OUT_DRIVE 8 -MSSIO_26_RES_PULL UP -MSSIO_26_SCHMITT_TRIGGER false -MSSIO_27_ATP_EN false -MSSIO_27_CLAMP_DIODE false -MSSIO_27_LPMD_IBUF false -MSSIO_27_LPMD_OBUF false -MSSIO_27_LP_PERSIST false -MSSIO_27_MD_IBUF true -MSSIO_27_OUT_DRIVE 8 -MSSIO_27_RES_PULL UP -MSSIO_27_SCHMITT_TRIGGER false -MSSIO_28_ATP_EN false -MSSIO_28_CLAMP_DIODE false -MSSIO_28_LPMD_IBUF false -MSSIO_28_LPMD_OBUF false -MSSIO_28_LP_PERSIST false -MSSIO_28_MD_IBUF true -MSSIO_28_OUT_DRIVE 8 -MSSIO_28_RES_PULL UP -MSSIO_28_SCHMITT_TRIGGER false -MSSIO_29_ATP_EN false -MSSIO_29_CLAMP_DIODE false -MSSIO_29_LPMD_IBUF false -MSSIO_29_LPMD_OBUF false -MSSIO_29_LP_PERSIST false -MSSIO_29_MD_IBUF true -MSSIO_29_OUT_DRIVE 8 -MSSIO_29_RES_PULL UP -MSSIO_29_SCHMITT_TRIGGER false -MSSIO_2_ATP_EN false -MSSIO_2_CLAMP_DIODE false -MSSIO_2_LPMD_IBUF false -MSSIO_2_LPMD_OBUF false -MSSIO_2_LP_PERSIST false -MSSIO_2_MD_IBUF true -MSSIO_2_OUT_DRIVE 8 -MSSIO_2_RES_PULL UP -MSSIO_2_SCHMITT_TRIGGER false -MSSIO_30_ATP_EN false -MSSIO_30_CLAMP_DIODE false -MSSIO_30_LPMD_IBUF false -MSSIO_30_LPMD_OBUF false -MSSIO_30_LP_PERSIST false -MSSIO_30_MD_IBUF true -MSSIO_30_OUT_DRIVE 8 -MSSIO_30_RES_PULL UP -MSSIO_30_SCHMITT_TRIGGER false -MSSIO_31_ATP_EN false -MSSIO_31_CLAMP_DIODE false -MSSIO_31_LPMD_IBUF false -MSSIO_31_LPMD_OBUF false -MSSIO_31_LP_PERSIST false -MSSIO_31_MD_IBUF true -MSSIO_31_OUT_DRIVE 8 -MSSIO_31_RES_PULL UP -MSSIO_31_SCHMITT_TRIGGER false -MSSIO_32_ATP_EN false -MSSIO_32_CLAMP_DIODE false -MSSIO_32_LPMD_IBUF false -MSSIO_32_LPMD_OBUF false -MSSIO_32_LP_PERSIST false -MSSIO_32_MD_IBUF true -MSSIO_32_OUT_DRIVE 8 -MSSIO_32_RES_PULL UP -MSSIO_32_SCHMITT_TRIGGER false -MSSIO_33_ATP_EN false -MSSIO_33_CLAMP_DIODE false -MSSIO_33_LPMD_IBUF false -MSSIO_33_LPMD_OBUF false -MSSIO_33_LP_PERSIST false -MSSIO_33_MD_IBUF true -MSSIO_33_OUT_DRIVE 8 -MSSIO_33_RES_PULL UP -MSSIO_33_SCHMITT_TRIGGER false -MSSIO_34_ATP_EN false -MSSIO_34_CLAMP_DIODE false -MSSIO_34_LPMD_IBUF false -MSSIO_34_LPMD_OBUF false -MSSIO_34_LP_PERSIST false -MSSIO_34_MD_IBUF true -MSSIO_34_OUT_DRIVE 8 -MSSIO_34_RES_PULL UP -MSSIO_34_SCHMITT_TRIGGER false -MSSIO_35_ATP_EN false -MSSIO_35_CLAMP_DIODE false -MSSIO_35_LPMD_IBUF false -MSSIO_35_LPMD_OBUF false -MSSIO_35_LP_PERSIST false -MSSIO_35_MD_IBUF true -MSSIO_35_OUT_DRIVE 8 -MSSIO_35_RES_PULL UP -MSSIO_35_SCHMITT_TRIGGER false -MSSIO_36_ATP_EN false -MSSIO_36_CLAMP_DIODE false -MSSIO_36_LPMD_IBUF false -MSSIO_36_LPMD_OBUF false -MSSIO_36_LP_PERSIST false -MSSIO_36_MD_IBUF true -MSSIO_36_OUT_DRIVE 8 -MSSIO_36_RES_PULL UP -MSSIO_36_SCHMITT_TRIGGER false -MSSIO_37_ATP_EN false -MSSIO_37_CLAMP_DIODE false -MSSIO_37_LPMD_IBUF false -MSSIO_37_LPMD_OBUF false -MSSIO_37_LP_PERSIST false -MSSIO_37_MD_IBUF true -MSSIO_37_OUT_DRIVE 8 -MSSIO_37_RES_PULL UP -MSSIO_37_SCHMITT_TRIGGER false -MSSIO_3_ATP_EN false -MSSIO_3_CLAMP_DIODE false -MSSIO_3_LPMD_IBUF false -MSSIO_3_LPMD_OBUF false -MSSIO_3_LP_PERSIST false -MSSIO_3_MD_IBUF true -MSSIO_3_OUT_DRIVE 8 -MSSIO_3_RES_PULL UP -MSSIO_3_SCHMITT_TRIGGER false -MSSIO_4_ATP_EN false -MSSIO_4_CLAMP_DIODE false -MSSIO_4_LPMD_IBUF false -MSSIO_4_LPMD_OBUF false -MSSIO_4_LP_PERSIST false -MSSIO_4_MD_IBUF true -MSSIO_4_OUT_DRIVE 8 -MSSIO_4_RES_PULL UP -MSSIO_4_SCHMITT_TRIGGER false -MSSIO_5_ATP_EN false -MSSIO_5_CLAMP_DIODE false -MSSIO_5_LPMD_IBUF false -MSSIO_5_LPMD_OBUF false -MSSIO_5_LP_PERSIST false -MSSIO_5_MD_IBUF true -MSSIO_5_OUT_DRIVE 8 -MSSIO_5_RES_PULL UP -MSSIO_5_SCHMITT_TRIGGER false -MSSIO_6_ATP_EN false -MSSIO_6_CLAMP_DIODE false -MSSIO_6_LPMD_IBUF false -MSSIO_6_LPMD_OBUF false -MSSIO_6_LP_PERSIST false -MSSIO_6_MD_IBUF true -MSSIO_6_OUT_DRIVE 8 -MSSIO_6_RES_PULL UP -MSSIO_6_SCHMITT_TRIGGER false -MSSIO_7_ATP_EN false -MSSIO_7_CLAMP_DIODE false -MSSIO_7_LPMD_IBUF false -MSSIO_7_LPMD_OBUF false -MSSIO_7_LP_PERSIST false -MSSIO_7_MD_IBUF true -MSSIO_7_OUT_DRIVE 8 -MSSIO_7_RES_PULL UP -MSSIO_7_SCHMITT_TRIGGER false -MSSIO_8_ATP_EN false -MSSIO_8_CLAMP_DIODE false -MSSIO_8_LPMD_IBUF false -MSSIO_8_LPMD_OBUF false -MSSIO_8_LP_PERSIST false -MSSIO_8_MD_IBUF true -MSSIO_8_OUT_DRIVE 8 -MSSIO_8_RES_PULL UP -MSSIO_8_SCHMITT_TRIGGER false -MSSIO_9_ATP_EN false -MSSIO_9_CLAMP_DIODE false -MSSIO_9_LPMD_IBUF false -MSSIO_9_LPMD_OBUF false -MSSIO_9_LP_PERSIST false -MSSIO_9_MD_IBUF true -MSSIO_9_OUT_DRIVE 8 -MSSIO_9_RES_PULL UP -MSSIO_9_SCHMITT_TRIGGER false -MSSIO_REFCLK_IOSTD LVDS25 -MSSIO_REFCLK_ODT 100 -MSSIO_REFCLK_PULL_UP false -MSSIO_REFCLK_SCHMITT_TRIGGER false -MSSIO_REFCLK_THEVENIN OFF -MSS_AHB_APB_CLK_DIV 4 -MSS_AXI_CLK_DIV 2 -MSS_CLK_DIV 1 -MSS_PLLOUT_FREQ 600.000 -MSS_PMP_ENABLE false -MSS_REFCLK DEDICATED_IO -PACKAGE FCG1152 -PFSOC_MSS_VERSION 2022.2 -PLL_NW_REFCLK0_FREQ 100 -PLL_NW_REFCLK1_FREQ 125 -PMP_CAN0_CONTEXT_A_EN true -PMP_CAN0_CONTEXT_B_EN false -PMP_CAN1_CONTEXT_A_EN false -PMP_CAN1_CONTEXT_B_EN true -PMP_CRYPTO_CFG_CONTEXT_A_EN true -PMP_CRYPTO_CFG_CONTEXT_B_EN false -PMP_CRYPTO_MEM_CONTEXT_A_EN true -PMP_CRYPTO_MEM_CONTEXT_B_EN false -PMP_EMMC_CONTEXT_A_EN true -PMP_EMMC_CONTEXT_B_EN false -PMP_GEM0_CONTEXT_A_EN true -PMP_GEM0_CONTEXT_B_EN false -PMP_GEM1_CONTEXT_A_EN false -PMP_GEM1_CONTEXT_B_EN true -PMP_GPIO0_CONTEXT_A_EN true -PMP_GPIO0_CONTEXT_B_EN false -PMP_GPIO1_CONTEXT_A_EN false -PMP_GPIO1_CONTEXT_B_EN true -PMP_GPIO2_CONTEXT_A_EN true -PMP_GPIO2_CONTEXT_B_EN false -PMP_I2C0_CONTEXT_A_EN true -PMP_I2C0_CONTEXT_B_EN false -PMP_I2C1_CONTEXT_A_EN false -PMP_I2C1_CONTEXT_B_EN true -PMP_INITIATOR_U54_1_CONTEXT_A_EN true -PMP_INITIATOR_U54_1_CONTEXT_B_EN false -PMP_INITIATOR_U54_2_CONTEXT_A_EN true -PMP_INITIATOR_U54_2_CONTEXT_B_EN false -PMP_INITIATOR_U54_3_CONTEXT_A_EN false -PMP_INITIATOR_U54_3_CONTEXT_B_EN true -PMP_INITIATOR_U54_4_CONTEXT_A_EN false -PMP_INITIATOR_U54_4_CONTEXT_B_EN true -PMP_MMUART1_CONTEXT_A_EN true -PMP_MMUART1_CONTEXT_B_EN false -PMP_MMUART2_CONTEXT_A_EN true -PMP_MMUART2_CONTEXT_B_EN false -PMP_MMUART3_CONTEXT_A_EN false -PMP_MMUART3_CONTEXT_B_EN true -PMP_MMUART4_CONTEXT_A_EN false -PMP_MMUART4_CONTEXT_B_EN true -PMP_QSPI_CONTEXT_A_EN true -PMP_QSPI_CONTEXT_B_EN false -PMP_RTC_CONTEXT_A_EN true -PMP_RTC_CONTEXT_B_EN false -PMP_SPI0_CONTEXT_A_EN true -PMP_SPI0_CONTEXT_B_EN false -PMP_SPI1_CONTEXT_A_EN false -PMP_SPI1_CONTEXT_B_EN true -PMP_USB_CONTEXT_A_EN true -PMP_USB_CONTEXT_B_EN false -QSPI UNUSED -QSPI_CLK UNUSED -QSPI_DATA_3_2 UNUSED -SD MSSIO_B4 -SD_CLE UNUSED -SD_LED UNUSED -SD_LED_IS_INVERTED false -SD_PORTS_DISABLE false -SD_SDIO_SPEED_MODE DDR50 -SD_VOLT_0 UNUSED -SD_VOLT_0_IS_INVERTED false -SD_VOLT_1 UNUSED -SD_VOLT_1_IS_INVERTED false -SD_VOLT_2 UNUSED -SD_VOLT_2_IS_INVERTED false -SD_VOLT_CMD_DIR_IS_INVERTED true -SD_VOLT_DIR_0_IS_INVERTED true -SD_VOLT_DIR_1_3_IS_INVERTED true -SD_VOLT_EN_IS_INVERTED false -SD_VOLT_PORTS MSSIO_B4 -SD_VOLT_SEL_IS_INVERTED true -SGMII_RX0_IOSTD LVDS33 -SGMII_RX0_ODT 100 -SGMII_RX0_PULLMODE NONE -SGMII_RX0_VCM_RANGE MID -SGMII_RX1_IOSTD LVDS33 -SGMII_RX1_ODT 100 -SGMII_RX1_PULLMODE NONE -SGMII_RX1_VCM_RANGE MID -SGMII_TX0_IOSTD LVDS33 -SGMII_TX0_OUT_DRIVE 6 -SGMII_TX0_PULLMODE NONE -SGMII_TX0_SOURCE_TERM 100 -SGMII_TX1_IOSTD LVDS33 -SGMII_TX1_OUT_DRIVE 6 -SGMII_TX1_PULLMODE NONE -SGMII_TX1_SOURCE_TERM 100 -SPEED STD -SPI_0 UNUSED -SPI_0_SPEED_MODE MASTER -SPI_0_SS1 UNUSED -SPI_1 UNUSED -SPI_1_SPEED_MODE MASTER -SPI_1_SS1 UNUSED -USB MSSIO_B2 -USOC_DEBUG_TRACE false -WD_RESETN UNUSED +ALT_MSSIO_0_ATP_EN false +ALT_MSSIO_0_CLAMP_DIODE false +ALT_MSSIO_0_LPMD_IBUF false +ALT_MSSIO_0_LPMD_OBUF false +ALT_MSSIO_0_LP_PERSIST false +ALT_MSSIO_0_MD_IBUF true +ALT_MSSIO_0_OUT_DRIVE 8 +ALT_MSSIO_0_RES_PULL UP +ALT_MSSIO_0_SCHMITT_TRIGGER false +ALT_MSSIO_10_ATP_EN false +ALT_MSSIO_10_CLAMP_DIODE false +ALT_MSSIO_10_LPMD_IBUF false +ALT_MSSIO_10_LPMD_OBUF false +ALT_MSSIO_10_LP_PERSIST false +ALT_MSSIO_10_MD_IBUF true +ALT_MSSIO_10_OUT_DRIVE 8 +ALT_MSSIO_10_RES_PULL UP +ALT_MSSIO_10_SCHMITT_TRIGGER false +ALT_MSSIO_11_ATP_EN false +ALT_MSSIO_11_CLAMP_DIODE false +ALT_MSSIO_11_LPMD_IBUF false +ALT_MSSIO_11_LPMD_OBUF false +ALT_MSSIO_11_LP_PERSIST false +ALT_MSSIO_11_MD_IBUF true +ALT_MSSIO_11_OUT_DRIVE 8 +ALT_MSSIO_11_RES_PULL UP +ALT_MSSIO_11_SCHMITT_TRIGGER false +ALT_MSSIO_12_ATP_EN false +ALT_MSSIO_12_CLAMP_DIODE false +ALT_MSSIO_12_LPMD_IBUF false +ALT_MSSIO_12_LPMD_OBUF false +ALT_MSSIO_12_LP_PERSIST false +ALT_MSSIO_12_MD_IBUF true +ALT_MSSIO_12_OUT_DRIVE 8 +ALT_MSSIO_12_RES_PULL UP +ALT_MSSIO_12_SCHMITT_TRIGGER false +ALT_MSSIO_13_ATP_EN false +ALT_MSSIO_13_CLAMP_DIODE false +ALT_MSSIO_13_LPMD_IBUF false +ALT_MSSIO_13_LPMD_OBUF false +ALT_MSSIO_13_LP_PERSIST false +ALT_MSSIO_13_MD_IBUF true +ALT_MSSIO_13_OUT_DRIVE 8 +ALT_MSSIO_13_RES_PULL UP +ALT_MSSIO_13_SCHMITT_TRIGGER false +ALT_MSSIO_14_ATP_EN false +ALT_MSSIO_14_CLAMP_DIODE false +ALT_MSSIO_14_LPMD_IBUF false +ALT_MSSIO_14_LPMD_OBUF false +ALT_MSSIO_14_LP_PERSIST false +ALT_MSSIO_14_MD_IBUF true +ALT_MSSIO_14_OUT_DRIVE 8 +ALT_MSSIO_14_RES_PULL UP +ALT_MSSIO_14_SCHMITT_TRIGGER false +ALT_MSSIO_15_ATP_EN false +ALT_MSSIO_15_CLAMP_DIODE false +ALT_MSSIO_15_LPMD_IBUF false +ALT_MSSIO_15_LPMD_OBUF false +ALT_MSSIO_15_LP_PERSIST false +ALT_MSSIO_15_MD_IBUF true +ALT_MSSIO_15_OUT_DRIVE 8 +ALT_MSSIO_15_RES_PULL UP +ALT_MSSIO_15_SCHMITT_TRIGGER false +ALT_MSSIO_16_ATP_EN false +ALT_MSSIO_16_CLAMP_DIODE false +ALT_MSSIO_16_LPMD_IBUF false +ALT_MSSIO_16_LPMD_OBUF false +ALT_MSSIO_16_LP_PERSIST false +ALT_MSSIO_16_MD_IBUF true +ALT_MSSIO_16_OUT_DRIVE 8 +ALT_MSSIO_16_RES_PULL UP +ALT_MSSIO_16_SCHMITT_TRIGGER false +ALT_MSSIO_17_ATP_EN false +ALT_MSSIO_17_CLAMP_DIODE false +ALT_MSSIO_17_LPMD_IBUF false +ALT_MSSIO_17_LPMD_OBUF false +ALT_MSSIO_17_LP_PERSIST false +ALT_MSSIO_17_MD_IBUF true +ALT_MSSIO_17_OUT_DRIVE 8 +ALT_MSSIO_17_RES_PULL UP +ALT_MSSIO_17_SCHMITT_TRIGGER false +ALT_MSSIO_18_ATP_EN false +ALT_MSSIO_18_CLAMP_DIODE false +ALT_MSSIO_18_LPMD_IBUF false +ALT_MSSIO_18_LPMD_OBUF false +ALT_MSSIO_18_LP_PERSIST false +ALT_MSSIO_18_MD_IBUF true +ALT_MSSIO_18_OUT_DRIVE 8 +ALT_MSSIO_18_RES_PULL UP +ALT_MSSIO_18_SCHMITT_TRIGGER false +ALT_MSSIO_19_ATP_EN false +ALT_MSSIO_19_CLAMP_DIODE false +ALT_MSSIO_19_LPMD_IBUF false +ALT_MSSIO_19_LPMD_OBUF false +ALT_MSSIO_19_LP_PERSIST false +ALT_MSSIO_19_MD_IBUF true +ALT_MSSIO_19_OUT_DRIVE 8 +ALT_MSSIO_19_RES_PULL UP +ALT_MSSIO_19_SCHMITT_TRIGGER false +ALT_MSSIO_1_ATP_EN false +ALT_MSSIO_1_CLAMP_DIODE false +ALT_MSSIO_1_LPMD_IBUF false +ALT_MSSIO_1_LPMD_OBUF false +ALT_MSSIO_1_LP_PERSIST false +ALT_MSSIO_1_MD_IBUF true +ALT_MSSIO_1_OUT_DRIVE 8 +ALT_MSSIO_1_RES_PULL UP +ALT_MSSIO_1_SCHMITT_TRIGGER false +ALT_MSSIO_20_ATP_EN false +ALT_MSSIO_20_CLAMP_DIODE false +ALT_MSSIO_20_LPMD_IBUF false +ALT_MSSIO_20_LPMD_OBUF false +ALT_MSSIO_20_LP_PERSIST false +ALT_MSSIO_20_MD_IBUF true +ALT_MSSIO_20_OUT_DRIVE 8 +ALT_MSSIO_20_RES_PULL UP +ALT_MSSIO_20_SCHMITT_TRIGGER false +ALT_MSSIO_21_ATP_EN false +ALT_MSSIO_21_CLAMP_DIODE false +ALT_MSSIO_21_LPMD_IBUF false +ALT_MSSIO_21_LPMD_OBUF false +ALT_MSSIO_21_LP_PERSIST false +ALT_MSSIO_21_MD_IBUF true +ALT_MSSIO_21_OUT_DRIVE 8 +ALT_MSSIO_21_RES_PULL UP +ALT_MSSIO_21_SCHMITT_TRIGGER false +ALT_MSSIO_22_ATP_EN false +ALT_MSSIO_22_CLAMP_DIODE false +ALT_MSSIO_22_LPMD_IBUF false +ALT_MSSIO_22_LPMD_OBUF false +ALT_MSSIO_22_LP_PERSIST false +ALT_MSSIO_22_MD_IBUF true +ALT_MSSIO_22_OUT_DRIVE 8 +ALT_MSSIO_22_RES_PULL UP +ALT_MSSIO_22_SCHMITT_TRIGGER false +ALT_MSSIO_23_ATP_EN false +ALT_MSSIO_23_CLAMP_DIODE false +ALT_MSSIO_23_LPMD_IBUF false +ALT_MSSIO_23_LPMD_OBUF false +ALT_MSSIO_23_LP_PERSIST false +ALT_MSSIO_23_MD_IBUF true +ALT_MSSIO_23_OUT_DRIVE 8 +ALT_MSSIO_23_RES_PULL UP +ALT_MSSIO_23_SCHMITT_TRIGGER false +ALT_MSSIO_24_ATP_EN false +ALT_MSSIO_24_CLAMP_DIODE false +ALT_MSSIO_24_LPMD_IBUF false +ALT_MSSIO_24_LPMD_OBUF false +ALT_MSSIO_24_LP_PERSIST false +ALT_MSSIO_24_MD_IBUF true +ALT_MSSIO_24_OUT_DRIVE 8 +ALT_MSSIO_24_RES_PULL UP +ALT_MSSIO_24_SCHMITT_TRIGGER false +ALT_MSSIO_25_ATP_EN false +ALT_MSSIO_25_CLAMP_DIODE false +ALT_MSSIO_25_LPMD_IBUF false +ALT_MSSIO_25_LPMD_OBUF false +ALT_MSSIO_25_LP_PERSIST false +ALT_MSSIO_25_MD_IBUF true +ALT_MSSIO_25_OUT_DRIVE 8 +ALT_MSSIO_25_RES_PULL UP +ALT_MSSIO_25_SCHMITT_TRIGGER false +ALT_MSSIO_26_ATP_EN false +ALT_MSSIO_26_CLAMP_DIODE false +ALT_MSSIO_26_LPMD_IBUF false +ALT_MSSIO_26_LPMD_OBUF false +ALT_MSSIO_26_LP_PERSIST false +ALT_MSSIO_26_MD_IBUF true +ALT_MSSIO_26_OUT_DRIVE 8 +ALT_MSSIO_26_RES_PULL UP +ALT_MSSIO_26_SCHMITT_TRIGGER false +ALT_MSSIO_27_ATP_EN false +ALT_MSSIO_27_CLAMP_DIODE false +ALT_MSSIO_27_LPMD_IBUF false +ALT_MSSIO_27_LPMD_OBUF false +ALT_MSSIO_27_LP_PERSIST false +ALT_MSSIO_27_MD_IBUF true +ALT_MSSIO_27_OUT_DRIVE 8 +ALT_MSSIO_27_RES_PULL UP +ALT_MSSIO_27_SCHMITT_TRIGGER false +ALT_MSSIO_28_ATP_EN false +ALT_MSSIO_28_CLAMP_DIODE false +ALT_MSSIO_28_LPMD_IBUF false +ALT_MSSIO_28_LPMD_OBUF false +ALT_MSSIO_28_LP_PERSIST false +ALT_MSSIO_28_MD_IBUF true +ALT_MSSIO_28_OUT_DRIVE 8 +ALT_MSSIO_28_RES_PULL UP +ALT_MSSIO_28_SCHMITT_TRIGGER false +ALT_MSSIO_29_ATP_EN false +ALT_MSSIO_29_CLAMP_DIODE false +ALT_MSSIO_29_LPMD_IBUF false +ALT_MSSIO_29_LPMD_OBUF false +ALT_MSSIO_29_LP_PERSIST false +ALT_MSSIO_29_MD_IBUF true +ALT_MSSIO_29_OUT_DRIVE 8 +ALT_MSSIO_29_RES_PULL UP +ALT_MSSIO_29_SCHMITT_TRIGGER false +ALT_MSSIO_2_ATP_EN false +ALT_MSSIO_2_CLAMP_DIODE false +ALT_MSSIO_2_LPMD_IBUF false +ALT_MSSIO_2_LPMD_OBUF false +ALT_MSSIO_2_LP_PERSIST false +ALT_MSSIO_2_MD_IBUF true +ALT_MSSIO_2_OUT_DRIVE 8 +ALT_MSSIO_2_RES_PULL UP +ALT_MSSIO_2_SCHMITT_TRIGGER false +ALT_MSSIO_30_ATP_EN false +ALT_MSSIO_30_CLAMP_DIODE false +ALT_MSSIO_30_LPMD_IBUF false +ALT_MSSIO_30_LPMD_OBUF false +ALT_MSSIO_30_LP_PERSIST false +ALT_MSSIO_30_MD_IBUF true +ALT_MSSIO_30_OUT_DRIVE 8 +ALT_MSSIO_30_RES_PULL UP +ALT_MSSIO_30_SCHMITT_TRIGGER false +ALT_MSSIO_31_ATP_EN false +ALT_MSSIO_31_CLAMP_DIODE false +ALT_MSSIO_31_LPMD_IBUF false +ALT_MSSIO_31_LPMD_OBUF false +ALT_MSSIO_31_LP_PERSIST false +ALT_MSSIO_31_MD_IBUF true +ALT_MSSIO_31_OUT_DRIVE 8 +ALT_MSSIO_31_RES_PULL UP +ALT_MSSIO_31_SCHMITT_TRIGGER false +ALT_MSSIO_32_ATP_EN false +ALT_MSSIO_32_CLAMP_DIODE false +ALT_MSSIO_32_LPMD_IBUF false +ALT_MSSIO_32_LPMD_OBUF false +ALT_MSSIO_32_LP_PERSIST false +ALT_MSSIO_32_MD_IBUF true +ALT_MSSIO_32_OUT_DRIVE 8 +ALT_MSSIO_32_RES_PULL UP +ALT_MSSIO_32_SCHMITT_TRIGGER false +ALT_MSSIO_33_ATP_EN false +ALT_MSSIO_33_CLAMP_DIODE false +ALT_MSSIO_33_LPMD_IBUF false +ALT_MSSIO_33_LPMD_OBUF false +ALT_MSSIO_33_LP_PERSIST false +ALT_MSSIO_33_MD_IBUF true +ALT_MSSIO_33_OUT_DRIVE 8 +ALT_MSSIO_33_RES_PULL UP +ALT_MSSIO_33_SCHMITT_TRIGGER false +ALT_MSSIO_34_ATP_EN false +ALT_MSSIO_34_CLAMP_DIODE false +ALT_MSSIO_34_LPMD_IBUF false +ALT_MSSIO_34_LPMD_OBUF false +ALT_MSSIO_34_LP_PERSIST false +ALT_MSSIO_34_MD_IBUF true +ALT_MSSIO_34_OUT_DRIVE 8 +ALT_MSSIO_34_RES_PULL UP +ALT_MSSIO_34_SCHMITT_TRIGGER false +ALT_MSSIO_35_ATP_EN false +ALT_MSSIO_35_CLAMP_DIODE false +ALT_MSSIO_35_LPMD_IBUF false +ALT_MSSIO_35_LPMD_OBUF false +ALT_MSSIO_35_LP_PERSIST false +ALT_MSSIO_35_MD_IBUF true +ALT_MSSIO_35_OUT_DRIVE 8 +ALT_MSSIO_35_RES_PULL UP +ALT_MSSIO_35_SCHMITT_TRIGGER false +ALT_MSSIO_36_ATP_EN false +ALT_MSSIO_36_CLAMP_DIODE false +ALT_MSSIO_36_LPMD_IBUF false +ALT_MSSIO_36_LPMD_OBUF false +ALT_MSSIO_36_LP_PERSIST false +ALT_MSSIO_36_MD_IBUF true +ALT_MSSIO_36_OUT_DRIVE 8 +ALT_MSSIO_36_RES_PULL UP +ALT_MSSIO_36_SCHMITT_TRIGGER false +ALT_MSSIO_37_ATP_EN false +ALT_MSSIO_37_CLAMP_DIODE false +ALT_MSSIO_37_LPMD_IBUF false +ALT_MSSIO_37_LPMD_OBUF false +ALT_MSSIO_37_LP_PERSIST false +ALT_MSSIO_37_MD_IBUF true +ALT_MSSIO_37_OUT_DRIVE 8 +ALT_MSSIO_37_RES_PULL UP +ALT_MSSIO_37_SCHMITT_TRIGGER false +ALT_MSSIO_3_ATP_EN false +ALT_MSSIO_3_CLAMP_DIODE false +ALT_MSSIO_3_LPMD_IBUF false +ALT_MSSIO_3_LPMD_OBUF false +ALT_MSSIO_3_LP_PERSIST false +ALT_MSSIO_3_MD_IBUF true +ALT_MSSIO_3_OUT_DRIVE 8 +ALT_MSSIO_3_RES_PULL UP +ALT_MSSIO_3_SCHMITT_TRIGGER false +ALT_MSSIO_4_ATP_EN false +ALT_MSSIO_4_CLAMP_DIODE false +ALT_MSSIO_4_LPMD_IBUF false +ALT_MSSIO_4_LPMD_OBUF false +ALT_MSSIO_4_LP_PERSIST false +ALT_MSSIO_4_MD_IBUF true +ALT_MSSIO_4_OUT_DRIVE 8 +ALT_MSSIO_4_RES_PULL UP +ALT_MSSIO_4_SCHMITT_TRIGGER false +ALT_MSSIO_5_ATP_EN false +ALT_MSSIO_5_CLAMP_DIODE false +ALT_MSSIO_5_LPMD_IBUF false +ALT_MSSIO_5_LPMD_OBUF false +ALT_MSSIO_5_LP_PERSIST false +ALT_MSSIO_5_MD_IBUF true +ALT_MSSIO_5_OUT_DRIVE 8 +ALT_MSSIO_5_RES_PULL UP +ALT_MSSIO_5_SCHMITT_TRIGGER false +ALT_MSSIO_6_ATP_EN false +ALT_MSSIO_6_CLAMP_DIODE false +ALT_MSSIO_6_LPMD_IBUF false +ALT_MSSIO_6_LPMD_OBUF false +ALT_MSSIO_6_LP_PERSIST false +ALT_MSSIO_6_MD_IBUF true +ALT_MSSIO_6_OUT_DRIVE 8 +ALT_MSSIO_6_RES_PULL UP +ALT_MSSIO_6_SCHMITT_TRIGGER false +ALT_MSSIO_7_ATP_EN false +ALT_MSSIO_7_CLAMP_DIODE false +ALT_MSSIO_7_LPMD_IBUF false +ALT_MSSIO_7_LPMD_OBUF false +ALT_MSSIO_7_LP_PERSIST false +ALT_MSSIO_7_MD_IBUF true +ALT_MSSIO_7_OUT_DRIVE 8 +ALT_MSSIO_7_RES_PULL UP +ALT_MSSIO_7_SCHMITT_TRIGGER false +ALT_MSSIO_8_ATP_EN false +ALT_MSSIO_8_CLAMP_DIODE false +ALT_MSSIO_8_LPMD_IBUF false +ALT_MSSIO_8_LPMD_OBUF false +ALT_MSSIO_8_LP_PERSIST false +ALT_MSSIO_8_MD_IBUF true +ALT_MSSIO_8_OUT_DRIVE 8 +ALT_MSSIO_8_RES_PULL UP +ALT_MSSIO_8_SCHMITT_TRIGGER false +ALT_MSSIO_9_ATP_EN false +ALT_MSSIO_9_CLAMP_DIODE false +ALT_MSSIO_9_LPMD_IBUF false +ALT_MSSIO_9_LPMD_OBUF false +ALT_MSSIO_9_LP_PERSIST false +ALT_MSSIO_9_MD_IBUF true +ALT_MSSIO_9_OUT_DRIVE 8 +ALT_MSSIO_9_RES_PULL UP +ALT_MSSIO_9_SCHMITT_TRIGGER false +BANK2_VOLTAGE 3.3 +BANK4_VOLTAGE 1.8 +BANK5_VOLTAGE 3.3 +CAN_0 UNUSED +CAN_0_TX_EBL_N UNUSED +CAN_1 UNUSED +CAN_1_TX_EBL_N UNUSED +CAN_CLK_FREQ 80 +CAN_CLK_SOURCE MSS_PLL +CORE_UP UNUSED +CRYPTO UNUSED +CRYPTO_DLL_JITTER_TOLERANCE MEDIUM_LOW +CRYPTO_ENABLE_ALARM false +CRYPTO_ENABLE_BUSERROR false +CRYPTO_ENABLE_BUSY true +CRYPTO_ENABLE_COMPLETE false +CRYPTO_ENABLE_DLL_LOCK true +CRYPTO_ENABLE_MESH false +CRYPTO_ENABLE_STREAMING false +CRYPTO_MSS_CLK_FREQ 200 +CRYPTO_USE_EMBEDDED_DLL true +DDR3_ADDRESS_MIRROR false +DDR3_ADDRESS_ORDERING CHIP_ROW_BANK_COL +DDR3_BANK_ADDR_WIDTH 3 +DDR3_BURST_LENGTH 0 +DDR3_CAS_ADDITIVE_LATENCY 0 +DDR3_CAS_LATENCY 5 +DDR3_CAS_WRITE_LATENCY 5 +DDR3_CLOCK_DDR 666 +DDR3_COL_ADDR_WIDTH 11 +DDR3_CONTROLLER_ADD_CMD_DRIVE 34 +DDR3_CONTROLLER_CLK_DRIVE 34 +DDR3_CONTROLLER_DQS_DRIVE 34 +DDR3_CONTROLLER_DQS_ODT 60 +DDR3_CONTROLLER_DQ_DRIVE 34 +DDR3_CONTROLLER_DQ_ODT 120 +DDR3_DM_MODE DM +DDR3_DQDQS_TRAINING_OFFSET 1 +DDR3_ENABLE_ECC false +DDR3_ENABLE_LOOKAHEAD_PRECHARGE_ACTIVATE false +DDR3_MEMORY_FORMAT COMPONENT +DDR3_NB_CLKS 1 +DDR3_NB_RANKS 1 +DDR3_ODT_ENABLE_RD_RNK0_ODT0 false +DDR3_ODT_ENABLE_RD_RNK0_ODT1 false +DDR3_ODT_ENABLE_RD_RNK1_ODT0 false +DDR3_ODT_ENABLE_RD_RNK1_ODT1 false +DDR3_ODT_ENABLE_WR_RNK0_ODT0 false +DDR3_ODT_ENABLE_WR_RNK0_ODT1 false +DDR3_ODT_ENABLE_WR_RNK1_ODT0 false +DDR3_ODT_ENABLE_WR_RNK1_ODT1 false +DDR3_OUTPUT_DRIVE_STRENGTH RZQ6 +DDR3_PARTIAL_ARRAY_SELF_REFRESH FULL +DDR3_READ_BURST_TYPE SEQUENTIAL +DDR3_ROW_ADDR_WIDTH 13 +DDR3_RTT_NOM DISABLED +DDR3_RTT_WR OFF +DDR3_SELF_REFRESH_TEMPERATURE NORMAL +DDR3_TIMING_FAW 40 +DDR3_TIMING_RAS 35 +DDR3_TIMING_RC 47.5 +DDR3_TIMING_RCD 12.5 +DDR3_TIMING_REFI 7.8 +DDR3_TIMING_RFC 110 +DDR3_TIMING_RP 12.5 +DDR3_TIMING_RRD 6.25 +DDR3_TIMING_RTP 8 +DDR3_TIMING_WR 18 +DDR3_TIMING_WTR 4 +DDR3_WIDTH 32 +DDR3_ZQ_CALIB_PERIOD 200 +DDR3_ZQ_CALIB_TYPE 0 +DDR3_ZQ_CAL_INIT_TIME 512 +DDR3_ZQ_CAL_L_TIME 256 +DDR3_ZQ_CAL_S_TIME 64 +DDR4_ADDRESS_MIRROR false +DDR4_ADDRESS_ORDERING CHIP_ROW_BG_BANK_COL +DDR4_AUTO_SELF_REFRESH 3 +DDR4_BANK_ADDR_WIDTH 2 +DDR4_BANK_GROUP_ADDRESS_WIDTH 1 +DDR4_BURST_LENGTH 0 +DDR4_CAS_ADDITIVE_LATENCY 0 +DDR4_CAS_LATENCY 12 +DDR4_CAS_WRITE_LATENCY 11 +DDR4_CA_PARITY_LATENCY_MODE 0 +DDR4_CLOCK_DDR 800 +DDR4_COL_ADDR_WIDTH 10 +DDR4_CONTROLLER_ADD_CMD_DRIVE 34 +DDR4_CONTROLLER_CLK_DRIVE 48 +DDR4_CONTROLLER_DQS_DRIVE 48 +DDR4_CONTROLLER_DQS_ODT 120 +DDR4_CONTROLLER_DQ_DRIVE 48 +DDR4_CONTROLLER_DQ_ODT 120 +DDR4_DM_MODE DM +DDR4_DQDQS_TRAINING_OFFSET 1 +DDR4_ENABLE_ECC false +DDR4_ENABLE_LOOKAHEAD_PRECHARGE_ACTIVATE false +DDR4_ENABLE_PAR_ALERT false +DDR4_GRANULARITY_MODE 0 +DDR4_INTERNAL_VREF_MONITER 0 +DDR4_MEMORY_FORMAT COMPONENT +DDR4_NB_CLKS 1 +DDR4_NB_RANKS 1 +DDR4_ODT_ENABLE_RD_RNK0_ODT0 false +DDR4_ODT_ENABLE_RD_RNK0_ODT1 false +DDR4_ODT_ENABLE_RD_RNK1_ODT0 false +DDR4_ODT_ENABLE_RD_RNK1_ODT1 false +DDR4_ODT_ENABLE_WR_RNK0_ODT0 false +DDR4_ODT_ENABLE_WR_RNK0_ODT1 false +DDR4_ODT_ENABLE_WR_RNK1_ODT0 false +DDR4_ODT_ENABLE_WR_RNK1_ODT1 false +DDR4_OUTPUT_DRIVE_STRENGTH RZQ7 +DDR4_POWERDOWN_INPUT_BUFFER 1 +DDR4_READ_BURST_TYPE SEQUENTIAL +DDR4_READ_PREAMBLE 0 +DDR4_ROW_ADDR_WIDTH 15 +DDR4_RTT_NOM RZQ4 +DDR4_RTT_PARK 0 +DDR4_RTT_WR OFF +DDR4_SELF_REFRESH_ABORT_MODE 0 +DDR4_TEMPERATURE_REFRESH_MODE 0 +DDR4_TEMPERATURE_REFRESH_RANGE NORMAL +DDR4_TIMING_CCD_L 5 +DDR4_TIMING_CCD_S 4 +DDR4_TIMING_FAW 25 +DDR4_TIMING_RAS 35 +DDR4_TIMING_RC 50 +DDR4_TIMING_RCD 15 +DDR4_TIMING_REFI 7.8 +DDR4_TIMING_RFC 160 +DDR4_TIMING_RP 15 +DDR4_TIMING_RRD_L 5 +DDR4_TIMING_RRD_S 4 +DDR4_TIMING_RTP 7.5 +DDR4_TIMING_WR 15 +DDR4_TIMING_WTR_L 6 +DDR4_TIMING_WTR_S 2 +DDR4_VREF_CA 45 +DDR4_VREF_CALIB_ENABLE 1 +DDR4_VREF_CALIB_RANGE 1 +DDR4_VREF_CALIB_VALUE 64.5 +DDR4_VREF_DATA 65 +DDR4_WIDTH 32 +DDR4_WRITE_PREAMBLE 0 +DDR4_ZQ_CALIB_PERIOD 200 +DDR4_ZQ_CALIB_TYPE 0 +DDR4_ZQ_CAL_INIT_TIME 1024 +DDR4_ZQ_CAL_L_TIME 512 +DDR4_ZQ_CAL_S_TIME 128 +DDR_CACHED_32BIT_MEM_SIZE 32 +DDR_CACHED_32BIT_MEM_UNIT MB +DDR_CACHED_32BIT_PHY_OFFSET 0x0000_0000 +DDR_CACHED_64BIT_MEM_SIZE 1888 +DDR_CACHED_64BIT_MEM_UNIT MB +DDR_CACHED_64BIT_PHY_OFFSET 0x200_0000 +DDR_NON_CACHED_32BIT_MEM_SIZE 128 +DDR_NON_CACHED_32BIT_MEM_UNIT MB +DDR_NON_CACHED_32BIT_PHY_OFFSET 0x7800_0000 +DDR_NON_CACHED_64BIT_MEM_SIZE 0 +DDR_NON_CACHED_64BIT_MEM_UNIT GB +DDR_NON_CACHED_64BIT_PHY_OFFSET 0x0000_0000 +DDR_REFCLK DEDICATED_IO +DDR_SDRAM_TYPE LPDDR4 +DIE MPFS250TS +EMMC MSSIO_B4 +EMMC_DATA_7_4 MSSIO_B4 +EMMC_SD_CLK_SOURCE MSS_PLL +EMMC_SD_SDIO_FREQ 200 +EMMC_SD_SWITCHING ENABLED_SD +EMMC_SPEED_MODE HIGH_SPEED_200 +ENABLE_FEEDBACK_PORTS false +EXPOSE_BOOT_STATUS_PORTS false +FF_IN_PROGRESS UNUSED +FIC_0_AXI4_INITIATOR_USED false +FIC_0_AXI4_TARGET_USED false +FIC_0_EMBEDDED_DLL_JITTER_RANGE LOW +FIC_0_EMBEDDED_DLL_USED false +FIC_1_AXI4_INITIATOR_USED false +FIC_1_AXI4_TARGET_USED true +FIC_1_EMBEDDED_DLL_JITTER_RANGE MEDIUM_LOW +FIC_1_EMBEDDED_DLL_USED true +FIC_2_AXI4_TARGET_USED false +FIC_2_EMBEDDED_DLL_JITTER_RANGE LOW +FIC_2_EMBEDDED_DLL_USED false +FIC_3_APB_INITIATOR_USED true +FIC_3_EMBEDDED_DLL_JITTER_RANGE LOW +FIC_3_EMBEDDED_DLL_USED false +FLASH_VALID UNUSED +FREQOUT UNUSED +G5C_IOOUT UNUSED +GPIO_0_0 UNUSED +GPIO_0_0_7_RESET_SOURCE MSS +GPIO_0_0_DIR IN +GPIO_0_1 UNUSED +GPIO_0_10 UNUSED +GPIO_0_10_DIR IN +GPIO_0_11 UNUSED +GPIO_0_11_DIR IN +GPIO_0_12 UNUSED +GPIO_0_12_DIR IN +GPIO_0_13 UNUSED +GPIO_0_13_DIR IN +GPIO_0_1_DIR IN +GPIO_0_2 UNUSED +GPIO_0_2_DIR IN +GPIO_0_3 UNUSED +GPIO_0_3_DIR IN +GPIO_0_4 UNUSED +GPIO_0_4_DIR IN +GPIO_0_5 UNUSED +GPIO_0_5_DIR IN +GPIO_0_6 UNUSED +GPIO_0_6_DIR IN +GPIO_0_7 UNUSED +GPIO_0_7_DIR IN +GPIO_0_8 UNUSED +GPIO_0_8_13_RESET_SOURCE MSS +GPIO_0_8_DIR IN +GPIO_0_9 UNUSED +GPIO_0_9_DIR IN +GPIO_1_0 UNUSED +GPIO_1_0_7_RESET_SOURCE MSS +GPIO_1_0_DIR IN +GPIO_1_1 UNUSED +GPIO_1_10 UNUSED +GPIO_1_10_DIR IN +GPIO_1_11 UNUSED +GPIO_1_11_DIR IN +GPIO_1_12 MSSIO_B2 +GPIO_1_12_DIR OUT +GPIO_1_13 UNUSED +GPIO_1_13_DIR IN +GPIO_1_14 UNUSED +GPIO_1_14_DIR IN +GPIO_1_15 UNUSED +GPIO_1_15_DIR IN +GPIO_1_16 MSSIO_B2 +GPIO_1_16_23_RESET_SOURCE MSS +GPIO_1_16_DIR OUT +GPIO_1_17 UNUSED +GPIO_1_17_DIR IN +GPIO_1_18 UNUSED +GPIO_1_18_DIR IN +GPIO_1_19 UNUSED +GPIO_1_19_DIR IN +GPIO_1_1_DIR IN +GPIO_1_2 UNUSED +GPIO_1_20 MSSIO_B2 +GPIO_1_20_DIR OUT +GPIO_1_21 UNUSED +GPIO_1_21_DIR IN +GPIO_1_22 UNUSED +GPIO_1_22_DIR IN +GPIO_1_23 MSSIO_B2 +GPIO_1_23_DIR OUT +GPIO_1_2_DIR IN +GPIO_1_3 UNUSED +GPIO_1_3_DIR IN +GPIO_1_4 UNUSED +GPIO_1_4_DIR IN +GPIO_1_5 UNUSED +GPIO_1_5_DIR IN +GPIO_1_6 UNUSED +GPIO_1_6_DIR IN +GPIO_1_7 UNUSED +GPIO_1_7_DIR IN +GPIO_1_8 UNUSED +GPIO_1_8_15_RESET_SOURCE MSS +GPIO_1_8_DIR IN +GPIO_1_9 UNUSED +GPIO_1_9_DIR IN +GPIO_2_0 UNUSED +GPIO_2_0_7_RESET_SOURCE MSS +GPIO_2_0_DIR IN +GPIO_2_1 FABRIC +GPIO_2_10 UNUSED +GPIO_2_10_DIR IN +GPIO_2_11 UNUSED +GPIO_2_11_DIR IN +GPIO_2_12 UNUSED +GPIO_2_12_DIR IN +GPIO_2_13 UNUSED +GPIO_2_13_DIR IN +GPIO_2_14 UNUSED +GPIO_2_14_DIR IN +GPIO_2_15 UNUSED +GPIO_2_15_DIR IN +GPIO_2_16 UNUSED +GPIO_2_16_23_RESET_SOURCE MSS +GPIO_2_16_DIR IN +GPIO_2_17 UNUSED +GPIO_2_17_DIR IN +GPIO_2_18 FABRIC +GPIO_2_18_DIR OUT +GPIO_2_19 FABRIC +GPIO_2_19_DIR OUT +GPIO_2_1_DIR OUT +GPIO_2_2 FABRIC +GPIO_2_20 UNUSED +GPIO_2_20_DIR IN +GPIO_2_21 UNUSED +GPIO_2_21_DIR IN +GPIO_2_22 UNUSED +GPIO_2_22_DIR IN +GPIO_2_23 UNUSED +GPIO_2_23_DIR IN +GPIO_2_24 UNUSED +GPIO_2_24_31_RESET_SOURCE MSS +GPIO_2_24_DIR IN +GPIO_2_25 FABRIC +GPIO_2_25_DIR IN +GPIO_2_26 UNUSED +GPIO_2_26_DIR IN +GPIO_2_27 UNUSED +GPIO_2_27_DIR IN +GPIO_2_28 UNUSED +GPIO_2_28_DIR IN +GPIO_2_29 UNUSED +GPIO_2_29_DIR IN +GPIO_2_2_DIR OUT +GPIO_2_3 FABRIC +GPIO_2_30 UNUSED +GPIO_2_30_DIR IN +GPIO_2_31 UNUSED +GPIO_2_31_DIR IN +GPIO_2_3_DIR OUT +GPIO_2_4 FABRIC +GPIO_2_4_DIR OUT +GPIO_2_5 UNUSED +GPIO_2_5_DIR IN +GPIO_2_6 UNUSED +GPIO_2_6_DIR IN +GPIO_2_7 UNUSED +GPIO_2_7_DIR IN +GPIO_2_8 FABRIC +GPIO_2_8_15_RESET_SOURCE MSS +GPIO_2_8_DIR OUT +GPIO_2_9 FABRIC +GPIO_2_9_DIR OUT +GPIO_INTERRUPT_FAB_CR_DATA 0x00000000 +I2C_0 FABRIC +I2C_0_BAUD_RATE_CLOCK FABRIC +I2C_0_SMBUS UNUSED +I2C_0_SPEED_MODE STANDARD +I2C_1 UNUSED +I2C_1_BAUD_RATE_CLOCK UNUSED +I2C_1_SMBUS UNUSED +I2C_1_SPEED_MODE STANDARD +INTERNAL_DEBUG false +INTERRUPT true +IO_REFCLK_FREQ 125 +JTAG_TRACE false +JTAG_TRACE_CONTROL_VIA_FABRIC false +L2CACHE_DMA_WAY0 true +L2CACHE_DMA_WAY1 true +L2CACHE_DMA_WAY10 false +L2CACHE_DMA_WAY11 false +L2CACHE_DMA_WAY12 false +L2CACHE_DMA_WAY13 false +L2CACHE_DMA_WAY14 false +L2CACHE_DMA_WAY15 false +L2CACHE_DMA_WAY2 true +L2CACHE_DMA_WAY3 true +L2CACHE_DMA_WAY4 true +L2CACHE_DMA_WAY5 true +L2CACHE_DMA_WAY6 true +L2CACHE_DMA_WAY7 true +L2CACHE_DMA_WAY8 false +L2CACHE_DMA_WAY9 false +L2CACHE_E51_D_WAY0 true +L2CACHE_E51_D_WAY1 true +L2CACHE_E51_D_WAY10 false +L2CACHE_E51_D_WAY11 false +L2CACHE_E51_D_WAY12 false +L2CACHE_E51_D_WAY13 false +L2CACHE_E51_D_WAY14 false +L2CACHE_E51_D_WAY15 false +L2CACHE_E51_D_WAY2 true +L2CACHE_E51_D_WAY3 true +L2CACHE_E51_D_WAY4 true +L2CACHE_E51_D_WAY5 true +L2CACHE_E51_D_WAY6 true +L2CACHE_E51_D_WAY7 true +L2CACHE_E51_D_WAY8 false +L2CACHE_E51_D_WAY9 false +L2CACHE_E51_I_WAY0 true +L2CACHE_E51_I_WAY1 true +L2CACHE_E51_I_WAY10 false +L2CACHE_E51_I_WAY11 false +L2CACHE_E51_I_WAY12 false +L2CACHE_E51_I_WAY13 false +L2CACHE_E51_I_WAY14 false +L2CACHE_E51_I_WAY15 false +L2CACHE_E51_I_WAY2 true +L2CACHE_E51_I_WAY3 true +L2CACHE_E51_I_WAY4 true +L2CACHE_E51_I_WAY5 true +L2CACHE_E51_I_WAY6 true +L2CACHE_E51_I_WAY7 true +L2CACHE_E51_I_WAY8 false +L2CACHE_E51_I_WAY9 false +L2CACHE_LIM_SIZE 4 +L2CACHE_PORT_0_WAY0 true +L2CACHE_PORT_0_WAY1 true +L2CACHE_PORT_0_WAY10 false +L2CACHE_PORT_0_WAY11 false +L2CACHE_PORT_0_WAY12 false +L2CACHE_PORT_0_WAY13 false +L2CACHE_PORT_0_WAY14 false +L2CACHE_PORT_0_WAY15 false +L2CACHE_PORT_0_WAY2 true +L2CACHE_PORT_0_WAY3 true +L2CACHE_PORT_0_WAY4 true +L2CACHE_PORT_0_WAY5 true +L2CACHE_PORT_0_WAY6 true +L2CACHE_PORT_0_WAY7 true +L2CACHE_PORT_0_WAY8 false +L2CACHE_PORT_0_WAY9 false +L2CACHE_PORT_1_WAY0 true +L2CACHE_PORT_1_WAY1 true +L2CACHE_PORT_1_WAY10 false +L2CACHE_PORT_1_WAY11 false +L2CACHE_PORT_1_WAY12 false +L2CACHE_PORT_1_WAY13 false +L2CACHE_PORT_1_WAY14 false +L2CACHE_PORT_1_WAY15 false +L2CACHE_PORT_1_WAY2 true +L2CACHE_PORT_1_WAY3 true +L2CACHE_PORT_1_WAY4 true +L2CACHE_PORT_1_WAY5 true +L2CACHE_PORT_1_WAY6 true +L2CACHE_PORT_1_WAY7 true +L2CACHE_PORT_1_WAY8 false +L2CACHE_PORT_1_WAY9 false +L2CACHE_PORT_2_WAY0 true +L2CACHE_PORT_2_WAY1 true +L2CACHE_PORT_2_WAY10 false +L2CACHE_PORT_2_WAY11 false +L2CACHE_PORT_2_WAY12 false +L2CACHE_PORT_2_WAY13 false +L2CACHE_PORT_2_WAY14 false +L2CACHE_PORT_2_WAY15 false +L2CACHE_PORT_2_WAY2 true +L2CACHE_PORT_2_WAY3 true +L2CACHE_PORT_2_WAY4 true +L2CACHE_PORT_2_WAY5 true +L2CACHE_PORT_2_WAY6 true +L2CACHE_PORT_2_WAY7 true +L2CACHE_PORT_2_WAY8 false +L2CACHE_PORT_2_WAY9 false +L2CACHE_PORT_3_WAY0 true +L2CACHE_PORT_3_WAY1 true +L2CACHE_PORT_3_WAY10 false +L2CACHE_PORT_3_WAY11 false +L2CACHE_PORT_3_WAY12 false +L2CACHE_PORT_3_WAY13 false +L2CACHE_PORT_3_WAY14 false +L2CACHE_PORT_3_WAY15 false +L2CACHE_PORT_3_WAY2 true +L2CACHE_PORT_3_WAY3 true +L2CACHE_PORT_3_WAY4 true +L2CACHE_PORT_3_WAY5 true +L2CACHE_PORT_3_WAY6 true +L2CACHE_PORT_3_WAY7 true +L2CACHE_PORT_3_WAY8 false +L2CACHE_PORT_3_WAY9 false +L2CACHE_SCRATCH_SIZE 4 +L2CACHE_U54_1_D_WAY0 true +L2CACHE_U54_1_D_WAY1 true +L2CACHE_U54_1_D_WAY10 false +L2CACHE_U54_1_D_WAY11 false +L2CACHE_U54_1_D_WAY12 false +L2CACHE_U54_1_D_WAY13 false +L2CACHE_U54_1_D_WAY14 false +L2CACHE_U54_1_D_WAY15 false +L2CACHE_U54_1_D_WAY2 true +L2CACHE_U54_1_D_WAY3 true +L2CACHE_U54_1_D_WAY4 true +L2CACHE_U54_1_D_WAY5 true +L2CACHE_U54_1_D_WAY6 true +L2CACHE_U54_1_D_WAY7 true +L2CACHE_U54_1_D_WAY8 false +L2CACHE_U54_1_D_WAY9 false +L2CACHE_U54_1_I_WAY0 true +L2CACHE_U54_1_I_WAY1 true +L2CACHE_U54_1_I_WAY10 false +L2CACHE_U54_1_I_WAY11 false +L2CACHE_U54_1_I_WAY12 false +L2CACHE_U54_1_I_WAY13 false +L2CACHE_U54_1_I_WAY14 false +L2CACHE_U54_1_I_WAY15 false +L2CACHE_U54_1_I_WAY2 true +L2CACHE_U54_1_I_WAY3 true +L2CACHE_U54_1_I_WAY4 true +L2CACHE_U54_1_I_WAY5 true +L2CACHE_U54_1_I_WAY6 true +L2CACHE_U54_1_I_WAY7 true +L2CACHE_U54_1_I_WAY8 false +L2CACHE_U54_1_I_WAY9 false +L2CACHE_U54_2_D_WAY0 true +L2CACHE_U54_2_D_WAY1 true +L2CACHE_U54_2_D_WAY10 false +L2CACHE_U54_2_D_WAY11 false +L2CACHE_U54_2_D_WAY12 false +L2CACHE_U54_2_D_WAY13 false +L2CACHE_U54_2_D_WAY14 false +L2CACHE_U54_2_D_WAY15 false +L2CACHE_U54_2_D_WAY2 true +L2CACHE_U54_2_D_WAY3 true +L2CACHE_U54_2_D_WAY4 true +L2CACHE_U54_2_D_WAY5 true +L2CACHE_U54_2_D_WAY6 true +L2CACHE_U54_2_D_WAY7 true +L2CACHE_U54_2_D_WAY8 false +L2CACHE_U54_2_D_WAY9 false +L2CACHE_U54_2_I_WAY0 true +L2CACHE_U54_2_I_WAY1 true +L2CACHE_U54_2_I_WAY10 false +L2CACHE_U54_2_I_WAY11 false +L2CACHE_U54_2_I_WAY12 false +L2CACHE_U54_2_I_WAY13 false +L2CACHE_U54_2_I_WAY14 false +L2CACHE_U54_2_I_WAY15 false +L2CACHE_U54_2_I_WAY2 true +L2CACHE_U54_2_I_WAY3 true +L2CACHE_U54_2_I_WAY4 true +L2CACHE_U54_2_I_WAY5 true +L2CACHE_U54_2_I_WAY6 true +L2CACHE_U54_2_I_WAY7 true +L2CACHE_U54_2_I_WAY8 false +L2CACHE_U54_2_I_WAY9 false +L2CACHE_U54_3_D_WAY0 true +L2CACHE_U54_3_D_WAY1 true +L2CACHE_U54_3_D_WAY10 false +L2CACHE_U54_3_D_WAY11 false +L2CACHE_U54_3_D_WAY12 false +L2CACHE_U54_3_D_WAY13 false +L2CACHE_U54_3_D_WAY14 false +L2CACHE_U54_3_D_WAY15 false +L2CACHE_U54_3_D_WAY2 true +L2CACHE_U54_3_D_WAY3 true +L2CACHE_U54_3_D_WAY4 true +L2CACHE_U54_3_D_WAY5 true +L2CACHE_U54_3_D_WAY6 true +L2CACHE_U54_3_D_WAY7 true +L2CACHE_U54_3_D_WAY8 false +L2CACHE_U54_3_D_WAY9 false +L2CACHE_U54_3_I_WAY0 true +L2CACHE_U54_3_I_WAY1 true +L2CACHE_U54_3_I_WAY10 false +L2CACHE_U54_3_I_WAY11 false +L2CACHE_U54_3_I_WAY12 false +L2CACHE_U54_3_I_WAY13 false +L2CACHE_U54_3_I_WAY14 false +L2CACHE_U54_3_I_WAY15 false +L2CACHE_U54_3_I_WAY2 true +L2CACHE_U54_3_I_WAY3 true +L2CACHE_U54_3_I_WAY4 true +L2CACHE_U54_3_I_WAY5 true +L2CACHE_U54_3_I_WAY6 true +L2CACHE_U54_3_I_WAY7 true +L2CACHE_U54_3_I_WAY8 false +L2CACHE_U54_3_I_WAY9 false +L2CACHE_U54_4_D_WAY0 true +L2CACHE_U54_4_D_WAY1 true +L2CACHE_U54_4_D_WAY10 false +L2CACHE_U54_4_D_WAY11 false +L2CACHE_U54_4_D_WAY12 false +L2CACHE_U54_4_D_WAY13 false +L2CACHE_U54_4_D_WAY14 false +L2CACHE_U54_4_D_WAY15 false +L2CACHE_U54_4_D_WAY2 true +L2CACHE_U54_4_D_WAY3 true +L2CACHE_U54_4_D_WAY4 true +L2CACHE_U54_4_D_WAY5 true +L2CACHE_U54_4_D_WAY6 true +L2CACHE_U54_4_D_WAY7 true +L2CACHE_U54_4_D_WAY8 false +L2CACHE_U54_4_D_WAY9 false +L2CACHE_U54_4_I_WAY0 true +L2CACHE_U54_4_I_WAY1 true +L2CACHE_U54_4_I_WAY10 false +L2CACHE_U54_4_I_WAY11 false +L2CACHE_U54_4_I_WAY12 false +L2CACHE_U54_4_I_WAY13 false +L2CACHE_U54_4_I_WAY14 false +L2CACHE_U54_4_I_WAY15 false +L2CACHE_U54_4_I_WAY2 true +L2CACHE_U54_4_I_WAY3 true +L2CACHE_U54_4_I_WAY4 true +L2CACHE_U54_4_I_WAY5 true +L2CACHE_U54_4_I_WAY6 true +L2CACHE_U54_4_I_WAY7 true +L2CACHE_U54_4_I_WAY8 false +L2CACHE_U54_4_I_WAY9 false +LOCK_DOWN_B2_IOS false +LOCK_DOWN_B4_IOS false +LOCK_DOWN_DDR_IOS false +LOCK_DOWN_SGMII_IOS false +LPDDR3_ADDRESS_ORDERING CHIP_ROW_BANK_COL +LPDDR3_BANK_ADDR_WIDTH 3 +LPDDR3_CLOCK_DDR 666 +LPDDR3_COL_ADDR_WIDTH 11 +LPDDR3_CONTROLLER_ADD_CMD_DRIVE 40 +LPDDR3_CONTROLLER_CLK_DRIVE 48 +LPDDR3_CONTROLLER_DQS_DRIVE 48 +LPDDR3_CONTROLLER_DQS_ODT 120 +LPDDR3_CONTROLLER_DQ_DRIVE 48 +LPDDR3_CONTROLLER_DQ_ODT 120 +LPDDR3_DATA_LATENCY RL10WL6 +LPDDR3_DM_MODE DM +LPDDR3_DQDQS_TRAINING_OFFSET 1 +LPDDR3_DQ_ODT DISABLE +LPDDR3_ENABLE_ECC false +LPDDR3_ENABLE_LOOKAHEAD_PRECHARGE_ACTIVATE false +LPDDR3_MEMORY_FORMAT COMPONENT +LPDDR3_ODT_ENABLE_RD_RNK0_ODT0 false +LPDDR3_ODT_ENABLE_WR_RNK0_ODT0 false +LPDDR3_OUTPUT_DRIVE_STRENGTH PDPU34P3 +LPDDR3_POWERDOWN_ODT 0 +LPDDR3_ROW_ADDR_WIDTH 14 +LPDDR3_TIMING_FAW 50 +LPDDR3_TIMING_MRR 4 +LPDDR3_TIMING_MRW 10 +LPDDR3_TIMING_RAS 42 +LPDDR3_TIMING_RC 57 +LPDDR3_TIMING_RCD 15 +LPDDR3_TIMING_REFI 3.9 +LPDDR3_TIMING_RFC 130 +LPDDR3_TIMING_RP 15 +LPDDR3_TIMING_RRD 10 +LPDDR3_TIMING_RTP 8 +LPDDR3_TIMING_WR 18 +LPDDR3_TIMING_WTR 4 +LPDDR3_WIDTH 32 +LPDDR3_ZQ_CALIB_PERIOD 200 +LPDDR3_ZQ_CALIB_TYPE 0 +LPDDR3_ZQ_CAL_INIT_TIME 1 +LPDDR3_ZQ_CAL_L_TIME 360 +LPDDR3_ZQ_CAL_R_TIME 50 +LPDDR3_ZQ_CAL_S_TIME 90 +LPDDR4_ADDRESS_ORDERING CHIP_ROW_BANK_COL +LPDDR4_BANK_ADDR_WIDTH 3 +LPDDR4_CA_ODT RZQ4 +LPDDR4_CLOCK_DDR 800 +LPDDR4_COL_ADDR_WIDTH 10 +LPDDR4_CONTROLLER_ADD_CMD_DRIVE 34 +LPDDR4_CONTROLLER_CLK_DRIVE 34 +LPDDR4_CONTROLLER_DQS_DRIVE 40 +LPDDR4_CONTROLLER_DQS_ODT 40 +LPDDR4_CONTROLLER_DQ_DRIVE 40 +LPDDR4_CONTROLLER_DQ_ODT 80 +LPDDR4_DM_MODE DM +LPDDR4_DQDQS_TRAINING_OFFSET 6 +LPDDR4_DQ_ODT RZQ2 +LPDDR4_DRIVE_STRENGTH RZQ6 +LPDDR4_ENABLE_ECC false +LPDDR4_ENABLE_LOOKAHEAD_PRECHARGE_ACTIVATE false +LPDDR4_MEMORY_FORMAT COMPONENT +LPDDR4_ODTE_CA 0 +LPDDR4_ODTE_CK 0 +LPDDR4_ODTE_CS 0 +LPDDR4_PULLUP_CAL VDDQ2P5 +LPDDR4_RD_POSTAMBLE CK0P5 +LPDDR4_RD_PREAMBLE STATIC +LPDDR4_READ_LATENCY RL14 +LPDDR4_ROW_ADDR_WIDTH 16 +LPDDR4_SELF_REFRESH_ABORT_MODE 0 +LPDDR4_SOC_ODT RZQ6 +LPDDR4_TIMING_FAW 40 +LPDDR4_TIMING_MRR 8 +LPDDR4_TIMING_MRW 10 +LPDDR4_TIMING_RAS 42 +LPDDR4_TIMING_RC 63 +LPDDR4_TIMING_RCD 18 +LPDDR4_TIMING_REFI 3.905 +LPDDR4_TIMING_RFC 380 +LPDDR4_TIMING_RP 21 +LPDDR4_TIMING_RRD 10 +LPDDR4_TIMING_RTP 10 +LPDDR4_TIMING_WR 18 +LPDDR4_TIMING_WTR 8 +LPDDR4_VREF_CA 50 +LPDDR4_VREF_CALIB_ENABLE 1 +LPDDR4_VREF_CALIB_RANGE 1 +LPDDR4_VREF_CALIB_VALUE 31.2 +LPDDR4_VREF_DATA 15 +LPDDR4_WIDTH 32 +LPDDR4_WRITE_LATENCY WL8 +LPDDR4_WR_POSTAMBLE CK0P5 +LPDDR4_ZQ_CALIB_PERIOD 200 +LPDDR4_ZQ_CAL_LATCH_TIME 30 +LPDDR4_ZQ_CAL_R_TIME 50 +LPDDR4_ZQ_CAL_TIME 1 +LP_STATE UNUSED +M2F_MONITOR UNUSED +MAC_0 SGMII_IO_B5 +MAC_0_MANAGEMENT MSSIO_B2_B +MAC_0_OTHER UNUSED +MAC_0_TSU UNUSED +MAC_1 SGMII_IO_B5 +MAC_1_MANAGEMENT UNUSED +MAC_1_OTHER UNUSED +MAC_1_TSU UNUSED +MAC_SGMII_REFCLK DEDICATED_IO +MAC_TSU_REFCLK DEDICATED_IO +MMUART_0 FABRIC +MMUART_0_MODE ASYNCHRONOUS +MMUART_0_MODEM UNUSED +MMUART_0_OTHER UNUSED +MMUART_1 FABRIC +MMUART_1_MODE ASYNCHRONOUS +MMUART_1_MODEM UNUSED +MMUART_1_OTHER UNUSED +MMUART_2 UNUSED +MMUART_3 UNUSED +MMUART_4 UNUSED +MODULE_NAME MSS_VIDEO_KIT +MSSIO_0_ATP_EN false +MSSIO_0_CLAMP_DIODE false +MSSIO_0_LPMD_IBUF false +MSSIO_0_LPMD_OBUF false +MSSIO_0_LP_PERSIST false +MSSIO_0_MD_IBUF true +MSSIO_0_OUT_DRIVE 8 +MSSIO_0_RES_PULL UP +MSSIO_0_SCHMITT_TRIGGER false +MSSIO_10_ATP_EN false +MSSIO_10_CLAMP_DIODE false +MSSIO_10_LPMD_IBUF false +MSSIO_10_LPMD_OBUF false +MSSIO_10_LP_PERSIST false +MSSIO_10_MD_IBUF true +MSSIO_10_OUT_DRIVE 8 +MSSIO_10_RES_PULL UP +MSSIO_10_SCHMITT_TRIGGER false +MSSIO_11_ATP_EN false +MSSIO_11_CLAMP_DIODE false +MSSIO_11_LPMD_IBUF false +MSSIO_11_LPMD_OBUF false +MSSIO_11_LP_PERSIST false +MSSIO_11_MD_IBUF true +MSSIO_11_OUT_DRIVE 8 +MSSIO_11_RES_PULL UP +MSSIO_11_SCHMITT_TRIGGER false +MSSIO_12_ATP_EN false +MSSIO_12_CLAMP_DIODE false +MSSIO_12_LPMD_IBUF false +MSSIO_12_LPMD_OBUF false +MSSIO_12_LP_PERSIST false +MSSIO_12_MD_IBUF true +MSSIO_12_OUT_DRIVE 8 +MSSIO_12_RES_PULL UP +MSSIO_12_SCHMITT_TRIGGER false +MSSIO_13_ATP_EN false +MSSIO_13_CLAMP_DIODE false +MSSIO_13_LPMD_IBUF false +MSSIO_13_LPMD_OBUF false +MSSIO_13_LP_PERSIST false +MSSIO_13_MD_IBUF true +MSSIO_13_OUT_DRIVE 8 +MSSIO_13_RES_PULL UP +MSSIO_13_SCHMITT_TRIGGER false +MSSIO_14_ATP_EN false +MSSIO_14_CLAMP_DIODE false +MSSIO_14_LPMD_IBUF false +MSSIO_14_LPMD_OBUF false +MSSIO_14_LP_PERSIST false +MSSIO_14_MD_IBUF true +MSSIO_14_OUT_DRIVE 8 +MSSIO_14_RES_PULL UP +MSSIO_14_SCHMITT_TRIGGER false +MSSIO_15_ATP_EN false +MSSIO_15_CLAMP_DIODE false +MSSIO_15_LPMD_IBUF false +MSSIO_15_LPMD_OBUF false +MSSIO_15_LP_PERSIST false +MSSIO_15_MD_IBUF true +MSSIO_15_OUT_DRIVE 8 +MSSIO_15_RES_PULL UP +MSSIO_15_SCHMITT_TRIGGER false +MSSIO_16_ATP_EN false +MSSIO_16_CLAMP_DIODE false +MSSIO_16_LPMD_IBUF false +MSSIO_16_LPMD_OBUF false +MSSIO_16_LP_PERSIST false +MSSIO_16_MD_IBUF true +MSSIO_16_OUT_DRIVE 8 +MSSIO_16_RES_PULL UP +MSSIO_16_SCHMITT_TRIGGER false +MSSIO_17_ATP_EN false +MSSIO_17_CLAMP_DIODE false +MSSIO_17_LPMD_IBUF false +MSSIO_17_LPMD_OBUF false +MSSIO_17_LP_PERSIST false +MSSIO_17_MD_IBUF true +MSSIO_17_OUT_DRIVE 8 +MSSIO_17_RES_PULL UP +MSSIO_17_SCHMITT_TRIGGER false +MSSIO_18_ATP_EN false +MSSIO_18_CLAMP_DIODE false +MSSIO_18_LPMD_IBUF false +MSSIO_18_LPMD_OBUF false +MSSIO_18_LP_PERSIST false +MSSIO_18_MD_IBUF true +MSSIO_18_OUT_DRIVE 8 +MSSIO_18_RES_PULL UP +MSSIO_18_SCHMITT_TRIGGER false +MSSIO_19_ATP_EN false +MSSIO_19_CLAMP_DIODE false +MSSIO_19_LPMD_IBUF false +MSSIO_19_LPMD_OBUF false +MSSIO_19_LP_PERSIST false +MSSIO_19_MD_IBUF true +MSSIO_19_OUT_DRIVE 8 +MSSIO_19_RES_PULL UP +MSSIO_19_SCHMITT_TRIGGER false +MSSIO_1_ATP_EN false +MSSIO_1_CLAMP_DIODE false +MSSIO_1_LPMD_IBUF false +MSSIO_1_LPMD_OBUF false +MSSIO_1_LP_PERSIST false +MSSIO_1_MD_IBUF true +MSSIO_1_OUT_DRIVE 8 +MSSIO_1_RES_PULL UP +MSSIO_1_SCHMITT_TRIGGER false +MSSIO_20_ATP_EN false +MSSIO_20_CLAMP_DIODE false +MSSIO_20_LPMD_IBUF false +MSSIO_20_LPMD_OBUF false +MSSIO_20_LP_PERSIST false +MSSIO_20_MD_IBUF true +MSSIO_20_OUT_DRIVE 8 +MSSIO_20_RES_PULL UP +MSSIO_20_SCHMITT_TRIGGER false +MSSIO_21_ATP_EN false +MSSIO_21_CLAMP_DIODE false +MSSIO_21_LPMD_IBUF false +MSSIO_21_LPMD_OBUF false +MSSIO_21_LP_PERSIST false +MSSIO_21_MD_IBUF true +MSSIO_21_OUT_DRIVE 8 +MSSIO_21_RES_PULL UP +MSSIO_21_SCHMITT_TRIGGER false +MSSIO_22_ATP_EN false +MSSIO_22_CLAMP_DIODE false +MSSIO_22_LPMD_IBUF false +MSSIO_22_LPMD_OBUF false +MSSIO_22_LP_PERSIST false +MSSIO_22_MD_IBUF true +MSSIO_22_OUT_DRIVE 8 +MSSIO_22_RES_PULL UP +MSSIO_22_SCHMITT_TRIGGER false +MSSIO_23_ATP_EN false +MSSIO_23_CLAMP_DIODE false +MSSIO_23_LPMD_IBUF false +MSSIO_23_LPMD_OBUF false +MSSIO_23_LP_PERSIST false +MSSIO_23_MD_IBUF true +MSSIO_23_OUT_DRIVE 8 +MSSIO_23_RES_PULL UP +MSSIO_23_SCHMITT_TRIGGER false +MSSIO_24_ATP_EN false +MSSIO_24_CLAMP_DIODE false +MSSIO_24_LPMD_IBUF false +MSSIO_24_LPMD_OBUF false +MSSIO_24_LP_PERSIST false +MSSIO_24_MD_IBUF true +MSSIO_24_OUT_DRIVE 8 +MSSIO_24_RES_PULL UP +MSSIO_24_SCHMITT_TRIGGER false +MSSIO_25_ATP_EN false +MSSIO_25_CLAMP_DIODE false +MSSIO_25_LPMD_IBUF false +MSSIO_25_LPMD_OBUF false +MSSIO_25_LP_PERSIST false +MSSIO_25_MD_IBUF true +MSSIO_25_OUT_DRIVE 8 +MSSIO_25_RES_PULL UP +MSSIO_25_SCHMITT_TRIGGER false +MSSIO_26_ATP_EN false +MSSIO_26_CLAMP_DIODE false +MSSIO_26_LPMD_IBUF false +MSSIO_26_LPMD_OBUF false +MSSIO_26_LP_PERSIST false +MSSIO_26_MD_IBUF true +MSSIO_26_OUT_DRIVE 8 +MSSIO_26_RES_PULL UP +MSSIO_26_SCHMITT_TRIGGER false +MSSIO_27_ATP_EN false +MSSIO_27_CLAMP_DIODE false +MSSIO_27_LPMD_IBUF false +MSSIO_27_LPMD_OBUF false +MSSIO_27_LP_PERSIST false +MSSIO_27_MD_IBUF true +MSSIO_27_OUT_DRIVE 8 +MSSIO_27_RES_PULL UP +MSSIO_27_SCHMITT_TRIGGER false +MSSIO_28_ATP_EN false +MSSIO_28_CLAMP_DIODE false +MSSIO_28_LPMD_IBUF false +MSSIO_28_LPMD_OBUF false +MSSIO_28_LP_PERSIST false +MSSIO_28_MD_IBUF true +MSSIO_28_OUT_DRIVE 8 +MSSIO_28_RES_PULL UP +MSSIO_28_SCHMITT_TRIGGER false +MSSIO_29_ATP_EN false +MSSIO_29_CLAMP_DIODE false +MSSIO_29_LPMD_IBUF false +MSSIO_29_LPMD_OBUF false +MSSIO_29_LP_PERSIST false +MSSIO_29_MD_IBUF true +MSSIO_29_OUT_DRIVE 8 +MSSIO_29_RES_PULL UP +MSSIO_29_SCHMITT_TRIGGER false +MSSIO_2_ATP_EN false +MSSIO_2_CLAMP_DIODE false +MSSIO_2_LPMD_IBUF false +MSSIO_2_LPMD_OBUF false +MSSIO_2_LP_PERSIST false +MSSIO_2_MD_IBUF true +MSSIO_2_OUT_DRIVE 8 +MSSIO_2_RES_PULL UP +MSSIO_2_SCHMITT_TRIGGER false +MSSIO_30_ATP_EN false +MSSIO_30_CLAMP_DIODE false +MSSIO_30_LPMD_IBUF false +MSSIO_30_LPMD_OBUF false +MSSIO_30_LP_PERSIST false +MSSIO_30_MD_IBUF true +MSSIO_30_OUT_DRIVE 8 +MSSIO_30_RES_PULL UP +MSSIO_30_SCHMITT_TRIGGER false +MSSIO_31_ATP_EN false +MSSIO_31_CLAMP_DIODE false +MSSIO_31_LPMD_IBUF false +MSSIO_31_LPMD_OBUF false +MSSIO_31_LP_PERSIST false +MSSIO_31_MD_IBUF true +MSSIO_31_OUT_DRIVE 8 +MSSIO_31_RES_PULL UP +MSSIO_31_SCHMITT_TRIGGER false +MSSIO_32_ATP_EN false +MSSIO_32_CLAMP_DIODE false +MSSIO_32_LPMD_IBUF false +MSSIO_32_LPMD_OBUF false +MSSIO_32_LP_PERSIST false +MSSIO_32_MD_IBUF true +MSSIO_32_OUT_DRIVE 8 +MSSIO_32_RES_PULL UP +MSSIO_32_SCHMITT_TRIGGER false +MSSIO_33_ATP_EN false +MSSIO_33_CLAMP_DIODE false +MSSIO_33_LPMD_IBUF false +MSSIO_33_LPMD_OBUF false +MSSIO_33_LP_PERSIST false +MSSIO_33_MD_IBUF true +MSSIO_33_OUT_DRIVE 8 +MSSIO_33_RES_PULL UP +MSSIO_33_SCHMITT_TRIGGER false +MSSIO_34_ATP_EN false +MSSIO_34_CLAMP_DIODE false +MSSIO_34_LPMD_IBUF false +MSSIO_34_LPMD_OBUF false +MSSIO_34_LP_PERSIST false +MSSIO_34_MD_IBUF true +MSSIO_34_OUT_DRIVE 8 +MSSIO_34_RES_PULL UP +MSSIO_34_SCHMITT_TRIGGER false +MSSIO_35_ATP_EN false +MSSIO_35_CLAMP_DIODE false +MSSIO_35_LPMD_IBUF false +MSSIO_35_LPMD_OBUF false +MSSIO_35_LP_PERSIST false +MSSIO_35_MD_IBUF true +MSSIO_35_OUT_DRIVE 8 +MSSIO_35_RES_PULL UP +MSSIO_35_SCHMITT_TRIGGER false +MSSIO_36_ATP_EN false +MSSIO_36_CLAMP_DIODE false +MSSIO_36_LPMD_IBUF false +MSSIO_36_LPMD_OBUF false +MSSIO_36_LP_PERSIST false +MSSIO_36_MD_IBUF true +MSSIO_36_OUT_DRIVE 8 +MSSIO_36_RES_PULL UP +MSSIO_36_SCHMITT_TRIGGER false +MSSIO_37_ATP_EN false +MSSIO_37_CLAMP_DIODE false +MSSIO_37_LPMD_IBUF false +MSSIO_37_LPMD_OBUF false +MSSIO_37_LP_PERSIST false +MSSIO_37_MD_IBUF true +MSSIO_37_OUT_DRIVE 8 +MSSIO_37_RES_PULL UP +MSSIO_37_SCHMITT_TRIGGER false +MSSIO_3_ATP_EN false +MSSIO_3_CLAMP_DIODE false +MSSIO_3_LPMD_IBUF false +MSSIO_3_LPMD_OBUF false +MSSIO_3_LP_PERSIST false +MSSIO_3_MD_IBUF true +MSSIO_3_OUT_DRIVE 8 +MSSIO_3_RES_PULL UP +MSSIO_3_SCHMITT_TRIGGER false +MSSIO_4_ATP_EN false +MSSIO_4_CLAMP_DIODE false +MSSIO_4_LPMD_IBUF false +MSSIO_4_LPMD_OBUF false +MSSIO_4_LP_PERSIST false +MSSIO_4_MD_IBUF true +MSSIO_4_OUT_DRIVE 8 +MSSIO_4_RES_PULL UP +MSSIO_4_SCHMITT_TRIGGER false +MSSIO_5_ATP_EN false +MSSIO_5_CLAMP_DIODE false +MSSIO_5_LPMD_IBUF false +MSSIO_5_LPMD_OBUF false +MSSIO_5_LP_PERSIST false +MSSIO_5_MD_IBUF true +MSSIO_5_OUT_DRIVE 8 +MSSIO_5_RES_PULL UP +MSSIO_5_SCHMITT_TRIGGER false +MSSIO_6_ATP_EN false +MSSIO_6_CLAMP_DIODE false +MSSIO_6_LPMD_IBUF false +MSSIO_6_LPMD_OBUF false +MSSIO_6_LP_PERSIST false +MSSIO_6_MD_IBUF true +MSSIO_6_OUT_DRIVE 8 +MSSIO_6_RES_PULL UP +MSSIO_6_SCHMITT_TRIGGER false +MSSIO_7_ATP_EN false +MSSIO_7_CLAMP_DIODE false +MSSIO_7_LPMD_IBUF false +MSSIO_7_LPMD_OBUF false +MSSIO_7_LP_PERSIST false +MSSIO_7_MD_IBUF true +MSSIO_7_OUT_DRIVE 8 +MSSIO_7_RES_PULL UP +MSSIO_7_SCHMITT_TRIGGER false +MSSIO_8_ATP_EN false +MSSIO_8_CLAMP_DIODE false +MSSIO_8_LPMD_IBUF false +MSSIO_8_LPMD_OBUF false +MSSIO_8_LP_PERSIST false +MSSIO_8_MD_IBUF true +MSSIO_8_OUT_DRIVE 8 +MSSIO_8_RES_PULL UP +MSSIO_8_SCHMITT_TRIGGER false +MSSIO_9_ATP_EN false +MSSIO_9_CLAMP_DIODE false +MSSIO_9_LPMD_IBUF false +MSSIO_9_LPMD_OBUF false +MSSIO_9_LP_PERSIST false +MSSIO_9_MD_IBUF true +MSSIO_9_OUT_DRIVE 8 +MSSIO_9_RES_PULL UP +MSSIO_9_SCHMITT_TRIGGER false +MSSIO_REFCLK_IOSTD LVDS25 +MSSIO_REFCLK_ODT 100 +MSSIO_REFCLK_PULL_UP false +MSSIO_REFCLK_SCHMITT_TRIGGER false +MSSIO_REFCLK_THEVENIN OFF +MSS_AHB_APB_CLK_DIV 4 +MSS_AXI_CLK_DIV 2 +MSS_CLK_DIV 1 +MSS_MANUAL_DDR_PHY_OFFSET_ENABLE false +MSS_PLLOUT_FREQ 600.000 +MSS_PMP_ENABLE false +MSS_REFCLK DEDICATED_IO +PACKAGE FCG1152 +PFSOC_MSS_VERSION 2022.3 +PLL_NW_REFCLK0_FREQ 100 +PLL_NW_REFCLK1_FREQ 125 +PMP_CAN0_CONTEXT_A_EN true +PMP_CAN0_CONTEXT_B_EN false +PMP_CAN1_CONTEXT_A_EN false +PMP_CAN1_CONTEXT_B_EN true +PMP_CRYPTO_CFG_CONTEXT_A_EN true +PMP_CRYPTO_CFG_CONTEXT_B_EN false +PMP_CRYPTO_MEM_CONTEXT_A_EN true +PMP_CRYPTO_MEM_CONTEXT_B_EN false +PMP_EMMC_CONTEXT_A_EN true +PMP_EMMC_CONTEXT_B_EN false +PMP_GEM0_CONTEXT_A_EN true +PMP_GEM0_CONTEXT_B_EN false +PMP_GEM1_CONTEXT_A_EN false +PMP_GEM1_CONTEXT_B_EN true +PMP_GPIO0_CONTEXT_A_EN true +PMP_GPIO0_CONTEXT_B_EN false +PMP_GPIO1_CONTEXT_A_EN false +PMP_GPIO1_CONTEXT_B_EN true +PMP_GPIO2_CONTEXT_A_EN true +PMP_GPIO2_CONTEXT_B_EN false +PMP_I2C0_CONTEXT_A_EN true +PMP_I2C0_CONTEXT_B_EN false +PMP_I2C1_CONTEXT_A_EN false +PMP_I2C1_CONTEXT_B_EN true +PMP_INITIATOR_U54_1_CONTEXT_A_EN true +PMP_INITIATOR_U54_1_CONTEXT_B_EN false +PMP_INITIATOR_U54_2_CONTEXT_A_EN true +PMP_INITIATOR_U54_2_CONTEXT_B_EN false +PMP_INITIATOR_U54_3_CONTEXT_A_EN false +PMP_INITIATOR_U54_3_CONTEXT_B_EN true +PMP_INITIATOR_U54_4_CONTEXT_A_EN false +PMP_INITIATOR_U54_4_CONTEXT_B_EN true +PMP_MMUART1_CONTEXT_A_EN true +PMP_MMUART1_CONTEXT_B_EN false +PMP_MMUART2_CONTEXT_A_EN true +PMP_MMUART2_CONTEXT_B_EN false +PMP_MMUART3_CONTEXT_A_EN false +PMP_MMUART3_CONTEXT_B_EN true +PMP_MMUART4_CONTEXT_A_EN false +PMP_MMUART4_CONTEXT_B_EN true +PMP_QSPI_CONTEXT_A_EN true +PMP_QSPI_CONTEXT_B_EN false +PMP_RTC_CONTEXT_A_EN true +PMP_RTC_CONTEXT_B_EN false +PMP_SPI0_CONTEXT_A_EN true +PMP_SPI0_CONTEXT_B_EN false +PMP_SPI1_CONTEXT_A_EN false +PMP_SPI1_CONTEXT_B_EN true +PMP_USB_CONTEXT_A_EN true +PMP_USB_CONTEXT_B_EN false +QSPI UNUSED +QSPI_CLK UNUSED +QSPI_DATA_3_2 UNUSED +SD MSSIO_B4 +SD_CLE UNUSED +SD_LED UNUSED +SD_LED_IS_INVERTED false +SD_PORTS_DISABLE false +SD_SDIO_SPEED_MODE DDR50 +SD_VOLT_0 UNUSED +SD_VOLT_0_IS_INVERTED false +SD_VOLT_1 UNUSED +SD_VOLT_1_IS_INVERTED false +SD_VOLT_2 UNUSED +SD_VOLT_2_IS_INVERTED false +SD_VOLT_CMD_DIR_IS_INVERTED true +SD_VOLT_DIR_0_IS_INVERTED true +SD_VOLT_DIR_1_3_IS_INVERTED true +SD_VOLT_EN_IS_INVERTED false +SD_VOLT_PORTS MSSIO_B4 +SD_VOLT_SEL_IS_INVERTED true +SGMII_RX0_IOSTD LVDS33 +SGMII_RX0_ODT 100 +SGMII_RX0_PULLMODE NONE +SGMII_RX0_VCM_RANGE MID +SGMII_RX1_IOSTD LVDS33 +SGMII_RX1_ODT 100 +SGMII_RX1_PULLMODE NONE +SGMII_RX1_VCM_RANGE MID +SGMII_TX0_IOSTD LVDS33 +SGMII_TX0_OUT_DRIVE 6 +SGMII_TX0_PULLMODE NONE +SGMII_TX0_SOURCE_TERM 100 +SGMII_TX1_IOSTD LVDS33 +SGMII_TX1_OUT_DRIVE 6 +SGMII_TX1_PULLMODE NONE +SGMII_TX1_SOURCE_TERM 100 +SPEED -1 +SPI_0 UNUSED +SPI_0_SPEED_MODE MASTER +SPI_0_SS1 UNUSED +SPI_1 UNUSED +SPI_1_SPEED_MODE MASTER +SPI_1_SS1 UNUSED +USB MSSIO_B2 +USOC_DEBUG_TRACE false +WD_RESETN UNUSED diff --git a/script_support/additional_configurations/functions.tcl b/script_support/additional_configurations/functions.tcl index 919d5ea..d2bd71a 100644 --- a/script_support/additional_configurations/functions.tcl +++ b/script_support/additional_configurations/functions.tcl @@ -1,70 +1,70 @@ -proc create_config {current_config updated_config} { - set def_config [open $current_config] - set def_config_data [read $def_config] - set data [split $def_config_data "\n"] - close $def_config - - set new_config [open $updated_config w] - foreach line $data { - puts $new_config "$line" - } - puts $new_config "" - close $new_config -} - -proc update_param {config param_to_update value_to_set} { - set config_file [open $config] - set config_file_data [read $config_file] - set config_file_lines [split $config_file_data "\n"] - close $config_file - set config_file [open $config w] - foreach line $config_file_lines { - if { [regexp $param_to_update $line] } { - puts $config_file "$param_to_update$value_to_set" - puts $line - } else { - puts $config_file "$line" - } - } - close $config_file -} - -proc create_eNVM_config {config client} { - set envm_config [open $config w] - - puts $envm_config "set_plain_text_client \\" - puts $envm_config "-client_name {BOOT_MODE_1_ENVM_CLIENT} \\" - puts $envm_config "-number_of_bytes 117248 \\" - puts $envm_config "-content_type {MEMORY_FILE} \\" - puts $envm_config "-content_file_format {Intel-Hex} \\" - puts $envm_config "-content_file {$client} \\" - puts $envm_config "-mem_file_base_address {0x20220000} \\" - puts $envm_config "-start_page 0 \\" - puts $envm_config "-use_for_simulation 0 \\" - puts $envm_config "-reprogram 1 \\" - puts $envm_config "-use_as_rom 0 \\" - puts $envm_config "-fabric_access_read 1 \\" - puts $envm_config "-fabric_access_write 0 \\" - puts $envm_config "-mss_access_read 1 \\" - puts $envm_config "-mss_access_write 0" - - close $envm_config -} - -proc export_fpe_job {name directory components} { - export_prog_job \ - -job_file_name $name \ - -export_dir $directory \ - -bitstream_file_type {TRUSTED_FACILITY} \ - -bitstream_file_components $components \ - -zeroization_likenew_action 0 \ - -zeroization_unrecoverable_action 0 \ - -program_design 1 \ - -program_spi_flash 0 \ - -include_plaintext_passkey 0 \ - -design_bitstream_format {PPD} \ - -prog_optional_procedures {} \ - -skip_recommended_procedures {} \ - -sanitize_snvm 0 \ - -sanitize_envm 0 -} +proc create_config {current_config updated_config} { + set def_config [open $current_config] + set def_config_data [read $def_config] + set data [split $def_config_data "\n"] + close $def_config + + set new_config [open $updated_config w] + foreach line $data { + puts $new_config "$line" + } + puts $new_config "" + close $new_config +} + +proc update_param {config param_to_update value_to_set} { + set config_file [open $config] + set config_file_data [read $config_file] + set config_file_lines [split $config_file_data "\n"] + close $config_file + set config_file [open $config w] + foreach line $config_file_lines { + if { [regexp $param_to_update $line] } { + puts $config_file "$param_to_update$value_to_set" + puts $line + } else { + puts $config_file "$line" + } + } + close $config_file +} + +proc create_eNVM_config {config client} { + set envm_config [open $config w] + + puts $envm_config "set_plain_text_client \\" + puts $envm_config "-client_name {BOOT_MODE_1_ENVM_CLIENT} \\" + puts $envm_config "-number_of_bytes 117248 \\" + puts $envm_config "-content_type {MEMORY_FILE} \\" + puts $envm_config "-content_file_format {Intel-Hex} \\" + puts $envm_config "-content_file {$client} \\" + puts $envm_config "-mem_file_base_address {0x20220000} \\" + puts $envm_config "-start_page 0 \\" + puts $envm_config "-use_for_simulation 0 \\" + puts $envm_config "-reprogram 1 \\" + puts $envm_config "-use_as_rom 0 \\" + puts $envm_config "-fabric_access_read 1 \\" + puts $envm_config "-fabric_access_write 0 \\" + puts $envm_config "-mss_access_read 1 \\" + puts $envm_config "-mss_access_write 0" + + close $envm_config +} + +proc export_fpe_job {name directory components} { + export_prog_job \ + -job_file_name $name \ + -export_dir $directory \ + -bitstream_file_type {TRUSTED_FACILITY} \ + -bitstream_file_components $components \ + -zeroization_likenew_action 0 \ + -zeroization_unrecoverable_action 0 \ + -program_design 1 \ + -program_spi_flash 0 \ + -include_plaintext_passkey 0 \ + -design_bitstream_format {PPD} \ + -prog_optional_procedures {} \ + -skip_recommended_procedures {} \ + -sanitize_snvm 0 \ + -sanitize_envm 0 +} diff --git a/script_support/components/Bayer_Interpolation_C0.tcl b/script_support/components/Bayer_Interpolation_C0.tcl index d60c7c6..92278a0 100644 --- a/script_support/components/Bayer_Interpolation_C0.tcl +++ b/script_support/components/Bayer_Interpolation_C0.tcl @@ -1,11 +1,11 @@ -# Exporting Component Description of Bayer_Interpolation_C0 to TCL -# Family: PolarFireSoC -# Part Number: MPFS250T_ES-1FCG1152E -# Create and Configure the core component Bayer_Interpolation_C0 -create_and_configure_core -core_vlnv {Microsemi:SolutionCore:Bayer_Interpolation:4.2.0} -component_name {Bayer_Interpolation_C0} -params {\ -"G_CONFIG:0" \ -"G_DATA_WIDTH:8" \ -"G_FORMAT:0" \ -"G_PIXELS:1" \ -"G_RAM_SIZE:2048" } -# Exporting Component Description of Bayer_Interpolation_C0 to TCL done +# Exporting Component Description of Bayer_Interpolation_C0 to TCL +# Family: PolarFireSoC +# Part Number: MPFS250T_ES-1FCG1152E +# Create and Configure the core component Bayer_Interpolation_C0 +create_and_configure_core -core_vlnv {Microsemi:SolutionCore:Bayer_Interpolation:4.4.0} -component_name {Bayer_Interpolation_C0} -params {\ +"G_CONFIG:0" \ +"G_DATA_WIDTH:8" \ +"G_FORMAT:0" \ +"G_PIXELS:1" \ +"G_RAM_SIZE:2048" } +# Exporting Component Description of Bayer_Interpolation_C0 to TCL done diff --git a/script_support/components/CAM_IOD_TIP_TOP.tcl b/script_support/components/CAM_IOD_TIP_TOP.tcl index 6ea9fdf..8b56313 100644 --- a/script_support/components/CAM_IOD_TIP_TOP.tcl +++ b/script_support/components/CAM_IOD_TIP_TOP.tcl @@ -1,223 +1,223 @@ -# Creating SmartDesign CAM_IOD_TIP_TOP -set sd_name {CAM_IOD_TIP_TOP} -create_smartdesign -sd_name ${sd_name} - -# Disable auto promotion of pins of type 'pad' -auto_promote_pad_pins -promote_all 0 - -# Create top level Scalar Ports -sd_create_scalar_port -sd_name ${sd_name} -port_name {ARST_N} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {HS_IO_CLK_PAUSE} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {HS_SEL} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {PLL_LOCK} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {RESTART_TRNG} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {RX_CLK_N} -port_direction {IN} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {RX_CLK_P} -port_direction {IN} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {SKIP_TRNG} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TRAINING_RESETN} -port_direction {IN} - -sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK_TRAIN_DONE} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK_TRAIN_ERROR} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {L0_LP_DATA_N} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {L0_LP_DATA} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {L1_LP_DATA_N} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {L1_LP_DATA} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {L2_LP_DATA_N} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {L2_LP_DATA} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {L3_LP_DATA_N} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {L3_LP_DATA} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {RX_CLK_G} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {training_done_o} -port_direction {OUT} - - -# Create top level Bus Ports -sd_create_bus_port -sd_name ${sd_name} -port_name {RXD_N} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1} -sd_create_bus_port -sd_name ${sd_name} -port_name {RXD} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1} - -sd_create_bus_port -sd_name ${sd_name} -port_name {L0_RXD_DATA} -port_direction {OUT} -port_range {[7:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {L1_RXD_DATA} -port_direction {OUT} -port_range {[7:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {L2_RXD_DATA} -port_direction {OUT} -port_range {[7:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {L3_RXD_DATA} -port_direction {OUT} -port_range {[7:0]} - - -# Add AND2_0 instance -sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0} - - - -# Add AND4_0 instance -sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND4} -instance_name {AND4_0} - - - -# Add CORERESET_PF_C1_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C1} -instance_name {CORERESET_PF_C1_0} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:BANK_x_VDDI_STATUS} -value {VCC} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:BANK_y_VDDI_STATUS} -value {VCC} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:PLL_LOCK} -value {VCC} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:SS_BUSY} -value {GND} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:INIT_DONE} -value {VCC} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:FF_US_RESTORE} -value {GND} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:FPGA_POR_N} -value {VCC} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:PLL_POWERDOWN_B} - - - -# Add CORERXIODBITALIGN_C1_L0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CORERXIODBITALIGN_C1} -instance_name {CORERXIODBITALIGN_C1_L0} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:BIT_ALGN_START} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:BIT_ALGN_OOR} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:BIT_ALGN_HOLD} -value {GND} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:BIT_ALGN_ERR} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:BIT_ALGN_EYE_IN} -value {011} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:DEM_BIT_ALGN_TAPDLY} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:RX_BIT_ALIGN_LEFT_WIN} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:RX_BIT_ALIGN_RGHT_WIN} - - - -# Add CORERXIODBITALIGN_C1_L1 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CORERXIODBITALIGN_C1} -instance_name {CORERXIODBITALIGN_C1_L1} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:BIT_ALGN_START} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:BIT_ALGN_OOR} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:BIT_ALGN_HOLD} -value {GND} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:BIT_ALGN_ERR} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:BIT_ALGN_EYE_IN} -value {011} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:DEM_BIT_ALGN_TAPDLY} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:RX_BIT_ALIGN_LEFT_WIN} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:RX_BIT_ALIGN_RGHT_WIN} - - - -# Add CORERXIODBITALIGN_C1_L2 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CORERXIODBITALIGN_C1} -instance_name {CORERXIODBITALIGN_C1_L2} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:BIT_ALGN_START} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:BIT_ALGN_OOR} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:BIT_ALGN_HOLD} -value {GND} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:BIT_ALGN_ERR} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:BIT_ALGN_EYE_IN} -value {011} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:DEM_BIT_ALGN_TAPDLY} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:RX_BIT_ALIGN_LEFT_WIN} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:RX_BIT_ALIGN_RGHT_WIN} - - - -# Add CORERXIODBITALIGN_C1_L3 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CORERXIODBITALIGN_C1} -instance_name {CORERXIODBITALIGN_C1_L3} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:BIT_ALGN_START} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:BIT_ALGN_OOR} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:BIT_ALGN_HOLD} -value {GND} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:BIT_ALGN_ERR} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:BIT_ALGN_EYE_IN} -value {011} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:DEM_BIT_ALGN_TAPDLY} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:RX_BIT_ALIGN_LEFT_WIN} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:RX_BIT_ALIGN_RGHT_WIN} - - - -# Add PF_IOD_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {PF_IOD_GENERIC_RX_C0} -instance_name {PF_IOD_0} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS} -pin_slices {[0:0]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS} -pin_slices {[1:1]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS} -pin_slices {[2:2]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS} -pin_slices {[3:3]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_EARLY} -pin_slices {[0:0]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_EARLY} -pin_slices {[1:1]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_EARLY} -pin_slices {[2:2]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_EARLY} -pin_slices {[3:3]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_LATE} -pin_slices {[0:0]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_LATE} -pin_slices {[1:1]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_LATE} -pin_slices {[2:2]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_LATE} -pin_slices {[3:3]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_MOVE} -pin_slices {[0:0]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_MOVE} -pin_slices {[1:1]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_MOVE} -pin_slices {[2:2]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_MOVE} -pin_slices {[3:3]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_DIRECTION} -pin_slices {[0:0]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_DIRECTION} -pin_slices {[1:1]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_DIRECTION} -pin_slices {[2:2]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_DIRECTION} -pin_slices {[3:3]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_LOAD} -pin_slices {[0:0]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_LOAD} -pin_slices {[1:1]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_LOAD} -pin_slices {[2:2]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_LOAD} -pin_slices {[3:3]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_OUT_OF_RANGE} -pin_slices {[0:0]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_OUT_OF_RANGE} -pin_slices {[1:1]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_OUT_OF_RANGE} -pin_slices {[2:2]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_OUT_OF_RANGE} -pin_slices {[3:3]} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_IOD_0:EYE_MONITOR_WIDTH} -value {011} - - - -# Add scalar net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "CORERESET_PF_C1_0:FABRIC_RESET_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "CLK_TRAIN_DONE" "PF_IOD_0:CLK_TRAIN_DONE" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "CORERXIODBITALIGN_C1_L0:RESETN" "CORERXIODBITALIGN_C1_L1:RESETN" "CORERXIODBITALIGN_C1_L2:RESETN" "CORERXIODBITALIGN_C1_L3:RESETN" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:A" "CORERXIODBITALIGN_C1_L0:BIT_ALGN_DONE" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:B" "CORERXIODBITALIGN_C1_L1:BIT_ALGN_DONE" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:C" "CORERXIODBITALIGN_C1_L2:BIT_ALGN_DONE" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:D" "CORERXIODBITALIGN_C1_L3:BIT_ALGN_DONE" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:Y" "training_done_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"ARST_N" "PF_IOD_0:ARST_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CLK_TRAIN_ERROR" "PF_IOD_0:CLK_TRAIN_ERROR" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:CLK" "CORERXIODBITALIGN_C1_L0:SCLK" "CORERXIODBITALIGN_C1_L1:SCLK" "CORERXIODBITALIGN_C1_L2:SCLK" "CORERXIODBITALIGN_C1_L3:SCLK" "PF_IOD_0:RX_CLK_G" "RX_CLK_G" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:EXT_RST_N" "TRAINING_RESETN" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:BIT_ALGN_CLR_FLGS" "PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS[0:0]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:BIT_ALGN_DIR" "PF_IOD_0:DELAY_LINE_DIRECTION[0:0]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:BIT_ALGN_LOAD" "PF_IOD_0:DELAY_LINE_LOAD[0:0]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:BIT_ALGN_MOVE" "PF_IOD_0:DELAY_LINE_MOVE[0:0]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:BIT_ALGN_RSTRT" "CORERXIODBITALIGN_C1_L1:BIT_ALGN_RSTRT" "CORERXIODBITALIGN_C1_L2:BIT_ALGN_RSTRT" "CORERXIODBITALIGN_C1_L3:BIT_ALGN_RSTRT" "RESTART_TRNG" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:BIT_ALGN_SKIP" "CORERXIODBITALIGN_C1_L1:BIT_ALGN_SKIP" "CORERXIODBITALIGN_C1_L2:BIT_ALGN_SKIP" "CORERXIODBITALIGN_C1_L3:BIT_ALGN_SKIP" "SKIP_TRNG" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:IOD_EARLY" "PF_IOD_0:EYE_MONITOR_EARLY[0:0]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:IOD_LATE" "PF_IOD_0:EYE_MONITOR_LATE[0:0]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:IOD_OOR" "PF_IOD_0:DELAY_LINE_OUT_OF_RANGE[0:0]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:LP_IN" "L0_LP_DATA_N" "PF_IOD_0:L0_LP_DATA_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:PLL_LOCK" "CORERXIODBITALIGN_C1_L1:PLL_LOCK" "CORERXIODBITALIGN_C1_L2:PLL_LOCK" "CORERXIODBITALIGN_C1_L3:PLL_LOCK" "PLL_LOCK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:BIT_ALGN_CLR_FLGS" "PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS[1:1]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:BIT_ALGN_DIR" "PF_IOD_0:DELAY_LINE_DIRECTION[1:1]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:BIT_ALGN_LOAD" "PF_IOD_0:DELAY_LINE_LOAD[1:1]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:BIT_ALGN_MOVE" "PF_IOD_0:DELAY_LINE_MOVE[1:1]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:IOD_EARLY" "PF_IOD_0:EYE_MONITOR_EARLY[1:1]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:IOD_LATE" "PF_IOD_0:EYE_MONITOR_LATE[1:1]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:IOD_OOR" "PF_IOD_0:DELAY_LINE_OUT_OF_RANGE[1:1]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:LP_IN" "L1_LP_DATA_N" "PF_IOD_0:L1_LP_DATA_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:BIT_ALGN_CLR_FLGS" "PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS[2:2]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:BIT_ALGN_DIR" "PF_IOD_0:DELAY_LINE_DIRECTION[2:2]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:BIT_ALGN_LOAD" "PF_IOD_0:DELAY_LINE_LOAD[2:2]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:BIT_ALGN_MOVE" "PF_IOD_0:DELAY_LINE_MOVE[2:2]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:IOD_EARLY" "PF_IOD_0:EYE_MONITOR_EARLY[2:2]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:IOD_LATE" "PF_IOD_0:EYE_MONITOR_LATE[2:2]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:IOD_OOR" "PF_IOD_0:DELAY_LINE_OUT_OF_RANGE[2:2]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:LP_IN" "L2_LP_DATA_N" "PF_IOD_0:L2_LP_DATA_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:BIT_ALGN_CLR_FLGS" "PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS[3:3]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:BIT_ALGN_DIR" "PF_IOD_0:DELAY_LINE_DIRECTION[3:3]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:BIT_ALGN_LOAD" "PF_IOD_0:DELAY_LINE_LOAD[3:3]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:BIT_ALGN_MOVE" "PF_IOD_0:DELAY_LINE_MOVE[3:3]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:IOD_EARLY" "PF_IOD_0:EYE_MONITOR_EARLY[3:3]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:IOD_LATE" "PF_IOD_0:EYE_MONITOR_LATE[3:3]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:IOD_OOR" "PF_IOD_0:DELAY_LINE_OUT_OF_RANGE[3:3]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:LP_IN" "L3_LP_DATA_N" "PF_IOD_0:L3_LP_DATA_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"HS_IO_CLK_PAUSE" "PF_IOD_0:HS_IO_CLK_PAUSE" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"HS_SEL" "PF_IOD_0:HS_SEL" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"L0_LP_DATA" "PF_IOD_0:L0_LP_DATA" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"L1_LP_DATA" "PF_IOD_0:L1_LP_DATA" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"L2_LP_DATA" "PF_IOD_0:L2_LP_DATA" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"L3_LP_DATA" "PF_IOD_0:L3_LP_DATA" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_0:RX_CLK_N" "RX_CLK_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_0:RX_CLK_P" "RX_CLK_P" } - -# Add bus net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"L0_RXD_DATA" "PF_IOD_0:L0_RXD_DATA" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"L1_RXD_DATA" "PF_IOD_0:L1_RXD_DATA" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"L2_RXD_DATA" "PF_IOD_0:L2_RXD_DATA" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"L3_RXD_DATA" "PF_IOD_0:L3_RXD_DATA" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_0:RXD" "RXD" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_0:RXD_N" "RXD_N" } - - -# Re-enable auto promotion of pins of type 'pad' -auto_promote_pad_pins -promote_all 1 -# Save the smartDesign -save_smartdesign -sd_name ${sd_name} -# Generate SmartDesign CAM_IOD_TIP_TOP -generate_component -component_name ${sd_name} +# Creating SmartDesign CAM_IOD_TIP_TOP +set sd_name {CAM_IOD_TIP_TOP} +create_smartdesign -sd_name ${sd_name} + +# Disable auto promotion of pins of type 'pad' +auto_promote_pad_pins -promote_all 0 + +# Create top level Scalar Ports +sd_create_scalar_port -sd_name ${sd_name} -port_name {ARST_N} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {HS_IO_CLK_PAUSE} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {HS_SEL} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {PLL_LOCK} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {RESTART_TRNG} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {RX_CLK_N} -port_direction {IN} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {RX_CLK_P} -port_direction {IN} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {SKIP_TRNG} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {TRAINING_RESETN} -port_direction {IN} + +sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK_TRAIN_DONE} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK_TRAIN_ERROR} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {L0_LP_DATA_N} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {L0_LP_DATA} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {L1_LP_DATA_N} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {L1_LP_DATA} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {L2_LP_DATA_N} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {L2_LP_DATA} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {L3_LP_DATA_N} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {L3_LP_DATA} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {RX_CLK_G} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {training_done_o} -port_direction {OUT} + + +# Create top level Bus Ports +sd_create_bus_port -sd_name ${sd_name} -port_name {RXD_N} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1} +sd_create_bus_port -sd_name ${sd_name} -port_name {RXD} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1} + +sd_create_bus_port -sd_name ${sd_name} -port_name {L0_RXD_DATA} -port_direction {OUT} -port_range {[7:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {L1_RXD_DATA} -port_direction {OUT} -port_range {[7:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {L2_RXD_DATA} -port_direction {OUT} -port_range {[7:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {L3_RXD_DATA} -port_direction {OUT} -port_range {[7:0]} + + +# Add AND2_0 instance +sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0} + + + +# Add AND4_0 instance +sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND4} -instance_name {AND4_0} + + + +# Add CORERESET_PF_C1_0 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C1} -instance_name {CORERESET_PF_C1_0} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:BANK_x_VDDI_STATUS} -value {VCC} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:BANK_y_VDDI_STATUS} -value {VCC} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:PLL_LOCK} -value {VCC} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:SS_BUSY} -value {GND} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:INIT_DONE} -value {VCC} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:FF_US_RESTORE} -value {GND} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:FPGA_POR_N} -value {VCC} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:PLL_POWERDOWN_B} + + + +# Add CORERXIODBITALIGN_C1_L0 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {CORERXIODBITALIGN_C1} -instance_name {CORERXIODBITALIGN_C1_L0} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:BIT_ALGN_START} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:BIT_ALGN_OOR} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:BIT_ALGN_HOLD} -value {GND} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:BIT_ALGN_ERR} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:BIT_ALGN_EYE_IN} -value {011} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:DEM_BIT_ALGN_TAPDLY} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:RX_BIT_ALIGN_LEFT_WIN} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:RX_BIT_ALIGN_RGHT_WIN} + + + +# Add CORERXIODBITALIGN_C1_L1 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {CORERXIODBITALIGN_C1} -instance_name {CORERXIODBITALIGN_C1_L1} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:BIT_ALGN_START} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:BIT_ALGN_OOR} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:BIT_ALGN_HOLD} -value {GND} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:BIT_ALGN_ERR} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:BIT_ALGN_EYE_IN} -value {011} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:DEM_BIT_ALGN_TAPDLY} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:RX_BIT_ALIGN_LEFT_WIN} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:RX_BIT_ALIGN_RGHT_WIN} + + + +# Add CORERXIODBITALIGN_C1_L2 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {CORERXIODBITALIGN_C1} -instance_name {CORERXIODBITALIGN_C1_L2} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:BIT_ALGN_START} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:BIT_ALGN_OOR} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:BIT_ALGN_HOLD} -value {GND} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:BIT_ALGN_ERR} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:BIT_ALGN_EYE_IN} -value {011} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:DEM_BIT_ALGN_TAPDLY} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:RX_BIT_ALIGN_LEFT_WIN} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:RX_BIT_ALIGN_RGHT_WIN} + + + +# Add CORERXIODBITALIGN_C1_L3 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {CORERXIODBITALIGN_C1} -instance_name {CORERXIODBITALIGN_C1_L3} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:BIT_ALGN_START} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:BIT_ALGN_OOR} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:BIT_ALGN_HOLD} -value {GND} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:BIT_ALGN_ERR} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:BIT_ALGN_EYE_IN} -value {011} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:DEM_BIT_ALGN_TAPDLY} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:RX_BIT_ALIGN_LEFT_WIN} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:RX_BIT_ALIGN_RGHT_WIN} + + + +# Add PF_IOD_0 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {PF_IOD_GENERIC_RX_C0} -instance_name {PF_IOD_0} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS} -pin_slices {[0:0]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS} -pin_slices {[1:1]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS} -pin_slices {[2:2]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS} -pin_slices {[3:3]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_EARLY} -pin_slices {[0:0]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_EARLY} -pin_slices {[1:1]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_EARLY} -pin_slices {[2:2]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_EARLY} -pin_slices {[3:3]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_LATE} -pin_slices {[0:0]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_LATE} -pin_slices {[1:1]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_LATE} -pin_slices {[2:2]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_LATE} -pin_slices {[3:3]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_MOVE} -pin_slices {[0:0]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_MOVE} -pin_slices {[1:1]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_MOVE} -pin_slices {[2:2]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_MOVE} -pin_slices {[3:3]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_DIRECTION} -pin_slices {[0:0]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_DIRECTION} -pin_slices {[1:1]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_DIRECTION} -pin_slices {[2:2]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_DIRECTION} -pin_slices {[3:3]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_LOAD} -pin_slices {[0:0]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_LOAD} -pin_slices {[1:1]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_LOAD} -pin_slices {[2:2]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_LOAD} -pin_slices {[3:3]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_OUT_OF_RANGE} -pin_slices {[0:0]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_OUT_OF_RANGE} -pin_slices {[1:1]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_OUT_OF_RANGE} -pin_slices {[2:2]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_OUT_OF_RANGE} -pin_slices {[3:3]} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_IOD_0:EYE_MONITOR_WIDTH} -value {011} + + + +# Add scalar net connections +sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "CORERESET_PF_C1_0:FABRIC_RESET_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "CLK_TRAIN_DONE" "PF_IOD_0:CLK_TRAIN_DONE" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "CORERXIODBITALIGN_C1_L0:RESETN" "CORERXIODBITALIGN_C1_L1:RESETN" "CORERXIODBITALIGN_C1_L2:RESETN" "CORERXIODBITALIGN_C1_L3:RESETN" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:A" "CORERXIODBITALIGN_C1_L0:BIT_ALGN_DONE" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:B" "CORERXIODBITALIGN_C1_L1:BIT_ALGN_DONE" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:C" "CORERXIODBITALIGN_C1_L2:BIT_ALGN_DONE" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:D" "CORERXIODBITALIGN_C1_L3:BIT_ALGN_DONE" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:Y" "training_done_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"ARST_N" "PF_IOD_0:ARST_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CLK_TRAIN_ERROR" "PF_IOD_0:CLK_TRAIN_ERROR" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:CLK" "CORERXIODBITALIGN_C1_L0:SCLK" "CORERXIODBITALIGN_C1_L1:SCLK" "CORERXIODBITALIGN_C1_L2:SCLK" "CORERXIODBITALIGN_C1_L3:SCLK" "PF_IOD_0:RX_CLK_G" "RX_CLK_G" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:EXT_RST_N" "TRAINING_RESETN" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:BIT_ALGN_CLR_FLGS" "PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS[0:0]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:BIT_ALGN_DIR" "PF_IOD_0:DELAY_LINE_DIRECTION[0:0]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:BIT_ALGN_LOAD" "PF_IOD_0:DELAY_LINE_LOAD[0:0]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:BIT_ALGN_MOVE" "PF_IOD_0:DELAY_LINE_MOVE[0:0]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:BIT_ALGN_RSTRT" "CORERXIODBITALIGN_C1_L1:BIT_ALGN_RSTRT" "CORERXIODBITALIGN_C1_L2:BIT_ALGN_RSTRT" "CORERXIODBITALIGN_C1_L3:BIT_ALGN_RSTRT" "RESTART_TRNG" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:BIT_ALGN_SKIP" "CORERXIODBITALIGN_C1_L1:BIT_ALGN_SKIP" "CORERXIODBITALIGN_C1_L2:BIT_ALGN_SKIP" "CORERXIODBITALIGN_C1_L3:BIT_ALGN_SKIP" "SKIP_TRNG" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:IOD_EARLY" "PF_IOD_0:EYE_MONITOR_EARLY[0:0]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:IOD_LATE" "PF_IOD_0:EYE_MONITOR_LATE[0:0]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:IOD_OOR" "PF_IOD_0:DELAY_LINE_OUT_OF_RANGE[0:0]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:LP_IN" "L0_LP_DATA_N" "PF_IOD_0:L0_LP_DATA_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:PLL_LOCK" "CORERXIODBITALIGN_C1_L1:PLL_LOCK" "CORERXIODBITALIGN_C1_L2:PLL_LOCK" "CORERXIODBITALIGN_C1_L3:PLL_LOCK" "PLL_LOCK" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:BIT_ALGN_CLR_FLGS" "PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS[1:1]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:BIT_ALGN_DIR" "PF_IOD_0:DELAY_LINE_DIRECTION[1:1]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:BIT_ALGN_LOAD" "PF_IOD_0:DELAY_LINE_LOAD[1:1]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:BIT_ALGN_MOVE" "PF_IOD_0:DELAY_LINE_MOVE[1:1]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:IOD_EARLY" "PF_IOD_0:EYE_MONITOR_EARLY[1:1]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:IOD_LATE" "PF_IOD_0:EYE_MONITOR_LATE[1:1]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:IOD_OOR" "PF_IOD_0:DELAY_LINE_OUT_OF_RANGE[1:1]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:LP_IN" "L1_LP_DATA_N" "PF_IOD_0:L1_LP_DATA_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:BIT_ALGN_CLR_FLGS" "PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS[2:2]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:BIT_ALGN_DIR" "PF_IOD_0:DELAY_LINE_DIRECTION[2:2]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:BIT_ALGN_LOAD" "PF_IOD_0:DELAY_LINE_LOAD[2:2]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:BIT_ALGN_MOVE" "PF_IOD_0:DELAY_LINE_MOVE[2:2]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:IOD_EARLY" "PF_IOD_0:EYE_MONITOR_EARLY[2:2]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:IOD_LATE" "PF_IOD_0:EYE_MONITOR_LATE[2:2]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:IOD_OOR" "PF_IOD_0:DELAY_LINE_OUT_OF_RANGE[2:2]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:LP_IN" "L2_LP_DATA_N" "PF_IOD_0:L2_LP_DATA_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:BIT_ALGN_CLR_FLGS" "PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS[3:3]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:BIT_ALGN_DIR" "PF_IOD_0:DELAY_LINE_DIRECTION[3:3]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:BIT_ALGN_LOAD" "PF_IOD_0:DELAY_LINE_LOAD[3:3]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:BIT_ALGN_MOVE" "PF_IOD_0:DELAY_LINE_MOVE[3:3]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:IOD_EARLY" "PF_IOD_0:EYE_MONITOR_EARLY[3:3]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:IOD_LATE" "PF_IOD_0:EYE_MONITOR_LATE[3:3]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:IOD_OOR" "PF_IOD_0:DELAY_LINE_OUT_OF_RANGE[3:3]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:LP_IN" "L3_LP_DATA_N" "PF_IOD_0:L3_LP_DATA_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"HS_IO_CLK_PAUSE" "PF_IOD_0:HS_IO_CLK_PAUSE" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"HS_SEL" "PF_IOD_0:HS_SEL" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"L0_LP_DATA" "PF_IOD_0:L0_LP_DATA" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"L1_LP_DATA" "PF_IOD_0:L1_LP_DATA" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"L2_LP_DATA" "PF_IOD_0:L2_LP_DATA" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"L3_LP_DATA" "PF_IOD_0:L3_LP_DATA" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_0:RX_CLK_N" "RX_CLK_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_0:RX_CLK_P" "RX_CLK_P" } + +# Add bus net connections +sd_connect_pins -sd_name ${sd_name} -pin_names {"L0_RXD_DATA" "PF_IOD_0:L0_RXD_DATA" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"L1_RXD_DATA" "PF_IOD_0:L1_RXD_DATA" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"L2_RXD_DATA" "PF_IOD_0:L2_RXD_DATA" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"L3_RXD_DATA" "PF_IOD_0:L3_RXD_DATA" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_0:RXD" "RXD" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_0:RXD_N" "RXD_N" } + + +# Re-enable auto promotion of pins of type 'pad' +auto_promote_pad_pins -promote_all 1 +# Save the smartDesign +save_smartdesign -sd_name ${sd_name} +# Generate SmartDesign CAM_IOD_TIP_TOP +generate_component -component_name ${sd_name} diff --git a/script_support/components/CLOCKS_AND_RESETS.tcl b/script_support/components/CLOCKS_AND_RESETS.tcl index 5140f3f..5078e0c 100644 --- a/script_support/components/CLOCKS_AND_RESETS.tcl +++ b/script_support/components/CLOCKS_AND_RESETS.tcl @@ -1,111 +1,111 @@ -# Creating SmartDesign CLOCKS_AND_RESETS -set sd_name {CLOCKS_AND_RESETS} -create_smartdesign -sd_name ${sd_name} - -# Disable auto promotion of pins of type 'pad' -auto_promote_pad_pins -promote_all 0 - -# Create top level Scalar Ports -sd_create_scalar_port -sd_name ${sd_name} -port_name {EXT_RST_N} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {MSS_PLL_LOCKS} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_N} -port_direction {IN} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_P} -port_direction {IN} -port_is_pad {1} - -sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK_125MHz} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK_50MHz} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {DEVICE_INIT_DONE} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {FABRIC_POR_N} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {I2C_BCLK} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {RESETN_125MHz} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {RESETN_50MHz} -port_direction {OUT} - - - -# Add AND2_0 instance -sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0} - - - -# Add CORERESET_CLK_50MHz instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C5} -instance_name {CORERESET_CLK_50MHz} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_CLK_50MHz:BANK_x_VDDI_STATUS} -value {VCC} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_CLK_50MHz:BANK_y_VDDI_STATUS} -value {VCC} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_CLK_50MHz:SS_BUSY} -value {GND} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_CLK_50MHz:FF_US_RESTORE} -value {GND} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERESET_CLK_50MHz:PLL_POWERDOWN_B} - - - -# Add CORERESET_CLK_125MHz instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET} -instance_name {CORERESET_CLK_125MHz} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_CLK_125MHz:BANK_x_VDDI_STATUS} -value {VCC} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_CLK_125MHz:BANK_y_VDDI_STATUS} -value {VCC} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_CLK_125MHz:SS_BUSY} -value {GND} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_CLK_125MHz:FF_US_RESTORE} -value {GND} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERESET_CLK_125MHz:PLL_POWERDOWN_B} - - - -# Add INIT_MONITOR_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {INIT_MONITOR} -instance_name {INIT_MONITOR_0} -sd_create_pin_group -sd_name ${sd_name} -group_name {Group} -instance_name {INIT_MONITOR_0} -pin_names {"USRAM_INIT_FROM_SNVM_DONE" "USRAM_INIT_DONE" "SRAM_INIT_FROM_UPROM_DONE" "USRAM_INIT_FROM_UPROM_DONE" "SRAM_INIT_FROM_SPI_DONE" "SRAM_INIT_DONE" "USRAM_INIT_FROM_SPI_DONE" "SRAM_INIT_FROM_SNVM_DONE" "AUTOCALIB_DONE" "PCIE_INIT_DONE" "XCVR_INIT_DONE" } -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:PCIE_INIT_DONE} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:USRAM_INIT_DONE} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:SRAM_INIT_DONE} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:XCVR_INIT_DONE} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:USRAM_INIT_FROM_SNVM_DONE} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:USRAM_INIT_FROM_UPROM_DONE} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:USRAM_INIT_FROM_SPI_DONE} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:SRAM_INIT_FROM_SNVM_DONE} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:SRAM_INIT_FROM_UPROM_DONE} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:SRAM_INIT_FROM_SPI_DONE} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:AUTOCALIB_DONE} - - - -# Add PF_CCC_C0_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_C0} -instance_name {PF_CCC_C0_0} - - - -# Add PF_CLK_DIV_C0_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CLK_DIV_C0} -instance_name {PF_CLK_DIV_C0_0} - - - -# Add PF_OSC_C0_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {PF_OSC_C0} -instance_name {PF_OSC_C0_0} - - - -# Add PF_XCVR_REF_CLK_C0_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_REF_CLK_C0} -instance_name {PF_XCVR_REF_CLK_C0_0} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_REF_CLK_C0_0:REF_CLK} - - - -# Add scalar net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "PF_CCC_C0_0:PLL_LOCK_0" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "MSS_PLL_LOCKS" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "CORERESET_CLK_125MHz:PLL_LOCK" "CORERESET_CLK_50MHz:PLL_LOCK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CLK_125MHz" "CORERESET_CLK_125MHz:CLK" "PF_CCC_C0_0:OUT0_FABCLK_0" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CLK_50MHz" "CORERESET_CLK_50MHz:CLK" "PF_CCC_C0_0:OUT1_FABCLK_0" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_CLK_125MHz:EXT_RST_N" "CORERESET_CLK_50MHz:EXT_RST_N" "EXT_RST_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_CLK_125MHz:FABRIC_RESET_N" "RESETN_125MHz" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_CLK_125MHz:FPGA_POR_N" "CORERESET_CLK_50MHz:FPGA_POR_N" "FABRIC_POR_N" "INIT_MONITOR_0:FABRIC_POR_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_CLK_125MHz:INIT_DONE" "CORERESET_CLK_50MHz:INIT_DONE" "DEVICE_INIT_DONE" "INIT_MONITOR_0:DEVICE_INIT_DONE" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_CLK_50MHz:FABRIC_RESET_N" "RESETN_50MHz" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"I2C_BCLK" "PF_CLK_DIV_C0_0:CLK_OUT" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_C0_0:REF_CLK_0" "PF_XCVR_REF_CLK_C0_0:FAB_REF_CLK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CLK_DIV_C0_0:CLK_IN" "PF_OSC_C0_0:RCOSC_2MHZ_CLK_DIV" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_C0_0:REF_CLK_PAD_N" "REF_CLK_PAD_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_C0_0:REF_CLK_PAD_P" "REF_CLK_PAD_P" } - - - -# Re-enable auto promotion of pins of type 'pad' -auto_promote_pad_pins -promote_all 1 -# Save the smartDesign -save_smartdesign -sd_name ${sd_name} -# Generate SmartDesign CLOCKS_AND_RESETS -generate_component -component_name ${sd_name} +# Creating SmartDesign CLOCKS_AND_RESETS +set sd_name {CLOCKS_AND_RESETS} +create_smartdesign -sd_name ${sd_name} + +# Disable auto promotion of pins of type 'pad' +auto_promote_pad_pins -promote_all 0 + +# Create top level Scalar Ports +sd_create_scalar_port -sd_name ${sd_name} -port_name {EXT_RST_N} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {MSS_PLL_LOCKS} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_N} -port_direction {IN} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_P} -port_direction {IN} -port_is_pad {1} + +sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK_125MHz} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK_50MHz} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {DEVICE_INIT_DONE} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {FABRIC_POR_N} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {I2C_BCLK} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {RESETN_125MHz} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {RESETN_50MHz} -port_direction {OUT} + + + +# Add AND2_0 instance +sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0} + + + +# Add CORERESET_CLK_50MHz instance +sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C5} -instance_name {CORERESET_CLK_50MHz} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_CLK_50MHz:BANK_x_VDDI_STATUS} -value {VCC} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_CLK_50MHz:BANK_y_VDDI_STATUS} -value {VCC} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_CLK_50MHz:SS_BUSY} -value {GND} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_CLK_50MHz:FF_US_RESTORE} -value {GND} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERESET_CLK_50MHz:PLL_POWERDOWN_B} + + + +# Add CORERESET_CLK_125MHz instance +sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET} -instance_name {CORERESET_CLK_125MHz} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_CLK_125MHz:BANK_x_VDDI_STATUS} -value {VCC} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_CLK_125MHz:BANK_y_VDDI_STATUS} -value {VCC} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_CLK_125MHz:SS_BUSY} -value {GND} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_CLK_125MHz:FF_US_RESTORE} -value {GND} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERESET_CLK_125MHz:PLL_POWERDOWN_B} + + + +# Add INIT_MONITOR_0 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {INIT_MONITOR} -instance_name {INIT_MONITOR_0} +sd_create_pin_group -sd_name ${sd_name} -group_name {Group} -instance_name {INIT_MONITOR_0} -pin_names {"USRAM_INIT_FROM_SNVM_DONE" "USRAM_INIT_DONE" "SRAM_INIT_FROM_UPROM_DONE" "USRAM_INIT_FROM_UPROM_DONE" "SRAM_INIT_FROM_SPI_DONE" "SRAM_INIT_DONE" "USRAM_INIT_FROM_SPI_DONE" "SRAM_INIT_FROM_SNVM_DONE" "AUTOCALIB_DONE" "PCIE_INIT_DONE" "XCVR_INIT_DONE" } +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:PCIE_INIT_DONE} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:USRAM_INIT_DONE} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:SRAM_INIT_DONE} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:XCVR_INIT_DONE} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:USRAM_INIT_FROM_SNVM_DONE} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:USRAM_INIT_FROM_UPROM_DONE} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:USRAM_INIT_FROM_SPI_DONE} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:SRAM_INIT_FROM_SNVM_DONE} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:SRAM_INIT_FROM_UPROM_DONE} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:SRAM_INIT_FROM_SPI_DONE} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:AUTOCALIB_DONE} + + + +# Add PF_CCC_C0_0 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_C0} -instance_name {PF_CCC_C0_0} + + + +# Add PF_CLK_DIV_C0_0 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CLK_DIV_C0} -instance_name {PF_CLK_DIV_C0_0} + + + +# Add PF_OSC_C0_0 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {PF_OSC_C0} -instance_name {PF_OSC_C0_0} + + + +# Add PF_XCVR_REF_CLK_C0_0 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_REF_CLK_C0} -instance_name {PF_XCVR_REF_CLK_C0_0} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_REF_CLK_C0_0:REF_CLK} + + + +# Add scalar net connections +sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "PF_CCC_C0_0:PLL_LOCK_0" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "MSS_PLL_LOCKS" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "CORERESET_CLK_125MHz:PLL_LOCK" "CORERESET_CLK_50MHz:PLL_LOCK" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CLK_125MHz" "CORERESET_CLK_125MHz:CLK" "PF_CCC_C0_0:OUT0_FABCLK_0" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CLK_50MHz" "CORERESET_CLK_50MHz:CLK" "PF_CCC_C0_0:OUT1_FABCLK_0" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_CLK_125MHz:EXT_RST_N" "CORERESET_CLK_50MHz:EXT_RST_N" "EXT_RST_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_CLK_125MHz:FABRIC_RESET_N" "RESETN_125MHz" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_CLK_125MHz:FPGA_POR_N" "CORERESET_CLK_50MHz:FPGA_POR_N" "FABRIC_POR_N" "INIT_MONITOR_0:FABRIC_POR_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_CLK_125MHz:INIT_DONE" "CORERESET_CLK_50MHz:INIT_DONE" "DEVICE_INIT_DONE" "INIT_MONITOR_0:DEVICE_INIT_DONE" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_CLK_50MHz:FABRIC_RESET_N" "RESETN_50MHz" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"I2C_BCLK" "PF_CLK_DIV_C0_0:CLK_OUT" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_C0_0:REF_CLK_0" "PF_XCVR_REF_CLK_C0_0:FAB_REF_CLK" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CLK_DIV_C0_0:CLK_IN" "PF_OSC_C0_0:RCOSC_2MHZ_CLK_DIV" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_C0_0:REF_CLK_PAD_N" "REF_CLK_PAD_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_C0_0:REF_CLK_PAD_P" "REF_CLK_PAD_P" } + + + +# Re-enable auto promotion of pins of type 'pad' +auto_promote_pad_pins -promote_all 1 +# Save the smartDesign +save_smartdesign -sd_name ${sd_name} +# Generate SmartDesign CLOCKS_AND_RESETS +generate_component -component_name ${sd_name} diff --git a/script_support/components/CORERESET.tcl b/script_support/components/CORERESET.tcl index fa36ea3..f230ed8 100644 --- a/script_support/components/CORERESET.tcl +++ b/script_support/components/CORERESET.tcl @@ -1,6 +1,6 @@ -# Exporting Component Description of CORERESET to TCL -# Family: PolarFireSoC -# Part Number: MPFS250T_ES-1FCG1152E -# Create and Configure the core component CORERESET -create_and_configure_core -core_vlnv {Actel:DirectCore:CORERESET_PF:2.3.100} -component_name {CORERESET} -params { } -# Exporting Component Description of CORERESET to TCL done +# Exporting Component Description of CORERESET to TCL +# Family: PolarFireSoC +# Part Number: MPFS250T_ES-1FCG1152E +# Create and Configure the core component CORERESET +create_and_configure_core -core_vlnv {Actel:DirectCore:CORERESET_PF:2.3.100} -component_name {CORERESET} -params { } +# Exporting Component Description of CORERESET to TCL done diff --git a/script_support/components/CORERESET_PF_C1.tcl b/script_support/components/CORERESET_PF_C1.tcl index 4b8bf59..c93e253 100644 --- a/script_support/components/CORERESET_PF_C1.tcl +++ b/script_support/components/CORERESET_PF_C1.tcl @@ -1,6 +1,6 @@ -# Exporting Component Description of CORERESET_PF_C1 to TCL -# Family: PolarFireSoC -# Part Number: MPFS250T_ES-1FCG1152E -# Create and Configure the core component CORERESET_PF_C1 -create_and_configure_core -core_vlnv {Actel:DirectCore:CORERESET_PF:2.3.100} -component_name {CORERESET_PF_C1} -params { } -# Exporting Component Description of CORERESET_PF_C1 to TCL done +# Exporting Component Description of CORERESET_PF_C1 to TCL +# Family: PolarFireSoC +# Part Number: MPFS250T_ES-1FCG1152E +# Create and Configure the core component CORERESET_PF_C1 +create_and_configure_core -core_vlnv {Actel:DirectCore:CORERESET_PF:2.3.100} -component_name {CORERESET_PF_C1} -params { } +# Exporting Component Description of CORERESET_PF_C1 to TCL done diff --git a/script_support/components/CORERESET_PF_C2.tcl b/script_support/components/CORERESET_PF_C2.tcl index eaac61e..c01db2d 100644 --- a/script_support/components/CORERESET_PF_C2.tcl +++ b/script_support/components/CORERESET_PF_C2.tcl @@ -1,6 +1,6 @@ -# Exporting Component Description of CORERESET_PF_C2 to TCL -# Family: PolarFireSoC -# Part Number: MPFS250T_ES-1FCG1152E -# Create and Configure the core component CORERESET_PF_C2 -create_and_configure_core -core_vlnv {Actel:DirectCore:CORERESET_PF:2.3.100} -component_name {CORERESET_PF_C2} -params { } -# Exporting Component Description of CORERESET_PF_C2 to TCL done +# Exporting Component Description of CORERESET_PF_C2 to TCL +# Family: PolarFireSoC +# Part Number: MPFS250T_ES-1FCG1152E +# Create and Configure the core component CORERESET_PF_C2 +create_and_configure_core -core_vlnv {Actel:DirectCore:CORERESET_PF:2.3.100} -component_name {CORERESET_PF_C2} -params { } +# Exporting Component Description of CORERESET_PF_C2 to TCL done diff --git a/script_support/components/CORERESET_PF_C5.tcl b/script_support/components/CORERESET_PF_C5.tcl index 87ca2f8..a71d974 100644 --- a/script_support/components/CORERESET_PF_C5.tcl +++ b/script_support/components/CORERESET_PF_C5.tcl @@ -1,6 +1,6 @@ -# Exporting Component Description of CORERESET_PF_C5 to TCL -# Family: PolarFireSoC -# Part Number: MPFS250T_ES-1FCG1152E -# Create and Configure the core component CORERESET_PF_C5 -create_and_configure_core -core_vlnv {Actel:DirectCore:CORERESET_PF:2.3.100} -component_name {CORERESET_PF_C5} -params { } -# Exporting Component Description of CORERESET_PF_C5 to TCL done +# Exporting Component Description of CORERESET_PF_C5 to TCL +# Family: PolarFireSoC +# Part Number: MPFS250T_ES-1FCG1152E +# Create and Configure the core component CORERESET_PF_C5 +create_and_configure_core -core_vlnv {Actel:DirectCore:CORERESET_PF:2.3.100} -component_name {CORERESET_PF_C5} -params { } +# Exporting Component Description of CORERESET_PF_C5 to TCL done diff --git a/script_support/components/CORERXIODBITALIGN_C1.tcl b/script_support/components/CORERXIODBITALIGN_C1.tcl index 47bd664..ff4d7d2 100644 --- a/script_support/components/CORERXIODBITALIGN_C1.tcl +++ b/script_support/components/CORERXIODBITALIGN_C1.tcl @@ -1,10 +1,10 @@ -# Exporting Component Description of CORERXIODBITALIGN_C1 to TCL -# Family: PolarFireSoC -# Part Number: MPFS250T_ES-1FCG1152E -# Create and Configure the core component CORERXIODBITALIGN_C1 -create_and_configure_core -core_vlnv {Actel:DirectCore:CORERXIODBITALIGN:2.2.100} -component_name {CORERXIODBITALIGN_C1} -params {\ -"DEM_TAP_WAIT_CNT_WIDTH:3" \ -"HOLD_TRNG:0" \ -"MIPI_TRNG:1" \ -"SKIP_TRNG:0" } -# Exporting Component Description of CORERXIODBITALIGN_C1 to TCL done +# Exporting Component Description of CORERXIODBITALIGN_C1 to TCL +# Family: PolarFireSoC +# Part Number: MPFS250T_ES-1FCG1152E +# Create and Configure the core component CORERXIODBITALIGN_C1 +create_and_configure_core -core_vlnv {Actel:DirectCore:CORERXIODBITALIGN:2.2.100} -component_name {CORERXIODBITALIGN_C1} -params {\ +"DEM_TAP_WAIT_CNT_WIDTH:3" \ +"HOLD_TRNG:0" \ +"MIPI_TRNG:1" \ +"SKIP_TRNG:0" } +# Exporting Component Description of CORERXIODBITALIGN_C1 to TCL done diff --git a/script_support/components/CoreAPB3_C0.tcl b/script_support/components/CoreAPB3_C0.tcl index fd99025..1ed1969 100644 --- a/script_support/components/CoreAPB3_C0.tcl +++ b/script_support/components/CoreAPB3_C0.tcl @@ -1,42 +1,42 @@ -# Exporting Component Description of CoreAPB3_C0 to TCL -# Family: PolarFireSoC -# Part Number: MPFS250T_ES-1FCG1152E -# Create and Configure the core component CoreAPB3_C0 -create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -component_name {CoreAPB3_C0} -params {\ -"APB_DWIDTH:32" \ -"APBSLOT0ENABLE:true" \ -"APBSLOT1ENABLE:true" \ -"APBSLOT2ENABLE:false" \ -"APBSLOT3ENABLE:false" \ -"APBSLOT4ENABLE:false" \ -"APBSLOT5ENABLE:false" \ -"APBSLOT6ENABLE:false" \ -"APBSLOT7ENABLE:false" \ -"APBSLOT8ENABLE:false" \ -"APBSLOT9ENABLE:false" \ -"APBSLOT10ENABLE:false" \ -"APBSLOT11ENABLE:false" \ -"APBSLOT12ENABLE:false" \ -"APBSLOT13ENABLE:false" \ -"APBSLOT14ENABLE:false" \ -"APBSLOT15ENABLE:false" \ -"IADDR_OPTION:0" \ -"MADDR_BITS:16" \ -"SC_0:false" \ -"SC_1:false" \ -"SC_2:false" \ -"SC_3:false" \ -"SC_4:false" \ -"SC_5:false" \ -"SC_6:false" \ -"SC_7:false" \ -"SC_8:false" \ -"SC_9:false" \ -"SC_10:false" \ -"SC_11:false" \ -"SC_12:false" \ -"SC_13:false" \ -"SC_14:false" \ -"SC_15:false" \ -"UPR_NIBBLE_POSN:3" } -# Exporting Component Description of CoreAPB3_C0 to TCL done +# Exporting Component Description of CoreAPB3_C0 to TCL +# Family: PolarFireSoC +# Part Number: MPFS250T_ES-1FCG1152E +# Create and Configure the core component CoreAPB3_C0 +create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -component_name {CoreAPB3_C0} -params {\ +"APB_DWIDTH:32" \ +"APBSLOT0ENABLE:true" \ +"APBSLOT1ENABLE:true" \ +"APBSLOT2ENABLE:false" \ +"APBSLOT3ENABLE:false" \ +"APBSLOT4ENABLE:false" \ +"APBSLOT5ENABLE:false" \ +"APBSLOT6ENABLE:false" \ +"APBSLOT7ENABLE:false" \ +"APBSLOT8ENABLE:false" \ +"APBSLOT9ENABLE:false" \ +"APBSLOT10ENABLE:false" \ +"APBSLOT11ENABLE:false" \ +"APBSLOT12ENABLE:false" \ +"APBSLOT13ENABLE:false" \ +"APBSLOT14ENABLE:false" \ +"APBSLOT15ENABLE:false" \ +"IADDR_OPTION:0" \ +"MADDR_BITS:16" \ +"SC_0:false" \ +"SC_1:false" \ +"SC_2:false" \ +"SC_3:false" \ +"SC_4:false" \ +"SC_5:false" \ +"SC_6:false" \ +"SC_7:false" \ +"SC_8:false" \ +"SC_9:false" \ +"SC_10:false" \ +"SC_11:false" \ +"SC_12:false" \ +"SC_13:false" \ +"SC_14:false" \ +"SC_15:false" \ +"UPR_NIBBLE_POSN:3" } +# Exporting Component Description of CoreAPB3_C0 to TCL done diff --git a/script_support/components/DDR_AXI4_ARBITER_PF_C0.tcl b/script_support/components/DDR_AXI4_ARBITER_PF_C0.tcl index ce63d41..8052138 100644 --- a/script_support/components/DDR_AXI4_ARBITER_PF_C0.tcl +++ b/script_support/components/DDR_AXI4_ARBITER_PF_C0.tcl @@ -1,12 +1,12 @@ -# Exporting Component Description of DDR_AXI4_ARBITER_PF_C0 to TCL -# Family: PolarFireSoC -# Part Number: MPFS250T_ES-1FCG1152E -# Create and Configure the core component DDR_AXI4_ARBITER_PF_C0 -create_and_configure_core -core_vlnv {Microsemi:SolutionCore:DDR_AXI4_ARBITER_PF:2.1.0} -component_name {DDR_AXI4_ARBITER_PF_C0} -params {\ -"AXI4_SELECTION:2" \ -"AXI_DATA_WIDTH:64" \ -"AXI_ID_WIDTH:4" \ -"FORMAT:0" \ -"NO_OF_READ_CHANNELS:1" \ -"NO_OF_WRITE_CHANNELS:1" } -# Exporting Component Description of DDR_AXI4_ARBITER_PF_C0 to TCL done +# Exporting Component Description of DDR_AXI4_ARBITER_PF_C0 to TCL +# Family: PolarFireSoC +# Part Number: MPFS250T_ES-1FCG1152E +# Create and Configure the core component DDR_AXI4_ARBITER_PF_C0 +create_and_configure_core -core_vlnv {Microsemi:SolutionCore:DDR_AXI4_ARBITER_PF:2.1.0} -component_name {DDR_AXI4_ARBITER_PF_C0} -params {\ +"AXI4_SELECTION:2" \ +"AXI_DATA_WIDTH:64" \ +"AXI_ID_WIDTH:4" \ +"FORMAT:0" \ +"NO_OF_READ_CHANNELS:1" \ +"NO_OF_WRITE_CHANNELS:1" } +# Exporting Component Description of DDR_AXI4_ARBITER_PF_C0 to TCL done diff --git a/script_support/components/Gamma_Correction_C0.tcl b/script_support/components/Gamma_Correction_C0.tcl index 13dd525..a02258f 100644 --- a/script_support/components/Gamma_Correction_C0.tcl +++ b/script_support/components/Gamma_Correction_C0.tcl @@ -1,9 +1,9 @@ -# Exporting Component Description of Gamma_Correction_C0 to TCL -# Family: PolarFireSoC -# Part Number: MPFS250T_ES-1FCG1152E -# Create and Configure the core component Gamma_Correction_C0 -create_and_configure_core -core_vlnv {Microsemi:SolutionCore:Gamma_Correction:4.2.0} -component_name {Gamma_Correction_C0} -params {\ -"G_DATA_WIDTH:8" \ -"G_FORMAT:0" \ -"G_PIXELS:1" } -# Exporting Component Description of Gamma_Correction_C0 to TCL done +# Exporting Component Description of Gamma_Correction_C0 to TCL +# Family: PolarFireSoC +# Part Number: MPFS250T_ES-1FCG1152E +# Create and Configure the core component Gamma_Correction_C0 +create_and_configure_core -core_vlnv {Microsemi:SolutionCore:Gamma_Correction:4.2.0} -component_name {Gamma_Correction_C0} -params {\ +"G_DATA_WIDTH:8" \ +"G_FORMAT:0" \ +"G_PIXELS:1" } +# Exporting Component Description of Gamma_Correction_C0 to TCL done diff --git a/script_support/components/H264/FIC_CONVERTER.tcl b/script_support/components/H264/FIC_CONVERTER.tcl index 0e2fe6b..babfc8e 100644 --- a/script_support/components/H264/FIC_CONVERTER.tcl +++ b/script_support/components/H264/FIC_CONVERTER.tcl @@ -1,70 +1,70 @@ -# Creating SmartDesign FIC_CONVERTER -set sd_name {FIC_CONVERTER} -create_smartdesign -sd_name ${sd_name} - -# Disable auto promotion of pins of type 'pad' -auto_promote_pad_pins -promote_all 0 - -# Create top level Scalar Ports -sd_create_scalar_port -sd_name ${sd_name} -port_name {FIC3_APB3_master_PENABLE} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {FIC3_APB3_master_PSEL} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {FIC3_APB3_master_PWRITE} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {PREADYS1} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {PSLVERRS1} -port_direction {IN} - -sd_create_scalar_port -sd_name ${sd_name} -port_name {FIC3_APB3_master_PREADY} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {FIC3_APB3_master_PSLVERR} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {PENABLES} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {PSELS1} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {PWRITES} -port_direction {OUT} - - -# Create top level Bus Ports -sd_create_bus_port -sd_name ${sd_name} -port_name {FIC3_APB3_master_PADDR} -port_direction {IN} -port_range {[31:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {FIC3_APB3_master_PWDATA} -port_direction {IN} -port_range {[31:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {PRDATAS1} -port_direction {IN} -port_range {[31:0]} - -sd_create_bus_port -sd_name ${sd_name} -port_name {FIC3_APB3_master_PRDATA} -port_direction {OUT} -port_range {[31:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {PADDRS} -port_direction {OUT} -port_range {[31:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {PWDATAS} -port_direction {OUT} -port_range {[31:0]} - - -# Create top level Bus interface Ports -sd_create_bif_port -sd_name ${sd_name} -port_name {APBmslave} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {mirroredSlave} -port_bif_mapping {\ -"PADDR:PADDRS" \ -"PSELx:PSELS1" \ -"PENABLE:PENABLES" \ -"PWRITE:PWRITES" \ -"PRDATA:PRDATAS1" \ -"PWDATA:PWDATAS" \ -"PREADY:PREADYS1" \ -"PSLVERR:PSLVERRS1" } - -sd_create_bif_port -sd_name ${sd_name} -port_name {FIC3_APB3_master} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {mirroredMaster} -port_bif_mapping {\ -"PADDR:FIC3_APB3_master_PADDR" \ -"PSELx:FIC3_APB3_master_PSEL" \ -"PENABLE:FIC3_APB3_master_PENABLE" \ -"PWRITE:FIC3_APB3_master_PWRITE" \ -"PRDATA:FIC3_APB3_master_PRDATA" \ -"PWDATA:FIC3_APB3_master_PWDATA" \ -"PREADY:FIC3_APB3_master_PREADY" \ -"PSLVERR:FIC3_APB3_master_PSLVERR" } - -# Add CoreAPB3_C0_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_C0} -instance_name {CoreAPB3_C0_0} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreAPB3_C0_0:APBmslave0} - - - - - -# Add bus interface net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"APBmslave" "CoreAPB3_C0_0:APBmslave1" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_C0_0:APB3mmaster" "FIC3_APB3_master" } - -# Re-enable auto promotion of pins of type 'pad' -auto_promote_pad_pins -promote_all 1 -# Save the smartDesign -save_smartdesign -sd_name ${sd_name} -# Generate SmartDesign FIC_CONVERTER -generate_component -component_name ${sd_name} +# Creating SmartDesign FIC_CONVERTER +set sd_name {FIC_CONVERTER} +create_smartdesign -sd_name ${sd_name} + +# Disable auto promotion of pins of type 'pad' +auto_promote_pad_pins -promote_all 0 + +# Create top level Scalar Ports +sd_create_scalar_port -sd_name ${sd_name} -port_name {FIC3_APB3_master_PENABLE} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {FIC3_APB3_master_PSEL} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {FIC3_APB3_master_PWRITE} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {PREADYS1} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {PSLVERRS1} -port_direction {IN} + +sd_create_scalar_port -sd_name ${sd_name} -port_name {FIC3_APB3_master_PREADY} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {FIC3_APB3_master_PSLVERR} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {PENABLES} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {PSELS1} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {PWRITES} -port_direction {OUT} + + +# Create top level Bus Ports +sd_create_bus_port -sd_name ${sd_name} -port_name {FIC3_APB3_master_PADDR} -port_direction {IN} -port_range {[31:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {FIC3_APB3_master_PWDATA} -port_direction {IN} -port_range {[31:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {PRDATAS1} -port_direction {IN} -port_range {[31:0]} + +sd_create_bus_port -sd_name ${sd_name} -port_name {FIC3_APB3_master_PRDATA} -port_direction {OUT} -port_range {[31:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {PADDRS} -port_direction {OUT} -port_range {[31:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {PWDATAS} -port_direction {OUT} -port_range {[31:0]} + + +# Create top level Bus interface Ports +sd_create_bif_port -sd_name ${sd_name} -port_name {APBmslave} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {mirroredSlave} -port_bif_mapping {\ +"PADDR:PADDRS" \ +"PSELx:PSELS1" \ +"PENABLE:PENABLES" \ +"PWRITE:PWRITES" \ +"PRDATA:PRDATAS1" \ +"PWDATA:PWDATAS" \ +"PREADY:PREADYS1" \ +"PSLVERR:PSLVERRS1" } + +sd_create_bif_port -sd_name ${sd_name} -port_name {FIC3_APB3_master} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {mirroredMaster} -port_bif_mapping {\ +"PADDR:FIC3_APB3_master_PADDR" \ +"PSELx:FIC3_APB3_master_PSEL" \ +"PENABLE:FIC3_APB3_master_PENABLE" \ +"PWRITE:FIC3_APB3_master_PWRITE" \ +"PRDATA:FIC3_APB3_master_PRDATA" \ +"PWDATA:FIC3_APB3_master_PWDATA" \ +"PREADY:FIC3_APB3_master_PREADY" \ +"PSLVERR:FIC3_APB3_master_PSLVERR" } + +# Add CoreAPB3_C0_0 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_C0} -instance_name {CoreAPB3_C0_0} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreAPB3_C0_0:APBmslave0} + + + + + +# Add bus interface net connections +sd_connect_pins -sd_name ${sd_name} -pin_names {"APBmslave" "CoreAPB3_C0_0:APBmslave1" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_C0_0:APB3mmaster" "FIC3_APB3_master" } + +# Re-enable auto promotion of pins of type 'pad' +auto_promote_pad_pins -promote_all 1 +# Save the smartDesign +save_smartdesign -sd_name ${sd_name} +# Generate SmartDesign FIC_CONVERTER +generate_component -component_name ${sd_name} diff --git a/script_support/components/H264/H264_DDR_WRITE.tcl b/script_support/components/H264/H264_DDR_WRITE.tcl index 079da01..9c2f5a2 100644 --- a/script_support/components/H264/H264_DDR_WRITE.tcl +++ b/script_support/components/H264/H264_DDR_WRITE.tcl @@ -1,107 +1,119 @@ -# Creating SmartDesign H264_DDR_WRITE -set sd_name {H264_DDR_WRITE} -create_smartdesign -sd_name ${sd_name} - -# Disable auto promotion of pins of type 'pad' -auto_promote_pad_pins -promote_all 0 - -# Create top level Scalar Ports -sd_create_scalar_port -sd_name ${sd_name} -port_name {clr_intr_i} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {data_valid_i} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {ddr_clk_i} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {frame_end_i} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {h264_clk_i} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {h264_encoder_en_i} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {reset_i} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {write_ackn_i} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {write_done_i} -port_direction {IN} - -sd_create_scalar_port -sd_name ${sd_name} -port_name {frm_interrupt_o} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {rdata_rdy_o} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {write_req_o} -port_direction {OUT} - - -# Create top level Bus Ports -sd_create_bus_port -sd_name ${sd_name} -port_name {data_i} -port_direction {IN} -port_range {[7:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {frame_ddr_addr_i} -port_direction {IN} -port_range {[9:0]} - -sd_create_bus_port -sd_name ${sd_name} -port_name {frame_bytes_o} -port_direction {OUT} -port_range {[31:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {frame_index_o} -port_direction {OUT} -port_range {[1:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {rdata_o} -port_direction {OUT} -port_range {[63:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {write_length_o} -port_direction {OUT} -port_range {[7:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {write_start_addr_o} -port_direction {OUT} -port_range {[31:0]} - - -# Add AND2_1 instance -sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_1} - - - -# Add data_packer_h264_0 instance -sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {data_packer_h264} -instance_name {data_packer_h264_0} -# Exporting Parameters of instance data_packer_h264_0 -sd_configure_core_instance -sd_name ${sd_name} -instance_name {data_packer_h264_0} -params {\ -"g_IP_DW:8" \ -"g_OP_DW:64" }\ --validate_rules 0 -sd_save_core_instance_config -sd_name ${sd_name} -instance_name {data_packer_h264_0} -sd_update_instance -sd_name ${sd_name} -instance_name {data_packer_h264_0} - -# Add ddr_write_controller_enc_0 instance -sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {ddr_write_controller_enc} -hdl_file {hdl\ddr_write_controller_enc.v} -instance_name {ddr_write_controller_enc_0} - -# Add video_fifo_0 instance -sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {video_fifo} -instance_name {video_fifo_0} -# Exporting Parameters of instance video_fifo_0 -sd_configure_core_instance -sd_name ${sd_name} -instance_name {video_fifo_0} -params {\ -"g_HALF_EMPTY_THRESHOLD:1280" \ -"g_INPUT_VIDEO_DATA_BIT_WIDTH:64" \ -"g_VIDEO_FIFO_AWIDTH:12" }\ --validate_rules 0 -sd_save_core_instance_config -sd_name ${sd_name} -instance_name {video_fifo_0} -sd_update_instance -sd_name ${sd_name} -instance_name {video_fifo_0} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {video_fifo_0:wfull_o} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {video_fifo_0:wafull_o} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {video_fifo_0:rempty_o} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {video_fifo_0:raempty_o} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {video_fifo_0:rhempty_o} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {video_fifo_0:wdata_count_o} - - - -# Add scalar net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:A" "ddr_write_controller_enc_0:reset_i" "ddr_write_controller_enc_0:wrclk_reset_i" "reset_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:B" "ddr_write_controller_enc_0:fifo_reset_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:Y" "video_fifo_0:rresetn_i" "video_fifo_0:wresetn_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"clr_intr_i" "ddr_write_controller_enc_0:clr_intr_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"data_packer_h264_0:data_valid_i" "data_valid_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"data_packer_h264_0:data_valid_o" "video_fifo_0:wen_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"data_packer_h264_0:frame_end_i" "ddr_write_controller_enc_0:eof_i" "frame_end_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"data_packer_h264_0:reset_i" "ddr_write_controller_enc_0:encoder_en_i" "h264_encoder_en_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"data_packer_h264_0:sys_clk_i" "ddr_write_controller_enc_0:wrclk_i" "h264_clk_i" "video_fifo_0:wclock_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"ddr_clk_i" "ddr_write_controller_enc_0:sys_clk_i" "video_fifo_0:rclock_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"ddr_write_controller_enc_0:frm_interrupt_o" "frm_interrupt_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"ddr_write_controller_enc_0:read_fifo_o" "video_fifo_0:ren_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"ddr_write_controller_enc_0:write_ackn_i" "write_ackn_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"ddr_write_controller_enc_0:write_done_i" "write_done_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"ddr_write_controller_enc_0:write_req_o" "write_req_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"rdata_rdy_o" "video_fifo_0:rdata_rdy_o" } - -# Add bus net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"data_i" "data_packer_h264_0:data_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"data_packer_h264_0:data_o" "video_fifo_0:wdata_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"ddr_write_controller_enc_0:fifo_count_i" "video_fifo_0:rdata_count_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"ddr_write_controller_enc_0:frame_ddr_addr_i" "frame_ddr_addr_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"ddr_write_controller_enc_0:frame_idx_o" "frame_index_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"ddr_write_controller_enc_0:frame_size_o" "frame_bytes_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"ddr_write_controller_enc_0:write_length_o" "write_length_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"ddr_write_controller_enc_0:write_start_addr_o" "write_start_addr_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"rdata_o" "video_fifo_0:rdata_o" } - - -# Re-enable auto promotion of pins of type 'pad' -auto_promote_pad_pins -promote_all 1 -# Save the smartDesign -save_smartdesign -sd_name ${sd_name} -# Generate SmartDesign H264_DDR_WRITE -generate_component -component_name ${sd_name} +# Creating SmartDesign H264_DDR_WRITE +set sd_name {H264_DDR_WRITE} +create_smartdesign -sd_name ${sd_name} + +# Disable auto promotion of pins of type 'pad' +auto_promote_pad_pins -promote_all 0 + +# Create top level Scalar Ports +sd_create_scalar_port -sd_name ${sd_name} -port_name {clr_intr_i} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {data_valid_i} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {ddr_clk_i} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {frame_end_i} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {h264_clk_i} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {h264_encoder_en_i} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {pclk_i} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {reset_i} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {write_ackn_i} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {write_done_i} -port_direction {IN} + +sd_create_scalar_port -sd_name ${sd_name} -port_name {frm_interrupt_o} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {rdata_rdy_o} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {write_req_o} -port_direction {OUT} + + +# Create top level Bus Ports +sd_create_bus_port -sd_name ${sd_name} -port_name {data_i} -port_direction {IN} -port_range {[15:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {frame_ddr_addr_i} -port_direction {IN} -port_range {[9:0]} + +sd_create_bus_port -sd_name ${sd_name} -port_name {frame_bytes_o} -port_direction {OUT} -port_range {[31:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {frame_index_o} -port_direction {OUT} -port_range {[1:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {rdata_o} -port_direction {OUT} -port_range {[63:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {write_length_o} -port_direction {OUT} -port_range {[7:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {write_start_addr_o} -port_direction {OUT} -port_range {[31:0]} + + +sd_create_pin_slices -sd_name ${sd_name} -pin_name {data_i} -pin_slices {[15:8]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {data_i} -pin_slices {[7:0]} +# Add AND2_1 instance +sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_1} + + + +# Add data_packer_h264_0 instance +sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {data_packer_h264} -instance_name {data_packer_h264_0} +# Exporting Parameters of instance data_packer_h264_0 +sd_configure_core_instance -sd_name ${sd_name} -instance_name {data_packer_h264_0} -params {\ +"g_IP_DW:16" \ +"g_OP_DW:64" }\ +-validate_rules 0 +sd_save_core_instance_config -sd_name ${sd_name} -instance_name {data_packer_h264_0} +sd_update_instance -sd_name ${sd_name} -instance_name {data_packer_h264_0} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {data_packer_h264_0:data_i} -pin_slices {[15:8]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {data_packer_h264_0:data_i} -pin_slices {[7:0]} + + + +# Add ddr_write_controller_enc_0 instance +sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {ddr_write_controller_enc} -hdl_file {hdl\ddr_write_controller_enc.v} -instance_name {ddr_write_controller_enc_0} + + + +# Add video_fifo_0 instance +sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {video_fifo} -instance_name {video_fifo_0} +# Exporting Parameters of instance video_fifo_0 +sd_configure_core_instance -sd_name ${sd_name} -instance_name {video_fifo_0} -params {\ +"g_HALF_EMPTY_THRESHOLD:1280" \ +"g_INPUT_VIDEO_DATA_BIT_WIDTH:64" \ +"g_VIDEO_FIFO_AWIDTH:12" }\ +-validate_rules 0 +sd_save_core_instance_config -sd_name ${sd_name} -instance_name {video_fifo_0} +sd_update_instance -sd_name ${sd_name} -instance_name {video_fifo_0} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {video_fifo_0:wfull_o} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {video_fifo_0:wafull_o} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {video_fifo_0:rempty_o} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {video_fifo_0:raempty_o} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {video_fifo_0:rhempty_o} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {video_fifo_0:wdata_count_o} + + + +# Add scalar net connections +sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:A" "ddr_write_controller_enc_0:reset_i" "ddr_write_controller_enc_0:wrclk_reset_i" "reset_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:B" "ddr_write_controller_enc_0:fifo_reset_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:Y" "video_fifo_0:rresetn_i" "video_fifo_0:wresetn_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"clr_intr_i" "ddr_write_controller_enc_0:clr_intr_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"data_packer_h264_0:data_valid_i" "data_valid_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"data_packer_h264_0:data_valid_o" "video_fifo_0:wen_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"data_packer_h264_0:frame_end_i" "frame_end_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"data_packer_h264_0:frame_end_o" "ddr_write_controller_enc_0:eof_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"data_packer_h264_0:reset_i" "ddr_write_controller_enc_0:encoder_en_i" "h264_encoder_en_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"data_packer_h264_0:sys_clk_i" "ddr_write_controller_enc_0:wrclk_i" "h264_clk_i" "video_fifo_0:wclock_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"ddr_clk_i" "ddr_write_controller_enc_0:sys_clk_i" "video_fifo_0:rclock_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"ddr_write_controller_enc_0:frm_interrupt_o" "frm_interrupt_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"ddr_write_controller_enc_0:pclk_i" "pclk_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"ddr_write_controller_enc_0:read_fifo_o" "video_fifo_0:ren_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"ddr_write_controller_enc_0:write_ackn_i" "write_ackn_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"ddr_write_controller_enc_0:write_done_i" "write_done_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"ddr_write_controller_enc_0:write_req_o" "write_req_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"rdata_rdy_o" "video_fifo_0:rdata_rdy_o" } + +# Add bus net connections +sd_connect_pins -sd_name ${sd_name} -pin_names {"data_i[15:8]" "data_packer_h264_0:data_i[7:0]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"data_i[7:0]" "data_packer_h264_0:data_i[15:8]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"data_packer_h264_0:data_o" "video_fifo_0:wdata_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"ddr_write_controller_enc_0:fifo_count_i" "video_fifo_0:rdata_count_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"ddr_write_controller_enc_0:frame_ddr_addr_i" "frame_ddr_addr_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"ddr_write_controller_enc_0:frame_idx_o" "frame_index_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"ddr_write_controller_enc_0:frame_size_o" "frame_bytes_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"ddr_write_controller_enc_0:write_length_o" "write_length_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"ddr_write_controller_enc_0:write_start_addr_o" "write_start_addr_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"rdata_o" "video_fifo_0:rdata_o" } + + +# Re-enable auto promotion of pins of type 'pad' +auto_promote_pad_pins -promote_all 1 +# Save the smartDesign +save_smartdesign -sd_name ${sd_name} +# Generate SmartDesign H264_DDR_WRITE +generate_component -component_name ${sd_name} diff --git a/script_support/components/H264/H264_Iframe_Encoder_C0.tcl b/script_support/components/H264/H264_Iframe_Encoder_C0.tcl index 407c68c..54f8354 100644 --- a/script_support/components/H264/H264_Iframe_Encoder_C0.tcl +++ b/script_support/components/H264/H264_Iframe_Encoder_C0.tcl @@ -1,8 +1,8 @@ -# Exporting Component Description of H264_Iframe_Encoder_C0 to TCL -# Family: PolarFireSoC -# Part Number: MPFS250T_ES-1FCG1152E -# Create and Configure the core component H264_Iframe_Encoder_C0 -create_and_configure_core -core_vlnv {Microchip:SolutionCore:H264_Iframe_Encoder:1.3.0} -component_name {H264_Iframe_Encoder_C0} -params {\ -"G_C_TYPE:1" \ -"G_DW:8" } -# Exporting Component Description of H264_Iframe_Encoder_C0 to TCL done +# Exporting Component Description of H264_Iframe_Encoder_C0 to TCL +# Family: PolarFireSoC +# Part Number: MPFS250T_ES-1FCG1152E +# Create and Configure the core component H264_Iframe_Encoder_C0 +create_and_configure_core -core_vlnv {Microchip:SolutionCore:H264_Iframe_Encoder:1.4.0} -component_name {H264_Iframe_Encoder_C0} -params {\ +"G_C_TYPE:1" \ +"G_DW:8" } +# Exporting Component Description of H264_Iframe_Encoder_C0 to TCL done diff --git a/script_support/components/H264/RGBtoYCbCr_C0.tcl b/script_support/components/H264/RGBtoYCbCr_C0.tcl index b0bd255..010f0e8 100644 --- a/script_support/components/H264/RGBtoYCbCr_C0.tcl +++ b/script_support/components/H264/RGBtoYCbCr_C0.tcl @@ -1,10 +1,10 @@ -# Exporting Component Description of RGBtoYCbCr_C0 to TCL -# Family: PolarFireSoC -# Part Number: MPFS250T_ES-1FCG1152E -# Create and Configure the core component RGBtoYCbCr_C0 -create_and_configure_core -core_vlnv {Microsemi:SolutionCore:RGBtoYCbCr:4.4.0} -component_name {RGBtoYCbCr_C0} -params {\ -"G_FORMAT:0" \ -"G_RGB_DATA_BIT_WIDTH:8" \ -"G_YCbCr_DATA_BIT_WIDTH:8" \ -"G_YCbCr_FORMAT:2" } -# Exporting Component Description of RGBtoYCbCr_C0 to TCL done +# Exporting Component Description of RGBtoYCbCr_C0 to TCL +# Family: PolarFireSoC +# Part Number: MPFS250T_ES-1FCG1152E +# Create and Configure the core component RGBtoYCbCr_C0 +create_and_configure_core -core_vlnv {Microsemi:SolutionCore:RGBtoYCbCr:4.4.0} -component_name {RGBtoYCbCr_C0} -params {\ +"G_FORMAT:0" \ +"G_RGB_DATA_BIT_WIDTH:8" \ +"G_YCbCr_DATA_BIT_WIDTH:8" \ +"G_YCbCr_FORMAT:2" } +# Exporting Component Description of RGBtoYCbCr_C0 to TCL done diff --git a/script_support/components/H264/SEVPFSOC_H264.tcl b/script_support/components/H264/VKPFSOC_H264.tcl similarity index 98% rename from script_support/components/H264/SEVPFSOC_H264.tcl rename to script_support/components/H264/VKPFSOC_H264.tcl index 930d9c8..b3b7c77 100644 --- a/script_support/components/H264/SEVPFSOC_H264.tcl +++ b/script_support/components/H264/VKPFSOC_H264.tcl @@ -1,249 +1,249 @@ -# Creating SmartDesign SEVPFSOC_TOP -set sd_name {SEVPFSOC_TOP} -create_smartdesign -sd_name ${sd_name} - -# Disable auto promotion of pins of type 'pad' -auto_promote_pad_pins -promote_all 0 - -# Create top level Scalar Ports -sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_RX_CLK_N} -port_direction {IN} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_RX_CLK_P} -port_direction {IN} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {MMUART_0_RXD_F2M} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {MMUART_1_RXD_F2M} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {REFCLK_N} -port_direction {IN} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {REFCLK} -port_direction {IN} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_N} -port_direction {IN} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_P} -port_direction {IN} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {SD_CD_EMMC_STRB} -port_direction {IN} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {SD_WP_EMMC_RSTN} -port_direction {IN} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {SGMII_RX0_N} -port_direction {IN} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {SGMII_RX0_P} -port_direction {IN} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {SGMII_RX1_N} -port_direction {IN} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {SGMII_RX1_P} -port_direction {IN} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {USB_CLK} -port_direction {IN} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {USB_DIR} -port_direction {IN} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {USB_NXT} -port_direction {IN} -port_is_pad {1} - -sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_RST} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_CLK_EN} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {CKE} -port_direction {OUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {CK_N} -port_direction {OUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {CK} -port_direction {OUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {CS} -port_direction {OUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {LED2} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {LED3} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {MAC_0_MDC} -port_direction {OUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {MMUART_0_TXD_M2F} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {MMUART_1_TXD_M2F} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {ODT} -port_direction {OUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {RESET_N} -port_direction {OUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {SDIO_SW_EN_N} -port_direction {OUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {SDIO_SW_SEL0} -port_direction {OUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {SDIO_SW_SEL1} -port_direction {OUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {SD_CLK_EMMC_CLK} -port_direction {OUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {SD_POW_EMMC_DATA4} -port_direction {OUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {SD_VOLT_CMD_DIR_EMMC_DATA7} -port_direction {OUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {SD_VOLT_DIR_0_EMMC_UNUSED} -port_direction {OUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {SD_VOLT_DIR_1_3_EMMC_UNUSED} -port_direction {OUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {SD_VOLT_EN_EMMC_DATA6} -port_direction {OUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {SD_VOLT_SEL_EMMC_DATA5} -port_direction {OUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {SGMII_TX0_N} -port_direction {OUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {SGMII_TX0_P} -port_direction {OUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {SGMII_TX1_N} -port_direction {OUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {SGMII_TX1_P} -port_direction {OUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TEN} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {USB_STP} -port_direction {OUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {USB_ULPI_RESET_N} -port_direction {OUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {VSC_8662_CMODE3} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {VSC_8662_CMODE4} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {VSC_8662_CMODE5} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {VSC_8662_CMODE6} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {VSC_8662_CMODE7} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {VSC_8662_RESETN} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {VSC_8662_SRESET} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {cam1inck} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {cam1xmaster} -port_direction {OUT} - -sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_SCL} -port_direction {INOUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_SDA} -port_direction {INOUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {MAC_0_MDIO} -port_direction {INOUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {SD_CMD_EMMC_CMD} -port_direction {INOUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {SD_DATA0_EMMC_DATA0} -port_direction {INOUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {SD_DATA1_EMMC_DATA1} -port_direction {INOUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {SD_DATA2_EMMC_DATA2} -port_direction {INOUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {SD_DATA3_EMMC_DATA3} -port_direction {INOUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {USB_DATA0} -port_direction {INOUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {USB_DATA1} -port_direction {INOUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {USB_DATA2} -port_direction {INOUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {USB_DATA3} -port_direction {INOUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {USB_DATA4} -port_direction {INOUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {USB_DATA5} -port_direction {INOUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {USB_DATA6} -port_direction {INOUT} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {USB_DATA7} -port_direction {INOUT} -port_is_pad {1} - -# Create top level Bus Ports -sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_RXD_N} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1} -sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_RXD} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1} - -sd_create_bus_port -sd_name ${sd_name} -port_name {CA} -port_direction {OUT} -port_range {[5:0]} -port_is_pad {1} -sd_create_bus_port -sd_name ${sd_name} -port_name {DM} -port_direction {OUT} -port_range {[3:0]} -port_is_pad {1} - -sd_create_bus_port -sd_name ${sd_name} -port_name {DQS_N} -port_direction {INOUT} -port_range {[3:0]} -port_is_pad {1} -sd_create_bus_port -sd_name ${sd_name} -port_name {DQS} -port_direction {INOUT} -port_range {[3:0]} -port_is_pad {1} -sd_create_bus_port -sd_name ${sd_name} -port_name {DQ} -port_direction {INOUT} -port_range {[31:0]} -port_is_pad {1} - -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {TEN} -value {GND} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {VSC_8662_CMODE3} -value {GND} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {VSC_8662_CMODE4} -value {GND} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {VSC_8662_CMODE5} -value {GND} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {VSC_8662_CMODE6} -value {VCC} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {VSC_8662_CMODE7} -value {GND} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {VSC_8662_SRESET} -value {VCC} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {cam1inck} -value {GND} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {cam1xmaster} -value {GND} -# Add BIBUF_1 instance -sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {BIBUF_1} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BIBUF_1:D} -value {GND} - - - -# Add BIBUF_2 instance -sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {BIBUF_2} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BIBUF_2:D} -value {GND} - - - -# Add CLOCKS_AND_RESETS instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CLOCKS_AND_RESETS} -instance_name {CLOCKS_AND_RESETS} - - - -# Add FIC_CONVERTER_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {FIC_CONVERTER} -instance_name {FIC_CONVERTER_0} - - - -# Add MSS instance -sd_instantiate_component -sd_name ${sd_name} -component_name {MSS_SEV} -instance_name {MSS} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MSS:MSS_INT_F2M} -pin_slices {[0:0]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MSS:MSS_INT_F2M} -pin_slices {[63:1]} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MSS:MSS_INT_F2M[63:1]} -value {GND} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MSS:GPIO_2_F2M_25} -value {VCC} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MSS:FIC_3_DLL_LOCK_M2F} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MSS:FIC_3_APB_M_PSTRB} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MSS:MMUART_0_TXD_OE_M2F} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MSS:MMUART_1_TXD_OE_M2F} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MSS:GPIO_2_M2F_3} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MSS:GPIO_2_M2F_2} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MSS:GPIO_2_M2F_1} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MSS:MSS_INT_M2F} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MSS:PLL_CPU_LOCK_M2F} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MSS:PLL_DDR_LOCK_M2F} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MSS:PLL_SGMII_LOCK_M2F} - - - -# Add Video_Pipeline_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {Video_Pipeline} -instance_name {Video_Pipeline_0} - - - -# Add scalar net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_1:E" "MSS:I2C_0_SCL_OE_M2F" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_1:PAD" "CAM1_SCL" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_1:Y" "MSS:I2C_0_SCL_F2M" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_2:E" "MSS:I2C_0_SDA_OE_M2F" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_2:PAD" "CAM1_SDA" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_2:Y" "MSS:I2C_0_SDA_F2M" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RST" "MSS:GPIO_2_M2F_8" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RX_CLK_N" "Video_Pipeline_0:CAM1_RX_CLK_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RX_CLK_P" "Video_Pipeline_0:CAM1_RX_CLK_P" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_CLK_EN" "MSS:GPIO_2_M2F_9" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CK" "MSS:CK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CKE" "MSS:CKE" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CK_N" "MSS:CK_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:CLK_125MHz" "MSS:FIC_1_ACLK" "Video_Pipeline_0:CLK_125MHz_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:CLK_50MHz" "MSS:FIC_3_PCLK" "Video_Pipeline_0:CLK_50MHz_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:DEVICE_INIT_DONE" "Video_Pipeline_0:INIT_DONE" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:EXT_RST_N" "MSS:MSS_RESET_N_M2F" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FABRIC_POR_N" "MSS:MSS_RESET_N_F2M" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:I2C_BCLK" "MSS:I2C_0_BCLK_F2M" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:MSS_PLL_LOCKS" "MSS:FIC_1_DLL_LOCK_M2F" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:REF_CLK_PAD_N" "REF_CLK_PAD_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:REF_CLK_PAD_P" "REF_CLK_PAD_P" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:RESETN_125MHz" "VSC_8662_RESETN" "Video_Pipeline_0:RESETN_125MHz_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:RESETN_50MHz" "Video_Pipeline_0:RESETN_50MHz_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CS" "MSS:CS" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"LED2" "MSS:GPIO_2_M2F_18" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"LED3" "MSS:GPIO_2_M2F_19" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MAC_0_MDC" "MSS:MAC_0_MDC" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MAC_0_MDIO" "MSS:MAC_0_MDIO" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MMUART_0_RXD_F2M" "MSS:MMUART_0_RXD_F2M" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MMUART_0_TXD_M2F" "MSS:MMUART_0_TXD_M2F" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MMUART_1_RXD_F2M" "MSS:MMUART_1_RXD_F2M" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MMUART_1_TXD_M2F" "MSS:MMUART_1_TXD_M2F" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:GPIO_1_12_OUT" "USB_ULPI_RESET_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:GPIO_1_16_OUT" "SDIO_SW_SEL0" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:GPIO_1_20_OUT" "SDIO_SW_SEL1" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:GPIO_1_23_OUT" "SDIO_SW_EN_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:GPIO_2_M2F_4" "Video_Pipeline_0:LPDDR4_RDY_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:MSS_INT_F2M[0:0]" "Video_Pipeline_0:frm_interrupt_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:ODT" "ODT" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:REFCLK" "REFCLK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:REFCLK_N" "REFCLK_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:RESET_N" "RESET_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SD_CD_EMMC_STRB" "SD_CD_EMMC_STRB" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SD_CLK_EMMC_CLK" "SD_CLK_EMMC_CLK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SD_CMD_EMMC_CMD" "SD_CMD_EMMC_CMD" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SD_DATA0_EMMC_DATA0" "SD_DATA0_EMMC_DATA0" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SD_DATA1_EMMC_DATA1" "SD_DATA1_EMMC_DATA1" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SD_DATA2_EMMC_DATA2" "SD_DATA2_EMMC_DATA2" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SD_DATA3_EMMC_DATA3" "SD_DATA3_EMMC_DATA3" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SD_POW_EMMC_DATA4" "SD_POW_EMMC_DATA4" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SD_VOLT_CMD_DIR_EMMC_DATA7" "SD_VOLT_CMD_DIR_EMMC_DATA7" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SD_VOLT_DIR_0_EMMC_UNUSED" "SD_VOLT_DIR_0_EMMC_UNUSED" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SD_VOLT_DIR_1_3_EMMC_UNUSED" "SD_VOLT_DIR_1_3_EMMC_UNUSED" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SD_VOLT_EN_EMMC_DATA6" "SD_VOLT_EN_EMMC_DATA6" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SD_VOLT_SEL_EMMC_DATA5" "SD_VOLT_SEL_EMMC_DATA5" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SD_WP_EMMC_RSTN" "SD_WP_EMMC_RSTN" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SGMII_RX0_N" "SGMII_RX0_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SGMII_RX0_P" "SGMII_RX0_P" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SGMII_RX1_N" "SGMII_RX1_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SGMII_RX1_P" "SGMII_RX1_P" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SGMII_TX0_N" "SGMII_TX0_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SGMII_TX0_P" "SGMII_TX0_P" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SGMII_TX1_N" "SGMII_TX1_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SGMII_TX1_P" "SGMII_TX1_P" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:USB_CLK" "USB_CLK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:USB_DATA0" "USB_DATA0" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:USB_DATA1" "USB_DATA1" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:USB_DATA2" "USB_DATA2" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:USB_DATA3" "USB_DATA3" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:USB_DATA4" "USB_DATA4" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:USB_DATA5" "USB_DATA5" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:USB_DATA6" "USB_DATA6" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:USB_DATA7" "USB_DATA7" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:USB_DIR" "USB_DIR" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:USB_NXT" "USB_NXT" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:USB_STP" "USB_STP" } - -# Add bus net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"CA" "MSS:CA" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RXD" "Video_Pipeline_0:CAM1_RXD" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RXD_N" "Video_Pipeline_0:CAM1_RXD_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"DM" "MSS:DM" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"DQ" "MSS:DQ" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"DQS" "MSS:DQS" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"DQS_N" "MSS:DQS_N" } - -# Add bus interface net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"FIC_CONVERTER_0:APBmslave" "Video_Pipeline_0:APBslave" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"FIC_CONVERTER_0:FIC3_APB3_master" "MSS:FIC_3_APB_INITIATOR" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:FIC_1_AXI4_TARGET" "Video_Pipeline_0:BIF_1" } - -# Re-enable auto promotion of pins of type 'pad' -auto_promote_pad_pins -promote_all 1 -# Save the smartDesign -save_smartdesign -sd_name ${sd_name} -# Generate SmartDesign SEVPFSOC_TOP -generate_component -component_name ${sd_name} +# Creating SmartDesign VKPFSOC_TOP +set sd_name {VKPFSOC_TOP} +create_smartdesign -sd_name ${sd_name} + +# Disable auto promotion of pins of type 'pad' +auto_promote_pad_pins -promote_all 0 + +# Create top level Scalar Ports +sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_RX_CLK_N} -port_direction {IN} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_RX_CLK_P} -port_direction {IN} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {MMUART_0_RXD_F2M} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {MMUART_1_RXD_F2M} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {REFCLK_N} -port_direction {IN} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {REFCLK} -port_direction {IN} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_N} -port_direction {IN} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_P} -port_direction {IN} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {SD_CD_EMMC_STRB} -port_direction {IN} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {SD_WP_EMMC_RSTN} -port_direction {IN} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {SGMII_RX0_N} -port_direction {IN} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {SGMII_RX0_P} -port_direction {IN} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {SGMII_RX1_N} -port_direction {IN} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {SGMII_RX1_P} -port_direction {IN} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {USB_CLK} -port_direction {IN} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {USB_DIR} -port_direction {IN} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {USB_NXT} -port_direction {IN} -port_is_pad {1} + +sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_RST} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_CLK_EN} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {CKE} -port_direction {OUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {CK_N} -port_direction {OUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {CK} -port_direction {OUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {CS} -port_direction {OUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {LED2} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {LED3} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {MAC_0_MDC} -port_direction {OUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {MMUART_0_TXD_M2F} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {MMUART_1_TXD_M2F} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {ODT} -port_direction {OUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {RESET_N} -port_direction {OUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {SDIO_SW_EN_N} -port_direction {OUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {SDIO_SW_SEL0} -port_direction {OUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {SDIO_SW_SEL1} -port_direction {OUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {SD_CLK_EMMC_CLK} -port_direction {OUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {SD_POW_EMMC_DATA4} -port_direction {OUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {SD_VOLT_CMD_DIR_EMMC_DATA7} -port_direction {OUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {SD_VOLT_DIR_0_EMMC_UNUSED} -port_direction {OUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {SD_VOLT_DIR_1_3_EMMC_UNUSED} -port_direction {OUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {SD_VOLT_EN_EMMC_DATA6} -port_direction {OUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {SD_VOLT_SEL_EMMC_DATA5} -port_direction {OUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {SGMII_TX0_N} -port_direction {OUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {SGMII_TX0_P} -port_direction {OUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {SGMII_TX1_N} -port_direction {OUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {SGMII_TX1_P} -port_direction {OUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {TEN} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {USB_STP} -port_direction {OUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {USB_ULPI_RESET_N} -port_direction {OUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {VSC_8662_CMODE3} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {VSC_8662_CMODE4} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {VSC_8662_CMODE5} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {VSC_8662_CMODE6} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {VSC_8662_CMODE7} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {VSC_8662_RESETN} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {VSC_8662_SRESET} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {cam1inck} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {cam1xmaster} -port_direction {OUT} + +sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_SCL} -port_direction {INOUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_SDA} -port_direction {INOUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {MAC_0_MDIO} -port_direction {INOUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {SD_CMD_EMMC_CMD} -port_direction {INOUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {SD_DATA0_EMMC_DATA0} -port_direction {INOUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {SD_DATA1_EMMC_DATA1} -port_direction {INOUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {SD_DATA2_EMMC_DATA2} -port_direction {INOUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {SD_DATA3_EMMC_DATA3} -port_direction {INOUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {USB_DATA0} -port_direction {INOUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {USB_DATA1} -port_direction {INOUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {USB_DATA2} -port_direction {INOUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {USB_DATA3} -port_direction {INOUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {USB_DATA4} -port_direction {INOUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {USB_DATA5} -port_direction {INOUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {USB_DATA6} -port_direction {INOUT} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {USB_DATA7} -port_direction {INOUT} -port_is_pad {1} + +# Create top level Bus Ports +sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_RXD_N} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1} +sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_RXD} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1} + +sd_create_bus_port -sd_name ${sd_name} -port_name {CA} -port_direction {OUT} -port_range {[5:0]} -port_is_pad {1} +sd_create_bus_port -sd_name ${sd_name} -port_name {DM} -port_direction {OUT} -port_range {[3:0]} -port_is_pad {1} + +sd_create_bus_port -sd_name ${sd_name} -port_name {DQS_N} -port_direction {INOUT} -port_range {[3:0]} -port_is_pad {1} +sd_create_bus_port -sd_name ${sd_name} -port_name {DQS} -port_direction {INOUT} -port_range {[3:0]} -port_is_pad {1} +sd_create_bus_port -sd_name ${sd_name} -port_name {DQ} -port_direction {INOUT} -port_range {[31:0]} -port_is_pad {1} + +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {TEN} -value {GND} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {VSC_8662_CMODE3} -value {GND} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {VSC_8662_CMODE4} -value {GND} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {VSC_8662_CMODE5} -value {GND} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {VSC_8662_CMODE6} -value {VCC} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {VSC_8662_CMODE7} -value {GND} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {VSC_8662_SRESET} -value {VCC} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {cam1inck} -value {GND} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {cam1xmaster} -value {GND} +# Add BIBUF_1 instance +sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {BIBUF_1} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BIBUF_1:D} -value {GND} + + + +# Add BIBUF_2 instance +sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {BIBUF_2} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BIBUF_2:D} -value {GND} + + + +# Add CLOCKS_AND_RESETS instance +sd_instantiate_component -sd_name ${sd_name} -component_name {CLOCKS_AND_RESETS} -instance_name {CLOCKS_AND_RESETS} + + + +# Add FIC_CONVERTER_0 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {FIC_CONVERTER} -instance_name {FIC_CONVERTER_0} + + + +# Add MSS instance +sd_instantiate_component -sd_name ${sd_name} -component_name {MSS_VIDEO_KIT} -instance_name {MSS} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {MSS:MSS_INT_F2M} -pin_slices {[0:0]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {MSS:MSS_INT_F2M} -pin_slices {[63:1]} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MSS:MSS_INT_F2M[63:1]} -value {GND} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MSS:GPIO_2_F2M_25} -value {VCC} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MSS:FIC_3_DLL_LOCK_M2F} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MSS:FIC_3_APB_M_PSTRB} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MSS:MMUART_0_TXD_OE_M2F} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MSS:MMUART_1_TXD_OE_M2F} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MSS:GPIO_2_M2F_3} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MSS:GPIO_2_M2F_2} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MSS:GPIO_2_M2F_1} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MSS:MSS_INT_M2F} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MSS:PLL_CPU_LOCK_M2F} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MSS:PLL_DDR_LOCK_M2F} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MSS:PLL_SGMII_LOCK_M2F} + + + +# Add Video_Pipeline_0 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {Video_Pipeline} -instance_name {Video_Pipeline_0} + + + +# Add scalar net connections +sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_1:E" "MSS:I2C_0_SCL_OE_M2F" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_1:PAD" "CAM1_SCL" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_1:Y" "MSS:I2C_0_SCL_F2M" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_2:E" "MSS:I2C_0_SDA_OE_M2F" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_2:PAD" "CAM1_SDA" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_2:Y" "MSS:I2C_0_SDA_F2M" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RST" "MSS:GPIO_2_M2F_8" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RX_CLK_N" "Video_Pipeline_0:CAM1_RX_CLK_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RX_CLK_P" "Video_Pipeline_0:CAM1_RX_CLK_P" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_CLK_EN" "MSS:GPIO_2_M2F_9" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CK" "MSS:CK" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CKE" "MSS:CKE" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CK_N" "MSS:CK_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:CLK_125MHz" "MSS:FIC_1_ACLK" "Video_Pipeline_0:CLK_125MHz_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:CLK_50MHz" "MSS:FIC_3_PCLK" "Video_Pipeline_0:CLK_50MHz_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:DEVICE_INIT_DONE" "Video_Pipeline_0:INIT_DONE" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:EXT_RST_N" "MSS:MSS_RESET_N_M2F" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FABRIC_POR_N" "MSS:MSS_RESET_N_F2M" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:I2C_BCLK" "MSS:I2C_0_BCLK_F2M" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:MSS_PLL_LOCKS" "MSS:FIC_1_DLL_LOCK_M2F" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:REF_CLK_PAD_N" "REF_CLK_PAD_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:REF_CLK_PAD_P" "REF_CLK_PAD_P" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:RESETN_125MHz" "VSC_8662_RESETN" "Video_Pipeline_0:RESETN_125MHz_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:RESETN_50MHz" "Video_Pipeline_0:RESETN_50MHz_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CS" "MSS:CS" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"LED2" "MSS:GPIO_2_M2F_18" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"LED3" "MSS:GPIO_2_M2F_19" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MAC_0_MDC" "MSS:MAC_0_MDC" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MAC_0_MDIO" "MSS:MAC_0_MDIO" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MMUART_0_RXD_F2M" "MSS:MMUART_0_RXD_F2M" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MMUART_0_TXD_M2F" "MSS:MMUART_0_TXD_M2F" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MMUART_1_RXD_F2M" "MSS:MMUART_1_RXD_F2M" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MMUART_1_TXD_M2F" "MSS:MMUART_1_TXD_M2F" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:GPIO_1_12_OUT" "USB_ULPI_RESET_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:GPIO_1_16_OUT" "SDIO_SW_SEL0" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:GPIO_1_20_OUT" "SDIO_SW_SEL1" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:GPIO_1_23_OUT" "SDIO_SW_EN_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:GPIO_2_M2F_4" "Video_Pipeline_0:LPDDR4_RDY_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:MSS_INT_F2M[0:0]" "Video_Pipeline_0:frm_interrupt_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:ODT" "ODT" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:REFCLK" "REFCLK" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:REFCLK_N" "REFCLK_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:RESET_N" "RESET_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SD_CD_EMMC_STRB" "SD_CD_EMMC_STRB" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SD_CLK_EMMC_CLK" "SD_CLK_EMMC_CLK" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SD_CMD_EMMC_CMD" "SD_CMD_EMMC_CMD" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SD_DATA0_EMMC_DATA0" "SD_DATA0_EMMC_DATA0" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SD_DATA1_EMMC_DATA1" "SD_DATA1_EMMC_DATA1" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SD_DATA2_EMMC_DATA2" "SD_DATA2_EMMC_DATA2" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SD_DATA3_EMMC_DATA3" "SD_DATA3_EMMC_DATA3" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SD_POW_EMMC_DATA4" "SD_POW_EMMC_DATA4" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SD_VOLT_CMD_DIR_EMMC_DATA7" "SD_VOLT_CMD_DIR_EMMC_DATA7" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SD_VOLT_DIR_0_EMMC_UNUSED" "SD_VOLT_DIR_0_EMMC_UNUSED" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SD_VOLT_DIR_1_3_EMMC_UNUSED" "SD_VOLT_DIR_1_3_EMMC_UNUSED" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SD_VOLT_EN_EMMC_DATA6" "SD_VOLT_EN_EMMC_DATA6" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SD_VOLT_SEL_EMMC_DATA5" "SD_VOLT_SEL_EMMC_DATA5" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SD_WP_EMMC_RSTN" "SD_WP_EMMC_RSTN" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SGMII_RX0_N" "SGMII_RX0_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SGMII_RX0_P" "SGMII_RX0_P" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SGMII_RX1_N" "SGMII_RX1_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SGMII_RX1_P" "SGMII_RX1_P" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SGMII_TX0_N" "SGMII_TX0_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SGMII_TX0_P" "SGMII_TX0_P" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SGMII_TX1_N" "SGMII_TX1_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:SGMII_TX1_P" "SGMII_TX1_P" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:USB_CLK" "USB_CLK" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:USB_DATA0" "USB_DATA0" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:USB_DATA1" "USB_DATA1" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:USB_DATA2" "USB_DATA2" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:USB_DATA3" "USB_DATA3" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:USB_DATA4" "USB_DATA4" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:USB_DATA5" "USB_DATA5" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:USB_DATA6" "USB_DATA6" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:USB_DATA7" "USB_DATA7" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:USB_DIR" "USB_DIR" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:USB_NXT" "USB_NXT" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:USB_STP" "USB_STP" } + +# Add bus net connections +sd_connect_pins -sd_name ${sd_name} -pin_names {"CA" "MSS:CA" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RXD" "Video_Pipeline_0:CAM1_RXD" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RXD_N" "Video_Pipeline_0:CAM1_RXD_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"DM" "MSS:DM" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"DQ" "MSS:DQ" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"DQS" "MSS:DQS" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"DQS_N" "MSS:DQS_N" } + +# Add bus interface net connections +sd_connect_pins -sd_name ${sd_name} -pin_names {"FIC_CONVERTER_0:APBmslave" "Video_Pipeline_0:APBslave" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"FIC_CONVERTER_0:FIC3_APB3_master" "MSS:FIC_3_APB_INITIATOR" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:FIC_1_AXI4_TARGET" "Video_Pipeline_0:BIF_1" } + +# Re-enable auto promotion of pins of type 'pad' +auto_promote_pad_pins -promote_all 1 +# Save the smartDesign +save_smartdesign -sd_name ${sd_name} +# Generate SmartDesign VKPFSOC_TOP +generate_component -component_name ${sd_name} diff --git a/script_support/components/H264/Video_Pipeline.tcl b/script_support/components/H264/Video_Pipeline.tcl index 5ba6e8f..ba6e1a1 100644 --- a/script_support/components/H264/Video_Pipeline.tcl +++ b/script_support/components/H264/Video_Pipeline.tcl @@ -1,221 +1,224 @@ -# Creating SmartDesign Video_Pipeline -set sd_name {Video_Pipeline} -create_smartdesign -sd_name ${sd_name} - -# Disable auto promotion of pins of type 'pad' -auto_promote_pad_pins -promote_all 0 - -# Create top level Scalar Ports -sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_RX_CLK_N} -port_direction {IN} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_RX_CLK_P} -port_direction {IN} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK_125MHz_i} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK_50MHz_i} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {INIT_DONE} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {LPDDR4_RDY_i} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {RESETN_125MHz_i} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {RESETN_50MHz_i} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {arready} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {awready} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {bvalid} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {penable_i} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {psel_i} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {pwrite_i} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {rlast} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {rvalid} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {wready} -port_direction {IN} - -sd_create_scalar_port -sd_name ${sd_name} -port_name {arvalid} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {awvalid} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {bready} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {frm_interrupt_o} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {pready_o} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {pslverr_o} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {rready} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {wlast} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {wvalid} -port_direction {OUT} - - -# Create top level Bus Ports -sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_RXD_N} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1} -sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_RXD} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1} -sd_create_bus_port -sd_name ${sd_name} -port_name {bid} -port_direction {IN} -port_range {[3:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {bresp} -port_direction {IN} -port_range {[1:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {paddr_i} -port_direction {IN} -port_range {[31:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {pwdata_i} -port_direction {IN} -port_range {[31:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {rdata} -port_direction {IN} -port_range {[63:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {rid} -port_direction {IN} -port_range {[3:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {rresp} -port_direction {IN} -port_range {[1:0]} - -sd_create_bus_port -sd_name ${sd_name} -port_name {araddr} -port_direction {OUT} -port_range {[31:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {arburst} -port_direction {OUT} -port_range {[1:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {arcache} -port_direction {OUT} -port_range {[3:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {arid} -port_direction {OUT} -port_range {[3:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {arlen} -port_direction {OUT} -port_range {[7:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {arlock} -port_direction {OUT} -port_range {[1:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {arprot} -port_direction {OUT} -port_range {[2:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {arsize} -port_direction {OUT} -port_range {[2:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {awaddr} -port_direction {OUT} -port_range {[31:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {awburst} -port_direction {OUT} -port_range {[1:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {awcache} -port_direction {OUT} -port_range {[3:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {awid} -port_direction {OUT} -port_range {[3:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {awlen} -port_direction {OUT} -port_range {[7:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {awlock} -port_direction {OUT} -port_range {[1:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {awprot} -port_direction {OUT} -port_range {[2:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {awsize} -port_direction {OUT} -port_range {[2:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {prdata_o} -port_direction {OUT} -port_range {[31:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {wdata} -port_direction {OUT} -port_range {[63:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {wstrb} -port_direction {OUT} -port_range {[63:0]} - - -# Create top level Bus interface Ports -sd_create_bif_port -sd_name ${sd_name} -port_name {APBslave} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {slave} -port_bif_mapping {\ -"PADDR:paddr_i" \ -"PSELx:psel_i" \ -"PENABLE:penable_i" \ -"PWRITE:pwrite_i" \ -"PRDATA:prdata_o" \ -"PWDATA:pwdata_i" \ -"PREADY:pready_o" \ -"PSLVERR:pslverr_o" } - -sd_create_bif_port -sd_name ${sd_name} -port_name {BIF_1} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {mirroredSlave} -port_bif_mapping {\ -"AWID:awid" \ -"AWADDR:awaddr" \ -"AWLEN:awlen" \ -"AWSIZE:awsize" \ -"AWBURST:awburst" \ -"AWLOCK:awlock" \ -"AWCACHE:awcache" \ -"AWPROT:awprot" \ -"AWVALID:awvalid" \ -"AWREADY:awready" \ -"WDATA:wdata" \ -"WSTRB:wstrb" \ -"WLAST:wlast" \ -"WVALID:wvalid" \ -"WREADY:wready" \ -"BID:bid" \ -"BRESP:bresp" \ -"BVALID:bvalid" \ -"BREADY:bready" \ -"ARID:arid" \ -"ARADDR:araddr" \ -"ARLEN:arlen" \ -"ARSIZE:arsize" \ -"ARBURST:arburst" \ -"ARLOCK:arlock" \ -"ARCACHE:arcache" \ -"ARPROT:arprot" \ -"ARVALID:arvalid" \ -"ARREADY:arready" \ -"RID:rid" \ -"RDATA:rdata" \ -"RRESP:rresp" \ -"RLAST:rlast" \ -"RVALID:rvalid" \ -"RREADY:rready" } - -# Add apb3_if_0 instance -sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {apb3_if} -instance_name {apb3_if_0} -# Exporting Parameters of instance apb3_if_0 -sd_configure_core_instance -sd_name ${sd_name} -instance_name {apb3_if_0} -params {\ -"g_APB3_IF_DATA_WIDTH:32" \ -"g_CONST_WIDTH:12" }\ --validate_rules 0 -sd_save_core_instance_config -sd_name ${sd_name} -instance_name {apb3_if_0} -sd_update_instance -sd_name ${sd_name} -instance_name {apb3_if_0} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {apb3_if_0:quality_o} -pin_slices {[5:0]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {apb3_if_0:quality_o} -pin_slices {[7:6]} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:quality_o[7:6]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {apb3_if_0:h264_ddrlsb_addr_o} -pin_slices {[21:0]} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:h264_ddrlsb_addr_o[21:0]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {apb3_if_0:h264_ddrlsb_addr_o} -pin_slices {[31:22]} -sd_create_pin_group -sd_name ${sd_name} -group_name {Group} -instance_name {apb3_if_0} -pin_names {"brightness_i" "r_gain_i" "b_gain_i" "quality_i" "contrast_i" "g_gain_i" "mode_o" "alpha_o" "step_o" "frame_tcount_o" } -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:mode_o} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {apb3_if_0:r_gain_i} -value {GND} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {apb3_if_0:g_gain_i} -value {GND} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {apb3_if_0:b_gain_i} -value {GND} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {apb3_if_0:brightness_i} -value {GND} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {apb3_if_0:contrast_i} -value {GND} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {apb3_if_0:quality_i} -value {GND} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:alpha_o} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:step_o} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:frame_tcount_o} - - - -# Add h264_top_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {h264_top} -instance_name {h264_top_0} - - - -# Add IMX334_IF_TOP_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {IMX334_IF_TOP} -instance_name {IMX334_IF_TOP_0} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {IMX334_IF_TOP_0:CAMERA_CLK} - - - -# Add RGBtoYCbCr_C0_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {RGBtoYCbCr_C0} -instance_name {RGBtoYCbCr_C0_0} - - - -# Add video_processing_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {video_processing} -instance_name {video_processing_0} - - - -# Add scalar net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RX_CLK_N" "IMX334_IF_TOP_0:CAM1_RX_CLK_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RX_CLK_P" "IMX334_IF_TOP_0:CAM1_RX_CLK_P" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CLK_125MHz_i" "h264_top_0:fic_clk" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CLK_50MHz_i" "apb3_if_0:pclk_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX334_IF_TOP_0:ARST_N" "IMX334_IF_TOP_0:INIT_DONE" "INIT_DONE" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX334_IF_TOP_0:CAMCLK_RESET_N" "RGBtoYCbCr_C0_0:RESET_N_I" "h264_top_0:resetn_i" "video_processing_0:RESETN_I" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX334_IF_TOP_0:PARALLEL_CLOCK" "RGBtoYCbCr_C0_0:CLOCK_I" "h264_top_0:sys_clk_i" "video_processing_0:SYS_CLK_I" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX334_IF_TOP_0:TRNG_RST_N" "LPDDR4_RDY_i" "h264_top_0:ddr_ctrl_ready_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX334_IF_TOP_0:c1_frame_start_o" "video_processing_0:frame_start_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX334_IF_TOP_0:c1_frame_valid_o" "apb3_if_0:frame_valid_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX334_IF_TOP_0:c1_line_valid_o" "video_processing_0:DATA_VALID_I" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"RESETN_125MHz_i" "h264_top_0:read_reset_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"RESETN_50MHz_i" "apb3_if_0:preset_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"RGBtoYCbCr_C0_0:DATA_VALID_I" "video_processing_0:DATA_VALID_O" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"RGBtoYCbCr_C0_0:DATA_VALID_O" "h264_top_0:data_valid_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:h264_clr_intr_o" "h264_top_0:clr_intr_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:h264_en_o" "video_processing_0:encoder_en_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"frm_interrupt_o" "h264_top_0:frm_interrupt_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"h264_top_0:eof_i" "video_processing_0:eof_encoder_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"h264_top_0:frame_valid_i" "video_processing_0:frame_start_encoder_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"h264_top_0:h264_encoder_en" "video_processing_0:encoder_en_o" } - -# Add bus net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RXD" "IMX334_IF_TOP_0:CAM1_RXD" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RXD_N" "IMX334_IF_TOP_0:CAM1_RXD_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX334_IF_TOP_0:c1_data_out_o" "video_processing_0:DATA_I" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"RGBtoYCbCr_C0_0:BLUE_I" "video_processing_0:DATA_B_O" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"RGBtoYCbCr_C0_0:C_OUT" "h264_top_0:data_c_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"RGBtoYCbCr_C0_0:GREEN_I" "video_processing_0:DATA_G_O" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"RGBtoYCbCr_C0_0:RED_I" "video_processing_0:DATA_R_O" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"RGBtoYCbCr_C0_0:Y_OUT" "h264_top_0:data_y_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:RGB_SUM_i" "video_processing_0:y_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:bconst_o" "video_processing_0:B_CONST_I" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:frame_bytes_i" "h264_top_0:frame_bytes_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:frame_index_i" "h264_top_0:frame_index_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:gconst_o" "video_processing_0:G_CONST_I" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:h264_ddrlsb_addr_o[31:22]" "h264_top_0:frame_ddr_addr_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:horiz_resl_o" "h264_top_0:hres_i" "video_processing_0:hres_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:quality_o[5:0]" "h264_top_0:qp_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:rconst_o" "video_processing_0:R_CONST_I" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:second_const_o" "video_processing_0:COMMON_CONST_I" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:vert_resl_o" "h264_top_0:vres_i" "video_processing_0:vres_i" } - -# Add bus interface net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"APBslave" "apb3_if_0:APB_slave" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"BIF_1" "h264_top_0:BIF_1" } - -# Re-enable auto promotion of pins of type 'pad' -auto_promote_pad_pins -promote_all 1 -# Save the smartDesign -save_smartdesign -sd_name ${sd_name} -# Generate SmartDesign Video_Pipeline -generate_component -component_name ${sd_name} +# Creating SmartDesign Video_Pipeline +set sd_name {Video_Pipeline} +create_smartdesign -sd_name ${sd_name} + +# Disable auto promotion of pins of type 'pad' +auto_promote_pad_pins -promote_all 0 + +# Create top level Scalar Ports +sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_RX_CLK_N} -port_direction {IN} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_RX_CLK_P} -port_direction {IN} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK_125MHz_i} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK_50MHz_i} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {INIT_DONE} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {LPDDR4_RDY_i} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {RESETN_125MHz_i} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {RESETN_50MHz_i} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {arready} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {awready} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {bvalid} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {penable_i} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {psel_i} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {pwrite_i} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {rlast} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {rvalid} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {wready} -port_direction {IN} + +sd_create_scalar_port -sd_name ${sd_name} -port_name {arvalid} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {awvalid} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {bready} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {frm_interrupt_o} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {pready_o} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {pslverr_o} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {rready} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {wlast} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {wvalid} -port_direction {OUT} + + +# Create top level Bus Ports +sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_RXD_N} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1} +sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_RXD} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1} +sd_create_bus_port -sd_name ${sd_name} -port_name {bid} -port_direction {IN} -port_range {[3:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {bresp} -port_direction {IN} -port_range {[1:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {paddr_i} -port_direction {IN} -port_range {[31:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {pwdata_i} -port_direction {IN} -port_range {[31:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {rdata} -port_direction {IN} -port_range {[63:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {rid} -port_direction {IN} -port_range {[3:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {rresp} -port_direction {IN} -port_range {[1:0]} + +sd_create_bus_port -sd_name ${sd_name} -port_name {araddr} -port_direction {OUT} -port_range {[31:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {arburst} -port_direction {OUT} -port_range {[1:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {arcache} -port_direction {OUT} -port_range {[3:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {arid} -port_direction {OUT} -port_range {[3:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {arlen} -port_direction {OUT} -port_range {[7:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {arlock} -port_direction {OUT} -port_range {[1:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {arprot} -port_direction {OUT} -port_range {[2:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {arsize} -port_direction {OUT} -port_range {[2:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {awaddr} -port_direction {OUT} -port_range {[31:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {awburst} -port_direction {OUT} -port_range {[1:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {awcache} -port_direction {OUT} -port_range {[3:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {awid} -port_direction {OUT} -port_range {[3:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {awlen} -port_direction {OUT} -port_range {[7:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {awlock} -port_direction {OUT} -port_range {[1:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {awprot} -port_direction {OUT} -port_range {[2:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {awsize} -port_direction {OUT} -port_range {[2:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {prdata_o} -port_direction {OUT} -port_range {[31:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {wdata} -port_direction {OUT} -port_range {[63:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {wstrb} -port_direction {OUT} -port_range {[63:0]} + + +# Create top level Bus interface Ports +sd_create_bif_port -sd_name ${sd_name} -port_name {APBslave} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {slave} -port_bif_mapping {\ +"PADDR:paddr_i" \ +"PSELx:psel_i" \ +"PENABLE:penable_i" \ +"PWRITE:pwrite_i" \ +"PRDATA:prdata_o" \ +"PWDATA:pwdata_i" \ +"PREADY:pready_o" \ +"PSLVERR:pslverr_o" } + +sd_create_bif_port -sd_name ${sd_name} -port_name {BIF_1} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {mirroredSlave} -port_bif_mapping {\ +"AWID:awid" \ +"AWADDR:awaddr" \ +"AWLEN:awlen" \ +"AWSIZE:awsize" \ +"AWBURST:awburst" \ +"AWLOCK:awlock" \ +"AWCACHE:awcache" \ +"AWPROT:awprot" \ +"AWVALID:awvalid" \ +"AWREADY:awready" \ +"WDATA:wdata" \ +"WSTRB:wstrb" \ +"WLAST:wlast" \ +"WVALID:wvalid" \ +"WREADY:wready" \ +"BID:bid" \ +"BRESP:bresp" \ +"BVALID:bvalid" \ +"BREADY:bready" \ +"ARID:arid" \ +"ARADDR:araddr" \ +"ARLEN:arlen" \ +"ARSIZE:arsize" \ +"ARBURST:arburst" \ +"ARLOCK:arlock" \ +"ARCACHE:arcache" \ +"ARPROT:arprot" \ +"ARVALID:arvalid" \ +"ARREADY:arready" \ +"RID:rid" \ +"RDATA:rdata" \ +"RRESP:rresp" \ +"RLAST:rlast" \ +"RVALID:rvalid" \ +"RREADY:rready" } + +# Add apb3_if_0 instance +sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {apb3_if} -instance_name {apb3_if_0} +# Exporting Parameters of instance apb3_if_0 +sd_configure_core_instance -sd_name ${sd_name} -instance_name {apb3_if_0} -params {\ +"g_APB3_IF_DATA_WIDTH:32" \ +"g_CONST_WIDTH:12" }\ +-validate_rules 0 +sd_save_core_instance_config -sd_name ${sd_name} -instance_name {apb3_if_0} +sd_update_instance -sd_name ${sd_name} -instance_name {apb3_if_0} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {apb3_if_0:quality_o} -pin_slices {[5:0]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {apb3_if_0:quality_o} -pin_slices {[7:6]} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:quality_o[7:6]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {apb3_if_0:h264_ddrlsb_addr_o} -pin_slices {[21:0]} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:h264_ddrlsb_addr_o[21:0]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {apb3_if_0:h264_ddrlsb_addr_o} -pin_slices {[31:22]} +sd_create_pin_group -sd_name ${sd_name} -group_name {Group} -instance_name {apb3_if_0} -pin_names {"brightness_i" "r_gain_i" "b_gain_i" "quality_i" "contrast_i" "g_gain_i" "mode_o" "alpha_o" "step_o" "frame_tcount_o" } +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:mode_o} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {apb3_if_0:r_gain_i} -value {GND} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {apb3_if_0:g_gain_i} -value {GND} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {apb3_if_0:b_gain_i} -value {GND} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {apb3_if_0:brightness_i} -value {GND} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {apb3_if_0:contrast_i} -value {GND} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {apb3_if_0:quality_i} -value {GND} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:alpha_o} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:step_o} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:frame_tcount_o} + + + +# Add h264_top_0 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {h264_top} -instance_name {h264_top_0} + + + +# Add IMX334_IF_TOP_0 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {IMX334_IF_TOP} -instance_name {IMX334_IF_TOP_0} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {IMX334_IF_TOP_0:CAMERA_CLK} + + + +# Add RGBtoYCbCr_C0_0 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {RGBtoYCbCr_C0} -instance_name {RGBtoYCbCr_C0_0} + + + +# Add video_processing_0 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {video_processing} -instance_name {video_processing_0} + + + +# Add scalar net connections +sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RX_CLK_N" "IMX334_IF_TOP_0:CAM1_RX_CLK_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RX_CLK_P" "IMX334_IF_TOP_0:CAM1_RX_CLK_P" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CLK_125MHz_i" "h264_top_0:fic_clk" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CLK_50MHz_i" "apb3_if_0:pclk_i" "h264_top_0:pclk_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX334_IF_TOP_0:ARST_N" "IMX334_IF_TOP_0:INIT_DONE" "INIT_DONE" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX334_IF_TOP_0:CAMCLK_RESET_N" "RGBtoYCbCr_C0_0:RESET_N_I" "h264_top_0:resetn_i" "video_processing_0:RESETN_I" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX334_IF_TOP_0:PARALLEL_CLOCK" "RGBtoYCbCr_C0_0:CLOCK_I" "h264_top_0:sys_clk_i" "video_processing_0:SYS_CLK_I" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX334_IF_TOP_0:TRNG_RST_N" "LPDDR4_RDY_i" "h264_top_0:ddr_ctrl_ready_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX334_IF_TOP_0:c1_frame_start_o" "video_processing_0:frame_start_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX334_IF_TOP_0:c1_frame_valid_o" "apb3_if_0:frame_valid_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX334_IF_TOP_0:c1_line_valid_o" "video_processing_0:DATA_VALID_I" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"RESETN_125MHz_i" "h264_top_0:read_reset_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"RESETN_50MHz_i" "apb3_if_0:preset_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"RGBtoYCbCr_C0_0:DATA_VALID_I" "video_processing_0:DATA_VALID_O" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"RGBtoYCbCr_C0_0:DATA_VALID_O" "h264_top_0:data_valid_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:h264_clr_intr_o" "h264_top_0:clr_intr_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:h264_en_o" "video_processing_0:encoder_en_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"frm_interrupt_o" "h264_top_0:frm_interrupt_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"h264_top_0:eof_i" "video_processing_0:eof_encoder_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"h264_top_0:frame_valid_i" "video_processing_0:frame_start_encoder_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"h264_top_0:h264_encoder_en" "video_processing_0:encoder_en_o" } + +# Add bus net connections +sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RXD" "IMX334_IF_TOP_0:CAM1_RXD" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RXD_N" "IMX334_IF_TOP_0:CAM1_RXD_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX334_IF_TOP_0:c1_data_out_o" "video_processing_0:DATA_I" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"RGBtoYCbCr_C0_0:BLUE_I" "video_processing_0:DATA_B_O" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"RGBtoYCbCr_C0_0:C_OUT" "h264_top_0:data_c_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"RGBtoYCbCr_C0_0:GREEN_I" "video_processing_0:DATA_G_O" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"RGBtoYCbCr_C0_0:RED_I" "video_processing_0:DATA_R_O" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"RGBtoYCbCr_C0_0:Y_OUT" "h264_top_0:data_y_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:RGB_SUM_i" "video_processing_0:y_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:bconst_o" "video_processing_0:B_CONST_I" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:disp_digits_o" "video_processing_0:digits_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:frame_bytes_i" "h264_top_0:frame_bytes_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:frame_index_i" "h264_top_0:frame_index_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:gconst_o" "video_processing_0:G_CONST_I" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:h264_ddrlsb_addr_o[31:22]" "h264_top_0:frame_ddr_addr_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:horiz_resl_o" "h264_top_0:hres_i" "video_processing_0:hres_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:quality_o[5:0]" "h264_top_0:qp_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:rconst_o" "video_processing_0:R_CONST_I" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:second_const_o" "video_processing_0:COMMON_CONST_I" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:text_color_o" "video_processing_0:text_color_rgb_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:text_coordinates_o" "video_processing_0:coordinate_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:vert_resl_o" "h264_top_0:vres_i" "video_processing_0:vres_i" } + +# Add bus interface net connections +sd_connect_pins -sd_name ${sd_name} -pin_names {"APBslave" "apb3_if_0:APB_slave" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"BIF_1" "h264_top_0:BIF_1" } + +# Re-enable auto promotion of pins of type 'pad' +auto_promote_pad_pins -promote_all 1 +# Save the smartDesign +save_smartdesign -sd_name ${sd_name} +# Generate SmartDesign Video_Pipeline +generate_component -component_name ${sd_name} diff --git a/script_support/components/H264/data_packer_h264.tcl b/script_support/components/H264/data_packer_h264.tcl index e36e65c..86e66e1 100644 --- a/script_support/components/H264/data_packer_h264.tcl +++ b/script_support/components/H264/data_packer_h264.tcl @@ -1,4 +1,4 @@ -# Exporting core data_packer_h264 to TCL -# Exporting Create HDL core command for module data_packer_h264 -create_hdl_core -file {hdl/data_packer_h264.vhd} -module {data_packer_h264} -library {work} -package {} -# Exporting BIF information of HDL core command for module data_packer_h264 +# Exporting core data_packer_h264 to TCL +# Exporting Create HDL core command for module data_packer_h264 +create_hdl_core -file {hdl/data_packer_h264.vhd} -module {data_packer_h264} -library {work} -package {} +# Exporting BIF information of HDL core command for module data_packer_h264 diff --git a/script_support/components/H264/h264_top.tcl b/script_support/components/H264/h264_top.tcl index 0f5dd25..1ace674 100644 --- a/script_support/components/H264/h264_top.tcl +++ b/script_support/components/H264/h264_top.tcl @@ -1,176 +1,178 @@ -# Creating SmartDesign h264_top -set sd_name {h264_top} -create_smartdesign -sd_name ${sd_name} - -# Disable auto promotion of pins of type 'pad' -auto_promote_pad_pins -promote_all 0 - -# Create top level Scalar Ports -sd_create_scalar_port -sd_name ${sd_name} -port_name {arready} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {awready} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {bvalid} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {clr_intr_i} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {data_valid_i} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {ddr_ctrl_ready_i} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {eof_i} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {fic_clk} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {frame_valid_i} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {h264_encoder_en} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {read_reset_i} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {resetn_i} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {rlast} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {rvalid} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {sys_clk_i} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {wready} -port_direction {IN} - -sd_create_scalar_port -sd_name ${sd_name} -port_name {arvalid} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {awvalid} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {bready} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {frm_interrupt_o} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {rready} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {wlast} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {wvalid} -port_direction {OUT} - - -# Create top level Bus Ports -sd_create_bus_port -sd_name ${sd_name} -port_name {bid} -port_direction {IN} -port_range {[3:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {bresp} -port_direction {IN} -port_range {[1:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {data_c_i} -port_direction {IN} -port_range {[7:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {data_y_i} -port_direction {IN} -port_range {[7:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {frame_ddr_addr_i} -port_direction {IN} -port_range {[9:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {hres_i} -port_direction {IN} -port_range {[15:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {qp_i} -port_direction {IN} -port_range {[5:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {rdata} -port_direction {IN} -port_range {[63:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {rid} -port_direction {IN} -port_range {[3:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {rresp} -port_direction {IN} -port_range {[1:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {vres_i} -port_direction {IN} -port_range {[15:0]} - -sd_create_bus_port -sd_name ${sd_name} -port_name {araddr} -port_direction {OUT} -port_range {[31:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {arburst} -port_direction {OUT} -port_range {[1:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {arcache} -port_direction {OUT} -port_range {[3:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {arid} -port_direction {OUT} -port_range {[3:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {arlen} -port_direction {OUT} -port_range {[7:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {arlock} -port_direction {OUT} -port_range {[1:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {arprot} -port_direction {OUT} -port_range {[2:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {arsize} -port_direction {OUT} -port_range {[2:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {awaddr} -port_direction {OUT} -port_range {[31:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {awburst} -port_direction {OUT} -port_range {[1:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {awcache} -port_direction {OUT} -port_range {[3:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {awid} -port_direction {OUT} -port_range {[3:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {awlen} -port_direction {OUT} -port_range {[7:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {awlock} -port_direction {OUT} -port_range {[1:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {awprot} -port_direction {OUT} -port_range {[2:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {awsize} -port_direction {OUT} -port_range {[2:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {frame_bytes_o} -port_direction {OUT} -port_range {[31:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {frame_index_o} -port_direction {OUT} -port_range {[1:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {wdata} -port_direction {OUT} -port_range {[63:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {wstrb} -port_direction {OUT} -port_range {[63:0]} - - -# Create top level Bus interface Ports -sd_create_bif_port -sd_name ${sd_name} -port_name {BIF_1} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {mirroredSlave} -port_bif_mapping {\ -"AWID:awid" \ -"AWADDR:awaddr" \ -"AWLEN:awlen" \ -"AWSIZE:awsize" \ -"AWBURST:awburst" \ -"AWLOCK:awlock" \ -"AWCACHE:awcache" \ -"AWPROT:awprot" \ -"AWVALID:awvalid" \ -"AWREADY:awready" \ -"WDATA:wdata" \ -"WSTRB:wstrb" \ -"WLAST:wlast" \ -"WVALID:wvalid" \ -"WREADY:wready" \ -"BID:bid" \ -"BRESP:bresp" \ -"BVALID:bvalid" \ -"BREADY:bready" \ -"ARID:arid" \ -"ARADDR:araddr" \ -"ARLEN:arlen" \ -"ARSIZE:arsize" \ -"ARBURST:arburst" \ -"ARLOCK:arlock" \ -"ARCACHE:arcache" \ -"ARPROT:arprot" \ -"ARVALID:arvalid" \ -"ARREADY:arready" \ -"RID:rid" \ -"RDATA:rdata" \ -"RRESP:rresp" \ -"RLAST:rlast" \ -"RVALID:rvalid" \ -"RREADY:rready" } - -# Add AND2_0 instance -sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0} - - - -# Add DDR_AXI4_ARBITER_PF_C0_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {DDR_AXI4_ARBITER_PF_C0} -instance_name {DDR_AXI4_ARBITER_PF_C0_0} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_AXI4_ARBITER_PF_C0_0:r0_req_i} -value {GND} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DDR_AXI4_ARBITER_PF_C0_0:r0_ack_o} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DDR_AXI4_ARBITER_PF_C0_0:r0_data_valid_o} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DDR_AXI4_ARBITER_PF_C0_0:r0_done_o} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_AXI4_ARBITER_PF_C0_0:r0_burst_size_i} -value {GND} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_AXI4_ARBITER_PF_C0_0:r0_rstart_addr_i} -value {GND} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DDR_AXI4_ARBITER_PF_C0_0:rdata_o} - - - -# Add H264_DDR_WRITE_64 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {H264_DDR_WRITE} -instance_name {H264_DDR_WRITE_64} - - - -# Add H264_Iframe_Encoder_C0_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {H264_Iframe_Encoder_C0} -instance_name {H264_Iframe_Encoder_C0_0} - - - -# Add scalar net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "resetn_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "H264_DDR_WRITE_64:h264_encoder_en_i" "h264_encoder_en" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "H264_Iframe_Encoder_C0_0:RESET_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:ddr_ctrl_ready_i" "ddr_ctrl_ready_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:reset_i" "H264_DDR_WRITE_64:reset_i" "read_reset_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:sys_clk_i" "H264_DDR_WRITE_64:ddr_clk_i" "fic_clk" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w0_ack_o" "H264_DDR_WRITE_64:write_ackn_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w0_data_valid_i" "H264_DDR_WRITE_64:rdata_rdy_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w0_done_o" "H264_DDR_WRITE_64:write_done_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w0_req_i" "H264_DDR_WRITE_64:write_req_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_DDR_WRITE_64:clr_intr_i" "clr_intr_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_DDR_WRITE_64:data_valid_i" "H264_Iframe_Encoder_C0_0:DATA_VALID_O" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_DDR_WRITE_64:frame_end_i" "H264_Iframe_Encoder_C0_0:FRAME_END_I" "eof_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_DDR_WRITE_64:frm_interrupt_o" "frm_interrupt_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_DDR_WRITE_64:h264_clk_i" "H264_Iframe_Encoder_C0_0:PIX_CLK" "sys_clk_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_Iframe_Encoder_C0_0:DATA_VALID_I" "data_valid_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_Iframe_Encoder_C0_0:FRAME_START_I" "frame_valid_i" } - -# Add bus net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w0_burst_size_i" "H264_DDR_WRITE_64:write_length_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w0_data_i" "H264_DDR_WRITE_64:rdata_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w0_wstart_addr_i" "H264_DDR_WRITE_64:write_start_addr_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_DDR_WRITE_64:data_i" "H264_Iframe_Encoder_C0_0:DATA_O" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_DDR_WRITE_64:frame_bytes_o" "frame_bytes_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_DDR_WRITE_64:frame_ddr_addr_i" "frame_ddr_addr_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_DDR_WRITE_64:frame_index_o" "frame_index_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_Iframe_Encoder_C0_0:DATA_C_I" "data_c_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_Iframe_Encoder_C0_0:DATA_Y_I" "data_y_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_Iframe_Encoder_C0_0:HRES_I" "hres_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_Iframe_Encoder_C0_0:QP_I" "qp_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_Iframe_Encoder_C0_0:VRES_I" "vres_i" } - -# Add bus interface net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"BIF_1" "DDR_AXI4_ARBITER_PF_C0_0:MIRRORED_SLAVE_AXI4" } - -# Re-enable auto promotion of pins of type 'pad' -auto_promote_pad_pins -promote_all 1 -# Save the smartDesign -save_smartdesign -sd_name ${sd_name} -# Generate SmartDesign h264_top -generate_component -component_name ${sd_name} +# Creating SmartDesign h264_top +set sd_name {h264_top} +create_smartdesign -sd_name ${sd_name} + +# Disable auto promotion of pins of type 'pad' +auto_promote_pad_pins -promote_all 0 + +# Create top level Scalar Ports +sd_create_scalar_port -sd_name ${sd_name} -port_name {arready} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {awready} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {bvalid} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {clr_intr_i} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {data_valid_i} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {ddr_ctrl_ready_i} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {eof_i} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {fic_clk} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {frame_valid_i} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {h264_encoder_en} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {pclk_i} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {read_reset_i} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {resetn_i} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {rlast} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {rvalid} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {sys_clk_i} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {wready} -port_direction {IN} + +sd_create_scalar_port -sd_name ${sd_name} -port_name {arvalid} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {awvalid} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {bready} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {frm_interrupt_o} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {rready} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {wlast} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {wvalid} -port_direction {OUT} + + +# Create top level Bus Ports +sd_create_bus_port -sd_name ${sd_name} -port_name {bid} -port_direction {IN} -port_range {[3:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {bresp} -port_direction {IN} -port_range {[1:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {data_c_i} -port_direction {IN} -port_range {[7:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {data_y_i} -port_direction {IN} -port_range {[7:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {frame_ddr_addr_i} -port_direction {IN} -port_range {[9:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {hres_i} -port_direction {IN} -port_range {[15:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {qp_i} -port_direction {IN} -port_range {[5:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {rdata} -port_direction {IN} -port_range {[63:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {rid} -port_direction {IN} -port_range {[3:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {rresp} -port_direction {IN} -port_range {[1:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {vres_i} -port_direction {IN} -port_range {[15:0]} + +sd_create_bus_port -sd_name ${sd_name} -port_name {araddr} -port_direction {OUT} -port_range {[31:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {arburst} -port_direction {OUT} -port_range {[1:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {arcache} -port_direction {OUT} -port_range {[3:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {arid} -port_direction {OUT} -port_range {[3:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {arlen} -port_direction {OUT} -port_range {[7:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {arlock} -port_direction {OUT} -port_range {[1:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {arprot} -port_direction {OUT} -port_range {[2:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {arsize} -port_direction {OUT} -port_range {[2:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {awaddr} -port_direction {OUT} -port_range {[31:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {awburst} -port_direction {OUT} -port_range {[1:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {awcache} -port_direction {OUT} -port_range {[3:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {awid} -port_direction {OUT} -port_range {[3:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {awlen} -port_direction {OUT} -port_range {[7:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {awlock} -port_direction {OUT} -port_range {[1:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {awprot} -port_direction {OUT} -port_range {[2:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {awsize} -port_direction {OUT} -port_range {[2:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {frame_bytes_o} -port_direction {OUT} -port_range {[31:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {frame_index_o} -port_direction {OUT} -port_range {[1:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {wdata} -port_direction {OUT} -port_range {[63:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {wstrb} -port_direction {OUT} -port_range {[63:0]} + + +# Create top level Bus interface Ports +sd_create_bif_port -sd_name ${sd_name} -port_name {BIF_1} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {mirroredSlave} -port_bif_mapping {\ +"AWID:awid" \ +"AWADDR:awaddr" \ +"AWLEN:awlen" \ +"AWSIZE:awsize" \ +"AWBURST:awburst" \ +"AWLOCK:awlock" \ +"AWCACHE:awcache" \ +"AWPROT:awprot" \ +"AWVALID:awvalid" \ +"AWREADY:awready" \ +"WDATA:wdata" \ +"WSTRB:wstrb" \ +"WLAST:wlast" \ +"WVALID:wvalid" \ +"WREADY:wready" \ +"BID:bid" \ +"BRESP:bresp" \ +"BVALID:bvalid" \ +"BREADY:bready" \ +"ARID:arid" \ +"ARADDR:araddr" \ +"ARLEN:arlen" \ +"ARSIZE:arsize" \ +"ARBURST:arburst" \ +"ARLOCK:arlock" \ +"ARCACHE:arcache" \ +"ARPROT:arprot" \ +"ARVALID:arvalid" \ +"ARREADY:arready" \ +"RID:rid" \ +"RDATA:rdata" \ +"RRESP:rresp" \ +"RLAST:rlast" \ +"RVALID:rvalid" \ +"RREADY:rready" } + +# Add AND2_0 instance +sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0} + + + +# Add DDR_AXI4_ARBITER_PF_C0_0 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {DDR_AXI4_ARBITER_PF_C0} -instance_name {DDR_AXI4_ARBITER_PF_C0_0} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_AXI4_ARBITER_PF_C0_0:r0_req_i} -value {GND} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DDR_AXI4_ARBITER_PF_C0_0:r0_ack_o} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DDR_AXI4_ARBITER_PF_C0_0:r0_data_valid_o} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DDR_AXI4_ARBITER_PF_C0_0:r0_done_o} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_AXI4_ARBITER_PF_C0_0:r0_burst_size_i} -value {GND} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_AXI4_ARBITER_PF_C0_0:r0_rstart_addr_i} -value {GND} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DDR_AXI4_ARBITER_PF_C0_0:rdata_o} + + + +# Add H264_DDR_WRITE_64 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {H264_DDR_WRITE} -instance_name {H264_DDR_WRITE_64} + + + +# Add H264_Iframe_Encoder_C0_0 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {H264_Iframe_Encoder_C0} -instance_name {H264_Iframe_Encoder_C0_0} + + + +# Add scalar net connections +sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "resetn_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "H264_DDR_WRITE_64:h264_encoder_en_i" "h264_encoder_en" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "H264_Iframe_Encoder_C0_0:RESET_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:ddr_ctrl_ready_i" "ddr_ctrl_ready_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:reset_i" "H264_DDR_WRITE_64:reset_i" "read_reset_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:sys_clk_i" "H264_DDR_WRITE_64:ddr_clk_i" "fic_clk" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w0_ack_o" "H264_DDR_WRITE_64:write_ackn_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w0_data_valid_i" "H264_DDR_WRITE_64:rdata_rdy_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w0_done_o" "H264_DDR_WRITE_64:write_done_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w0_req_i" "H264_DDR_WRITE_64:write_req_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_DDR_WRITE_64:clr_intr_i" "clr_intr_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_DDR_WRITE_64:data_valid_i" "H264_Iframe_Encoder_C0_0:DATA_VALID_O" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_DDR_WRITE_64:frame_end_i" "H264_Iframe_Encoder_C0_0:FRAME_END_I" "eof_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_DDR_WRITE_64:frm_interrupt_o" "frm_interrupt_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_DDR_WRITE_64:h264_clk_i" "H264_Iframe_Encoder_C0_0:PIX_CLK" "sys_clk_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_DDR_WRITE_64:pclk_i" "pclk_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_Iframe_Encoder_C0_0:DATA_VALID_I" "data_valid_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_Iframe_Encoder_C0_0:FRAME_START_I" "frame_valid_i" } + +# Add bus net connections +sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w0_burst_size_i" "H264_DDR_WRITE_64:write_length_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w0_data_i" "H264_DDR_WRITE_64:rdata_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w0_wstart_addr_i" "H264_DDR_WRITE_64:write_start_addr_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_DDR_WRITE_64:data_i" "H264_Iframe_Encoder_C0_0:DATA_O" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_DDR_WRITE_64:frame_bytes_o" "frame_bytes_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_DDR_WRITE_64:frame_ddr_addr_i" "frame_ddr_addr_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_DDR_WRITE_64:frame_index_o" "frame_index_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_Iframe_Encoder_C0_0:DATA_C_I" "data_c_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_Iframe_Encoder_C0_0:DATA_Y_I" "data_y_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_Iframe_Encoder_C0_0:HRES_I" "hres_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_Iframe_Encoder_C0_0:QP_I" "qp_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"H264_Iframe_Encoder_C0_0:VRES_I" "vres_i" } + +# Add bus interface net connections +sd_connect_pins -sd_name ${sd_name} -pin_names {"BIF_1" "DDR_AXI4_ARBITER_PF_C0_0:MIRRORED_SLAVE_AXI4" } + +# Re-enable auto promotion of pins of type 'pad' +auto_promote_pad_pins -promote_all 1 +# Save the smartDesign +save_smartdesign -sd_name ${sd_name} +# Generate SmartDesign h264_top +generate_component -component_name ${sd_name} diff --git a/script_support/components/IMAGE_SCALER_C0.tcl b/script_support/components/IMAGE_SCALER_C0.tcl index 89ecd93..1556335 100644 --- a/script_support/components/IMAGE_SCALER_C0.tcl +++ b/script_support/components/IMAGE_SCALER_C0.tcl @@ -1,11 +1,11 @@ -# Exporting Component Description of IMAGE_SCALER_C0 to TCL -# Family: PolarFireSoC -# Part Number: MPFS250T_ES-1FCG1152E -# Create and Configure the core component IMAGE_SCALER_C0 -create_and_configure_core -core_vlnv {Microsemi:SolutionCore:IMAGE_SCALER:4.0.0} -component_name {IMAGE_SCALER_C0} -params {\ -"G_CONFIG:0" \ -"G_DATA_WIDTH:8" \ -"G_FORMAT:0" \ -"G_INPUT_FIFO_AWIDTH:11" \ -"G_OUTPUT_FIFO_AWIDTH:11" } -# Exporting Component Description of IMAGE_SCALER_C0 to TCL done +# Exporting Component Description of IMAGE_SCALER_C0 to TCL +# Family: PolarFireSoC +# Part Number: MPFS250T_ES-1FCG1152E +# Create and Configure the core component IMAGE_SCALER_C0 +create_and_configure_core -core_vlnv {Microsemi:SolutionCore:IMAGE_SCALER:4.1.0} -component_name {IMAGE_SCALER_C0} -params {\ +"G_CONFIG:0" \ +"G_DATA_WIDTH:8" \ +"G_FORMAT:0" \ +"G_INPUT_FIFO_AWIDTH:11" \ +"G_OUTPUT_FIFO_AWIDTH:11" } +# Exporting Component Description of IMAGE_SCALER_C0 to TCL done diff --git a/script_support/components/IMX334_IF_TOP.tcl b/script_support/components/IMX334_IF_TOP.tcl index 07d699c..9af0002 100644 --- a/script_support/components/IMX334_IF_TOP.tcl +++ b/script_support/components/IMX334_IF_TOP.tcl @@ -1,125 +1,128 @@ -# Creating SmartDesign IMX334_IF_TOP -set sd_name {IMX334_IF_TOP} -create_smartdesign -sd_name ${sd_name} - -# Disable auto promotion of pins of type 'pad' -auto_promote_pad_pins -promote_all 0 - -# Create top level Scalar Ports -sd_create_scalar_port -sd_name ${sd_name} -port_name {ARST_N} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_RX_CLK_N} -port_direction {IN} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_RX_CLK_P} -port_direction {IN} -port_is_pad {1} -sd_create_scalar_port -sd_name ${sd_name} -port_name {INIT_DONE} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TRNG_RST_N} -port_direction {IN} - -sd_create_scalar_port -sd_name ${sd_name} -port_name {CAMCLK_RESET_N} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {CAMERA_CLK} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {PARALLEL_CLOCK} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {c1_frame_start_o} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {c1_frame_valid_o} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {c1_line_valid_o} -port_direction {OUT} - - -# Create top level Bus Ports -sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_RXD_N} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1} -sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_RXD} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1} - -sd_create_bus_port -sd_name ${sd_name} -port_name {c1_data_out_o} -port_direction {OUT} -port_range {[7:0]} - - -# Add AND2_0 instance -sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0} - - - -# Add CORERESET_PF_C1_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C1} -instance_name {CORERESET_PF_C1_0} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:BANK_x_VDDI_STATUS} -value {VCC} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:BANK_y_VDDI_STATUS} -value {VCC} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:SS_BUSY} -value {GND} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:FF_US_RESTORE} -value {GND} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:FPGA_POR_N} -value {VCC} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:PLL_POWERDOWN_B} - - - -# Add CORERESET_PF_C2_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C2} -instance_name {CORERESET_PF_C2_0} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C2_0:BANK_x_VDDI_STATUS} -value {VCC} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C2_0:BANK_y_VDDI_STATUS} -value {VCC} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C2_0:SS_BUSY} -value {GND} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C2_0:FF_US_RESTORE} -value {GND} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C2_0:FPGA_POR_N} -value {VCC} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERESET_PF_C2_0:PLL_POWERDOWN_B} - - - -# Add CSI2_RXDecoder_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {mipicsi2rxdecoderPF_C0} -instance_name {CSI2_RXDecoder_0} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CSI2_RXDecoder_0:data_out_o} -pin_slices {[9:2]} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:frame_end_o} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:line_end_o} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:line_start_o} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:ecc_error_o} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:data_type_o} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:word_count_o} - - - -# Add PF_CCC_C2_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_C2} -instance_name {PF_CCC_C2_0} - - - -# Add PF_IOD_GENERIC_RX_C0_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CAM_IOD_TIP_TOP} -instance_name {PF_IOD_GENERIC_RX_C0_0} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:SKIP_TRNG} -value {GND} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:RESTART_TRNG} -value {GND} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:HS_SEL} -value {VCC} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:HS_IO_CLK_PAUSE} -value {GND} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:CLK_TRAIN_ERROR} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:CLK_TRAIN_DONE} - - - -# Add scalar net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "TRNG_RST_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "CORERESET_PF_C1_0:PLL_LOCK" "CORERESET_PF_C2_0:PLL_LOCK" "PF_CCC_C2_0:PLL_LOCK_0" "PF_IOD_GENERIC_RX_C0_0:PLL_LOCK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "PF_IOD_GENERIC_RX_C0_0:TRAINING_RESETN" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"ARST_N" "PF_IOD_GENERIC_RX_C0_0:ARST_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RX_CLK_N" "PF_IOD_GENERIC_RX_C0_0:RX_CLK_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RX_CLK_P" "PF_IOD_GENERIC_RX_C0_0:RX_CLK_P" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CAMCLK_RESET_N" "CORERESET_PF_C1_0:FABRIC_RESET_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CAMERA_CLK" "CORERESET_PF_C2_0:CLK" "CSI2_RXDecoder_0:CAM_CLOCK_I" "PF_CCC_C2_0:REF_CLK_0" "PF_IOD_GENERIC_RX_C0_0:RX_CLK_G" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:CLK" "CSI2_RXDecoder_0:PARALLEL_CLOCK_I" "PARALLEL_CLOCK" "PF_CCC_C2_0:OUT0_FABCLK_0" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:EXT_RST_N" "CORERESET_PF_C2_0:EXT_RST_N" "PF_IOD_GENERIC_RX_C0_0:training_done_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:INIT_DONE" "CORERESET_PF_C2_0:INIT_DONE" "INIT_DONE" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C2_0:FABRIC_RESET_N" "CSI2_RXDecoder_0:RESET_n_I" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L0_LP_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L0_LP_DATA" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L0_LP_DATA_N_I" "PF_IOD_GENERIC_RX_C0_0:L0_LP_DATA_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L1_LP_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L1_LP_DATA" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L1_LP_DATA_N_I" "PF_IOD_GENERIC_RX_C0_0:L1_LP_DATA_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L2_LP_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L2_LP_DATA" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L2_LP_DATA_N_I" "PF_IOD_GENERIC_RX_C0_0:L2_LP_DATA_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L3_LP_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L3_LP_DATA" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L3_LP_DATA_N_I" "PF_IOD_GENERIC_RX_C0_0:L3_LP_DATA_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:frame_start_o" "c1_frame_start_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:frame_valid_o" "c1_frame_valid_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:line_valid_o" "c1_line_valid_o" } - -# Add bus net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RXD" "PF_IOD_GENERIC_RX_C0_0:RXD" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RXD_N" "PF_IOD_GENERIC_RX_C0_0:RXD_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L0_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L0_RXD_DATA" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L1_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L1_RXD_DATA" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L2_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L2_RXD_DATA" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L3_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L3_RXD_DATA" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:data_out_o[9:2]" "c1_data_out_o" } - - -# Re-enable auto promotion of pins of type 'pad' -auto_promote_pad_pins -promote_all 1 -# Save the smartDesign -save_smartdesign -sd_name ${sd_name} -# Generate SmartDesign IMX334_IF_TOP -generate_component -component_name ${sd_name} +# Creating SmartDesign IMX334_IF_TOP +set sd_name {IMX334_IF_TOP} +create_smartdesign -sd_name ${sd_name} + +# Disable auto promotion of pins of type 'pad' +auto_promote_pad_pins -promote_all 0 + +# Create top level Scalar Ports +sd_create_scalar_port -sd_name ${sd_name} -port_name {ARST_N} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_RX_CLK_N} -port_direction {IN} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_RX_CLK_P} -port_direction {IN} -port_is_pad {1} +sd_create_scalar_port -sd_name ${sd_name} -port_name {INIT_DONE} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {TRNG_RST_N} -port_direction {IN} + +sd_create_scalar_port -sd_name ${sd_name} -port_name {CAMCLK_RESET_N} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {CAMERA_CLK} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {PARALLEL_CLOCK} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {c1_frame_start_o} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {c1_frame_valid_o} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {c1_line_valid_o} -port_direction {OUT} + + +# Create top level Bus Ports +sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_RXD_N} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1} +sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_RXD} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1} + +sd_create_bus_port -sd_name ${sd_name} -port_name {c1_data_out_o} -port_direction {OUT} -port_range {[7:0]} + + +# Add AND2_0 instance +sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0} + + + +# Add CORERESET_PF_C1_0 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C1} -instance_name {CORERESET_PF_C1_0} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:BANK_x_VDDI_STATUS} -value {VCC} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:BANK_y_VDDI_STATUS} -value {VCC} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:SS_BUSY} -value {GND} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:FF_US_RESTORE} -value {GND} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:FPGA_POR_N} -value {VCC} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:PLL_POWERDOWN_B} + + + +# Add CORERESET_PF_C2_0 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C2} -instance_name {CORERESET_PF_C2_0} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C2_0:BANK_x_VDDI_STATUS} -value {VCC} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C2_0:BANK_y_VDDI_STATUS} -value {VCC} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C2_0:SS_BUSY} -value {GND} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C2_0:FF_US_RESTORE} -value {GND} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C2_0:FPGA_POR_N} -value {VCC} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERESET_PF_C2_0:PLL_POWERDOWN_B} + + + +# Add CSI2_RXDecoder_0 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {mipicsi2rxdecoderPF_C0} -instance_name {CSI2_RXDecoder_0} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {CSI2_RXDecoder_0:DATA_O} -pin_slices {[9:2]} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:FRAME_END_O} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:LINE_START_O} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:LINE_END_O} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:ECC_ERROR_O} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:CRC_ERROR_O} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:EBD_VALID_O} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:VIRTUAL_CHANNEL_O} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:DATA_TYPE_O} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:WORD_COUNT_O} + + + +# Add PF_CCC_C2_0 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_C2} -instance_name {PF_CCC_C2_0} + + + +# Add PF_IOD_GENERIC_RX_C0_0 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {CAM_IOD_TIP_TOP} -instance_name {PF_IOD_GENERIC_RX_C0_0} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:HS_IO_CLK_PAUSE} -value {GND} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:HS_SEL} -value {VCC} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:RESTART_TRNG} -value {GND} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:SKIP_TRNG} -value {GND} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:CLK_TRAIN_DONE} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:CLK_TRAIN_ERROR} + + + +# Add scalar net connections +sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "TRNG_RST_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "CORERESET_PF_C1_0:PLL_LOCK" "CORERESET_PF_C2_0:PLL_LOCK" "PF_CCC_C2_0:PLL_LOCK_0" "PF_IOD_GENERIC_RX_C0_0:PLL_LOCK" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "PF_IOD_GENERIC_RX_C0_0:TRAINING_RESETN" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"ARST_N" "PF_IOD_GENERIC_RX_C0_0:ARST_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RX_CLK_N" "PF_IOD_GENERIC_RX_C0_0:RX_CLK_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RX_CLK_P" "PF_IOD_GENERIC_RX_C0_0:RX_CLK_P" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CAMCLK_RESET_N" "CORERESET_PF_C1_0:FABRIC_RESET_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CAMERA_CLK" "CORERESET_PF_C2_0:CLK" "CSI2_RXDecoder_0:CAM_CLOCK_I" "PF_CCC_C2_0:REF_CLK_0" "PF_IOD_GENERIC_RX_C0_0:RX_CLK_G" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:CLK" "CSI2_RXDecoder_0:PARALLEL_CLOCK_I" "PARALLEL_CLOCK" "PF_CCC_C2_0:OUT0_FABCLK_0" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:EXT_RST_N" "CORERESET_PF_C2_0:EXT_RST_N" "PF_IOD_GENERIC_RX_C0_0:training_done_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:INIT_DONE" "CORERESET_PF_C2_0:INIT_DONE" "INIT_DONE" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C2_0:FABRIC_RESET_N" "CSI2_RXDecoder_0:RESET_N_I" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:FRAME_START_O" "c1_frame_start_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:FRAME_VALID_O" "c1_frame_valid_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L0_LP_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L0_LP_DATA" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L0_LP_DATA_N_I" "PF_IOD_GENERIC_RX_C0_0:L0_LP_DATA_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L1_LP_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L1_LP_DATA" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L1_LP_DATA_N_I" "PF_IOD_GENERIC_RX_C0_0:L1_LP_DATA_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L2_LP_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L2_LP_DATA" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L2_LP_DATA_N_I" "PF_IOD_GENERIC_RX_C0_0:L2_LP_DATA_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L3_LP_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L3_LP_DATA" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L3_LP_DATA_N_I" "PF_IOD_GENERIC_RX_C0_0:L3_LP_DATA_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:LINE_VALID_O" "c1_line_valid_o" } + +# Add bus net connections +sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RXD" "PF_IOD_GENERIC_RX_C0_0:RXD" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RXD_N" "PF_IOD_GENERIC_RX_C0_0:RXD_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:DATA_O[9:2]" "c1_data_out_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L0_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L0_RXD_DATA" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L1_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L1_RXD_DATA" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L2_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L2_RXD_DATA" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L3_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L3_RXD_DATA" } + + +# Re-enable auto promotion of pins of type 'pad' +auto_promote_pad_pins -promote_all 1 +# Save the smartDesign +save_smartdesign -sd_name ${sd_name} +# Generate SmartDesign IMX334_IF_TOP +generate_component -component_name ${sd_name} diff --git a/script_support/components/INIT_MONITOR.tcl b/script_support/components/INIT_MONITOR.tcl index 6b8f9de..8607f72 100644 --- a/script_support/components/INIT_MONITOR.tcl +++ b/script_support/components/INIT_MONITOR.tcl @@ -1,52 +1,52 @@ -# Exporting Component Description of INIT_MONITOR to TCL -# Family: PolarFireSoC -# Part Number: MPFS250T_ES-1FCG1152E -# Create and Configure the core component INIT_MONITOR -create_and_configure_core -core_vlnv {Microsemi:SgCore:PFSOC_INIT_MONITOR:1.0.304} -component_name {INIT_MONITOR} -params {\ -"BANK_0_CALIB_STATUS_ENABLED:false" \ -"BANK_0_CALIB_STATUS_SIMULATION_DELAY:1" \ -"BANK_0_RECALIBRATION_ENABLED:false" \ -"BANK_0_VDDI_STATUS_ENABLED:false" \ -"BANK_0_VDDI_STATUS_SIMULATION_DELAY:1" \ -"BANK_1_CALIB_STATUS_ENABLED:false" \ -"BANK_1_CALIB_STATUS_SIMULATION_DELAY:1" \ -"BANK_1_RECALIBRATION_ENABLED:false" \ -"BANK_1_VDDI_STATUS_ENABLED:false" \ -"BANK_1_VDDI_STATUS_SIMULATION_DELAY:1" \ -"BANK_7_CALIB_STATUS_ENABLED:true" \ -"BANK_7_CALIB_STATUS_SIMULATION_DELAY:1" \ -"BANK_7_RECALIBRATION_ENABLED:false" \ -"BANK_7_VDDI_STATUS_ENABLED:false" \ -"BANK_7_VDDI_STATUS_SIMULATION_DELAY:1" \ -"BANK_8_CALIB_STATUS_ENABLED:true" \ -"BANK_8_CALIB_STATUS_SIMULATION_DELAY:1" \ -"BANK_8_RECALIBRATION_ENABLED:false" \ -"BANK_8_VDDI_STATUS_ENABLED:false" \ -"BANK_8_VDDI_STATUS_SIMULATION_DELAY:1" \ -"BANK_9_CALIB_STATUS_ENABLED:true" \ -"BANK_9_CALIB_STATUS_SIMULATION_DELAY:1" \ -"BANK_9_RECALIBRATION_ENABLED:false" \ -"BANK_9_VDDI_STATUS_ENABLED:false" \ -"BANK_9_VDDI_STATUS_SIMULATION_DELAY:1" \ -"DEVICE_INIT_DONE_SIMULATION_DELAY:7" \ -"FABRIC_POR_N_SIMULATION_DELAY:1" \ -"LATCH_SC_OUTPUTS:false" \ -"PCIE_INIT_DONE_SIMULATION_DELAY:4" \ -"SHOW_BANK_0_CALIB_STATUS_ENABLED:false" \ -"SHOW_BANK_0_RECALIBRATION_ENABLED:true" \ -"SHOW_BANK_0_VDDI_STATUS_ENABLED:true" \ -"SHOW_BANK_1_CALIB_STATUS_ENABLED:false" \ -"SHOW_BANK_1_RECALIBRATION_ENABLED:true" \ -"SHOW_BANK_1_VDDI_STATUS_ENABLED:true" \ -"SHOW_BANK_7_CALIB_STATUS_ENABLED:false" \ -"SHOW_BANK_7_RECALIBRATION_ENABLED:false" \ -"SHOW_BANK_7_VDDI_STATUS_ENABLED:false" \ -"SHOW_BANK_8_CALIB_STATUS_ENABLED:false" \ -"SHOW_BANK_8_RECALIBRATION_ENABLED:0" \ -"SHOW_BANK_8_VDDI_STATUS_ENABLED:false" \ -"SHOW_BANK_9_CALIB_STATUS_ENABLED:false" \ -"SHOW_BANK_9_RECALIBRATION_ENABLED:false" \ -"SHOW_BANK_9_VDDI_STATUS_ENABLED:false" \ -"SRAM_INIT_DONE_SIMULATION_DELAY:6" \ -"USRAM_INIT_DONE_SIMULATION_DELAY:5" } -# Exporting Component Description of INIT_MONITOR to TCL done +# Exporting Component Description of INIT_MONITOR to TCL +# Family: PolarFireSoC +# Part Number: MPFS250T_ES-1FCG1152E +# Create and Configure the core component INIT_MONITOR +create_and_configure_core -core_vlnv {Microsemi:SgCore:PFSOC_INIT_MONITOR:1.0.304} -component_name {INIT_MONITOR} -params {\ +"BANK_0_CALIB_STATUS_ENABLED:false" \ +"BANK_0_CALIB_STATUS_SIMULATION_DELAY:1" \ +"BANK_0_RECALIBRATION_ENABLED:false" \ +"BANK_0_VDDI_STATUS_ENABLED:false" \ +"BANK_0_VDDI_STATUS_SIMULATION_DELAY:1" \ +"BANK_1_CALIB_STATUS_ENABLED:false" \ +"BANK_1_CALIB_STATUS_SIMULATION_DELAY:1" \ +"BANK_1_RECALIBRATION_ENABLED:false" \ +"BANK_1_VDDI_STATUS_ENABLED:false" \ +"BANK_1_VDDI_STATUS_SIMULATION_DELAY:1" \ +"BANK_7_CALIB_STATUS_ENABLED:true" \ +"BANK_7_CALIB_STATUS_SIMULATION_DELAY:1" \ +"BANK_7_RECALIBRATION_ENABLED:false" \ +"BANK_7_VDDI_STATUS_ENABLED:false" \ +"BANK_7_VDDI_STATUS_SIMULATION_DELAY:1" \ +"BANK_8_CALIB_STATUS_ENABLED:true" \ +"BANK_8_CALIB_STATUS_SIMULATION_DELAY:1" \ +"BANK_8_RECALIBRATION_ENABLED:false" \ +"BANK_8_VDDI_STATUS_ENABLED:false" \ +"BANK_8_VDDI_STATUS_SIMULATION_DELAY:1" \ +"BANK_9_CALIB_STATUS_ENABLED:true" \ +"BANK_9_CALIB_STATUS_SIMULATION_DELAY:1" \ +"BANK_9_RECALIBRATION_ENABLED:false" \ +"BANK_9_VDDI_STATUS_ENABLED:false" \ +"BANK_9_VDDI_STATUS_SIMULATION_DELAY:1" \ +"DEVICE_INIT_DONE_SIMULATION_DELAY:7" \ +"FABRIC_POR_N_SIMULATION_DELAY:1" \ +"LATCH_SC_OUTPUTS:false" \ +"PCIE_INIT_DONE_SIMULATION_DELAY:4" \ +"SHOW_BANK_0_CALIB_STATUS_ENABLED:false" \ +"SHOW_BANK_0_RECALIBRATION_ENABLED:true" \ +"SHOW_BANK_0_VDDI_STATUS_ENABLED:true" \ +"SHOW_BANK_1_CALIB_STATUS_ENABLED:false" \ +"SHOW_BANK_1_RECALIBRATION_ENABLED:true" \ +"SHOW_BANK_1_VDDI_STATUS_ENABLED:true" \ +"SHOW_BANK_7_CALIB_STATUS_ENABLED:false" \ +"SHOW_BANK_7_RECALIBRATION_ENABLED:false" \ +"SHOW_BANK_7_VDDI_STATUS_ENABLED:false" \ +"SHOW_BANK_8_CALIB_STATUS_ENABLED:false" \ +"SHOW_BANK_8_RECALIBRATION_ENABLED:0" \ +"SHOW_BANK_8_VDDI_STATUS_ENABLED:false" \ +"SHOW_BANK_9_CALIB_STATUS_ENABLED:false" \ +"SHOW_BANK_9_RECALIBRATION_ENABLED:false" \ +"SHOW_BANK_9_VDDI_STATUS_ENABLED:false" \ +"SRAM_INIT_DONE_SIMULATION_DELAY:6" \ +"USRAM_INIT_DONE_SIMULATION_DELAY:5" } +# Exporting Component Description of INIT_MONITOR to TCL done diff --git a/script_support/components/Image_Enhancement_C0.tcl b/script_support/components/Image_Enhancement_C0.tcl index a8502d9..d067e24 100644 --- a/script_support/components/Image_Enhancement_C0.tcl +++ b/script_support/components/Image_Enhancement_C0.tcl @@ -1,10 +1,10 @@ -# Exporting Component Description of Image_Enhancement_C0 to TCL -# Family: PolarFireSoC -# Part Number: MPFS250T_ES-1FCG1152E -# Create and Configure the core component Image_Enhancement_C0 -create_and_configure_core -core_vlnv {Microsemi:SolutionCore:Image_Enhancement:4.3.0} -component_name {Image_Enhancement_C0} -params {\ -"G_CONFIG:0" \ -"G_FORMAT:0" \ -"G_PIXEL_WIDTH:8" \ -"G_PIXELS:1" } -# Exporting Component Description of Image_Enhancement_C0 to TCL done +# Exporting Component Description of Image_Enhancement_C0 to TCL +# Family: PolarFireSoC +# Part Number: MPFS250T_ES-1FCG1152E +# Create and Configure the core component Image_Enhancement_C0 +create_and_configure_core -core_vlnv {Microsemi:SolutionCore:Image_Enhancement:4.3.0} -component_name {Image_Enhancement_C0} -params {\ +"G_CONFIG:0" \ +"G_FORMAT:0" \ +"G_PIXEL_WIDTH:8" \ +"G_PIXELS:1" } +# Exporting Component Description of Image_Enhancement_C0 to TCL done diff --git a/script_support/components/PF_CCC_C0.tcl b/script_support/components/PF_CCC_C0.tcl index 344d73f..8682069 100644 --- a/script_support/components/PF_CCC_C0.tcl +++ b/script_support/components/PF_CCC_C0.tcl @@ -1,248 +1,248 @@ -# Exporting Component Description of PF_CCC_C0 to TCL -# Family: PolarFireSoC -# Part Number: MPFS250T_ES-1FCG1152E -# Create and Configure the core component PF_CCC_C0 -create_and_configure_core -core_vlnv {Actel:SgCore:PF_CCC:2.2.214} -component_name {PF_CCC_C0} -params {\ -"DLL_CLK_0_BANKCLK_EN:false" \ -"DLL_CLK_0_DEDICATED_EN:false" \ -"DLL_CLK_0_FABCLK_EN:false" \ -"DLL_CLK_1_BANKCLK_EN:false" \ -"DLL_CLK_1_DEDICATED_EN:false" \ -"DLL_CLK_1_FABCLK_EN:false" \ -"DLL_CLK_P_EN:false" \ -"DLL_CLK_P_OPTIONS_EN:false" \ -"DLL_CLK_REF_OPTION:DIVIDE_BY_1" \ -"DLL_CLK_REF_OPTIONS_EN:false" \ -"DLL_CLK_S_EN:false" \ -"DLL_CLK_S_OPTION:DIVIDE_BY_1" \ -"DLL_CLK_S_OPTIONS_EN:false" \ -"DLL_DELAY4:0" \ -"DLL_DYNAMIC_CODE_EN:false" \ -"DLL_DYNAMIC_RECONFIG_INTERFACE_EN:false" \ -"DLL_EXPORT_PWRDWN:false" \ -"DLL_FB_CLK:Primary" \ -"DLL_FB_EN:false" \ -"DLL_FINE_PHASE_CODE:0" \ -"DLL_IN:133" \ -"DLL_JITTER:0" \ -"DLL_MODE:PHASE_REF_MODE" \ -"DLL_ONLY_EN:false" \ -"DLL_OUT_0:1" \ -"DLL_OUT_1:1" \ -"DLL_PRIM_PHASE:90" \ -"DLL_PRIM_PHASE_CODE:0" \ -"DLL_SEC_PHASE:90" \ -"DLL_SEC_PHASE_CODE:0" \ -"DLL_SELECTED_IN:Output2" \ -"FF_REQUIRES_LOCK_EN_0:0" \ -"GL0_0_BANKCLK_USED:false" \ -"GL0_0_BYPASS:0" \ -"GL0_0_BYPASS_EN:false" \ -"GL0_0_DEDICATED_USED:false" \ -"GL0_0_DIV:8" \ -"GL0_0_DIVSTART:0" \ -"GL0_0_DYNAMIC_PH:false" \ -"GL0_0_EXPOSE_EN:false" \ -"GL0_0_FABCLK_GATED_USED:false" \ -"GL0_0_FABCLK_USED:true" \ -"GL0_0_FREQ_SEL:false" \ -"GL0_0_IS_USED:true" \ -"GL0_0_OUT_FREQ:125" \ -"GL0_0_PHASE_INDEX:0" \ -"GL0_0_PHASE_SEL:false" \ -"GL0_0_PLL_PHASE:0" \ -"GL0_1_BANKCLK_USED:false" \ -"GL0_1_BYPASS:0" \ -"GL0_1_BYPASS_EN:false" \ -"GL0_1_DEDICATED_USED:false" \ -"GL0_1_DIV:1" \ -"GL0_1_DIVSTART:0" \ -"GL0_1_DYNAMIC_PH:false" \ -"GL0_1_EXPOSE_EN:false" \ -"GL0_1_FABCLK_USED:false" \ -"GL0_1_FREQ_SEL:false" \ -"GL0_1_IS_USED:true" \ -"GL0_1_OUT_FREQ:100" \ -"GL0_1_PHASE_INDEX:0" \ -"GL0_1_PHASE_SEL:false" \ -"GL0_1_PLL_PHASE:0" \ -"GL1_0_BANKCLK_USED:false" \ -"GL1_0_BYPASS:0" \ -"GL1_0_BYPASS_EN:false" \ -"GL1_0_DEDICATED_USED:false" \ -"GL1_0_DIV:20" \ -"GL1_0_DIVSTART:0" \ -"GL1_0_DYNAMIC_PH:false" \ -"GL1_0_EXPOSE_EN:false" \ -"GL1_0_FABCLK_GATED_USED:false" \ -"GL1_0_FABCLK_USED:true" \ -"GL1_0_FREQ_SEL:false" \ -"GL1_0_IS_USED:true" \ -"GL1_0_OUT_FREQ:50" \ -"GL1_0_PHASE_INDEX:0" \ -"GL1_0_PHASE_SEL:false" \ -"GL1_0_PLL_PHASE:0" \ -"GL1_1_BANKCLK_USED:false" \ -"GL1_1_BYPASS:0" \ -"GL1_1_BYPASS_EN:false" \ -"GL1_1_DEDICATED_USED:false" \ -"GL1_1_DIV:1" \ -"GL1_1_DIVSTART:0" \ -"GL1_1_DYNAMIC_PH:false" \ -"GL1_1_EXPOSE_EN:false" \ -"GL1_1_FABCLK_USED:false" \ -"GL1_1_FREQ_SEL:false" \ -"GL1_1_IS_USED:false" \ -"GL1_1_OUT_FREQ:0" \ -"GL1_1_PHASE_INDEX:0" \ -"GL1_1_PHASE_SEL:false" \ -"GL1_1_PLL_PHASE:0" \ -"GL2_0_BANKCLK_USED:false" \ -"GL2_0_BYPASS:0" \ -"GL2_0_BYPASS_EN:false" \ -"GL2_0_DEDICATED_USED:false" \ -"GL2_0_DIV:50" \ -"GL2_0_DIVSTART:0" \ -"GL2_0_DYNAMIC_PH:false" \ -"GL2_0_EXPOSE_EN:false" \ -"GL2_0_FABCLK_GATED_USED:false" \ -"GL2_0_FABCLK_USED:true" \ -"GL2_0_FREQ_SEL:false" \ -"GL2_0_IS_USED:false" \ -"GL2_0_OUT_FREQ:20" \ -"GL2_0_PHASE_INDEX:0" \ -"GL2_0_PHASE_SEL:false" \ -"GL2_0_PLL_PHASE:0" \ -"GL2_1_BANKCLK_USED:false" \ -"GL2_1_BYPASS:0" \ -"GL2_1_BYPASS_EN:false" \ -"GL2_1_DEDICATED_USED:false" \ -"GL2_1_DIV:1" \ -"GL2_1_DIVSTART:0" \ -"GL2_1_DYNAMIC_PH:false" \ -"GL2_1_EXPOSE_EN:false" \ -"GL2_1_FABCLK_USED:false" \ -"GL2_1_FREQ_SEL:false" \ -"GL2_1_IS_USED:false" \ -"GL2_1_OUT_FREQ:0" \ -"GL2_1_PHASE_INDEX:0" \ -"GL2_1_PHASE_SEL:false" \ -"GL2_1_PLL_PHASE:0" \ -"GL3_0_BANKCLK_USED:false" \ -"GL3_0_BYPASS:0" \ -"GL3_0_BYPASS_EN:false" \ -"GL3_0_DEDICATED_USED:false" \ -"GL3_0_DIV:1" \ -"GL3_0_DIVSTART:0" \ -"GL3_0_DYNAMIC_PH:false" \ -"GL3_0_EXPOSE_EN:false" \ -"GL3_0_FABCLK_GATED_USED:false" \ -"GL3_0_FABCLK_USED:true" \ -"GL3_0_FREQ_SEL:false" \ -"GL3_0_IS_USED:false" \ -"GL3_0_OUT_FREQ:100" \ -"GL3_0_PHASE_INDEX:0" \ -"GL3_0_PHASE_SEL:false" \ -"GL3_0_PLL_PHASE:0" \ -"GL3_1_BANKCLK_USED:false" \ -"GL3_1_BYPASS:0" \ -"GL3_1_BYPASS_EN:false" \ -"GL3_1_DEDICATED_USED:false" \ -"GL3_1_DIV:1" \ -"GL3_1_DIVSTART:0" \ -"GL3_1_DYNAMIC_PH:false" \ -"GL3_1_EXPOSE_EN:false" \ -"GL3_1_FABCLK_USED:false" \ -"GL3_1_FREQ_SEL:false" \ -"GL3_1_IS_USED:false" \ -"GL3_1_OUT_FREQ:0" \ -"GL3_1_PHASE_INDEX:0" \ -"GL3_1_PHASE_SEL:false" \ -"GL3_1_PLL_PHASE:0" \ -"PLL_ALLOW_CCC_EXT_FB:false" \ -"PLL_BANDWIDTH_0:2" \ -"PLL_BANDWIDTH_1:1" \ -"PLL_BYPASS_GO_B_0:false" \ -"PLL_BYPASS_GO_B_1:false" \ -"PLL_BYPASS_POST_0:0" \ -"PLL_BYPASS_POST_0_0:false" \ -"PLL_BYPASS_POST_0_1:false" \ -"PLL_BYPASS_POST_0_2:false" \ -"PLL_BYPASS_POST_0_3:false" \ -"PLL_BYPASS_POST_1:0" \ -"PLL_BYPASS_POST_1_0:false" \ -"PLL_BYPASS_POST_1_1:false" \ -"PLL_BYPASS_POST_1_2:false" \ -"PLL_BYPASS_POST_1_3:false" \ -"PLL_BYPASS_PRE_0:0" \ -"PLL_BYPASS_PRE_0_0:false" \ -"PLL_BYPASS_PRE_0_1:false" \ -"PLL_BYPASS_PRE_0_2:false" \ -"PLL_BYPASS_PRE_0_3:false" \ -"PLL_BYPASS_PRE_1:0" \ -"PLL_BYPASS_PRE_1_0:false" \ -"PLL_BYPASS_PRE_1_1:false" \ -"PLL_BYPASS_PRE_1_2:false" \ -"PLL_BYPASS_PRE_1_3:false" \ -"PLL_BYPASS_SEL_0:0" \ -"PLL_BYPASS_SEL_0_0:false" \ -"PLL_BYPASS_SEL_0_1:false" \ -"PLL_BYPASS_SEL_0_2:false" \ -"PLL_BYPASS_SEL_0_3:false" \ -"PLL_BYPASS_SEL_1:0" \ -"PLL_BYPASS_SEL_1_0:false" \ -"PLL_BYPASS_SEL_1_1:false" \ -"PLL_BYPASS_SEL_1_2:false" \ -"PLL_BYPASS_SEL_1_3:false" \ -"PLL_DELAY_LINE_REF_FB_0:false" \ -"PLL_DELAY_LINE_REF_FB_1:false" \ -"PLL_DELAY_LINE_USED_0:false" \ -"PLL_DELAY_LINE_USED_1:false" \ -"PLL_DELAY_STEPS_0:1" \ -"PLL_DELAY_STEPS_1:1" \ -"PLL_DLL_CASCADED_EN:false" \ -"PLL_DYNAMIC_CONTROL_EN_0:true" \ -"PLL_DYNAMIC_CONTROL_EN_1:false" \ -"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_0:false" \ -"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_1:false" \ -"PLL_EXPORT_PWRDWN:false" \ -"PLL_EXT_MAX_ADDR_0:128" \ -"PLL_EXT_MAX_ADDR_1:128" \ -"PLL_EXT_WAVE_SEL_0:0" \ -"PLL_EXT_WAVE_SEL_1:0" \ -"PLL_FB_CLK_0:GL0_0" \ -"PLL_FB_CLK_1:GL0_1" \ -"PLL_FEEDBACK_MODE_0:Post-VCO" \ -"PLL_FEEDBACK_MODE_1:Post-VCO" \ -"PLL_IN_FREQ_0:148.5" \ -"PLL_IN_FREQ_1:100" \ -"PLL_INT_MODE_EN_0:false" \ -"PLL_INT_MODE_EN_1:false" \ -"PLL_LOCK_COUNT_0:0" \ -"PLL_LOCK_COUNT_1:0" \ -"PLL_LP_REQUIRES_LOCK_EN_0:false" \ -"PLL_LP_REQUIRES_LOCK_EN_1:false" \ -"PLL_PLL_CASCADED_EN:false" \ -"PLL_PLL_CASCADED_SELECTED_CLK:Output2" \ -"PLL_POSTDIVIDERADDSOFTLOGIC_0:true" \ -"PLL_REF_CLK_SEL_0:false" \ -"PLL_REF_CLK_SEL_1:false" \ -"PLL_REFDIV_0:1" \ -"PLL_REFDIV_1:1" \ -"PLL_SPREAD_MODE_0:false" \ -"PLL_SPREAD_MODE_1:false" \ -"PLL_SSM_DEPTH_0:5" \ -"PLL_SSM_DEPTH_1:5" \ -"PLL_SSM_DIVVAL_0:1" \ -"PLL_SSM_DIVVAL_1:1" \ -"PLL_SSM_FREQ_0:32" \ -"PLL_SSM_FREQ_1:32" \ -"PLL_SSM_RAND_PATTERN_0:2" \ -"PLL_SSM_RAND_PATTERN_1:2" \ -"PLL_SSMD_EN_0:false" \ -"PLL_SSMD_EN_1:false" \ -"PLL_SYNC_CORNER_PLL:false" \ -"PLL_SYNC_EN:false" \ -"PLL_VCO_MODE_0:MIN_JITTER" \ -"PLL_VCO_MODE_1:MIN_JITTER" } -# Exporting Component Description of PF_CCC_C0 to TCL done +# Exporting Component Description of PF_CCC_C0 to TCL +# Family: PolarFireSoC +# Part Number: MPFS250T_ES-1FCG1152E +# Create and Configure the core component PF_CCC_C0 +create_and_configure_core -core_vlnv {Actel:SgCore:PF_CCC:2.2.220} -component_name {PF_CCC_C0} -params {\ +"DLL_CLK_0_BANKCLK_EN:false" \ +"DLL_CLK_0_DEDICATED_EN:false" \ +"DLL_CLK_0_FABCLK_EN:false" \ +"DLL_CLK_1_BANKCLK_EN:false" \ +"DLL_CLK_1_DEDICATED_EN:false" \ +"DLL_CLK_1_FABCLK_EN:false" \ +"DLL_CLK_P_EN:false" \ +"DLL_CLK_P_OPTIONS_EN:false" \ +"DLL_CLK_REF_OPTION:DIVIDE_BY_1" \ +"DLL_CLK_REF_OPTIONS_EN:false" \ +"DLL_CLK_S_EN:false" \ +"DLL_CLK_S_OPTION:DIVIDE_BY_1" \ +"DLL_CLK_S_OPTIONS_EN:false" \ +"DLL_DELAY4:0" \ +"DLL_DYNAMIC_CODE_EN:false" \ +"DLL_DYNAMIC_RECONFIG_INTERFACE_EN:false" \ +"DLL_EXPORT_PWRDWN:false" \ +"DLL_FB_CLK:Primary" \ +"DLL_FB_EN:false" \ +"DLL_FINE_PHASE_CODE:0" \ +"DLL_IN:133" \ +"DLL_JITTER:0" \ +"DLL_MODE:PHASE_REF_MODE" \ +"DLL_ONLY_EN:false" \ +"DLL_OUT_0:1" \ +"DLL_OUT_1:1" \ +"DLL_PRIM_PHASE:90" \ +"DLL_PRIM_PHASE_CODE:0" \ +"DLL_SEC_PHASE:90" \ +"DLL_SEC_PHASE_CODE:0" \ +"DLL_SELECTED_IN:Output2" \ +"FF_REQUIRES_LOCK_EN_0:0" \ +"GL0_0_BANKCLK_USED:false" \ +"GL0_0_BYPASS:0" \ +"GL0_0_BYPASS_EN:false" \ +"GL0_0_DEDICATED_USED:false" \ +"GL0_0_DIV:8" \ +"GL0_0_DIVSTART:0" \ +"GL0_0_DYNAMIC_PH:false" \ +"GL0_0_EXPOSE_EN:false" \ +"GL0_0_FABCLK_GATED_USED:false" \ +"GL0_0_FABCLK_USED:true" \ +"GL0_0_FREQ_SEL:false" \ +"GL0_0_IS_USED:true" \ +"GL0_0_OUT_FREQ:125" \ +"GL0_0_PHASE_INDEX:0" \ +"GL0_0_PHASE_SEL:false" \ +"GL0_0_PLL_PHASE:0" \ +"GL0_1_BANKCLK_USED:false" \ +"GL0_1_BYPASS:0" \ +"GL0_1_BYPASS_EN:false" \ +"GL0_1_DEDICATED_USED:false" \ +"GL0_1_DIV:1" \ +"GL0_1_DIVSTART:0" \ +"GL0_1_DYNAMIC_PH:false" \ +"GL0_1_EXPOSE_EN:false" \ +"GL0_1_FABCLK_USED:false" \ +"GL0_1_FREQ_SEL:false" \ +"GL0_1_IS_USED:true" \ +"GL0_1_OUT_FREQ:100" \ +"GL0_1_PHASE_INDEX:0" \ +"GL0_1_PHASE_SEL:false" \ +"GL0_1_PLL_PHASE:0" \ +"GL1_0_BANKCLK_USED:false" \ +"GL1_0_BYPASS:0" \ +"GL1_0_BYPASS_EN:false" \ +"GL1_0_DEDICATED_USED:false" \ +"GL1_0_DIV:20" \ +"GL1_0_DIVSTART:0" \ +"GL1_0_DYNAMIC_PH:false" \ +"GL1_0_EXPOSE_EN:false" \ +"GL1_0_FABCLK_GATED_USED:false" \ +"GL1_0_FABCLK_USED:true" \ +"GL1_0_FREQ_SEL:false" \ +"GL1_0_IS_USED:true" \ +"GL1_0_OUT_FREQ:50" \ +"GL1_0_PHASE_INDEX:0" \ +"GL1_0_PHASE_SEL:false" \ +"GL1_0_PLL_PHASE:0" \ +"GL1_1_BANKCLK_USED:false" \ +"GL1_1_BYPASS:0" \ +"GL1_1_BYPASS_EN:false" \ +"GL1_1_DEDICATED_USED:false" \ +"GL1_1_DIV:1" \ +"GL1_1_DIVSTART:0" \ +"GL1_1_DYNAMIC_PH:false" \ +"GL1_1_EXPOSE_EN:false" \ +"GL1_1_FABCLK_USED:false" \ +"GL1_1_FREQ_SEL:false" \ +"GL1_1_IS_USED:false" \ +"GL1_1_OUT_FREQ:0" \ +"GL1_1_PHASE_INDEX:0" \ +"GL1_1_PHASE_SEL:false" \ +"GL1_1_PLL_PHASE:0" \ +"GL2_0_BANKCLK_USED:false" \ +"GL2_0_BYPASS:0" \ +"GL2_0_BYPASS_EN:false" \ +"GL2_0_DEDICATED_USED:false" \ +"GL2_0_DIV:50" \ +"GL2_0_DIVSTART:0" \ +"GL2_0_DYNAMIC_PH:false" \ +"GL2_0_EXPOSE_EN:false" \ +"GL2_0_FABCLK_GATED_USED:false" \ +"GL2_0_FABCLK_USED:true" \ +"GL2_0_FREQ_SEL:false" \ +"GL2_0_IS_USED:false" \ +"GL2_0_OUT_FREQ:20" \ +"GL2_0_PHASE_INDEX:0" \ +"GL2_0_PHASE_SEL:false" \ +"GL2_0_PLL_PHASE:0" \ +"GL2_1_BANKCLK_USED:false" \ +"GL2_1_BYPASS:0" \ +"GL2_1_BYPASS_EN:false" \ +"GL2_1_DEDICATED_USED:false" \ +"GL2_1_DIV:1" \ +"GL2_1_DIVSTART:0" \ +"GL2_1_DYNAMIC_PH:false" \ +"GL2_1_EXPOSE_EN:false" \ +"GL2_1_FABCLK_USED:false" \ +"GL2_1_FREQ_SEL:false" \ +"GL2_1_IS_USED:false" \ +"GL2_1_OUT_FREQ:0" \ +"GL2_1_PHASE_INDEX:0" \ +"GL2_1_PHASE_SEL:false" \ +"GL2_1_PLL_PHASE:0" \ +"GL3_0_BANKCLK_USED:false" \ +"GL3_0_BYPASS:0" \ +"GL3_0_BYPASS_EN:false" \ +"GL3_0_DEDICATED_USED:false" \ +"GL3_0_DIV:1" \ +"GL3_0_DIVSTART:0" \ +"GL3_0_DYNAMIC_PH:false" \ +"GL3_0_EXPOSE_EN:false" \ +"GL3_0_FABCLK_GATED_USED:false" \ +"GL3_0_FABCLK_USED:true" \ +"GL3_0_FREQ_SEL:false" \ +"GL3_0_IS_USED:false" \ +"GL3_0_OUT_FREQ:100" \ +"GL3_0_PHASE_INDEX:0" \ +"GL3_0_PHASE_SEL:false" \ +"GL3_0_PLL_PHASE:0" \ +"GL3_1_BANKCLK_USED:false" \ +"GL3_1_BYPASS:0" \ +"GL3_1_BYPASS_EN:false" \ +"GL3_1_DEDICATED_USED:false" \ +"GL3_1_DIV:1" \ +"GL3_1_DIVSTART:0" \ +"GL3_1_DYNAMIC_PH:false" \ +"GL3_1_EXPOSE_EN:false" \ +"GL3_1_FABCLK_USED:false" \ +"GL3_1_FREQ_SEL:false" \ +"GL3_1_IS_USED:false" \ +"GL3_1_OUT_FREQ:0" \ +"GL3_1_PHASE_INDEX:0" \ +"GL3_1_PHASE_SEL:false" \ +"GL3_1_PLL_PHASE:0" \ +"PLL_ALLOW_CCC_EXT_FB:false" \ +"PLL_BANDWIDTH_0:2" \ +"PLL_BANDWIDTH_1:1" \ +"PLL_BYPASS_GO_B_0:false" \ +"PLL_BYPASS_GO_B_1:false" \ +"PLL_BYPASS_POST_0:0" \ +"PLL_BYPASS_POST_0_0:false" \ +"PLL_BYPASS_POST_0_1:false" \ +"PLL_BYPASS_POST_0_2:false" \ +"PLL_BYPASS_POST_0_3:false" \ +"PLL_BYPASS_POST_1:0" \ +"PLL_BYPASS_POST_1_0:false" \ +"PLL_BYPASS_POST_1_1:false" \ +"PLL_BYPASS_POST_1_2:false" \ +"PLL_BYPASS_POST_1_3:false" \ +"PLL_BYPASS_PRE_0:0" \ +"PLL_BYPASS_PRE_0_0:false" \ +"PLL_BYPASS_PRE_0_1:false" \ +"PLL_BYPASS_PRE_0_2:false" \ +"PLL_BYPASS_PRE_0_3:false" \ +"PLL_BYPASS_PRE_1:0" \ +"PLL_BYPASS_PRE_1_0:false" \ +"PLL_BYPASS_PRE_1_1:false" \ +"PLL_BYPASS_PRE_1_2:false" \ +"PLL_BYPASS_PRE_1_3:false" \ +"PLL_BYPASS_SEL_0:0" \ +"PLL_BYPASS_SEL_0_0:false" \ +"PLL_BYPASS_SEL_0_1:false" \ +"PLL_BYPASS_SEL_0_2:false" \ +"PLL_BYPASS_SEL_0_3:false" \ +"PLL_BYPASS_SEL_1:0" \ +"PLL_BYPASS_SEL_1_0:false" \ +"PLL_BYPASS_SEL_1_1:false" \ +"PLL_BYPASS_SEL_1_2:false" \ +"PLL_BYPASS_SEL_1_3:false" \ +"PLL_DELAY_LINE_REF_FB_0:false" \ +"PLL_DELAY_LINE_REF_FB_1:false" \ +"PLL_DELAY_LINE_USED_0:false" \ +"PLL_DELAY_LINE_USED_1:false" \ +"PLL_DELAY_STEPS_0:1" \ +"PLL_DELAY_STEPS_1:1" \ +"PLL_DLL_CASCADED_EN:false" \ +"PLL_DYNAMIC_CONTROL_EN_0:true" \ +"PLL_DYNAMIC_CONTROL_EN_1:false" \ +"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_0:false" \ +"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_1:false" \ +"PLL_EXPORT_PWRDWN:false" \ +"PLL_EXT_MAX_ADDR_0:128" \ +"PLL_EXT_MAX_ADDR_1:128" \ +"PLL_EXT_WAVE_SEL_0:0" \ +"PLL_EXT_WAVE_SEL_1:0" \ +"PLL_FB_CLK_0:GL0_0" \ +"PLL_FB_CLK_1:GL0_1" \ +"PLL_FEEDBACK_MODE_0:Post-VCO" \ +"PLL_FEEDBACK_MODE_1:Post-VCO" \ +"PLL_IN_FREQ_0:148.5" \ +"PLL_IN_FREQ_1:100" \ +"PLL_INT_MODE_EN_0:false" \ +"PLL_INT_MODE_EN_1:false" \ +"PLL_LOCK_COUNT_0:0" \ +"PLL_LOCK_COUNT_1:0" \ +"PLL_LP_REQUIRES_LOCK_EN_0:false" \ +"PLL_LP_REQUIRES_LOCK_EN_1:false" \ +"PLL_PLL_CASCADED_EN:false" \ +"PLL_PLL_CASCADED_SELECTED_CLK:Output2" \ +"PLL_POSTDIVIDERADDSOFTLOGIC_0:true" \ +"PLL_REF_CLK_SEL_0:false" \ +"PLL_REF_CLK_SEL_1:false" \ +"PLL_REFDIV_0:1" \ +"PLL_REFDIV_1:1" \ +"PLL_SPREAD_MODE_0:false" \ +"PLL_SPREAD_MODE_1:false" \ +"PLL_SSM_DEPTH_0:5" \ +"PLL_SSM_DEPTH_1:5" \ +"PLL_SSM_DIVVAL_0:1" \ +"PLL_SSM_DIVVAL_1:1" \ +"PLL_SSM_FREQ_0:32" \ +"PLL_SSM_FREQ_1:32" \ +"PLL_SSM_RAND_PATTERN_0:2" \ +"PLL_SSM_RAND_PATTERN_1:2" \ +"PLL_SSMD_EN_0:false" \ +"PLL_SSMD_EN_1:false" \ +"PLL_SYNC_CORNER_PLL:false" \ +"PLL_SYNC_EN:false" \ +"PLL_VCO_MODE_0:MIN_JITTER" \ +"PLL_VCO_MODE_1:MIN_JITTER" } +# Exporting Component Description of PF_CCC_C0 to TCL done diff --git a/script_support/components/PF_CCC_C2.tcl b/script_support/components/PF_CCC_C2.tcl index 54ba5e5..89b198a 100644 --- a/script_support/components/PF_CCC_C2.tcl +++ b/script_support/components/PF_CCC_C2.tcl @@ -1,248 +1,248 @@ -# Exporting Component Description of PF_CCC_C2 to TCL -# Family: PolarFireSoC -# Part Number: MPFS250T_ES-1FCG1152E -# Create and Configure the core component PF_CCC_C2 -create_and_configure_core -core_vlnv {Actel:SgCore:PF_CCC:2.2.214} -component_name {PF_CCC_C2} -params {\ -"DLL_CLK_0_BANKCLK_EN:false" \ -"DLL_CLK_0_DEDICATED_EN:false" \ -"DLL_CLK_0_FABCLK_EN:false" \ -"DLL_CLK_1_BANKCLK_EN:false" \ -"DLL_CLK_1_DEDICATED_EN:false" \ -"DLL_CLK_1_FABCLK_EN:false" \ -"DLL_CLK_P_EN:false" \ -"DLL_CLK_P_OPTIONS_EN:false" \ -"DLL_CLK_REF_OPTION:DIVIDE_BY_1" \ -"DLL_CLK_REF_OPTIONS_EN:false" \ -"DLL_CLK_S_EN:false" \ -"DLL_CLK_S_OPTION:DIVIDE_BY_1" \ -"DLL_CLK_S_OPTIONS_EN:false" \ -"DLL_DELAY4:0" \ -"DLL_DYNAMIC_CODE_EN:false" \ -"DLL_DYNAMIC_RECONFIG_INTERFACE_EN:false" \ -"DLL_EXPORT_PWRDWN:false" \ -"DLL_FB_CLK:Primary" \ -"DLL_FB_EN:false" \ -"DLL_FINE_PHASE_CODE:0" \ -"DLL_IN:133" \ -"DLL_JITTER:0" \ -"DLL_MODE:PHASE_REF_MODE" \ -"DLL_ONLY_EN:false" \ -"DLL_OUT_0:1" \ -"DLL_OUT_1:1" \ -"DLL_PRIM_PHASE:90" \ -"DLL_PRIM_PHASE_CODE:0" \ -"DLL_SEC_PHASE:90" \ -"DLL_SEC_PHASE_CODE:0" \ -"DLL_SELECTED_IN:Output2" \ -"FF_REQUIRES_LOCK_EN_0:0" \ -"GL0_0_BANKCLK_USED:false" \ -"GL0_0_BYPASS:0" \ -"GL0_0_BYPASS_EN:false" \ -"GL0_0_DEDICATED_USED:false" \ -"GL0_0_DIV:7" \ -"GL0_0_DIVSTART:0" \ -"GL0_0_DYNAMIC_PH:false" \ -"GL0_0_EXPOSE_EN:false" \ -"GL0_0_FABCLK_GATED_USED:false" \ -"GL0_0_FABCLK_USED:true" \ -"GL0_0_FREQ_SEL:false" \ -"GL0_0_IS_USED:true" \ -"GL0_0_OUT_FREQ:170" \ -"GL0_0_PHASE_INDEX:0" \ -"GL0_0_PHASE_SEL:false" \ -"GL0_0_PLL_PHASE:0" \ -"GL0_1_BANKCLK_USED:false" \ -"GL0_1_BYPASS:0" \ -"GL0_1_BYPASS_EN:false" \ -"GL0_1_DEDICATED_USED:false" \ -"GL0_1_DIV:1" \ -"GL0_1_DIVSTART:0" \ -"GL0_1_DYNAMIC_PH:false" \ -"GL0_1_EXPOSE_EN:false" \ -"GL0_1_FABCLK_USED:false" \ -"GL0_1_FREQ_SEL:false" \ -"GL0_1_IS_USED:true" \ -"GL0_1_OUT_FREQ:100" \ -"GL0_1_PHASE_INDEX:0" \ -"GL0_1_PHASE_SEL:false" \ -"GL0_1_PLL_PHASE:0" \ -"GL1_0_BANKCLK_USED:false" \ -"GL1_0_BYPASS:0" \ -"GL1_0_BYPASS_EN:false" \ -"GL1_0_DEDICATED_USED:false" \ -"GL1_0_DIV:1" \ -"GL1_0_DIVSTART:0" \ -"GL1_0_DYNAMIC_PH:false" \ -"GL1_0_EXPOSE_EN:false" \ -"GL1_0_FABCLK_GATED_USED:false" \ -"GL1_0_FABCLK_USED:true" \ -"GL1_0_FREQ_SEL:false" \ -"GL1_0_IS_USED:false" \ -"GL1_0_OUT_FREQ:100" \ -"GL1_0_PHASE_INDEX:0" \ -"GL1_0_PHASE_SEL:false" \ -"GL1_0_PLL_PHASE:0" \ -"GL1_1_BANKCLK_USED:false" \ -"GL1_1_BYPASS:0" \ -"GL1_1_BYPASS_EN:false" \ -"GL1_1_DEDICATED_USED:false" \ -"GL1_1_DIV:1" \ -"GL1_1_DIVSTART:0" \ -"GL1_1_DYNAMIC_PH:false" \ -"GL1_1_EXPOSE_EN:false" \ -"GL1_1_FABCLK_USED:false" \ -"GL1_1_FREQ_SEL:false" \ -"GL1_1_IS_USED:false" \ -"GL1_1_OUT_FREQ:0" \ -"GL1_1_PHASE_INDEX:0" \ -"GL1_1_PHASE_SEL:false" \ -"GL1_1_PLL_PHASE:0" \ -"GL2_0_BANKCLK_USED:false" \ -"GL2_0_BYPASS:0" \ -"GL2_0_BYPASS_EN:false" \ -"GL2_0_DEDICATED_USED:false" \ -"GL2_0_DIV:1" \ -"GL2_0_DIVSTART:0" \ -"GL2_0_DYNAMIC_PH:false" \ -"GL2_0_EXPOSE_EN:false" \ -"GL2_0_FABCLK_GATED_USED:false" \ -"GL2_0_FABCLK_USED:true" \ -"GL2_0_FREQ_SEL:false" \ -"GL2_0_IS_USED:false" \ -"GL2_0_OUT_FREQ:100" \ -"GL2_0_PHASE_INDEX:0" \ -"GL2_0_PHASE_SEL:false" \ -"GL2_0_PLL_PHASE:0" \ -"GL2_1_BANKCLK_USED:false" \ -"GL2_1_BYPASS:0" \ -"GL2_1_BYPASS_EN:false" \ -"GL2_1_DEDICATED_USED:false" \ -"GL2_1_DIV:1" \ -"GL2_1_DIVSTART:0" \ -"GL2_1_DYNAMIC_PH:false" \ -"GL2_1_EXPOSE_EN:false" \ -"GL2_1_FABCLK_USED:false" \ -"GL2_1_FREQ_SEL:false" \ -"GL2_1_IS_USED:false" \ -"GL2_1_OUT_FREQ:0" \ -"GL2_1_PHASE_INDEX:0" \ -"GL2_1_PHASE_SEL:false" \ -"GL2_1_PLL_PHASE:0" \ -"GL3_0_BANKCLK_USED:false" \ -"GL3_0_BYPASS:0" \ -"GL3_0_BYPASS_EN:false" \ -"GL3_0_DEDICATED_USED:false" \ -"GL3_0_DIV:1" \ -"GL3_0_DIVSTART:0" \ -"GL3_0_DYNAMIC_PH:false" \ -"GL3_0_EXPOSE_EN:false" \ -"GL3_0_FABCLK_GATED_USED:false" \ -"GL3_0_FABCLK_USED:true" \ -"GL3_0_FREQ_SEL:false" \ -"GL3_0_IS_USED:false" \ -"GL3_0_OUT_FREQ:100" \ -"GL3_0_PHASE_INDEX:0" \ -"GL3_0_PHASE_SEL:false" \ -"GL3_0_PLL_PHASE:0" \ -"GL3_1_BANKCLK_USED:false" \ -"GL3_1_BYPASS:0" \ -"GL3_1_BYPASS_EN:false" \ -"GL3_1_DEDICATED_USED:false" \ -"GL3_1_DIV:1" \ -"GL3_1_DIVSTART:0" \ -"GL3_1_DYNAMIC_PH:false" \ -"GL3_1_EXPOSE_EN:false" \ -"GL3_1_FABCLK_USED:false" \ -"GL3_1_FREQ_SEL:false" \ -"GL3_1_IS_USED:false" \ -"GL3_1_OUT_FREQ:0" \ -"GL3_1_PHASE_INDEX:0" \ -"GL3_1_PHASE_SEL:false" \ -"GL3_1_PLL_PHASE:0" \ -"PLL_ALLOW_CCC_EXT_FB:false" \ -"PLL_BANDWIDTH_0:2" \ -"PLL_BANDWIDTH_1:1" \ -"PLL_BYPASS_GO_B_0:false" \ -"PLL_BYPASS_GO_B_1:false" \ -"PLL_BYPASS_POST_0:0" \ -"PLL_BYPASS_POST_0_0:false" \ -"PLL_BYPASS_POST_0_1:false" \ -"PLL_BYPASS_POST_0_2:false" \ -"PLL_BYPASS_POST_0_3:false" \ -"PLL_BYPASS_POST_1:0" \ -"PLL_BYPASS_POST_1_0:false" \ -"PLL_BYPASS_POST_1_1:false" \ -"PLL_BYPASS_POST_1_2:false" \ -"PLL_BYPASS_POST_1_3:false" \ -"PLL_BYPASS_PRE_0:0" \ -"PLL_BYPASS_PRE_0_0:false" \ -"PLL_BYPASS_PRE_0_1:false" \ -"PLL_BYPASS_PRE_0_2:false" \ -"PLL_BYPASS_PRE_0_3:false" \ -"PLL_BYPASS_PRE_1:0" \ -"PLL_BYPASS_PRE_1_0:false" \ -"PLL_BYPASS_PRE_1_1:false" \ -"PLL_BYPASS_PRE_1_2:false" \ -"PLL_BYPASS_PRE_1_3:false" \ -"PLL_BYPASS_SEL_0:0" \ -"PLL_BYPASS_SEL_0_0:false" \ -"PLL_BYPASS_SEL_0_1:false" \ -"PLL_BYPASS_SEL_0_2:false" \ -"PLL_BYPASS_SEL_0_3:false" \ -"PLL_BYPASS_SEL_1:0" \ -"PLL_BYPASS_SEL_1_0:false" \ -"PLL_BYPASS_SEL_1_1:false" \ -"PLL_BYPASS_SEL_1_2:false" \ -"PLL_BYPASS_SEL_1_3:false" \ -"PLL_DELAY_LINE_REF_FB_0:false" \ -"PLL_DELAY_LINE_REF_FB_1:false" \ -"PLL_DELAY_LINE_USED_0:false" \ -"PLL_DELAY_LINE_USED_1:false" \ -"PLL_DELAY_STEPS_0:1" \ -"PLL_DELAY_STEPS_1:1" \ -"PLL_DLL_CASCADED_EN:false" \ -"PLL_DYNAMIC_CONTROL_EN_0:true" \ -"PLL_DYNAMIC_CONTROL_EN_1:false" \ -"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_0:false" \ -"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_1:false" \ -"PLL_EXPORT_PWRDWN:false" \ -"PLL_EXT_MAX_ADDR_0:128" \ -"PLL_EXT_MAX_ADDR_1:128" \ -"PLL_EXT_WAVE_SEL_0:0" \ -"PLL_EXT_WAVE_SEL_1:0" \ -"PLL_FB_CLK_0:GL0_0" \ -"PLL_FB_CLK_1:GL0_1" \ -"PLL_FEEDBACK_MODE_0:Post-VCO" \ -"PLL_FEEDBACK_MODE_1:Post-VCO" \ -"PLL_IN_FREQ_0:62.5" \ -"PLL_IN_FREQ_1:100" \ -"PLL_INT_MODE_EN_0:false" \ -"PLL_INT_MODE_EN_1:false" \ -"PLL_LOCK_COUNT_0:0" \ -"PLL_LOCK_COUNT_1:0" \ -"PLL_LP_REQUIRES_LOCK_EN_0:false" \ -"PLL_LP_REQUIRES_LOCK_EN_1:false" \ -"PLL_PLL_CASCADED_EN:false" \ -"PLL_PLL_CASCADED_SELECTED_CLK:Output2" \ -"PLL_POSTDIVIDERADDSOFTLOGIC_0:true" \ -"PLL_REF_CLK_SEL_0:false" \ -"PLL_REF_CLK_SEL_1:false" \ -"PLL_REFDIV_0:5" \ -"PLL_REFDIV_1:1" \ -"PLL_SPREAD_MODE_0:false" \ -"PLL_SPREAD_MODE_1:false" \ -"PLL_SSM_DEPTH_0:5" \ -"PLL_SSM_DEPTH_1:5" \ -"PLL_SSM_DIVVAL_0:1" \ -"PLL_SSM_DIVVAL_1:1" \ -"PLL_SSM_FREQ_0:32" \ -"PLL_SSM_FREQ_1:32" \ -"PLL_SSM_RAND_PATTERN_0:2" \ -"PLL_SSM_RAND_PATTERN_1:2" \ -"PLL_SSMD_EN_0:false" \ -"PLL_SSMD_EN_1:false" \ -"PLL_SYNC_CORNER_PLL:false" \ -"PLL_SYNC_EN:false" \ -"PLL_VCO_MODE_0:MIN_JITTER" \ -"PLL_VCO_MODE_1:MIN_JITTER" } -# Exporting Component Description of PF_CCC_C2 to TCL done +# Exporting Component Description of PF_CCC_C2 to TCL +# Family: PolarFireSoC +# Part Number: MPFS250T_ES-1FCG1152E +# Create and Configure the core component PF_CCC_C2 +create_and_configure_core -core_vlnv {Actel:SgCore:PF_CCC:2.2.220} -component_name {PF_CCC_C2} -params {\ +"DLL_CLK_0_BANKCLK_EN:false" \ +"DLL_CLK_0_DEDICATED_EN:false" \ +"DLL_CLK_0_FABCLK_EN:false" \ +"DLL_CLK_1_BANKCLK_EN:false" \ +"DLL_CLK_1_DEDICATED_EN:false" \ +"DLL_CLK_1_FABCLK_EN:false" \ +"DLL_CLK_P_EN:false" \ +"DLL_CLK_P_OPTIONS_EN:false" \ +"DLL_CLK_REF_OPTION:DIVIDE_BY_1" \ +"DLL_CLK_REF_OPTIONS_EN:false" \ +"DLL_CLK_S_EN:false" \ +"DLL_CLK_S_OPTION:DIVIDE_BY_1" \ +"DLL_CLK_S_OPTIONS_EN:false" \ +"DLL_DELAY4:0" \ +"DLL_DYNAMIC_CODE_EN:false" \ +"DLL_DYNAMIC_RECONFIG_INTERFACE_EN:false" \ +"DLL_EXPORT_PWRDWN:false" \ +"DLL_FB_CLK:Primary" \ +"DLL_FB_EN:false" \ +"DLL_FINE_PHASE_CODE:0" \ +"DLL_IN:133" \ +"DLL_JITTER:0" \ +"DLL_MODE:PHASE_REF_MODE" \ +"DLL_ONLY_EN:false" \ +"DLL_OUT_0:1" \ +"DLL_OUT_1:1" \ +"DLL_PRIM_PHASE:90" \ +"DLL_PRIM_PHASE_CODE:0" \ +"DLL_SEC_PHASE:90" \ +"DLL_SEC_PHASE_CODE:0" \ +"DLL_SELECTED_IN:Output2" \ +"FF_REQUIRES_LOCK_EN_0:0" \ +"GL0_0_BANKCLK_USED:false" \ +"GL0_0_BYPASS:0" \ +"GL0_0_BYPASS_EN:false" \ +"GL0_0_DEDICATED_USED:false" \ +"GL0_0_DIV:7" \ +"GL0_0_DIVSTART:0" \ +"GL0_0_DYNAMIC_PH:false" \ +"GL0_0_EXPOSE_EN:false" \ +"GL0_0_FABCLK_GATED_USED:false" \ +"GL0_0_FABCLK_USED:true" \ +"GL0_0_FREQ_SEL:false" \ +"GL0_0_IS_USED:true" \ +"GL0_0_OUT_FREQ:170" \ +"GL0_0_PHASE_INDEX:0" \ +"GL0_0_PHASE_SEL:false" \ +"GL0_0_PLL_PHASE:0" \ +"GL0_1_BANKCLK_USED:false" \ +"GL0_1_BYPASS:0" \ +"GL0_1_BYPASS_EN:false" \ +"GL0_1_DEDICATED_USED:false" \ +"GL0_1_DIV:1" \ +"GL0_1_DIVSTART:0" \ +"GL0_1_DYNAMIC_PH:false" \ +"GL0_1_EXPOSE_EN:false" \ +"GL0_1_FABCLK_USED:false" \ +"GL0_1_FREQ_SEL:false" \ +"GL0_1_IS_USED:true" \ +"GL0_1_OUT_FREQ:100" \ +"GL0_1_PHASE_INDEX:0" \ +"GL0_1_PHASE_SEL:false" \ +"GL0_1_PLL_PHASE:0" \ +"GL1_0_BANKCLK_USED:false" \ +"GL1_0_BYPASS:0" \ +"GL1_0_BYPASS_EN:false" \ +"GL1_0_DEDICATED_USED:false" \ +"GL1_0_DIV:1" \ +"GL1_0_DIVSTART:0" \ +"GL1_0_DYNAMIC_PH:false" \ +"GL1_0_EXPOSE_EN:false" \ +"GL1_0_FABCLK_GATED_USED:false" \ +"GL1_0_FABCLK_USED:true" \ +"GL1_0_FREQ_SEL:false" \ +"GL1_0_IS_USED:false" \ +"GL1_0_OUT_FREQ:100" \ +"GL1_0_PHASE_INDEX:0" \ +"GL1_0_PHASE_SEL:false" \ +"GL1_0_PLL_PHASE:0" \ +"GL1_1_BANKCLK_USED:false" \ +"GL1_1_BYPASS:0" \ +"GL1_1_BYPASS_EN:false" \ +"GL1_1_DEDICATED_USED:false" \ +"GL1_1_DIV:1" \ +"GL1_1_DIVSTART:0" \ +"GL1_1_DYNAMIC_PH:false" \ +"GL1_1_EXPOSE_EN:false" \ +"GL1_1_FABCLK_USED:false" \ +"GL1_1_FREQ_SEL:false" \ +"GL1_1_IS_USED:false" \ +"GL1_1_OUT_FREQ:0" \ +"GL1_1_PHASE_INDEX:0" \ +"GL1_1_PHASE_SEL:false" \ +"GL1_1_PLL_PHASE:0" \ +"GL2_0_BANKCLK_USED:false" \ +"GL2_0_BYPASS:0" \ +"GL2_0_BYPASS_EN:false" \ +"GL2_0_DEDICATED_USED:false" \ +"GL2_0_DIV:1" \ +"GL2_0_DIVSTART:0" \ +"GL2_0_DYNAMIC_PH:false" \ +"GL2_0_EXPOSE_EN:false" \ +"GL2_0_FABCLK_GATED_USED:false" \ +"GL2_0_FABCLK_USED:true" \ +"GL2_0_FREQ_SEL:false" \ +"GL2_0_IS_USED:false" \ +"GL2_0_OUT_FREQ:100" \ +"GL2_0_PHASE_INDEX:0" \ +"GL2_0_PHASE_SEL:false" \ +"GL2_0_PLL_PHASE:0" \ +"GL2_1_BANKCLK_USED:false" \ +"GL2_1_BYPASS:0" \ +"GL2_1_BYPASS_EN:false" \ +"GL2_1_DEDICATED_USED:false" \ +"GL2_1_DIV:1" \ +"GL2_1_DIVSTART:0" \ +"GL2_1_DYNAMIC_PH:false" \ +"GL2_1_EXPOSE_EN:false" \ +"GL2_1_FABCLK_USED:false" \ +"GL2_1_FREQ_SEL:false" \ +"GL2_1_IS_USED:false" \ +"GL2_1_OUT_FREQ:0" \ +"GL2_1_PHASE_INDEX:0" \ +"GL2_1_PHASE_SEL:false" \ +"GL2_1_PLL_PHASE:0" \ +"GL3_0_BANKCLK_USED:false" \ +"GL3_0_BYPASS:0" \ +"GL3_0_BYPASS_EN:false" \ +"GL3_0_DEDICATED_USED:false" \ +"GL3_0_DIV:1" \ +"GL3_0_DIVSTART:0" \ +"GL3_0_DYNAMIC_PH:false" \ +"GL3_0_EXPOSE_EN:false" \ +"GL3_0_FABCLK_GATED_USED:false" \ +"GL3_0_FABCLK_USED:true" \ +"GL3_0_FREQ_SEL:false" \ +"GL3_0_IS_USED:false" \ +"GL3_0_OUT_FREQ:100" \ +"GL3_0_PHASE_INDEX:0" \ +"GL3_0_PHASE_SEL:false" \ +"GL3_0_PLL_PHASE:0" \ +"GL3_1_BANKCLK_USED:false" \ +"GL3_1_BYPASS:0" \ +"GL3_1_BYPASS_EN:false" \ +"GL3_1_DEDICATED_USED:false" \ +"GL3_1_DIV:1" \ +"GL3_1_DIVSTART:0" \ +"GL3_1_DYNAMIC_PH:false" \ +"GL3_1_EXPOSE_EN:false" \ +"GL3_1_FABCLK_USED:false" \ +"GL3_1_FREQ_SEL:false" \ +"GL3_1_IS_USED:false" \ +"GL3_1_OUT_FREQ:0" \ +"GL3_1_PHASE_INDEX:0" \ +"GL3_1_PHASE_SEL:false" \ +"GL3_1_PLL_PHASE:0" \ +"PLL_ALLOW_CCC_EXT_FB:false" \ +"PLL_BANDWIDTH_0:2" \ +"PLL_BANDWIDTH_1:1" \ +"PLL_BYPASS_GO_B_0:false" \ +"PLL_BYPASS_GO_B_1:false" \ +"PLL_BYPASS_POST_0:0" \ +"PLL_BYPASS_POST_0_0:false" \ +"PLL_BYPASS_POST_0_1:false" \ +"PLL_BYPASS_POST_0_2:false" \ +"PLL_BYPASS_POST_0_3:false" \ +"PLL_BYPASS_POST_1:0" \ +"PLL_BYPASS_POST_1_0:false" \ +"PLL_BYPASS_POST_1_1:false" \ +"PLL_BYPASS_POST_1_2:false" \ +"PLL_BYPASS_POST_1_3:false" \ +"PLL_BYPASS_PRE_0:0" \ +"PLL_BYPASS_PRE_0_0:false" \ +"PLL_BYPASS_PRE_0_1:false" \ +"PLL_BYPASS_PRE_0_2:false" \ +"PLL_BYPASS_PRE_0_3:false" \ +"PLL_BYPASS_PRE_1:0" \ +"PLL_BYPASS_PRE_1_0:false" \ +"PLL_BYPASS_PRE_1_1:false" \ +"PLL_BYPASS_PRE_1_2:false" \ +"PLL_BYPASS_PRE_1_3:false" \ +"PLL_BYPASS_SEL_0:0" \ +"PLL_BYPASS_SEL_0_0:false" \ +"PLL_BYPASS_SEL_0_1:false" \ +"PLL_BYPASS_SEL_0_2:false" \ +"PLL_BYPASS_SEL_0_3:false" \ +"PLL_BYPASS_SEL_1:0" \ +"PLL_BYPASS_SEL_1_0:false" \ +"PLL_BYPASS_SEL_1_1:false" \ +"PLL_BYPASS_SEL_1_2:false" \ +"PLL_BYPASS_SEL_1_3:false" \ +"PLL_DELAY_LINE_REF_FB_0:false" \ +"PLL_DELAY_LINE_REF_FB_1:false" \ +"PLL_DELAY_LINE_USED_0:false" \ +"PLL_DELAY_LINE_USED_1:false" \ +"PLL_DELAY_STEPS_0:1" \ +"PLL_DELAY_STEPS_1:1" \ +"PLL_DLL_CASCADED_EN:false" \ +"PLL_DYNAMIC_CONTROL_EN_0:true" \ +"PLL_DYNAMIC_CONTROL_EN_1:false" \ +"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_0:false" \ +"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_1:false" \ +"PLL_EXPORT_PWRDWN:false" \ +"PLL_EXT_MAX_ADDR_0:128" \ +"PLL_EXT_MAX_ADDR_1:128" \ +"PLL_EXT_WAVE_SEL_0:0" \ +"PLL_EXT_WAVE_SEL_1:0" \ +"PLL_FB_CLK_0:GL0_0" \ +"PLL_FB_CLK_1:GL0_1" \ +"PLL_FEEDBACK_MODE_0:Post-VCO" \ +"PLL_FEEDBACK_MODE_1:Post-VCO" \ +"PLL_IN_FREQ_0:62.5" \ +"PLL_IN_FREQ_1:100" \ +"PLL_INT_MODE_EN_0:false" \ +"PLL_INT_MODE_EN_1:false" \ +"PLL_LOCK_COUNT_0:0" \ +"PLL_LOCK_COUNT_1:0" \ +"PLL_LP_REQUIRES_LOCK_EN_0:false" \ +"PLL_LP_REQUIRES_LOCK_EN_1:false" \ +"PLL_PLL_CASCADED_EN:false" \ +"PLL_PLL_CASCADED_SELECTED_CLK:Output2" \ +"PLL_POSTDIVIDERADDSOFTLOGIC_0:true" \ +"PLL_REF_CLK_SEL_0:false" \ +"PLL_REF_CLK_SEL_1:false" \ +"PLL_REFDIV_0:5" \ +"PLL_REFDIV_1:1" \ +"PLL_SPREAD_MODE_0:false" \ +"PLL_SPREAD_MODE_1:false" \ +"PLL_SSM_DEPTH_0:5" \ +"PLL_SSM_DEPTH_1:5" \ +"PLL_SSM_DIVVAL_0:1" \ +"PLL_SSM_DIVVAL_1:1" \ +"PLL_SSM_FREQ_0:32" \ +"PLL_SSM_FREQ_1:32" \ +"PLL_SSM_RAND_PATTERN_0:2" \ +"PLL_SSM_RAND_PATTERN_1:2" \ +"PLL_SSMD_EN_0:false" \ +"PLL_SSMD_EN_1:false" \ +"PLL_SYNC_CORNER_PLL:false" \ +"PLL_SYNC_EN:false" \ +"PLL_VCO_MODE_0:MIN_JITTER" \ +"PLL_VCO_MODE_1:MIN_JITTER" } +# Exporting Component Description of PF_CCC_C2 to TCL done diff --git a/script_support/components/PF_CLK_DIV_C0.tcl b/script_support/components/PF_CLK_DIV_C0.tcl index 43bcad2..40a1fd3 100644 --- a/script_support/components/PF_CLK_DIV_C0.tcl +++ b/script_support/components/PF_CLK_DIV_C0.tcl @@ -1,9 +1,9 @@ -# Exporting Component Description of PF_CLK_DIV_C0 to TCL -# Family: PolarFireSoC -# Part Number: MPFS250T_ES-1FCG1152E -# Create and Configure the core component PF_CLK_DIV_C0 -create_and_configure_core -core_vlnv {Actel:SgCore:PF_CLK_DIV:1.0.103} -component_name {PF_CLK_DIV_C0} -params {\ -"DIVIDER:2" \ -"ENABLE_BIT_SLIP:false" \ -"ENABLE_SRESET:false" } -# Exporting Component Description of PF_CLK_DIV_C0 to TCL done +# Exporting Component Description of PF_CLK_DIV_C0 to TCL +# Family: PolarFireSoC +# Part Number: MPFS250T_ES-1FCG1152E +# Create and Configure the core component PF_CLK_DIV_C0 +create_and_configure_core -core_vlnv {Actel:SgCore:PF_CLK_DIV:1.0.103} -component_name {PF_CLK_DIV_C0} -params {\ +"DIVIDER:2" \ +"ENABLE_BIT_SLIP:false" \ +"ENABLE_SRESET:false" } +# Exporting Component Description of PF_CLK_DIV_C0 to TCL done diff --git a/script_support/components/PF_IOD_GENERIC_RX_C0.tcl b/script_support/components/PF_IOD_GENERIC_RX_C0.tcl index 7d75c84..2be1a39 100644 --- a/script_support/components/PF_IOD_GENERIC_RX_C0.tcl +++ b/script_support/components/PF_IOD_GENERIC_RX_C0.tcl @@ -1,43 +1,43 @@ -# Exporting Component Description of PF_IOD_GENERIC_RX_C0 to TCL -# Family: PolarFireSoC -# Part Number: MPFS250T_ES-1FCG1152E -# Create and Configure the core component PF_IOD_GENERIC_RX_C0 -create_and_configure_core -core_vlnv {Actel:SystemBuilder:PF_IOD_GENERIC_RX:2.1.109} -component_name {PF_IOD_GENERIC_RX_C0} -params {\ -"CLOCK_DELAY_VALUE:0" \ -"DATA_RATE:500" \ -"DATA_RATIO:8" \ -"DATA_WIDTH:7" \ -"DDR_MODE:DDR" \ -"DYN_USE_WIDE_MODE:false" \ -"EXPOSE_CLK_TRAIN_PORTS:false" \ -"EXPOSE_DYNAMIC_DELAY_CTRL:false" \ -"EXPOSE_EXTRA_TRAINING_PORTS:false" \ -"EXPOSE_FA_CLK_DATA:false" \ -"EXPOSE_RX_RAW_DATA:false" \ -"FABRIC_CLK_SOURCE:GLOBAL" \ -"FRACTIONAL_CLOCK_RATIO:RATIO" \ -"ICB_BCLK_OFFSET:0" \ -"ICB_USE_WIDE_MODE:true" \ -"IO_NUMBER:4" \ -"NEED_LANECTRL:false" \ -"NEED_TIP:false" \ -"PLL_BCLK_OFFSET:3" \ -"RATIO:4" \ -"RXCTL_SPLIT_WIDTH:1" \ -"RXD_LVDS_FAILSAFE_EN:false" \ -"RXD_SPLIT_WIDTH:4" \ -"RX_BIT_SLIP_EN:false" \ -"RX_CLK_DIFFERENTIAL:true" \ -"RX_CLK_LVDS_FAILSAFE_EN:false" \ -"RX_CLK_SOURCE:HS_IO_CLK" \ -"RX_CLK_TO_DATA:DYNAMIC" \ -"RX_DATA_BUS_MODE:RX_DATA_PER_IO" \ -"RX_DATA_DIFFERENTIAL:true" \ -"RX_ENABLED:true" \ -"RX_INTERFACE_NAME:RX_DDRX_B_G_DYN" \ -"RX_IOG_ARCHETYPE:RX_DDRX_L_DYN_X4" \ -"RX_MIPI_MODE:true" \ -"SIMULATION_MODE:FULL" \ -"USE_SHARED_PLL:false" \ -"X1_ADD_DELAY_LINE_ON_CLOCK:false" } -# Exporting Component Description of PF_IOD_GENERIC_RX_C0 to TCL done +# Exporting Component Description of PF_IOD_GENERIC_RX_C0 to TCL +# Family: PolarFireSoC +# Part Number: MPFS250T_ES-1FCG1152E +# Create and Configure the core component PF_IOD_GENERIC_RX_C0 +create_and_configure_core -core_vlnv {Actel:SystemBuilder:PF_IOD_GENERIC_RX:2.1.110} -component_name {PF_IOD_GENERIC_RX_C0} -params {\ +"CLOCK_DELAY_VALUE:0" \ +"DATA_RATE:500" \ +"DATA_RATIO:8" \ +"DATA_WIDTH:7" \ +"DDR_MODE:DDR" \ +"DYN_USE_WIDE_MODE:false" \ +"EXPOSE_CLK_TRAIN_PORTS:false" \ +"EXPOSE_DYNAMIC_DELAY_CTRL:false" \ +"EXPOSE_EXTRA_TRAINING_PORTS:false" \ +"EXPOSE_FA_CLK_DATA:false" \ +"EXPOSE_RX_RAW_DATA:false" \ +"FABRIC_CLK_SOURCE:GLOBAL" \ +"FRACTIONAL_CLOCK_RATIO:RATIO" \ +"ICB_BCLK_OFFSET:0" \ +"ICB_USE_WIDE_MODE:true" \ +"IO_NUMBER:4" \ +"NEED_LANECTRL:false" \ +"NEED_TIP:false" \ +"PLL_BCLK_OFFSET:3" \ +"RATIO:4" \ +"RXCTL_SPLIT_WIDTH:1" \ +"RXD_LVDS_FAILSAFE_EN:false" \ +"RXD_SPLIT_WIDTH:4" \ +"RX_BIT_SLIP_EN:false" \ +"RX_CLK_DIFFERENTIAL:true" \ +"RX_CLK_LVDS_FAILSAFE_EN:false" \ +"RX_CLK_SOURCE:HS_IO_CLK" \ +"RX_CLK_TO_DATA:DYNAMIC" \ +"RX_DATA_BUS_MODE:RX_DATA_PER_IO" \ +"RX_DATA_DIFFERENTIAL:true" \ +"RX_ENABLED:true" \ +"RX_INTERFACE_NAME:RX_DDRX_B_G_DYN" \ +"RX_IOG_ARCHETYPE:RX_DDRX_L_DYN_X4" \ +"RX_MIPI_MODE:true" \ +"SIMULATION_MODE:FULL" \ +"USE_SHARED_PLL:false" \ +"X1_ADD_DELAY_LINE_ON_CLOCK:false" } +# Exporting Component Description of PF_IOD_GENERIC_RX_C0 to TCL done diff --git a/script_support/components/PF_OSC_C0.tcl b/script_support/components/PF_OSC_C0.tcl index e3dfd24..041166d 100644 --- a/script_support/components/PF_OSC_C0.tcl +++ b/script_support/components/PF_OSC_C0.tcl @@ -1,12 +1,12 @@ -# Exporting Component Description of PF_OSC_C0 to TCL -# Family: PolarFireSoC -# Part Number: MPFS250T_ES-1FCG1152E -# Create and Configure the core component PF_OSC_C0 -create_and_configure_core -core_vlnv {Actel:SgCore:PF_OSC:1.0.102} -component_name {PF_OSC_C0} -params {\ -"RCOSC_2MHZ_CLK_DIV_EN:true" \ -"RCOSC_2MHZ_GL_EN:false" \ -"RCOSC_2MHZ_NGMUX_EN:false" \ -"RCOSC_160MHZ_CLK_DIV_EN:false" \ -"RCOSC_160MHZ_GL_EN:false" \ -"RCOSC_160MHZ_NGMUX_EN:false" } -# Exporting Component Description of PF_OSC_C0 to TCL done +# Exporting Component Description of PF_OSC_C0 to TCL +# Family: PolarFireSoC +# Part Number: MPFS250T_ES-1FCG1152E +# Create and Configure the core component PF_OSC_C0 +create_and_configure_core -core_vlnv {Actel:SgCore:PF_OSC:1.0.102} -component_name {PF_OSC_C0} -params {\ +"RCOSC_2MHZ_CLK_DIV_EN:true" \ +"RCOSC_2MHZ_GL_EN:false" \ +"RCOSC_2MHZ_NGMUX_EN:false" \ +"RCOSC_160MHZ_CLK_DIV_EN:false" \ +"RCOSC_160MHZ_GL_EN:false" \ +"RCOSC_160MHZ_NGMUX_EN:false" } +# Exporting Component Description of PF_OSC_C0 to TCL done diff --git a/script_support/components/PF_XCVR_REF_CLK_C0.tcl b/script_support/components/PF_XCVR_REF_CLK_C0.tcl index 57638e7..c3a8372 100644 --- a/script_support/components/PF_XCVR_REF_CLK_C0.tcl +++ b/script_support/components/PF_XCVR_REF_CLK_C0.tcl @@ -1,12 +1,12 @@ -# Exporting Component Description of PF_XCVR_REF_CLK_C0 to TCL -# Family: PolarFireSoC -# Part Number: MPFS250T_ES-1FCG1152E -# Create and Configure the core component PF_XCVR_REF_CLK_C0 -create_and_configure_core -core_vlnv {Actel:SgCore:PF_XCVR_REF_CLK:1.0.103} -component_name {PF_XCVR_REF_CLK_C0} -params {\ -"ENABLE_FAB_CLK_0:true" \ -"ENABLE_FAB_CLK_1:false" \ -"ENABLE_REF_CLK_0:true" \ -"ENABLE_REF_CLK_1:false" \ -"REF_CLK_MODE_0:DIFFERENTIAL" \ -"REF_CLK_MODE_1:LVCMOS" } -# Exporting Component Description of PF_XCVR_REF_CLK_C0 to TCL done +# Exporting Component Description of PF_XCVR_REF_CLK_C0 to TCL +# Family: PolarFireSoC +# Part Number: MPFS250T_ES-1FCG1152E +# Create and Configure the core component PF_XCVR_REF_CLK_C0 +create_and_configure_core -core_vlnv {Actel:SgCore:PF_XCVR_REF_CLK:1.0.103} -component_name {PF_XCVR_REF_CLK_C0} -params {\ +"ENABLE_FAB_CLK_0:true" \ +"ENABLE_FAB_CLK_1:false" \ +"ENABLE_REF_CLK_0:true" \ +"ENABLE_REF_CLK_1:false" \ +"REF_CLK_MODE_0:DIFFERENTIAL" \ +"REF_CLK_MODE_1:LVCMOS" } +# Exporting Component Description of PF_XCVR_REF_CLK_C0 to TCL done diff --git a/script_support/components/apb3_if.tcl b/script_support/components/apb3_if.tcl index 8e90819..cb52cab 100644 --- a/script_support/components/apb3_if.tcl +++ b/script_support/components/apb3_if.tcl @@ -1,13 +1,13 @@ -# Exporting core apb3_if to TCL -# Exporting Create HDL core command for module apb3_if -create_hdl_core -file {hdl/apb_wrapper.vhd} -module {apb3_if} -library {work} -package {} -# Exporting BIF information of HDL core command for module apb3_if -hdl_core_add_bif -hdl_core_name {apb3_if} -bif_definition {APB:AMBA:AMBA2:slave} -bif_name {APB_slave} -signal_map {\ -"PADDR:paddr_i" \ -"PSELx:psel_i" \ -"PENABLE:penable_i" \ -"PWRITE:pwrite_i" \ -"PRDATA:prdata_o" \ -"PWDATA:pwdata_i" \ -"PREADY:pready_o" \ -"PSLVERR:pslverr_o" } +# Exporting core apb3_if to TCL +# Exporting Create HDL core command for module apb3_if +create_hdl_core -file {hdl/apb_wrapper.vhd} -module {apb3_if} -library {work} -package {} +# Exporting BIF information of HDL core command for module apb3_if +hdl_core_add_bif -hdl_core_name {apb3_if} -bif_definition {APB:AMBA:AMBA2:slave} -bif_name {APB_slave} -signal_map {\ +"PADDR:paddr_i" \ +"PSELx:psel_i" \ +"PENABLE:penable_i" \ +"PWRITE:pwrite_i" \ +"PRDATA:prdata_o" \ +"PWDATA:pwdata_i" \ +"PREADY:pready_o" \ +"PSLVERR:pslverr_o" } diff --git a/script_support/components/mipicsi2rxdecoderPF_C0.tcl b/script_support/components/mipicsi2rxdecoderPF_C0.tcl index 2d0d9af..98f843d 100644 --- a/script_support/components/mipicsi2rxdecoderPF_C0.tcl +++ b/script_support/components/mipicsi2rxdecoderPF_C0.tcl @@ -1,12 +1,12 @@ -# Exporting Component Description of mipicsi2rxdecoderPF_C0 to TCL -# Family: PolarFireSoC -# Part Number: MPFS250T_ES-1FCG1152E -# Create and Configure the core component mipicsi2rxdecoderPF_C0 -create_and_configure_core -core_vlnv {Microsemi:SolutionCore:mipicsi2rxdecoderPF:4.4.0} -component_name {mipicsi2rxdecoderPF_C0} -params {\ -"g_DATAWIDTH:10" \ -"g_FIFO_SIZE:12" \ -"g_FORMAT:0" \ -"g_INPUT_DATA_INVERT:0" \ -"g_LANE_WIDTH:4" \ -"g_NUM_OF_PIXELS:1" } -# Exporting Component Description of mipicsi2rxdecoderPF_C0 to TCL done +# Exporting Component Description of mipicsi2rxdecoderPF_C0 to TCL +# Family: PolarFireSoC +# Part Number: MPFS250T_ES-1FCG1152E +# Create and Configure the core component mipicsi2rxdecoderPF_C0 +create_and_configure_core -core_vlnv {Microchip:SolutionCore:mipicsi2rxdecoderPF:4.7.0} -component_name {mipicsi2rxdecoderPF_C0} -params {\ +"g_DATAWIDTH:10" \ +"g_FIFO_SIZE:12" \ +"g_FORMAT:0" \ +"g_INPUT_DATA_INVERT:0" \ +"g_LANE_WIDTH:4" \ +"g_NUM_OF_PIXELS:1" } +# Exporting Component Description of mipicsi2rxdecoderPF_C0 to TCL done diff --git a/script_support/components/video_fifo.tcl b/script_support/components/video_fifo.tcl index 595bc61..78de8fe 100644 --- a/script_support/components/video_fifo.tcl +++ b/script_support/components/video_fifo.tcl @@ -1,4 +1,4 @@ -# Exporting core video_fifo to TCL -# Exporting Create HDL core command for module video_fifo -create_hdl_core -file {hdl/video_fifo.vhd} -module {video_fifo} -library {work} -package {} -# Exporting BIF information of HDL core command for module video_fifo +# Exporting core video_fifo to TCL +# Exporting Create HDL core command for module video_fifo +create_hdl_core -file {hdl/video_fifo.vhd} -module {video_fifo} -library {work} -package {} +# Exporting BIF information of HDL core command for module video_fifo diff --git a/script_support/components/video_processing.tcl b/script_support/components/video_processing.tcl index 689262b..db2f3fd 100644 --- a/script_support/components/video_processing.tcl +++ b/script_support/components/video_processing.tcl @@ -1,137 +1,151 @@ -# Creating SmartDesign video_processing -set sd_name {video_processing} -create_smartdesign -sd_name ${sd_name} - -# Disable auto promotion of pins of type 'pad' -auto_promote_pad_pins -promote_all 0 - -# Create top level Scalar Ports -sd_create_scalar_port -sd_name ${sd_name} -port_name {DATA_VALID_I} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {RESETN_I} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {SYS_CLK_I} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {encoder_en_i} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {frame_start_i} -port_direction {IN} - -sd_create_scalar_port -sd_name ${sd_name} -port_name {DATA_VALID_O} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {encoder_en_o} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {eof_encoder_o} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {frame_start_encoder_o} -port_direction {OUT} - - -# Create top level Bus Ports -sd_create_bus_port -sd_name ${sd_name} -port_name {B_CONST_I} -port_direction {IN} -port_range {[9:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {COMMON_CONST_I} -port_direction {IN} -port_range {[19:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {DATA_I} -port_direction {IN} -port_range {[7:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {G_CONST_I} -port_direction {IN} -port_range {[9:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {R_CONST_I} -port_direction {IN} -port_range {[9:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {hres_i} -port_direction {IN} -port_range {[15:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {vres_i} -port_direction {IN} -port_range {[15:0]} - -sd_create_bus_port -sd_name ${sd_name} -port_name {DATA_B_O} -port_direction {OUT} -port_range {[7:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {DATA_G_O} -port_direction {OUT} -port_range {[7:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {DATA_R_O} -port_direction {OUT} -port_range {[7:0]} -sd_create_bus_port -sd_name ${sd_name} -port_name {y_o} -port_direction {OUT} -port_range {[31:0]} - - -sd_create_pin_slices -sd_name ${sd_name} -pin_name {hres_i} -pin_slices {[12:0]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {vres_i} -pin_slices {[12:0]} -# Add AND2_0 instance -sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0} -sd_invert_pins -sd_name ${sd_name} -pin_names {AND2_0:B} - - - -# Add Bayer_Interpolation_C0_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {Bayer_Interpolation_C0} -instance_name {Bayer_Interpolation_C0_0} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Bayer_Interpolation_C0_0:BAYER_FORMAT} -value {10} - - - -# Add frame_controls_gen_0 instance -sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {frame_controls_gen} -hdl_file {hdl\frame_controls_gen.v} -instance_name {frame_controls_gen_0} - - - -# Add Gamma_Correction_C0_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {Gamma_Correction_C0} -instance_name {Gamma_Correction_C0_0} - - - -# Add Image_Enhancement_C0_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {Image_Enhancement_C0} -instance_name {Image_Enhancement_C0_0} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {Image_Enhancement_C0_0:DATA_I} -pin_slices {[15:8]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {Image_Enhancement_C0_0:DATA_I} -pin_slices {[23:16]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {Image_Enhancement_C0_0:DATA_I} -pin_slices {[7:0]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {Image_Enhancement_C0_0:DATA_O} -pin_slices {[15:8]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {Image_Enhancement_C0_0:DATA_O} -pin_slices {[23:16]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {Image_Enhancement_C0_0:DATA_O} -pin_slices {[7:0]} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Image_Enhancement_C0_0:ENABLE_I} -value {VCC} - - - -# Add IMAGE_SCALER_C0_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {IMAGE_SCALER_C0} -instance_name {IMAGE_SCALER_C0_0} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {IMAGE_SCALER_C0_0:HORZ_RES_IN_I} -value {0011110000000} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {IMAGE_SCALER_C0_0:VERT_RES_IN_I} -value {0010000111000} - - - -# Add intensity_average_0 instance -sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {intensity_average} -hdl_file {hdl\intensity_average.vhd} -instance_name {intensity_average_0} - - - -# Add scalar net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "Bayer_Interpolation_C0_0:RESETN_I" "Gamma_Correction_C0_0:RESETN_I" "Image_Enhancement_C0_0:RESETN_I" "RESETN_I" "frame_controls_gen_0:resetn_i" "intensity_average_0:RESETN_I" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "frame_controls_gen_0:frame_start_r1_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "IMAGE_SCALER_C0_0:RESETN_I" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C0_0:DATA_VALID_I" "DATA_VALID_I" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C0_0:EOF_I" "frame_controls_gen_0:frame_start_i" "frame_start_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C0_0:EOF_O" "intensity_average_0:frame_end_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C0_0:RGB_VALID_O" "Gamma_Correction_C0_0:DATA_VALID_I" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C0_0:SYS_CLK_I" "Gamma_Correction_C0_0:SYS_CLK_I" "IMAGE_SCALER_C0_0:IP_CLK_I" "IMAGE_SCALER_C0_0:SYS_CLK_I" "Image_Enhancement_C0_0:SYS_CLK_I" "SYS_CLK_I" "frame_controls_gen_0:sys_clk_i" "intensity_average_0:SYS_CLK_I" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"DATA_VALID_O" "frame_controls_gen_0:data_valid_r1_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C0_0:DATA_VALID_O" "Image_Enhancement_C0_0:DATA_VALID_I" "intensity_average_0:data_valid_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"IMAGE_SCALER_C0_0:DATA_VALID_I" "Image_Enhancement_C0_0:DATA_VALID_O" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"IMAGE_SCALER_C0_0:DATA_VALID_O" "frame_controls_gen_0:data_valid_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"encoder_en_i" "frame_controls_gen_0:encoder_en_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"encoder_en_o" "frame_controls_gen_0:encoder_en_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"eof_encoder_o" "frame_controls_gen_0:eof_encoder_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"frame_controls_gen_0:frame_start_encoder_o" "frame_start_encoder_o" } - -# Add bus net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"B_CONST_I" "Image_Enhancement_C0_0:B_CONST_I" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C0_0:B_O" "Gamma_Correction_C0_0:BLUE_I" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C0_0:DATA_I" "DATA_I" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C0_0:G_O" "Gamma_Correction_C0_0:GREEN_I" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C0_0:R_O" "Gamma_Correction_C0_0:RED_I" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"COMMON_CONST_I" "Image_Enhancement_C0_0:COMMON_CONST_I" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"DATA_B_O" "frame_controls_gen_0:data_b_r1_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"DATA_G_O" "frame_controls_gen_0:data_g_r1_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"DATA_R_O" "frame_controls_gen_0:data_r_r1_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"G_CONST_I" "Image_Enhancement_C0_0:G_CONST_I" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C0_0:BLUE_O" "Image_Enhancement_C0_0:DATA_I[7:0]" "intensity_average_0:b_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C0_0:GREEN_O" "Image_Enhancement_C0_0:DATA_I[15:8]" "intensity_average_0:g_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C0_0:RED_O" "Image_Enhancement_C0_0:DATA_I[23:16]" "intensity_average_0:r_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"IMAGE_SCALER_C0_0:DATA_B_I" "Image_Enhancement_C0_0:DATA_O[7:0]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"IMAGE_SCALER_C0_0:DATA_B_O" "frame_controls_gen_0:data_b_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"IMAGE_SCALER_C0_0:DATA_G_I" "Image_Enhancement_C0_0:DATA_O[15:8]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"IMAGE_SCALER_C0_0:DATA_G_O" "frame_controls_gen_0:data_g_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"IMAGE_SCALER_C0_0:DATA_R_I" "Image_Enhancement_C0_0:DATA_O[23:16]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"IMAGE_SCALER_C0_0:DATA_R_O" "frame_controls_gen_0:data_r_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"IMAGE_SCALER_C0_0:HORZ_RES_OUT_I" "hres_i[12:0]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"IMAGE_SCALER_C0_0:SCALE_FACTOR_HORZ_I" "frame_controls_gen_0:h_scale_factor_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"IMAGE_SCALER_C0_0:SCALE_FACTOR_VERT_I" "frame_controls_gen_0:v_scale_factor_o" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"IMAGE_SCALER_C0_0:VERT_RES_OUT_I" "vres_i[12:0]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"Image_Enhancement_C0_0:R_CONST_I" "R_CONST_I" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"frame_controls_gen_0:hres_i" "hres_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"frame_controls_gen_0:vres_i" "vres_i" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"intensity_average_0:y_o" "y_o" } - - -# Re-enable auto promotion of pins of type 'pad' -auto_promote_pad_pins -promote_all 1 -# Save the smartDesign -save_smartdesign -sd_name ${sd_name} -# Generate SmartDesign video_processing -generate_component -component_name ${sd_name} +# Creating SmartDesign video_processing +set sd_name {video_processing} +create_smartdesign -sd_name ${sd_name} + +# Disable auto promotion of pins of type 'pad' +auto_promote_pad_pins -promote_all 0 + +# Create top level Scalar Ports +sd_create_scalar_port -sd_name ${sd_name} -port_name {DATA_VALID_I} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {RESETN_I} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {SYS_CLK_I} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {encoder_en_i} -port_direction {IN} +sd_create_scalar_port -sd_name ${sd_name} -port_name {frame_start_i} -port_direction {IN} + +sd_create_scalar_port -sd_name ${sd_name} -port_name {DATA_VALID_O} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {encoder_en_o} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {eof_encoder_o} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sd_name} -port_name {frame_start_encoder_o} -port_direction {OUT} + + +# Create top level Bus Ports +sd_create_bus_port -sd_name ${sd_name} -port_name {B_CONST_I} -port_direction {IN} -port_range {[9:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {COMMON_CONST_I} -port_direction {IN} -port_range {[19:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {DATA_I} -port_direction {IN} -port_range {[7:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {G_CONST_I} -port_direction {IN} -port_range {[9:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {R_CONST_I} -port_direction {IN} -port_range {[9:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {coordinate_i} -port_direction {IN} -port_range {[31:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {digits_i} -port_direction {IN} -port_range {[11:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {hres_i} -port_direction {IN} -port_range {[15:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {text_color_rgb_i} -port_direction {IN} -port_range {[23:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {vres_i} -port_direction {IN} -port_range {[15:0]} + +sd_create_bus_port -sd_name ${sd_name} -port_name {DATA_B_O} -port_direction {OUT} -port_range {[7:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {DATA_G_O} -port_direction {OUT} -port_range {[7:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {DATA_R_O} -port_direction {OUT} -port_range {[7:0]} +sd_create_bus_port -sd_name ${sd_name} -port_name {y_o} -port_direction {OUT} -port_range {[31:0]} + + +sd_create_pin_slices -sd_name ${sd_name} -pin_name {hres_i} -pin_slices {[12:0]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {vres_i} -pin_slices {[12:0]} +# Add AND2_0 instance +sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0} +sd_invert_pins -sd_name ${sd_name} -pin_names {AND2_0:B} + + + +# Add Bayer_Interpolation_C0_0 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {Bayer_Interpolation_C0} -instance_name {Bayer_Interpolation_C0_0} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Bayer_Interpolation_C0_0:BAYER_FORMAT} -value {00} + + + +# Add CR_OSD_0 instance +sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {CR_OSD} -hdl_file {hdl\CR_OSD.v} -instance_name {CR_OSD_0} + + + +# Add frame_controls_gen_0 instance +sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {frame_controls_gen} -hdl_file {hdl\frame_controls_gen.v} -instance_name {frame_controls_gen_0} + + + +# Add Gamma_Correction_C0_0 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {Gamma_Correction_C0} -instance_name {Gamma_Correction_C0_0} + + + +# Add Image_Enhancement_C0_0 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {Image_Enhancement_C0} -instance_name {Image_Enhancement_C0_0} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {Image_Enhancement_C0_0:DATA_I} -pin_slices {[15:8]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {Image_Enhancement_C0_0:DATA_I} -pin_slices {[23:16]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {Image_Enhancement_C0_0:DATA_I} -pin_slices {[7:0]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {Image_Enhancement_C0_0:DATA_O} -pin_slices {[15:8]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {Image_Enhancement_C0_0:DATA_O} -pin_slices {[23:16]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {Image_Enhancement_C0_0:DATA_O} -pin_slices {[7:0]} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Image_Enhancement_C0_0:ENABLE_I} -value {VCC} + + + +# Add IMAGE_SCALER_C0_0 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {IMAGE_SCALER_C0} -instance_name {IMAGE_SCALER_C0_0} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {IMAGE_SCALER_C0_0:HORZ_RES_IN_I} -value {0011110000000} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {IMAGE_SCALER_C0_0:VERT_RES_IN_I} -value {0010000111000} + + + +# Add intensity_average_0 instance +sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {intensity_average} -hdl_file {hdl\intensity_average.vhd} -instance_name {intensity_average_0} + + + +# Add scalar net connections +sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "Bayer_Interpolation_C0_0:RESETN_I" "CR_OSD_0:RESETN_I" "Gamma_Correction_C0_0:RESETN_I" "Image_Enhancement_C0_0:RESETN_I" "RESETN_I" "frame_controls_gen_0:resetn_i" "intensity_average_0:RESETN_I" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "frame_controls_gen_0:frame_start_r1_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "IMAGE_SCALER_C0_0:RESETN_I" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C0_0:DATA_VALID_I" "DATA_VALID_I" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C0_0:EOF_I" "frame_controls_gen_0:frame_start_i" "frame_start_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C0_0:EOF_O" "intensity_average_0:frame_end_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C0_0:RGB_VALID_O" "Gamma_Correction_C0_0:DATA_VALID_I" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C0_0:SYS_CLK_I" "CR_OSD_0:SYS_CLK_I" "Gamma_Correction_C0_0:SYS_CLK_I" "IMAGE_SCALER_C0_0:IP_CLK_I" "IMAGE_SCALER_C0_0:SYS_CLK_I" "Image_Enhancement_C0_0:SYS_CLK_I" "SYS_CLK_I" "frame_controls_gen_0:sys_clk_i" "intensity_average_0:SYS_CLK_I" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CR_OSD_0:DATA_ENABLE_I" "DATA_VALID_O" "frame_controls_gen_0:data_valid_r1_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CR_OSD_0:FRAME_END_I" "eof_encoder_o" "frame_controls_gen_0:eof_encoder_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C0_0:DATA_VALID_O" "Image_Enhancement_C0_0:DATA_VALID_I" "intensity_average_0:data_valid_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"IMAGE_SCALER_C0_0:DATA_VALID_I" "Image_Enhancement_C0_0:DATA_VALID_O" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"IMAGE_SCALER_C0_0:DATA_VALID_O" "frame_controls_gen_0:data_valid_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"encoder_en_i" "frame_controls_gen_0:encoder_en_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"encoder_en_o" "frame_controls_gen_0:encoder_en_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"frame_controls_gen_0:frame_start_encoder_o" "frame_start_encoder_o" } + +# Add bus net connections +sd_connect_pins -sd_name ${sd_name} -pin_names {"B_CONST_I" "Image_Enhancement_C0_0:B_CONST_I" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C0_0:B_O" "Gamma_Correction_C0_0:BLUE_I" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C0_0:DATA_I" "DATA_I" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C0_0:G_O" "Gamma_Correction_C0_0:GREEN_I" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C0_0:R_O" "Gamma_Correction_C0_0:RED_I" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CR_OSD_0:b_i" "frame_controls_gen_0:data_b_r1_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CR_OSD_0:b_o" "DATA_B_O" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CR_OSD_0:coordinate_i" "coordinate_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CR_OSD_0:g_i" "frame_controls_gen_0:data_g_r1_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CR_OSD_0:g_o" "DATA_G_O" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CR_OSD_0:num_i" "digits_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CR_OSD_0:r_i" "frame_controls_gen_0:data_r_r1_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CR_OSD_0:r_o" "DATA_R_O" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CR_OSD_0:text_color_rgb_i" "text_color_rgb_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"COMMON_CONST_I" "Image_Enhancement_C0_0:COMMON_CONST_I" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"G_CONST_I" "Image_Enhancement_C0_0:G_CONST_I" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C0_0:BLUE_O" "Image_Enhancement_C0_0:DATA_I[7:0]" "intensity_average_0:b_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C0_0:GREEN_O" "Image_Enhancement_C0_0:DATA_I[15:8]" "intensity_average_0:g_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C0_0:RED_O" "Image_Enhancement_C0_0:DATA_I[23:16]" "intensity_average_0:r_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"IMAGE_SCALER_C0_0:DATA_B_I" "Image_Enhancement_C0_0:DATA_O[7:0]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"IMAGE_SCALER_C0_0:DATA_B_O" "frame_controls_gen_0:data_b_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"IMAGE_SCALER_C0_0:DATA_G_I" "Image_Enhancement_C0_0:DATA_O[15:8]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"IMAGE_SCALER_C0_0:DATA_G_O" "frame_controls_gen_0:data_g_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"IMAGE_SCALER_C0_0:DATA_R_I" "Image_Enhancement_C0_0:DATA_O[23:16]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"IMAGE_SCALER_C0_0:DATA_R_O" "frame_controls_gen_0:data_r_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"IMAGE_SCALER_C0_0:HORZ_RES_OUT_I" "hres_i[12:0]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"IMAGE_SCALER_C0_0:SCALE_FACTOR_HORZ_I" "frame_controls_gen_0:h_scale_factor_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"IMAGE_SCALER_C0_0:SCALE_FACTOR_VERT_I" "frame_controls_gen_0:v_scale_factor_o" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"IMAGE_SCALER_C0_0:VERT_RES_OUT_I" "vres_i[12:0]" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"Image_Enhancement_C0_0:R_CONST_I" "R_CONST_I" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"frame_controls_gen_0:hres_i" "hres_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"frame_controls_gen_0:vres_i" "vres_i" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"intensity_average_0:y_o" "y_o" } + + +# Re-enable auto promotion of pins of type 'pad' +auto_promote_pad_pins -promote_all 1 +# Save the smartDesign +save_smartdesign -sd_name ${sd_name} +# Generate SmartDesign video_processing +generate_component -component_name ${sd_name} diff --git a/script_support/constraint/fp/user.pdc b/script_support/constraint/fp/user.pdc index c227292..2bb18e9 100644 --- a/script_support/constraint/fp/user.pdc +++ b/script_support/constraint/fp/user.pdc @@ -1,14 +1,8 @@ # Microsemi Physical design constraints file -# Version: 2022.1 2022.1.0.10 +# Design Name: VKPFSOC_H264 -# Design Name: SEVPFSOC_H264 - -# Input Netlist Format: EDIF - -# Family: PolarFireSoC , Die: MPFS250T_ES , Package: FCG1152 , Speed grade: -1 - -# Date generated: Mon May 30 18:07:59 2022 +# Family: PolarFireSoC , Die: MPFS250TS , Package: FCG1152 , Speed grade: -1 # diff --git a/script_support/constraint/io/SEV_MAC.pdc b/script_support/constraint/io/VIDEO_KIT_MAC.pdc similarity index 91% rename from script_support/constraint/io/SEV_MAC.pdc rename to script_support/constraint/io/VIDEO_KIT_MAC.pdc index 15bcea9..fd0cb60 100644 --- a/script_support/constraint/io/SEV_MAC.pdc +++ b/script_support/constraint/io/VIDEO_KIT_MAC.pdc @@ -1,98 +1,90 @@ -# Microsemi I/O Physical Design Constraints file - -# User I/O Constraints file - -# Version: v12.6 12.900.20.24 - -# Family: PolarFireSoC , Die: MPFS250T_ES , Package: FCG1152 - -# Date generated: Fri Jan 22 15:09:18 2021 - - -# -# User Locked I/O Bank Settings -# - - -# -# Unlocked I/O Bank Settings -# The I/O Bank Settings can be locked by directly editing this file -# or by making changes in the I/O Attribute Editor -# - -set_iobank -bank_name Bank1 \ - -vcci 3.30 \ - -fixed false \ - -update_iostd true - - -# -# User Locked I/O settings -# - -set_io -port_name VSC_8662_CMODE3 \ - -pin_name H12 \ - -fixed true \ - -io_std LVCMOS33 \ - -DIRECTION OUTPUT - - -set_io -port_name VSC_8662_CMODE4 \ - -pin_name G12 \ - -fixed true \ - -io_std LVCMOS33 \ - -DIRECTION OUTPUT - - -set_io -port_name VSC_8662_CMODE5 \ - -pin_name F12 \ - -fixed true \ - -io_std LVCMOS33 \ - -DIRECTION OUTPUT - - -set_io -port_name VSC_8662_CMODE6 \ - -pin_name E12 \ - -fixed true \ - -io_std LVCMOS33 \ - -DIRECTION OUTPUT - - -set_io -port_name VSC_8662_CMODE7 \ - -pin_name G14 \ - -fixed true \ - -io_std LVCMOS33 \ - -DIRECTION OUTPUT - - -set_io -port_name VSC_8662_RESETN \ - -pin_name A8 \ - -fixed true \ - -io_std LVCMOS33 \ - -DIRECTION OUTPUT - - -set_io -port_name VSC_8662_SRESET \ - -pin_name A7 \ - -fixed true \ - -io_std LVCMOS33 \ - -DIRECTION OUTPUT - - - -# -# Dedicated Peripheral I/O Settings -# - - -# -# Unlocked I/O settings -# The I/Os in this section are unplaced or placed but are not locked -# the other listed attributes have been applied -# - -# -#Ports using Dedicated Pins - -# - +# Microsemi I/O Physical Design Constraints file + +# Family: PolarFireSoC , Die: MPFS250TS , Package: FCG1152 +# +# User Locked I/O Bank Settings +# + + +# +# Unlocked I/O Bank Settings +# The I/O Bank Settings can be locked by directly editing this file +# or by making changes in the I/O Attribute Editor +# + +set_iobank -bank_name Bank1 \ + -vcci 3.30 \ + -fixed false \ + -update_iostd true + + +# +# User Locked I/O settings +# + +set_io -port_name VSC_8662_CMODE3 \ + -pin_name H12 \ + -fixed true \ + -io_std LVCMOS33 \ + -DIRECTION OUTPUT + + +set_io -port_name VSC_8662_CMODE4 \ + -pin_name G12 \ + -fixed true \ + -io_std LVCMOS33 \ + -DIRECTION OUTPUT + + +set_io -port_name VSC_8662_CMODE5 \ + -pin_name F12 \ + -fixed true \ + -io_std LVCMOS33 \ + -DIRECTION OUTPUT + + +set_io -port_name VSC_8662_CMODE6 \ + -pin_name E12 \ + -fixed true \ + -io_std LVCMOS33 \ + -DIRECTION OUTPUT + + +set_io -port_name VSC_8662_CMODE7 \ + -pin_name G14 \ + -fixed true \ + -io_std LVCMOS33 \ + -DIRECTION OUTPUT + + +set_io -port_name VSC_8662_RESETN \ + -pin_name A8 \ + -fixed true \ + -io_std LVCMOS33 \ + -DIRECTION OUTPUT + + +set_io -port_name VSC_8662_SRESET \ + -pin_name A7 \ + -fixed true \ + -io_std LVCMOS33 \ + -DIRECTION OUTPUT + + + +# +# Dedicated Peripheral I/O Settings +# + + +# +# Unlocked I/O settings +# The I/Os in this section are unplaced or placed but are not locked +# the other listed attributes have been applied +# + +# +#Ports using Dedicated Pins + +# + diff --git a/script_support/constraint/io/SEV_MMUART0.pdc b/script_support/constraint/io/VIDEO_KIT_MMUART0.pdc similarity index 87% rename from script_support/constraint/io/SEV_MMUART0.pdc rename to script_support/constraint/io/VIDEO_KIT_MMUART0.pdc index 1bae69b..33f7736 100644 --- a/script_support/constraint/io/SEV_MMUART0.pdc +++ b/script_support/constraint/io/VIDEO_KIT_MMUART0.pdc @@ -1,64 +1,58 @@ -# Microsemi I/O Physical Design Constraints file - -# User I/O Constraints file - -# Version: v12.6 12.900.20.24 - -# Family: PolarFireSoC , Die: MPFS250T_ES , Package: FCG1152 - -# Date generated: Fri Jan 22 14:55:44 2021 - - -# -# User Locked I/O Bank Settings -# - - -# -# Unlocked I/O Bank Settings -# The I/O Bank Settings can be locked by directly editing this file -# or by making changes in the I/O Attribute Editor -# - -set_iobank -bank_name Bank1 \ - -vcci 3.30 \ - -fixed false \ - -update_iostd true - - -# -# User Locked I/O settings -# - -set_io -port_name MMUART_0_RXD_F2M \ - -pin_name C7 \ - -fixed true \ - -io_std LVCMOS33 \ - -DIRECTION INPUT - - -set_io -port_name MMUART_0_TXD_M2F \ - -pin_name B7 \ - -fixed true \ - -io_std LVCMOS33 \ - -DIRECTION OUTPUT - - - -# -# Dedicated Peripheral I/O Settings -# - - -# -# Unlocked I/O settings -# The I/Os in this section are unplaced or placed but are not locked -# the other listed attributes have been applied -# - - -# -#Ports using Dedicated Pins - -# - +# Microsemi I/O Physical Design Constraints file + +# User I/O Constraints file + +# Family: PolarFireSoC , Die: MPFS250TS , Package: FCG1152 +# +# User Locked I/O Bank Settings +# + + +# +# Unlocked I/O Bank Settings +# The I/O Bank Settings can be locked by directly editing this file +# or by making changes in the I/O Attribute Editor +# + +set_iobank -bank_name Bank1 \ + -vcci 3.30 \ + -fixed false \ + -update_iostd true + + +# +# User Locked I/O settings +# + +set_io -port_name MMUART_0_RXD_F2M \ + -pin_name C7 \ + -fixed true \ + -io_std LVCMOS33 \ + -DIRECTION INPUT + + +set_io -port_name MMUART_0_TXD_M2F \ + -pin_name B7 \ + -fixed true \ + -io_std LVCMOS33 \ + -DIRECTION OUTPUT + + + +# +# Dedicated Peripheral I/O Settings +# + + +# +# Unlocked I/O settings +# The I/Os in this section are unplaced or placed but are not locked +# the other listed attributes have been applied +# + + +# +#Ports using Dedicated Pins + +# + diff --git a/script_support/constraint/io/SEV_MMUART1.pdc b/script_support/constraint/io/VIDEO_KIT_MMUART1.pdc similarity index 87% rename from script_support/constraint/io/SEV_MMUART1.pdc rename to script_support/constraint/io/VIDEO_KIT_MMUART1.pdc index 2c25d88..69a302f 100644 --- a/script_support/constraint/io/SEV_MMUART1.pdc +++ b/script_support/constraint/io/VIDEO_KIT_MMUART1.pdc @@ -1,64 +1,58 @@ -# Microsemi I/O Physical Design Constraints file - -# User I/O Constraints file - -# Version: v12.6 12.900.20.24 - -# Family: PolarFireSoC , Die: MPFS250T_ES , Package: FCG1152 - -# Date generated: Wed Feb 10 17:01:23 2021 - - -# -# User Locked I/O Bank Settings -# - - -# -# Unlocked I/O Bank Settings -# The I/O Bank Settings can be locked by directly editing this file -# or by making changes in the I/O Attribute Editor -# - -set_iobank -bank_name Bank1 \ - -vcci 3.30 \ - -fixed false \ - -update_iostd true - - -# -# User Locked I/O settings -# - -set_io -port_name MMUART_1_RXD_F2M \ - -pin_name D4 \ - -fixed true \ - -io_std LVCMOS33 \ - -DIRECTION INPUT - - -set_io -port_name MMUART_1_TXD_M2F \ - -pin_name C4 \ - -fixed true \ - -io_std LVCMOS33 \ - -DIRECTION OUTPUT - - - -# -# Dedicated Peripheral I/O Settings -# - - -# -# Unlocked I/O settings -# The I/Os in this section are unplaced or placed but are not locked -# the other listed attributes have been applied -# - - -# -#Ports using Dedicated Pins - -# - +# Microsemi I/O Physical Design Constraints file + +# User I/O Constraints file + +# Family: PolarFireSoC , Die: MPFS250TS , Package: FCG1152 +# +# User Locked I/O Bank Settings +# + + +# +# Unlocked I/O Bank Settings +# The I/O Bank Settings can be locked by directly editing this file +# or by making changes in the I/O Attribute Editor +# + +set_iobank -bank_name Bank1 \ + -vcci 3.30 \ + -fixed false \ + -update_iostd true + + +# +# User Locked I/O settings +# + +set_io -port_name MMUART_1_RXD_F2M \ + -pin_name D4 \ + -fixed true \ + -io_std LVCMOS33 \ + -DIRECTION INPUT + + +set_io -port_name MMUART_1_TXD_M2F \ + -pin_name C4 \ + -fixed true \ + -io_std LVCMOS33 \ + -DIRECTION OUTPUT + + + +# +# Dedicated Peripheral I/O Settings +# + + +# +# Unlocked I/O settings +# The I/Os in this section are unplaced or placed but are not locked +# the other listed attributes have been applied +# + + +# +#Ports using Dedicated Pins + +# + diff --git a/script_support/constraint/io/user.pdc b/script_support/constraint/io/user.pdc index ec47fbd..61cdc4c 100644 --- a/script_support/constraint/io/user.pdc +++ b/script_support/constraint/io/user.pdc @@ -1,194 +1,187 @@ -# Microsemi I/O Physical Design Constraints file - -# User I/O Constraints file - -# Version: 2022.1 2022.1.0.10 - -# Family: PolarFireSoC , Die: MPFS250T_ES , Package: FCG1152 - -# Date generated: Mon May 30 18:07:58 2022 - - -# -# User Locked I/O Bank Settings -# - - -# -# Unlocked I/O Bank Settings -# The I/O Bank Settings can be locked by directly editing this file -# or by making changes in the I/O Attribute Editor -# - -set_iobank -bank_name Bank0 \ - -vcci 1.20 \ - -vref 0.60 \ - -fixed false \ - -update_iostd true - - -# -# User Locked I/O settings -# - -set_io -port_name CAM1_RST \ - -pin_name K3 \ - -fixed true \ - -io_std LVCMOS25 \ - -DIRECTION OUTPUT - - -set_io -port_name {CAM1_RXD[0]} \ - -pin_name L12 \ - -fixed true \ - -io_std MIPI25 \ - -DIRECTION INPUT - - -set_io -port_name {CAM1_RXD[1]} \ - -pin_name L10 \ - -fixed true \ - -io_std MIPI25 \ - -DIRECTION INPUT - - -set_io -port_name {CAM1_RXD[2]} \ - -pin_name M11 \ - -fixed true \ - -io_std MIPI25 \ - -DIRECTION INPUT - - -set_io -port_name {CAM1_RXD[3]} \ - -pin_name N13 \ - -fixed true \ - -io_std MIPI25 \ - -DIRECTION INPUT - - -set_io -port_name {CAM1_RXD_N[0]} \ - -pin_name M12 \ - -fixed true \ - -io_std MIPI25 \ - -DIRECTION INPUT - - -set_io -port_name {CAM1_RXD_N[1]} \ - -pin_name K10 \ - -fixed true \ - -io_std MIPI25 \ - -DIRECTION INPUT - - -set_io -port_name {CAM1_RXD_N[2]} \ - -pin_name N11 \ - -fixed true \ - -io_std MIPI25 \ - -DIRECTION INPUT - - -set_io -port_name {CAM1_RXD_N[3]} \ - -pin_name N12 \ - -fixed true \ - -io_std MIPI25 \ - -DIRECTION INPUT - - -set_io -port_name CAM1_RX_CLK_N \ - -pin_name N14 \ - -fixed true \ - -io_std MIPI25 \ - -DIRECTION INPUT - - -set_io -port_name CAM1_RX_CLK_P \ - -pin_name M14 \ - -fixed true \ - -io_std MIPI25 \ - -DIRECTION INPUT - - -set_io -port_name CAM1_SCL \ - -pin_name K7 \ - -fixed true \ - -io_std LVCMOS25 \ - -DIRECTION INOUT - - -set_io -port_name CAM1_SDA \ - -pin_name J8 \ - -fixed true \ - -io_std LVCMOS25 \ - -DIRECTION INOUT - - -set_io -port_name CAM_CLK_EN \ - -pin_name K5 \ - -fixed true \ - -io_std LVCMOS25 \ - -DIRECTION OUTPUT - - -set_io -port_name LED2 \ - -pin_name AP28 \ - -fixed true \ - -io_std LVCMOS12 \ - -DIRECTION OUTPUT - - -set_io -port_name LED3 \ - -pin_name AP29 \ - -fixed true \ - -io_std LVCMOS12 \ - -DIRECTION OUTPUT - - -set_io -port_name TEN \ - -pin_name AM5 \ - -fixed true \ - -io_std HSTL12I \ - -DIRECTION OUTPUT - - -set_io -port_name cam1inck \ - -pin_name J5 \ - -fixed true \ - -io_std LVCMOS25 \ - -DIRECTION OUTPUT - - -set_io -port_name cam1xmaster \ - -pin_name J4 \ - -fixed true \ - -io_std LVCMOS25 \ - -DIRECTION OUTPUT - - - -# -# Dedicated Peripheral I/O Settings -# - - -# -# Unlocked I/O settings -# The I/Os in this section are unplaced or placed but are not locked -# the other listed attributes have been applied -# - - -# -#Ports using Dedicated Pins - -# - -set_io -port_name REF_CLK_PAD_N \ - -pin_name AF30 \ - -DIRECTION INPUT - - -set_io -port_name REF_CLK_PAD_P \ - -pin_name AF29 \ - -DIRECTION INPUT - - +# Microsemi I/O Physical Design Constraints file + +# User I/O Constraints file +# Family: PolarFireSoC , Die: MPFS250TS , Package: FCG1152 +# +# User Locked I/O Bank Settings +# + + +# +# Unlocked I/O Bank Settings +# The I/O Bank Settings can be locked by directly editing this file +# or by making changes in the I/O Attribute Editor +# + +set_iobank -bank_name Bank0 \ + -vcci 1.20 \ + -vref 0.60 \ + -fixed false \ + -update_iostd true + + +# +# User Locked I/O settings +# + +set_io -port_name CAM1_RST \ + -pin_name K3 \ + -fixed true \ + -io_std LVCMOS25 \ + -DIRECTION OUTPUT + + +set_io -port_name {CAM1_RXD[0]} \ + -pin_name L12 \ + -fixed true \ + -io_std MIPI25 \ + -DIRECTION INPUT + + +set_io -port_name {CAM1_RXD[1]} \ + -pin_name L10 \ + -fixed true \ + -io_std MIPI25 \ + -DIRECTION INPUT + + +set_io -port_name {CAM1_RXD[2]} \ + -pin_name M11 \ + -fixed true \ + -io_std MIPI25 \ + -DIRECTION INPUT + + +set_io -port_name {CAM1_RXD[3]} \ + -pin_name N13 \ + -fixed true \ + -io_std MIPI25 \ + -DIRECTION INPUT + + +set_io -port_name {CAM1_RXD_N[0]} \ + -pin_name M12 \ + -fixed true \ + -io_std MIPI25 \ + -DIRECTION INPUT + + +set_io -port_name {CAM1_RXD_N[1]} \ + -pin_name K10 \ + -fixed true \ + -io_std MIPI25 \ + -DIRECTION INPUT + + +set_io -port_name {CAM1_RXD_N[2]} \ + -pin_name N11 \ + -fixed true \ + -io_std MIPI25 \ + -DIRECTION INPUT + + +set_io -port_name {CAM1_RXD_N[3]} \ + -pin_name N12 \ + -fixed true \ + -io_std MIPI25 \ + -DIRECTION INPUT + + +set_io -port_name CAM1_RX_CLK_N \ + -pin_name N14 \ + -fixed true \ + -io_std MIPI25 \ + -DIRECTION INPUT + + +set_io -port_name CAM1_RX_CLK_P \ + -pin_name M14 \ + -fixed true \ + -io_std MIPI25 \ + -DIRECTION INPUT + + +set_io -port_name CAM1_SCL \ + -pin_name K7 \ + -fixed true \ + -io_std LVCMOS25 \ + -DIRECTION INOUT + + +set_io -port_name CAM1_SDA \ + -pin_name J8 \ + -fixed true \ + -io_std LVCMOS25 \ + -DIRECTION INOUT + + +set_io -port_name CAM_CLK_EN \ + -pin_name K5 \ + -fixed true \ + -io_std LVCMOS25 \ + -DIRECTION OUTPUT + + +set_io -port_name LED2 \ + -pin_name AP28 \ + -fixed true \ + -io_std LVCMOS12 \ + -DIRECTION OUTPUT + + +set_io -port_name LED3 \ + -pin_name AP29 \ + -fixed true \ + -io_std LVCMOS12 \ + -DIRECTION OUTPUT + + +set_io -port_name TEN \ + -pin_name AM5 \ + -fixed true \ + -io_std HSTL12I \ + -DIRECTION OUTPUT + + +set_io -port_name cam1inck \ + -pin_name J5 \ + -fixed true \ + -io_std LVCMOS25 \ + -DIRECTION OUTPUT + + +set_io -port_name cam1xmaster \ + -pin_name J4 \ + -fixed true \ + -io_std LVCMOS25 \ + -DIRECTION OUTPUT + + + +# +# Dedicated Peripheral I/O Settings +# + + +# +# Unlocked I/O settings +# The I/Os in this section are unplaced or placed but are not locked +# the other listed attributes have been applied +# + + +# +#Ports using Dedicated Pins + +# + +set_io -port_name REF_CLK_PAD_N \ + -pin_name AF30 \ + -DIRECTION INPUT + + +set_io -port_name REF_CLK_PAD_P \ + -pin_name AF29 \ + -DIRECTION INPUT + + diff --git a/script_support/constraint/user.sdc b/script_support/constraint/user.sdc index 6c12115..46f7cca 100644 --- a/script_support/constraint/user.sdc +++ b/script_support/constraint/user.sdc @@ -1,16 +1,16 @@ - -# Reset path to ALn hence ignoring -#set_false_path -from [ get_pins { Video_Pipeline_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/COREBCLKSCLKALIGN_0/PF_IOD_GENERIC_RX_C0_TR_0/genblk1.U_ICB_BCLKSCLKALIGN/RX_CLK_ALIGN_DONE/CLK } ] -# 125MHz clock used in AXI interconnect, FIC1 and LPDDR memory access -set_clock_groups -name {clk_grp_fic1} -asynchronous -group [ get_clocks { CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0 } ] -# APB clock -set_clock_groups -name {clk_grp_fab_apb} -asynchronous -group [ get_clocks { CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT1 } ] -# I2C clock for camera data given to MSS block -set_clock_groups -name {clk_grp_i2c} -asynchronous -group [ get_clocks { CLOCKS_AND_RESETS_inst_0/PF_OSC_C0_0/PF_OSC_C0_0/I_OSC_2/CLK } ] -#cam clocks -set_clock_groups -name {clk_grp_cam_ccc_o0} -asynchronous -group [ get_clocks { Video_Pipeline_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0 } ] -set_clock_groups -name {clk_grp_cam_ccc_ydiv0} -asynchronous -group [ get_clocks {Video_Pipeline_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV } ] - -# scale factors are mostly static and will change only on frame start -set_false_path -from [ get_pins { Video_Pipeline_0/video_processing_0/frame_controls_gen_0/h_scale_factor_o* } ] -set_false_path -from [ get_pins { Video_Pipeline_0/video_processing_0/frame_controls_gen_0/v_scale_factor_o* } ] + +# Reset path to ALn hence ignoring +#set_false_path -from [ get_pins { Video_Pipeline_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/COREBCLKSCLKALIGN_0/PF_IOD_GENERIC_RX_C0_TR_0/genblk1.U_ICB_BCLKSCLKALIGN/RX_CLK_ALIGN_DONE/CLK } ] +# 125MHz clock used in AXI interconnect, FIC1 and LPDDR memory access +set_clock_groups -name {clk_grp_fic1} -asynchronous -group [ get_clocks { CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0 } ] +# APB clock +set_clock_groups -name {clk_grp_fab_apb} -asynchronous -group [ get_clocks { CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT1 } ] +# I2C clock for camera data given to MSS block +set_clock_groups -name {clk_grp_i2c} -asynchronous -group [ get_clocks { CLOCKS_AND_RESETS_inst_0/PF_OSC_C0_0/PF_OSC_C0_0/I_OSC_2/CLK } ] +#cam clocks +set_clock_groups -name {clk_grp_cam_ccc_o0} -asynchronous -group [ get_clocks { Video_Pipeline_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0 } ] +set_clock_groups -name {clk_grp_cam_ccc_ydiv0} -asynchronous -group [ get_clocks {Video_Pipeline_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV } ] + +# scale factors are mostly static and will change only on frame start +set_false_path -from [ get_pins { Video_Pipeline_0/video_processing_0/frame_controls_gen_0/h_scale_factor_o* } ] +set_false_path -from [ get_pins { Video_Pipeline_0/video_processing_0/frame_controls_gen_0/v_scale_factor_o* } ] diff --git a/script_support/hdl/CR_OSD.v b/script_support/hdl/CR_OSD.v new file mode 100644 index 0000000..419fda3 --- /dev/null +++ b/script_support/hdl/CR_OSD.v @@ -0,0 +1,682 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2022, Microchip Corporation +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// * Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// * Neither the name of the nor the +// names of its contributors may be used to endorse or promote products +// derived from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL MICROCHIP CORPORATIONM BE LIABLE FOR ANY +// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// APACHE LICENSE +// Copyright (c) 2022, Microchip Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//////////////////////////////////////////////////////////////////////////////// +//compression ratio on screen display +module CR_OSD( + // Inputs + DATA_ENABLE_I, + FRAME_END_I, + RESETN_I, + SYS_CLK_I, + b_i, + coordinate_i, + g_i, + num_i, + r_i, + text_color_rgb_i, + // Outputs + b_o, + g_o, + r_o +); + +//-------------------------------------------------------------------- +// Input +//-------------------------------------------------------------------- +input DATA_ENABLE_I; +input FRAME_END_I; +input RESETN_I; +input SYS_CLK_I; +input [7:0] b_i; +input [31:0] coordinate_i; +input [7:0] g_i; +input [11:0] num_i; +input [7:0] r_i; +input [23:0] text_color_rgb_i; +//-------------------------------------------------------------------- +// Output +//-------------------------------------------------------------------- +output [7:0] b_o; +output [7:0] g_o; +output [7:0] r_o; +//-------------------------------------------------------------------- +// Nets +//-------------------------------------------------------------------- +wire [7:0] b_i; +wire [7:0] b_o_net_0; +wire [19:0] CH_ROM_0_dout; +wire [31:0] coordinate_i; +wire DATA_ENABLE_I; +wire FRAME_END_I; +wire [7:0] g_i; +wire [7:0] g_o_net_0; +wire [15:0] HV_COUNTER_0_H_COUNT_O; +wire HV_COUNTER_0_LINE_END_O; +wire [15:0] HV_COUNTER_0_V_COUNT_O; +wire [11:0] num_i; +wire [7:0] NUM_ROM_0_dout; +wire [9:0] obj_generator_0_mem_addr_o; +wire obj_generator_0_mem_rd_o; +wire obj_generator_0_text_valid_o; +wire [9:0] obj_generator_num_0_mem_addr_o; +wire obj_generator_num_0_mem_rd_o; +wire obj_generator_num_0_text_valid_o; +wire OR2_0_Y; +wire [7:0] r_i; +wire [7:0] r_o_net_0; +wire RESETN_I; +wire SYS_CLK_I; +wire [23:16] text_color_rgb_i_slice_0; +wire [15:8] text_color_rgb_i_slice_1; +wire [7:0] text_color_rgb_i_slice_2; +wire [7:0] b_o_net_1; +wire [7:0] r_o_net_1; +wire [7:0] g_o_net_1; +wire [23:0] text_color_rgb_i; +//-------------------------------------------------------------------- +// Top level output port assignments +//-------------------------------------------------------------------- +assign b_o_net_1 = b_o_net_0; +assign b_o[7:0] = b_o_net_1; +assign r_o_net_1 = r_o_net_0; +assign r_o[7:0] = r_o_net_1; +assign g_o_net_1 = g_o_net_0; +assign g_o[7:0] = g_o_net_1; +//-------------------------------------------------------------------- +// Slices assignments +//-------------------------------------------------------------------- +assign text_color_rgb_i_slice_0 = text_color_rgb_i[23:16]; +assign text_color_rgb_i_slice_1 = text_color_rgb_i[15:8]; +assign text_color_rgb_i_slice_2 = text_color_rgb_i[7:0]; +//-------------------------------------------------------------------- +// Component instances +//-------------------------------------------------------------------- +//--------CH_ROM +CH_ROM CH_ROM_0( + // Inputs + .clk ( SYS_CLK_I ), + .en ( obj_generator_0_mem_rd_o ), + .addr ( obj_generator_0_mem_addr_o ), + // Outputs + .dout ( CH_ROM_0_dout ) + ); + +//--------HV_COUNTER +HV_COUNTER HV_COUNTER_0( + // Inputs + .resetn_i ( RESETN_I ), + .sys_clk_i ( SYS_CLK_I ), + .DATA_ENABLE_I ( DATA_ENABLE_I ), + .FRAME_END_I ( FRAME_END_I ), + // Outputs + .LINE_END_O ( HV_COUNTER_0_LINE_END_O ), + .H_COUNT_O ( HV_COUNTER_0_H_COUNT_O ), + .V_COUNT_O ( HV_COUNTER_0_V_COUNT_O ) + ); + +//--------NUM_ROM +NUM_ROM NUM_ROM_0( + // Inputs + .clk ( SYS_CLK_I ), + .en ( obj_generator_num_0_mem_rd_o ), + .addr ( obj_generator_num_0_mem_addr_o ), + // Outputs + .dout ( NUM_ROM_0_dout ) + ); + +//--------obj_generator +obj_generator obj_generator_0( + // Inputs + .resetn_i ( RESETN_I ), + .sys_clk_i ( SYS_CLK_I ), + .line_end_i ( HV_COUNTER_0_LINE_END_O ), + .h_counter_i ( HV_COUNTER_0_H_COUNT_O ), + .v_counter_i ( HV_COUNTER_0_V_COUNT_O ), + .ram_data_i ( CH_ROM_0_dout ), + .coordinate_i ( coordinate_i ), + // Outputs + .mem_rd_o ( obj_generator_0_mem_rd_o ), + .text_valid_o ( obj_generator_0_text_valid_o ), + .mem_addr_o ( obj_generator_0_mem_addr_o ) + ); + +//--------obj_generator_num +obj_generator_num obj_generator_num_0( + // Inputs + .resetn_i ( RESETN_I ), + .sys_clk_i ( SYS_CLK_I ), + .line_end_i ( HV_COUNTER_0_LINE_END_O ), + .h_counter_i ( HV_COUNTER_0_H_COUNT_O ), + .v_counter_i ( HV_COUNTER_0_V_COUNT_O ), + .num_i ( num_i ), + .ram_data_i ( NUM_ROM_0_dout ), + .coordinate_i ( coordinate_i ), + // Outputs + .mem_rd_o ( obj_generator_num_0_mem_rd_o ), + .text_valid_o ( obj_generator_num_0_text_valid_o ), + .mem_addr_o ( obj_generator_num_0_mem_addr_o ) + ); + +//--------OR2 +OR2 OR2_0( + // Inputs + .A ( obj_generator_0_text_valid_o ), + .B ( obj_generator_num_0_text_valid_o ), + // Outputs + .Y ( OR2_0_Y ) + ); + +//--------text_out +text_out text_out_0( + // Inputs + .txt_vld_i ( OR2_0_Y ), + .r_i ( r_i ), + .g_i ( g_i ), + .b_i ( b_i ), + .text_color_r_i ( text_color_rgb_i_slice_0 ), + .text_color_g_i ( text_color_rgb_i_slice_1 ), + .text_color_b_i ( text_color_rgb_i_slice_2 ), + // Outputs + .r_o ( r_o_net_0 ), + .g_o ( g_o_net_0 ), + .b_o ( b_o_net_0 ) + ); + + +endmodule + +//pixel,line counter +module HV_COUNTER ( + input resetn_i , + input sys_clk_i , + input DATA_ENABLE_I, + input FRAME_END_I , + output LINE_END_O , + output [15:0] H_COUNT_O , + output [15:0] V_COUNT_O + ); +/************************************************************************ + Register/Wire Declarations +*************************************************************************/ +reg [15:0] s_h_counter; +reg [15:0] s_v_counter; +reg s_data_en_dly; +wire s_data_en_ne; +/************************************************************************ + Top level ouput port assignments +*************************************************************************/ +assign H_COUNT_O = s_h_counter; +assign V_COUNT_O = s_v_counter; +assign LINE_END_O = s_data_en_ne; +/************************************************************************ + Internal assignments +*************************************************************************/ +assign s_data_en_ne = (~ DATA_ENABLE_I) & (s_data_en_dly); +/************************************************************************ + horizontal counter +*************************************************************************/ +always@(posedge sys_clk_i, negedge resetn_i) + if (!resetn_i) + s_h_counter <= 0; + else if (FRAME_END_I == 1 || DATA_ENABLE_I == 0) + s_h_counter <= 0; + else + s_h_counter <= s_h_counter + 1; +/************************************************************************ + vertical counter +*************************************************************************/ +always@(posedge sys_clk_i, negedge resetn_i) + if (!resetn_i) + s_v_counter <= 0; + else if (FRAME_END_I) + s_v_counter <= 0; + else if (s_data_en_ne) + s_v_counter <= s_v_counter + 1; +/************************************************************************ + Delays the sgnals +*************************************************************************/ +always@(posedge sys_clk_i, negedge resetn_i) + if (!resetn_i) + s_data_en_dly <= 0; + else + s_data_en_dly <= DATA_ENABLE_I; +endmodule + +//obj_generator for text +module obj_generator#( + parameter g_NUM_OF_CHAR = 25, + parameter g_ADDR_WIDTH = 10) +( + input resetn_i , + input sys_clk_i , + input line_end_i, + input [15:0] h_counter_i, + input [15:0] v_counter_i, + input [19:0] ram_data_i, + input [31:0] coordinate_i, + output mem_rd_o , + output [g_ADDR_WIDTH-1 : 0] mem_addr_o, + output text_valid_o + + ); +/************************************************************************ + Register/Wire Declarations +*************************************************************************/ + reg [g_ADDR_WIDTH-1 : 0] s_addr_offset; + reg [g_ADDR_WIDTH-1 : 0] s_addr_counter ; + reg [4:0] s_data_bus_width_counter ; + wire s_obj1_valid; + reg s_data_bit; + wire [15:0] s_x_coordinate; + wire [15:0] s_y_coordinate; +/************************************************************************ + Top level ouput port assignments +*************************************************************************/ +assign mem_addr_o = s_addr_counter; +assign mem_rd_o = 1'b1; +assign text_valid_o = s_data_bit & s_obj1_valid; +/************************************************************************ + Internal assignments +*************************************************************************/ +assign s_x_coordinate = coordinate_i[31:16]; +assign s_y_coordinate = coordinate_i[15:0]; +assign s_obj1_valid = (h_counter_i >= s_x_coordinate && + h_counter_i < (s_x_coordinate + (16*g_NUM_OF_CHAR)) && + v_counter_i >= s_y_coordinate && + v_counter_i < (s_y_coordinate + 16)) ? 1'b1 : 1'b0 ; +assign s_data_bit = ram_data_i[s_data_bus_width_counter]; +/************************************************************************ + address offset +*************************************************************************/ +always@(posedge sys_clk_i, negedge resetn_i) + if (!resetn_i) + s_addr_offset <= 0; + else begin + if (h_counter_i == s_x_coordinate && v_counter_i == s_y_coordinate) + s_addr_offset <= 0; + else if (line_end_i == 1 && v_counter_i[0] == 1) + s_addr_offset <= s_addr_offset + 10; + end + +/************************************************************************ + address counter +*************************************************************************/ +always@(posedge sys_clk_i, negedge resetn_i) + if (!resetn_i) + s_addr_counter <= 0; + else begin + if (h_counter_i == s_x_coordinate && v_counter_i == s_y_coordinate) + s_addr_counter <= 0; + else if (h_counter_i == 0) + s_addr_counter <= s_addr_offset; + else if (s_obj1_valid == 1 && s_data_bus_width_counter == 0 && h_counter_i[0] == 0) + s_addr_counter <= s_addr_counter + 1; + end +/************************************************************************ + address bus width counter +*************************************************************************/ +always@(posedge sys_clk_i, negedge resetn_i) + if (!resetn_i) + s_data_bus_width_counter <= 19; + else begin + if ( + (h_counter_i == s_x_coordinate && v_counter_i == s_y_coordinate) || + (s_data_bus_width_counter == 0 && h_counter_i[0] == 1)) + s_data_bus_width_counter <= 19; + else if (s_obj1_valid == 1 && s_data_bus_width_counter > 0 && h_counter_i[0] == 1) + s_data_bus_width_counter <= s_data_bus_width_counter - 1; + end +endmodule + +//obj_generator for numbers +module obj_generator_num#( + parameter g_NUM_OF_CHAR = 3, + parameter g_ADDR_WIDTH = 10) +( + input resetn_i , + input sys_clk_i , + input line_end_i, + input [15:0] h_counter_i, + input [15:0] v_counter_i, + + //input number each four bits represent a digit + input [11:0] num_i, + input [7:0] ram_data_i, + input [31:0] coordinate_i, + output mem_rd_o , + output [g_ADDR_WIDTH-1 : 0] mem_addr_o, + output text_valid_o + + ); +/************************************************************************ + Register/Wire Declarations +*************************************************************************/ + reg [g_ADDR_WIDTH-1 : 0] s_addr_offset; + reg [g_ADDR_WIDTH-1 : 0] s_addr_counter; + reg [7:0] s_num1_addr; + reg [7:0] s_num2_addr; + reg [7:0] s_num3_addr; + reg [4:0] s_data_bus_width_counter ; + wire s_obj1_valid; + reg s_data_bit; + wire [15:0] s_x_coordinate; + wire [15:0] s_y_coordinate; +/************************************************************************ + Top level ouput port assignments +*************************************************************************/ +assign mem_addr_o = s_addr_counter; +assign mem_rd_o = 1'b1; +assign text_valid_o = s_data_bit & s_obj1_valid; +/************************************************************************ + Internal assignments +*************************************************************************/ +assign s_x_coordinate = coordinate_i[31:16] + 288;//18 chars offset - 18*16;; +assign s_y_coordinate = coordinate_i[15:0]; +assign s_obj1_valid = (h_counter_i >= s_x_coordinate && + h_counter_i < (s_x_coordinate + (16*g_NUM_OF_CHAR)) && + v_counter_i >= s_y_coordinate && + v_counter_i < (s_y_coordinate + 16)) ? 1'b1 : 1'b0 ; +assign s_data_bit = ram_data_i[s_data_bus_width_counter]; +/************************************************************************ + address offset +*************************************************************************/ +always@(posedge sys_clk_i, negedge resetn_i) + if (!resetn_i) + s_addr_offset <= 0; + else begin + if (h_counter_i == s_x_coordinate-3 && v_counter_i == s_y_coordinate) + s_addr_offset <= 0; + else if (line_end_i == 1 && v_counter_i[0] == 1) + s_addr_offset <= s_addr_offset + 1; + end + +/************************************************************************ + address counter +*************************************************************************/ +always@(posedge sys_clk_i, negedge resetn_i) + if (!resetn_i) + s_addr_counter <= 0; + else begin + if (h_counter_i == s_x_coordinate-2) + s_addr_counter <= s_num1_addr + s_addr_offset; + else if (h_counter_i == s_x_coordinate-2+16) + s_addr_counter <= s_num2_addr + s_addr_offset; + else if (h_counter_i == s_x_coordinate-2+32) + s_addr_counter <= s_num3_addr + s_addr_offset; + end +/************************************************************************ + address bus width counter +*************************************************************************/ +always@(posedge sys_clk_i, negedge resetn_i) + if (!resetn_i) + s_data_bus_width_counter <= 7; + else begin + if ((h_counter_i == s_x_coordinate && v_counter_i == s_y_coordinate) || + (s_data_bus_width_counter == 0 && h_counter_i[0] == 1)) + s_data_bus_width_counter <= 7; + else if (s_obj1_valid == 1 && s_data_bus_width_counter > 0 && h_counter_i[0] == 1) + s_data_bus_width_counter <= s_data_bus_width_counter - 1; + end +/************************************************************************ + digit address offset +*************************************************************************/ +always@(posedge sys_clk_i, negedge resetn_i) + if (!resetn_i) begin + s_num1_addr <= 0; + s_num2_addr <= 0; + s_num3_addr <= 0; + end + else if (h_counter_i == 0 && v_counter_i == 0) begin + s_num1_addr <= {num_i[11:8] , 3'b0}; //each digit takes 8 bytes + s_num2_addr <= {num_i[7 :4] , 3'b0}; + s_num3_addr <= {num_i[3 :0] , 3'b0}; + end +endmodule + +// Characters ROM.v +module CH_ROM(clk,en,addr,dout); +input clk; +input en; +input [9:0] addr; +output reg [19:0] dout; + +reg [19:0] mem [0:79] = '{ 20'h1f3e6, + 20'h37c78, + 20'h7e3e3, + 20'he7f3e, + 20'h41007, + 20'h81c7f, + 20'h7f3e0, + 20'h0 , + 20'h0 , + 20'h0 , + 20'h20415, + 20'h54244, + 20'h40404, + 20'h841 , + 20'h61004, + 20'h42208, + 20'h8410 , + 20'h0 , + 20'h0 , + 20'h0 , + 20'h20414, + 20'h94244, + 20'h40404, + 20'h841 , + 20'h61004, + 20'h44108, + 20'h8410 , + 20'h0 , + 20'h0 , + 20'h0 , + 20'h40414, + 20'h9424c, + 20'h7c3c3, + 20'hc0841, + 20'h51004, + 20'hc4108, + 20'h8410 , + 20'h0 , + 20'h0 , + 20'h0 , + 20'h40414, + 20'h17c70, + 20'h40020, + 20'h20841, + 20'h49007, + 20'h7f08 , + 20'h8410 , + 20'h0 , + 20'h0 , + 20'h0 , + 20'h60414, + 20'h14048, + 20'h40020, + 20'h20841, + 20'h45004, + 20'h84108, + 20'h8410 , + 20'h0 , + 20'h0 , + 20'h0 , + 20'h20414, + 20'h14044, + 20'h40020, + 20'h20841, + 20'h43004, + 20'h44108, + 20'h8410 , + 20'h0 , + 20'h0 , + 20'h0 , + 20'h1f3e4, + 20'h14042, + 20'h7e7c7, + 20'hc7f3e, + 20'h41004, + 20'h24108, + 20'h7f3e0, + 20'h0 , + 20'h0 , + 20'h0}; + +always@(posedge clk) +begin + if(en) + dout <= mem[addr]; +end +endmodule + +// Numbers ROM.v +module NUM_ROM(clk,en,addr,dout); +input clk; +input en; +input [9:0] addr; +output reg [7:0] dout; + +reg [7:0] mem [0:79] = '{8'h3e, + 8'h43, + 8'h45, + 8'h49, + 8'h51, + 8'h61, + 8'h41, + 8'h3e, + 8'h08, + 8'h18, + 8'h28, + 8'h48, + 8'h08, + 8'h08, + 8'h08, + 8'h7f, + 8'h7c, + 8'h02, + 8'h01, + 8'h01, + 8'h3e, + 8'h40, + 8'h40, + 8'h7f, + 8'h7c, + 8'h02, + 8'h01, + 8'h01, + 8'h7e, + 8'h01, + 8'h01, + 8'h7e, + 8'h06, + 8'h0e, + 8'h1a, + 8'h22, + 8'h7f, + 8'h02, + 8'h02, + 8'h02, + 8'h7e, + 8'h40, + 8'h40, + 8'h7e, + 8'h01, + 8'h01, + 8'h01, + 8'h7e, + 8'h1e, + 8'h20, + 8'h40, + 8'h7e, + 8'h41, + 8'h41, + 8'h22, + 8'h1c, + 8'h7f, + 8'h01, + 8'h02, + 8'h04, + 8'h08, + 8'h10, + 8'h20, + 8'h40, + 8'h3e, + 8'h41, + 8'h41, + 8'h3e, + 8'h41, + 8'h41, + 8'h41, + 8'h3e, + 8'h3f, + 8'h41, + 8'h41, + 8'h41, + 8'h3f, + 8'h01, + 8'h01, + 8'h01}; + +always@(posedge clk) +begin + if(en) + dout <= mem[addr]; +end +endmodule + +// text_out.v +module text_out ( + input txt_vld_i, + input [7:0] r_i, + input [7:0] g_i, + input [7:0] b_i, + input [7:0] text_color_r_i, + input [7:0] text_color_g_i, + input [7:0] text_color_b_i, + output [7:0] r_o, + output [7:0] g_o, + output [7:0] b_o + ); + +assign r_o = txt_vld_i ? text_color_r_i : r_i; +assign g_o = txt_vld_i ? text_color_g_i : g_i; +assign b_o = txt_vld_i ? text_color_b_i : b_i; + +endmodule \ No newline at end of file diff --git a/script_support/hdl/H264/apb_wrapper.vhd b/script_support/hdl/H264/apb_wrapper.vhd index 3f0339d..6a6a24e 100644 --- a/script_support/hdl/H264/apb_wrapper.vhd +++ b/script_support/hdl/H264/apb_wrapper.vhd @@ -1,432 +1,472 @@ ---////////////////////////////////////////////////////////////////////////////// --- Copyright (c) 2022, Microchip Corporation --- All rights reserved. --- --- Redistribution and use in source and binary forms, with or without --- modification, are permitted provided that the following conditions are met: --- * Redistributions of source code must retain the above copyright --- notice, this list of conditions and the following disclaimer. --- * Redistributions in binary form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- * Neither the name of the nor the --- names of its contributors may be used to endorse or promote products --- derived from this software without specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND --- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED --- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE --- DISCLAIMED. IN NO EVENT SHALL MICROCHIP CORPORATIONM BE LIABLE FOR ANY --- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; --- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND --- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT --- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS --- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --- --- APACHE LICENSE --- Copyright (c) 2022, Microchip Corporation --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. ---////////////////////////////////////////////////////////////////////////////// - ---================================================================================================= --- Libraries ---================================================================================================= -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.NUMERIC_STD.all; - ---================================================================================================= --- apb3_if entity declaration ---================================================================================================= -entity apb3_if is - generic ( - -- Specifies pwdata_i,prdata_o signal width - g_APB3_IF_DATA_WIDTH : integer := 32; - - -- Specifies the width of constants - g_CONST_WIDTH : integer := 12 - ); - port ( --- Port list - -- APB reset - preset_i : in std_logic; - -- APB clock - pclk_i : in std_logic; - - -- APB slave interface - psel_i : in std_logic; - pwrite_i : in std_logic; - penable_i : in std_logic; - paddr_i : in std_logic_vector(g_APB3_IF_DATA_WIDTH-1 downto 0); - pwdata_i : in std_logic_vector(g_APB3_IF_DATA_WIDTH-1 downto 0); - pready_o : out std_logic; - pslverr_o : out std_logic; - prdata_o : out std_logic_vector(g_APB3_IF_DATA_WIDTH-1 downto 0); - - --frame valid from camera - frame_valid_i : in std_logic; - - r_gain_i : in std_logic_vector(7 downto 0); - g_gain_i : in std_logic_vector(7 downto 0); - b_gain_i : in std_logic_vector(7 downto 0); - brightness_i : in std_logic_vector(7 downto 0); - contrast_i : in std_logic_vector(7 downto 0); - quality_i : in std_logic_vector(7 downto 0); - RGB_SUM_i : in std_logic_vector(31 downto 0); - frame_index_i: in std_logic_vector(1 downto 0); - frame_bytes_i: in std_logic_vector(31 downto 0); - - mode_o : out std_logic; - alpha_o : out std_logic_vector(7 downto 0); - step_o : out std_logic_vector(7 downto 0); - rconst_o : out std_logic_vector(9 downto 0); - gconst_o : out std_logic_vector(9 downto 0); - bconst_o : out std_logic_vector(9 downto 0); - second_const_o : out std_logic_vector(19 downto 0); - horiz_resl_o : out std_logic_vector(15 downto 0); - vert_resl_o : out std_logic_vector(15 downto 0); - quality_o : out std_logic_vector(7 downto 0) ; - frame_tcount_o : out std_logic_vector(3 downto 0) ; - h264_en_o : out std_logic; - h264_ddrlsb_addr_o : out std_logic_vector(31 downto 0); - h264_clr_intr_o: out std_logic - ); -end apb3_if; - ---================================================================================================= --- apb3_if architecture body ---================================================================================================= - -architecture apb3_if of apb3_if is - ---================================================================================================= --- Component declarations ---================================================================================================= ---NA-- - ---================================================================================================= --- Synthesis Attributes ---================================================================================================= ---NA-- - ---================================================================================================= --- Signal declarations ---================================================================================================= ---ADC Register Addresses - constant C_ALPHA_REG_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"000"; - constant C_RCONST_REG_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"004"; - constant C_GCONST_REG_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"008"; - constant C_BCONST_REG_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"00C"; - constant C_SECOND_CONST_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"010"; - constant C_RGAIN_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"020"; - constant C_GGAIN_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"024"; - constant C_BGAIN_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"028"; - constant C_CONTRAST_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"030"; - constant C_BRIGHTNESS_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"034"; - constant C_RGB_SUM_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"038"; - - constant C_STEP_OUT_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"060"; - constant C_MODE_OUT_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"064"; - constant C_FRAME_TCOUNT_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"070"; - constant C_QUALITY_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"074"; - constant C_HORIZ_RESL_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"078"; - constant C_VERT_RESL_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"07C"; - - --H264 - constant C_FRM_BYTES_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"080"; - constant C_H264START_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"084"; - constant C_H264DDRLSB_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"088"; - constant C_H264DDRMSB_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"08C"; - - constant C_ID_ROM_3_0_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"500"; - constant C_ID_ROM_7_4_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"504"; - - signal s_frame_valid_dly1 : std_logic; - signal s_frame_valid_re : std_logic; - signal s_horiz_resl : std_logic_vector(15 downto 0); - signal s_vert_resl : std_logic_vector(15 downto 0); - - signal s_signature : std_logic_vector(63 downto 0) := x"48_32_36_34_00_00_00_01";--h264 0001 - -begin - - ---================================================================================================= --- Top level output port assignments ---================================================================================================= - pready_o <= '1'; -- pready_o Is always ready,there will not be any - -- latency from the Fabric modules - pslverr_o <= '0'; -- Slave error is always '0' as there will not be - --any slave error. - ---================================================================================================= --- Generate blocks ---================================================================================================= - ---================================================================================================= --- Asynchronous blocks ---================================================================================================= -s_frame_valid_re <= frame_valid_i AND (NOT s_frame_valid_dly1); --------------------------------------------------------------------------- --- Name : READ_DECODE_PROC --- Description: Process implements the APB read operation --------------------------------------------------------------------------- - - READ_DECODE_PROC : - process (paddr_i, r_gain_i, g_gain_i, b_gain_i, contrast_i, brightness_i, quality_i, RGB_SUM_i) - begin - case paddr_i(11 downto 0) is --------------------- --- C_RCONST_REG_ADDR --------------------- - when C_RCONST_REG_ADDR => - prdata_o(9 downto 0) <= rconst_o; - prdata_o(g_APB3_IF_DATA_WIDTH-1 downto 10) - <= (others => '0'); - --------------------- --- C_RGAIN_ADDR --------------------- - when C_RGAIN_ADDR => - prdata_o(7 downto 0) <= r_gain_i; - prdata_o(g_APB3_IF_DATA_WIDTH-1 downto 8) - <= (others => '0'); - --------------------- --- C_GGAIN_ADDR --------------------- - when C_GGAIN_ADDR => - prdata_o(7 downto 0) <= g_gain_i; - prdata_o(g_APB3_IF_DATA_WIDTH-1 downto 8) - <= (others => '0'); - --------------------- --- C_BGAIN_ADDR --------------------- - when C_BGAIN_ADDR => - prdata_o(7 downto 0) <= b_gain_i; - prdata_o(g_APB3_IF_DATA_WIDTH-1 downto 8) - <= (others => '0'); --------------------- --- C_CONTRAST_ADDR --------------------- - when C_CONTRAST_ADDR => - prdata_o(7 downto 0) <= contrast_i; - prdata_o(g_APB3_IF_DATA_WIDTH-1 downto 8) - <= (others => '0'); --------------------- --- C_BRIGHTNESS_ADDR --------------------- - when C_BRIGHTNESS_ADDR => - prdata_o(7 downto 0) <= brightness_i; - prdata_o(g_APB3_IF_DATA_WIDTH-1 downto 8) - <= (others => '0'); - --------------------- --- C_RGB_SUM_ADDR --------------------- - when C_RGB_SUM_ADDR => - prdata_o(31 downto 0) <= RGB_SUM_i; - --------------------- --- C_QUALITY_ADDR --------------------- - when C_QUALITY_ADDR => - prdata_o(7 downto 0) <= quality_i; - prdata_o(g_APB3_IF_DATA_WIDTH-1 downto 8) - <= (others => '0'); - --------------------- --- C_FRM_BYTES_ADDR --------------------- - when C_FRM_BYTES_ADDR => - prdata_o(g_APB3_IF_DATA_WIDTH-1 downto 0) <= "00"&frame_index_i&frame_bytes_i(27 downto 0); - --------------------- --- C_ID_ROM_3_0_ADDR --------------------- - when C_ID_ROM_3_0_ADDR => - prdata_o(g_APB3_IF_DATA_WIDTH-1 downto 0) <= s_signature(63 downto 32); - --------------------- --- C_ID_ROM_7_4_ADDR --------------------- - when C_ID_ROM_7_4_ADDR => - prdata_o(g_APB3_IF_DATA_WIDTH-1 downto 0) <= s_signature(31 downto 0); - --------------------- --- OTHERS --------------------- - when others => - prdata_o <= (others => '0'); - - end case; - - end process; - ---================================================================================================= --- Synchronous blocks ---================================================================================================= --------------------------------------------------------------------------- --- Name : H264_CLE_INTR_PROC --- Description: Process to clear h264 interrupt --------------------------------------------------------------------------- - H264_CLE_INTR_PROC : - process (preset_i, pclk_i) - begin - if(preset_i = '0')then - h264_clr_intr_o <= '0'; - elsif (pclk_i'event and pclk_i = '1') then - if ((psel_i = '1') and (penable_i = '1') and (pwrite_i = '0')) then - if( paddr_i(11 downto 0) = C_FRM_BYTES_ADDR ) then - h264_clr_intr_o <= '1'; - end if; - else - h264_clr_intr_o <= '0'; - end if; - end if; - end process; --------------------------------------------------------------------------- --- Name : WRITE_DECODE_PROC --- Description: Process implements the APB write operation --------------------------------------------------------------------------- - WRITE_DECODE_PROC : - process (preset_i, pclk_i) - begin - if(preset_i = '0')then - alpha_o <= x"FF"; - rconst_o <= "00"&x"7A"; - gconst_o <= "00"&x"66"; - bconst_o <= "00"&x"8A"; - step_o <= x"01"; - mode_o <= '1'; - second_const_o <= (others => '0'); - s_horiz_resl <= x"0500" ; - s_vert_resl <= x"02D0" ; - quality_o <= x"1E" ; - h264_ddrlsb_addr_o <= x"AE000000"; - h264_en_o <= '0'; - elsif (pclk_i'event and pclk_i = '1') then - if ((psel_i = '1') and (pwrite_i = '1') and (penable_i = '1')) then - case paddr_i(11 downto 0) is --------------------- --- C_RCONST_REG_ADDR --------------------- - when C_RCONST_REG_ADDR => - rconst_o <= pwdata_i(9 downto 0); - --------------------- --- C_ALPHA_REG_ADDR --------------------- - when C_ALPHA_REG_ADDR => - alpha_o <= pwdata_i(7 downto 0); --------------------- --- C_GCONST_REG_ADDR --------------------- - when C_GCONST_REG_ADDR => - gconst_o <= pwdata_i(9 downto 0); --------------------- --- C_BCONST_REG_ADDR --------------------- - when C_BCONST_REG_ADDR => - bconst_o <= pwdata_i(9 downto 0); - --------------------- --- C_SECOND_CONST_ADDR --------------------- - when C_SECOND_CONST_ADDR => - second_const_o <= pwdata_i(19 downto 0); - --------------------- --- C_STEP_OUT_ADDR --------------------- - when C_STEP_OUT_ADDR => - step_o <= pwdata_i(7 downto 0); --------------------- --- C_MODE_OUT_ADDR --------------------- - when C_MODE_OUT_ADDR => - mode_o <= pwdata_i(0); - --------------------- --- C_FRAME_TCOUNT_ADDR --------------------- - when C_FRAME_TCOUNT_ADDR => - frame_tcount_o <= pwdata_i(3 downto 0); - --------------------- --- C_QUALITY_ADDR --------------------- - when C_QUALITY_ADDR => - quality_o <= pwdata_i(7 downto 0); - --------------------- --- C_HORIZ_RESL_ADDR --------------------- - when C_HORIZ_RESL_ADDR => - s_horiz_resl <= pwdata_i(15 downto 0); - --------------------- --- C_VERT_RESL_ADDR --------------------- - when C_VERT_RESL_ADDR => - s_vert_resl <= pwdata_i(15 downto 0); - --------------------- --- C_H264START_ADDR --------------------- - when C_H264START_ADDR => - h264_en_o <= pwdata_i(0); - --------------------- --- C_H264DDRLSB_ADDR --------------------- - when C_H264DDRLSB_ADDR => - h264_ddrlsb_addr_o <= pwdata_i; - --------------------- --- OTHERS --------------------- - when others => - null; - end case; - end if; - end if; - end process; --------------------------------------------------------------------------- --- Name : DLY_PROC --- Description: Process to delay the signals --------------------------------------------------------------------------- - DLY_PROC : - process (preset_i, pclk_i) - begin - if(preset_i = '0')then - s_frame_valid_dly1 <= '0'; - horiz_resl_o <= x"0500" ; - vert_resl_o <= x"02D0" ; - elsif (pclk_i'event and pclk_i = '1') then - s_frame_valid_dly1 <= frame_valid_i; - if (s_frame_valid_re = '1') then - horiz_resl_o <= s_horiz_resl; - vert_resl_o <= s_vert_resl; - end if; - end if; - end process; ---================================================================================================= --- Component Instantiations ---================================================================================================= ---NA-- - -end architecture apb3_if; +--////////////////////////////////////////////////////////////////////////////// +-- Copyright (c) 2022, Microchip Corporation +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- * Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- * Redistributions in binary form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- * Neither the name of the nor the +-- names of its contributors may be used to endorse or promote products +-- derived from this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL MICROCHIP CORPORATIONM BE LIABLE FOR ANY +-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- APACHE LICENSE +-- Copyright (c) 2022, Microchip Corporation +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +--////////////////////////////////////////////////////////////////////////////// + +--================================================================================================= +-- Libraries +--================================================================================================= +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +--================================================================================================= +-- apb3_if entity declaration +--================================================================================================= +entity apb3_if is + generic ( + -- Specifies pwdata_i,prdata_o signal width + g_APB3_IF_DATA_WIDTH : integer := 32; + + -- Specifies the width of constants + g_CONST_WIDTH : integer := 12 + ); + port ( +-- Port list + -- APB reset + preset_i : in std_logic; + -- APB clock + pclk_i : in std_logic; + + -- APB slave interface + psel_i : in std_logic; + pwrite_i : in std_logic; + penable_i : in std_logic; + paddr_i : in std_logic_vector(g_APB3_IF_DATA_WIDTH-1 downto 0); + pwdata_i : in std_logic_vector(g_APB3_IF_DATA_WIDTH-1 downto 0); + pready_o : out std_logic; + pslverr_o : out std_logic; + prdata_o : out std_logic_vector(g_APB3_IF_DATA_WIDTH-1 downto 0); + + --frame valid from camera + frame_valid_i : in std_logic; + + r_gain_i : in std_logic_vector(7 downto 0); + g_gain_i : in std_logic_vector(7 downto 0); + b_gain_i : in std_logic_vector(7 downto 0); + brightness_i : in std_logic_vector(7 downto 0); + contrast_i : in std_logic_vector(7 downto 0); + quality_i : in std_logic_vector(7 downto 0); + RGB_SUM_i : in std_logic_vector(31 downto 0); + frame_index_i: in std_logic_vector(1 downto 0); + frame_bytes_i: in std_logic_vector(31 downto 0); + + mode_o : out std_logic; + alpha_o : out std_logic_vector(7 downto 0); + step_o : out std_logic_vector(7 downto 0); + rconst_o : out std_logic_vector(9 downto 0); + gconst_o : out std_logic_vector(9 downto 0); + bconst_o : out std_logic_vector(9 downto 0); + second_const_o : out std_logic_vector(19 downto 0); + horiz_resl_o : out std_logic_vector(15 downto 0); + vert_resl_o : out std_logic_vector(15 downto 0); + quality_o : out std_logic_vector(7 downto 0) ; + frame_tcount_o : out std_logic_vector(3 downto 0) ; + h264_en_o : out std_logic; + h264_ddrlsb_addr_o : out std_logic_vector(31 downto 0); + h264_clr_intr_o: out std_logic; + text_color_o : out std_logic_vector(23 downto 0); + text_coordinates_o : out std_logic_vector(31 downto 0); + disp_digits_o : out std_logic_vector(11 downto 0) + ); +end apb3_if; + +--================================================================================================= +-- apb3_if architecture body +--================================================================================================= + +architecture apb3_if of apb3_if is + +--================================================================================================= +-- Component declarations +--================================================================================================= +--NA-- + +--================================================================================================= +-- Synthesis Attributes +--================================================================================================= +--NA-- + +--================================================================================================= +-- Signal declarations +--================================================================================================= +--ADC Register Addresses + constant C_ALPHA_REG_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"000"; + constant C_RCONST_REG_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"004"; + constant C_GCONST_REG_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"008"; + constant C_BCONST_REG_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"00C"; + constant C_SECOND_CONST_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"010"; + constant C_RGAIN_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"020"; + constant C_GGAIN_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"024"; + constant C_BGAIN_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"028"; + constant C_CONTRAST_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"030"; + constant C_BRIGHTNESS_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"034"; + constant C_RGB_SUM_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"038"; + + constant C_STEP_OUT_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"060"; + constant C_MODE_OUT_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"064"; + constant C_FRAME_TCOUNT_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"070"; + constant C_QUALITY_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"074"; + constant C_HORIZ_RESL_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"078"; + constant C_VERT_RESL_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"07C"; + + --H264 + constant C_FRM_BYTES_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"080"; + constant C_H264START_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"084"; + constant C_H264DDRLSB_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"088"; + constant C_H264DDRMSB_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"08C"; + constant C_TEXT_COORDI_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"100"; + constant C_TEXT_COLOR_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"104"; + constant C_DIGITS_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"108"; + constant C_HORIZ_RESL_RADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"10C"; + constant C_VERT_RESL_RADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"110"; + + constant C_ID_ROM_3_0_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"500"; + constant C_ID_ROM_7_4_ADDR : std_logic_vector(g_CONST_WIDTH-1 downto 0) := x"504"; + + signal s_frame_valid_dly1 : std_logic; + signal s_frame_valid_re : std_logic; + signal s_horiz_resl : std_logic_vector(15 downto 0); + signal s_vert_resl : std_logic_vector(15 downto 0); + + signal s_signature : std_logic_vector(63 downto 0) := x"48_32_36_34_00_00_00_01";--h264 0001 + +begin + + +--================================================================================================= +-- Top level output port assignments +--================================================================================================= + pready_o <= '1'; -- pready_o Is always ready,there will not be any + -- latency from the Fabric modules + pslverr_o <= '0'; -- Slave error is always '0' as there will not be + --any slave error. + +--================================================================================================= +-- Generate blocks +--================================================================================================= + +--================================================================================================= +-- Asynchronous blocks +--================================================================================================= +s_frame_valid_re <= frame_valid_i AND (NOT s_frame_valid_dly1); +-------------------------------------------------------------------------- +-- Name : READ_DECODE_PROC +-- Description: Process implements the APB read operation +-------------------------------------------------------------------------- + + READ_DECODE_PROC : + process (paddr_i, r_gain_i, g_gain_i, b_gain_i, contrast_i, brightness_i, quality_i, RGB_SUM_i) + begin + case paddr_i(11 downto 0) is +-------------------- +-- C_RCONST_REG_ADDR +-------------------- + when C_RCONST_REG_ADDR => + prdata_o(9 downto 0) <= rconst_o; + prdata_o(g_APB3_IF_DATA_WIDTH-1 downto 10) + <= (others => '0'); + +-------------------- +-- C_RGAIN_ADDR +-------------------- + when C_RGAIN_ADDR => + prdata_o(7 downto 0) <= r_gain_i; + prdata_o(g_APB3_IF_DATA_WIDTH-1 downto 8) + <= (others => '0'); + +-------------------- +-- C_GGAIN_ADDR +-------------------- + when C_GGAIN_ADDR => + prdata_o(7 downto 0) <= g_gain_i; + prdata_o(g_APB3_IF_DATA_WIDTH-1 downto 8) + <= (others => '0'); + +-------------------- +-- C_BGAIN_ADDR +-------------------- + when C_BGAIN_ADDR => + prdata_o(7 downto 0) <= b_gain_i; + prdata_o(g_APB3_IF_DATA_WIDTH-1 downto 8) + <= (others => '0'); +-------------------- +-- C_CONTRAST_ADDR +-------------------- + when C_CONTRAST_ADDR => + prdata_o(7 downto 0) <= contrast_i; + prdata_o(g_APB3_IF_DATA_WIDTH-1 downto 8) + <= (others => '0'); +-------------------- +-- C_BRIGHTNESS_ADDR +-------------------- + when C_BRIGHTNESS_ADDR => + prdata_o(7 downto 0) <= brightness_i; + prdata_o(g_APB3_IF_DATA_WIDTH-1 downto 8) + <= (others => '0'); + +-------------------- +-- C_RGB_SUM_ADDR +-------------------- + when C_RGB_SUM_ADDR => + prdata_o(31 downto 0) <= RGB_SUM_i; + +-------------------- +-- C_QUALITY_ADDR +-------------------- + when C_QUALITY_ADDR => + prdata_o(7 downto 0) <= quality_i; + prdata_o(g_APB3_IF_DATA_WIDTH-1 downto 8) + <= (others => '0'); + +-------------------- +-- C_HORIZ_RESL_RADDR +-------------------- + when C_HORIZ_RESL_RADDR => + prdata_o(g_APB3_IF_DATA_WIDTH-1 downto 0) <= x"0000" & s_horiz_resl; + +-------------------- +-- C_VERT_RESL_RADDR +-------------------- + when C_VERT_RESL_RADDR => + prdata_o(g_APB3_IF_DATA_WIDTH-1 downto 0) <= x"0000" & s_vert_resl; + +-------------------- +-- C_FRM_BYTES_ADDR +-------------------- + when C_FRM_BYTES_ADDR => + prdata_o(g_APB3_IF_DATA_WIDTH-1 downto 0) <= "00"&frame_index_i&frame_bytes_i(27 downto 0); + +-------------------- +-- C_ID_ROM_3_0_ADDR +-------------------- + when C_ID_ROM_3_0_ADDR => + prdata_o(g_APB3_IF_DATA_WIDTH-1 downto 0) <= s_signature(63 downto 32); + +-------------------- +-- C_ID_ROM_7_4_ADDR +-------------------- + when C_ID_ROM_7_4_ADDR => + prdata_o(g_APB3_IF_DATA_WIDTH-1 downto 0) <= s_signature(31 downto 0); + +-------------------- +-- OTHERS +-------------------- + when others => + prdata_o <= (others => '0'); + + end case; + + end process; + +--================================================================================================= +-- Synchronous blocks +--================================================================================================= +-------------------------------------------------------------------------- +-- Name : H264_CLE_INTR_PROC +-- Description: Process to clear h264 interrupt +-------------------------------------------------------------------------- + H264_CLE_INTR_PROC : + process (preset_i, pclk_i) + begin + if(preset_i = '0')then + h264_clr_intr_o <= '0'; + elsif (pclk_i'event and pclk_i = '1') then + if ((psel_i = '1') and (penable_i = '1') and (pwrite_i = '0')) then + if( paddr_i(11 downto 0) = C_FRM_BYTES_ADDR ) then + h264_clr_intr_o <= '1'; + end if; + else + h264_clr_intr_o <= '0'; + end if; + end if; + end process; +-------------------------------------------------------------------------- +-- Name : WRITE_DECODE_PROC +-- Description: Process implements the APB write operation +-------------------------------------------------------------------------- + WRITE_DECODE_PROC : + process (preset_i, pclk_i) + begin + if(preset_i = '0')then + alpha_o <= x"FF"; + rconst_o <= "00"&x"7A"; + gconst_o <= "00"&x"66"; + bconst_o <= "00"&x"8A"; + step_o <= x"01"; + mode_o <= '1'; + second_const_o <= (others => '0'); + s_horiz_resl <= x"0500" ; + s_vert_resl <= x"02D0" ; + quality_o <= x"1E" ; + text_color_o <= x"FFFFFF"; + text_coordinates_o <= x"00100010"; + disp_digits_o <= x"000"; + h264_ddrlsb_addr_o <= x"AE000000"; + h264_en_o <= '0'; + elsif (pclk_i'event and pclk_i = '1') then + if ((psel_i = '1') and (pwrite_i = '1') and (penable_i = '1')) then + case paddr_i(11 downto 0) is +-------------------- +-- C_RCONST_REG_ADDR +-------------------- + when C_RCONST_REG_ADDR => + rconst_o <= pwdata_i(9 downto 0); + +-------------------- +-- C_ALPHA_REG_ADDR +-------------------- + when C_ALPHA_REG_ADDR => + alpha_o <= pwdata_i(7 downto 0); +-------------------- +-- C_GCONST_REG_ADDR +-------------------- + when C_GCONST_REG_ADDR => + gconst_o <= pwdata_i(9 downto 0); +-------------------- +-- C_BCONST_REG_ADDR +-------------------- + when C_BCONST_REG_ADDR => + bconst_o <= pwdata_i(9 downto 0); + +-------------------- +-- C_SECOND_CONST_ADDR +-------------------- + when C_SECOND_CONST_ADDR => + second_const_o <= pwdata_i(19 downto 0); + +-------------------- +-- C_STEP_OUT_ADDR +-------------------- + when C_STEP_OUT_ADDR => + step_o <= pwdata_i(7 downto 0); +-------------------- +-- C_MODE_OUT_ADDR +-------------------- + when C_MODE_OUT_ADDR => + mode_o <= pwdata_i(0); + +-------------------- +-- C_FRAME_TCOUNT_ADDR +-------------------- + when C_FRAME_TCOUNT_ADDR => + frame_tcount_o <= pwdata_i(3 downto 0); + +-------------------- +-- C_QUALITY_ADDR +-------------------- + when C_QUALITY_ADDR => + quality_o <= pwdata_i(7 downto 0); + +-------------------- +-- C_HORIZ_RESL_ADDR +-------------------- + when C_HORIZ_RESL_ADDR => + s_horiz_resl <= pwdata_i(15 downto 0); + +-------------------- +-- C_VERT_RESL_ADDR +-------------------- + when C_VERT_RESL_ADDR => + s_vert_resl <= pwdata_i(15 downto 0); +-------------------- +-- C_TEXT_COLOR_ADDR +-------------------- + when C_TEXT_COLOR_ADDR => + text_color_o <= pwdata_i(23 downto 0); + +-------------------- +-- C_TEXT_COORDI_ADDR +-------------------- + when C_TEXT_COORDI_ADDR => + text_coordinates_o <= pwdata_i(31 downto 0); + +-------------------- +-- C_DIGITS_ADDR +-------------------- + when C_DIGITS_ADDR => + disp_digits_o <= pwdata_i(11 downto 0); + +-------------------- +-- C_H264START_ADDR +-------------------- + when C_H264START_ADDR => + h264_en_o <= pwdata_i(0); + +-------------------- +-- C_H264DDRLSB_ADDR +-------------------- + when C_H264DDRLSB_ADDR => + h264_ddrlsb_addr_o <= pwdata_i; + +-------------------- +-- OTHERS +-------------------- + when others => + null; + end case; + end if; + end if; + end process; +-------------------------------------------------------------------------- +-- Name : DLY_PROC +-- Description: Process to delay the signals +-------------------------------------------------------------------------- + DLY_PROC : + process (preset_i, pclk_i) + begin + if(preset_i = '0')then + s_frame_valid_dly1 <= '0'; + horiz_resl_o <= x"0500" ; + vert_resl_o <= x"02D0" ; + elsif (pclk_i'event and pclk_i = '1') then + s_frame_valid_dly1 <= frame_valid_i; + if (s_frame_valid_re = '1') then + horiz_resl_o <= s_horiz_resl; + vert_resl_o <= s_vert_resl; + end if; + end if; + end process; +--================================================================================================= +-- Component Instantiations +--================================================================================================= +--NA-- + +end architecture apb3_if; diff --git a/script_support/hdl/H264/data_packer_h264.vhd b/script_support/hdl/H264/data_packer_h264.vhd index 393d90e..113a6eb 100644 --- a/script_support/hdl/H264/data_packer_h264.vhd +++ b/script_support/hdl/H264/data_packer_h264.vhd @@ -1,217 +1,220 @@ ---////////////////////////////////////////////////////////////////////////////// --- Copyright (c) 2022, Microchip Corporation --- All rights reserved. --- --- Redistribution and use in source and binary forms, with or without --- modification, are permitted provided that the following conditions are met: --- * Redistributions of source code must retain the above copyright --- notice, this list of conditions and the following disclaimer. --- * Redistributions in binary form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- * Neither the name of the nor the --- names of its contributors may be used to endorse or promote products --- derived from this software without specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND --- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED --- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE --- DISCLAIMED. IN NO EVENT SHALL MICROCHIP CORPORATIONM BE LIABLE FOR ANY --- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; --- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND --- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT --- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS --- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --- --- APACHE LICENSE --- Copyright (c) 2022, Microchip Corporation --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. ---////////////////////////////////////////////////////////////////////////////// - ---================================================================================================= --- Libraries ---================================================================================================= -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.NUMERIC_STD.all; -use IEEE.STD_LOGIC_UNSIGNED.all; -use IEEE.math_real."ceil"; -use IEEE.math_real."log2"; ---================================================================================================= --- data_packer_h264 entity declaration ---================================================================================================= -entity data_packer_h264 is - generic( --- Generic list - g_IP_DW : integer := 8; -- input data width should be powers of 2 - g_OP_DW : integer := 512 -- output data width - ); - port( --- Port list - -- System reset - reset_i : in std_logic; - - -- System clock - sys_clk_i : in std_logic; - - -- enable - data_valid_i : in std_logic; - - --Frame end input - frame_end_i : in std_logic; - - -- Data Input - data_i : in std_logic_vector(g_IP_DW-1 downto 0); - - -- Data Enable - data_valid_o : out std_logic; - - -- Data output - data_o : out std_logic_vector(g_OP_DW-1 downto 0) - - ); -end data_packer_h264; - ---================================================================================================= --- data_packer_h264 architecture body ---================================================================================================= - -architecture data_packer_h264 of data_packer_h264 is - ---================================================================================================= --- Component declarations ---================================================================================================= ---NA-- ---================================================================================================= --- Synthesis Attributes ---================================================================================================= ---NA-- ---================================================================================================= --- Signal declarations ---================================================================================================= - CONSTANT C_MC : INTEGER := g_OP_DW / g_IP_DW;--max count - CONSTANT C_CW : INTEGER := integer(ceil(log2(real(C_MC))));--counter width - CONSTANT C_MAX_WLEN : INTEGER := 32;--max burst length/ number of data valids - TYPE DATA_ARRAY IS ARRAY (0 to C_MC-1) OF STD_LOGIC_VECTOR(g_IP_DW-1 DOWNTO 0); - signal s_data_arr : DATA_ARRAY; - signal s_counter : std_logic_vector(C_CW-1 downto 0); -- input data count - signal s_data_pack : std_logic_vector(g_OP_DW-1 downto 0); - signal s_frame_end_sr : std_logic_vector(5 downto 0); - signal s_frame_end_re : std_logic; - signal s_frame_end_re_dly : std_logic; - signal s_buf_wr_done_dly1 : std_logic; - signal s_buf_wr_done_dly2 : std_logic; - signal s_data_valid_out : std_logic; - signal s_ones : std_logic_vector(C_CW-1 downto 0); - -begin - ---================================================================================================= --- Top level output port assignments ---================================================================================================= - data_o <= s_data_pack; - data_valid_o <= s_data_valid_out; ---================================================================================================= --- Generate blocks ---================================================================================================= --------------------------------------------------------------------------- --- Name : GENERATE_DATA_PACK --- Description: data packing --------------------------------------------------------------------------- -GENERATE_DATA_PACK: FOR I IN 0 TO C_MC-1 GENERATE - s_data_pack(g_IP_DW*(I+1)-1 DOWNTO g_IP_DW*I) <= s_data_arr(I); - DATA_PACK_PROC: - PROCESS(SYS_CLK_I,RESET_I) - BEGIN - IF (RESET_I = '0') THEN - s_data_arr(I) <= (OTHERS=>'0'); - ELSIF rising_edge(SYS_CLK_I) THEN - IF(data_valid_i = '1' AND s_counter = 0) THEN - IF (I > 0) THEN - s_data_arr(I) <= (OTHERS=>'0'); - ELSE - s_data_arr(I) <= data_i; - END IF; - ELSIF(data_valid_i = '1' AND s_counter = I) THEN - s_data_arr(I) <= data_i; - END IF; - END IF; - END PROCESS; -END GENERATE GENERATE_DATA_PACK; ---================================================================================================= --- Asynchronous blocks ---================================================================================================= - s_frame_end_re <= s_frame_end_sr(4) and not(s_frame_end_sr(5)); - s_ones <= (others => '1'); ---================================================================================================= --- Synchronous blocks ---================================================================================================= --------------------------------------------------------------------------- --- Name : DELAY --- Description: Process delays input signals --------------------------------------------------------------------------- - DELAY : - process(SYS_CLK_I, RESET_I) - begin - if RESET_I = '0' then - s_frame_end_sr <= (others => '0'); - s_frame_end_re_dly <= '0'; - elsif rising_edge(SYS_CLK_I) then - s_frame_end_sr <= s_frame_end_sr(4 downto 0) & frame_end_i; - s_frame_end_re_dly <= s_frame_end_re; - end if; - end process; - --------------------------------------------------------------------------- --- Name : DATA_COUNTER --- Description: Counter to count data --------------------------------------------------------------------------- - DATA_COUNTER : - process(SYS_CLK_I, RESET_I) - begin - if RESET_I = '0' then - s_counter <= (others => '0'); - elsif rising_edge(SYS_CLK_I) then - if(data_valid_i = '1')then - s_counter <= s_counter + '1'; - elsif (s_frame_end_re = '1') then - s_counter <= (others => '0'); - end if; - end if; - end process; - --------------------------------------------------------------------------- --- Name : DATA_VALID --- Description: Process to generate data valid output --------------------------------------------------------------------------- - DATA_VALID : - process(SYS_CLK_I, RESET_I) - begin - if RESET_I = '0' then - s_data_valid_out <= '0'; - elsif rising_edge(SYS_CLK_I) then - if ((data_valid_i = '1' AND s_counter = s_ones) OR - (s_frame_end_re = '1' AND s_counter /= 0)) then - s_data_valid_out <= '1'; - else - s_data_valid_out <= '0'; - end if; - end if; - end process; ---================================================================================================= --- Component Instantiations ---================================================================================================= ---NA-- -end data_packer_h264; +--////////////////////////////////////////////////////////////////////////////// +-- Copyright (c) 2022, Microchip Corporation +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- * Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- * Redistributions in binary form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- * Neither the name of the nor the +-- names of its contributors may be used to endorse or promote products +-- derived from this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL MICROCHIP CORPORATIONM BE LIABLE FOR ANY +-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- APACHE LICENSE +-- Copyright (c) 2022, Microchip Corporation +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +--////////////////////////////////////////////////////////////////////////////// + +--================================================================================================= +-- Libraries +--================================================================================================= +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use IEEE.STD_LOGIC_UNSIGNED.all; +use IEEE.math_real."ceil"; +use IEEE.math_real."log2"; +--================================================================================================= +-- data_packer_h264 entity declaration +--================================================================================================= +entity data_packer_h264 is + generic( +-- Generic list + g_IP_DW : integer := 16; -- input data width should be powers of 2 + g_OP_DW : integer := 512 -- output data width + ); + port( +-- Port list + -- System reset + reset_i : in std_logic; + + -- System clock + sys_clk_i : in std_logic; + + -- enable + data_valid_i : in std_logic; + + --Frame end input + frame_end_i : in std_logic; + + -- Data Input + data_i : in std_logic_vector(g_IP_DW-1 downto 0); + + -- Data Enable + data_valid_o : out std_logic; + -- Frame end output + frame_end_o : out std_logic; + + -- Data output + data_o : out std_logic_vector(g_OP_DW-1 downto 0) + + ); +end data_packer_h264; + +--================================================================================================= +-- data_packer_h264 architecture body +--================================================================================================= + +architecture data_packer_h264 of data_packer_h264 is + +--================================================================================================= +-- Component declarations +--================================================================================================= +--NA-- +--================================================================================================= +-- Synthesis Attributes +--================================================================================================= +--NA-- +--================================================================================================= +-- Signal declarations +--================================================================================================= + CONSTANT C_MC : INTEGER := g_OP_DW / g_IP_DW;--max count + CONSTANT C_CW : INTEGER := integer(ceil(log2(real(C_MC))));--counter width + CONSTANT C_MAX_WLEN : INTEGER := 32;--max burst length/ number of data valids + TYPE DATA_ARRAY IS ARRAY (0 to C_MC-1) OF STD_LOGIC_VECTOR(g_IP_DW-1 DOWNTO 0); + signal s_data_arr : DATA_ARRAY; + signal s_counter : std_logic_vector(C_CW-1 downto 0); -- input data count + signal s_data_pack : std_logic_vector(g_OP_DW-1 downto 0); + signal s_frame_end_sr : std_logic_vector(15 downto 0); + signal s_frame_end_re : std_logic; + signal s_frame_end_re_dly : std_logic; + signal s_buf_wr_done_dly1 : std_logic; + signal s_buf_wr_done_dly2 : std_logic; + signal s_data_valid_out : std_logic; + signal s_ones : std_logic_vector(C_CW-1 downto 0); + +begin + +--================================================================================================= +-- Top level output port assignments +--================================================================================================= + data_o <= s_data_pack; + data_valid_o <= s_data_valid_out; + frame_end_o <= s_frame_end_re_dly; +--================================================================================================= +-- Generate blocks +--================================================================================================= +-------------------------------------------------------------------------- +-- Name : GENERATE_DATA_PACK +-- Description: data packing +-------------------------------------------------------------------------- +GENERATE_DATA_PACK: FOR I IN 0 TO C_MC-1 GENERATE + s_data_pack(g_IP_DW*(I+1)-1 DOWNTO g_IP_DW*I) <= s_data_arr(I); + DATA_PACK_PROC: + PROCESS(SYS_CLK_I,RESET_I) + BEGIN + IF (RESET_I = '0') THEN + s_data_arr(I) <= (OTHERS=>'0'); + ELSIF rising_edge(SYS_CLK_I) THEN + IF(data_valid_i = '1' AND s_counter = 0) THEN + IF (I > 0) THEN + s_data_arr(I) <= (OTHERS=>'0'); + ELSE + s_data_arr(I) <= data_i; + END IF; + ELSIF(data_valid_i = '1' AND s_counter = I) THEN + s_data_arr(I) <= data_i; + END IF; + END IF; + END PROCESS; +END GENERATE GENERATE_DATA_PACK; +--================================================================================================= +-- Asynchronous blocks +--================================================================================================= + s_frame_end_re <= s_frame_end_sr(14) and not(s_frame_end_sr(15)); + s_ones <= (others => '1'); +--================================================================================================= +-- Synchronous blocks +--================================================================================================= +-------------------------------------------------------------------------- +-- Name : DELAY +-- Description: Process delays input signals +-------------------------------------------------------------------------- + DELAY : + process(SYS_CLK_I, RESET_I) + begin + if RESET_I = '0' then + s_frame_end_sr <= (others => '0'); + s_frame_end_re_dly <= '0'; + elsif rising_edge(SYS_CLK_I) then + s_frame_end_sr <= s_frame_end_sr(14 downto 0) & frame_end_i; + s_frame_end_re_dly <= s_frame_end_re; + end if; + end process; + +-------------------------------------------------------------------------- +-- Name : DATA_COUNTER +-- Description: Counter to count data +-------------------------------------------------------------------------- + DATA_COUNTER : + process(SYS_CLK_I, RESET_I) + begin + if RESET_I = '0' then + s_counter <= (others => '0'); + elsif rising_edge(SYS_CLK_I) then + if(data_valid_i = '1')then + s_counter <= s_counter + '1'; + elsif (s_frame_end_re = '1') then + s_counter <= (others => '0'); + end if; + end if; + end process; + +-------------------------------------------------------------------------- +-- Name : DATA_VALID +-- Description: Process to generate data valid output +-------------------------------------------------------------------------- + DATA_VALID : + process(SYS_CLK_I, RESET_I) + begin + if RESET_I = '0' then + s_data_valid_out <= '0'; + elsif rising_edge(SYS_CLK_I) then + if ((data_valid_i = '1' AND s_counter = s_ones) OR + (s_frame_end_re = '1' AND s_counter /= 0)) then + s_data_valid_out <= '1'; + else + s_data_valid_out <= '0'; + end if; + end if; + end process; +--================================================================================================= +-- Component Instantiations +--================================================================================================= +--NA-- +end data_packer_h264; diff --git a/script_support/hdl/ddr_write_controller_enc.v b/script_support/hdl/ddr_write_controller_enc.v index 583b1fc..8aba8ce 100644 --- a/script_support/hdl/ddr_write_controller_enc.v +++ b/script_support/hdl/ddr_write_controller_enc.v @@ -1,243 +1,281 @@ -//////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 2022, Microchip Corporation -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// * Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// * Neither the name of the nor the -// names of its contributors may be used to endorse or promote products -// derived from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -// DISCLAIMED. IN NO EVENT SHALL MICROCHIP CORPORATIONM BE LIABLE FOR ANY -// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// APACHE LICENSE -// Copyright (c) 2022, Microchip Corporation -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -//////////////////////////////////////////////////////////////////////////////// - -module ddr_write_controller_enc #(parameter g_DDR_AXI_AWIDTH = 32) ( - input reset_i, //System Reset - input sys_clk_i, // System clock - input wrclk_reset_i, //Write clock reset - input wrclk_i, //Write clock - input [11:0] fifo_count_i, //Fifo count - input eof_i, //End of Frame - - //from apb wrapper - input encoder_en_i, //enable or start - input clr_intr_i, //clear interrupt from apb - - input write_ackn_i, //Write Acknowledgement - input write_done_i, //Write Done - input [9:0] frame_ddr_addr_i, //Frame address to write - output fifo_reset_o, //fifo reset - - output wire read_fifo_o, //Read Request to FIFO - output wire frm_interrupt_o,//interrupt to MSS - - //to apb wrapper - output wire [1:0] frame_idx_o, //frame index - output wire [31:0] frame_size_o, //Frame Size - - //to arbiter - output wire write_req_o, //Write Request to DDR - output wire [g_DDR_AXI_AWIDTH-1:0] write_start_addr_o, //DDR memory address to write data - output wire [7:0] write_length_o //Write Burst size - - ); - - localparam IDLE = 2'b00, - WRITE_REQUESTING = 2'b01, - WRITING = 2'b10; - - reg [1:0] s_state; - reg s_eof_wrclk; - reg [9:0] s_eof_sync_reg; - reg s_eof_reg; - wire s_set_eof_reg; - reg s_clr_eof_reg; - reg s_write_req; - reg s_read_fifo; - wire[g_DDR_AXI_AWIDTH-1:0] s_write_start_addr; - reg [8:0] s_counter; - reg [8:0] s_count_max; - reg [19:0] s_line_counter; - reg s_frm_intr; - reg [1:0] s_clr_intr_r;//double flop - reg [1:0] s_frame_index; - wire[1:0] s_disp_frame_index; - reg s_last_data_in_frame; - reg [31:0] s_frame_size; - reg [31:0] s_frame_size_out; - reg encoder_en_dly1; - -assign write_req_o = s_write_req; -assign write_start_addr_o = s_write_start_addr; -assign write_length_o = s_count_max - 1'b1; -assign read_fifo_o = s_read_fifo; -assign frame_size_o = s_frame_size_out ; -assign frame_idx_o = s_disp_frame_index; -assign frm_interrupt_o = s_frm_intr; -assign fifo_reset_o = ~(encoder_en_i & (~ encoder_en_dly1)); -assign s_disp_frame_index = s_frame_index - 1'b1 ; -assign s_write_start_addr = {frame_ddr_addr_i[9:0], s_frame_index, s_line_counter}; -assign s_set_eof_reg = s_eof_sync_reg[9] & (~s_eof_sync_reg[8]) ; //neg edge - -/*------------------------------------------------------------------------ --- Name : EOF_SYNC --- Description: Process to delay signal and find rising edge -------------------------------------------------------------------------*/ - always @( posedge wrclk_i or negedge wrclk_reset_i) - begin - if (!wrclk_reset_i) - s_eof_wrclk <= 1'b0; - else - s_eof_wrclk <= eof_i; - end -/*------------------------------------------------------------------------ --- Name : INTR_GEN --- Description: Process to generate and clear interrupt -------------------------------------------------------------------------*/ - always @ (posedge sys_clk_i or negedge reset_i) - begin - if (!reset_i) begin - s_frm_intr <= 1'b0; - end - else begin - if (s_clr_eof_reg && encoder_en_i) begin - if (s_frame_size != 0) - s_frm_intr <= 1'b1; - end - else if (s_clr_intr_r[1]) begin - s_frm_intr <= 1'b0; - end - end - end -/*------------------------------------------------------------------------ --- Name : SIGNAL_DELAY --- Description: Process to delay signal and find rising edge -------------------------------------------------------------------------*/ - always @ (posedge sys_clk_i or negedge reset_i) - begin - if (!reset_i) begin - s_eof_sync_reg <= 0 ; - s_eof_reg <= 1'b0 ; - encoder_en_dly1 <= 1'b0 ; - s_clr_intr_r <= 0; - end - else begin - s_eof_sync_reg <= {s_eof_sync_reg[8:0], s_eof_wrclk | eof_i} ; - encoder_en_dly1 <= encoder_en_i; - s_clr_intr_r <= {s_clr_intr_r[0],clr_intr_i}; - - if (s_set_eof_reg) s_eof_reg <= 1'b1; - else if (s_clr_eof_reg) s_eof_reg <= 1'b0; - end - end - -/*------------------------------------------------------------------------ --- Name : Write_FSM_PROC --- Description: FSM implements Write operations -------------------------------------------------------------------------*/ - always @ (posedge sys_clk_i or negedge reset_i) - begin - if (!reset_i) begin - s_state <= IDLE; - s_write_req <= 1'b0; - s_read_fifo <= 1'b0; - s_count_max <= 0 ; - s_counter <= 0 ; - s_frame_index <= 2'd0 ; - s_line_counter <= 20'd0 ; - s_last_data_in_frame <= 1'b0 ; - s_clr_eof_reg <= 1'b0; - s_frame_size <= 32'd0 ; - s_frame_size_out <= 32'd0 ; - end - else begin - case({s_state}) - IDLE : begin - s_write_req <= 1'b0 ; - s_read_fifo <= 1'b0 ; - s_counter <= 0 ; - s_clr_eof_reg <= s_eof_reg & (fifo_count_i == 0) & (~s_clr_eof_reg) ; - - if (s_clr_eof_reg && encoder_en_i) begin - s_frame_index <= s_frame_index + 1'b1 ; - s_frame_size_out <= s_frame_size ; - s_frame_size <= 0 ; - s_line_counter <= 0 ; - end - else if (encoder_en_i == 0) begin - s_frame_size <= 0 ; - s_frame_size_out <= 0 ; - s_line_counter <= 0 ; - s_frame_index <= 0 ; - end - - if (!s_clr_eof_reg && ((s_eof_reg && (|fifo_count_i)) || (|fifo_count_i[11:4]))) begin - if (fifo_count_i > 256) - s_count_max <= 9'd256 ; //max 256 burst length - else - s_count_max <= fifo_count_i[8:0] ; - s_state <= WRITE_REQUESTING ; - s_last_data_in_frame <= s_eof_reg ; - end - end - WRITE_REQUESTING : begin - if(write_ackn_i) begin - s_write_req <= 1'b0; - s_state <= WRITING; - end - else begin - s_write_req <= 1'b1 ; - end - end - WRITING : begin - if(write_done_i) begin - s_read_fifo <= 1'b0; - s_state <= IDLE; - s_clr_eof_reg <= s_last_data_in_frame; - s_line_counter <= s_line_counter + {s_count_max, 3'b000} ; - s_frame_size <= s_frame_size + {s_count_max, 3'b000} ; - end - else if(s_counter >= s_count_max) begin - s_read_fifo <= 1'b0; - end - else begin - s_counter <= s_counter + 1'b1; - s_read_fifo <= 1'b1; - end - end - default : s_state <= IDLE; - endcase - end -end - -endmodule - +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2022, Microchip Corporation +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// * Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// * Neither the name of the nor the +// names of its contributors may be used to endorse or promote products +// derived from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL MICROCHIP CORPORATIONM BE LIABLE FOR ANY +// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// APACHE LICENSE +// Copyright (c) 2022, Microchip Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//////////////////////////////////////////////////////////////////////////////// + +module ddr_write_controller_enc #(parameter g_DDR_AXI_AWIDTH = 32) ( + input reset_i, //System Reset + input sys_clk_i, // System clock + input wrclk_reset_i, //Write clock reset + input wrclk_i, //Write clock + input pclk_i, //APB clock for frame size and index + input [11:0] fifo_count_i, //Fifo count + input eof_i, //End of Frame + + //from apb wrapper + input encoder_en_i, //enable or start + input clr_intr_i, //clear interrupt from apb + + input write_ackn_i, //Write Acknowledgement + input write_done_i, //Write Done + input [9:0] frame_ddr_addr_i, //Frame address to write + output fifo_reset_o, //fifo reset + + output wire read_fifo_o, //Read Request to FIFO + output wire frm_interrupt_o,//interrupt to MSS + + //to apb wrapper + output reg [1:0] frame_idx_o, //frame index + output reg [31:0] frame_size_o, //Frame Size + + //to arbiter + output wire write_req_o, //Write Request to DDR + output wire [g_DDR_AXI_AWIDTH-1:0] write_start_addr_o, //DDR memory address to write data + output wire [7:0] write_length_o //Write Burst size + + ); + + localparam IDLE = 2'b00, + WRITE_REQUESTING = 2'b01, + WRITING = 2'b10; + + reg [1:0] s_state; + reg s_eof_wrclk; + reg [9:0] s_eof_sync_reg; + reg s_eof_reg; + wire s_set_eof_reg; + reg s_clr_eof_reg; + reg s_write_req; + reg s_read_fifo; + wire[g_DDR_AXI_AWIDTH-1:0] s_write_start_addr; + reg [8:0] s_counter; + reg [8:0] s_count_max; + reg [19:0] s_line_counter; + reg s_frm_intr; + reg [1:0] s_clr_intr_r;//double flop + reg [1:0] s_frame_index; + wire[1:0] s_disp_frame_index; + reg s_last_data_in_frame; + reg [31:0] s_frame_size; + reg [31:0] s_frame_size_out; + reg encoder_en_dly1; + reg [3:0] s_clr_eof_cnt; + reg frm_sz_vld; + +assign write_req_o = s_write_req; +assign write_start_addr_o = s_write_start_addr; +assign write_length_o = s_count_max - 1'b1; +assign read_fifo_o = s_read_fifo; +assign frm_interrupt_o = s_frm_intr; +assign fifo_reset_o = ~(encoder_en_i & (~ encoder_en_dly1)); +assign s_disp_frame_index = s_frame_index - 1'b1 ; +assign s_write_start_addr = {frame_ddr_addr_i[9:0], s_frame_index, s_line_counter}; +assign s_set_eof_reg = s_eof_sync_reg[9] & (~s_eof_sync_reg[8]) ; //neg edge + +/*------------------------------------------------------------------------ +-- Name : EOF_SYNC +-- Description: Process to delay signal and find rising edge +------------------------------------------------------------------------*/ + always @( posedge wrclk_i or negedge wrclk_reset_i) + begin + if (!wrclk_reset_i) + s_eof_wrclk <= 1'b0; + else + s_eof_wrclk <= eof_i; + end +/*------------------------------------------------------------------------ +-- Name : INTR_GEN +-- Description: Process to generate and clear interrupt +------------------------------------------------------------------------*/ + always @ (posedge sys_clk_i or negedge reset_i) + begin + if (!reset_i) begin + s_frm_intr <= 1'b0; + end + else begin + if (s_clr_eof_reg && encoder_en_i) begin + if (s_frame_size != 0) + s_frm_intr <= 1'b1; + end + else if (s_clr_intr_r[1]) begin + s_frm_intr <= 1'b0; + end + end + end +/*------------------------------------------------------------------------ +-- Name : SIGNAL_DELAY +-- Description: Process to delay signal and find rising edge +------------------------------------------------------------------------*/ + always @ (posedge sys_clk_i or negedge reset_i) + begin + if (!reset_i) begin + s_eof_sync_reg <= 0 ; + s_eof_reg <= 1'b0 ; + encoder_en_dly1 <= 1'b0 ; + s_clr_intr_r <= 0; + end + else begin + s_eof_sync_reg <= {s_eof_sync_reg[8:0], s_eof_wrclk | eof_i} ; + encoder_en_dly1 <= encoder_en_i; + s_clr_intr_r <= {s_clr_intr_r[0],clr_intr_i}; + + if (s_set_eof_reg) s_eof_reg <= 1'b1; + else if (s_clr_eof_reg) s_eof_reg <= 1'b0; + end + end + +/*------------------------------------------------------------------------ +-- Name : Write_FSM_PROC +-- Description: FSM implements Write operations +------------------------------------------------------------------------*/ + always @ (posedge sys_clk_i or negedge reset_i) + begin + if (!reset_i) begin + s_state <= IDLE; + s_write_req <= 1'b0; + s_read_fifo <= 1'b0; + s_count_max <= 0 ; + s_counter <= 0 ; + s_frame_index <= 2'd0 ; + s_line_counter <= 20'd0 ; + s_last_data_in_frame <= 1'b0 ; + s_clr_eof_reg <= 1'b0; + s_frame_size <= 32'd0 ; + s_frame_size_out <= 32'd0 ; + end + else begin + case({s_state}) + IDLE : begin + s_write_req <= 1'b0 ; + s_read_fifo <= 1'b0 ; + s_counter <= 0 ; + s_clr_eof_reg <= s_eof_reg & (fifo_count_i == 0) & (~s_clr_eof_reg) ; + + if (s_clr_eof_reg && encoder_en_i) begin + s_frame_index <= s_frame_index + 1'b1 ; + s_frame_size_out <= s_frame_size ; + s_frame_size <= 0 ; + s_line_counter <= 0 ; + end + else if (encoder_en_i == 0) begin + s_frame_size <= 0 ; + s_frame_size_out <= 0 ; + s_line_counter <= 0 ; + s_frame_index <= 0 ; + end + + if (!s_clr_eof_reg && ((s_eof_reg && (|fifo_count_i)) || (|fifo_count_i[11:4]))) begin + if (fifo_count_i > 256) + s_count_max <= 9'd256 ; //max 256 burst length + else + s_count_max <= fifo_count_i[8:0] ; + s_state <= WRITE_REQUESTING ; + s_last_data_in_frame <= s_eof_reg ; + end + end + WRITE_REQUESTING : begin + if(write_ackn_i) begin + s_write_req <= 1'b0; + s_state <= WRITING; + end + else begin + s_write_req <= 1'b1 ; + end + end + WRITING : begin + if(write_done_i) begin + s_read_fifo <= 1'b0; + s_state <= IDLE; + s_clr_eof_reg <= s_last_data_in_frame; + s_line_counter <= s_line_counter + {s_count_max, 3'b000} ; + s_frame_size <= s_frame_size + {s_count_max, 3'b000} ; + end + else if(s_counter >= s_count_max) begin + s_read_fifo <= 1'b0; + end + else begin + s_counter <= s_counter + 1'b1; + s_read_fifo <= 1'b1; + end + end + default : s_state <= IDLE; + endcase + end +end + +/*------------------------------------------------------------------------ +-- Name : s_clr_eof_cnt +-- Description: frm sz valid +------------------------------------------------------------------------*/ + always @ (posedge sys_clk_i or negedge reset_i) + begin + if (!reset_i) begin + s_clr_eof_cnt <= 0; + frm_sz_vld <= 0; + end + else begin + if (s_clr_eof_reg) + s_clr_eof_cnt <= 1; + else if (s_clr_eof_cnt != 0) + s_clr_eof_cnt <= s_clr_eof_cnt + 1; + + if (s_clr_eof_cnt > 3) + frm_sz_vld <= 1; + else + frm_sz_vld <= 0; + end + end +/*------------------------------------------------------------------------ +-- Name : cdc_pclk +-- Description: frm sz to APB +------------------------------------------------------------------------*/ + always @ (posedge pclk_i or negedge reset_i) + begin + if (!reset_i) begin + frame_size_o <= 0; + frame_idx_o <= 0; + end + else if (frm_sz_vld) begin + frame_size_o <= s_frame_size_out ; + frame_idx_o <= s_disp_frame_index; + end + end +endmodule + diff --git a/script_support/hdl/frame_controls_gen.v b/script_support/hdl/frame_controls_gen.v index bbe9931..3d209b4 100644 --- a/script_support/hdl/frame_controls_gen.v +++ b/script_support/hdl/frame_controls_gen.v @@ -1,182 +1,182 @@ -//////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 2022, Microchip Corporation -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// * Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// * Neither the name of the nor the -// names of its contributors may be used to endorse or promote products -// derived from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -// DISCLAIMED. IN NO EVENT SHALL MICROCHIP CORPORATIONM BE LIABLE FOR ANY -// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// APACHE LICENSE -// Copyright (c) 2022, Microchip Corporation -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -//////////////////////////////////////////////////////////////////////////////// -`timescale 1ns/1ps -module frame_controls_gen - ( - input sys_clk_i, - input resetn_i, - input encoder_en_i, //from MSS GPIO - input frame_start_i, - input [15:0] hres_i, - input [15:0] vres_i, - input data_valid_i, - input [7:0] data_r_i, - input [7:0] data_g_i, - input [7:0] data_b_i, - output reg data_valid_r1_o, //registering for scaler to RBG2YCB timing - output reg [7:0] data_r_r1_o, - output reg [7:0] data_g_r1_o, - output reg [7:0] data_b_r1_o, - output frame_start_r1_o, //to reset scaler IP - output reg [15:0] h_scale_factor_o, - output reg [15:0] v_scale_factor_o, - output reg encoder_en_o, - output reg frame_start_encoder_o, - output eof_encoder_o - ); - -/************************************************************************ - Local parameters -*************************************************************************/ - -/************************************************************************ - Register/Wire Declarations -*************************************************************************/ -reg [15:0] hres_eof; -reg [15:0] vres_eof; -reg res_change; -reg [19:0] frame_start_sr; -wire frame_start_re; -/************************************************************************ - Module Instantiations -*************************************************************************/ - -/************************************************************************ - Top level output port assignments - delay1 eof_encoder_o - delay4 encoder_en_o - delay18 frame_start_encoder_o -*************************************************************************/ -assign frame_start_r1_o = frame_start_sr[0]; -assign eof_encoder_o = (frame_start_sr[0] | frame_start_sr[1]) & encoder_en_o; -assign frame_start_encoder_o = frame_start_sr[19] | frame_start_sr[18]; -/************************************************************************ - Internal assignments -*************************************************************************/ -assign frame_start_re = frame_start_sr[0] & (~frame_start_i); -/************************************************************************ - latch encoder en on frame start -*************************************************************************/ -always@(posedge sys_clk_i, negedge resetn_i) - if (~resetn_i) - encoder_en_o <= 0; - else if (res_change && frame_start_sr[2]) //to regenerate sps&pps - encoder_en_o <= 0; - else if ( frame_start_sr[3] & (~frame_start_sr[4]) ) - encoder_en_o <= encoder_en_i; -/************************************************************************ - H scale factors 1920x1072 , 1280x720, 960x544, 640x480 and 432x240 -*************************************************************************/ -always@(posedge sys_clk_i, negedge resetn_i) - if (!resetn_i) - h_scale_factor_o <= 1535; - else if (frame_start_i) - if (hres_i == 1920) - h_scale_factor_o <= 1023; - else if (hres_i == 1280) - h_scale_factor_o <= 1535; - else if (hres_i == 960) - h_scale_factor_o <= 2046; - else if (hres_i == 640) - h_scale_factor_o <= 3070; - else //432 - h_scale_factor_o <= 4548; - -/************************************************************************ - V scale factors -*************************************************************************/ -always@(posedge sys_clk_i, negedge resetn_i) - if (!resetn_i) - v_scale_factor_o <= 1534; - else if (frame_start_i) - if (vres_i == 1072) - v_scale_factor_o <= 1030; - else if (vres_i == 720) - v_scale_factor_o <= 1534; - else if (vres_i == 544) - v_scale_factor_o <= 2031; - else if (vres_i == 480) - v_scale_factor_o <= 2031; - else //240 - v_scale_factor_o <= 4603; - -/************************************************************************ - Process to register on frame start -*************************************************************************/ -always@(posedge sys_clk_i, negedge resetn_i) - if (!resetn_i) - begin - hres_eof <= 1280; - vres_eof <= 720; - res_change <= 1'b0; - end - else if (frame_start_i) - begin - hres_eof <= hres_i; - vres_eof <= vres_i; - if ((hres_eof != hres_i) || (vres_eof != vres_i)) - res_change <= 1'b1; - else - res_change <= 1'b0; - end -/************************************************************************ - Process to register signals -*************************************************************************/ -always@(posedge sys_clk_i, negedge resetn_i) - if (!resetn_i) - begin - frame_start_sr <= 0; - data_valid_r1_o <= 0; - data_r_r1_o <= 0; - data_g_r1_o <= 0; - data_b_r1_o <= 0; - end - else - begin - frame_start_sr <= {frame_start_sr[18:0],frame_start_i}; - data_valid_r1_o <= data_valid_i; - data_r_r1_o <= data_r_i; - data_g_r1_o <= data_g_i; - data_b_r1_o <= data_b_i; - end - +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2022, Microchip Corporation +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// * Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// * Neither the name of the nor the +// names of its contributors may be used to endorse or promote products +// derived from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL MICROCHIP CORPORATIONM BE LIABLE FOR ANY +// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// APACHE LICENSE +// Copyright (c) 2022, Microchip Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//////////////////////////////////////////////////////////////////////////////// +`timescale 1ns/1ps +module frame_controls_gen + ( + input sys_clk_i, + input resetn_i, + input encoder_en_i, //from MSS GPIO + input frame_start_i, + input [15:0] hres_i, + input [15:0] vres_i, + input data_valid_i, + input [7:0] data_r_i, + input [7:0] data_g_i, + input [7:0] data_b_i, + output reg data_valid_r1_o, //registering for scaler to RBG2YCB timing + output reg [7:0] data_r_r1_o, + output reg [7:0] data_g_r1_o, + output reg [7:0] data_b_r1_o, + output frame_start_r1_o, //to reset scaler IP + output reg [15:0] h_scale_factor_o, + output reg [15:0] v_scale_factor_o, + output reg encoder_en_o, + output reg frame_start_encoder_o, + output eof_encoder_o + ); + +/************************************************************************ + Local parameters +*************************************************************************/ + +/************************************************************************ + Register/Wire Declarations +*************************************************************************/ +reg [15:0] hres_eof; +reg [15:0] vres_eof; +reg res_change; +reg [19:0] frame_start_sr; +wire frame_start_re; +/************************************************************************ + Module Instantiations +*************************************************************************/ + +/************************************************************************ + Top level output port assignments + delay1 eof_encoder_o + delay4 encoder_en_o + delay18 frame_start_encoder_o +*************************************************************************/ +assign frame_start_r1_o = frame_start_sr[0]; +assign eof_encoder_o = (frame_start_sr[0] | frame_start_sr[1]) & encoder_en_o; +assign frame_start_encoder_o = frame_start_sr[19] | frame_start_sr[18]; +/************************************************************************ + Internal assignments +*************************************************************************/ +assign frame_start_re = frame_start_sr[0] & (~frame_start_i); +/************************************************************************ + latch encoder en on frame start +*************************************************************************/ +always@(posedge sys_clk_i, negedge resetn_i) + if (~resetn_i) + encoder_en_o <= 0; + else if (res_change && frame_start_sr[2]) //to regenerate sps&pps + encoder_en_o <= 0; + else if ( frame_start_sr[3] & (~frame_start_sr[4]) ) + encoder_en_o <= encoder_en_i; +/************************************************************************ + H scale factors 1920x1072 , 1280x720, 960x544, 640x480 and 432x240 +*************************************************************************/ +always@(posedge sys_clk_i, negedge resetn_i) + if (!resetn_i) + h_scale_factor_o <= 1535; + else if (frame_start_i) + if (hres_i == 1920) + h_scale_factor_o <= 1023; + else if (hres_i == 1280) + h_scale_factor_o <= 1535; + else if (hres_i == 960) + h_scale_factor_o <= 2046; + else if (hres_i == 640) + h_scale_factor_o <= 3070; + else //432 + h_scale_factor_o <= 4548; + +/************************************************************************ + V scale factors +*************************************************************************/ +always@(posedge sys_clk_i, negedge resetn_i) + if (!resetn_i) + v_scale_factor_o <= 1534; + else if (frame_start_i) + if (vres_i == 1072) + v_scale_factor_o <= 1030; + else if (vres_i == 720) + v_scale_factor_o <= 1534; + else if (vres_i == 544) + v_scale_factor_o <= 2031; + else if (vres_i == 480) + v_scale_factor_o <= 2031; + else //240 + v_scale_factor_o <= 4603; + +/************************************************************************ + Process to register on frame start +*************************************************************************/ +always@(posedge sys_clk_i, negedge resetn_i) + if (!resetn_i) + begin + hres_eof <= 1280; + vres_eof <= 720; + res_change <= 1'b0; + end + else if (frame_start_i) + begin + hres_eof <= hres_i; + vres_eof <= vres_i; + if ((hres_eof != hres_i) || (vres_eof != vres_i)) + res_change <= 1'b1; + else + res_change <= 1'b0; + end +/************************************************************************ + Process to register signals +*************************************************************************/ +always@(posedge sys_clk_i, negedge resetn_i) + if (!resetn_i) + begin + frame_start_sr <= 0; + data_valid_r1_o <= 0; + data_r_r1_o <= 0; + data_g_r1_o <= 0; + data_b_r1_o <= 0; + end + else + begin + frame_start_sr <= {frame_start_sr[18:0],frame_start_i}; + data_valid_r1_o <= data_valid_i; + data_r_r1_o <= data_r_i; + data_g_r1_o <= data_g_i; + data_b_r1_o <= data_b_i; + end + endmodule \ No newline at end of file diff --git a/script_support/hdl/intensity_average.vhd b/script_support/hdl/intensity_average.vhd index 87a365d..4e636e7 100644 --- a/script_support/hdl/intensity_average.vhd +++ b/script_support/hdl/intensity_average.vhd @@ -1,120 +1,120 @@ ---////////////////////////////////////////////////////////////////////////////// --- Copyright (c) 2022, Microchip Corporation --- All rights reserved. --- --- Redistribution and use in source and binary forms, with or without --- modification, are permitted provided that the following conditions are met: --- * Redistributions of source code must retain the above copyright --- notice, this list of conditions and the following disclaimer. --- * Redistributions in binary form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- * Neither the name of the nor the --- names of its contributors may be used to endorse or promote products --- derived from this software without specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND --- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED --- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE --- DISCLAIMED. IN NO EVENT SHALL MICROCHIP CORPORATIONM BE LIABLE FOR ANY --- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; --- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND --- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT --- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS --- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --- --- APACHE LICENSE --- Copyright (c) 2022, Microchip Corporation --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. ---////////////////////////////////////////////////////////////////////////////// - -------------------------------------------------------------------------------- --- Library -------------------------------------------------------------------------------- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_UNSIGNED.all; - -------------------------------------------------------------------------------- --- intensity average entity declaration -------------------------------------------------------------------------------- -entity intensity_average is - port ( - RESETN_I : in std_logic; - SYS_CLK_I : in std_logic; - data_valid_i : in std_logic; - frame_end_i : in std_logic; - r_i : in std_logic_vector(7 downto 0); - g_i : in std_logic_vector(7 downto 0); - b_i : in std_logic_vector(7 downto 0); - y_o : out std_logic_vector(31 downto 0) - ); -end intensity_average; - - -------------------------------------------------------------------------------- --- intensity_average architecture body -------------------------------------------------------------------------------- -architecture architecture_intensity_average of intensity_average is - - ----------------------------------------------------------------------------- - -- Signal declarations - ----------------------------------------------------------------------------- - signal s_sum_reg : std_logic_vector(31 downto 0); - signal s_sum_reg1 : std_logic_vector(31 downto 0); - signal s_frame_end : std_logic; - signal s_frame_end1 : std_logic; - signal s_frame_valid_re : std_logic; - -begin - - y_o <= s_sum_reg1; - s_frame_valid_re <= not (s_frame_end) and s_frame_end1; - - ----------------------------------------------------------------------------- - -- Storing frame end signal in two back to back DFF - ----------------------------------------------------------------------------- - process(SYS_CLK_I, RESETN_I) - begin - if (RESETN_I = '0') then - s_frame_end <= '0'; - s_frame_end1 <= '0'; - elsif rising_edge(SYS_CLK_I) then - s_frame_end <= frame_end_i; - s_frame_end1 <= s_frame_end; - end if; - end process; - ------------------------------------------------------------------------------ - - ----------------------------------------------------------------------------- - -- Adder process to add RGB inputs and store it in a register - ----------------------------------------------------------------------------- - process(SYS_CLK_I, RESETN_I) - begin - if (RESETN_I = '0') then - s_sum_reg <= (others => '0'); - s_sum_reg1 <= (others => '0'); - elsif rising_edge(SYS_CLK_I) then - if (s_frame_valid_re = '1') then - s_sum_reg <= (others => '0'); - s_sum_reg1 <= s_sum_reg; - elsif (data_valid_i = '1') then - s_sum_reg <= s_sum_reg + (x"000000" & '0' & r_i(7 downto 1)) + (x"000000" & g_i) + (x"000000" & "00" & b_i(7 downto 2)); end if; - end if; - end process; - ----------------------------------------------------------------------------- - -end architecture_intensity_average; - +--////////////////////////////////////////////////////////////////////////////// +-- Copyright (c) 2022, Microchip Corporation +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- * Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- * Redistributions in binary form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- * Neither the name of the nor the +-- names of its contributors may be used to endorse or promote products +-- derived from this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL MICROCHIP CORPORATIONM BE LIABLE FOR ANY +-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- APACHE LICENSE +-- Copyright (c) 2022, Microchip Corporation +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +--////////////////////////////////////////////////////////////////////////////// + +------------------------------------------------------------------------------- +-- Library +------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_UNSIGNED.all; + +------------------------------------------------------------------------------- +-- intensity average entity declaration +------------------------------------------------------------------------------- +entity intensity_average is + port ( + RESETN_I : in std_logic; + SYS_CLK_I : in std_logic; + data_valid_i : in std_logic; + frame_end_i : in std_logic; + r_i : in std_logic_vector(7 downto 0); + g_i : in std_logic_vector(7 downto 0); + b_i : in std_logic_vector(7 downto 0); + y_o : out std_logic_vector(31 downto 0) + ); +end intensity_average; + + +------------------------------------------------------------------------------- +-- intensity_average architecture body +------------------------------------------------------------------------------- +architecture architecture_intensity_average of intensity_average is + + ----------------------------------------------------------------------------- + -- Signal declarations + ----------------------------------------------------------------------------- + signal s_sum_reg : std_logic_vector(31 downto 0); + signal s_sum_reg1 : std_logic_vector(31 downto 0); + signal s_frame_end : std_logic; + signal s_frame_end1 : std_logic; + signal s_frame_valid_re : std_logic; + +begin + + y_o <= s_sum_reg1; + s_frame_valid_re <= not (s_frame_end) and s_frame_end1; + + ----------------------------------------------------------------------------- + -- Storing frame end signal in two back to back DFF + ----------------------------------------------------------------------------- + process(SYS_CLK_I, RESETN_I) + begin + if (RESETN_I = '0') then + s_frame_end <= '0'; + s_frame_end1 <= '0'; + elsif rising_edge(SYS_CLK_I) then + s_frame_end <= frame_end_i; + s_frame_end1 <= s_frame_end; + end if; + end process; + ------------------------------------------------------------------------------ + + ----------------------------------------------------------------------------- + -- Adder process to add RGB inputs and store it in a register + ----------------------------------------------------------------------------- + process(SYS_CLK_I, RESETN_I) + begin + if (RESETN_I = '0') then + s_sum_reg <= (others => '0'); + s_sum_reg1 <= (others => '0'); + elsif rising_edge(SYS_CLK_I) then + if (s_frame_valid_re = '1') then + s_sum_reg <= (others => '0'); + s_sum_reg1 <= s_sum_reg; + elsif (data_valid_i = '1') then + s_sum_reg <= s_sum_reg + (x"000000" & '0' & r_i(7 downto 1)) + (x"000000" & g_i) + (x"000000" & "00" & b_i(7 downto 2)); end if; + end if; + end process; + ----------------------------------------------------------------------------- + +end architecture_intensity_average; + diff --git a/script_support/hdl/ram2port.vhd b/script_support/hdl/ram2port.vhd index 515c62d..d111b89 100644 --- a/script_support/hdl/ram2port.vhd +++ b/script_support/hdl/ram2port.vhd @@ -1,95 +1,95 @@ ---////////////////////////////////////////////////////////////////////////////// --- Copyright (c) 2022, Microchip Corporation --- All rights reserved. --- --- Redistribution and use in source and binary forms, with or without --- modification, are permitted provided that the following conditions are met: --- * Redistributions of source code must retain the above copyright --- notice, this list of conditions and the following disclaimer. --- * Redistributions in binary form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- * Neither the name of the nor the --- names of its contributors may be used to endorse or promote products --- derived from this software without specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND --- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED --- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE --- DISCLAIMED. IN NO EVENT SHALL MICROCHIP CORPORATIONM BE LIABLE FOR ANY --- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; --- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND --- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT --- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS --- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --- --- APACHE LICENSE --- Copyright (c) 2022, Microchip Corporation --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. ---////////////////////////////////////////////////////////////////////////////// - -------------------------------------------------------------------------------- --- Library -------------------------------------------------------------------------------- -library ieee; -use ieee.STD_logic_1164.all; -use ieee.NUMERIc_std.all; -use IEEE.std_logic_unsigned.all; - -------------------------------------------------------------------------------- --- intensity average entity declaration -------------------------------------------------------------------------------- -entity ram2PORT is -generic (G_BUFF_AWIDTH: INTEGER := 10; -G_DWIDTH: integer := 64); port (WCLOck_i: in std_logic; -rclock_i: in STD_LOGIC; -WE_i: in STD_LOGIC; -rd_addr_i: in std_logic_vector(G_BUFF_AWIDTH-1 downto 0); -WR_ADDR_I: in std_loGIC_VECTOR(G_BUFF_AWIDTH-1 downto 0); -wr_data_i: in STD_logic_vector(G_DWIDTH-1 downto 0); -RD_DATA_O: out STD_LOGIC_VECtor(G_DWIDTH-1 downto 0)); -end RAM2port; - -architecture RAM2PORT of ram2port is - -type O0II is array ((2**g_buff_awidth)-1 downto 0) of sTD_LOGIC_VECTOR(g_dwidth-1 downto 0); - -signal l0ii: std_logiC_VECTOR(g_buff_awidth-1 downto 0); - -signal IO1L: o0ii; - -attribute SYN_RAMSTYLE: STRING; - -attribute syn_raMSTYLE of IO1L: signal is "lsram"; - -begin -rd_daTA_O <= IO1L(to_integer(UNSIGNED(l0ii))); -i0ii: -process (WCLock_i) -begin -if (RISING_EDGE(wclock_i)) then -if (WE_i = '1') then -IO1L(To_integer(UNSIGNED(wr_addr_i))) <= wr_data_i; -end if; -end if; -end process; -O1ii: -process (RCLOCK_I) -begin -if (rising_edge(RCLOCK_I)) then -L0II <= RD_addr_i; -end if; -end process; -end RAM2PORT; +--////////////////////////////////////////////////////////////////////////////// +-- Copyright (c) 2022, Microchip Corporation +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- * Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- * Redistributions in binary form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- * Neither the name of the nor the +-- names of its contributors may be used to endorse or promote products +-- derived from this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL MICROCHIP CORPORATIONM BE LIABLE FOR ANY +-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- APACHE LICENSE +-- Copyright (c) 2022, Microchip Corporation +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +--////////////////////////////////////////////////////////////////////////////// + +------------------------------------------------------------------------------- +-- Library +------------------------------------------------------------------------------- +library ieee; +use ieee.STD_logic_1164.all; +use ieee.NUMERIc_std.all; +use IEEE.std_logic_unsigned.all; + +------------------------------------------------------------------------------- +-- intensity average entity declaration +------------------------------------------------------------------------------- +entity ram2PORT is +generic (G_BUFF_AWIDTH: INTEGER := 10; +G_DWIDTH: integer := 64); port (WCLOck_i: in std_logic; +rclock_i: in STD_LOGIC; +WE_i: in STD_LOGIC; +rd_addr_i: in std_logic_vector(G_BUFF_AWIDTH-1 downto 0); +WR_ADDR_I: in std_loGIC_VECTOR(G_BUFF_AWIDTH-1 downto 0); +wr_data_i: in STD_logic_vector(G_DWIDTH-1 downto 0); +RD_DATA_O: out STD_LOGIC_VECtor(G_DWIDTH-1 downto 0)); +end RAM2port; + +architecture RAM2PORT of ram2port is + +type O0II is array ((2**g_buff_awidth)-1 downto 0) of sTD_LOGIC_VECTOR(g_dwidth-1 downto 0); + +signal l0ii: std_logiC_VECTOR(g_buff_awidth-1 downto 0); + +signal IO1L: o0ii; + +attribute SYN_RAMSTYLE: STRING; + +attribute syn_raMSTYLE of IO1L: signal is "lsram"; + +begin +rd_daTA_O <= IO1L(to_integer(UNSIGNED(l0ii))); +i0ii: +process (WCLock_i) +begin +if (RISING_EDGE(wclock_i)) then +if (WE_i = '1') then +IO1L(To_integer(UNSIGNED(wr_addr_i))) <= wr_data_i; +end if; +end if; +end process; +O1ii: +process (RCLOCK_I) +begin +if (rising_edge(RCLOCK_I)) then +L0II <= RD_addr_i; +end if; +end process; +end RAM2PORT; diff --git a/script_support/hdl_source.tcl b/script_support/hdl_source.tcl index d46a513..f8ff234 100644 --- a/script_support/hdl_source.tcl +++ b/script_support/hdl_source.tcl @@ -1,9 +1,10 @@ -#Importing and Linking all the HDL source files used in the design -import_files -library work -hdl_source script_support/hdl/H264/apb_wrapper.vhd -import_files -library work -hdl_source script_support/hdl/H264/data_packer_h264.vhd -import_files -library work -hdl_source script_support/hdl/ddr_write_controller_enc.v -import_files -library work -hdl_source script_support/hdl/frame_controls_gen.v -import_files -library work -hdl_source script_support/hdl/intensity_average.vhd -import_files -library work -hdl_source script_support/hdl/ram2port.vhd -import_files -library work -hdl_source script_support/hdl/video_fifo.vhd - +#Importing and Linking all the HDL source files used in the design +import_files -library work -hdl_source script_support/hdl/H264/apb_wrapper.vhd +import_files -library work -hdl_source script_support/hdl/H264/data_packer_h264.vhd +import_files -library work -hdl_source script_support/hdl/ddr_write_controller_enc.v +import_files -library work -hdl_source script_support/hdl/frame_controls_gen.v +import_files -library work -hdl_source script_support/hdl/intensity_average.vhd +import_files -library work -hdl_source script_support/hdl/ram2port.vhd +import_files -library work -hdl_source script_support/hdl/video_fifo.vhd +import_files -library work -hdl_source script_support/hdl/CR_OSD.v +