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master/index.html

@@ -24,7 +24,8 @@ <h2 id="modules">Modules</h2>
 </td></tr><tr><td><a class="module" href="module.axi_cut.html">axi_cut</a></td><td><p>An AXI4 cut.</p>
 </td></tr><tr><td><a class="module" href="module.axi_cut_intf.html">axi_cut_intf</a></td><td></td></tr><tr><td><a class="module" href="module.axi_lite_cut_intf.html">axi_lite_cut_intf</a></td><td></td></tr><tr><td><a class="module" href="module.axi_delayer.html">axi_delayer</a></td><td><p>Synthesizable module that (randomly) delays AXI channels.</p>
 </td></tr><tr><td><a class="module" href="module.axi_delayer_intf.html">axi_delayer_intf</a></td><td></td></tr><tr><td><a class="module" href="module.axi_demux.html">axi_demux</a></td><td><p>Demultiplex one AXI4+ATOP slave port to multiple AXI4+ATOP master ports.</p>
-</td></tr><tr><td><a class="module" href="module.axi_demux_id_counters.html">axi_demux_id_counters</a></td><td></td></tr><tr><td><a class="module" href="module.axi_demux_intf.html">axi_demux_intf</a></td><td></td></tr><tr><td><a class="module" href="module.axi_dumper.html">axi_dumper</a></td><td><p>Simulation-Only dumper for AXI transactions</p>
+</td></tr><tr><td><a class="module" href="module.axi_demux_intf.html">axi_demux_intf</a></td><td></td></tr><tr><td><a class="module" href="module.axi_demux_simple.html">axi_demux_simple</a></td><td><p>Demultiplex one AXI4+ATOP slave port to multiple AXI4+ATOP master ports.</p>
+</td></tr><tr><td><a class="module" href="module.axi_demux_id_counters.html">axi_demux_id_counters</a></td><td></td></tr><tr><td><a class="module" href="module.axi_dumper.html">axi_dumper</a></td><td><p>Simulation-Only dumper for AXI transactions</p>
 </td></tr><tr><td><a class="module" href="module.axi_dumper_intf.html">axi_dumper_intf</a></td><td></td></tr><tr><td><a class="module" href="module.axi_dw_converter.html">axi_dw_converter</a></td><td></td></tr><tr><td><a class="module" href="module.axi_dw_converter_intf.html">axi_dw_converter_intf</a></td><td></td></tr><tr><td><a class="module" href="module.axi_dw_downsizer.html">axi_dw_downsizer</a></td><td></td></tr><tr><td><a class="module" href="module.axi_dw_upsizer.html">axi_dw_upsizer</a></td><td></td></tr><tr><td><a class="module" href="module.axi_err_slv.html">axi_err_slv</a></td><td></td></tr><tr><td><a class="module" href="module.axi_fifo.html">axi_fifo</a></td><td></td></tr><tr><td><a class="module" href="module.axi_fifo_intf.html">axi_fifo_intf</a></td><td></td></tr><tr><td><a class="module" href="module.axi_from_mem.html">axi_from_mem</a></td><td><p>Protocol adapter which translates memory requests to the AXI4 protocol.</p>
 </td></tr><tr><td><a class="module" href="module.axi_id_prepend.html">axi_id_prepend</a></td><td></td></tr><tr><td><a class="module" href="module.axi_id_remap.html">axi_id_remap</a></td><td><p>Remap AXI IDs from wide IDs at the slave port to narrower IDs at the master port.</p>
 </td></tr><tr><td><a class="module" href="module.axi_id_remap_table.html">axi_id_remap_table</a></td><td><p>Internal module of <a href="module.axi_id_remap"><code>axi_id_remap</code></a>: Table to remap input to output IDs.</p>

master/module.axi_demux.html

@@ -38,7 +38,6 @@ <h3 id="parameter.AxiIdWidth" class="impl"><code class="in-band">AxiIdWidth<span
 ></div><h3 id="parameter.SpillR" class="impl"><code class="in-band">SpillR<span class="type-annotation">: bit</span></code></h3><div class="docblock"
 ></div><h3 id="parameter.SelectWidth" class="impl"><code class="in-band">SelectWidth<span class="type-annotation">: int unsigned</span></code></h3><div class="docblock"
 ></div><h3 id="parameter.select_t" class="impl"><code class="in-band">select_t<span class="type-annotation">: type</span></code></h3><div class="docblock"
-></div><h3 id="parameter.IdCounterWidth" class="impl"><code class="in-band">IdCounterWidth<span class="type-annotation">: int unsigned</span></code></h3><div class="docblock"
 ></div><h2 id="ports" class="section-header"><a href="#ports">Ports</a></h2>
 <h3 id="port.clk_i" class="impl"><code class="in-band">clk_i<span class="type-annotation">: input  logic</span></code></h3><div class="docblock"
 ></div><h3 id="port.rst_ni" class="impl"><code class="in-band">rst_ni<span class="type-annotation">: input  logic</span></code></h3><div class="docblock"
@@ -49,21 +48,10 @@ <h3 id="port.clk_i" class="impl"><code class="in-band">clk_i<span class="type-an
 ></div><h3 id="port.slv_resp_o" class="impl"><code class="in-band">slv_resp_o<span class="type-annotation">: output axi_resp_t</span></code></h3><div class="docblock"
 ></div><h3 id="port.mst_reqs_o" class="impl"><code class="in-band">mst_reqs_o<span class="type-annotation">: output axi_req_t    [NoMstPorts-1:0]</span></code></h3><div class="docblock"
 ></div><h3 id="port.mst_resps_i" class="impl"><code class="in-band">mst_resps_i<span class="type-annotation">: input  axi_resp_t   [NoMstPorts-1:0]</span></code></h3><div class="docblock"
-></div><h2 id="types" class="section-header"><a href="#types">Types<a></h2>
-<table>
-<tr><td><a class="type" href="type.id_cnt_t.html">id_cnt_t</a></td><td></td></tr></table>
-<h2 id="signals" class="section-header"><a href="#signals">Signals</a></h2>
-<h3 id="signal.slv_aw_chan" class="impl"><code class="in-band">slv_aw_chan<span class="type-annotation">: aw_chan_t</span></code></h3><div class="docblock"
+></div><h2 id="signals" class="section-header"><a href="#signals">Signals</a></h2>
+<h3 id="signal.slv_req_cut" class="impl"><code class="in-band">slv_req_cut<span class="type-annotation">: axi_req_t</span></code></h3><div class="docblock"
+></div><h3 id="signal.slv_resp_cut" class="impl"><code class="in-band">slv_resp_cut<span class="type-annotation">: axi_resp_t</span></code></h3><div class="docblock"
 ></div><h3 id="signal.slv_aw_select" class="impl"><code class="in-band">slv_aw_select<span class="type-annotation">: select_t</span></code></h3><div class="docblock"
-></div><h3 id="signal.lookup_aw_select" class="impl"><code class="in-band">lookup_aw_select<span class="type-annotation">: select_t</span></code></h3><div class="docblock"
-></div><h3 id="signal.w_select" class="impl"><code class="in-band">w_select<span class="type-annotation">: select_t</span></code></h3><div class="docblock"
-></div><h3 id="signal.w_select_q" class="impl"><code class="in-band">w_select_q<span class="type-annotation">: select_t</span></code></h3><div class="docblock"
-></div><h3 id="signal.w_open" class="impl"><code class="in-band">w_open<span class="type-annotation">: id_cnt_t</span></code></h3><div class="docblock"
-></div><h3 id="signal.slv_w_chan" class="impl"><code class="in-band">slv_w_chan<span class="type-annotation">: w_chan_t</span></code></h3><div class="docblock"
-></div><h3 id="signal.slv_b_chan" class="impl"><code class="in-band">slv_b_chan<span class="type-annotation">: b_chan_t</span></code></h3><div class="docblock"
-></div><h3 id="signal.lookup_ar_select" class="impl"><code class="in-band">lookup_ar_select<span class="type-annotation">: select_t</span></code></h3><div class="docblock"
-></div><h3 id="signal.slv_r_chan" class="impl"><code class="in-band">slv_r_chan<span class="type-annotation">: r_chan_t</span></code></h3><div class="docblock"
-></div><h3 id="signal.slv_ar_chan" class="impl"><code class="in-band">slv_ar_chan<span class="type-annotation">: ar_chan_t</span></code></h3><div class="docblock"
 ></div><h3 id="signal.slv_ar_select" class="impl"><code class="in-band">slv_ar_select<span class="type-annotation">: select_t</span></code></h3><div class="docblock"
 ></div></section>
 </body>

master/module.axi_demux_simple.html

@@ -0,0 +1,53 @@
+<html>
+<link rel="stylesheet" type="text/css" href="static/rustdoc.css">
+<link rel="stylesheet" type="text/css" href="static/light.css">
+<link rel="stylesheet" type="text/css" href="static/svdoc.css">
+<body>
+<section id="main" class="content"><h1 class="fqn">Module <a class="module">axi_demux_simple</a></h1>
+<div class="docblock">
+<p>Demultiplex one AXI4+ATOP slave port to multiple AXI4+ATOP master ports.</p>
+<p>The AW and AR slave channels each have a <code>select</code> input to determine to which master port the
+current request is sent.  The <code>select</code> can, for example, be driven by an address decoding module
+to map address ranges to different AXI slaves.</p>
+<h2>Design overview</h2>
+<p><img src="module.axi_demux.png" alt="Block diagram" title="Block diagram" /></p>
+<p>Beats on the W channel are routed by demultiplexer according to the selection for the
+corresponding AW beat.  This relies on the AXI property that W bursts must be sent in the same
+order as AW beats and beats from different W bursts may not be interleaved.</p>
+<p>Beats on the B and R channel are multiplexed from the master ports to the slave port with
+a round-robin arbitration tree.</p>
+</div>
+<h2 id="parameters" class="section-header"><a href="#parameters">Parameters</a></h2>
+<h3 id="parameter.AxiIdWidth" class="impl"><code class="in-band">AxiIdWidth<span class="type-annotation">: int unsigned</span></code></h3><div class="docblock"
+></div><h3 id="parameter.AtopSupport" class="impl"><code class="in-band">AtopSupport<span class="type-annotation">: bit</span></code></h3><div class="docblock"
+></div><h3 id="parameter.axi_req_t" class="impl"><code class="in-band">axi_req_t<span class="type-annotation">: type</span></code></h3><div class="docblock"
+></div><h3 id="parameter.axi_resp_t" class="impl"><code class="in-band">axi_resp_t<span class="type-annotation">: type</span></code></h3><div class="docblock"
+></div><h3 id="parameter.NoMstPorts" class="impl"><code class="in-band">NoMstPorts<span class="type-annotation">: int unsigned</span></code></h3><div class="docblock"
+></div><h3 id="parameter.MaxTrans" class="impl"><code class="in-band">MaxTrans<span class="type-annotation">: int unsigned</span></code></h3><div class="docblock"
+></div><h3 id="parameter.AxiLookBits" class="impl"><code class="in-band">AxiLookBits<span class="type-annotation">: int unsigned</span></code></h3><div class="docblock"
+></div><h3 id="parameter.UniqueIds" class="impl"><code class="in-band">UniqueIds<span class="type-annotation">: bit</span></code></h3><div class="docblock"
+></div><h3 id="parameter.SelectWidth" class="impl"><code class="in-band">SelectWidth<span class="type-annotation">: int unsigned</span></code></h3><div class="docblock"
+></div><h3 id="parameter.select_t" class="impl"><code class="in-band">select_t<span class="type-annotation">: type</span></code></h3><div class="docblock"
+></div><h3 id="parameter.IdCounterWidth" class="impl"><code class="in-band">IdCounterWidth<span class="type-annotation">: int unsigned</span></code></h3><div class="docblock"
+></div><h2 id="ports" class="section-header"><a href="#ports">Ports</a></h2>
+<h3 id="port.clk_i" class="impl"><code class="in-band">clk_i<span class="type-annotation">: input  logic</span></code></h3><div class="docblock"
+></div><h3 id="port.rst_ni" class="impl"><code class="in-band">rst_ni<span class="type-annotation">: input  logic</span></code></h3><div class="docblock"
+></div><h3 id="port.test_i" class="impl"><code class="in-band">test_i<span class="type-annotation">: input  logic</span></code></h3><div class="docblock"
+></div><h3 id="port.slv_req_i" class="impl"><code class="in-band">slv_req_i<span class="type-annotation">: input  axi_req_t</span></code></h3><div class="docblock"
+></div><h3 id="port.slv_aw_select_i" class="impl"><code class="in-band">slv_aw_select_i<span class="type-annotation">: input  select_t</span></code></h3><div class="docblock"
+></div><h3 id="port.slv_ar_select_i" class="impl"><code class="in-band">slv_ar_select_i<span class="type-annotation">: input  select_t</span></code></h3><div class="docblock"
+></div><h3 id="port.slv_resp_o" class="impl"><code class="in-band">slv_resp_o<span class="type-annotation">: output axi_resp_t</span></code></h3><div class="docblock"
+></div><h3 id="port.mst_reqs_o" class="impl"><code class="in-band">mst_reqs_o<span class="type-annotation">: output axi_req_t    [NoMstPorts-1:0]</span></code></h3><div class="docblock"
+></div><h3 id="port.mst_resps_i" class="impl"><code class="in-band">mst_resps_i<span class="type-annotation">: input  axi_resp_t   [NoMstPorts-1:0]</span></code></h3><div class="docblock"
+></div><h2 id="types" class="section-header"><a href="#types">Types<a></h2>
+<table>
+<tr><td><a class="type" href="type.id_cnt_t.html">id_cnt_t</a></td><td></td></tr></table>
+<h2 id="signals" class="section-header"><a href="#signals">Signals</a></h2>
+<h3 id="signal.lookup_aw_select" class="impl"><code class="in-band">lookup_aw_select<span class="type-annotation">: select_t</span></code></h3><div class="docblock"
+></div><h3 id="signal.w_select" class="impl"><code class="in-band">w_select<span class="type-annotation">: select_t</span></code></h3><div class="docblock"
+></div><h3 id="signal.w_select_q" class="impl"><code class="in-band">w_select_q<span class="type-annotation">: select_t</span></code></h3><div class="docblock"
+></div><h3 id="signal.w_open" class="impl"><code class="in-band">w_open<span class="type-annotation">: id_cnt_t</span></code></h3><div class="docblock"
+></div><h3 id="signal.lookup_ar_select" class="impl"><code class="in-band">lookup_ar_select<span class="type-annotation">: select_t</span></code></h3><div class="docblock"
+></div></section>
+</body>
+</html>

master/module.axi_to_mem_interleaved.html

@@ -40,6 +40,8 @@ <h3 id="port.clk_i" class="impl"><code class="in-band">clk_i<span class="type-an
 ><p>Clock input.</p>
 </div><h3 id="port.rst_ni" class="impl"><code class="in-band">rst_ni<span class="type-annotation">: input  logic</span></code></h3><div class="docblock"
 ><p>Asynchronous reset, active low.</p>
+</div><h3 id="port.test_i" class="impl"><code class="in-band">test_i<span class="type-annotation">: input  logic</span></code></h3><div class="docblock"
+><p>Testmode enable</p>
 </div><h3 id="port.busy_o" class="impl"><code class="in-band">busy_o<span class="type-annotation">: output logic</span></code></h3><div class="docblock"
 ><p>The unit is busy handling an AXI4+ATOP request.</p>
 </div><h3 id="port.axi_req_i" class="impl"><code class="in-band">axi_req_i<span class="type-annotation">: input  axi_req_t</span></code></h3><div class="docblock"

master/module.axi_to_mem_split.html

@@ -43,6 +43,8 @@ <h3 id="port.clk_i" class="impl"><code class="in-band">clk_i<span class="type-an
 ><p>Clock input.</p>
 </div><h3 id="port.rst_ni" class="impl"><code class="in-band">rst_ni<span class="type-annotation">: input logic</span></code></h3><div class="docblock"
 ><p>Asynchronous reset, active low.</p>
+</div><h3 id="port.test_i" class="impl"><code class="in-band">test_i<span class="type-annotation">: input  logic</span></code></h3><div class="docblock"
+><p>Testmode enable</p>
 </div><h3 id="port.busy_o" class="impl"><code class="in-band">busy_o<span class="type-annotation">: output logic</span></code></h3><div class="docblock"
 ><p>The unit is busy handling an AXI4+ATOP request.</p>
 </div><h3 id="port.axi_req_i" class="impl"><code class="in-band">axi_req_i<span class="type-annotation">: input  axi_req_t</span></code></h3><div class="docblock"