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@micprog
micprog committed Jul 5, 2023
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36 changes: 20 additions & 16 deletions detailed_mem/module.axi_to_detailed_mem.html
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Expand Up @@ -53,38 +53,42 @@ <h3 id="port.clk_i" class="impl"><code class="in-band">clk_i<span class="type-an
><p>AXI4+ATOP slave port, request input.</p>
</div><h3 id="port.axi_resp_o" class="impl"><code class="in-band">axi_resp_o<span class="type-annotation">: output axi_resp_t</span></code></h3><div class="docblock"
><p>AXI4+ATOP slave port, response output.</p>
</div><h3 id="port.mem_req_o" class="impl"><code class="in-band">mem_req_o<span class="type-annotation">: output logic [NumBanks-1:0]</span></code></h3><div class="docblock"
</div><h3 id="port.mem_req_o" class="impl"><code class="in-band">mem_req_o<span class="type-annotation">: output logic [NumBanks-1:0]</span></code></h3><div class="docblock"
><p>Memory stream master, request is valid for this bank.</p>
</div><h3 id="port.mem_gnt_i" class="impl"><code class="in-band">mem_gnt_i<span class="type-annotation">: input logic [NumBanks-1:0]</span></code></h3><div class="docblock"
</div><h3 id="port.mem_gnt_i" class="impl"><code class="in-band">mem_gnt_i<span class="type-annotation">: input logic [NumBanks-1:0]</span></code></h3><div class="docblock"
><p>Memory stream master, request can be granted by this bank.</p>
</div><h3 id="port.mem_addr_o" class="impl"><code class="in-band">mem_addr_o<span class="type-annotation">: output addr_t [NumBanks-1:0]</span></code></h3><div class="docblock"
</div><h3 id="port.mem_addr_o" class="impl"><code class="in-band">mem_addr_o<span class="type-annotation">: output addr_t [NumBanks-1:0]</span></code></h3><div class="docblock"
><p>Memory stream master, byte address of the request.</p>
</div><h3 id="port.mem_wdata_o" class="impl"><code class="in-band">mem_wdata_o<span class="type-annotation">: output mem_data_t [NumBanks-1:0]</span></code></h3><div class="docblock"
</div><h3 id="port.mem_wdata_o" class="impl"><code class="in-band">mem_wdata_o<span class="type-annotation">: output mem_data_t [NumBanks-1:0]</span></code></h3><div class="docblock"
><p>Memory stream master, write data for this bank. Valid when <code>mem_req_o</code>.</p>
</div><h3 id="port.mem_strb_o" class="impl"><code class="in-band">mem_strb_o<span class="type-annotation">: output mem_strb_t [NumBanks-1:0]</span></code></h3><div class="docblock"
</div><h3 id="port.mem_strb_o" class="impl"><code class="in-band">mem_strb_o<span class="type-annotation">: output mem_strb_t [NumBanks-1:0]</span></code></h3><div class="docblock"
><p>Memory stream master, byte-wise strobe (byte enable).</p>
</div><h3 id="port.mem_atop_o" class="impl"><code class="in-band">mem_atop_o<span class="type-annotation">: output axi_pkg::atop_t [NumBanks-1:0]</span></code></h3><div class="docblock"
</div><h3 id="port.mem_atop_o" class="impl"><code class="in-band">mem_atop_o<span class="type-annotation">: output axi_pkg::atop_t [NumBanks-1:0]</span></code></h3><div class="docblock"
><p>Memory stream master, <code>axi_pkg::atop_t</code> signal associated with this request.</p>
</div><h3 id="port.mem_lock_o" class="impl"><code class="in-band">mem_lock_o<span class="type-annotation">: output logic [NumBanks-1:0]</span></code></h3><div class="docblock"
</div><h3 id="port.mem_lock_o" class="impl"><code class="in-band">mem_lock_o<span class="type-annotation">: output logic [NumBanks-1:0]</span></code></h3><div class="docblock"
><p>Memory stream master, lock signal.</p>
</div><h3 id="port.mem_we_o" class="impl"><code class="in-band">mem_we_o<span class="type-annotation">: output logic [NumBanks-1:0]</span></code></h3><div class="docblock"
</div><h3 id="port.mem_we_o" class="impl"><code class="in-band">mem_we_o<span class="type-annotation">: output logic [NumBanks-1:0]</span></code></h3><div class="docblock"
><p>Memory stream master, write enable. Then asserted store of <code>mem_w_data</code> is requested.</p>
</div><h3 id="port.mem_id_o" class="impl"><code class="in-band">mem_id_o<span class="type-annotation">: output mem_id_t [NumBanks-1:0]</span></code></h3><div class="docblock"
</div><h3 id="port.mem_id_o" class="impl"><code class="in-band">mem_id_o<span class="type-annotation">: output mem_id_t [NumBanks-1:0]</span></code></h3><div class="docblock"
><p>Memory stream master, ID. Response ID is managed internally, ensure in-order responses.</p>
</div><h3 id="port.mem_user_o" class="impl"><code class="in-band">mem_user_o<span class="type-annotation">: output mem_user_t [NumBanks-1:0]</span></code></h3><div class="docblock"
</div><h3 id="port.mem_user_o" class="impl"><code class="in-band">mem_user_o<span class="type-annotation">: output mem_user_t [NumBanks-1:0]</span></code></h3><div class="docblock"
><p>Memory stream master, user signal. Ax channel user bits used.</p>
</div><h3 id="port.mem_cache_o" class="impl"><code class="in-band">mem_cache_o<span class="type-annotation">: output axi_pkg::cache_t [NumBanks-1:0]</span></code></h3><div class="docblock"
</div><h3 id="port.mem_cache_o" class="impl"><code class="in-band">mem_cache_o<span class="type-annotation">: output axi_pkg::cache_t [NumBanks-1:0]</span></code></h3><div class="docblock"
><p>Memory stream master, cache signal.</p>
</div><h3 id="port.mem_prot_o" class="impl"><code class="in-band">mem_prot_o<span class="type-annotation">: output axi_pkg::prot_t [NumBanks-1:0]</span></code></h3><div class="docblock"
</div><h3 id="port.mem_prot_o" class="impl"><code class="in-band">mem_prot_o<span class="type-annotation">: output axi_pkg::prot_t [NumBanks-1:0]</span></code></h3><div class="docblock"
><p>Memory stream master, protection signal.</p>
</div><h3 id="port.mem_rvalid_i" class="impl"><code class="in-band">mem_rvalid_i<span class="type-annotation">: input logic [NumBanks-1:0]</span></code></h3><div class="docblock"
</div><h3 id="port.mem_qos_o" class="impl"><code class="in-band">mem_qos_o<span class="type-annotation">: output axi_pkg::qos_t [NumBanks-1:0]</span></code></h3><div class="docblock"
><p>Memory stream master, QOS signal.</p>
</div><h3 id="port.mem_region_o" class="impl"><code class="in-band">mem_region_o<span class="type-annotation">: output axi_pkg::region_t [NumBanks-1:0]</span></code></h3><div class="docblock"
><p>Memory stream master, region signal.</p>
</div><h3 id="port.mem_rvalid_i" class="impl"><code class="in-band">mem_rvalid_i<span class="type-annotation">: input logic [NumBanks-1:0]</span></code></h3><div class="docblock"
><p>Memory stream master, response is valid. This module expects always a response valid for a
request regardless if the request was a write or a read.</p>
</div><h3 id="port.mem_rdata_i" class="impl"><code class="in-band">mem_rdata_i<span class="type-annotation">: input mem_data_t [NumBanks-1:0]</span></code></h3><div class="docblock"
</div><h3 id="port.mem_rdata_i" class="impl"><code class="in-band">mem_rdata_i<span class="type-annotation">: input mem_data_t [NumBanks-1:0]</span></code></h3><div class="docblock"
><p>Memory stream master, read response data.</p>
</div><h3 id="port.mem_err_i" class="impl"><code class="in-band">mem_err_i<span class="type-annotation">: input logic [NumBanks-1:0]</span></code></h3><div class="docblock"
</div><h3 id="port.mem_err_i" class="impl"><code class="in-band">mem_err_i<span class="type-annotation">: input logic [NumBanks-1:0]</span></code></h3><div class="docblock"
><p>Memory stream master, error response.</p>
</div><h3 id="port.mem_exokay_i" class="impl"><code class="in-band">mem_exokay_i<span class="type-annotation">: input logic [NumBanks-1:0]</span></code></h3><div class="docblock"
</div><h3 id="port.mem_exokay_i" class="impl"><code class="in-band">mem_exokay_i<span class="type-annotation">: input logic [NumBanks-1:0]</span></code></h3><div class="docblock"
><p>Memory stream master, read response exclusive access OK.</p>
</div><h2 id="types" class="section-header"><a href="#types">Types<a></h2>
<table>
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36 changes: 22 additions & 14 deletions detailed_mem/module.axi_to_detailed_mem_intf.html
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Expand Up @@ -39,33 +39,41 @@ <h3 id="port.clk_i" class="impl"><code class="in-band">clk_i<span class="type-an
><p>See <code>axi_to_mem</code>, port <code>busy_o</code>.</p>
</div><h3 id="port.slv" class="impl"><code class="in-band">slv<span class="type-annotation">: AXI_BUS.Slave</span></code></h3><div class="docblock"
><p>AXI4+ATOP slave interface port.</p>
</div><h3 id="port.mem_req_o" class="impl"><code class="in-band">mem_req_o<span class="type-annotation">: output logic [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
</div><h3 id="port.mem_req_o" class="impl"><code class="in-band">mem_req_o<span class="type-annotation">: output logic [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
><p>See <code>axi_to_mem</code>, port <code>mem_req_o</code>.</p>
</div><h3 id="port.mem_gnt_i" class="impl"><code class="in-band">mem_gnt_i<span class="type-annotation">: input logic [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
</div><h3 id="port.mem_gnt_i" class="impl"><code class="in-band">mem_gnt_i<span class="type-annotation">: input logic [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
><p>See <code>axi_to_mem</code>, port <code>mem_gnt_i</code>.</p>
</div><h3 id="port.mem_addr_o" class="impl"><code class="in-band">mem_addr_o<span class="type-annotation">: output addr_t [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
</div><h3 id="port.mem_addr_o" class="impl"><code class="in-band">mem_addr_o<span class="type-annotation">: output addr_t [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
><p>See <code>axi_to_mem</code>, port <code>mem_addr_o</code>.</p>
</div><h3 id="port.mem_wdata_o" class="impl"><code class="in-band">mem_wdata_o<span class="type-annotation">: output mem_data_t [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
</div><h3 id="port.mem_wdata_o" class="impl"><code class="in-band">mem_wdata_o<span class="type-annotation">: output mem_data_t [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
><p>See <code>axi_to_mem</code>, port <code>mem_wdata_o</code>.</p>
</div><h3 id="port.mem_strb_o" class="impl"><code class="in-band">mem_strb_o<span class="type-annotation">: output mem_strb_t [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
</div><h3 id="port.mem_strb_o" class="impl"><code class="in-band">mem_strb_o<span class="type-annotation">: output mem_strb_t [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
><p>See <code>axi_to_mem</code>, port <code>mem_strb_o</code>.</p>
</div><h3 id="port.mem_atop_o" class="impl"><code class="in-band">mem_atop_o<span class="type-annotation">: output axi_pkg::atop_t [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
</div><h3 id="port.mem_atop_o" class="impl"><code class="in-band">mem_atop_o<span class="type-annotation">: output axi_pkg::atop_t [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
><p>See <code>axi_to_mem</code>, port <code>mem_atop_o</code>.</p>
</div><h3 id="port.mem_lock_o" class="impl"><code class="in-band">mem_lock_o<span class="type-annotation">: output logic [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
</div><h3 id="port.mem_lock_o" class="impl"><code class="in-band">mem_lock_o<span class="type-annotation">: output logic [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
><p>See <code>axi_to_mem</code>, port <code>mem_lock_o</code>.</p>
</div><h3 id="port.mem_we_o" class="impl"><code class="in-band">mem_we_o<span class="type-annotation">: output logic [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
</div><h3 id="port.mem_we_o" class="impl"><code class="in-band">mem_we_o<span class="type-annotation">: output logic [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
><p>See <code>axi_to_mem</code>, port <code>mem_we_o</code>.</p>
</div><h3 id="port.mem_id_o" class="impl"><code class="in-band">mem_id_o<span class="type-annotation">: output logic [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
</div><h3 id="port.mem_id_o" class="impl"><code class="in-band">mem_id_o<span class="type-annotation">: output logic [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
><p>See <code>axi_to_mem</code>, port <code>mem_id_o</code>.</p>
</div><h3 id="port.mem_user_o" class="impl"><code class="in-band">mem_user_o<span class="type-annotation">: output logic [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
</div><h3 id="port.mem_user_o" class="impl"><code class="in-band">mem_user_o<span class="type-annotation">: output logic [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
><p>See <code>axi_to_mem</code>, port <code>mem_user_o</code>.</p>
</div><h3 id="port.mem_rvalid_i" class="impl"><code class="in-band">mem_rvalid_i<span class="type-annotation">: input logic [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
</div><h3 id="port.mem_cache_o" class="impl"><code class="in-band">mem_cache_o<span class="type-annotation">: output axi_pkg::cache_t [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
><p>See <code>axi_to_mem</code>, port <code>mem_cache_o</code>.</p>
</div><h3 id="port.mem_prot_o" class="impl"><code class="in-band">mem_prot_o<span class="type-annotation">: output axi_pkg::prot_t [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
><p>See <code>axi_to_mem</code>, port <code>mem_prot_o</code>.</p>
</div><h3 id="port.mem_qos_o" class="impl"><code class="in-band">mem_qos_o<span class="type-annotation">: output axi_pkg::qos_t [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
><p>See <code>axi_to_mem</code>, port <code>mem_qos_o</code>.</p>
</div><h3 id="port.mem_region_o" class="impl"><code class="in-band">mem_region_o<span class="type-annotation">: output axi_pkg::region_t [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
><p>See <code>axi_to_mem</code>, port <code>mem_region_o</code>.</p>
</div><h3 id="port.mem_rvalid_i" class="impl"><code class="in-band">mem_rvalid_i<span class="type-annotation">: input logic [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
><p>See <code>axi_to_mem</code>, port <code>mem_rvalid_i</code>.</p>
</div><h3 id="port.mem_rdata_i" class="impl"><code class="in-band">mem_rdata_i<span class="type-annotation">: input mem_data_t [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
</div><h3 id="port.mem_rdata_i" class="impl"><code class="in-band">mem_rdata_i<span class="type-annotation">: input mem_data_t [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
><p>See <code>axi_to_mem</code>, port <code>mem_rdata_i</code>.</p>
</div><h3 id="port.mem_err_i" class="impl"><code class="in-band">mem_err_i<span class="type-annotation">: input logic [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
</div><h3 id="port.mem_err_i" class="impl"><code class="in-band">mem_err_i<span class="type-annotation">: input logic [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
><p>See <code>axi_to_mem</code>, port <code>mem_err_i</code>.</p>
</div><h3 id="port.mem_exokay_i" class="impl"><code class="in-band">mem_exokay_i<span class="type-annotation">: input logic [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
</div><h3 id="port.mem_exokay_i" class="impl"><code class="in-band">mem_exokay_i<span class="type-annotation">: input logic [NUM_BANKS-1:0]</span></code></h3><div class="docblock"
><p>See <code>axi_to_mem</code>, port <code>mem_exokay_i</code>.</p>
</div><h2 id="types" class="section-header"><a href="#types">Types<a></h2>
<table>
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22 changes: 12 additions & 10 deletions detailed_mem/type.mem_req_t.html
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Expand Up @@ -5,16 +5,18 @@
<body>
<section id="main" class="content"><h1 class="fqn">Typedef <a class="type">mem_req_t</a></h1>
<pre>typedef struct packed {
addr_t addr;
axi_pkg::atop_t atop;
logic lock;
axi_strb_t strb;
axi_data_t wdata;
logic we;
mem_id_t id;
mem_user_t user;
axi_pkg::cache_t cache;
axi_pkg::prot_t prot;
addr_t addr;
axi_pkg::atop_t atop;
logic lock;
axi_strb_t strb;
axi_data_t wdata;
logic we;
mem_id_t id;
mem_user_t user;
axi_pkg::cache_t cache;
axi_pkg::prot_t prot;
axi_pkg::qos_t qos;
axi_pkg::region_t region;
} mem_req_t;</pre>
</section>
</body>
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24 changes: 13 additions & 11 deletions detailed_mem/type.meta_t.html
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<body>
<section id="main" class="content"><h1 class="fqn">Typedef <a class="type">meta_t</a></h1>
<pre>typedef struct packed {
addr_t addr;
axi_pkg::atop_t atop;
logic lock;
axi_id_t id;
logic last;
axi_pkg::qos_t qos;
axi_pkg::size_t size;
logic write;
mem_user_t user;
axi_pkg::cache_t cache;
axi_pkg::prot_t prot;
addr_t addr;
axi_pkg::atop_t atop;
logic lock;
axi_id_t id;
logic last;
axi_pkg::qos_t qos;
axi_pkg::size_t size;
logic write;
mem_user_t user;
axi_pkg::cache_t cache;
axi_pkg::prot_t prot;
axi_pkg::qos_t qos;
axi_pkg::region_t region;
} meta_t;</pre>
</section>
</body>
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14 changes: 8 additions & 6 deletions detailed_mem/type.tmp_atop_t.html
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<body>
<section id="main" class="content"><h1 class="fqn">Typedef <a class="type">tmp_atop_t</a></h1>
<pre>typedef struct packed {
axi_pkg::atop_t atop;
logic lock;
mem_id_t id;
mem_user_t user;
axi_pkg::cache_t cache;
axi_pkg::prot_t prot;
axi_pkg::atop_t atop;
logic lock;
mem_id_t id;
mem_user_t user;
axi_pkg::cache_t cache;
axi_pkg::prot_t prot;
axi_pkg::qos_t qos;
axi_pkg::region_t region;
} tmp_atop_t;</pre>
</section>
</body>
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