-
Notifications
You must be signed in to change notification settings - Fork 268
Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
Deploying to gh-pages from @ 1c9a102 🚀
- Loading branch information
1 parent
74952d0
commit 78ae5a4
Showing
320 changed files
with
10,765 additions
and
0 deletions.
There are no files selected for viewing
Loading
Sorry, something went wrong. Reload?
Sorry, we cannot display this file.
Sorry, this file is invalid so it cannot be displayed.
Large diffs are not rendered by default.
Oops, something went wrong.
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,73 @@ | ||
| <html> | ||
| <link rel="stylesheet" type="text/css" href="static/rustdoc.css"> | ||
| <link rel="stylesheet" type="text/css" href="static/light.css"> | ||
| <link rel="stylesheet" type="text/css" href="static/svdoc.css"> | ||
| <body> | ||
| <section id="main" class="content"><h1 class="fqn">Module <a class="module">axi_atop_filter</a></h1> | ||
| <div class="docblock"> | ||
| <p>Filter atomic operations (ATOPs) in a protocol-compliant manner.</p> | ||
| <p>This module filters atomic operations (ATOPs), i.e., write transactions that have a non-zero | ||
| <code>aw_atop</code> value, from its <code>slv</code> to its <code>mst</code> port. This module guarantees that:</p> | ||
| <ol> | ||
| <li> | ||
| <p><code>aw_atop</code> is always zero on the <code>mst</code> port;</p> | ||
| </li> | ||
| <li> | ||
| <p>write transactions with non-zero <code>aw_atop</code> on the <code>slv</code> port are handled in conformance with | ||
| the AXI standard by replying to such write transactions with the proper B and R responses. | ||
| The response code on atomic operations that reach this module is always SLVERR | ||
| (implementation-specific, not defined in the AXI standard).</p> | ||
| </li> | ||
| </ol> | ||
| <h2>Intended usage</h2> | ||
| <p>This module is intended to be placed between masters that may issue ATOPs and slaves that do not | ||
| support ATOPs. That way, this module ensures that the AXI protocol remains in a defined state on | ||
| systems with mixed ATOP capabilities.</p> | ||
| <h2>Specification reminder</h2> | ||
| <p>The AXI standard specifies that there may be no ordering requirements between different atomic | ||
| bursts (i.e., a burst started by an AW with ATOP other than 0) and none between atomic bursts | ||
| and non-atomic bursts [E2.1.4]. That is, <strong>an atomic burst may never have the same ID as any | ||
| other write or read burst that is in-flight at the same time</strong>.</p> | ||
| </div> | ||
| <h2 id="parameters" class="section-header"><a href="#parameters">Parameters</a></h2> | ||
| <h3 id="parameter.AxiIdWidth" class="impl"><code class="in-band">AxiIdWidth<span class="type-annotation">: int unsigned</span></code></h3><div class="docblock" | ||
| ><p>AXI ID width</p> | ||
| </div><h3 id="parameter.AxiMaxWriteTxns" class="impl"><code class="in-band">AxiMaxWriteTxns<span class="type-annotation">: int unsigned</span></code></h3><div class="docblock" | ||
| ><p>Maximum number of in-flight AXI write transactions</p> | ||
| </div><h3 id="parameter.axi_req_t" class="impl"><code class="in-band">axi_req_t<span class="type-annotation">: type</span></code></h3><div class="docblock" | ||
| ><p>AXI request type</p> | ||
| </div><h3 id="parameter.axi_resp_t" class="impl"><code class="in-band">axi_resp_t<span class="type-annotation">: type</span></code></h3><div class="docblock" | ||
| ><p>AXI response type</p> | ||
| </div><h3 id="parameter.COUNTER_WIDTH" class="impl"><code class="in-band">COUNTER_WIDTH<span class="type-annotation">: int unsigned</span></code></h3><div class="docblock" | ||
| ></div><h2 id="ports" class="section-header"><a href="#ports">Ports</a></h2> | ||
| <h3 id="port.clk_i" class="impl"><code class="in-band">clk_i<span class="type-annotation">: input logic</span></code></h3><div class="docblock" | ||
| ><p>Rising-edge clock of both ports</p> | ||
| </div><h3 id="port.rst_ni" class="impl"><code class="in-band">rst_ni<span class="type-annotation">: input logic</span></code></h3><div class="docblock" | ||
| ><p>Asynchronous reset, active low</p> | ||
| </div><h3 id="port.slv_req_i" class="impl"><code class="in-band">slv_req_i<span class="type-annotation">: input axi_req_t</span></code></h3><div class="docblock" | ||
| ><p>Slave port request</p> | ||
| </div><h3 id="port.slv_resp_o" class="impl"><code class="in-band">slv_resp_o<span class="type-annotation">: output axi_resp_t</span></code></h3><div class="docblock" | ||
| ><p>Slave port response</p> | ||
| </div><h3 id="port.mst_req_o" class="impl"><code class="in-band">mst_req_o<span class="type-annotation">: output axi_req_t</span></code></h3><div class="docblock" | ||
| ><p>Master port request</p> | ||
| </div><h3 id="port.mst_resp_i" class="impl"><code class="in-band">mst_resp_i<span class="type-annotation">: input axi_resp_t</span></code></h3><div class="docblock" | ||
| ><p>Master port response</p> | ||
| </div><h2 id="types" class="section-header"><a href="#types">Types<a></h2> | ||
| <table> | ||
| <tr><td><a class="type" href="type.cnt_t.html">cnt_t</a></td><td></td></tr><tr><td><a class="type" href="type.w_state_e.html">w_state_e</a></td><td></td></tr><tr><td><a class="type" href="type.r_state_e.html">r_state_e</a></td><td></td></tr><tr><td><a class="type" href="type.id_t.html">id_t</a></td><td></td></tr><tr><td><a class="type" href="type.len_t.html">len_t</a></td><td></td></tr><tr><td><a class="type" href="type.r_resp_cmd_t.html">r_resp_cmd_t</a></td><td></td></tr></table> | ||
| <h2 id="signals" class="section-header"><a href="#signals">Signals</a></h2> | ||
| <h3 id="signal.w_cnt_d" class="impl"><code class="in-band">w_cnt_d<span class="type-annotation">: cnt_t</span></code></h3><div class="docblock" | ||
| ></div><h3 id="signal.w_cnt_q" class="impl"><code class="in-band">w_cnt_q<span class="type-annotation">: cnt_t</span></code></h3><div class="docblock" | ||
| ></div><h3 id="signal.w_state_d" class="impl"><code class="in-band">w_state_d<span class="type-annotation">: w_state_e</span></code></h3><div class="docblock" | ||
| ></div><h3 id="signal.w_state_q" class="impl"><code class="in-band">w_state_q<span class="type-annotation">: w_state_e</span></code></h3><div class="docblock" | ||
| ></div><h3 id="signal.r_state_d" class="impl"><code class="in-band">r_state_d<span class="type-annotation">: r_state_e</span></code></h3><div class="docblock" | ||
| ></div><h3 id="signal.r_state_q" class="impl"><code class="in-band">r_state_q<span class="type-annotation">: r_state_e</span></code></h3><div class="docblock" | ||
| ></div><h3 id="signal.id_d" class="impl"><code class="in-band">id_d<span class="type-annotation">: id_t</span></code></h3><div class="docblock" | ||
| ></div><h3 id="signal.id_q" class="impl"><code class="in-band">id_q<span class="type-annotation">: id_t</span></code></h3><div class="docblock" | ||
| ></div><h3 id="signal.r_beats_d" class="impl"><code class="in-band">r_beats_d<span class="type-annotation">: len_t</span></code></h3><div class="docblock" | ||
| ></div><h3 id="signal.r_beats_q" class="impl"><code class="in-band">r_beats_q<span class="type-annotation">: len_t</span></code></h3><div class="docblock" | ||
| ></div><h3 id="signal.r_resp_cmd_push" class="impl"><code class="in-band">r_resp_cmd_push<span class="type-annotation">: r_resp_cmd_t</span></code></h3><div class="docblock" | ||
| ></div><h3 id="signal.r_resp_cmd_pop" class="impl"><code class="in-band">r_resp_cmd_pop<span class="type-annotation">: r_resp_cmd_t</span></code></h3><div class="docblock" | ||
| ></div></section> | ||
| </body> | ||
| </html> |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,40 @@ | ||
| <html> | ||
| <link rel="stylesheet" type="text/css" href="static/rustdoc.css"> | ||
| <link rel="stylesheet" type="text/css" href="static/light.css"> | ||
| <link rel="stylesheet" type="text/css" href="static/svdoc.css"> | ||
| <body> | ||
| <section id="main" class="content"><h1 class="fqn">Module <a class="module">axi_atop_filter_intf</a></h1> | ||
| <div class="docblock"> | ||
| <p>Interface variant of <a href="module.axi_atop_filter"><code>axi_atop_filter</code></a>.</p> | ||
| </div> | ||
| <h2 id="parameters" class="section-header"><a href="#parameters">Parameters</a></h2> | ||
| <h3 id="parameter.AXI_ID_WIDTH" class="impl"><code class="in-band">AXI_ID_WIDTH<span class="type-annotation">: int unsigned</span></code></h3><div class="docblock" | ||
| ><p>AXI ID width</p> | ||
| </div><h3 id="parameter.AXI_ADDR_WIDTH" class="impl"><code class="in-band">AXI_ADDR_WIDTH<span class="type-annotation">: int unsigned</span></code></h3><div class="docblock" | ||
| ><p>AXI address width</p> | ||
| </div><h3 id="parameter.AXI_DATA_WIDTH" class="impl"><code class="in-band">AXI_DATA_WIDTH<span class="type-annotation">: int unsigned</span></code></h3><div class="docblock" | ||
| ><p>AXI data width</p> | ||
| </div><h3 id="parameter.AXI_USER_WIDTH" class="impl"><code class="in-band">AXI_USER_WIDTH<span class="type-annotation">: int unsigned</span></code></h3><div class="docblock" | ||
| ><p>AXI user signal width</p> | ||
| </div><h3 id="parameter.AXI_MAX_WRITE_TXNS" class="impl"><code class="in-band">AXI_MAX_WRITE_TXNS<span class="type-annotation">: int unsigned</span></code></h3><div class="docblock" | ||
| ><p>Maximum number of in-flight AXI write transactions</p> | ||
| </div><h2 id="ports" class="section-header"><a href="#ports">Ports</a></h2> | ||
| <h3 id="port.clk_i" class="impl"><code class="in-band">clk_i<span class="type-annotation">: input logic</span></code></h3><div class="docblock" | ||
| ><p>Rising-edge clock of both ports</p> | ||
| </div><h3 id="port.rst_ni" class="impl"><code class="in-band">rst_ni<span class="type-annotation">: input logic</span></code></h3><div class="docblock" | ||
| ><p>Asynchronous reset, active low</p> | ||
| </div><h3 id="port.slv" class="impl"><code class="in-band">slv<span class="type-annotation">: AXI_BUS.Slave</span></code></h3><div class="docblock" | ||
| ><p>Slave interface port</p> | ||
| </div><h3 id="port.mst" class="impl"><code class="in-band">mst<span class="type-annotation">: AXI_BUS.Master</span></code></h3><div class="docblock" | ||
| ><p>Master interface port</p> | ||
| </div><h2 id="types" class="section-header"><a href="#types">Types<a></h2> | ||
| <table> | ||
| <tr><td><a class="type" href="type.id_t.html">id_t</a></td><td></td></tr><tr><td><a class="type" href="type.addr_t.html">addr_t</a></td><td></td></tr><tr><td><a class="type" href="type.data_t.html">data_t</a></td><td></td></tr><tr><td><a class="type" href="type.strb_t.html">strb_t</a></td><td></td></tr><tr><td><a class="type" href="type.user_t.html">user_t</a></td><td></td></tr><tr><td><a class="type" href="type.aw_chan_t.html">aw_chan_t</a></td><td></td></tr><tr><td><a class="type" href="type.w_chan_t.html">w_chan_t</a></td><td></td></tr><tr><td><a class="type" href="type.b_chan_t.html">b_chan_t</a></td><td></td></tr><tr><td><a class="type" href="type.ar_chan_t.html">ar_chan_t</a></td><td></td></tr><tr><td><a class="type" href="type.r_chan_t.html">r_chan_t</a></td><td></td></tr><tr><td><a class="type" href="type.axi_req_t.html">axi_req_t</a></td><td></td></tr><tr><td><a class="type" href="type.axi_resp_t.html">axi_resp_t</a></td><td></td></tr></table> | ||
| <h2 id="signals" class="section-header"><a href="#signals">Signals</a></h2> | ||
| <h3 id="signal.slv_req" class="impl"><code class="in-band">slv_req<span class="type-annotation">: axi_req_t</span></code></h3><div class="docblock" | ||
| ></div><h3 id="signal.mst_req" class="impl"><code class="in-band">mst_req<span class="type-annotation">: axi_req_t</span></code></h3><div class="docblock" | ||
| ></div><h3 id="signal.slv_resp" class="impl"><code class="in-band">slv_resp<span class="type-annotation">: axi_resp_t</span></code></h3><div class="docblock" | ||
| ></div><h3 id="signal.mst_resp" class="impl"><code class="in-band">mst_resp<span class="type-annotation">: axi_resp_t</span></code></h3><div class="docblock" | ||
| ></div></section> | ||
| </body> | ||
| </html> |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,45 @@ | ||
| <html> | ||
| <link rel="stylesheet" type="text/css" href="static/rustdoc.css"> | ||
| <link rel="stylesheet" type="text/css" href="static/light.css"> | ||
| <link rel="stylesheet" type="text/css" href="static/svdoc.css"> | ||
| <body> | ||
| <section id="main" class="content"><h1 class="fqn">Module <a class="module">axi_burst_splitter</a></h1> | ||
| <div class="docblock"> | ||
| <p>Split AXI4 bursts into single-beat transactions.</p> | ||
| <h2>Limitations</h2> | ||
| <ul> | ||
| <li>This module does not support wrapping (<a href="package.axi_pkg"><code>axi_pkg::BURST_WRAP</code></a>) bursts and | ||
| responds to such bursts with slave error(s).</li> | ||
| <li>This module does not support atomic operations (ATOPs) and responds to ATOPs with a slave | ||
| error. Place an <a href="module.axi_atop_filter"><code>axi_atop_filter</code></a> before this module if upstream | ||
| modules can generate ATOPs.</li> | ||
| </ul> | ||
| </div> | ||
| <h2 id="parameters" class="section-header"><a href="#parameters">Parameters</a></h2> | ||
| <h3 id="parameter.MaxReadTxns" class="impl"><code class="in-band">MaxReadTxns<span class="type-annotation">: int unsigned</span></code></h3><div class="docblock" | ||
| ></div><h3 id="parameter.MaxWriteTxns" class="impl"><code class="in-band">MaxWriteTxns<span class="type-annotation">: int unsigned</span></code></h3><div class="docblock" | ||
| ></div><h3 id="parameter.AddrWidth" class="impl"><code class="in-band">AddrWidth<span class="type-annotation">: int unsigned</span></code></h3><div class="docblock" | ||
| ></div><h3 id="parameter.DataWidth" class="impl"><code class="in-band">DataWidth<span class="type-annotation">: int unsigned</span></code></h3><div class="docblock" | ||
| ></div><h3 id="parameter.IdWidth" class="impl"><code class="in-band">IdWidth<span class="type-annotation">: int unsigned</span></code></h3><div class="docblock" | ||
| ></div><h3 id="parameter.UserWidth" class="impl"><code class="in-band">UserWidth<span class="type-annotation">: int unsigned</span></code></h3><div class="docblock" | ||
| ></div><h3 id="parameter.axi_req_t" class="impl"><code class="in-band">axi_req_t<span class="type-annotation">: type</span></code></h3><div class="docblock" | ||
| ></div><h3 id="parameter.axi_resp_t" class="impl"><code class="in-band">axi_resp_t<span class="type-annotation">: type</span></code></h3><div class="docblock" | ||
| ></div><h3 id="parameter.MaxTxns" class="impl"><code class="in-band">MaxTxns<span class="type-annotation">: int unsigned</span></code></h3><div class="docblock" | ||
| ></div><h2 id="ports" class="section-header"><a href="#ports">Ports</a></h2> | ||
| <h3 id="port.clk_i" class="impl"><code class="in-band">clk_i<span class="type-annotation">: input logic</span></code></h3><div class="docblock" | ||
| ></div><h3 id="port.rst_ni" class="impl"><code class="in-band">rst_ni<span class="type-annotation">: input logic</span></code></h3><div class="docblock" | ||
| ></div><h3 id="port.slv_req_i" class="impl"><code class="in-band">slv_req_i<span class="type-annotation">: input axi_req_t</span></code></h3><div class="docblock" | ||
| ></div><h3 id="port.slv_resp_o" class="impl"><code class="in-band">slv_resp_o<span class="type-annotation">: output axi_resp_t</span></code></h3><div class="docblock" | ||
| ></div><h3 id="port.mst_req_o" class="impl"><code class="in-band">mst_req_o<span class="type-annotation">: output axi_req_t</span></code></h3><div class="docblock" | ||
| ></div><h3 id="port.mst_resp_i" class="impl"><code class="in-band">mst_resp_i<span class="type-annotation">: input axi_resp_t</span></code></h3><div class="docblock" | ||
| ></div><h2 id="types" class="section-header"><a href="#types">Types<a></h2> | ||
| <table> | ||
| <tr><td><a class="type" href="type.addr_t.html">addr_t</a></td><td></td></tr><tr><td><a class="type" href="type.data_t.html">data_t</a></td><td></td></tr><tr><td><a class="type" href="type.id_t.html">id_t</a></td><td></td></tr><tr><td><a class="type" href="type.strb_t.html">strb_t</a></td><td></td></tr><tr><td><a class="type" href="type.user_t.html">user_t</a></td><td></td></tr><tr><td><a class="type" href="type.aw_chan_t.html">aw_chan_t</a></td><td></td></tr><tr><td><a class="type" href="type.w_chan_t.html">w_chan_t</a></td><td></td></tr><tr><td><a class="type" href="type.b_chan_t.html">b_chan_t</a></td><td></td></tr><tr><td><a class="type" href="type.ar_chan_t.html">ar_chan_t</a></td><td></td></tr><tr><td><a class="type" href="type.r_chan_t.html">r_chan_t</a></td><td></td></tr></table> | ||
| <h2 id="signals" class="section-header"><a href="#signals">Signals</a></h2> | ||
| <h3 id="signal.act_req" class="impl"><code class="in-band">act_req<span class="type-annotation">: axi_req_t</span></code></h3><div class="docblock" | ||
| ></div><h3 id="signal.unsupported_req" class="impl"><code class="in-band">unsupported_req<span class="type-annotation">: axi_req_t</span></code></h3><div class="docblock" | ||
| ></div><h3 id="signal.act_resp" class="impl"><code class="in-band">act_resp<span class="type-annotation">: axi_resp_t</span></code></h3><div class="docblock" | ||
| ></div><h3 id="signal.unsupported_resp" class="impl"><code class="in-band">unsupported_resp<span class="type-annotation">: axi_resp_t</span></code></h3><div class="docblock" | ||
| ></div></section> | ||
| </body> | ||
| </html> |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,41 @@ | ||
| <html> | ||
| <link rel="stylesheet" type="text/css" href="static/rustdoc.css"> | ||
| <link rel="stylesheet" type="text/css" href="static/light.css"> | ||
| <link rel="stylesheet" type="text/css" href="static/svdoc.css"> | ||
| <body> | ||
| <section id="main" class="content"><h1 class="fqn">Module <a class="module">axi_burst_splitter_ax_chan</a></h1> | ||
| <div class="docblock"> | ||
| <p>Internal module of <a href="module.axi_burst_splitter"><code>axi_burst_splitter</code></a> to control Ax channels.</p> | ||
| <p>Store burst lengths in counters, which are associated to AXI IDs through ID queues (to allow | ||
| reordering of responses w.r.t. requests).</p> | ||
| </div> | ||
| <h2 id="parameters" class="section-header"><a href="#parameters">Parameters</a></h2> | ||
| <h3 id="parameter.chan_t" class="impl"><code class="in-band">chan_t<span class="type-annotation">: type</span></code></h3><div class="docblock" | ||
| ></div><h3 id="parameter.IdWidth" class="impl"><code class="in-band">IdWidth<span class="type-annotation">: int unsigned</span></code></h3><div class="docblock" | ||
| ></div><h3 id="parameter.MaxTxns" class="impl"><code class="in-band">MaxTxns<span class="type-annotation">: int unsigned</span></code></h3><div class="docblock" | ||
| ></div><h3 id="parameter.id_t" class="impl"><code class="in-band">id_t<span class="type-annotation">: type</span></code></h3><div class="docblock" | ||
| ></div><h2 id="ports" class="section-header"><a href="#ports">Ports</a></h2> | ||
| <h3 id="port.clk_i" class="impl"><code class="in-band">clk_i<span class="type-annotation">: input logic</span></code></h3><div class="docblock" | ||
| ></div><h3 id="port.rst_ni" class="impl"><code class="in-band">rst_ni<span class="type-annotation">: input logic</span></code></h3><div class="docblock" | ||
| ></div><h3 id="port.ax_i" class="impl"><code class="in-band">ax_i<span class="type-annotation">: input chan_t</span></code></h3><div class="docblock" | ||
| ></div><h3 id="port.ax_valid_i" class="impl"><code class="in-band">ax_valid_i<span class="type-annotation">: input logic</span></code></h3><div class="docblock" | ||
| ></div><h3 id="port.ax_ready_o" class="impl"><code class="in-band">ax_ready_o<span class="type-annotation">: output logic</span></code></h3><div class="docblock" | ||
| ></div><h3 id="port.ax_o" class="impl"><code class="in-band">ax_o<span class="type-annotation">: output chan_t</span></code></h3><div class="docblock" | ||
| ></div><h3 id="port.ax_valid_o" class="impl"><code class="in-band">ax_valid_o<span class="type-annotation">: output logic</span></code></h3><div class="docblock" | ||
| ></div><h3 id="port.ax_ready_i" class="impl"><code class="in-band">ax_ready_i<span class="type-annotation">: input logic</span></code></h3><div class="docblock" | ||
| ></div><h3 id="port.cnt_id_i" class="impl"><code class="in-band">cnt_id_i<span class="type-annotation">: input id_t</span></code></h3><div class="docblock" | ||
| ></div><h3 id="port.cnt_len_o" class="impl"><code class="in-band">cnt_len_o<span class="type-annotation">: output axi_pkg::len_t</span></code></h3><div class="docblock" | ||
| ></div><h3 id="port.cnt_set_err_i" class="impl"><code class="in-band">cnt_set_err_i<span class="type-annotation">: input logic</span></code></h3><div class="docblock" | ||
| ></div><h3 id="port.cnt_err_o" class="impl"><code class="in-band">cnt_err_o<span class="type-annotation">: output logic</span></code></h3><div class="docblock" | ||
| ></div><h3 id="port.cnt_dec_i" class="impl"><code class="in-band">cnt_dec_i<span class="type-annotation">: input logic</span></code></h3><div class="docblock" | ||
| ></div><h3 id="port.cnt_req_i" class="impl"><code class="in-band">cnt_req_i<span class="type-annotation">: input logic</span></code></h3><div class="docblock" | ||
| ></div><h3 id="port.cnt_gnt_o" class="impl"><code class="in-band">cnt_gnt_o<span class="type-annotation">: output logic</span></code></h3><div class="docblock" | ||
| ></div><h2 id="types" class="section-header"><a href="#types">Types<a></h2> | ||
| <table> | ||
| <tr><td><a class="type" href="type.cnt_id_t.html">cnt_id_t</a></td><td></td></tr></table> | ||
| <h2 id="signals" class="section-header"><a href="#signals">Signals</a></h2> | ||
| <h3 id="signal.ax_d" class="impl"><code class="in-band">ax_d<span class="type-annotation">: chan_t</span></code></h3><div class="docblock" | ||
| ></div><h3 id="signal.ax_q" class="impl"><code class="in-band">ax_q<span class="type-annotation">: chan_t</span></code></h3><div class="docblock" | ||
| ></div></section> | ||
| </body> | ||
| </html> |
Oops, something went wrong.