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thommythomaso committed Jul 18, 2023
1 parent d9b7ecd commit cb96080
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2 changes: 2 additions & 0 deletions Bender.yml
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Expand Up @@ -7,10 +7,12 @@ package:
- "Matheus Cavalcante <matheusd@iis.ee.ethz.ch>"
- "Tim Fischer <fischeti@iis.ee.ethz.ch>"
- "Noah Huetter <huettern@ethz.ch>"
- "Cyril Koenig <cykoenig@iis.ee.ethz.ch>"
- "Andreas Kurth <akurth@iis.ee.ethz.ch>"
- "Stefan Mach <smach@iis.ee.ethz.ch>"
- "Samuel Riedel <sriedel@iis.ee.ethz.ch>"
- "Wolfgang Rönninger <wroennin@iis.ee.ethz.ch>"
- "Paul Scheffler <paulsc@iis.ee.ethz.ch>"
- "Fabian Schuiki <fschuiki@iis.ee.ethz.ch>"
- "Luca Valente <luca.valente@unibo.it>"
- "Nils Wistoff <nwistoff@iis.ee.ethz.ch>"
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1 change: 1 addition & 0 deletions CHANGELOG.md
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Expand Up @@ -53,6 +53,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
- No longer check *ModelSim* versions `10.7e` and `2021.3`, add `2022.3`.
- More thorough verification runs for the `xbar`.
- Start transitioning from shell script to Makefile to run simulations.
- Use `scripts/update_authors` to update authors, slight manual fixes performed.

### Fixed
- `axi_to_mem_banked`: Reduce hardware by properly setting `UniqueIds`.
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1 change: 1 addition & 0 deletions include/axi/typedef.svh
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Expand Up @@ -11,6 +11,7 @@
//
// Authors:
// - Andreas Kurth <akurth@iis.ee.ethz.ch>
// - Thomas Benz <tbenz@iis.ee.ethz.ch>
// - Florian Zaruba <zarubaf@iis.ee.ethz.ch>
// - Wolfgang Roenninger <wroennin@iis.ee.ethz.ch>

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1 change: 1 addition & 0 deletions scripts/run_verilator.sh
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Expand Up @@ -14,6 +14,7 @@
# - Fabian Schuiki <fschuiki@iis.ee.ethz.ch>
# - Florian Zaruba <zarubaf@iis.ee.ethz.ch>
# - Andreas Kurth <akurth@iis.ee.ethz.ch>
# - Thomas Benz <tbenz@iis.ee.ethz.ch>

set -e
ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
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1 change: 1 addition & 0 deletions scripts/run_vsim.sh
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Expand Up @@ -13,6 +13,7 @@
# Authors:
# - Andreas Kurth <akurth@iis.ee.ethz.ch>
# - Fabian Schuiki <fschuiki@iis.ee.ethz.ch>
# - Wolfgang Roenninger <wroennin@iis.ee.ethz.ch>

set -euo pipefail
ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
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3 changes: 3 additions & 0 deletions scripts/update_authors
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Expand Up @@ -19,6 +19,7 @@ declare -A hide=( \
# Map each author name to an email address.
declare -A emails=( \
["Andreas Kurth"]="akurth@iis.ee.ethz.ch" \
["Cyril Koenig"]="cykoenig@iis.ee.ethz.ch" \
["Fabian Schuiki"]="fschuiki@iis.ee.ethz.ch" \
["Florian Zaruba"]="zarubaf@iis.ee.ethz.ch" \
["Matheus Cavalcante"]="matheusd@iis.ee.ethz.ch" \
Expand All @@ -30,6 +31,8 @@ declare -A emails=( \
["Luca Valente"]="luca.valente@unibo.it" \
["Noah Huetter"]="huettern@ethz.ch" \
["Nils Wistoff"]="nwistoff@iis.ee.ethz.ch" \
["Nicole Narr"]="narrn@ethz.ch" \
["Paul Scheffler"]="paulsc@iis.ee.ethz.ch" \
["Tim Fischer"]="fischeti@iis.ee.ethz.ch" \
)

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4 changes: 2 additions & 2 deletions src/axi_chan_compare.sv
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Expand Up @@ -9,9 +9,9 @@
// specific language governing permissions and limitations under the License.
//
// Authors:
// - Thomas Benz <tbenz@iis.ee.ethz.ch>
// - Thomas Benz <tbenz@iis.ee.ethz.ch>
// - Paul Scheffler <paulsc@iis.ee.ethz.ch>
// - Tim Fischer <fischeti@iis.ee.ethz.ch>
// - Tim Fischer <fischeti@iis.ee.ethz.ch>

/// Non-synthesizable module comparing two AXI channels of the same type
module axi_chan_compare #(
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2 changes: 2 additions & 0 deletions src/axi_demux.sv
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Expand Up @@ -9,7 +9,9 @@
// specific language governing permissions and limitations under the License.
//
// Authors:
// - Michael Rogenmoser <michaero@iis.ee.ethz.ch>
// - Wolfgang Roenninger <wroennin@iis.ee.ethz.ch>
// - Thomas Benz <tbenz@iis.ee.ethz.ch>
// - Andreas Kurth <akurth@iis.ee.ethz.ch>

`include "common_cells/assertions.svh"
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2 changes: 2 additions & 0 deletions src/axi_demux_simple.sv
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Expand Up @@ -10,6 +10,8 @@
//
// Authors:
// - Wolfgang Roenninger <wroennin@iis.ee.ethz.ch>
// - Michael Rogenmoser <michaero@iis.ee.ethz.ch>
// - Thomas Benz <tbenz@iis.ee.ethz.ch>
// - Andreas Kurth <akurth@iis.ee.ethz.ch>

`include "common_cells/assertions.svh"
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2 changes: 1 addition & 1 deletion src/axi_from_mem.sv
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Expand Up @@ -10,7 +10,7 @@
//
// Authors:
// - Christopher Reinwardt <creinwar@ethz.ch>
// - Nicole Narr <narrn@ethz.ch
// - Nicole Narr <narrn@ethz.ch>

`include "axi/typedef.svh"

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1 change: 1 addition & 0 deletions src/axi_id_serialize.sv
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Expand Up @@ -11,6 +11,7 @@
//
// Authors:
// - Andreas Kurth <akurth@iis.ee.ethz.ch>
// - Paul Scheffler <paulsc@iis.ee.ethz.ch>

`include "axi/assign.svh"
`include "axi/typedef.svh"
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2 changes: 1 addition & 1 deletion src/axi_lite_dw_converter.sv
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Expand Up @@ -9,7 +9,7 @@
// specific language governing permissions and limitations under the License.

// Authors:
// - Wolfgang Rönninger <wroennin@iis.ee.ethz.ch>
// - Wolfgang Roenninger <wroennin@iis.ee.ethz.ch>

/// # AXI4-Lite data width downsize module.
///
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1 change: 1 addition & 0 deletions src/axi_lite_from_mem.sv
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Expand Up @@ -10,6 +10,7 @@
//
// Authors:
// - Wolfgang Roenninger <wroennin@iis.ee.ethz.ch>
// - Nicole Narr <narrn@ethz.ch>

/// Protocol adapter which translates memory requests to the AXI4-Lite protocol.
///
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2 changes: 2 additions & 0 deletions src/axi_pkg.sv
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Expand Up @@ -12,8 +12,10 @@
// Authors:
// - Andreas Kurth <akurth@iis.ee.ethz.ch>
// - Florian Zaruba <zarubaf@iis.ee.ethz.ch>
// - Thomas Benz <tbenz@iis.ee.ethz.ch>
// - Wolfgang Roenninger <wroennin@iis.ee.ethz.ch>
// - Fabian Schuiki <fschuiki@iis.ee.ethz.ch>
// - Cyril Koenig <cykoenig@iis.ee.ethz.ch>
// - Matheus Cavalcante <matheusd@iis.ee.ethz.ch>

//! AXI Package
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1 change: 1 addition & 0 deletions src/axi_test.sv
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Expand Up @@ -13,6 +13,7 @@
// - Andreas Kurth <akurth@iis.ee.ethz.ch>
// - Wolfgang Roenninger <wroennin@iis.ee.ethz.ch>
// - Fabian Schuiki <fschuiki@iis.ee.ethz.ch>
// - Thomas Benz <tbenz@iis.ee.ethz.ch>
// - Matheus Cavalcante <matheusd@iis.ee.ethz.ch>


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1 change: 1 addition & 0 deletions src/axi_to_detailed_mem.sv
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Expand Up @@ -10,6 +10,7 @@

// Authors:
// - Michael Rogenmoser <michaero@iis.ee.ethz.ch>
// - Thomas Benz <tbenz@iis.ee.ethz.ch>

`include "common_cells/registers.svh"
/// AXI4+ATOP slave module which translates AXI bursts into a memory stream.
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1 change: 1 addition & 0 deletions src/axi_to_mem.sv
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Expand Up @@ -10,6 +10,7 @@

// Authors:
// - Michael Rogenmoser <michaero@iis.ee.ethz.ch>
// - Thomas Benz <tbenz@iis.ee.ethz.ch>

`include "common_cells/registers.svh"
/// AXI4+ATOP slave module which translates AXI bursts into a memory stream.
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1 change: 1 addition & 0 deletions src/axi_to_mem_split.sv
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Expand Up @@ -10,6 +10,7 @@
//
// Authors:
// - Michael Rogenmoser <michaero@iis.ee.ethz.ch>
// - Thomas Benz <tbenz@iis.ee.ethz.ch>

`include "axi/assign.svh"
/// AXI4+ATOP to memory-protocol interconnect. Completely separates the read and write channel to
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4 changes: 3 additions & 1 deletion test/tb_axi_lite_dw_converter.sv
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Expand Up @@ -8,7 +8,9 @@
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.

// Author: Wolfgang Roenninger <wroennin@ethz.ch>
// Authors:
// - Wolfgang Roenninger <wroennin@iis.ee.ethz.ch>
// - Michael Rogenmoser <michaero@iis.ee.ethz.ch>


`include "axi/typedef.svh"
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2 changes: 2 additions & 0 deletions test/tb_axi_slave_compare.sv
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Expand Up @@ -2,7 +2,9 @@
// SPDX-License-Identifier: SHL-0.51
//
// Authors:
// - Andreas Kurth <akurth@iis.ee.ethz.ch>
// - Thomas Benz <tbenz@iis.ee.ethz.ch>
// - Michael Rogenmoser <michaero@iis.ee.ethz.ch>

`include "axi/assign.svh"
`include "axi/typedef.svh"
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