diff --git a/Bender.yml b/Bender.yml index 3c4a29be1..8f16f74cb 100644 --- a/Bender.yml +++ b/Bender.yml @@ -7,10 +7,12 @@ package: - "Matheus Cavalcante " - "Tim Fischer " - "Noah Huetter " + - "Cyril Koenig " - "Andreas Kurth " - "Stefan Mach " - "Samuel Riedel " - "Wolfgang Rönninger " + - "Paul Scheffler " - "Fabian Schuiki " - "Luca Valente " - "Nils Wistoff " diff --git a/CHANGELOG.md b/CHANGELOG.md index 14ebd113c..20b2f41e0 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -53,6 +53,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. - No longer check *ModelSim* versions `10.7e` and `2021.3`, add `2022.3`. - More thorough verification runs for the `xbar`. - Start transitioning from shell script to Makefile to run simulations. +- Use `scripts/update_authors` to update authors, slight manual fixes performed. ### Fixed - `axi_to_mem_banked`: Reduce hardware by properly setting `UniqueIds`. diff --git a/include/axi/typedef.svh b/include/axi/typedef.svh index 5eec91171..648c3fed7 100644 --- a/include/axi/typedef.svh +++ b/include/axi/typedef.svh @@ -11,6 +11,7 @@ // // Authors: // - Andreas Kurth +// - Thomas Benz // - Florian Zaruba // - Wolfgang Roenninger diff --git a/scripts/run_verilator.sh b/scripts/run_verilator.sh index ef21af120..dd9be3c0b 100755 --- a/scripts/run_verilator.sh +++ b/scripts/run_verilator.sh @@ -14,6 +14,7 @@ # - Fabian Schuiki # - Florian Zaruba # - Andreas Kurth +# - Thomas Benz set -e ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) diff --git a/scripts/run_vsim.sh b/scripts/run_vsim.sh index b9656ddf6..9812c5ed5 100755 --- a/scripts/run_vsim.sh +++ b/scripts/run_vsim.sh @@ -13,6 +13,7 @@ # Authors: # - Andreas Kurth # - Fabian Schuiki +# - Wolfgang Roenninger set -euo pipefail ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) diff --git a/scripts/update_authors b/scripts/update_authors index 674bad51b..79fcc24eb 100755 --- a/scripts/update_authors +++ b/scripts/update_authors @@ -19,6 +19,7 @@ declare -A hide=( \ # Map each author name to an email address. declare -A emails=( \ ["Andreas Kurth"]="akurth@iis.ee.ethz.ch" \ + ["Cyril Koenig"]="cykoenig@iis.ee.ethz.ch" \ ["Fabian Schuiki"]="fschuiki@iis.ee.ethz.ch" \ ["Florian Zaruba"]="zarubaf@iis.ee.ethz.ch" \ ["Matheus Cavalcante"]="matheusd@iis.ee.ethz.ch" \ @@ -30,6 +31,8 @@ declare -A emails=( \ ["Luca Valente"]="luca.valente@unibo.it" \ ["Noah Huetter"]="huettern@ethz.ch" \ ["Nils Wistoff"]="nwistoff@iis.ee.ethz.ch" \ + ["Nicole Narr"]="narrn@ethz.ch" \ + ["Paul Scheffler"]="paulsc@iis.ee.ethz.ch" \ ["Tim Fischer"]="fischeti@iis.ee.ethz.ch" \ ) diff --git a/src/axi_chan_compare.sv b/src/axi_chan_compare.sv index 59c99179c..e2339aedf 100644 --- a/src/axi_chan_compare.sv +++ b/src/axi_chan_compare.sv @@ -9,9 +9,9 @@ // specific language governing permissions and limitations under the License. // // Authors: -// - Thomas Benz +// - Thomas Benz // - Paul Scheffler -// - Tim Fischer +// - Tim Fischer /// Non-synthesizable module comparing two AXI channels of the same type module axi_chan_compare #( diff --git a/src/axi_demux.sv b/src/axi_demux.sv index a5f8389ad..899d83521 100644 --- a/src/axi_demux.sv +++ b/src/axi_demux.sv @@ -9,7 +9,9 @@ // specific language governing permissions and limitations under the License. // // Authors: +// - Michael Rogenmoser // - Wolfgang Roenninger +// - Thomas Benz // - Andreas Kurth `include "common_cells/assertions.svh" diff --git a/src/axi_demux_simple.sv b/src/axi_demux_simple.sv index f77514c4f..1c11f794a 100644 --- a/src/axi_demux_simple.sv +++ b/src/axi_demux_simple.sv @@ -10,6 +10,8 @@ // // Authors: // - Wolfgang Roenninger +// - Michael Rogenmoser +// - Thomas Benz // - Andreas Kurth `include "common_cells/assertions.svh" diff --git a/src/axi_from_mem.sv b/src/axi_from_mem.sv index 23ed2d3af..466a384e3 100644 --- a/src/axi_from_mem.sv +++ b/src/axi_from_mem.sv @@ -10,7 +10,7 @@ // // Authors: // - Christopher Reinwardt -// - Nicole Narr `include "axi/typedef.svh" diff --git a/src/axi_id_serialize.sv b/src/axi_id_serialize.sv index b032c7766..9a787dd25 100644 --- a/src/axi_id_serialize.sv +++ b/src/axi_id_serialize.sv @@ -11,6 +11,7 @@ // // Authors: // - Andreas Kurth +// - Paul Scheffler `include "axi/assign.svh" `include "axi/typedef.svh" diff --git a/src/axi_lite_dw_converter.sv b/src/axi_lite_dw_converter.sv index f70940674..d8055481f 100644 --- a/src/axi_lite_dw_converter.sv +++ b/src/axi_lite_dw_converter.sv @@ -9,7 +9,7 @@ // specific language governing permissions and limitations under the License. // Authors: -// - Wolfgang Rönninger +// - Wolfgang Roenninger /// # AXI4-Lite data width downsize module. /// diff --git a/src/axi_lite_from_mem.sv b/src/axi_lite_from_mem.sv index 6b5446c6b..e13793b37 100644 --- a/src/axi_lite_from_mem.sv +++ b/src/axi_lite_from_mem.sv @@ -10,6 +10,7 @@ // // Authors: // - Wolfgang Roenninger +// - Nicole Narr /// Protocol adapter which translates memory requests to the AXI4-Lite protocol. /// diff --git a/src/axi_pkg.sv b/src/axi_pkg.sv index 11c0f8ba7..dd60c451e 100644 --- a/src/axi_pkg.sv +++ b/src/axi_pkg.sv @@ -12,8 +12,10 @@ // Authors: // - Andreas Kurth // - Florian Zaruba +// - Thomas Benz // - Wolfgang Roenninger // - Fabian Schuiki +// - Cyril Koenig // - Matheus Cavalcante //! AXI Package diff --git a/src/axi_test.sv b/src/axi_test.sv index 6fd789415..ea621d91e 100644 --- a/src/axi_test.sv +++ b/src/axi_test.sv @@ -13,6 +13,7 @@ // - Andreas Kurth // - Wolfgang Roenninger // - Fabian Schuiki +// - Thomas Benz // - Matheus Cavalcante diff --git a/src/axi_to_detailed_mem.sv b/src/axi_to_detailed_mem.sv index 3e6cfdcab..691a1f5c8 100644 --- a/src/axi_to_detailed_mem.sv +++ b/src/axi_to_detailed_mem.sv @@ -10,6 +10,7 @@ // Authors: // - Michael Rogenmoser +// - Thomas Benz `include "common_cells/registers.svh" /// AXI4+ATOP slave module which translates AXI bursts into a memory stream. diff --git a/src/axi_to_mem.sv b/src/axi_to_mem.sv index e935e69ff..37992d449 100644 --- a/src/axi_to_mem.sv +++ b/src/axi_to_mem.sv @@ -10,6 +10,7 @@ // Authors: // - Michael Rogenmoser +// - Thomas Benz `include "common_cells/registers.svh" /// AXI4+ATOP slave module which translates AXI bursts into a memory stream. diff --git a/src/axi_to_mem_split.sv b/src/axi_to_mem_split.sv index 1d86cc3eb..28ce40831 100644 --- a/src/axi_to_mem_split.sv +++ b/src/axi_to_mem_split.sv @@ -10,6 +10,7 @@ // // Authors: // - Michael Rogenmoser +// - Thomas Benz `include "axi/assign.svh" /// AXI4+ATOP to memory-protocol interconnect. Completely separates the read and write channel to diff --git a/test/tb_axi_lite_dw_converter.sv b/test/tb_axi_lite_dw_converter.sv index 65319b0ad..e376cb1d6 100644 --- a/test/tb_axi_lite_dw_converter.sv +++ b/test/tb_axi_lite_dw_converter.sv @@ -8,7 +8,9 @@ // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. -// Author: Wolfgang Roenninger +// Authors: +// - Wolfgang Roenninger +// - Michael Rogenmoser `include "axi/typedef.svh" diff --git a/test/tb_axi_slave_compare.sv b/test/tb_axi_slave_compare.sv index 45809e5d2..2fa47bdc7 100644 --- a/test/tb_axi_slave_compare.sv +++ b/test/tb_axi_slave_compare.sv @@ -2,7 +2,9 @@ // SPDX-License-Identifier: SHL-0.51 // // Authors: +// - Andreas Kurth // - Thomas Benz +// - Michael Rogenmoser `include "axi/assign.svh" `include "axi/typedef.svh"