Udpdate changelog

CHANGELOG.md

@@ -8,30 +8,55 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 ## Unreleased
 
 ### Added
-- Add `axi_chan_compare.sv`: Non-synthesizable module comparing two AXI channels of the same type
-- Add `axi_bus_compare` and `axi_slave_compare`; two synthesizable verification IPs meant to be used
-  to compare two AXI buses on an FPGA.
-- Add `axi_lite_from_mem` and `axi_from_mem` acting like SRAMs making AXI4 requests downstream.
-- Add `axi_rw_join` and `axi_rw_split` to split/join AXI buses.
-- Add `#_width` functions returning the width of the AXI channels.
-- Add `axi_lite_dw_converter`: Convert the data width of AXI4-Lite transactions. Emmits the
-  appropriate amount of downstream transactions to perform the whole requested access.
-
+- Synthesizable IPs:
+  - `axi_bus_compare` and `axi_slave_compare`; two synthesizable verification IPs meant to be used
+    to compare two AXI buses on an FPGA.
+  - `axi_lite_from_mem` and `axi_from_mem` acting like SRAMs making AXI4 requests downstream.
+  - `axi_lite_dw_converter`: Convert the data width of AXI4-Lite transactions. Emits the
+     appropriate amount of downstream transactions to perform the whole requested access.
+  - `axi_rw_join` and `axi_rw_split` to split/join AXI buses.
+- `CT`-macros allowing to instantiate AXI structs with custom channel names.
+- Testbench IPs:
+  - `axi_chan_compare.sv`: Non-synthesizable module comparing two AXI channels of the same type
+  - Add `axi_file_master` to `axi_test`, allowing file-based AXI verification approaches.
+  - Add `#_width` functions to `axi_test` returning the width of the AXI channels.
 
 ### Changed
-- `axi_demux`: Replace FIFO between AW and W channel by a register plus a counter.  This prevents
-  AWs from being issued to one master port while Ws from another burst are ongoing to another
-  master port.  This is required to prevents deadlocks due to circular waits downstream.
-- `axi_xbar`: Add parameter `PipelineStages` to `axi_pkg::xbar_cfg_t`.  This adds `axi_multicuts`
-  in the crossed connections in the xbar between the demuxes and muxes.
-- `axi_pkg`: Add documentation to `xbar_cfg_t`.
-- Move `mem_to_banks` to `common_cells`.
-- Update `common_cells` from version `v1.26.0` to `v1.27.0`.
+- Synthesizable IPs:
+  - `axi_demux`: Replace FIFO between AW and W channel by a register plus a counter.  This prevents
+    AWs from being issued to one master port while Ws from another burst are ongoing to another
+    master port.  This is required to prevents deadlocks due to circular waits downstream.
+  - Split the `axi_demux` logic and timing decoupling. A new module called `axi_demux_simple` contains
+    the core logic.
+  - `axi_dw_downsizer` uses `axi_pkg::RESP_EXOKAY` as a default value.
+  - Simplify the `casez` in `axi_id_remap`.
+  - Add explicit mapping to the `axi_id_serialize` module.
+  - Expand `axi_to_mem` to `axi_to_detailed_mem` exposing all of AXI's side-signals; namely `id`, `user`,
+    `cache`, `prot`, `qos`, `region`, `atop`. Add possibility to inject `err` and `exokay`.
+  - `axi_xbar`: Add parameter `PipelineStages` to `axi_pkg::xbar_cfg_t`. This adds `axi_multicuts`
+    in the crossed connections in the `xbar` between the *demuxes* and *muxes*. Improve inline
+    documentation.
+  - Move `mem_to_banks` to `common_cells`.
+- `axi_pkg`:
+  - Add documentation to `xbar_cfg_t`.
+  - Improve for better compatibility with *Vivado*.
+- `axi_test:
+  - `axi_rand_lite_slave`: `R` response field is now randomized.
+  - Silence random master and slave.
+  - Properly size-align the address.
 - `axi_pkg`: Define `localparams` to define AXI type widths.
-- `axi_test:axi_rand_lite_slave`: R response field is now random.
+- Update `tb_axi_xbar`.
+- Update `common_cells` from version `v1.26.0` to `v1.27.0`.
+- Tooling:
+  - Use `pulp-platform/pulp-actions/gitlab-ci@v2` in the GitHub CI to communicate with the internal CI.
+  - Bump `DC Shell version` from `2019.12` to `2022.03`
+  - No longer check *ModelSim* versions `10.7e` and `2021.3`, add `2022.3`.
+  - More thorough verification runs for the `xbar`.
+  - Start transitioning from shell script to Makefile to run simulations.
 
 ### Fixed
-
+- `axi_to_mem_banked`: Reduce hardware by properly setting `UniqueIds`.
+- `axi_to_mem_interleaved` and `axi_to_mem_split` properly instantiates a demultiplexer now.
 
 ## 0.38.0 - 2022-09-28