diff --git a/Bender.yml b/Bender.yml index e88148e32..a911bc617 100644 --- a/Bender.yml +++ b/Bender.yml @@ -57,6 +57,13 @@ sources: - src/axi_iw_converter.sv - src/axi_lite_xbar.sv - src/axi_xbar.sv + # Level 5 + - src/axi_xp.sv + - src/axi_dma_backend.sv + - src/axi_dma_burst_reshaper.sv + - src/axi_dma_data_mover.sv + - src/axi_dma_data_path.sv + - src/axi_aw_w_sync.sv - target: synth_test files: @@ -72,6 +79,7 @@ sources: # Level 0 - test/tb_axi_dw_pkg.sv - test/tb_axi_xbar_pkg.sv + - test/tb_axi_xp_pkg.sv # Level 1 - test/tb_axi_addr_test.sv - test/tb_axi_atop_filter.sv @@ -91,3 +99,6 @@ sources: - test/tb_axi_sim_mem.sv - test/tb_axi_to_axi_lite.sv - test/tb_axi_xbar.sv + - test/tb_axi_xp.sv + - test/tb_axi_dma_backend.sv + - test/fixture_axi_dma_backend.sv diff --git a/CHANGELOG.md b/CHANGELOG.md index a9f5e91f8..0a07bab42 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -8,6 +8,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. ## Unreleased ### Added +- `axi_xp`: Crosspoint with homomorphous slave and master ports. ### Changed diff --git a/compile.tcl b/compile.tcl new file mode 100644 index 000000000..cb56f4c5e --- /dev/null +++ b/compile.tcl @@ -0,0 +1,356 @@ +# This script was generated automatically by bender. +set ROOT "/home/jvikram/crosspoint/axi" + +if {[catch {vlog -incr -sv \ + -svinputport=compat \ + -override_timescale 1ns/1ps \ + -suppress 2583 \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/include" \ + "+incdir+$ROOT/include" \ + "$ROOT/.bender/git/checkouts/common_verification-9891eaba585d537d/src/clk_rst_gen.sv" \ + "$ROOT/.bender/git/checkouts/common_verification-9891eaba585d537d/src/rand_id_queue.sv" \ + "$ROOT/.bender/git/checkouts/common_verification-9891eaba585d537d/src/rand_stream_mst.sv" \ + "$ROOT/.bender/git/checkouts/common_verification-9891eaba585d537d/src/rand_synch_holdable_driver.sv" \ + "$ROOT/.bender/git/checkouts/common_verification-9891eaba585d537d/src/rand_verif_pkg.sv" \ + "$ROOT/.bender/git/checkouts/common_verification-9891eaba585d537d/src/sim_timeout.sv" \ + "$ROOT/.bender/git/checkouts/common_verification-9891eaba585d537d/src/rand_synch_driver.sv" \ + "$ROOT/.bender/git/checkouts/common_verification-9891eaba585d537d/src/rand_stream_slv.sv" +}]} {return 1} + +if {[catch {vlog -incr -sv \ + -svinputport=compat \ + -override_timescale 1ns/1ps \ + -suppress 2583 \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/include" \ + "+incdir+$ROOT/include" \ + "$ROOT/.bender/git/checkouts/common_verification-9891eaba585d537d/test/tb_clk_rst_gen.sv" +}]} {return 1} + +if {[catch {vlog -incr -sv \ + -svinputport=compat \ + -override_timescale 1ns/1ps \ + -suppress 2583 \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/include" \ + "+incdir+$ROOT/include" \ + "$ROOT/.bender/git/checkouts/tech_cells_generic-9dd79c3e4b5c8549/src/rtl/tc_sram.sv" +}]} {return 1} + +if {[catch {vlog -incr -sv \ + -svinputport=compat \ + -override_timescale 1ns/1ps \ + -suppress 2583 \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/include" \ + "+incdir+$ROOT/include" \ + "$ROOT/.bender/git/checkouts/tech_cells_generic-9dd79c3e4b5c8549/src/rtl/tc_clk.sv" +}]} {return 1} + +if {[catch {vlog -incr -sv \ + -svinputport=compat \ + -override_timescale 1ns/1ps \ + -suppress 2583 \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/include" \ + "+incdir+$ROOT/include" \ + "$ROOT/.bender/git/checkouts/tech_cells_generic-9dd79c3e4b5c8549/src/deprecated/cluster_pwr_cells.sv" \ + "$ROOT/.bender/git/checkouts/tech_cells_generic-9dd79c3e4b5c8549/src/deprecated/generic_memory.sv" \ + "$ROOT/.bender/git/checkouts/tech_cells_generic-9dd79c3e4b5c8549/src/deprecated/generic_rom.sv" \ + "$ROOT/.bender/git/checkouts/tech_cells_generic-9dd79c3e4b5c8549/src/deprecated/pad_functional.sv" \ + "$ROOT/.bender/git/checkouts/tech_cells_generic-9dd79c3e4b5c8549/src/deprecated/pulp_buffer.sv" \ + "$ROOT/.bender/git/checkouts/tech_cells_generic-9dd79c3e4b5c8549/src/deprecated/pulp_pwr_cells.sv" +}]} {return 1} + +if {[catch {vlog -incr -sv \ + -svinputport=compat \ + -override_timescale 1ns/1ps \ + -suppress 2583 \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/include" \ + "+incdir+$ROOT/include" \ + "$ROOT/.bender/git/checkouts/tech_cells_generic-9dd79c3e4b5c8549/src/tc_pwr.sv" +}]} {return 1} + +if {[catch {vlog -incr -sv \ + -svinputport=compat \ + -override_timescale 1ns/1ps \ + -suppress 2583 \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/include" \ + "+incdir+$ROOT/include" \ + "$ROOT/.bender/git/checkouts/tech_cells_generic-9dd79c3e4b5c8549/test/tb_tc_sram.sv" +}]} {return 1} + +if {[catch {vlog -incr -sv \ + -svinputport=compat \ + -override_timescale 1ns/1ps \ + -suppress 2583 \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/include" \ + "+incdir+$ROOT/include" \ + "$ROOT/.bender/git/checkouts/tech_cells_generic-9dd79c3e4b5c8549/src/deprecated/pulp_clock_gating_async.sv" \ + "$ROOT/.bender/git/checkouts/tech_cells_generic-9dd79c3e4b5c8549/src/deprecated/cluster_clk_cells.sv" \ + "$ROOT/.bender/git/checkouts/tech_cells_generic-9dd79c3e4b5c8549/src/deprecated/pulp_clk_cells.sv" +}]} {return 1} + +if {[catch {vlog -incr -sv \ + -svinputport=compat \ + -override_timescale 1ns/1ps \ + -suppress 2583 \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/include" \ + "+incdir+$ROOT/include" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/binary_to_gray.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/cb_filter_pkg.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/cc_onehot.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/cf_math_pkg.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/clk_int_div.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/delta_counter.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/ecc_pkg.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/edge_propagator_tx.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/exp_backoff.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/fifo_v3.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/gray_to_binary.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/isochronous_4phase_handshake.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/isochronous_spill_register.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/lfsr.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/lfsr_16bit.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/lfsr_8bit.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/mv_filter.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/onehot_to_bin.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/plru_tree.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/popcount.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/rr_arb_tree.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/rstgen_bypass.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/serial_deglitch.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/shift_reg.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/spill_register_flushable.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/stream_demux.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/stream_filter.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/stream_fork.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/stream_intf.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/stream_join.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/stream_mux.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/sub_per_hash.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/sync.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/sync_wedge.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/unread.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/cdc_reset_ctrlr_pkg.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/cdc_2phase.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/cdc_4phase.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/addr_decode.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/cb_filter.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/cdc_fifo_2phase.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/counter.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/ecc_decode.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/ecc_encode.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/edge_detect.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/lzc.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/max_counter.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/rstgen.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/spill_register.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/stream_delay.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/stream_fifo.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/stream_fork_dynamic.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/cdc_reset_ctrlr.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/cdc_fifo_gray.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/fall_through_register.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/id_queue.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/stream_to_mem.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/stream_arbiter_flushable.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/stream_register.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/stream_xbar.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/cdc_fifo_gray_clearable.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/cdc_2phase_clearable.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/stream_arbiter.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/stream_omega_net.sv" +}]} {return 1} + +if {[catch {vlog -incr -sv \ + -svinputport=compat \ + -override_timescale 1ns/1ps \ + -suppress 2583 \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/include" \ + "+incdir+$ROOT/include" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/deprecated/sram.sv" +}]} {return 1} + +if {[catch {vlog -incr -sv \ + -svinputport=compat \ + -override_timescale 1ns/1ps \ + -suppress 2583 \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/include" \ + "+incdir+$ROOT/include" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/test/addr_decode_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/test/cb_filter_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/test/cdc_2phase_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/test/cdc_2phase_clearable_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/test/cdc_fifo_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/test/cdc_fifo_clearable_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/test/fifo_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/test/graycode_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/test/id_queue_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/test/popcount_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/test/rr_arb_tree_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/test/stream_test.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/test/stream_register_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/test/stream_to_mem_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/test/sub_per_hash_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/test/isochronous_crossing_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/test/stream_omega_net_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/test/stream_xbar_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/test/clk_int_div_tb.sv" +}]} {return 1} + +if {[catch {vlog -incr -sv \ + -svinputport=compat \ + -override_timescale 1ns/1ps \ + -suppress 2583 \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/include" \ + "+incdir+$ROOT/include" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/deprecated/clock_divider_counter.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/deprecated/clk_div.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/deprecated/find_first_one.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/deprecated/generic_LFSR_8bit.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/deprecated/generic_fifo.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/deprecated/prioarbiter.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/deprecated/pulp_sync.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/deprecated/pulp_sync_wedge.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/deprecated/rrarbiter.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/deprecated/clock_divider.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/deprecated/fifo_v2.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/deprecated/fifo_v1.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/edge_propagator_ack.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/edge_propagator.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/src/edge_propagator_rx.sv" +}]} {return 1} + +if {[catch {vlog -incr -sv \ + -svinputport=compat \ + -override_timescale 1ns/1ps \ + -suppress 2583 \ + -lint -pedanticerrors \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/include" \ + "+incdir+$ROOT/include" \ + "$ROOT/src/axi_pkg.sv" \ + "$ROOT/src/axi_intf.sv" \ + "$ROOT/src/axi_atop_filter.sv" \ + "$ROOT/src/axi_burst_splitter.sv" \ + "$ROOT/src/axi_cdc_dst.sv" \ + "$ROOT/src/axi_cdc_src.sv" \ + "$ROOT/src/axi_cut.sv" \ + "$ROOT/src/axi_delayer.sv" \ + "$ROOT/src/axi_demux.sv" \ + "$ROOT/src/axi_dw_downsizer.sv" \ + "$ROOT/src/axi_dw_upsizer.sv" \ + "$ROOT/src/axi_id_remap.sv" \ + "$ROOT/src/axi_id_prepend.sv" \ + "$ROOT/src/axi_isolate.sv" \ + "$ROOT/src/axi_join.sv" \ + "$ROOT/src/axi_lite_demux.sv" \ + "$ROOT/src/axi_lite_join.sv" \ + "$ROOT/src/axi_lite_mailbox.sv" \ + "$ROOT/src/axi_lite_mux.sv" \ + "$ROOT/src/axi_lite_regs.sv" \ + "$ROOT/src/axi_lite_to_apb.sv" \ + "$ROOT/src/axi_lite_to_axi.sv" \ + "$ROOT/src/axi_modify_address.sv" \ + "$ROOT/src/axi_mux.sv" \ + "$ROOT/src/axi_serializer.sv" \ + "$ROOT/src/axi_cdc.sv" \ + "$ROOT/src/axi_err_slv.sv" \ + "$ROOT/src/axi_dw_converter.sv" \ + "$ROOT/src/axi_id_serialize.sv" \ + "$ROOT/src/axi_multicut.sv" \ + "$ROOT/src/axi_to_axi_lite.sv" \ + "$ROOT/src/axi_iw_converter.sv" \ + "$ROOT/src/axi_lite_xbar.sv" \ + "$ROOT/src/axi_xbar.sv" \ + "$ROOT/src/axi_xp.sv" \ + "$ROOT/src/axi_dma_backend.sv" \ + "$ROOT/src/axi_dma_burst_reshaper.sv" \ + "$ROOT/src/axi_dma_data_mover.sv" \ + "$ROOT/src/axi_dma_data_path.sv" \ + "$ROOT/src/axi_aw_w_sync.sv" +}]} {return 1} + +if {[catch {vlog -incr -sv \ + -svinputport=compat \ + -override_timescale 1ns/1ps \ + -suppress 2583 \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/include" \ + "+incdir+$ROOT/include" \ + "$ROOT/src/axi_sim_mem.sv" \ + "$ROOT/src/axi_test.sv" +}]} {return 1} + +if {[catch {vlog -incr -sv \ + -svinputport=compat \ + -override_timescale 1ns/1ps \ + -suppress 2583 \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-ecf39c06fbbac60d/include" \ + "+incdir+$ROOT/include" \ + "$ROOT/test/tb_axi_dw_pkg.sv" \ + "$ROOT/test/tb_axi_xbar_pkg.sv" \ + "$ROOT/test/tb_axi_xp_pkg.sv" \ + "$ROOT/test/tb_axi_addr_test.sv" \ + "$ROOT/test/tb_axi_atop_filter.sv" \ + "$ROOT/test/tb_axi_cdc.sv" \ + "$ROOT/test/tb_axi_delayer.sv" \ + "$ROOT/test/tb_axi_dw_downsizer.sv" \ + "$ROOT/test/tb_axi_dw_upsizer.sv" \ + "$ROOT/test/tb_axi_isolate.sv" \ + "$ROOT/test/tb_axi_lite_mailbox.sv" \ + "$ROOT/test/tb_axi_lite_regs.sv" \ + "$ROOT/test/tb_axi_iw_converter.sv" \ + "$ROOT/test/tb_axi_lite_to_apb.sv" \ + "$ROOT/test/tb_axi_lite_to_axi.sv" \ + "$ROOT/test/tb_axi_lite_xbar.sv" \ + "$ROOT/test/tb_axi_modify_address.sv" \ + "$ROOT/test/tb_axi_serializer.sv" \ + "$ROOT/test/tb_axi_sim_mem.sv" \ + "$ROOT/test/tb_axi_to_axi_lite.sv" \ + "$ROOT/test/tb_axi_xbar.sv" \ + "$ROOT/test/tb_axi_xp.sv" \ + "$ROOT/test/tb_axi_dma_backend.sv" \ + "$ROOT/test/fixture_axi_dma_backend.sv" +}]} {return 1} +return 0 diff --git a/parse_trace.py b/parse_trace.py new file mode 100644 index 000000000..c3962cdcb --- /dev/null +++ b/parse_trace.py @@ -0,0 +1,31 @@ +#GVSoC trace files input +f1 = open("traces_pip_16cl.txt", 'r') +#testbench dma input traces +f2 = open("traces_pip_16cl_tb.txt", 'w+') +total_bytes=0 +f1_lines = f1.readlines() +for l in f1_lines: + try: + key_word1 = list(l.split())[2] + key_word2 = list(l.split())[11] + key_word3 = list(l.split())[13] + key_word4 = list(l.split())[15] + if key_word1[-1] == 'e': + if key_word1[29] == '/': + f2.write('0'+' '+key_word2[:-1]+' '+key_word3[:-1]+' '+key_word4[:-1]+'\n') + total_bytes = total_bytes + int(key_word4[2:-1], base=16) + #print(int(key_word4[2:-1], base=16)) + elif key_word1[29] == '_': + if key_word1[31] == '/': + f2.write(key_word1[30]+' '+key_word2[:-1]+' '+key_word3[:-1]+' '+key_word4[:-1]+'\n') + total_bytes = total_bytes + int(key_word4[2:-1], base=16) + #print(int(key_word4[2:-1], base=16)) + else: + f2.write(key_word1[30:32]+' '+key_word2[:-1]+' '+key_word3[:-1]+' '+key_word4[:-1]+'\n') + total_bytes = total_bytes + int(key_word4[2:-1], base=16) + except: + continue + +print(total_bytes) +f1.close() +f2.close() diff --git a/scripts/run_vsim.sh b/scripts/run_vsim.sh index c72be8e8d..7649f0831 100755 --- a/scripts/run_vsim.sh +++ b/scripts/run_vsim.sh @@ -29,7 +29,7 @@ SEEDS=(0) call_vsim() { for seed in ${SEEDS[@]}; do - echo "run -all" | $VSIM -sv_seed $seed "$@" | tee vsim.log 2>&1 + echo "run -all" | $VSIM -sv_seed $seed "$@" | tee vsim.log 2>&1 #-gui grep "Errors: 0," vsim.log done } @@ -174,6 +174,24 @@ exec_test() { done done ;; + axi_xp) + for NumMst in 1 4; do + for NumSlv in 1 4; do + for Atop in 0 1; do + for Exclusive in 0 1; do + for UniqueIds in 0 1; do + call_vsim tb_axi_xp -gTbNumMst=$NumMst -gTbNumSlv=$NumSlv \ + -gTbEnAtop=$Atop -gTbEnExcl=$Exclusive \ + -gTbUniqueIds=$UniqueIds + done + done + done + done + done + ;; + axi_dma_backend) + call_vsim tb_$1 -voptargs="+acc +cover=bcesfx" + ;; *) call_vsim tb_$1 -t 1ns -coverage -voptargs="+acc +cover=bcesfx" ;; diff --git a/src/axi_aw_w_sync.sv b/src/axi_aw_w_sync.sv new file mode 100644 index 000000000..cf0c86154 --- /dev/null +++ b/src/axi_aw_w_sync.sv @@ -0,0 +1,128 @@ +/* Copyright 2021 ETH Zurich and University of Bologna. + * Copyright and related rights are licensed under the Solderpad Hardware + * License, Version 0.51 (the “License”); you may not use this file except in + * compliance with the License. You may obtain a copy of the License at + * http: //solderpad.org/licenses/SHL-0.51. Unless required by applicable law + * or agreed to in writing, software, hardware and materials distributed under + * this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR + * CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * Author: Michael Rogenmoser + * Date: 15.02.2022 + * + */ + +/// Only allows passing of AW if corresponding W is valid. +/// Only allows passing of W if corresponding AW is valid or sent. + +`include "axi/assign.svh" +`include "common_cells/registers.svh" + +module axi_aw_w_sync #( + parameter type axi_req_t = logic, + parameter type axi_resp_t = logic +) ( + input logic clk_i, + input logic rst_ni, + + input axi_req_t slv_req_i, + output axi_resp_t slv_resp_o, + + output axi_req_t mst_req_o, + input axi_resp_t mst_resp_i +); + + `AXI_ASSIGN_AR_STRUCT(mst_req_o.ar, slv_req_i.ar) + assign mst_req_o.ar_valid = slv_req_i.ar_valid; + assign slv_resp_o.ar_ready = mst_resp_i.ar_ready; + `AXI_ASSIGN_R_STRUCT(slv_resp_o.r, mst_resp_i.r) + assign slv_resp_o.r_valid = mst_resp_i.r_valid; + assign mst_req_o.r_ready = slv_req_i.r_ready; + `AXI_ASSIGN_B_STRUCT(slv_resp_o.b, mst_resp_i.b) + assign slv_resp_o.b_valid = mst_resp_i.b_valid; + assign mst_req_o.b_ready = slv_req_i.b_ready; + + `AXI_ASSIGN_AW_STRUCT(mst_req_o.aw, slv_req_i.aw) + `AXI_ASSIGN_W_STRUCT(mst_req_o.w, slv_req_i.w) + + logic aw_valid, w_valid; + logic w_completed_d, w_completed_q; + `FF(w_completed_q, w_completed_d, 1'b1) + + + // AW is valid when previous write completed and current AW and W are valid + assign aw_valid = w_completed_q && slv_req_i.aw_valid && slv_req_i.w_valid; + + // W is valid when corresponding AW is valid or sent + assign w_valid = slv_req_i.w_valid && (!w_completed_q || (aw_valid && mst_resp_i.aw_ready)); // This is probably pretty bad for timing + + always_comb begin + w_completed_d = w_completed_q; + // reset w_completed to 0 when a new AW request happens + if (aw_valid && mst_resp_i.aw_ready) begin + w_completed_d = 1'b0; + end + // assign w_completed to w_last when W handshake is done and W is ongoing + if (slv_req_i.w_valid && slv_resp_o.w_ready) begin + w_completed_d = slv_req_i.w.last; + end + end + + assign mst_req_o.w_valid = w_valid; + assign slv_resp_o.w_ready = w_valid && mst_resp_i.w_ready; + assign mst_req_o.aw_valid = aw_valid; + assign slv_resp_o.aw_ready = aw_valid && mst_resp_i.aw_ready; + +endmodule + +`include "axi/typedef.svh" + +module axi_aw_w_sync_intf #( + parameter int unsigned AXI_ADDR_WIDTH = 0, + parameter int unsigned AXI_DATA_WIDTH = 0, + parameter int unsigned AXI_ID_WIDTH = 0, + parameter int unsigned AXI_USER_WIDTH = 0 +) ( + input logic clk_i, + input logic rst_ni, + AXI_BUS.Slave in, + AXI_BUS.Master out +); + + typedef logic [ AXI_ID_WIDTH-1:0] id_t; + typedef logic [ AXI_ADDR_WIDTH-1:0] addr_t; + typedef logic [ AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; + typedef logic [ AXI_USER_WIDTH-1:0] user_t; + + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) + `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) + + axi_req_t slv_req, mst_req; + axi_resp_t slv_resp, mst_resp; + + `AXI_ASSIGN_TO_REQ(slv_req, in) + `AXI_ASSIGN_FROM_RESP(in, slv_resp) + + `AXI_ASSIGN_FROM_REQ(out, mst_req) + `AXI_ASSIGN_TO_RESP(mst_resp, out) + + axi_aw_w_sync #( + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ) + ) i_axi_aw_w_sync ( + .clk_i, + .rst_ni, + .slv_req_i ( slv_req ), + .slv_resp_o ( slv_resp ), + .mst_req_o ( mst_req ), + .mst_resp_i ( mst_resp ) + ); + +endmodule \ No newline at end of file diff --git a/src/axi_dma_backend.sv b/src/axi_dma_backend.sv new file mode 100644 index 000000000..d665ac48d --- /dev/null +++ b/src/axi_dma_backend.sv @@ -0,0 +1,588 @@ +// Copyright (c) 2020 ETH Zurich, University of Bologna +// All rights reserved. +// +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// +// Thomas Benz + +/// The backend implements the generic 1D data transfer on an AXI BUS +module axi_dma_backend #( + /// Data width of the AXI bus + parameter int unsigned DataWidth = -1, + /// Address width of the AXI bus + parameter int unsigned AddrWidth = -1, + /// ID width of the AXI bus + parameter int unsigned IdWidth = -1, + /// Number of AX beats that can be in-flight + parameter int unsigned AxReqFifoDepth = -1, + /// Number of generic 1D requests that can be buffered + parameter int unsigned TransFifoDepth = -1, + /// Number of elements the realignment buffer can hold. To achieve + /// full performance a depth of 3 is minimally required. + parameter int unsigned BufferDepth = -1, + /// AXI4+ATOP request struct definition. + parameter type axi_req_t = logic, + /// AXI4+ATOP response struct definition. + parameter type axi_res_t = logic, + /// Arbitrary 1D burst request definition: + /// - `id`: the AXI id used - this id should be constant, as the DMA does not support reordering + /// - `src`, `dst`: source and destination address, same width as the AXI 4 channels + /// - `num_bytes`: the length of the contiguous 1D transfer requested, can be up to 32/64 bit long + /// num_bytes will be interpreted as an unsigned number + /// A value of 0 will cause the backend to discard the transfer prematurely + /// - `cache_src`, `cache_dst`: the configuration of the cache fields in the AX beats + /// - `burst_src`, `burst_dst`: currently only incremental bursts are supported (`2'b01`) + /// - `decouple_rw`: if set to true, there is no longer exactly one AXI write_request issued for + /// every read request. This mode can improve performance of unaligned transfers when + /// crossing the AXI page boundaries. + /// - `deburst`: if set, the DMA will split all bursts in single transfers + /// - `serialize`: if set, the DMA will only send AX belonging to a given Arbitrary 1D burst request + /// at a time. This is default behavior to prevent deadlocks. Setting `serialize` to + /// zero violates the AXI4+ATOP specification. + parameter type burst_req_t = logic, + /// Give each DMA backend a unique id + parameter int unsigned DmaIdWidth = -1, + /// Enable or disable tracing + parameter bit DmaTracing = 0 + +) ( + /// Clock + input logic clk_i, + /// Asynchronous reset, active low + input logic rst_ni, + /// AXI4+ATOP master request + output axi_req_t axi_dma_req_o, + /// AXI4+ATOP master response + input axi_res_t axi_dma_res_i, + /// Arbitrary 1D burst request + input burst_req_t burst_req_i, + /// Handshake: 1D burst request is valid + input logic valid_i, + /// Handshake: 1D burst can be accepted + output logic ready_o, + /// High if the backend is idle + output logic backend_idle_o, + /// Event: a 1D burst request has completed + output logic trans_complete_o, + /// unique DMA id + input logic [DmaIdWidth-1:0] dma_id_i +); + + /// Number of bytes per word + localparam int unsigned StrobeWidth = DataWidth / 8; + /// Offset width + localparam int unsigned OffsetWidth = $clog2(StrobeWidth); + /// Offset type + typedef logic [OffsetWidth-1:0] offset_t; + /// Address Type + typedef logic [ AddrWidth-1:0] addr_t; + /// AXI ID Type + typedef logic [ IdWidth-1:0] axi_id_t; + + /// id: AXI id + /// last: last transaction in burst + /// address: address of burst + /// length: burst length + /// size: bytes in each burst + /// burst: burst type; only INC supported + /// cache: cache type + typedef struct packed { + axi_id_t id; + logic last; + addr_t addr; + axi_pkg::len_t len; + axi_pkg::size_t size; + axi_pkg::burst_t burst; + axi_pkg::cache_t cache; + } desc_ax_t; + + /// offset: initial misalignment + /// tailer: final misalignment + /// shift: amount the data needs to be shifted to realign it + typedef struct packed { + offset_t offset; + offset_t tailer; + offset_t shift; + } desc_r_t; + + /// offset: initial misalignment + /// tailer: final misalignment + /// num_beats: number of beats in the burst + /// is_single: burst length is 0 + typedef struct packed { + offset_t offset; + offset_t tailer; + axi_pkg::len_t num_beats; + logic is_single; + } desc_w_t; + + /// Write request definition + typedef struct packed { + desc_ax_t aw; + desc_w_t w; + } write_req_t; + + /// Read request definition + typedef struct packed { + desc_ax_t ar; + desc_r_t r; + } read_req_t; + + //-------------------------------------- + // Assertions + //-------------------------------------- + // pragma translate_off + `ifndef VERILATOR + initial begin + assert (DataWidth inside {16, 32, 64, 128, 256, 512, 1024}) + else $fatal(1, "16 <= DataWidth <= 1024"); + assert (AddrWidth >= 32 & AddrWidth <= 128) + else $fatal(1, " 8 <= AddrWidth <= 128"); + end + `endif + // pragma translate_on + + //-------------------------------------- + // Request Fifo + //-------------------------------------- + burst_req_t burst_req; + logic burst_req_empty; + logic burst_req_pop; + logic burst_req_full; + + // buffer the input requests in a fifo + fifo_v3 #( + .dtype ( burst_req_t ), + .DEPTH ( TransFifoDepth ) + ) i_burst_request_fifo ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i( 1'b0 ), + .full_o ( burst_req_full ), + .empty_o ( burst_req_empty ), + .usage_o ( ), + .data_i ( burst_req_i ), + .push_i ( valid_i && ready_o ), + .data_o ( burst_req ), + .pop_i ( burst_req_pop ) + ); + + assign ready_o = !burst_req_full; + + //-------------------------------------- + // Burst reshaper + //-------------------------------------- + write_req_t write_req; + read_req_t read_req; + + logic read_req_valid; + logic read_req_ready; + logic write_req_valid; + logic write_req_ready; + + // send the next burst either immediately or once the last burst + // has been completed. The former mode is not AXI4+ATOP spec + // conform and may result in deadlocks! + logic in_flight_d, in_flight_q; + logic burst_valid; + always_comb begin : proc_select_burst_valid + if (burst_req.serialize) begin + // AXI4-conform behavior. As both the buffer and the memory system + // assume in-order operation. + burst_valid = ~burst_req_empty & (~in_flight_q | trans_complete_o); + end else begin + // legacy, non-AXI4-conform behavior. Send as many AX as possible + // This can lead to deadlocks due to in-memory reordering + burst_valid = ~burst_req_empty; + end + end + + // transforms arbitrary burst into AXI conform bursts + axi_dma_burst_reshaper #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .burst_req_t ( burst_req_t ), + .read_req_t ( read_req_t ), + .write_req_t ( write_req_t ) + ) i_axi_dma_burst_reshaper ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .burst_req_i ( burst_req ), + .valid_i ( burst_valid ), + .ready_o ( burst_req_pop ), + .write_req_o ( write_req ), + .read_req_o ( read_req ), + .r_valid_o ( read_req_valid ), + .r_ready_i ( read_req_ready ), + .w_valid_o ( write_req_valid ), + .w_ready_i ( write_req_ready ) + ); + + //-------------------------------------- + // Data mover + //-------------------------------------- + axi_dma_data_mover #( + .DataWidth ( DataWidth ), + .ReqFifoDepth ( AxReqFifoDepth ), + .BufferDepth ( BufferDepth ), + .read_req_t ( read_req_t ), + .write_req_t ( write_req_t ), + .axi_req_t ( axi_req_t ), + .axi_res_t ( axi_res_t ), + .desc_ax_t ( desc_ax_t ), + .desc_r_t ( desc_r_t ), + .desc_w_t ( desc_w_t ) + ) i_axi_dma_data_mover ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .axi_dma_req_o ( axi_dma_req_o ), + .axi_dma_res_i ( axi_dma_res_i ), + .read_req_i ( read_req ), + .write_req_i ( write_req ), + .r_valid_i ( read_req_valid ), + .r_ready_o ( read_req_ready ), + .w_valid_i ( write_req_valid ), + .w_ready_o ( write_req_ready ), + .data_mover_idle_o ( backend_idle_o ), + .trans_complete_o ( trans_complete_o ) + ); + + //-------------------------------------- + // In-flight check + //-------------------------------------- + // to conform to the AXI4+ATOP spec: only send a burst + // once the last one has been completed . This check can be overridden + always_comb begin : proc_in_flight_check + + // default: last state + in_flight_d = in_flight_q; + + // new transfer: set in-flight to one + if (burst_req_pop & ~burst_req_empty) begin + in_flight_d = 1; + end else begin + // no new transfer and the old retires -> idle + if (trans_complete_o) begin + in_flight_d = 0; + end + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin : proc_in_flight_check_state + if(~rst_ni) begin + in_flight_q <= 0; + end else begin + in_flight_q <= in_flight_d; + end + end + + //-------------------------------------- + // Tracer + //-------------------------------------- + //pragma translate_off + `ifndef SYNTHESYS + `ifndef VERILATOR + generate if (DmaTracing) begin : gen_dma_tracer + string fn; + integer f; + + logic [DataWidth/8-1:0][BufferDepth-1:0][7:0] buffer_mem; + + // open file + initial begin + #1; + $sformat(fn, "dma_trace_%05x.log", dma_id_i); + f = $fopen(fn, "w"); + $display("[Tracer] Logging DMA %d to %s", dma_id_i, fn); + end + + // access buffer memory storage + for(genvar d = 0; d < BufferDepth; d++) begin + for(genvar i = 0; i < DataWidth/8-1; i++) begin + assign buffer_mem[i][d] = + i_axi_dma_data_mover.i_axi_dma_data_path.fifo_buffer[i].i_fifo_buffer.mem_q[d]; + end + end + + // do the tracing + always_ff @(posedge clk_i) begin : proc_tracer + // dict + automatic longint dma_meta [string]; + automatic longint dma_backend [string]; + automatic longint dma_burst_res [string]; + automatic longint dma_data_mover [string]; + automatic logic [DataWidth-1:0] dma_data_path [string]; + automatic string dma_string; + + // start of python dict + dma_string = "{"; + + // we do not dump while reset + if (rst_ni) begin + + // commented signals are currently not used by the python golden model :) + + //-------------------------------------- + // Metadata + //-------------------------------------- + dma_meta = '{ + // time + "time" : $time(), + "DataWidth" : DataWidth, + "AddrWidth" : AddrWidth, + "IdWidth" : IdWidth, + "AxReqFifoDepth" : AxReqFifoDepth, + "TransFifoDepth" : TransFifoDepth, + "BufferDepth" : BufferDepth + }; + + //-------------------------------------- + // Backend + //-------------------------------------- + dma_backend = '{ + // dma backend interface + "backend_burst_req_id" : burst_req_i.id, + "backend_burst_req_src" : burst_req_i.src, + "backend_burst_req_dst" : burst_req_i.dst, + "backend_burst_req_num_bytes" : burst_req_i.num_bytes, + // "backend_burst_req_cache_src" : burst_req_i.cache_src, + // "backend_burst_req_cache_dst" : burst_req_i.cache_dst, + // "backend_burst_req_burst_src" : burst_req_i.burst_src, + // "backend_burst_req_burst_dst" : burst_req_i.burst_dst, + "backend_burst_req_burst_decouple_rw" : burst_req_i.decouple_rw, + "backend_burst_req_burst_deburst" : burst_req_i.deburst, + "backend_burst_req_valid" : valid_i, + "backend_burst_req_ready" : ready_o, + "backend_idle" : backend_idle_o, + "transfer_completed" : trans_complete_o + }; + + //-------------------------------------- + // Burst Reshaper + //-------------------------------------- + dma_burst_res = '{ + // burst request + "burst_reshaper_burst_req_id" : i_axi_dma_burst_reshaper.burst_req_i.id, + "burst_reshaper_burst_req_src" : i_axi_dma_burst_reshaper.burst_req_i.src, + "burst_reshaper_burst_req_dst" : i_axi_dma_burst_reshaper.burst_req_i.dst, + "burst_reshaper_burst_req_num_bytes" : i_axi_dma_burst_reshaper.burst_req_i.num_bytes, + // "burst_reshaper_burst_req_cache_src" : i_axi_dma_burst_reshaper.burst_req_i.cache_src, + // "burst_reshaper_burst_req_cache_dst" : i_axi_dma_burst_reshaper.burst_req_i.cache_dst, + // "burst_reshaper_burst_req_burst_src" : i_axi_dma_burst_reshaper.burst_req_i.burst_src, + // "burst_reshaper_burst_req_burst_dst" : i_axi_dma_burst_reshaper.burst_req_i.burst_dst, + "burst_reshaper_burst_req_decouple_rw" : i_axi_dma_burst_reshaper.burst_req_i.decouple_rw, + "burst_reshaper_burst_req_deburst" : i_axi_dma_burst_reshaper.burst_req_i.deburst, + "burst_reshaper_burst_req_valid" : i_axi_dma_burst_reshaper.valid_i, + "burst_reshaper_burst_req_ready" : i_axi_dma_burst_reshaper.ready_o, + // write request + "burst_reshaper_write_req_aw_id" : i_axi_dma_burst_reshaper.write_req_o.aw.id, + "burst_reshaper_write_req_aw_last" : i_axi_dma_burst_reshaper.write_req_o.aw.last, + "burst_reshaper_write_req_aw_addr" : i_axi_dma_burst_reshaper.write_req_o.aw.addr, + "burst_reshaper_write_req_aw_len" : i_axi_dma_burst_reshaper.write_req_o.aw.len, + "burst_reshaper_write_req_aw_size" : i_axi_dma_burst_reshaper.write_req_o.aw.size, + "burst_reshaper_write_req_aw_burst" : i_axi_dma_burst_reshaper.write_req_o.aw.burst, + "burst_reshaper_write_req_aw_cache" : i_axi_dma_burst_reshaper.write_req_o.aw.cache, + "burst_reshaper_write_req_w_offset" : i_axi_dma_burst_reshaper.write_req_o.w.offset, + "burst_reshaper_write_req_w_tailer" : i_axi_dma_burst_reshaper.write_req_o.w.tailer, + "burst_reshaper_write_req_w_num_beats" : i_axi_dma_burst_reshaper.write_req_o.w.num_beats, + // "burst_reshaper_write_req_w_is_single" : i_axi_dma_burst_reshaper.write_req_o.w.is_single, + "burst_reshaper_write_req_valid" : i_axi_dma_burst_reshaper.w_valid_o, + "burst_reshaper_write_req_ready" : i_axi_dma_burst_reshaper.w_ready_i, + // read request + "burst_reshaper_read_req_ar_id" : i_axi_dma_burst_reshaper.read_req_o.ar.id, + "burst_reshaper_read_req_ar_last" : i_axi_dma_burst_reshaper.read_req_o.ar.last, + "burst_reshaper_read_req_ar_addr" : i_axi_dma_burst_reshaper.read_req_o.ar.addr, + "burst_reshaper_read_req_ar_len" : i_axi_dma_burst_reshaper.read_req_o.ar.len, + "burst_reshaper_read_req_ar_size" : i_axi_dma_burst_reshaper.read_req_o.ar.size, + "burst_reshaper_read_req_ar_burst" : i_axi_dma_burst_reshaper.read_req_o.ar.burst, + "burst_reshaper_read_req_ar_cache" : i_axi_dma_burst_reshaper.read_req_o.ar.cache, + "burst_reshaper_read_req_r_offset" : i_axi_dma_burst_reshaper.read_req_o.r.offset, + "burst_reshaper_read_req_r_tailer" : i_axi_dma_burst_reshaper.read_req_o.r.tailer, + "burst_reshaper_read_req_r_shift" : i_axi_dma_burst_reshaper.read_req_o.r.shift, + "burst_reshaper_read_req_valid" : i_axi_dma_burst_reshaper.r_valid_o, + "burst_reshaper_read_req_ready" : i_axi_dma_burst_reshaper.r_ready_i// , + // current burst + // "burst_reshaper_burst_src_id" : i_axi_dma_burst_reshaper.burst_q.src.id, + // "burst_reshaper_burst_src_addr" : i_axi_dma_burst_reshaper.burst_q.src.addr, + // "burst_reshaper_burst_src_num_bytes" : i_axi_dma_burst_reshaper.burst_q.src.num_bytes, + // "burst_reshaper_burst_src_cache" : i_axi_dma_burst_reshaper.burst_q.src.cache, + // "burst_reshaper_burst_src_burst" : i_axi_dma_burst_reshaper.burst_q.src.burst, + // "burst_reshaper_burst_src_valid" : i_axi_dma_burst_reshaper.burst_q.src.valid, + // "burst_reshaper_burst_dst_id" : i_axi_dma_burst_reshaper.burst_q.dst.id, + // "burst_reshaper_burst_dst_addr" : i_axi_dma_burst_reshaper.burst_q.dst.addr, + // "burst_reshaper_burst_dst_num_bytes" : i_axi_dma_burst_reshaper.burst_q.dst.num_bytes, + // "burst_reshaper_burst_dst_cache" : i_axi_dma_burst_reshaper.burst_q.dst.cache, + // "burst_reshaper_burst_dst_burst" : i_axi_dma_burst_reshaper.burst_q.dst.burst, + // "burst_reshaper_burst_dst_valid" : i_axi_dma_burst_reshaper.burst_q.dst.valid, + // "burst_reshaper_burst_shift" : i_axi_dma_burst_reshaper.burst_q.shift, + // "burst_reshaper_burst_decouple_rw" : i_axi_dma_burst_reshaper.burst_q.decouple_rw, + // "burst_reshaper_burst_deburst" : i_axi_dma_burst_reshaper.burst_q.deburst, + // page + // "burst_reshaper_r_page_offset" : i_axi_dma_burst_reshaper.r_page_offset, + // "burst_reshaper_r_num_bytes_to_pb" : i_axi_dma_burst_reshaper.r_num_bytes_to_pb, + // "burst_reshaper_w_page_offset" : i_axi_dma_burst_reshaper.w_page_offset, + // "burst_reshaper_w_num_bytes_to_pb" : i_axi_dma_burst_reshaper.w_num_bytes_to_pb, + // "burst_reshaper_c_num_bytes_to_pb" : i_axi_dma_burst_reshaper.c_num_bytes_to_pb, + // issue process + // "burst_reshaper_r_num_bytes_possible" : i_axi_dma_burst_reshaper.r_num_bytes_possible, + // "burst_reshaper_r_num_bytes" : i_axi_dma_burst_reshaper.r_num_bytes, + // "burst_reshaper_r_finish" : i_axi_dma_burst_reshaper.r_finish, + // "burst_reshaper_r_addr_offset" : i_axi_dma_burst_reshaper.r_addr_offset, + // "burst_reshaper_w_num_bytes_possible" : i_axi_dma_burst_reshaper.w_num_bytes_possible, + // "burst_reshaper_w_num_bytes" : i_axi_dma_burst_reshaper.w_num_bytes, + // "burst_reshaper_w_finish" : i_axi_dma_burst_reshaper.w_finish, + // "burst_reshaper_w_addr_offset" : i_axi_dma_burst_reshaper.w_addr_offset + }; + + //-------------------------------------- + // Data Mover + //-------------------------------------- + dma_data_mover = '{ + // AR emitter + // "data_mover_ar_emitter_full" : i_axi_dma_data_mover.ar_emitter_full, + // "data_mover_ar_emitter_empty" : i_axi_dma_data_mover.ar_emitter_empty, + // "data_mover_ar_emitter_push" : i_axi_dma_data_mover.ar_emitter_push, + // "data_mover_ar_emitter_pop" : i_axi_dma_data_mover.ar_emitter_pop, + // AW emitter + // "data_mover_aw_emitter_full" : i_axi_dma_data_mover.aw_emitter_full, + // "data_mover_aw_emitter_empty" : i_axi_dma_data_mover.aw_emitter_empty, + // "data_mover_aw_emitter_push" : i_axi_dma_data_mover.aw_emitter_push, + // "data_mover_aw_emitter_pop" : i_axi_dma_data_mover.aw_emitter_pop, + // "data_mover_is_last_aw" : i_axi_dma_data_mover.is_last_aw, + // R emitter + // "data_mover_r_emitter_full" : i_axi_dma_data_mover.r_emitter_full, + // "data_mover_r_emitter_empty" : i_axi_dma_data_mover.r_emitter_empty, + // "data_mover_r_emitter_push" : i_axi_dma_data_mover.r_emitter_push, + // "data_mover_r_emitter_pop" : i_axi_dma_data_mover.r_emitter_pop, + // W emitter + // "data_mover_w_emitter_full" : i_axi_dma_data_mover.w_emitter_full, + // "data_mover_w_emitter_empty" : i_axi_dma_data_mover.w_emitter_empty, + // "data_mover_w_emitter_push" : i_axi_dma_data_mover.w_emitter_push, + // "data_mover_w_emitter_pop" : i_axi_dma_data_mover.w_emitter_pop, + // AW AXI signals + // "axi_dma_bus_aw_id" : i_axi_dma_data_mover.axi_dma_req_o.aw.id, + // "axi_dma_bus_aw_addr" : i_axi_dma_data_mover.axi_dma_req_o.aw.addr, + "axi_dma_bus_aw_len" : i_axi_dma_data_mover.axi_dma_req_o.aw.len, + "axi_dma_bus_aw_size" : i_axi_dma_data_mover.axi_dma_req_o.aw.size, + // "axi_dma_bus_aw_burst" : i_axi_dma_data_mover.axi_dma_req_o.aw.burst, + // "axi_dma_bus_aw_cache" : i_axi_dma_data_mover.axi_dma_req_o.aw.cache, + "axi_dma_bus_aw_valid" : i_axi_dma_data_mover.axi_dma_req_o.aw_valid, + "axi_dma_bus_aw_ready" : i_axi_dma_data_mover.axi_dma_res_i.aw_ready, + // B AXI signals + "axi_dma_bus_b_ready" : i_axi_dma_data_mover.axi_dma_req_o.b_ready, + "axi_dma_bus_b_valid" : i_axi_dma_data_mover.axi_dma_res_i.b_valid, + // AR AXI signals + // "axi_dma_bus_ar_id" : i_axi_dma_data_mover.axi_dma_req_o.ar.id, + // "axi_dma_bus_ar_addr" : i_axi_dma_data_mover.axi_dma_req_o.ar.addr, + "axi_dma_bus_ar_len" : i_axi_dma_data_mover.axi_dma_req_o.ar.len, + "axi_dma_bus_ar_size" : i_axi_dma_data_mover.axi_dma_req_o.ar.size, + // "axi_dma_bus_ar_burst" : i_axi_dma_data_mover.axi_dma_req_o.ar.burst, + // "axi_dma_bus_ar_cache" : i_axi_dma_data_mover.axi_dma_req_o.ar.cache, + "axi_dma_bus_ar_valid" : i_axi_dma_data_mover.axi_dma_req_o.ar_valid, + "axi_dma_bus_ar_ready" : i_axi_dma_data_mover.axi_dma_res_i.ar_ready + }; + + //-------------------------------------- + // Data Path + //-------------------------------------- + dma_data_path = '{ + // r channel + "data_path_r_dp_valid" : i_axi_dma_data_mover.i_axi_dma_data_path.r_dp_valid_i, + "data_path_r_dp_ready" : i_axi_dma_data_mover.i_axi_dma_data_path.r_dp_ready_o, + "data_path_r_tailer_i" : i_axi_dma_data_mover.i_axi_dma_data_path.r_tailer_i, + "data_path_r_offset_i" : i_axi_dma_data_mover.i_axi_dma_data_path.r_offset_i, + "data_path_r_shift_i" : i_axi_dma_data_mover.i_axi_dma_data_path.r_shift_i, + "axi_dma_bus_r_valid" : i_axi_dma_data_mover.i_axi_dma_data_path.r_valid_i, + // "axi_dma_bus_r_data" : i_axi_dma_data_mover.i_axi_dma_data_path.r_data_i, + // "axi_dma_bus_r_last" : i_axi_dma_data_mover.i_axi_dma_data_path.r_last_i, + // "axi_dma_bus_r_resp" : i_axi_dma_data_mover.i_axi_dma_data_path.r_resp_i, + "axi_dma_bus_r_ready" : i_axi_dma_data_mover.i_axi_dma_data_path.r_ready_o, + // w channel + "data_path_w_dp_valid" : i_axi_dma_data_mover.i_axi_dma_data_path.w_dp_valid_i, + "data_path_w_dp_ready" : i_axi_dma_data_mover.i_axi_dma_data_path.w_dp_ready_o, + "data_path_w_tailer_i" : i_axi_dma_data_mover.i_axi_dma_data_path.w_tailer_i, + "data_path_w_offset_i" : i_axi_dma_data_mover.i_axi_dma_data_path.w_offset_i, + "data_path_w_num_beats" : i_axi_dma_data_mover.i_axi_dma_data_path.w_num_beats_i, + "data_path_w_is_single" : i_axi_dma_data_mover.i_axi_dma_data_path.w_is_single_i, + "axi_dma_bus_w_valid" : i_axi_dma_data_mover.i_axi_dma_data_path.w_valid_o, + // "axi_dma_bus_w_data" : i_axi_dma_data_mover.i_axi_dma_data_path.w_data_o, + "axi_dma_bus_w_strb" : i_axi_dma_data_mover.i_axi_dma_data_path.w_strb_o, + // "axi_dma_bus_w_last" : i_axi_dma_data_mover.i_axi_dma_data_path.w_last_o, + "axi_dma_bus_w_ready" : i_axi_dma_data_mover.i_axi_dma_data_path.w_ready_i, + // mask pre-calculation + "data_path_r_first_mask" : i_axi_dma_data_mover.i_axi_dma_data_path.r_first_mask, + "data_path_r_last_mask" : i_axi_dma_data_mover.i_axi_dma_data_path.r_last_mask, + "data_path_w_first_mask" : i_axi_dma_data_mover.i_axi_dma_data_path.w_first_mask, + "data_path_w_last_mask" : i_axi_dma_data_mover.i_axi_dma_data_path.w_last_mask, + // barrel shifter + // "data_path_buffer_in" : i_axi_dma_data_mover.i_axi_dma_data_path.buffer_in, + "data_path_read_aligned_in_mask" : i_axi_dma_data_mover.i_axi_dma_data_path.read_aligned_in_mask, + "data_path_write_aligned_in_mask" : i_axi_dma_data_mover.i_axi_dma_data_path.in_mask, + // in mask generation + // "data_path_is_first_r" : i_axi_dma_data_mover.i_axi_dma_data_path.is_first_r, + // "data_path_is_first_r_d" : i_axi_dma_data_mover.i_axi_dma_data_path.is_first_r_d, + // "data_path_is_first_r_d" : i_axi_dma_data_mover.i_axi_dma_data_path.is_first_r_d, + // read control + // "data_path_buffer_full" : i_axi_dma_data_mover.i_axi_dma_data_path.buffer_full, + // "data_path_buffer_push" : i_axi_dma_data_mover.i_axi_dma_data_path.buffer_push, + // "data_path_full" : i_axi_dma_data_mover.i_axi_dma_data_path.full, + "data_path_push" : i_axi_dma_data_mover.i_axi_dma_data_path.push, + // out mask generation + "data_path_out_mask" : i_axi_dma_data_mover.i_axi_dma_data_path.out_mask, + // "data_path_is_first_w" : i_axi_dma_data_mover.i_axi_dma_data_path.is_first_w, + // "data_path_is_last_w" : i_axi_dma_data_mover.i_axi_dma_data_path.is_last_w, + // write control + // "data_path_buffer_out" : i_axi_dma_data_mover.i_axi_dma_data_path.buffer_out, + // "data_path_buffer_empty" : i_axi_dma_data_mover.i_axi_dma_data_path.buffer_empty, + // "data_path_buffer_pop" : i_axi_dma_data_mover.i_axi_dma_data_path.buffer_pop, + // "data_path_w_num_beats" : i_axi_dma_data_mover.i_axi_dma_data_path.w_num_beats_q, + // "data_path_w_cnt_valid" : i_axi_dma_data_mover.i_axi_dma_data_path.w_cnt_valid_q, + "data_path_pop" : i_axi_dma_data_mover.i_axi_dma_data_path.pop// , + // "data_path_write_happening" : i_axi_dma_data_mover.i_axi_dma_data_path.write_happening, + // "data_path_ready_to_write" : i_axi_dma_data_mover.i_axi_dma_data_path.ready_to_write, + // "data_path_first_possible" : i_axi_dma_data_mover.i_axi_dma_data_path.first_possible, + // "data_path_buffer_clean" : i_axi_dma_data_mover.i_axi_dma_data_path.buffer_clean + }; + + // write dicts to string + foreach(dma_meta[key]) dma_string = $sformatf("%s'%s': 0x%0x, ", dma_string, key, dma_meta[key]); + // only write bulk of data if dma is actually active :) + if (!backend_idle_o | valid_i & ready_o | i_axi_dma_burst_reshaper.valid_i & i_axi_dma_burst_reshaper.ready_o | + i_axi_dma_burst_reshaper.burst_q.src.valid | i_axi_dma_burst_reshaper.burst_q.dst.valid | trans_complete_o) begin + foreach(dma_backend[key]) dma_string = $sformatf("%s'%s': 0x%0x, ", dma_string, key, dma_backend[key]); + foreach(dma_burst_res[key]) dma_string = $sformatf("%s'%s': 0x%0x, ", dma_string, key, dma_burst_res[key]); + foreach(dma_data_mover[key]) dma_string = $sformatf("%s'%s': 0x%0x, ", dma_string, key, dma_data_mover[key]); + foreach(dma_data_path[key]) dma_string = $sformatf("%s'%s': 0x%0x, ", dma_string, key, dma_data_path[key]); + + //-------------------------------------- + // Realign Buffer Data Store + //-------------------------------------- + // for(int d = 0; d < BUFFER_DEPTH; d++) begin + // for(int i = 0; i < DATA_WIDTH/8; i++) begin + // dma_string = $sformatf("%s'buffer_mem_%0d_level_%0d': 0x%0x, ", + // dma_string, i, d, buffer_mem[i][d] + // ); + // end + // end + end + dma_string = $sformatf("%s}", dma_string); + $fwrite(f, dma_string); + $fwrite(f, "\n"); + end + end + // close the file + final begin + $fclose(f); + end + end + endgenerate + `endif + `endif + //pragma translate_on +endmodule : axi_dma_backend diff --git a/src/axi_dma_backend_mesh_wrapper.sv b/src/axi_dma_backend_mesh_wrapper.sv new file mode 100644 index 000000000..6c1fa534e --- /dev/null +++ b/src/axi_dma_backend_mesh_wrapper.sv @@ -0,0 +1,313 @@ +// Copyright (c) 2019 ETH Zurich, University of Bologna +// All rights reserved. +// +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// +// Thomas Benz + +// fixture for the AXi DMA backend +// the fixture instantiates the DMA backend, a golden model of the backend , and tasks controlling +// both. + +`timescale 1ns/1ns + +`include "axi/assign.svh" +`include "axi/typedef.svh" + +module axi_dma_backend_mesh_wrapper #( + parameter bit ATOPs = 1'b0, + parameter int unsigned NoSlvPorts_1 = 32'd2, + parameter int unsigned NoMstPorts_1 = 32'd2, + parameter int unsigned NoSlvPorts_0 = 32'd1, + parameter int unsigned NoMstPorts_0 = 32'd1, + parameter bit [NoSlvPorts_1-1:0][NoMstPorts_1-1:0] Connectivity_1 = '1, + parameter bit [NoSlvPorts_0-1:0][NoMstPorts_0-1:0] Connectivity_0 = '1, + parameter int unsigned AxiAddrWidth = 32'd64, + parameter int unsigned AxiDataWidth = 32'd512, + parameter int unsigned AxiIdWidth = 32'd6, + parameter int unsigned AxiUserWidth = 32'd1, + parameter int unsigned AxiStrbWidth = (AxiDataWidth/8), + parameter int unsigned AxiSlvPortMaxUniqIds = 32'd16, + parameter int unsigned AxiSlvPortMaxTxnsPerId = 32'd128, + parameter int unsigned AxiSlvPortMaxTxns = 32'd31, + parameter int unsigned AxiMstPortMaxUniqIds = 32'd4, + parameter int unsigned AxiMstPortMaxTxnsPerId = 32'd7, + parameter int unsigned NoAddrRules_1 = 32'd2, + parameter int unsigned NoAddrRules_0 = 32'd1 +) ( + input logic clk_i, + input logic rst_ni, + input logic test_en_i, + AXI_BUS.Slave dma [NoMstPorts_1-1:0], + AXI_BUS.Master mem_0 [NoSlvPorts_0-1:0], + AXI_BUS.Master mem_1 [NoSlvPorts_0-1:0] +); + + //-------------------------------------- + // Parameters + //-------------------------------------- + + typedef axi_pkg::xbar_rule_64_t rule_t; // Has to be the same width as axi addr + + // in the bench can change this variables which are set here freely + localparam axi_pkg::xbar_cfg_t xbar_cfg_2 = '{ + NoSlvPorts: NoMstPorts_1, + NoMstPorts: NoSlvPorts_1, + MaxMstTrans: AxiSlvPortMaxTxns, + MaxSlvTrans: AxiSlvPortMaxTxnsPerId, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_AX, + AxiIdWidthSlvPorts: AxiIdWidth, + AxiIdUsedSlvPorts: (AxiIdWidth-1), + UniqueIds: 1'b0, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: NoAddrRules_1 + }; + + localparam axi_pkg::xbar_cfg_t xbar_cfg_1 = '{ + NoSlvPorts: NoMstPorts_1, + NoMstPorts: NoSlvPorts_1, + MaxMstTrans: AxiSlvPortMaxTxns, + MaxSlvTrans: AxiSlvPortMaxTxnsPerId, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_AX, + AxiIdWidthSlvPorts: AxiIdWidth, + AxiIdUsedSlvPorts: (AxiIdWidth-1), + UniqueIds: 1'b0, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: NoAddrRules_1 + }; + + localparam axi_pkg::xbar_cfg_t xbar_cfg_0 = '{ + NoSlvPorts: NoMstPorts_0, + NoMstPorts: NoSlvPorts_0, + MaxMstTrans: AxiSlvPortMaxTxns, + MaxSlvTrans: AxiSlvPortMaxTxnsPerId, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_AX, + AxiIdWidthSlvPorts: AxiIdWidth, + AxiIdUsedSlvPorts: (AxiIdWidth-1), + UniqueIds: 1'b0, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: NoAddrRules_0 + }; + + localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2 = '{ + '{idx: 32'd1 % NoSlvPorts_1, start_addr: {AxiAddrWidth{1'b0}}, end_addr: {1'b0, {(AxiAddrWidth-1){1'b1}}}}, + '{idx: 32'd0 % NoSlvPorts_1, start_addr: {1'b0, {(AxiAddrWidth-1){1'b1}}}, end_addr: {(AxiAddrWidth){1'b1}}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp1 = '{ + '{idx: 32'd1 % NoSlvPorts_1, start_addr: {1'b0, {(AxiAddrWidth-1){1'b1}}}, end_addr: {(AxiAddrWidth){1'b1}}}, + '{idx: 32'd0 % NoSlvPorts_1, start_addr: {AxiAddrWidth{1'b0}}, end_addr: {1'b0, {(AxiAddrWidth-1){1'b1}}}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_0.NoAddrRules-1:0] AddrMap_xp0 = '{ + '{idx: 32'd0 % NoSlvPorts_0, start_addr: {AxiAddrWidth{1'b0}}, end_addr: {(AxiAddrWidth){1'b1}}} + }; + + /// Address Type + typedef logic [ AxiAddrWidth-1:0] addr_t; + /// Data Type + typedef logic [ AxiDataWidth-1:0] data_t; + /// Strobe Type + typedef logic [ AxiStrbWidth-1:0] strb_t; + /// AXI ID Type + typedef logic [ AxiIdWidth-1:0] axi_id_t; + /// AXI USER Type + typedef logic [ AxiUserWidth-1:0] user_t; + + // master AXI bus --> DMA + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_dma_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_dma_t, axi_id_t, user_t) + + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_dma_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_dma_t, data_t, axi_id_t, user_t) + + `AXI_TYPEDEF_REQ_T(dma_req_t, aw_chan_dma_t, w_chan_t, ar_chan_dma_t) + `AXI_TYPEDEF_RESP_T(dma_resp_t, b_chan_dma_t, r_chan_dma_t) + + // slave AXI bus --> mem + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_mem_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_mem_t, axi_id_t, user_t) + + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_mem_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_mem_t, data_t, axi_id_t, user_t) + + `AXI_TYPEDEF_REQ_T(mem_req_t, aw_chan_mem_t, w_chan_t, ar_chan_mem_t) + `AXI_TYPEDEF_RESP_T(mem_resp_t, b_chan_mem_t, r_chan_mem_t) + + //-------------------------------------- + // DUT Axi busses + //-------------------------------------- + + // AXI_BUS #( + // .AXI_ADDR_WIDTH ( AxiAddrWidth ), + // .AXI_DATA_WIDTH ( AxiDataWidth ), + // .AXI_ID_WIDTH ( AxiIdWidth ), + // .AXI_USER_WIDTH ( 1 ) + // ) dma [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_ID_WIDTH ( AxiIdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_ID_WIDTH ( AxiIdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_slv_0 [NoSlvPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_ID_WIDTH ( AxiIdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_slv_1 [NoSlvPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_ID_WIDTH ( AxiIdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_slv [NoSlvPorts_0-1:0] (); + + `AXI_ASSIGN (xp0_slv_0[0], xp0_slv[0]) + `AXI_ASSIGN (xp0_slv_1[0], xp0_slv[1]) + + // AXI_BUS #( + // .AXI_ADDR_WIDTH ( AxiAddrWidth ), + // .AXI_DATA_WIDTH ( AxiDataWidth ), + // .AXI_ID_WIDTH ( AxiIdWidth ), + // .AXI_USER_WIDTH ( 1 ) + // ) mem_0 [NoSlvPorts_0-1:0] (); + + // AXI_BUS #( + // .AXI_ADDR_WIDTH ( AxiAddrWidth ), + // .AXI_DATA_WIDTH ( AxiDataWidth ), + // .AXI_ID_WIDTH ( AxiIdWidth ), + // .AXI_USER_WIDTH ( 1 ) + // ) mem_1 [NoSlvPorts_0-1:0] (); + + //----------------------------------- + // DUT + //----------------------------------- + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_0 ), + .NoSlvPorts ( xbar_cfg_0.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_0.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_0.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_3 ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp1_slv ), + .mst_ports ( mem_0 ), + .addr_map_i ( AddrMap_xp0 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_0 ), + .NoSlvPorts ( xbar_cfg_0.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_0.NoMstPorts ), + .Connectivity ( Connectivity_0 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_0.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_2 ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp0_slv_1 ), + .mst_ports ( mem_1 ), + .addr_map_i ( AddrMap_xp0 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_0 ), + .NoSlvPorts ( xbar_cfg_0.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_0.NoMstPorts ), + .Connectivity ( Connectivity_0 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_0.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_1 ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp0_slv_0 ), + .mst_ports ( xp1_slv ), + .addr_map_i ( AddrMap_xp0 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_0 ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_en_i ( 1'b0 ), + .slv_ports ( dma ), + .mst_ports ( xp0_slv ), + .addr_map_i ( AddrMap_xp1 ) + ); + +endmodule : axi_dma_backend_mesh_wrapper diff --git a/src/axi_dma_backend_wrapper.sv b/src/axi_dma_backend_wrapper.sv new file mode 100644 index 000000000..7d4e4edbf --- /dev/null +++ b/src/axi_dma_backend_wrapper.sv @@ -0,0 +1,128 @@ +`timescale 1ns/1ns + +`include "axi/assign.svh" +`include "axi/typedef.svh" + +module axi_dma_backend_wrapper #( + parameter bit ATOPs = 1'b0, + parameter int unsigned NoSlvPorts = 32'd1, + parameter int unsigned NoMstPorts = 32'd1, + parameter bit [NoSlvPorts-1:0][NoMstPorts-1:0] Connectivity = '1, + parameter int unsigned AxiAddrWidth = 32'd64, + parameter int unsigned AxiDataWidth = 32'd512, + parameter int unsigned AxiIdWidth = 32'd6, + parameter int unsigned AxiUserWidth = 32'd1, + parameter int unsigned AxiSlvPortMaxUniqIds = 32'd16, + parameter int unsigned AxiSlvPortMaxTxnsPerId = 32'd128, + parameter int unsigned AxiSlvPortMaxTxns = 32'd31, + parameter int unsigned AxiMstPortMaxUniqIds = 32'd4, + parameter int unsigned AxiMstPortMaxTxnsPerId = 32'd7, + parameter int unsigned NoAddrRules = 32'd1 +) ( + input logic clk_i, + input logic rst_ni, + input logic test_en_i, + AXI_BUS.Slave slv_ports [NoSlvPorts-1:0], + AXI_BUS.Master mst_ports [NoMstPorts-1:0] +); + + typedef axi_pkg::xbar_rule_64_t rule_t; // Has to be the same width as axi addr + + typedef logic [AxiIdWidth -1:0] id_mst_t; + typedef logic [AxiIdWidth -1:0] id_slv_t; + typedef logic [AxiAddrWidth -1:0] addr_t; + typedef logic [AxiDataWidth -1:0] data_t; + typedef logic [AxiDataWidth/8 -1:0] strb_t; + typedef logic [AxiUserWidth -1:0] user_t; + + localparam axi_pkg::xbar_cfg_t Cfg = '{ + NoSlvPorts: NoMstPorts, + NoMstPorts: NoSlvPorts, + MaxMstTrans: AxiSlvPortMaxTxns, + MaxSlvTrans: AxiSlvPortMaxTxnsPerId, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_AX, + AxiIdWidthSlvPorts: AxiIdWidth, + AxiIdUsedSlvPorts: (AxiIdWidth-1), + UniqueIds: 1'b0, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: NoAddrRules + }; + + localparam rule_t [Cfg.NoAddrRules-1:0] AddrMap = '{ + '{idx: 32'd0 % NoSlvPorts, start_addr: {AxiAddrWidth{1'b0}}, end_addr: {(AxiAddrWidth){1'b1}}} + }; + + + `AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, addr_t, id_mst_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, addr_t, id_slv_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(mst_b_chan_t, id_mst_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, id_slv_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, addr_t, id_mst_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, addr_t, id_slv_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, data_t, id_mst_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, data_t, id_slv_t, user_t) + `AXI_TYPEDEF_REQ_T(mst_req_t, mst_aw_chan_t, w_chan_t, mst_ar_chan_t) + `AXI_TYPEDEF_REQ_T(slv_req_t, slv_aw_chan_t, w_chan_t, slv_ar_chan_t) + `AXI_TYPEDEF_RESP_T(mst_resp_t, mst_b_chan_t, mst_r_chan_t) + `AXI_TYPEDEF_RESP_T(slv_resp_t, slv_b_chan_t, slv_r_chan_t) + + mst_req_t [NoMstPorts-1:0] mst_reqs; + mst_resp_t [NoMstPorts-1:0] mst_resps; + slv_req_t [NoSlvPorts-1:0] slv_reqs; + slv_resp_t [NoSlvPorts-1:0] slv_resps; + + for (genvar i = 0; i < NoMstPorts; i++) begin : gen_assign_mst + `AXI_ASSIGN_FROM_REQ(mst_ports[i], mst_reqs[i]) + `AXI_ASSIGN_TO_RESP(mst_resps[i], mst_ports[i]) + end + + for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_assign_slv + `AXI_ASSIGN_TO_REQ(slv_reqs[i], slv_ports[i]) + `AXI_ASSIGN_FROM_RESP(slv_ports[i], slv_resps[i]) + end + + axi_xp #( + .ATOPs ( ATOPs ), + .Cfg ( Cfg ), + .NoSlvPorts ( Cfg.NoSlvPorts), + .NoMstPorts ( Cfg.NoMstPorts), + .Connectivity ( Connectivity ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( NoAddrRules ), + .slv_aw_chan_t ( slv_aw_chan_t ), + .mst_aw_chan_t ( mst_aw_chan_t ), + .w_chan_t ( w_chan_t ), + .slv_b_chan_t ( slv_b_chan_t ), + .mst_b_chan_t ( mst_b_chan_t ), + .slv_ar_chan_t ( slv_ar_chan_t ), + .mst_ar_chan_t ( mst_ar_chan_t ), + .slv_r_chan_t ( slv_r_chan_t ), + .mst_r_chan_t ( mst_r_chan_t ), + .slv_req_t ( slv_req_t ), + .slv_resp_t ( slv_resp_t ), + .mst_req_t ( mst_req_t ), + .mst_resp_t ( mst_resp_t ), + .rule_t ( rule_t ) + ) i_xp ( + .clk_i, + .rst_ni, + .test_en_i, + .slv_req_i (slv_reqs ), + .slv_resp_o (slv_resps), + .mst_req_o (mst_reqs ), + .mst_resp_i (mst_resps), + .addr_map_i (AddrMap ) + ); + +endmodule \ No newline at end of file diff --git a/src/axi_dma_burst_reshaper.sv b/src/axi_dma_burst_reshaper.sv new file mode 100644 index 000000000..ecdfdd495 --- /dev/null +++ b/src/axi_dma_burst_reshaper.sv @@ -0,0 +1,356 @@ +// Copyright (c) 2020 ETH Zurich, University of Bologna +// All rights reserved. +// +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// +// Thomas Benz + +/// Splits a generic 1D transfer in AXI-conform transfers +module axi_dma_burst_reshaper #( + /// Data width of the AXI bus + parameter int unsigned DataWidth = -1, + /// Address width of the AXI bus + parameter int unsigned AddrWidth = -1, + /// ID width of the AXI bus + parameter int unsigned IdWidth = -1, + /// Arbitrary 1D burst request definition: + /// - id: the AXI id used - this id should be constant, as the DMA does not support reordering + /// - src, dst: source and destination address, same width as the AXI 4 interface + /// - num_bytes: the length of the contiguous 1D transfer requested, can be up to 32/64 bit long + /// num_bytes will be interpreted as an unsigned number + /// A value of 0 will cause the backend to discard the transfer prematurely + /// - cache_src, cache_dst: the configuration of the cache fields in the AX beats + /// - burst_dst, burst_dst: currently only incremental bursts are supported (2'b01) + /// - decouple_rw: if set to true, there is no longer exactly one AXI write_request issued for + /// every read request. This mode can improve performance of unaligned transfers when crossing + /// the AXI page boundaries. + /// - deburst: if set, the DMA will split all bursts in single transfers + parameter type burst_req_t = logic, + /// Read request definition. Includes: + /// - ax descriptor + /// - id: AXI id + /// - last: last transaction in burst + /// - address: address of burst + /// - length: burst length + /// - size: bytes in each burst + /// - burst: burst type; only INC supported + /// - cache: cache type + /// - r descriptor + /// - offset: initial misalignment + /// - tailer: final misalignment + /// - shift: amount the data needs to be shifted to realign it + parameter type read_req_t = logic, + /// Write request definition. Includes: + /// - ax descriptor + /// - id: AXI id + /// - last: last transaction in burst + /// - address: address of burst + /// - length: burst length + /// - size: bytes in each burst + /// - burst: burst type; only INC supported + /// - cache: cache type + /// - w descriptor + /// - offset: initial misalignment + /// - tailer: final misalignment + /// - num_beats: number of beats in the burst + /// - is_single: burst length is 0 + parameter type write_req_t = logic + +) ( + /// Clock + input logic clk_i, + /// Asynchronous reset, active low + input logic rst_ni, + /// Arbitrary 1D burst request + input burst_req_t burst_req_i, + + /// Handshake: burst request is valid + input logic valid_i, + /// Handshake: burst request can be accepted + output logic ready_o, + + /// Write transfer request + output write_req_t write_req_o, + /// Read transfer request + output read_req_t read_req_o, + + /// Handshake: read transfer request valid + output logic r_valid_o, + /// Handshake: read transfer request ready + input logic r_ready_i, + /// Handshake: write transfer request valid + output logic w_valid_o, + /// Handshake: write transfer request ready + input logic w_ready_i +); + + localparam int unsigned StrbWidth = DataWidth / 8; + localparam int unsigned OffsetWidth = $clog2(StrbWidth); + localparam int unsigned PageSize = (256 * StrbWidth > 4096) ? 4096 : 256 * StrbWidth; + localparam int unsigned PageAddrWidth = $clog2(PageSize); + /// Offset type + typedef logic [ OffsetWidth-1:0] offset_t; + /// Address Type + typedef logic [ AddrWidth-1:0] addr_t; + /// AXI ID Type + typedef logic [ IdWidth-1:0] axi_id_t; + + /// Type containing burst description for each channel independently + typedef struct packed { + axi_id_t id; + addr_t addr; + addr_t num_bytes; + axi_pkg::cache_t cache; + axi_pkg::burst_t burst; + logic valid; + } burst_chan_t; + + /// Type containing burst description + typedef struct packed { + burst_chan_t src; + burst_chan_t dst; + offset_t shift; + logic decouple_rw; + logic deburst; + } burst_decoupled_t; + + //-------------------------------------- + // state; internally hold one transfer + //-------------------------------------- + burst_decoupled_t burst_d, burst_q; + + //-------------------------------------- + // page boundary check + //-------------------------------------- + logic [PageAddrWidth-1:0] r_page_offset; + logic [PageAddrWidth :0] r_num_bytes_to_pb; + logic [PageAddrWidth-1:0] w_page_offset; + logic [PageAddrWidth :0] w_num_bytes_to_pb; + logic [PageAddrWidth :0] c_num_bytes_to_pb; + + always_comb begin : proc_write_page_boundry_check + // implement deburst operation + if (burst_q.deburst) begin + // deburst + // read pages + r_page_offset = burst_q.src.addr[OffsetWidth-1:0]; + // how many transfers are remaining until the end of the bus? + r_num_bytes_to_pb = (StrbWidth - r_page_offset) % (2 * StrbWidth); + + // write pages + w_page_offset = burst_q.dst.addr[OffsetWidth-1:0]; + // how many transfers are remaining until the end of the bus? + w_num_bytes_to_pb = (StrbWidth - w_page_offset) % (2 * StrbWidth); + end else begin + // bursts allowed + // read pages + r_page_offset = burst_q.src.addr[PageAddrWidth-1:0]; + // how many transfers are remaining in current page? + r_num_bytes_to_pb = PageSize - r_page_offset; + + // write pages + w_page_offset = burst_q.dst.addr[PageAddrWidth-1:0]; + // how many transfers are remaining in current page? + w_num_bytes_to_pb = PageSize - w_page_offset; + end + // how many transfers are remaining when concerning both r/w pages? + // take the boundary that is closer + c_num_bytes_to_pb = (r_num_bytes_to_pb > w_num_bytes_to_pb) ? + w_num_bytes_to_pb : r_num_bytes_to_pb; + + end + + //-------------------------------------- + // Synchronized R/W process + //-------------------------------------- + logic [PageAddrWidth:0] r_num_bytes_possible; + logic [PageAddrWidth:0] r_num_bytes; + logic r_finish; + logic [OffsetWidth-1:0] r_addr_offset; + + logic [PageAddrWidth:0] w_num_bytes_possible; + logic [PageAddrWidth:0] w_num_bytes; + logic w_finish; + logic [OffsetWidth-1:0] w_addr_offset; + + always_comb begin : proc_read_write_transaction + + // default: keep last state + burst_d = burst_q; + + //-------------------------------------- + // Specify read transaction + //-------------------------------------- + // max num bytes according to page(s) + r_num_bytes_possible = (burst_q.decouple_rw == 1'b1) ? + r_num_bytes_to_pb : c_num_bytes_to_pb; + + // more bytes remaining than we can send + if (burst_q.src.num_bytes > r_num_bytes_possible) begin + r_num_bytes = r_num_bytes_possible; + // calculate remainder + burst_d.src.num_bytes = burst_q.src.num_bytes - r_num_bytes_possible; + // not finished + r_finish = 1'b0; + // next address, depends on burst type. only type 01 is supported yet + burst_d.src.addr = (burst_q.src.burst == axi_pkg::BURST_INCR) ? + burst_q.src.addr + r_num_bytes : burst_q.src.addr; + + // remaining bytes fit in one burst + // reset storage for the read channel to stop this channel + end else begin + r_num_bytes = burst_q.src.num_bytes[PageAddrWidth:0]; + // default: when a transfer is finished, set it to 0 + burst_d.src = '0; + // finished + r_finish = 1'b1; + end + + // calculate the address offset aligned to transfer sizes. + r_addr_offset = burst_q.src.addr[OffsetWidth-1:0]; + + // create the AR request + read_req_o.ar.addr = { burst_q.src.addr[AddrWidth-1:OffsetWidth], + {{OffsetWidth}{1'b0}} }; + read_req_o.ar.len = ((r_num_bytes + r_addr_offset - 1) >> OffsetWidth); + read_req_o.ar.size = axi_pkg::size_t'(OffsetWidth); + read_req_o.ar.id = burst_q.src.id; + read_req_o.ar.last = r_finish; + read_req_o.ar.burst = burst_q.src.burst; + read_req_o.ar.cache = burst_q.src.cache; + r_valid_o = burst_q.decouple_rw ? + burst_q.src.valid : burst_q.src.valid & w_ready_i; + + // create the R request + read_req_o.r.offset = r_addr_offset; + read_req_o.r.tailer = OffsetWidth'(r_num_bytes + r_addr_offset); + // shift is determined on a per 1D request base + read_req_o.r.shift = burst_q.shift; + + //-------------------------------------- + // Specify write transaction + //-------------------------------------- + // max num bytes according to page(s) + w_num_bytes_possible = (burst_q.decouple_rw == 1'b1) ? + w_num_bytes_to_pb : c_num_bytes_to_pb; + + // more bytes remaining than we can send + if (burst_q.dst.num_bytes > w_num_bytes_possible) begin + w_num_bytes = w_num_bytes_possible; + // calculate remainder + burst_d.dst.num_bytes = burst_q.dst.num_bytes - w_num_bytes_possible; + // not finished + w_finish = 1'b0; + // next address, depends on burst type. only type 01 is supported yet + burst_d.dst.addr = (burst_q.dst.burst == axi_pkg::BURST_INCR) ? + burst_q.dst.addr + w_num_bytes : burst_q.dst.addr; + + // remaining bytes fit in one burst + // reset storage for the write channel to stop this channel + end else begin + w_num_bytes = burst_q.dst.num_bytes[PageAddrWidth:0]; + // default: when a transfer is finished, set it to 0 + burst_d.dst = '0; + // finished + w_finish = 1'b1; + end + + // calculate the address offset aligned to transfer sizes. + w_addr_offset = burst_q.dst.addr[OffsetWidth-1:0]; + + // create the AW request + write_req_o.aw.addr = { burst_q.dst.addr[AddrWidth-1:OffsetWidth], + {{OffsetWidth}{1'b0}} }; + write_req_o.aw.len = ((w_num_bytes + w_addr_offset - 1) >> OffsetWidth); + write_req_o.aw.size = axi_pkg::size_t'(OffsetWidth); + write_req_o.aw.id = burst_q.dst.id; + // hand over internal transaction id + write_req_o.aw.last = w_finish; + write_req_o.aw.burst = burst_q.dst.burst; + write_req_o.aw.cache = burst_q.dst.cache; + w_valid_o = burst_q.decouple_rw ? + burst_q.dst.valid : burst_q.dst.valid & r_ready_i; + + // create the W request + write_req_o.w.offset = w_addr_offset; + write_req_o.w.tailer = OffsetWidth'(w_num_bytes + w_addr_offset); + write_req_o.w.num_beats = write_req_o.aw.len; + // is the transfer be only one beat in length? Counters don't have to be initialized then. + write_req_o.w.is_single = (write_req_o.aw.len == '0); + + //-------------------------------------- + // Module control + //-------------------------------------- + ready_o = r_finish & w_finish & valid_i & r_ready_i & w_ready_i; + + //-------------------------------------- + // Refill + //-------------------------------------- + // new request is taken in if both r and w machines are ready. + if (ready_o) begin + // unfortunately this is unpacked + burst_d.src.id = burst_req_i.id; + burst_d.src.addr = burst_req_i.src; + burst_d.src.num_bytes = burst_req_i.num_bytes; + burst_d.src.cache = burst_req_i.cache_src; + burst_d.src.burst = burst_req_i.burst_src; + // check if transfer is possible -> num_bytes has to be larger than 0 + burst_d.src.valid = (burst_req_i.num_bytes == '0) ? 1'b0 : valid_i; + + burst_d.dst.id = burst_req_i.id; + burst_d.dst.addr = burst_req_i.dst; + burst_d.dst.num_bytes = burst_req_i.num_bytes; + burst_d.dst.cache = burst_req_i.cache_dst; + burst_d.dst.burst = burst_req_i.burst_dst; + // check if transfer is possible -> num_bytes has to be larger than 0 + burst_d.dst.valid = (burst_req_i.num_bytes == '0) ? 1'b0 : valid_i; + + burst_d.decouple_rw = burst_req_i.decouple_rw; + burst_d.deburst = burst_req_i.deburst; + // shift is calculated for each 1D transfer + burst_d.shift = burst_req_i.src[OffsetWidth-1:0] - + burst_req_i.dst[OffsetWidth-1:0]; + + // assertions + // pragma translate_off + `ifndef VERILATOR + assert property (@(posedge clk_i) disable iff (~rst_ni) + (valid_i |-> burst_req_i.burst_src inside {axi_pkg::BURST_INCR})) else + $fatal(1, "Unsupported DMA src_burst request.."); + assert property (@(posedge clk_i) disable iff (~rst_ni) + (valid_i |-> burst_req_i.burst_dst inside {axi_pkg::BURST_INCR})) else + $fatal(1, "Unsupported DMA dst_burst request."); + `endif + // pragma translate_on + end + end + + //-------------------------------------- + // State + //-------------------------------------- + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + burst_q.decouple_rw <= '0; + burst_q.deburst <= '0; + burst_q.shift <= '0; + burst_q.src <= '0; + burst_q.dst <= '0; + end else begin + burst_q.decouple_rw <= burst_d.decouple_rw; + burst_q.deburst <= burst_d.deburst; + burst_q.shift <= burst_d.shift; + // couple read and write machines in the coupled test + if (burst_d.decouple_rw) begin + if (r_ready_i) burst_q.src <= burst_d.src; + if (w_ready_i) burst_q.dst <= burst_d.dst; + end else begin + if (r_ready_i & w_ready_i) burst_q.src <= burst_d.src; + if (w_ready_i & r_ready_i) burst_q.dst <= burst_d.dst; + end + end + end +endmodule : axi_dma_burst_reshaper diff --git a/src/axi_dma_data_mover.sv b/src/axi_dma_data_mover.sv new file mode 100644 index 000000000..fd65c50d8 --- /dev/null +++ b/src/axi_dma_data_mover.sv @@ -0,0 +1,369 @@ +// Copyright (c) 2020 ETH Zurich, University of Bologna +// All rights reserved. +// +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// +// Thomas Benz + +/// Module, that controls the AXI bus. Takes two configuration structs (R/W) as an +/// input. Implements the DMA functionality on the AXI bus. +/// R and W config structs need to appear at the input simultaneously; sending a +/// R config w/o the corresponding W could lead to wrong AXI transfers. +module axi_dma_data_mover #( + /// Data width of the AXI bus + parameter int unsigned DataWidth = -1, + /// Number of AX beats that can be in-flight + parameter int unsigned ReqFifoDepth = -1, + /// Number of elements the realignment buffer can hold. To achieve + /// full performance a depth of 3 is minimally required. + parameter int unsigned BufferDepth = -1, + /// AXI4+ATOP request struct definition. + parameter type axi_req_t = logic, + /// AXI4+ATOP response struct definition. + parameter type axi_res_t = logic, + /// ax descriptor + /// - `id`: AXI id + /// - `last`: last transaction in burst + /// - `address`: address of burst + /// - `length`: burst length + /// - `size`: bytes in each burst + /// - `burst`: burst type; only INC supported + /// - `cache`: cache type + parameter type desc_ax_t = logic, + /// r descriptor + /// - `offset`: initial misalignment + /// - `tailer`: final misalignment + /// - `shift`: amount the data needs to be shifted to realign it + parameter type desc_r_t = logic, + /// w descriptor + /// - `offset`: initial misalignment + /// - `tailer`: final misalignment + /// - `num_beats`: number of beats in the burst + /// - `is_single`: burst length is 0 + parameter type desc_w_t = logic, + /// Read request definition. Includes: + /// - ax descriptor + /// - `id`: AXI id + /// - `last`: last transaction in burst + /// - `address`: address of burst + /// - `length`: burst length + /// - `size`: bytes in each burst + /// - `burst`: burst type; only INC supported + /// - `cache`: cache type + /// - r descriptor + /// - `offset`: initial misalignment + /// - `tailer`: final misalignment + /// - `shift`: amount the data needs to be shifted to realign it + parameter type read_req_t = logic, + /// Write request definition. Includes: + /// - ax descriptor + /// - `id`: AXI id + /// - `last`: last transaction in burst + /// - `address`: address of burst + /// - `length`: burst length + /// - `size`: bytes in each burst + /// - `burst`: burst type; only INC supported + /// - `cache`: cache type + /// - w descriptor + /// - `offset`: initial misalignment + /// - `tailer`: final misalignment + /// - `num_beats`: number of beats in the burst + /// - `is_single`: burst length is 0 + parameter type write_req_t = logic +) ( + /// Clock + input logic clk_i, + /// Asynchronous reset, active low + input logic rst_ni, + /// AXI4+ATOP master request + output axi_req_t axi_dma_req_o, + /// AXI4+ATOP master response + input axi_res_t axi_dma_res_i, + /// Read transfer request + input read_req_t read_req_i, + /// Write transfer request + input write_req_t write_req_i, + /// Handshake: read transfer request valid + input logic r_valid_i, + /// Handshake: read transfer request ready + output logic r_ready_o, + /// Handshake: write transfer request valid + input logic w_valid_i, + /// Handshake: write transfer request ready + output logic w_ready_o, + /// High if the data mover is idle + output logic data_mover_idle_o, + /// Event: a transaction has completed + output logic trans_complete_o +); + + localparam int unsigned StrbWidth = DataWidth / 8; + // local types + typedef logic [DataWidth-1:0] data_t; + typedef logic [StrbWidth-1:0] strb_t; + + //-------------------------------------- + // AR emitter + //-------------------------------------- + // object currently at the tail of the fifo + desc_ax_t current_ar_req; + // control signals + logic ar_emitter_full; + logic ar_emitter_empty; + logic ar_emitter_push; + logic ar_emitter_pop; + + // instanciate a fifo to buffer the address read requests + fifo_v3 #( + .FALL_THROUGH ( 1'b0 ), + .DEPTH ( ReqFifoDepth ), + .dtype ( desc_ax_t ) + ) i_fifo_ar_emitter ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .full_o ( ar_emitter_full ), + .empty_o ( ar_emitter_empty ), + .usage_o ( ), + .data_i ( read_req_i.ar ), + .push_i ( ar_emitter_push ), + .data_o ( current_ar_req ), + .pop_i ( ar_emitter_pop ) + ); + + //-------------------------------------- + // AW emitter + //-------------------------------------- + // object currently at the tail of the fifo + desc_ax_t current_aw_req; + // control signals + logic aw_emitter_full; + logic aw_emitter_empty; + logic aw_emitter_push; + logic aw_emitter_pop; + + // instantiate a fifo to buffer the address write requests + fifo_v3 #( + .FALL_THROUGH ( 1'b0 ), + .dtype ( desc_ax_t ), + .DEPTH ( ReqFifoDepth ) + ) i_fifo_aw_emitter ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .full_o ( aw_emitter_full ), + .empty_o ( aw_emitter_empty ), + .usage_o ( ), + .data_i ( write_req_i.aw ), + .push_i ( aw_emitter_push ), + .data_o ( current_aw_req ), + .pop_i ( aw_emitter_pop ) + ); + + //-------------------------------------- + // R emitter + //-------------------------------------- + // object currently at the tail of the fifo + desc_r_t current_r_req; + // control signals + logic r_emitter_full; + logic r_emitter_empty; + logic r_emitter_push; + logic r_emitter_pop; + + // instantiate a fifo to buffer the read requests + fifo_v3 #( + .FALL_THROUGH ( 1'b0 ), + .dtype ( desc_r_t ), + .DEPTH ( ReqFifoDepth ) + ) i_fifo_r_emitter ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .full_o ( r_emitter_full ), + .empty_o ( r_emitter_empty ), + .usage_o ( ), + .data_i ( read_req_i.r ), + .push_i ( r_emitter_push ), + .data_o ( current_r_req ), + .pop_i ( r_emitter_pop ) + ); + + //-------------------------------------- + // W emitter + //-------------------------------------- + // object currently at the tail of the fifo + desc_w_t current_w_req; + // control signals + logic w_emitter_full; + logic w_emitter_empty; + logic w_emitter_push; + logic w_emitter_pop; + + // instanciate a fifo to buffer the read requests + fifo_v3 #( + .FALL_THROUGH ( 1'b0 ), + .dtype ( desc_w_t ), + .DEPTH ( ReqFifoDepth ) + ) i_fifo_w_emitter ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .full_o ( w_emitter_full ), + .empty_o ( w_emitter_empty ), + .usage_o ( ), + .data_i ( write_req_i.w ), + .push_i ( w_emitter_push ), + .data_o ( current_w_req ), + .pop_i ( w_emitter_pop ) + ); + + //-------------------------------------- + // instantiate of the data path + //-------------------------------------- + // AXI bus signals from and to the datapath + data_t r_data; + axi_pkg::resp_t r_resp; + logic r_last; + logic r_valid; + logic r_ready; + data_t w_data; + strb_t w_strb; + logic w_valid; + logic w_last; + logic w_ready; + + logic w_next; + + axi_dma_data_path #( + .DataWidth ( DataWidth ), + .BufferDepth ( BufferDepth ) + ) i_axi_dma_data_path ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .r_dp_valid_i ( ~r_emitter_empty ), + .r_dp_ready_o ( r_emitter_pop ), + .w_dp_valid_i ( ~w_emitter_empty ), + .w_dp_ready_o ( w_emitter_pop ), + .data_path_idle_o ( data_mover_idle_o ), + // AXI R signals + .r_data_i ( r_data ), + .r_valid_i ( r_valid ), + .r_last_i ( r_last ), + .r_resp_i ( r_resp ), + .r_ready_o ( r_ready ), + // R control + .r_tailer_i ( current_r_req.tailer ), + .r_offset_i ( current_r_req.offset ), + .r_shift_i ( current_r_req.shift ), + // AXI W signals + .w_data_o ( w_data ), + .w_strb_o ( w_strb ), + .w_valid_o ( w_valid ), + .w_last_o ( w_last ), + .w_ready_i ( w_ready ), + // W control + .w_offset_i ( current_w_req.offset ), + .w_tailer_i ( current_w_req.tailer ), + .w_num_beats_i ( current_w_req.num_beats ), + .w_is_single_i ( current_w_req.is_single ) + ); + + //-------------------------------------- + // Refill control + //-------------------------------------- + // the ax and x fifos of both channels are filled + // together, as request come bundled. + always_comb begin : proc_refill + // Read related channels + r_ready_o = ~ar_emitter_full & ~r_emitter_full; + r_emitter_push = r_valid_i & r_ready_o; + ar_emitter_push = r_valid_i & r_ready_o; + + // Write related channels + w_ready_o = ~aw_emitter_full & ~w_emitter_full; + w_emitter_push = w_valid_i & w_ready_o; + aw_emitter_push = w_valid_i & w_ready_o; + end + + //-------------------------------------- + // Bus control + //-------------------------------------- + // here the AXI bus is unpacked/packed. + always_comb begin : proc_bus_packer + // defaults: not used signals -> 0 + axi_dma_req_o = '0; + + // assign R signals + r_data = axi_dma_res_i.r.data; + r_resp = axi_dma_res_i.r.resp; + r_last = axi_dma_res_i.r.last; + r_valid = axi_dma_res_i.r_valid; + axi_dma_req_o.r_ready = r_ready; + + // assign W signals + axi_dma_req_o.w.data = w_data; + axi_dma_req_o.w.strb = w_strb; + axi_dma_req_o.w.last = w_last; + axi_dma_req_o.w_valid = w_valid; + w_ready = axi_dma_res_i.w_ready; + + // AW signals + axi_dma_req_o.aw.id = current_aw_req.id; + axi_dma_req_o.aw.addr = current_aw_req.addr; + axi_dma_req_o.aw.len = current_aw_req.len; + axi_dma_req_o.aw.size = current_aw_req.size; + axi_dma_req_o.aw.burst = current_aw_req.burst; + axi_dma_req_o.aw.cache = current_aw_req.cache; + // flow control + axi_dma_req_o.aw_valid = ~aw_emitter_empty; + aw_emitter_pop = axi_dma_res_i.aw_ready & axi_dma_req_o.aw_valid; + + // B signals + // we are always ready to accept b signals, as we do not need them + // inside the DMA (we don't care if write failed) + axi_dma_req_o.b_ready = 1'b1; + + // AR signals + axi_dma_req_o.ar.id = current_ar_req.id; + axi_dma_req_o.ar.addr = current_ar_req.addr; + axi_dma_req_o.ar.len = current_ar_req.len; + axi_dma_req_o.ar.size = current_ar_req.size; + axi_dma_req_o.ar.burst = current_ar_req.burst; + axi_dma_req_o.ar.cache = current_ar_req.cache; + // flow control + axi_dma_req_o.ar_valid = ~ar_emitter_empty; + ar_emitter_pop = axi_dma_res_i.ar_ready & axi_dma_req_o.ar_valid; + end + + //-------------------------------------- + // ID control + //-------------------------------------- + logic is_last_aw; + fifo_v3 #( + .DEPTH ( ReqFifoDepth + BufferDepth + ReqFifoDepth ), // This size may need adjusting + .dtype ( logic ) + ) i_last_transaction_queue ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .full_o ( ), + .empty_o ( ), + .usage_o ( ), + .data_i ( current_aw_req.last ), + .push_i ( aw_emitter_pop ), + .data_o ( is_last_aw ), + .pop_i ( axi_dma_res_i.b_valid ) + ); + assign trans_complete_o = is_last_aw & axi_dma_res_i.b_valid; + +endmodule : axi_dma_data_mover diff --git a/src/axi_dma_data_path.sv b/src/axi_dma_data_path.sv new file mode 100644 index 000000000..5bdea4474 --- /dev/null +++ b/src/axi_dma_data_path.sv @@ -0,0 +1,392 @@ +// Copyright (c) 2020 ETH Zurich, University of Bologna +// All rights reserved. +// +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// +// Thomas Benz + +/// Data path for the AXI DMA. This modules handles the R/W channel of the +/// AXI protocol. +/// Module gets read stream, realigns data and emits a write stream. +/// AXI-like valid/ready handshaking is used to communicate with the rest +/// of the backend. +module axi_dma_data_path #( + /// Data width of the AXI bus + parameter int DataWidth = -1, + /// Number of elements the realignment buffer can hold. To achieve + /// full performance a depth of 3 is minimally required. + parameter int BufferDepth = -1, + // DO NOT OVERWRITE THIS PARAMETER + parameter int StrbWidth = DataWidth / 8, + parameter int OffsetWidth = $clog2(StrbWidth) +) ( + // status signals + /// Clock + input logic clk_i, + /// Asynchronous reset, active low + input logic rst_ni, + + // handshaking signals + /// Handshake: read side of data path is presented with a valid request + input logic r_dp_valid_i, + /// Handshake: read side of data path is ready to accept new requests + output logic r_dp_ready_o, + /// Handshake: write side of data path is presented with a valid request + input logic w_dp_valid_i, + /// Handshake: write side of data path is ready to accept new requests + output logic w_dp_ready_o, + + // status signal + /// High if the data path is idle + output logic data_path_idle_o, + + // r-channel + /// Read data from the AXI bus + input logic [DataWidth-1:0] r_data_i, + /// Valid signal of the AXI r channel + input logic r_valid_i, + /// Last signal of the AXI r channel + input logic r_last_i, + /// Response signal of the AXI r channel + input logic [ 1:0] r_resp_i, + /// Ready signal of the AXI r channel + output logic r_ready_o, + + /// number of bytes the end of the read transfer is short to reach a + /// Bus-aligned boundary + input logic [OffsetWidth-1:0] r_tailer_i, + /// number of bytes the read transfers starts after a + /// Bus-aligned boundary + input logic [OffsetWidth-1:0] r_offset_i, + /// The amount the read data has to be shifted to write-align it + input logic [OffsetWidth-1:0] r_shift_i, + + // w-channel + /// Write data of the AXI bus + output logic [DataWidth-1:0] w_data_o, + /// Write strobe of the AXI bus + output logic [StrbWidth-1:0] w_strb_o, + /// Valid signal of the AXI w channel + output logic w_valid_o, + /// Last signal of the AXI w channel + output logic w_last_o, + /// Ready signal of the AXI w channel + input logic w_ready_i, + + /// number of bytes the write transfers starts after a + /// Bus-aligned boundary + input logic [OffsetWidth-1:0] w_offset_i, + /// number of bytes the end of the write transfer is short to reach a + /// Bus-aligned boundary + input logic [OffsetWidth-1:0] w_tailer_i, + /// Number of beats requested by this transfer + input logic [ 7:0] w_num_beats_i, + /// True if the transfer only consists of a single beat + input logic w_is_single_i +); + + // buffer contains 8 data bits per FIFO + // buffer is at least 3 deep to prevent stalls + + // 64 bit DATA Width example: + // DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD <- head + // DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD + // DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD <- tail + // -byte7--|-byte6--|-byte5--|-byte4--|-byte3--|-byte2--|-byte1--|-byte0--| + + + //-------------------------------------- + // Mask pre-calculation + //-------------------------------------- + // in contiguous transfers that are unaligned, there will be some + // invalid bytes at the beginning and the end of the stream + // example: 25B in 64 bit system + // iiiivvvv|vvvvvvvv|vvvvvvvv|vvvvviii + // last msk|----full mask----|first msk + + // offsets needed for masks to fill/empty buffer + logic [StrbWidth-1:0] r_first_mask; + logic [StrbWidth-1:0] r_last_mask; + logic [StrbWidth-1:0] w_first_mask; + logic [StrbWidth-1:0] w_last_mask; + + // read align masks + assign r_first_mask = '1 << r_offset_i; + assign r_last_mask = '1 >> (StrbWidth - r_tailer_i); + + // write align masks + assign w_first_mask = '1 << w_offset_i; + assign w_last_mask = '1 >> (StrbWidth - w_tailer_i); + + + //-------------------------------------- + // Barrel shifter + //-------------------------------------- + // data arrives in chuncks of length DATA_WDITH, the buffer will be filled with + // the realigned data. StrbWidth bytes will be inserted starting from the + // provided address, overflows will naturally wrap + + // signals connected to the buffer + logic [StrbWidth-1:0][7:0] buffer_in; + + // read aligned in mask. needs to be rotated together with the data before + // it can be used to fill in valid data into the buffer + logic [StrbWidth-1:0] read_aligned_in_mask; + + // in mask is write aligned, so it is the result of the read aligned in mask + // that is rotated together with the data in the barrel shifter + logic [StrbWidth-1:0] in_mask; + + // a barrel shifter is a concatenation of the same array with itself and a normal + // shift. + assign buffer_in = {r_data_i, r_data_i} >> (r_shift_i * 8); + assign in_mask = {read_aligned_in_mask, read_aligned_in_mask} >> r_shift_i; + + //-------------------------------------- + // In mask generation + //-------------------------------------- + // in the case of unaligned reads -> not all data is valid + logic is_first_r, is_first_r_d; + + always_comb begin : proc_in_mask_generator + // default case: all ones + read_aligned_in_mask = '1; + // is first word: some bytes at the beginning may be invalid + read_aligned_in_mask = is_first_r ? + read_aligned_in_mask & r_first_mask : read_aligned_in_mask; + // is last word in write burst: some bytes at the end may be invalid + if (r_tailer_i != '0) begin + read_aligned_in_mask = r_last_i ? + read_aligned_in_mask & r_last_mask : read_aligned_in_mask; + end + end + + //-------------------------------------- + // Read control + //-------------------------------------- + logic [StrbWidth-1:0] buffer_full; + logic [StrbWidth-1:0] buffer_push; + logic full; + // this signal is used for pushing data to the control fifo + logic push; + + always_comb begin : proc_read_control + // sticky is first bit for read + if (r_valid_i & !r_last_i) begin + // new transfer has started + is_first_r_d = 1'b0; + end else if (r_last_i & r_valid_i) begin + // finish read burst + is_first_r_d = 1'b1; + end else begin + // no change + is_first_r_d = is_first_r; + end + + // the buffer can be pushed to if all the masked fifo buffers (in_mask) are not full. + full = |(buffer_full & in_mask); + // the read can accept data if the buffer is not full + r_ready_o = ~full; + + // once valid data is applied, it can be pushed in all the selected (in_mask) buffers + push = r_valid_i && ~full; + buffer_push = push ? in_mask : '0; + + // r_dp_ready_o is triggered by the last element arriving from the read + r_dp_ready_o = r_dp_valid_i && r_last_i && r_valid_i && ~full;; + end + + //-------------------------------------- + // Out mask generation -> wstrb mask + //-------------------------------------- + // only pop the data actually needed for write from the buffer, + // determine valid data to pop by calculation the wstrb + logic [StrbWidth-1:0] out_mask; + logic is_first_w; + logic is_last_w; + + always_comb begin : proc_out_mask_generator + // default case: all ones + out_mask = '1; + // is first word: some bytes at the beginning may be invalid + out_mask = is_first_w ? (out_mask & w_first_mask) : out_mask; + // is last word in write burst: some bytes at the end may be invalid + if (w_tailer_i != '0) begin + out_mask = is_last_w ? out_mask & w_last_mask : out_mask; + end + end + + //-------------------------------------- + // Write control + //-------------------------------------- + // once buffer contains a full line -> all fifos are non-empty + // push it out. + // signals connected to the buffer + logic [StrbWidth-1:0][7:0] buffer_out; + logic [StrbWidth-1:0] buffer_empty; + logic [StrbWidth-1:0] buffer_pop; + + // write is decoupled from read, due to misalignments in the read/write + // addresses, page crossing can be encountered at any time. + // To handle this efficiently, a 2-to-1 or 1-to-2 mapping of r/w beats + // is required. The write unit needs to keep track of progress through + // a counter and cannot use `r_last` for that. + logic [7:0] w_num_beats_d, w_num_beats_q; + logic w_cnt_valid_d, w_cnt_valid_q; + + // data from buffer is popped + logic pop; + // write happens + logic write_happening; + // buffer is ready to write the requested data + logic ready_to_write; + // first transfer is possible - this signal is used to detect + // the first write transfer in a burst + logic first_possible; + // buffer is completely empty + logic buffer_clean; + + always_comb begin : proc_write_control + // counter + w_num_beats_d = w_num_beats_q; + w_cnt_valid_d = w_cnt_valid_q; + // buffer ctrl + pop = 1'b0; + buffer_pop = 'b0; + write_happening = 1'b0; + ready_to_write = 1'b0; + first_possible = 1'b0; + // bus signals + w_valid_o = 1'b0; + w_data_o = '0; + w_strb_o = '0; + w_last_o = 1'b0; + // mask control + is_first_w = 1'b0; + is_last_w = 1'b0; + // data flow + w_dp_ready_o = 1'b0; + + + // all elements needed (defined by the mask) are in the buffer and the buffer is non-empty + ready_to_write = ((~buffer_empty & out_mask) == out_mask) && (buffer_empty != '1); + + // data needed by the first mask is available in the buffer -> r_first happened for sure + // this signal can be high during a transfer as well, it needs to be masked + first_possible = ((~buffer_empty & w_first_mask) == w_first_mask) && (buffer_empty != '1); + + // the buffer is completely empty (debug only signal) + buffer_clean = &(buffer_empty); + + // write happening: both the bus (w_ready) and the buffer (ready_to_write) is high + write_happening = ready_to_write & w_ready_i; + + // signal the control fifo it could be popped + pop = write_happening; + + // the main buffer is conditionally to the write mask popped + buffer_pop = write_happening ? out_mask : '0; + + // signal the bus that we are ready + w_valid_o = ready_to_write; + + // control the write to the bus apply data to the bus only if data should be written + if (ready_to_write == 1'b1) begin + // assign data from buffers, mask out non valid entries + for (int i = 0; i < StrbWidth; i++) begin + w_data_o[i*8 +: 8] = out_mask[i] ? buffer_out[i] : 8'b0; + end + // assign the out mask to the strobe + w_strb_o = out_mask; + end + + // differentiate between the burst and non-burst case. If a transfer + // consists just of one beat the counters are disabled + if (w_is_single_i) begin + // in the single case the transfer is both first and last. + is_first_w = 1'b1; + is_last_w = 1'b1; + + // in the bursted case the counters are needed to keep track of the progress of sending + // beats. The w_last_o depends on the state of the counter + end else begin + // first transfer happens as soon as a) the buffer is ready for a first transfer and b) + // the counter is currently invalid + is_first_w = first_possible & ~w_cnt_valid_q; + + // last happens as soon as a) the counter is valid and b) the counter is now down to 1 + is_last_w = w_cnt_valid_q & (w_num_beats_q == 8'h01); + + // load the counter with data in a first cycle, only modifying state if bus is ready + if (is_first_w && write_happening) begin + w_num_beats_d = w_num_beats_i; + w_cnt_valid_d = 1'b1; + end + + // if we hit the last element, invalidate the counter, only modifying state + // if bus is ready + if (is_last_w && write_happening) begin + w_cnt_valid_d = 1'b0; + end + + // count down the beats if the counter is valid and valid data is written to the bus + if (w_cnt_valid_q && write_happening) w_num_beats_d = w_num_beats_q - 8'h01; + end + + // the w_last_o signal should only be applied to the bus if an actual transfer happens + w_last_o = is_last_w & ready_to_write; + + // we are ready for the next transfer internally, once the w_last_o signal is applied + w_dp_ready_o = is_last_w & write_happening; + end + + + //-------------------------------------- + // Buffer - implemented as fifo + //-------------------------------------- + logic control_empty; + + for (genvar i = 0; i < StrbWidth; i++) begin : fifo_buffer + fifo_v3 #( + .FALL_THROUGH ( 1'b0 ), + .DATA_WIDTH ( 8 ), + .DEPTH ( BufferDepth ) + ) i_fifo_buffer ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .full_o ( buffer_full [i] ), + .empty_o ( buffer_empty[i] ), + .usage_o ( ), + .data_i ( buffer_in [i] ), + .push_i ( buffer_push [i] ), + .data_o ( buffer_out [i] ), + .pop_i ( buffer_pop [i] ) + ); + end + + //-------------------------------------- + // Module Control + //------------------------------------- + assign data_path_idle_o = !(r_dp_valid_i | r_dp_ready_o | + w_dp_valid_i | w_dp_ready_o | !buffer_clean); + + always_ff @(posedge clk_i or negedge rst_ni) begin : proc_ff + if (!rst_ni) begin + is_first_r <= 1'b1; + w_cnt_valid_q <= 1'b0; + w_num_beats_q <= 8'h0; + end else begin + // running_q <= running_d; + if (r_valid_i & r_ready_o) is_first_r <= is_first_r_d; + w_cnt_valid_q <= w_cnt_valid_d; + w_num_beats_q <= w_num_beats_d; + end + end + +endmodule : axi_dma_data_path diff --git a/src/axi_sim_mem.sv b/src/axi_sim_mem.sv index a518be9a0..a19010b7c 100644 --- a/src/axi_sim_mem.sv +++ b/src/axi_sim_mem.sv @@ -224,10 +224,15 @@ module axi_sim_mem #( $warning("Access to non-initialized byte at address 0x%016x by ID 0x%x.", byte_addr, r_beat.id); end + // uncomment below line to emulate a initialized memory for the NoC + // mem[byte_addr] = byte_addr; + // comment below line to emulate a initialized memory for NoC r_beat.data[i_byte*8+:8] = 'x; end else begin r_beat.data[i_byte*8+:8] = mem[byte_addr]; end + // uncomment below line to emulate a initialized memory for the NoC + //r_beat.data[i_byte*8+:8] = mem[byte_addr]; end if (r_cnt == ar_queue[0].len) begin r_beat.last = 1'b1; diff --git a/src/axi_xp.sv b/src/axi_xp.sv new file mode 100644 index 000000000..b568d54eb --- /dev/null +++ b/src/axi_xp.sv @@ -0,0 +1,342 @@ +// Copyright (c) 2020 ETH Zurich, University of Bologna +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Authors: +// - Andreas Kurth +// - Vikram Jain + +`include "axi/typedef.svh" + +/// AXI Crosspoint (XP) with homomorphous slave and master ports. +module axi_xp #( + // Atomic operations settings + parameter bit ATOPs = 1'b1, + // xbar configuration + parameter axi_pkg::xbar_cfg_t Cfg = '0, + /// Number of slave ports. + parameter int unsigned NoSlvPorts = 32'd0, + /// Number of master ports. + parameter int unsigned NoMstPorts = 32'd0, + /// Connectivity from a slave port to the master ports. A `1'b1` in `Connectivity[i][j]` means + /// that slave port `i` is connected to master port `j`. By default, all slave ports are + /// connected to all master ports. + parameter bit [NoSlvPorts-1:0][NoMstPorts-1:0] Connectivity = '1, + /// Address width of all ports. + parameter int unsigned AxiAddrWidth = 32'd0, + /// Data width of all ports. + parameter int unsigned AxiDataWidth = 32'd0, + /// ID width of all ports. + parameter int unsigned AxiIdWidth = 32'd0, + /// User signal width of all ports. + parameter int unsigned AxiUserWidth = 32'd0, + /// Maximum number of different IDs that can be in flight at each slave port. Reads and writes + /// are counted separately (except for ATOPs, which count as both read and write). + /// + /// It is legal for upstream to have transactions with more unique IDs than the maximum given by + /// this parameter in flight, but a transaction exceeding the maximum will be stalled until all + /// transactions of another ID complete. + parameter int unsigned AxiSlvPortMaxUniqIds = 32'd0, + /// Maximum number of in-flight transactions with the same ID at the slave port. + /// + /// This parameter is only relevant if `AxiSlvPortMaxUniqIds <= 2**AxiMstPortIdWidth`. In that + /// case, this parameter is passed to [`axi_id_remap` as `AxiMaxTxnsPerId` + /// parameter](module.axi_id_remap#parameter.AxiMaxTxnsPerId). + parameter int unsigned AxiSlvPortMaxTxnsPerId = 32'd0, + /// Maximum number of in-flight transactions at the slave port. Reads and writes are counted + /// separately (except for ATOPs, which count as both read and write). + /// + /// This parameter is only relevant if `AxiSlvPortMaxUniqIds > 2**AxiMstPortIdWidth`. In that + /// case, this parameter is passed to + /// [`axi_id_serialize`](module.axi_id_serialize#parameter.AxiSlvPortMaxTxns). + parameter int unsigned AxiSlvPortMaxTxns = 32'd0, + /// Maximum number of different IDs that can be in flight at the master port. Reads and writes + /// are counted separately (except for ATOPs, which count as both read and write). + /// + /// This parameter is only relevant if `AxiSlvPortMaxUniqIds > 2**AxiMstPortIdWidth`. In that + /// case, this parameter is passed to + /// [`axi_id_serialize`](module.axi_id_serialize#parameter.AxiMstPortMaxUniqIds). + parameter int unsigned AxiMstPortMaxUniqIds = 32'd0, + /// Maximum number of in-flight transactions with the same ID at the master port. + /// + /// This parameter is only relevant if `AxiSlvPortMaxUniqIds > 2**AxiMstPortIdWidth`. In that + /// case, this parameter is passed to + /// [`axi_id_serialize`](module.axi_id_serialize#parameter.AxiMstPortMaxTxnsPerId). + parameter int unsigned AxiMstPortMaxTxnsPerId = 32'd0, + /// Number of rules in the address map. + parameter int unsigned NoAddrRules = 32'd0, + parameter type slv_aw_chan_t = logic, + parameter type mst_aw_chan_t = logic, + parameter type w_chan_t = logic, + parameter type slv_b_chan_t = logic, + parameter type mst_b_chan_t = logic, + parameter type slv_ar_chan_t = logic, + parameter type mst_ar_chan_t = logic, + parameter type slv_r_chan_t = logic, + parameter type mst_r_chan_t = logic, + /// Request struct type of the AXI4+ATOP slave port + parameter type slv_req_t = logic, + /// Response struct type of the AXI4+ATOP slave port + parameter type slv_resp_t = logic, + /// Request struct type of the AXI4+ATOP master port + parameter type mst_req_t = logic, + /// Response struct type of the AXI4+ATOP master port + parameter type mst_resp_t = logic, + /// Rule type (see documentation of `axi_xbar` for details). + parameter type rule_t = axi_pkg::xbar_rule_64_t +) ( + /// Rising-edge clock of all ports + input logic clk_i, + /// Asynchronous reset, active low + input logic rst_ni, + /// Test mode enable + input logic test_en_i, + /// Slave ports request + input slv_req_t [NoSlvPorts-1:0] slv_req_i, + /// Slave ports response + output slv_resp_t [NoSlvPorts-1:0] slv_resp_o, + /// Master ports request + output mst_req_t [NoMstPorts-1:0] mst_req_o, + /// Master ports response + input mst_resp_t [NoMstPorts-1:0] mst_resp_i, + /// Address map for transferring transactions from slave to master ports + input rule_t [NoAddrRules-1:0] addr_map_i +); + + parameter int unsigned AxiXbarIdWidth = AxiIdWidth + $clog2(NoSlvPorts); + typedef logic [AxiAddrWidth-1:0] addr_t; + typedef logic [AxiDataWidth-1:0] data_t; + typedef logic [AxiIdWidth-1:0] id_t; + typedef logic [AxiXbarIdWidth-1:0] xbar_id_t; + typedef logic [AxiDataWidth/8-1:0] strb_t; + typedef logic [AxiUserWidth-1:0] user_t; + + `AXI_TYPEDEF_AW_CHAN_T(aw_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(xbar_aw_t, addr_t, xbar_id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_t, id_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(xbar_b_t, xbar_id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(xbar_ar_t, addr_t, xbar_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_t, data_t, id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(xbar_r_t, data_t, xbar_id_t, user_t) + `AXI_TYPEDEF_REQ_T(req_t, aw_t, w_t, ar_t) + `AXI_TYPEDEF_REQ_T(xbar_req_t, xbar_aw_t, w_t, xbar_ar_t) + `AXI_TYPEDEF_RESP_T(resp_t, b_t, r_t) + `AXI_TYPEDEF_RESP_T(xbar_resp_t, xbar_b_t, xbar_r_t) + + xbar_req_t [NoMstPorts-1:0] xbar_req; + xbar_resp_t [NoMstPorts-1:0] xbar_resp; + + // localparam axi_pkg::xbar_cfg_t xbar_cfg = '{ + // NoSlvPorts: NoSlvPorts, + // NoMstPorts: NoMstPorts, + // MaxMstTrans: AxiMstPortMaxTxnsPerId, + // MaxSlvTrans: AxiSlvPortMaxTxns, + // FallThrough: 1'b0, + // LatencyMode: axi_pkg::CUT_ALL_PORTS, + // AxiIdWidthSlvPorts: AxiIdWidth, + // AxiIdUsedSlvPorts: AxiIdWidth, + // UniqueIds: AxiSlvPortMaxUniqIds, + // AxiAddrWidth: AxiAddrWidth, + // AxiDataWidth: AxiDataWidth, + // NoAddrRules: NoAddrRules + // }; + + axi_xbar #( + .Cfg ( Cfg ), + .ATOPs ( ATOPs ), + .Connectivity ( Connectivity ), + .slv_aw_chan_t ( aw_t ), + .mst_aw_chan_t ( xbar_aw_t ), + .w_chan_t ( w_t ), + .slv_b_chan_t ( b_t ), + .mst_b_chan_t ( xbar_b_t ), + .slv_ar_chan_t ( ar_t ), + .mst_ar_chan_t ( xbar_ar_t ), + .slv_r_chan_t ( r_t ), + .mst_r_chan_t ( xbar_r_t ), + .slv_req_t ( mst_req_t ), + .slv_resp_t ( mst_resp_t ), + .mst_req_t ( xbar_req_t ), + .mst_resp_t ( xbar_resp_t ), + .rule_t ( rule_t ) + ) i_xbar ( + .clk_i, + .rst_ni, + .test_i ( test_en_i ), + .slv_ports_req_i ( slv_req_i ), + .slv_ports_resp_o ( slv_resp_o ), + .mst_ports_req_o ( xbar_req ), + .mst_ports_resp_i ( xbar_resp ), + .addr_map_i, + .en_default_mst_port_i ( '0 ), + .default_mst_port_i ( '0 ) + ); + + // for (genvar i = 0; i < NoMstPorts; i++) begin : gen_iw_conv + // axi_iw_converter #( + // .AxiSlvPortIdWidth ( AxiXbarIdWidth ), + // .AxiMstPortIdWidth ( AxiIdWidth ), + // .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + // .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + // .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + // .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + // .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + // .AxiAddrWidth ( AxiAddrWidth ), + // .AxiDataWidth ( AxiDataWidth ), + // .AxiUserWidth ( AxiUserWidth ), + // .slv_req_t ( xbar_req_t ), + // .slv_resp_t ( xbar_resp_t ), + // .mst_req_t ( req_t ), + // .mst_resp_t ( resp_t ) + // ) i_axi_iw_converter ( + // .clk_i, + // .rst_ni, + // .slv_req_i ( xbar_req[i] ), + // .slv_resp_o ( xbar_resp[i] ), + // .mst_req_o ( mst_req_o[i] ), + // .mst_resp_i ( mst_resp_i[i] ) + // ); + // end + + for (genvar i = 0; i < NoMstPorts; i++) begin : gen_remap + axi_id_remap #( + .AxiSlvPortIdWidth ( AxiXbarIdWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiMstPortIdWidth ( AxiIdWidth ), + .slv_req_t ( xbar_req_t ), + .slv_resp_t ( xbar_resp_t ), + .mst_req_t ( mst_req_t ), + .mst_resp_t ( mst_resp_t ) + ) i_axi_id_remap ( + .clk_i, + .rst_ni, + .slv_req_i ( xbar_req[i] ), + .slv_resp_o ( xbar_resp[i] ), + .mst_req_o ( mst_req_o[i] ), + .mst_resp_i ( mst_resp_i[i] ) + ); + end + +endmodule + +`include "axi/assign.svh" +`include "axi/typedef.svh" + +module axi_xp_intf +import cf_math_pkg::idx_width; +#( + parameter bit ATOPs = 1'b1, + parameter axi_pkg::xbar_cfg_t Cfg = '0, + parameter int unsigned NoSlvPorts = 32'd0, + parameter int unsigned NoMstPorts = 32'd0, + parameter bit [NoSlvPorts-1:0][NoMstPorts-1:0] Connectivity = '1, + parameter int unsigned AxiAddrWidth = 32'd0, + parameter int unsigned AxiDataWidth = 32'd0, + parameter int unsigned AxiIdWidth = 32'd0, + parameter int unsigned AxiUserWidth = 32'd0, + parameter int unsigned AxiSlvPortMaxUniqIds = 32'd0, + parameter int unsigned AxiSlvPortMaxTxnsPerId = 32'd0, + parameter int unsigned AxiSlvPortMaxTxns = 32'd0, + parameter int unsigned AxiMstPortMaxUniqIds = 32'd0, + parameter int unsigned AxiMstPortMaxTxnsPerId = 32'd0, + parameter int unsigned NoAddrRules = 32'd0, + parameter type rule_t = axi_pkg::xbar_rule_64_t +) ( + input logic clk_i, + input logic rst_ni, + input logic test_en_i, + AXI_BUS.Slave slv_ports [NoSlvPorts-1:0], + AXI_BUS.Master mst_ports [NoMstPorts-1:0], + input rule_t [NoAddrRules-1:0] addr_map_i +); + + // localparam int unsigned AxiIdWidthMstPorts = AxiIdWidth + $clog2(NoSlvPorts); + + typedef logic [AxiIdWidth -1:0] id_mst_t; + typedef logic [AxiIdWidth -1:0] id_slv_t; + typedef logic [AxiAddrWidth -1:0] addr_t; + typedef logic [AxiDataWidth -1:0] data_t; + typedef logic [AxiDataWidth/8 -1:0] strb_t; + typedef logic [AxiUserWidth -1:0] user_t; + + `AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, addr_t, id_mst_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, addr_t, id_slv_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(mst_b_chan_t, id_mst_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, id_slv_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, addr_t, id_mst_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, addr_t, id_slv_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, data_t, id_mst_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, data_t, id_slv_t, user_t) + `AXI_TYPEDEF_REQ_T(mst_req_t, mst_aw_chan_t, w_chan_t, mst_ar_chan_t) + `AXI_TYPEDEF_REQ_T(slv_req_t, slv_aw_chan_t, w_chan_t, slv_ar_chan_t) + `AXI_TYPEDEF_RESP_T(mst_resp_t, mst_b_chan_t, mst_r_chan_t) + `AXI_TYPEDEF_RESP_T(slv_resp_t, slv_b_chan_t, slv_r_chan_t) + + mst_req_t [NoMstPorts-1:0] mst_reqs; + mst_resp_t [NoMstPorts-1:0] mst_resps; + slv_req_t [NoSlvPorts-1:0] slv_reqs; + slv_resp_t [NoSlvPorts-1:0] slv_resps; + + for (genvar i = 0; i < NoMstPorts; i++) begin : gen_assign_mst + `AXI_ASSIGN_FROM_REQ(mst_ports[i], mst_reqs[i]) + `AXI_ASSIGN_TO_RESP(mst_resps[i], mst_ports[i]) + end + + for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_assign_slv + `AXI_ASSIGN_TO_REQ(slv_reqs[i], slv_ports[i]) + `AXI_ASSIGN_FROM_RESP(slv_ports[i], slv_resps[i]) + end + + axi_xp #( + .ATOPs ( ATOPs ), + .Cfg ( Cfg ), + .NoSlvPorts ( NoSlvPorts ), + .NoMstPorts ( NoMstPorts ), + .Connectivity ( Connectivity ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( NoAddrRules ), + .slv_aw_chan_t ( slv_aw_chan_t ), + .mst_aw_chan_t ( mst_aw_chan_t ), + .w_chan_t ( w_chan_t ), + .slv_b_chan_t ( slv_b_chan_t ), + .mst_b_chan_t ( mst_b_chan_t ), + .slv_ar_chan_t ( slv_ar_chan_t ), + .mst_ar_chan_t ( mst_ar_chan_t ), + .slv_r_chan_t ( slv_r_chan_t ), + .mst_r_chan_t ( mst_r_chan_t ), + .slv_req_t ( slv_req_t ), + .slv_resp_t ( slv_resp_t ), + .mst_req_t ( mst_req_t ), + .mst_resp_t ( mst_resp_t ), + .rule_t ( rule_t ) + ) i_xp ( + .clk_i, + .rst_ni, + .test_en_i, + .slv_req_i (slv_reqs ), + .slv_resp_o (slv_resps), + .mst_req_o (mst_reqs ), + .mst_resp_i (mst_resps), + .addr_map_i + ); + +endmodule \ No newline at end of file diff --git a/src_files.yml b/src_files.yml index 752fd90df..c83edfbd0 100644 --- a/src_files.yml +++ b/src_files.yml @@ -48,6 +48,7 @@ axi: - src/axi_iw_converter.sv - src/axi_lite_xbar.sv - src/axi_xbar.sv + - src/axi_xp.sv axi_sim: files: diff --git a/test/fixture_axi_dma_backend.sv b/test/fixture_axi_dma_backend.sv new file mode 100644 index 000000000..a3f527fe2 --- /dev/null +++ b/test/fixture_axi_dma_backend.sv @@ -0,0 +1,4664 @@ +// Copyright (c) 2019 ETH Zurich, University of Bologna +// All rights reserved. +// +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// +// Thomas Benz + +// fixture for the AXi DMA backend +// the fixture instantiates the DMA backend, a golden model of the backend , and tasks controlling +// both. + +`timescale 1ns/1ns +module fixture_axi_dma_backend(); + + // `include "../axi/include/axi/assign.svh" + `define MASTERS_16 + `define MEM_DEBUG 1 + `include "axi/assign.svh" + `include "axi/typedef.svh" + + //-------------------------------------- + // Parameters + //-------------------------------------- + localparam TA = 0.2ns; // must be nonzero to avoid Snitch load fifo double pop glitch + localparam TT = 0.8ns; + localparam HalfPeriod = 5ns; + localparam Reset = 7.5ns; + + localparam DataWidth = 32; + localparam AddrWidth = 32; + localparam StrbWidth = DataWidth / 8; + localparam IdWidth = 6; + localparam UserWidth = 1; + + // DUT parameters + localparam bit ATOPs = 0; + localparam int unsigned NoMst = 16; + localparam int unsigned NoSlv = 16; + localparam int unsigned NoSlvPorts_2 = 5; + localparam int unsigned NoMstPorts_2 = 5; + localparam int unsigned NoSlvPorts_1 = 4; + localparam int unsigned NoMstPorts_1 = 4; + localparam int unsigned NoSlvPorts_0 = 3; + localparam int unsigned NoMstPorts_0 = 3; + localparam bit [NoSlvPorts_2-1:0][NoMstPorts_2-1:0] Connectivity_2 = {5'h1f,5'h1f,5'h1f,5'h1f,5'h1f}; + localparam bit [NoSlvPorts_1-1:0][NoMstPorts_1-1:0] Connectivity_1 = {4'hf,4'hf,4'hf,4'hf}; + localparam bit [NoSlvPorts_0-1:0][NoMstPorts_0-1:0] Connectivity_0 = '1;//{3'h6,3'h6,3'h6}; + localparam int unsigned AxiSlvPortMaxUniqIds = 32'd16; + localparam int unsigned AxiSlvPortMaxTxnsPerId = 32'd128; + localparam int unsigned AxiSlvPortMaxTxns = 32'd31; + localparam int unsigned AxiMstPortMaxUniqIds = 32'd4; + localparam int unsigned AxiMstPortMaxTxnsPerId = 32'd7; + localparam int unsigned NoAddrRules_2 = 32'd5; + localparam int unsigned NoAddrRules_1 = 32'd4; + localparam int unsigned NoAddrRules_0 = 32'd3; + + typedef axi_pkg::xbar_rule_32_t rule_t; // Has to be the same width as axi addr + + // axi configuration + localparam int unsigned AxiIdWidthMasters = IdWidth; + localparam int unsigned AxiIdUsed = IdWidth-1; // Has to be <= AxiIdWidthMasters + localparam int unsigned AxiIdWidthSlaves = AxiIdWidthMasters + $clog2(NoMstPorts_1); + localparam int unsigned AxiAddrWidth = AddrWidth; // Axi Address Width + localparam int unsigned AxiDataWidth = DataWidth; // Axi Data Width + localparam int unsigned AxiStrbWidth = StrbWidth; + localparam int unsigned AxiUserWidth = UserWidth; + localparam int unsigned AxiIdWidth = IdWidth; + + // in the bench can change this variables which are set here freely + localparam axi_pkg::xbar_cfg_t xbar_cfg_2 = '{ + NoSlvPorts: NoMstPorts_2, + NoMstPorts: NoSlvPorts_2, + MaxMstTrans: AxiSlvPortMaxTxns, + MaxSlvTrans: AxiSlvPortMaxTxnsPerId, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_PORTS, + AxiIdWidthSlvPorts: AxiIdWidthMasters, + AxiIdUsedSlvPorts: AxiIdUsed, + UniqueIds: 1'b0, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: NoAddrRules_2 + }; + + localparam axi_pkg::xbar_cfg_t xbar_cfg_1 = '{ + NoSlvPorts: NoMstPorts_1, + NoMstPorts: NoSlvPorts_1, + MaxMstTrans: AxiSlvPortMaxTxns, + MaxSlvTrans: AxiSlvPortMaxTxnsPerId, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_PORTS, + AxiIdWidthSlvPorts: AxiIdWidthMasters, + AxiIdUsedSlvPorts: AxiIdUsed, + UniqueIds: 1'b0, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: NoAddrRules_1 + }; + + localparam axi_pkg::xbar_cfg_t xbar_cfg_0 = '{ + NoSlvPorts: NoMstPorts_0, + NoMstPorts: NoSlvPorts_0, + MaxMstTrans: AxiSlvPortMaxTxns, + MaxSlvTrans: AxiSlvPortMaxTxnsPerId, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_PORTS, + AxiIdWidthSlvPorts: AxiIdWidthMasters, + AxiIdUsedSlvPorts: AxiIdUsed, + UniqueIds: 1'b0, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: NoAddrRules_0 + }; + + //localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2 = '{ + // '{idx: 32'd1 % NoSlvPorts_1, start_addr: {AddrWidth{1'b0}}, end_addr: {1'b0, {(AddrWidth-1){1'b1}}}}, + // '{idx: 32'd0 % NoSlvPorts_1, start_addr: {1'b0, {(AddrWidth-1){1'b1}}}, end_addr: {(AddrWidth){1'b1}}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + //}; + + // localparam rule_t [xbar_cfg_0.NoAddrRules-1:0] AddrMap_xp0 = '{ + // '{idx: 32'd2 % NoSlvPorts_0, start_addr: {32'h0fffffff}, end_addr: {32'hffffffff}}, + // '{idx: 32'd1 % NoSlvPorts_0, start_addr: {32'h0000ffff}, end_addr: {32'h0fffffff}}, + // '{idx: 32'd0 % NoSlvPorts_0, start_addr: {32'b0}, end_addr: {32'h0000ffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp1 = '{ + // '{idx: 32'd3 % NoSlvPorts_1, start_addr: {32'b0}, end_addr: {32'h00000fff}}, + // '{idx: 32'd2 % NoSlvPorts_1, start_addr: {32'h00000fff}, end_addr: {32'h000fffff}}, + // '{idx: 32'd1 % NoSlvPorts_1, start_addr: {32'h0fffffff}, end_addr: {32'hffffffff}}, + // '{idx: 32'd0 % NoSlvPorts_1, start_addr: {32'h000fffff}, end_addr: {32'h0fffffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2 = '{ + // // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'b0}, end_addr: {32'h00000fff}}, + // // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h000fffff}}, + // // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h000fffff}, end_addr: {32'h00ffffff}}, + // // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h00ffffff}, end_addr: {32'h0fffffff}}, + // // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h0fffffff}, end_addr: {32'hffffffff}} + // // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // // }; + + // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2_1 = '{ + // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'b0}, end_addr: {32'h00000fff}}, + // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h0fffffff}, end_addr: {32'hffffffff}}, + // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h000fffff}}, + // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h000fffff}, end_addr: {32'h00ffffff}}, + // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h00ffffff}, end_addr: {32'h0fffffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2_2 = '{ + // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'b0}, end_addr: {32'h00000fff}}, + // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h000fffff}}, + // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h000fffff}, end_addr: {32'h00ffffff}}, + // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h00ffffff}, end_addr: {32'h0fffffff}}, + // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h0fffffff}, end_addr: {32'hffffffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2_3 = '{ + // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h0fffffff}, end_addr: {32'hffffffff}}, + // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h00000000}, end_addr: {32'h00000fff}}, + // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h000fffff}}, + // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h000fffff}, end_addr: {32'h00ffffff}}, + // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h00ffffff}, end_addr: {32'h0fffffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + //localparam rule_t [xbar_cfg_0.NoAddrRules-1:0] AddrMap_xp0 = '{ + // '{idx: 32'd0 % NoSlvPorts_0, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + //}; + + //////////////////////////////// Realtime traffic start ////////////////////////////////////// + + ////// row 1 + + localparam rule_t [xbar_cfg_0.NoAddrRules-1:0] AddrMap_xp0 = '{ + '{idx: 32'd2 % NoSlvPorts_0, start_addr: {32'h11000000}, end_addr: {32'hffffffff}}, + '{idx: 32'd1 % NoSlvPorts_0, start_addr: {32'h10400000}, end_addr: {32'h11000000}}, + '{idx: 32'd0 % NoSlvPorts_0, start_addr: {32'h10000000}, end_addr: {32'h10400000}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp1 = '{ + '{idx: 32'd3 % NoSlvPorts_1, start_addr: {32'h10800000}, end_addr: {32'h11000000}}, + '{idx: 32'd2 % NoSlvPorts_1, start_addr: {32'h11000000}, end_addr: {32'hffffffff}}, + '{idx: 32'd1 % NoSlvPorts_1, start_addr: {32'h10000000}, end_addr: {32'h10400000}}, + '{idx: 32'd0 % NoSlvPorts_1, start_addr: {32'h10400000}, end_addr: {32'h10800000}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp2 = '{ + '{idx: 32'd3 % NoSlvPorts_1, start_addr: {32'h10000000}, end_addr: {32'h10800000}}, + '{idx: 32'd2 % NoSlvPorts_1, start_addr: {32'h11000000}, end_addr: {32'hffffffff}}, + '{idx: 32'd1 % NoSlvPorts_1, start_addr: {32'h10c00000}, end_addr: {32'h11000000}}, + '{idx: 32'd0 % NoSlvPorts_1, start_addr: {32'h10800000}, end_addr: {32'h10c00000}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_0.NoAddrRules-1:0] AddrMap_xp3 = '{ + '{idx: 32'd2 % NoSlvPorts_0, start_addr: {32'h11000000}, end_addr: {32'hffffffff}}, + '{idx: 32'd1 % NoSlvPorts_0, start_addr: {32'h10000000}, end_addr: {32'h10c00000}}, + '{idx: 32'd0 % NoSlvPorts_0, start_addr: {32'h10c00000}, end_addr: {32'h11000000}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + ////// row 2 + + localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp4 = '{ + '{idx: 32'd3 % NoSlvPorts_1, start_addr: {32'h12000000}, end_addr: {32'hffffffff}}, + '{idx: 32'd2 % NoSlvPorts_1, start_addr: {32'h10000000}, end_addr: {32'h11000000}}, + '{idx: 32'd1 % NoSlvPorts_1, start_addr: {32'h11400000}, end_addr: {32'h12000000}}, + '{idx: 32'd0 % NoSlvPorts_1, start_addr: {32'h11000000}, end_addr: {32'h11400000}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp5 = '{ + '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h12000000}, end_addr: {32'hffffffff}}, + '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h11800000}, end_addr: {32'h12000000}}, + '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h10000000}, end_addr: {32'h11000000}}, + '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h11000000}, end_addr: {32'h11400000}}, + '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h11400000}, end_addr: {32'h11800000}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp6 = '{ + '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h12000000}, end_addr: {32'hffffffff}}, + '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h11000000}, end_addr: {32'h11800000}}, + '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h10000000}, end_addr: {32'h11000000}}, + '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h11c00000}, end_addr: {32'h12000000}}, + '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h11800000}, end_addr: {32'h11c00000}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp7 = '{ + '{idx: 32'd3 % NoSlvPorts_1, start_addr: {32'h12000000}, end_addr: {32'hffffffff}}, + '{idx: 32'd2 % NoSlvPorts_1, start_addr: {32'h10000000}, end_addr: {32'h11000000}}, + '{idx: 32'd1 % NoSlvPorts_1, start_addr: {32'h11000000}, end_addr: {32'h11c00000}}, + '{idx: 32'd0 % NoSlvPorts_1, start_addr: {32'h11c00000}, end_addr: {32'h12000000}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + ////// row 3 + + localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp8 = '{ + '{idx: 32'd3 % NoSlvPorts_1, start_addr: {32'h10000000}, end_addr: {32'h12000000}}, + '{idx: 32'd2 % NoSlvPorts_1, start_addr: {32'h13000000}, end_addr: {32'hffffffff}}, + '{idx: 32'd1 % NoSlvPorts_1, start_addr: {32'h12400000}, end_addr: {32'h13000000}}, + '{idx: 32'd0 % NoSlvPorts_1, start_addr: {32'h12000000}, end_addr: {32'h12400000}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp9 = '{ + '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h10000000}, end_addr: {32'h12000000}}, + '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h12800000}, end_addr: {32'h13000000}}, + '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h13000000}, end_addr: {32'hffffffff}}, + '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h12000000}, end_addr: {32'h12400000}}, + '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h12400000}, end_addr: {32'h12800000}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp10 = '{ + '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h10000000}, end_addr: {32'h12000000}}, + '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h12000000}, end_addr: {32'h12800000}}, + '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h13000000}, end_addr: {32'hffffffff}}, + '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h12c00000}, end_addr: {32'h13000000}}, + '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h12800000}, end_addr: {32'h12c00000}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp11 = '{ + '{idx: 32'd3 % NoSlvPorts_1, start_addr: {32'h10000000}, end_addr: {32'h12000000}}, + '{idx: 32'd2 % NoSlvPorts_1, start_addr: {32'h13000000}, end_addr: {32'hffffffff}}, + '{idx: 32'd1 % NoSlvPorts_1, start_addr: {32'h12000000}, end_addr: {32'h12c00000}}, + '{idx: 32'd0 % NoSlvPorts_1, start_addr: {32'h12c00000}, end_addr: {32'h13000000}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + ////// row 4 + + localparam rule_t [xbar_cfg_0.NoAddrRules-1:0] AddrMap_xp12 = '{ + '{idx: 32'd2 % NoSlvPorts_0, start_addr: {32'h10000000}, end_addr: {32'h13000000}}, + '{idx: 32'd1 % NoSlvPorts_0, start_addr: {32'h13400000}, end_addr: {32'hffffffff}}, + '{idx: 32'd0 % NoSlvPorts_0, start_addr: {32'h13000000}, end_addr: {32'h13400000}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp13 = '{ + '{idx: 32'd3 % NoSlvPorts_1, start_addr: {32'h13800000}, end_addr: {32'hffffffff}}, + '{idx: 32'd2 % NoSlvPorts_1, start_addr: {32'h10000000}, end_addr: {32'h13000000}}, + '{idx: 32'd1 % NoSlvPorts_1, start_addr: {32'h13000000}, end_addr: {32'h13400000}}, + '{idx: 32'd0 % NoSlvPorts_1, start_addr: {32'h13400000}, end_addr: {32'h13800000}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp14 = '{ + '{idx: 32'd3 % NoSlvPorts_1, start_addr: {32'h13000000}, end_addr: {32'h13800000}}, + '{idx: 32'd2 % NoSlvPorts_1, start_addr: {32'h10000000}, end_addr: {32'h13000000}}, + '{idx: 32'd1 % NoSlvPorts_1, start_addr: {32'h13c00000}, end_addr: {32'hffffffff}}, + '{idx: 32'd0 % NoSlvPorts_1, start_addr: {32'h13800000}, end_addr: {32'h13c00000}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_0.NoAddrRules-1:0] AddrMap_xp15 = '{ + '{idx: 32'd2 % NoSlvPorts_0, start_addr: {32'h10000000}, end_addr: {32'h13000000}}, + '{idx: 32'd1 % NoSlvPorts_0, start_addr: {32'h13000000}, end_addr: {32'h13c00000}}, + '{idx: 32'd0 % NoSlvPorts_0, start_addr: {32'h13c00000}, end_addr: {32'hffffffff}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + //////////////////// 4 egress L2 ////////////////// + + // localparam rule_t [xbar_cfg_0.NoAddrRules-1:0] AddrMap_xp12 = '{ + // '{idx: 32'd2 % NoSlvPorts_0, start_addr: {32'h10000000}, end_addr: {32'h13000000}}, + // '{idx: 32'd1 % NoSlvPorts_0, start_addr: {32'h00000000}, end_addr: {32'h10000000}}, + // '{idx: 32'd0 % NoSlvPorts_0, start_addr: {32'h13000000}, end_addr: {32'hffffffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp13 = '{ + // '{idx: 32'd3 % NoSlvPorts_1, start_addr: {32'h00000000}, end_addr: {32'h10000000}}, + // '{idx: 32'd2 % NoSlvPorts_1, start_addr: {32'h10000000}, end_addr: {32'h13000000}}, + // '{idx: 32'd1 % NoSlvPorts_1, start_addr: {32'h13000000}, end_addr: {32'h13400000}}, + // '{idx: 32'd0 % NoSlvPorts_1, start_addr: {32'h13400000}, end_addr: {32'hffffffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp14 = '{ + // '{idx: 32'd3 % NoSlvPorts_1, start_addr: {32'h13000000}, end_addr: {32'h13800000}}, + // '{idx: 32'd2 % NoSlvPorts_1, start_addr: {32'h10000000}, end_addr: {32'h13000000}}, + // '{idx: 32'd1 % NoSlvPorts_1, start_addr: {32'h00000000}, end_addr: {32'h10000000}}, + // '{idx: 32'd0 % NoSlvPorts_1, start_addr: {32'h13800000}, end_addr: {32'hffffffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // localparam rule_t [xbar_cfg_0.NoAddrRules-1:0] AddrMap_xp15 = '{ + // '{idx: 32'd2 % NoSlvPorts_0, start_addr: {32'h10000000}, end_addr: {32'h13000000}}, + // '{idx: 32'd1 % NoSlvPorts_0, start_addr: {32'h13000000}, end_addr: {32'h13c00000}}, + // '{idx: 32'd0 % NoSlvPorts_0, start_addr: {32'h13c00000}, end_addr: {32'hffffffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + //////////////////////////////// Realtime traffic end ////////////////////////////////////// + + typedef union packed { + logic [StrbWidth-1:0][7:0] bytes; + logic [DataWidth-1:0] data; + } block_t; + + /// Address Type + typedef logic [ AddrWidth-1:0] addr_t; + /// Data Type + typedef logic [ DataWidth-1:0] data_t; + /// Strobe Type + typedef logic [ StrbWidth-1:0] strb_t; + /// AXI ID Type + typedef logic [ IdWidth-1:0] axi_id_t; + /// AXI USER Type + typedef logic [ UserWidth-1:0] user_t; + /// 1D burst request + typedef struct packed { + axi_id_t id; + addr_t src, dst, num_bytes; + axi_pkg::cache_t cache_src, cache_dst; + axi_pkg::burst_t burst_src, burst_dst; + logic decouple_rw; + logic deburst; + logic serialize; + } burst_req_t; + + // master AXI bus --> DMA + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_dma_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_dma_t, axi_id_t, user_t) + + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_dma_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_dma_t, data_t, axi_id_t, user_t) + + `AXI_TYPEDEF_REQ_T(dma_req_t, aw_chan_dma_t, w_chan_t, ar_chan_dma_t) + `AXI_TYPEDEF_RESP_T(dma_resp_t, b_chan_dma_t, r_chan_dma_t) + + // slave AXI bus --> mem + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_mem_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_mem_t, axi_id_t, user_t) + + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_mem_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_mem_t, data_t, axi_id_t, user_t) + + `AXI_TYPEDEF_REQ_T(mem_req_t, aw_chan_mem_t, w_chan_t, ar_chan_mem_t) + `AXI_TYPEDEF_RESP_T(mem_resp_t, b_chan_mem_t, r_chan_mem_t) + + //-------------------------------------- + // Clock and Reset + //-------------------------------------- + logic clk; + initial begin + forever begin + clk = 0; + #HalfPeriod; + clk = 1; + #HalfPeriod; + end + end + + logic rst_n; + initial begin + rst_n = 0; + #Reset; + rst_n = 1; + end + + task wait_for_reset; + @(posedge rst_n); + @(posedge clk); + endtask + + //-------------------------------------- + // DUT Axi busses + //-------------------------------------- + + dma_req_t [NoMst-1:0] axi_dma_req; + dma_resp_t [NoMst-1:0] axi_dma_res; + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) dma [NoMst-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) dma_sync [NoMst-1:0] (); + + AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) dma_dv [NoMst-1:0] (clk); + + for (genvar i = 0; i < NoMst; i++) begin : gen_conn_dv_masters + //`AXI_ASSIGN (dma_dv[i], dma[i]) + `AXI_ASSIGN_FROM_REQ(dma[i], axi_dma_req[i]) + `AXI_ASSIGN_TO_RESP(axi_dma_res[i], dma[i]) + end + + ////////////////////////////////////////// Row 1 ///////////////////////////////////////// + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_mst [NoMstPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_mst_2 [0:0] (); + + `AXI_ASSIGN (mem_0[0], xp0_mst[0]) + `AXI_ASSIGN (xp0_mst_1[0], xp0_mst[1]) + `AXI_ASSIGN (xp0_mst_2[0], xp0_mst[2]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_slv [NoSlvPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_slv_2 [0:0] (); + + `AXI_ASSIGN (xp0_slv[0], dma_sync[0]) + `AXI_ASSIGN (xp0_slv[1], xp0_slv_1[0]) + `AXI_ASSIGN (xp0_slv[2], xp0_slv_2[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_mst [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_mst_3 [0:0] (); + + `AXI_ASSIGN (mem_0[1], xp1_mst[0]) + `AXI_ASSIGN (xp1_mst_1[0], xp1_mst[1]) + `AXI_ASSIGN (xp1_mst_2[0], xp1_mst[2]) + `AXI_ASSIGN (xp1_mst_3[0], xp1_mst[3]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_slv_3 [0:0] (); + + `AXI_ASSIGN (xp1_slv[0], dma_sync[1]) + `AXI_ASSIGN (xp1_slv[1], xp1_slv_1[0]) + `AXI_ASSIGN (xp1_slv[2], xp1_slv_2[0]) + `AXI_ASSIGN (xp1_slv[3], xp1_slv_3[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_mst [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_mst_3 [0:0] (); + + `AXI_ASSIGN (mem_0[2], xp2_mst[0]) + `AXI_ASSIGN (xp2_mst_1[0], xp2_mst[1]) + `AXI_ASSIGN (xp2_mst_2[0], xp2_mst[2]) + `AXI_ASSIGN (xp2_mst_3[0], xp2_mst[3]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_slv_3 [0:0] (); + + `AXI_ASSIGN (xp2_slv[0], dma_sync[2]) + `AXI_ASSIGN (xp2_slv[1], xp2_slv_1[0]) + `AXI_ASSIGN (xp2_slv[2], xp2_slv_2[0]) + `AXI_ASSIGN (xp2_slv[3], xp2_slv_3[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_mst [NoMstPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_mst_2 [0:0] (); + + `AXI_ASSIGN (mem_0[3], xp3_mst[0]) + `AXI_ASSIGN (xp3_mst_1[0], xp3_mst[1]) + `AXI_ASSIGN (xp3_mst_2[0], xp3_mst[2]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_slv [NoSlvPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_slv_2 [0:0] (); + + `AXI_ASSIGN (xp3_slv[0], dma_sync[3]) + `AXI_ASSIGN (xp3_slv[1], xp3_slv_1[0]) + `AXI_ASSIGN (xp3_slv[2], xp3_slv_2[0]) + + /////////////////////////////////////////// Row 2 //////////////////////////////////////////////// + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp4_mst [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp4_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp4_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp4_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp4_mst_3 [0:0] (); + + `AXI_ASSIGN (mem_0[4], xp4_mst[0]) + `AXI_ASSIGN (xp4_mst_1[0], xp4_mst[1]) + `AXI_ASSIGN (xp4_mst_2[0], xp4_mst[2]) + `AXI_ASSIGN (xp4_mst_3[0], xp4_mst[3]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp4_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp4_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp4_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp4_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp4_slv_3 [0:0] (); + + `AXI_ASSIGN (xp4_slv[0], dma_sync[4]) + `AXI_ASSIGN (xp4_slv[1], xp4_slv_1[0]) + `AXI_ASSIGN (xp4_slv[2], xp4_slv_2[0]) + `AXI_ASSIGN (xp4_slv[3], xp4_slv_3[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_mst [NoMstPorts_2-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_mst_3 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_mst_4 [0:0] (); + + `AXI_ASSIGN (mem_0[5], xp5_mst[0]) + `AXI_ASSIGN (xp5_mst_1[0], xp5_mst[1]) + `AXI_ASSIGN (xp5_mst_2[0], xp5_mst[2]) + `AXI_ASSIGN (xp5_mst_3[0], xp5_mst[3]) + `AXI_ASSIGN (xp5_mst_4[0], xp5_mst[4]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_slv [NoSlvPorts_2-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_slv_3 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_slv_4 [0:0] (); + + `AXI_ASSIGN (xp5_slv[0], dma_sync[5]) + `AXI_ASSIGN (xp5_slv[1], xp5_slv_1[0]) + `AXI_ASSIGN (xp5_slv[2], xp5_slv_2[0]) + `AXI_ASSIGN (xp5_slv[3], xp5_slv_3[0]) + `AXI_ASSIGN (xp5_slv[4], xp5_slv_4[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_mst [NoMstPorts_2-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_mst_3 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_mst_4 [0:0] (); + + `AXI_ASSIGN (mem_0[6], xp6_mst[0]) + `AXI_ASSIGN (xp6_mst_1[0], xp6_mst[1]) + `AXI_ASSIGN (xp6_mst_2[0], xp6_mst[2]) + `AXI_ASSIGN (xp6_mst_3[0], xp6_mst[3]) + `AXI_ASSIGN (xp6_mst_4[0], xp6_mst[4]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_slv [NoSlvPorts_2-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_slv_3 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_slv_4 [0:0] (); + + `AXI_ASSIGN (xp6_slv[0], dma_sync[6]) + `AXI_ASSIGN (xp6_slv[1], xp6_slv_1[0]) + `AXI_ASSIGN (xp6_slv[2], xp6_slv_2[0]) + `AXI_ASSIGN (xp6_slv[3], xp6_slv_3[0]) + `AXI_ASSIGN (xp6_slv[4], xp6_slv_4[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp7_mst [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp7_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp7_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp7_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp7_mst_3 [0:0] (); + + `AXI_ASSIGN (mem_0[7], xp7_mst[0]) + `AXI_ASSIGN (xp7_mst_1[0], xp7_mst[1]) + `AXI_ASSIGN (xp7_mst_2[0], xp7_mst[2]) + `AXI_ASSIGN (xp7_mst_3[0], xp7_mst[3]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp7_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp7_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp7_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp7_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp7_slv_3 [0:0] (); + + `AXI_ASSIGN (xp7_slv[0], dma_sync[7]) + `AXI_ASSIGN (xp7_slv[1], xp7_slv_1[0]) + `AXI_ASSIGN (xp7_slv[2], xp7_slv_2[0]) + `AXI_ASSIGN (xp7_slv[3], xp7_slv_3[0]) + + /////////////////////////////////////////// Row 3 //////////////////////////////////////////////// + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp8_mst [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp8_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp8_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp8_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp8_mst_3 [0:0] (); + + `AXI_ASSIGN (mem_0[8], xp8_mst[0]) + `AXI_ASSIGN (xp8_mst_1[0], xp8_mst[1]) + `AXI_ASSIGN (xp8_mst_2[0], xp8_mst[2]) + `AXI_ASSIGN (xp8_mst_3[0], xp8_mst[3]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp8_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp8_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp8_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp8_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp8_slv_3 [0:0] (); + + `AXI_ASSIGN (xp8_slv[0], dma_sync[8]) + `AXI_ASSIGN (xp8_slv[1], xp8_slv_1[0]) + `AXI_ASSIGN (xp8_slv[2], xp8_slv_2[0]) + `AXI_ASSIGN (xp8_slv[3], xp8_slv_3[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_mst [NoMstPorts_2-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_mst_3 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_mst_4 [0:0] (); + + `AXI_ASSIGN (mem_0[9], xp9_mst[0]) + `AXI_ASSIGN (xp9_mst_1[0], xp9_mst[1]) + `AXI_ASSIGN (xp9_mst_2[0], xp9_mst[2]) + `AXI_ASSIGN (xp9_mst_3[0], xp9_mst[3]) + `AXI_ASSIGN (xp9_mst_4[0], xp9_mst[4]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_slv [NoSlvPorts_2-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_slv_3 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_slv_4 [0:0] (); + + `AXI_ASSIGN (xp9_slv[0], dma_sync[9]) + `AXI_ASSIGN (xp9_slv[1], xp9_slv_1[0]) + `AXI_ASSIGN (xp9_slv[2], xp9_slv_2[0]) + `AXI_ASSIGN (xp9_slv[3], xp9_slv_3[0]) + `AXI_ASSIGN (xp9_slv[4], xp9_slv_4[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_mst [NoMstPorts_2-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_mst_3 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_mst_4 [0:0] (); + + `AXI_ASSIGN (mem_0[10], xp10_mst[0]) + `AXI_ASSIGN (xp10_mst_1[0], xp10_mst[1]) + `AXI_ASSIGN (xp10_mst_2[0], xp10_mst[2]) + `AXI_ASSIGN (xp10_mst_3[0], xp10_mst[3]) + `AXI_ASSIGN (xp10_mst_4[0], xp10_mst[4]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_slv [NoSlvPorts_2-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_slv_3 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_slv_4 [0:0] (); + + `AXI_ASSIGN (xp10_slv[0], dma_sync[10]) + `AXI_ASSIGN (xp10_slv[1], xp10_slv_1[0]) + `AXI_ASSIGN (xp10_slv[2], xp10_slv_2[0]) + `AXI_ASSIGN (xp10_slv[3], xp10_slv_3[0]) + `AXI_ASSIGN (xp10_slv[4], xp10_slv_4[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp11_mst [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp11_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp11_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp11_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp11_mst_3 [0:0] (); + + `AXI_ASSIGN (mem_0[11], xp11_mst[0]) + `AXI_ASSIGN (xp11_mst_1[0], xp11_mst[1]) + `AXI_ASSIGN (xp11_mst_2[0], xp11_mst[2]) + `AXI_ASSIGN (xp11_mst_3[0], xp11_mst[3]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp11_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp11_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp11_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp11_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp11_slv_3 [0:0] (); + + `AXI_ASSIGN (xp11_slv[0], dma_sync[11]) + `AXI_ASSIGN (xp11_slv[1], xp11_slv_1[0]) + `AXI_ASSIGN (xp11_slv[2], xp11_slv_2[0]) + `AXI_ASSIGN (xp11_slv[3], xp11_slv_3[0]) + + ////////////////////////////////////////////// Row 4 /////////////////////////////////////////// + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp12_mst [NoMstPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp12_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp12_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp12_mst_2 [0:0] (); + + `AXI_ASSIGN (mem_0[12], xp12_mst[0]) + `AXI_ASSIGN (xp12_mst_1[0], xp12_mst[1]) + `AXI_ASSIGN (xp12_mst_2[0], xp12_mst[2]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp12_slv [NoSlvPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp12_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp12_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp12_slv_2 [0:0] (); + + `AXI_ASSIGN (xp12_slv[0], dma_sync[12]) + `AXI_ASSIGN (xp12_slv[1], xp12_slv_1[0]) + `AXI_ASSIGN (xp12_slv[2], xp12_slv_2[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp13_mst [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp13_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp13_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp13_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp13_mst_3 [0:0] (); + + `AXI_ASSIGN (mem_0[13], xp13_mst[0]) + `AXI_ASSIGN (xp13_mst_1[0], xp13_mst[1]) + `AXI_ASSIGN (xp13_mst_2[0], xp13_mst[2]) + `AXI_ASSIGN (xp13_mst_3[0], xp13_mst[3]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp13_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp13_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp13_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp13_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp13_slv_3 [0:0] (); + + `AXI_ASSIGN (xp13_slv[0], dma_sync[13]) + `AXI_ASSIGN (xp13_slv[1], xp13_slv_1[0]) + `AXI_ASSIGN (xp13_slv[2], xp13_slv_2[0]) + `AXI_ASSIGN (xp13_slv[3], xp13_slv_3[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp14_mst [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp14_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp14_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp14_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp14_mst_3 [0:0] (); + + `AXI_ASSIGN (mem_0[14], xp14_mst[0]) + `AXI_ASSIGN (xp14_mst_1[0], xp14_mst[1]) + `AXI_ASSIGN (xp14_mst_2[0], xp14_mst[2]) + `AXI_ASSIGN (xp14_mst_3[0], xp14_mst[3]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp14_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp14_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp14_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp14_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp14_slv_3 [0:0] (); + + `AXI_ASSIGN (xp14_slv[0], dma_sync[14]) + `AXI_ASSIGN (xp14_slv[1], xp14_slv_1[0]) + `AXI_ASSIGN (xp14_slv[2], xp14_slv_2[0]) + `AXI_ASSIGN (xp14_slv[3], xp14_slv_3[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp15_mst [NoMstPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp15_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp15_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp15_mst_2 [0:0] (); + + `AXI_ASSIGN (mem_0[15], xp15_mst[0]) + `AXI_ASSIGN (xp15_mst_1[0], xp15_mst[1]) + `AXI_ASSIGN (xp15_mst_2[0], xp15_mst[2]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp15_slv [NoSlvPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp15_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp15_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp15_slv_2 [0:0] (); + + `AXI_ASSIGN (xp15_slv[0], dma_sync[15]) + `AXI_ASSIGN (xp15_slv[1], xp15_slv_1[0]) + `AXI_ASSIGN (xp15_slv[2], xp15_slv_2[0]) + + // XP0 <--> XP1 + + `AXI_ASSIGN (xp1_slv_1[0], xp0_mst_1[0]) + `AXI_ASSIGN (xp0_slv_1[0], xp1_mst_1[0]) + + // XP0 <--> XP4 + + `AXI_ASSIGN (xp4_slv_2[0], xp0_mst_2[0]) + `AXI_ASSIGN (xp0_slv_2[0], xp4_mst_2[0]) + + // XP1 <--> XP2 + + `AXI_ASSIGN (xp2_slv_3[0], xp1_mst_3[0]) + `AXI_ASSIGN (xp1_slv_3[0], xp2_mst_3[0]) + + // XP1 <--> XP5 + + `AXI_ASSIGN (xp5_slv_2[0], xp1_mst_2[0]) + `AXI_ASSIGN (xp1_slv_2[0], xp5_mst_2[0]) + + // XP2 <--> XP3 + + `AXI_ASSIGN (xp2_slv_1[0], xp3_mst_1[0]) + `AXI_ASSIGN (xp3_slv_1[0], xp2_mst_1[0]) + + // XP2 <--> XP6 + + `AXI_ASSIGN (xp6_slv_2[0], xp2_mst_2[0]) + `AXI_ASSIGN (xp2_slv_2[0], xp6_mst_2[0]) + + // XP3 <--> XP7 + + `AXI_ASSIGN (xp7_slv_2[0], xp3_mst_2[0]) + `AXI_ASSIGN (xp3_slv_2[0], xp7_mst_2[0]) + + // XP4 <--> XP5 + + `AXI_ASSIGN (xp5_slv_1[0], xp4_mst_1[0]) + `AXI_ASSIGN (xp4_slv_1[0], xp5_mst_1[0]) + + // XP4 <--> XP8 + + `AXI_ASSIGN (xp8_slv_3[0], xp4_mst_3[0]) + `AXI_ASSIGN (xp4_slv_3[0], xp8_mst_3[0]) + + // XP5 <--> XP6 + + `AXI_ASSIGN (xp6_slv_3[0], xp5_mst_3[0]) + `AXI_ASSIGN (xp5_slv_3[0], xp6_mst_3[0]) + + // XP5 <--> XP9 + + `AXI_ASSIGN (xp9_slv_4[0], xp5_mst_4[0]) + `AXI_ASSIGN (xp5_slv_4[0], xp9_mst_4[0]) + + // XP6 <--> XP7 + + `AXI_ASSIGN (xp7_slv_1[0], xp6_mst_1[0]) + `AXI_ASSIGN (xp6_slv_1[0], xp7_mst_1[0]) + + // XP6 <--> XP10 + + `AXI_ASSIGN (xp10_slv_4[0], xp6_mst_4[0]) + `AXI_ASSIGN (xp6_slv_4[0], xp10_mst_4[0]) + + // XP7 <--> XP11 + + `AXI_ASSIGN (xp11_slv_3[0], xp7_mst_3[0]) + `AXI_ASSIGN (xp7_slv_3[0], xp11_mst_3[0]) + + // XP8 <--> XP9 + + `AXI_ASSIGN (xp9_slv_1[0], xp8_mst_1[0]) + `AXI_ASSIGN (xp8_slv_1[0], xp9_mst_1[0]) + + // XP8 <--> XP12 + + `AXI_ASSIGN (xp12_slv_2[0], xp8_mst_2[0]) + `AXI_ASSIGN (xp8_slv_2[0], xp12_mst_2[0]) + + // XP9 <--> XP10 + + `AXI_ASSIGN (xp10_slv_3[0], xp9_mst_3[0]) + `AXI_ASSIGN (xp9_slv_3[0], xp10_mst_3[0]) + + // XP9 <--> XP13 + + `AXI_ASSIGN (xp13_slv_2[0], xp9_mst_2[0]) + `AXI_ASSIGN (xp9_slv_2[0], xp13_mst_2[0]) + + // XP10 <--> XP11 + + `AXI_ASSIGN (xp11_slv_1[0], xp10_mst_1[0]) + `AXI_ASSIGN (xp10_slv_1[0], xp11_mst_1[0]) + + // XP10 <--> XP14 + + `AXI_ASSIGN (xp14_slv_2[0], xp10_mst_2[0]) + `AXI_ASSIGN (xp10_slv_2[0], xp14_mst_2[0]) + + // XP11 <--> XP15 + + `AXI_ASSIGN (xp15_slv_2[0], xp11_mst_2[0]) + `AXI_ASSIGN (xp11_slv_2[0], xp15_mst_2[0]) + + // XP12 <--> XP13 + + `AXI_ASSIGN (xp13_slv_1[0], xp12_mst_1[0]) + `AXI_ASSIGN (xp12_slv_1[0], xp13_mst_1[0]) + + // XP13 <--> XP14 + + `AXI_ASSIGN (xp14_slv_3[0], xp13_mst_3[0]) + `AXI_ASSIGN (xp13_slv_3[0], xp14_mst_3[0]) + + // XP14 <--> XP15 + + `AXI_ASSIGN (xp15_slv_1[0], xp14_mst_1[0]) + `AXI_ASSIGN (xp14_slv_1[0], xp15_mst_1[0]) + + AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) mem_dv [NoSlv-1:0] (clk); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) mem_0 [NoSlv-1:0] (); + + `AXI_ASSIGN (mem_dv[0], mem_0[0]) + `AXI_ASSIGN (mem_dv[1], mem_0[1]) + `AXI_ASSIGN (mem_dv[2], mem_0[2]) + `AXI_ASSIGN (mem_dv[3], mem_0[3]) + `AXI_ASSIGN (mem_dv[4], mem_0[4]) + `AXI_ASSIGN (mem_dv[5], mem_0[5]) + `AXI_ASSIGN (mem_dv[6], mem_0[6]) + `AXI_ASSIGN (mem_dv[7], mem_0[7]) + `AXI_ASSIGN (mem_dv[8], mem_0[8]) + `AXI_ASSIGN (mem_dv[9], mem_0[9]) + `AXI_ASSIGN (mem_dv[10], mem_0[10]) + `AXI_ASSIGN (mem_dv[11], mem_0[11]) + `AXI_ASSIGN (mem_dv[12], mem_0[12]) + `AXI_ASSIGN (mem_dv[13], mem_0[13]) + `AXI_ASSIGN (mem_dv[14], mem_0[14]) + `AXI_ASSIGN (mem_dv[15], mem_0[15]) + + //`AXI_ASSIGN (mem_dv[1], mem_1[0]) + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma1_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma2_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma3_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma4_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma5_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma6_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma7_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma8_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma9_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma10_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma11_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma12_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma13_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma14_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma15_t; + + driver_dma_t driver_dma = new(mem_dv[0]); + driver_dma1_t driver_dma1 = new(mem_dv[1]); + driver_dma2_t driver_dma2 = new(mem_dv[2]); + driver_dma3_t driver_dma3 = new(mem_dv[3]); + driver_dma4_t driver_dma4 = new(mem_dv[4]); + driver_dma5_t driver_dma5 = new(mem_dv[5]); + driver_dma6_t driver_dma6 = new(mem_dv[6]); + driver_dma7_t driver_dma7 = new(mem_dv[7]); + driver_dma8_t driver_dma8 = new(mem_dv[8]); + driver_dma9_t driver_dma9 = new(mem_dv[9]); + driver_dma10_t driver_dma10 = new(mem_dv[10]); + driver_dma11_t driver_dma11 = new(mem_dv[11]); + driver_dma12_t driver_dma12 = new(mem_dv[12]); + driver_dma13_t driver_dma13 = new(mem_dv[13]); + driver_dma14_t driver_dma14 = new(mem_dv[14]); + driver_dma15_t driver_dma15 = new(mem_dv[15]); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem0 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[0]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem1 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[1]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem2 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[2]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem3 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[3]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem4 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[4]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem5 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[5]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem6 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[6]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem7 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[7]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem8 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[8]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem9 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[9]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem10 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[10]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem11 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[11]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem12 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[12]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem13 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[13]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem14 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[14]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem15 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[15]) + ); + + // initial begin + // $readmemh("sim_mem0.mem", i_sim_mem0.mem); + // $readmemh("sim_mem1.mem", i_sim_mem1.mem); + // end + + //-------------------------------------- + // DUT AXI Memory System + //-------------------------------------- + // lfsr + logic [784:0] lfsr_dut_q, lfsr_dut_d; + + // transaction id + logic [ 7:0] transaction_id = 0; + + // Memory + block_t dma_memory [bit [AddrWidth-$clog2($bits(block_t))-1:0]]; + block_t dma_memory1 [bit [AddrWidth-$clog2($bits(block_t))-1:0]]; + + //-------------------------------------- + // DMA instantiation + //-------------------------------------- + burst_req_t burst0_req; + burst_req_t burst1_req; + logic burst0_req_valid; + logic burst1_req_valid; + logic burst0_req_ready; + logic burst1_req_ready; + logic backend_idle_0; + logic backend_idle_1; + burst_req_t burst2_req; + burst_req_t burst3_req; + logic burst2_req_valid; + logic burst3_req_valid; + logic burst2_req_ready; + logic burst3_req_ready; + logic backend_idle_2; + logic backend_idle_3; + burst_req_t burst4_req; + burst_req_t burst5_req; + logic burst4_req_valid; + logic burst5_req_valid; + logic burst4_req_ready; + logic burst5_req_ready; + logic backend_idle_4; + logic backend_idle_5; + burst_req_t burst6_req; + burst_req_t burst7_req; + logic burst6_req_valid; + logic burst7_req_valid; + logic burst6_req_ready; + logic burst7_req_ready; + logic backend_idle_6; + logic backend_idle_7; + + burst_req_t burst8_req; + burst_req_t burst9_req; + logic burst8_req_valid; + logic burst9_req_valid; + logic burst8_req_ready; + logic burst9_req_ready; + logic backend_idle_8; + logic backend_idle_9; + burst_req_t burst10_req; + burst_req_t burst11_req; + logic burst10_req_valid; + logic burst11_req_valid; + logic burst10_req_ready; + logic burst11_req_ready; + logic backend_idle_10; + logic backend_idle_11; + burst_req_t burst12_req; + burst_req_t burst13_req; + logic burst12_req_valid; + logic burst13_req_valid; + logic burst12_req_ready; + logic burst13_req_ready; + logic backend_idle_12; + logic backend_idle_13; + burst_req_t burst14_req; + burst_req_t burst15_req; + logic burst14_req_valid; + logic burst15_req_valid; + logic burst14_req_ready; + logic burst15_req_ready; + logic backend_idle_14; + logic backend_idle_15; + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_0 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[0] ), + .axi_dma_res_i ( axi_dma_res[0] ), + .burst_req_i ( burst0_req ), + .valid_i ( burst0_req_valid ), + .ready_o ( burst0_req_ready ), + .backend_idle_o ( backend_idle_0 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000000 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_0 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[0] ), + .out ( dma_sync[0] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_1 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[1] ), + .axi_dma_res_i ( axi_dma_res[1] ), + .burst_req_i ( burst1_req ), + .valid_i ( burst1_req_valid ), + .ready_o ( burst1_req_ready ), + .backend_idle_o ( backend_idle_1 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000001 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_1 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[1] ), + .out ( dma_sync[1] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_2 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[2] ), + .axi_dma_res_i ( axi_dma_res[2] ), + .burst_req_i ( burst2_req ), + .valid_i ( burst2_req_valid ), + .ready_o ( burst2_req_ready ), + .backend_idle_o ( backend_idle_2 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000002 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_2 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[2] ), + .out ( dma_sync[2] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_3 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[3] ), + .axi_dma_res_i ( axi_dma_res[3] ), + .burst_req_i ( burst3_req ), + .valid_i ( burst3_req_valid ), + .ready_o ( burst3_req_ready ), + .backend_idle_o ( backend_idle_3 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000003 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_3 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[3] ), + .out ( dma_sync[3] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_4 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[4] ), + .axi_dma_res_i ( axi_dma_res[4] ), + .burst_req_i ( burst4_req ), + .valid_i ( burst4_req_valid ), + .ready_o ( burst4_req_ready ), + .backend_idle_o ( backend_idle_4 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000004 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_4 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[4] ), + .out ( dma_sync[4] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_5 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[5] ), + .axi_dma_res_i ( axi_dma_res[5] ), + .burst_req_i ( burst5_req ), + .valid_i ( burst5_req_valid ), + .ready_o ( burst5_req_ready ), + .backend_idle_o ( backend_idle_5 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000005 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_5 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[5] ), + .out ( dma_sync[5] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_6 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[6] ), + .axi_dma_res_i ( axi_dma_res[6] ), + .burst_req_i ( burst6_req ), + .valid_i ( burst6_req_valid ), + .ready_o ( burst6_req_ready ), + .backend_idle_o ( backend_idle_6 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000006 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_6 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[6] ), + .out ( dma_sync[6] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_7 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[7] ), + .axi_dma_res_i ( axi_dma_res[7] ), + .burst_req_i ( burst7_req ), + .valid_i ( burst7_req_valid ), + .ready_o ( burst7_req_ready ), + .backend_idle_o ( backend_idle_7 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000007 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_7 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[7] ), + .out ( dma_sync[7] ) + ); + + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_8 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[8] ), + .axi_dma_res_i ( axi_dma_res[8] ), + .burst_req_i ( burst8_req ), + .valid_i ( burst8_req_valid ), + .ready_o ( burst8_req_ready ), + .backend_idle_o ( backend_idle_8 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000008 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_8 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[8] ), + .out ( dma_sync[8] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_9 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[9] ), + .axi_dma_res_i ( axi_dma_res[9] ), + .burst_req_i ( burst9_req ), + .valid_i ( burst9_req_valid ), + .ready_o ( burst9_req_ready ), + .backend_idle_o ( backend_idle_9 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000009 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_9 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[9] ), + .out ( dma_sync[9] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_10 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[10] ), + .axi_dma_res_i ( axi_dma_res[10] ), + .burst_req_i ( burst10_req ), + .valid_i ( burst10_req_valid ), + .ready_o ( burst10_req_ready ), + .backend_idle_o ( backend_idle_10 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h0000000a ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_10 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[10] ), + .out ( dma_sync[10] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_11 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[11] ), + .axi_dma_res_i ( axi_dma_res[11] ), + .burst_req_i ( burst11_req ), + .valid_i ( burst11_req_valid ), + .ready_o ( burst11_req_ready ), + .backend_idle_o ( backend_idle_11 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h0000000b ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_11 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[11] ), + .out ( dma_sync[11] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_12 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[12] ), + .axi_dma_res_i ( axi_dma_res[12] ), + .burst_req_i ( burst12_req ), + .valid_i ( burst12_req_valid ), + .ready_o ( burst12_req_ready ), + .backend_idle_o ( backend_idle_12 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h0000000c ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_12 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[12] ), + .out ( dma_sync[12] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_13 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[13] ), + .axi_dma_res_i ( axi_dma_res[13] ), + .burst_req_i ( burst13_req ), + .valid_i ( burst13_req_valid ), + .ready_o ( burst13_req_ready ), + .backend_idle_o ( backend_idle_13 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h0000000d ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_13 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[13] ), + .out ( dma_sync[13] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_14 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[14] ), + .axi_dma_res_i ( axi_dma_res[14] ), + .burst_req_i ( burst14_req ), + .valid_i ( burst14_req_valid ), + .ready_o ( burst14_req_ready ), + .backend_idle_o ( backend_idle_14 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h0000000e ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_14 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[14] ), + .out ( dma_sync[14] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_15 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[15] ), + .axi_dma_res_i ( axi_dma_res[15] ), + .burst_req_i ( burst15_req ), + .valid_i ( burst15_req_valid ), + .ready_o ( burst15_req_ready ), + .backend_idle_o ( backend_idle_15 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h0000000f ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_15 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[15] ), + .out ( dma_sync[15] ) + ); + + //----------------------------------- + // DUT + //----------------------------------- + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_0 ), + .NoSlvPorts ( xbar_cfg_0.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_0.NoMstPorts ), + .Connectivity ( Connectivity_0 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_0.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_15 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp15_slv ), + .mst_ports ( xp15_mst ), + .addr_map_i ( AddrMap_xp15 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_14 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp14_slv ), + .mst_ports ( xp14_mst ), + .addr_map_i ( AddrMap_xp14 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_13 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp13_slv ), + .mst_ports ( xp13_mst ), + .addr_map_i ( AddrMap_xp13 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_0 ), + .NoSlvPorts ( xbar_cfg_0.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_0.NoMstPorts ), + .Connectivity ( Connectivity_0 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_0.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_12 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp12_slv ), + .mst_ports ( xp12_mst ), + .addr_map_i ( AddrMap_xp12 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_11 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp11_slv ), + .mst_ports ( xp11_mst ), + .addr_map_i ( AddrMap_xp11 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_2 ), + .NoSlvPorts ( xbar_cfg_2.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_2.NoMstPorts ), + .Connectivity ( Connectivity_2 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_2.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_10 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp10_slv ), + .mst_ports ( xp10_mst ), + .addr_map_i ( AddrMap_xp10 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_2 ), + .NoSlvPorts ( xbar_cfg_2.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_2.NoMstPorts ), + .Connectivity ( Connectivity_2 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_2.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_9 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp9_slv ), + .mst_ports ( xp9_mst ), + .addr_map_i ( AddrMap_xp9 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_8 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp8_slv ), + .mst_ports ( xp8_mst ), + .addr_map_i ( AddrMap_xp8 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_7 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp7_slv ), + .mst_ports ( xp7_mst ), + .addr_map_i ( AddrMap_xp7 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_2 ), + .NoSlvPorts ( xbar_cfg_2.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_2.NoMstPorts ), + .Connectivity ( Connectivity_2 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_2.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_6 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp6_slv ), + .mst_ports ( xp6_mst ), + .addr_map_i ( AddrMap_xp6 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_2 ), + .NoSlvPorts ( xbar_cfg_2.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_2.NoMstPorts ), + .Connectivity ( Connectivity_2 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_2.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_5 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp5_slv ), + .mst_ports ( xp5_mst ), + .addr_map_i ( AddrMap_xp5 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_4 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp4_slv ), + .mst_ports ( xp4_mst ), + .addr_map_i ( AddrMap_xp4 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_0 ), + .NoSlvPorts ( xbar_cfg_0.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_0.NoMstPorts ), + .Connectivity ( Connectivity_0 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_0.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_3 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp3_slv ), + .mst_ports ( xp3_mst ), + .addr_map_i ( AddrMap_xp3 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_2 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp2_slv ), + .mst_ports ( xp2_mst ), + .addr_map_i ( AddrMap_xp2 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_1 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp1_slv ), + .mst_ports ( xp1_mst ), + .addr_map_i ( AddrMap_xp1 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_0 ), + .NoSlvPorts ( xbar_cfg_0.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_0.NoMstPorts ), + .Connectivity ( Connectivity_0 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_0.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_0 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp0_slv ), + .mst_ports ( xp0_mst ), + .addr_map_i ( AddrMap_xp0 ) + ); + + //-------------------------------------- + // DMA DUT tasks + //-------------------------------------- + + task oned_dut_launch_15 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst15_req_valid <= 1'b0; + burst15_req <= '0; + @(posedge clk); + while (burst15_req_ready !== 1) @(posedge clk); + // write data + burst15_req.id <= transf_id_i; + burst15_req.src <= src_addr_i; + burst15_req.dst <= dst_addr_i; + burst15_req.num_bytes <= num_bytes_i; + burst15_req.cache_src <= src_cache_i; + burst15_req.cache_dst <= dst_cache_i; + burst15_req.burst_src <= src_burst_i; + burst15_req.burst_dst <= dst_burst_i; + burst15_req.decouple_rw <= decouple_rw_i; + burst15_req.deburst <= deburst_i; + burst15_req.serialize <= serialize_i; + burst15_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst15_req_valid <= 1'b0; + burst15_req <= '0; + endtask + + task oned_dut_launch_14 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst14_req_valid <= 1'b0; + burst14_req <= '0; + @(posedge clk); + while (burst14_req_ready !== 1) @(posedge clk); + // write data + burst14_req.id <= transf_id_i; + burst14_req.src <= src_addr_i; + burst14_req.dst <= dst_addr_i; + burst14_req.num_bytes <= num_bytes_i; + burst14_req.cache_src <= src_cache_i; + burst14_req.cache_dst <= dst_cache_i; + burst14_req.burst_src <= src_burst_i; + burst14_req.burst_dst <= dst_burst_i; + burst14_req.decouple_rw <= decouple_rw_i; + burst14_req.deburst <= deburst_i; + burst14_req.serialize <= serialize_i; + burst14_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst14_req_valid <= 1'b0; + burst14_req <= '0; + endtask + + task oned_dut_launch_13 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst13_req_valid <= 1'b0; + burst13_req <= '0; + @(posedge clk); + while (burst13_req_ready !== 1) @(posedge clk); + // write data + burst13_req.id <= transf_id_i; + burst13_req.src <= src_addr_i; + burst13_req.dst <= dst_addr_i; + burst13_req.num_bytes <= num_bytes_i; + burst13_req.cache_src <= src_cache_i; + burst13_req.cache_dst <= dst_cache_i; + burst13_req.burst_src <= src_burst_i; + burst13_req.burst_dst <= dst_burst_i; + burst13_req.decouple_rw <= decouple_rw_i; + burst13_req.deburst <= deburst_i; + burst13_req.serialize <= serialize_i; + burst13_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst13_req_valid <= 1'b0; + burst13_req <= '0; + endtask + + task oned_dut_launch_12 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst12_req_valid <= 1'b0; + burst12_req <= '0; + @(posedge clk); + while (burst12_req_ready !== 1) @(posedge clk); + // write data + burst12_req.id <= transf_id_i; + burst12_req.src <= src_addr_i; + burst12_req.dst <= dst_addr_i; + burst12_req.num_bytes <= num_bytes_i; + burst12_req.cache_src <= src_cache_i; + burst12_req.cache_dst <= dst_cache_i; + burst12_req.burst_src <= src_burst_i; + burst12_req.burst_dst <= dst_burst_i; + burst12_req.decouple_rw <= decouple_rw_i; + burst12_req.deburst <= deburst_i; + burst12_req.serialize <= serialize_i; + burst12_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst12_req_valid <= 1'b0; + burst12_req <= '0; + endtask + + task oned_dut_launch_11 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst11_req_valid <= 1'b0; + burst11_req <= '0; + @(posedge clk); + while (burst11_req_ready !== 1) @(posedge clk); + // write data + burst11_req.id <= transf_id_i; + burst11_req.src <= src_addr_i; + burst11_req.dst <= dst_addr_i; + burst11_req.num_bytes <= num_bytes_i; + burst11_req.cache_src <= src_cache_i; + burst11_req.cache_dst <= dst_cache_i; + burst11_req.burst_src <= src_burst_i; + burst11_req.burst_dst <= dst_burst_i; + burst11_req.decouple_rw <= decouple_rw_i; + burst11_req.deburst <= deburst_i; + burst11_req.serialize <= serialize_i; + burst11_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst11_req_valid <= 1'b0; + burst11_req <= '0; + endtask + + task oned_dut_launch_10 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst10_req_valid <= 1'b0; + burst10_req <= '0; + @(posedge clk); + while (burst10_req_ready !== 1) @(posedge clk); + // write data + burst10_req.id <= transf_id_i; + burst10_req.src <= src_addr_i; + burst10_req.dst <= dst_addr_i; + burst10_req.num_bytes <= num_bytes_i; + burst10_req.cache_src <= src_cache_i; + burst10_req.cache_dst <= dst_cache_i; + burst10_req.burst_src <= src_burst_i; + burst10_req.burst_dst <= dst_burst_i; + burst10_req.decouple_rw <= decouple_rw_i; + burst10_req.deburst <= deburst_i; + burst10_req.serialize <= serialize_i; + burst10_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst10_req_valid <= 1'b0; + burst10_req <= '0; + endtask + + task oned_dut_launch_9 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst9_req_valid <= 1'b0; + burst9_req <= '0; + @(posedge clk); + while (burst9_req_ready !== 1) @(posedge clk); + // write data + burst9_req.id <= transf_id_i; + burst9_req.src <= src_addr_i; + burst9_req.dst <= dst_addr_i; + burst9_req.num_bytes <= num_bytes_i; + burst9_req.cache_src <= src_cache_i; + burst9_req.cache_dst <= dst_cache_i; + burst9_req.burst_src <= src_burst_i; + burst9_req.burst_dst <= dst_burst_i; + burst9_req.decouple_rw <= decouple_rw_i; + burst9_req.deburst <= deburst_i; + burst9_req.serialize <= serialize_i; + burst9_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst9_req_valid <= 1'b0; + burst9_req <= '0; + endtask + + task oned_dut_launch_8 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst8_req_valid <= 1'b0; + burst8_req <= '0; + @(posedge clk); + while (burst8_req_ready !== 1) @(posedge clk); + // write data + burst8_req.id <= transf_id_i; + burst8_req.src <= src_addr_i; + burst8_req.dst <= dst_addr_i; + burst8_req.num_bytes <= num_bytes_i; + burst8_req.cache_src <= src_cache_i; + burst8_req.cache_dst <= dst_cache_i; + burst8_req.burst_src <= src_burst_i; + burst8_req.burst_dst <= dst_burst_i; + burst8_req.decouple_rw <= decouple_rw_i; + burst8_req.deburst <= deburst_i; + burst8_req.serialize <= serialize_i; + burst8_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst8_req_valid <= 1'b0; + burst8_req <= '0; + endtask + + task oned_dut_launch_7 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst7_req_valid <= 1'b0; + burst7_req <= '0; + @(posedge clk); + while (burst7_req_ready !== 1) @(posedge clk); + // write data + burst7_req.id <= transf_id_i; + burst7_req.src <= src_addr_i; + burst7_req.dst <= dst_addr_i; + burst7_req.num_bytes <= num_bytes_i; + burst7_req.cache_src <= src_cache_i; + burst7_req.cache_dst <= dst_cache_i; + burst7_req.burst_src <= src_burst_i; + burst7_req.burst_dst <= dst_burst_i; + burst7_req.decouple_rw <= decouple_rw_i; + burst7_req.deburst <= deburst_i; + burst7_req.serialize <= serialize_i; + burst7_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst7_req_valid <= 1'b0; + burst7_req <= '0; + endtask + + task oned_dut_launch_6 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst6_req_valid <= 1'b0; + burst6_req <= '0; + @(posedge clk); + while (burst6_req_ready !== 1) @(posedge clk); + // write data + burst6_req.id <= transf_id_i; + burst6_req.src <= src_addr_i; + burst6_req.dst <= dst_addr_i; + burst6_req.num_bytes <= num_bytes_i; + burst6_req.cache_src <= src_cache_i; + burst6_req.cache_dst <= dst_cache_i; + burst6_req.burst_src <= src_burst_i; + burst6_req.burst_dst <= dst_burst_i; + burst6_req.decouple_rw <= decouple_rw_i; + burst6_req.deburst <= deburst_i; + burst6_req.serialize <= serialize_i; + burst6_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst6_req_valid <= 1'b0; + burst6_req <= '0; + endtask + + task oned_dut_launch_5 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst5_req_valid <= 1'b0; + burst5_req <= '0; + @(posedge clk); + while (burst5_req_ready !== 1) @(posedge clk); + // write data + burst5_req.id <= transf_id_i; + burst5_req.src <= src_addr_i; + burst5_req.dst <= dst_addr_i; + burst5_req.num_bytes <= num_bytes_i; + burst5_req.cache_src <= src_cache_i; + burst5_req.cache_dst <= dst_cache_i; + burst5_req.burst_src <= src_burst_i; + burst5_req.burst_dst <= dst_burst_i; + burst5_req.decouple_rw <= decouple_rw_i; + burst5_req.deburst <= deburst_i; + burst5_req.serialize <= serialize_i; + burst5_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst5_req_valid <= 1'b0; + burst5_req <= '0; + endtask + + task oned_dut_launch_4 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst4_req_valid <= 1'b0; + burst4_req <= '0; + @(posedge clk); + while (burst4_req_ready !== 1) @(posedge clk); + // write data + burst4_req.id <= transf_id_i; + burst4_req.src <= src_addr_i; + burst4_req.dst <= dst_addr_i; + burst4_req.num_bytes <= num_bytes_i; + burst4_req.cache_src <= src_cache_i; + burst4_req.cache_dst <= dst_cache_i; + burst4_req.burst_src <= src_burst_i; + burst4_req.burst_dst <= dst_burst_i; + burst4_req.decouple_rw <= decouple_rw_i; + burst4_req.deburst <= deburst_i; + burst4_req.serialize <= serialize_i; + burst4_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst4_req_valid <= 1'b0; + burst4_req <= '0; + endtask + + task oned_dut_launch_3 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst3_req_valid <= 1'b0; + burst3_req <= '0; + @(posedge clk); + while (burst3_req_ready !== 1) @(posedge clk); + // write data + burst3_req.id <= transf_id_i; + burst3_req.src <= src_addr_i; + burst3_req.dst <= dst_addr_i; + burst3_req.num_bytes <= num_bytes_i; + burst3_req.cache_src <= src_cache_i; + burst3_req.cache_dst <= dst_cache_i; + burst3_req.burst_src <= src_burst_i; + burst3_req.burst_dst <= dst_burst_i; + burst3_req.decouple_rw <= decouple_rw_i; + burst3_req.deburst <= deburst_i; + burst3_req.serialize <= serialize_i; + burst3_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst3_req_valid <= 1'b0; + burst3_req <= '0; + endtask + + task oned_dut_launch_2 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst2_req_valid <= 1'b0; + burst2_req <= '0; + @(posedge clk); + while (burst2_req_ready !== 1) @(posedge clk); + // write data + burst2_req.id <= transf_id_i; + burst2_req.src <= src_addr_i; + burst2_req.dst <= dst_addr_i; + burst2_req.num_bytes <= num_bytes_i; + burst2_req.cache_src <= src_cache_i; + burst2_req.cache_dst <= dst_cache_i; + burst2_req.burst_src <= src_burst_i; + burst2_req.burst_dst <= dst_burst_i; + burst2_req.decouple_rw <= decouple_rw_i; + burst2_req.deburst <= deburst_i; + burst2_req.serialize <= serialize_i; + burst2_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst2_req_valid <= 1'b0; + burst2_req <= '0; + endtask + + task oned_dut_launch_1 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst1_req_valid <= 1'b0; + burst1_req <= '0; + @(posedge clk); + while (burst1_req_ready !== 1) @(posedge clk); + // write data + burst1_req.id <= transf_id_i; + burst1_req.src <= src_addr_i; + burst1_req.dst <= dst_addr_i; + burst1_req.num_bytes <= num_bytes_i; + burst1_req.cache_src <= src_cache_i; + burst1_req.cache_dst <= dst_cache_i; + burst1_req.burst_src <= src_burst_i; + burst1_req.burst_dst <= dst_burst_i; + burst1_req.decouple_rw <= decouple_rw_i; + burst1_req.deburst <= deburst_i; + burst1_req.serialize <= serialize_i; + burst1_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst1_req_valid <= 1'b0; + burst1_req <= '0; + endtask + + task oned_dut_launch_0 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst0_req_valid <= 1'b0; + burst0_req <= '0; + @(posedge clk); + while (burst0_req_ready !== 1) @(posedge clk); + // write data + burst0_req.id <= transf_id_i; + burst0_req.src <= src_addr_i; + burst0_req.dst <= dst_addr_i; + burst0_req.num_bytes <= num_bytes_i; + burst0_req.cache_src <= src_cache_i; + burst0_req.cache_dst <= dst_cache_i; + burst0_req.burst_src <= src_burst_i; + burst0_req.burst_dst <= dst_burst_i; + burst0_req.decouple_rw <= decouple_rw_i; + burst0_req.deburst <= deburst_i; + burst0_req.serialize <= serialize_i; + burst0_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst0_req_valid <= 1'b0; + burst0_req <= '0; + endtask + + task oned_reset (); + burst0_req_valid <= 1'b0; + burst0_req <= '0; + burst1_req_valid <= 1'b0; + burst1_req <= '0; + burst2_req_valid <= 1'b0; + burst2_req <= '0; + burst3_req_valid <= 1'b0; + burst3_req <= '0; + burst4_req_valid <= 1'b0; + burst4_req <= '0; + burst5_req_valid <= 1'b0; + burst5_req <= '0; + burst6_req_valid <= 1'b0; + burst6_req <= '0; + burst7_req_valid <= 1'b0; + burst7_req <= '0; + burst8_req_valid <= 1'b0; + burst8_req <= '0; + burst9_req_valid <= 1'b0; + burst9_req <= '0; + burst10_req_valid <= 1'b0; + burst10_req <= '0; + burst11_req_valid <= 1'b0; + burst11_req <= '0; + burst12_req_valid <= 1'b0; + burst12_req <= '0; + burst13_req_valid <= 1'b0; + burst13_req <= '0; + burst14_req_valid <= 1'b0; + burst14_req <= '0; + burst15_req_valid <= 1'b0; + burst15_req <= '0; + endtask + + task wait_for_dut_completion (); + repeat(10) @(posedge clk); + while (backend_idle_0 === 0) @(posedge clk); + while (backend_idle_1 === 0) @(posedge clk); + while (backend_idle_2 === 0) @(posedge clk); + while (backend_idle_3 === 0) @(posedge clk); + while (backend_idle_4 === 0) @(posedge clk); + while (backend_idle_5 === 0) @(posedge clk); + while (backend_idle_6 === 0) @(posedge clk); + while (backend_idle_7 === 0) @(posedge clk); + while (backend_idle_8 === 0) @(posedge clk); + while (backend_idle_9 === 0) @(posedge clk); + while (backend_idle_10 === 0) @(posedge clk); + while (backend_idle_11 === 0) @(posedge clk); + while (backend_idle_12 === 0) @(posedge clk); + while (backend_idle_13 === 0) @(posedge clk); + while (backend_idle_14 === 0) @(posedge clk); + while (backend_idle_15 === 0) @(posedge clk); + repeat(50) @(posedge clk); + endtask + + task clear_dut_memory (); + dma_memory.delete(); + dma_memory1.delete(); + endtask + + task reset_dut_lfsr (); + lfsr_dut_q <= 'hc0a232c162b2bab5b960668030f4efce27940bd0de965f0b8d4315f15b79704195e4e0a6b495fc269f65ae17e10e9ca98510fc143327a292b418597f9dd175fc91c3d61be287d5462a23e00fa7ae906ae9eb339ab5225021356138cd46b6e5a73540c5591116b6b5e08d2c0e54eaf0d5143b33b2186b6cf841c076a98c412a63981f0e323dce93481ed1c37e4f1d7553b6c2fba1a3af6c3ad88b15ad58812ba07d1753917ac4e6ab1e8c4f67a47b4b0f48a34f42a52c546e979f4e4968e80a732a0a5e7a51146cf08482f349f94336752b765c0b1d70803d883d5058d127264335213da4163c62f65a4e65501b90fa5f177675c0747cfca328e131bfb3f7bcc5c27680c7bf86491f4ed3d36c25531edfa74b1e32fafe426958ae356eb8ef0fd818eaca4227a667b7c934ebfa282ab6bfc6db89b927c91a41e63a9554dced774f30268d0725a1a565368703b9f81d5c027ba196ef8b803a51c639c7ead834e1d6bc537d33800fe5eb12f1ed67758f1dfe85ffdbae56e8ef27f2ecedcee75b8dbb5f5f1a629ba3b755; + endtask + + //-------------------------------------- + // Osmium Model + //-------------------------------------- + // Memory + block_t osmium_memory [bit [AddrWidth-$clog2($bits(block_t))-1:0]]; + // lfsr + logic [784:0] lfsr_osmium_q,lfsr_osmium_d; + + task oned_osmium_launch ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i + ); + logic [AddrWidth-1:0] read_addr, write_addr; + logic [AddrWidth-1:0] read_word, write_word; + logic [$clog2(AddrWidth):0] read_offset, write_offset; + // perform the transfer + for(int i = 0; i < num_bytes_i; i = i + 1) begin + read_addr = src_addr_i + i; + write_addr = dst_addr_i + i; + read_word = src_burst_i == 2'b00 ? src_addr_i >> $clog2(AddrWidth) : read_addr >> $clog2(AddrWidth); + write_word = dst_burst_i == 2'b00 ? dst_addr_i >> $clog2(AddrWidth) : write_addr >> $clog2(AddrWidth); + read_offset = read_addr [$clog2(AddrWidth)-1:0]; + write_offset = write_addr[$clog2(AddrWidth)-1:0]; + + // do the read + if (!osmium_memory.exists(read_word) === 1) begin + osmium_memory[read_word].data = lfsr_osmium_q[784:273]; + //shift 513x + repeat(513) begin + // next state + for (int i = 1; i < 785; i = i +1) lfsr_osmium_d[i-1] = lfsr_osmium_q[i]; + lfsr_osmium_d[784] = lfsr_osmium_q[0]; + lfsr_osmium_d[692] = lfsr_osmium_q[0] ^ lfsr_osmium_q[693]; + lfsr_osmium_q = lfsr_osmium_d; + end + end + // do the write + osmium_memory[write_word].bytes[write_offset] = osmium_memory[read_word].bytes[read_offset]; + // $display("W: %d - %d R: %d - %d", write_word, write_offset, read_word, read_offset); + end + + endtask + + task clear_osmium_memory (); + osmium_memory.delete(); + endtask + + task reset_osmium_lfsr (); + lfsr_osmium_q = 'hc0a232c162b2bab5b960668030f4efce27940bd0de965f0b8d4315f15b79704195e4e0a6b495fc269f65ae17e10e9ca98510fc143327a292b418597f9dd175fc91c3d61be287d5462a23e00fa7ae906ae9eb339ab5225021356138cd46b6e5a73540c5591116b6b5e08d2c0e54eaf0d5143b33b2186b6cf841c076a98c412a63981f0e323dce93481ed1c37e4f1d7553b6c2fba1a3af6c3ad88b15ad58812ba07d1753917ac4e6ab1e8c4f67a47b4b0f48a34f42a52c546e979f4e4968e80a732a0a5e7a51146cf08482f349f94336752b765c0b1d70803d883d5058d127264335213da4163c62f65a4e65501b90fa5f177675c0747cfca328e131bfb3f7bcc5c27680c7bf86491f4ed3d36c25531edfa74b1e32fafe426958ae356eb8ef0fd818eaca4227a667b7c934ebfa282ab6bfc6db89b927c91a41e63a9554dced774f30268d0725a1a565368703b9f81d5c027ba196ef8b803a51c639c7ead834e1d6bc537d33800fe5eb12f1ed67758f1dfe85ffdbae56e8ef27f2ecedcee75b8dbb5f5f1a629ba3b755; + endtask + + //-------------------------------------- + // Compare Memory content + //-------------------------------------- + task compare_memories (); + + // go through osmium memory and compare contents + foreach(osmium_memory[i]) begin + if (osmium_memory[i] !== dma_memory[i]) $fatal("Memory mismatch @ %x\nexpect: %x\ngot :%x\n", i << $clog2(AddrWidth), osmium_memory[i], dma_memory[i]); + end + // go through dma memory and compare contents + foreach(dma_memory[i]) begin + if (osmium_memory[i] !== dma_memory[i]) $fatal("Memory mismatch @ %x\nexpect: %x\ngot :%x\n", i << $clog2(AddrWidth), osmium_memory[i], dma_memory[i]); + end + + // it worked :P + $display(" - :D"); + + endtask + + //-------------------------------------- + // Master tasks + //-------------------------------------- + + task clear_memory (); + clear_dut_memory(); + clear_osmium_memory(); + endtask + + task reset_lfsr (); + reset_dut_lfsr(); + reset_osmium_lfsr(); + endtask + + task oned_launch_15 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma15_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_15(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_14 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma14_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_14(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_13 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma13_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_13(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_12 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma12_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_12(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_11 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma11_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_11(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_10 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma10_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_10(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_9 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma9_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_9(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_8 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma8_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_8(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_7 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma7_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_7(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_6 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma6_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_6(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_5 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma5_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_5(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_4 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma4_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_4(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_3 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma3_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_3(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_2 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma2_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_2(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_1 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma1_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_1(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_0 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma0_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_0(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task reset (); + int my_file; + oned_reset(); + wait_for_reset(); + // clear trace file + my_file = $fopen("dma_transfers.txt", "w"); + $fwrite(my_file, "Transfers launched:\n"); + $fclose(my_file); + endtask + + task oned_random_launch( + input logic [15:0] max_len, + input logic [31:0] src_add, + input logic [31:0] dst_add, + input logic [15:0] master_id, + input logic [15:0] size, + input logic wait_for_completion + ); + + logic [ IdWidth-1:0] transf_id_0; + logic [ AddrWidth-1:0] src_addr_0, dst_addr_0, num_bytes_0; + logic [ IdWidth-1:0] transf_id_1; + logic [ AddrWidth-1:0] src_addr_1, dst_addr_1, num_bytes_1; + logic [ IdWidth-1:0] transf_id_2; + logic [ AddrWidth-1:0] src_addr_2, dst_addr_2, num_bytes_2; + logic [ IdWidth-1:0] transf_id_3; + logic [ AddrWidth-1:0] src_addr_3, dst_addr_3, num_bytes_3; + logic [ IdWidth-1:0] transf_id_4; + logic [ AddrWidth-1:0] src_addr_4, dst_addr_4, num_bytes_4; + logic [ IdWidth-1:0] transf_id_5; + logic [ AddrWidth-1:0] src_addr_5, dst_addr_5, num_bytes_5; + logic [ IdWidth-1:0] transf_id_6; + logic [ AddrWidth-1:0] src_addr_6, dst_addr_6, num_bytes_6; + logic [ IdWidth-1:0] transf_id_7; + logic [ AddrWidth-1:0] src_addr_7, dst_addr_7, num_bytes_7; + logic [ IdWidth-1:0] transf_id_8; + logic [ AddrWidth-1:0] src_addr_8, dst_addr_8, num_bytes_8; + logic [ IdWidth-1:0] transf_id_9; + logic [ AddrWidth-1:0] src_addr_9, dst_addr_9, num_bytes_9; + logic [ IdWidth-1:0] transf_id_10; + logic [ AddrWidth-1:0] src_addr_10, dst_addr_10, num_bytes_10; + logic [ IdWidth-1:0] transf_id_11; + logic [ AddrWidth-1:0] src_addr_11, dst_addr_11, num_bytes_11; + logic [ IdWidth-1:0] transf_id_12; + logic [ AddrWidth-1:0] src_addr_12, dst_addr_12, num_bytes_12; + logic [ IdWidth-1:0] transf_id_13; + logic [ AddrWidth-1:0] src_addr_13, dst_addr_13, num_bytes_13; + logic [ IdWidth-1:0] transf_id_14; + logic [ AddrWidth-1:0] src_addr_14, dst_addr_14, num_bytes_14; + logic [ IdWidth-1:0] transf_id_15; + logic [ AddrWidth-1:0] src_addr_15, dst_addr_15, num_bytes_15; + logic decouple_rw; + logic deburst; + logic serialize; + + decouple_rw = 0;//$urandom(); + deburst = 0;//$urandom(); + serialize = 0;//$urandom(); + + if (master_id == 0) begin + transf_id_0 = 0;//$urandom(); + // transf_id = transaction_id; + //src_addr_0[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //src_addr_0[(AddrWidth/2)-1: 0] = $urandom(); + //dst_addr_0[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //dst_addr_0[(AddrWidth/2)-1: 0] = $urandom(); + num_bytes_0 = 0; + num_bytes_0[15: 0] = size; + src_addr_0 = src_add; + dst_addr_0 = dst_add; + + oned_launch_0(transf_id_0, src_addr_0, dst_addr_0, num_bytes_0, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 1) begin + transf_id_1 = 1;//$urandom(); + // transf_id = transaction_id; + //src_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //src_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + //dst_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //dst_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + num_bytes_1 = 0; + num_bytes_1[15: 0] = size; + src_addr_1 = src_add; + dst_addr_1 = dst_add; + + oned_launch_1(transf_id_1, src_addr_1, dst_addr_1, num_bytes_1, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 2) begin + transf_id_2 = 2;//$urandom(); + // transf_id = transaction_id; + //src_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //src_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + //dst_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //dst_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + num_bytes_2 = 0; + num_bytes_2[15: 0] = size; + src_addr_2 = src_add; + dst_addr_2 = dst_add; + + oned_launch_2(transf_id_2, src_addr_2, dst_addr_2, num_bytes_2, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 3) begin + transf_id_3 = 3;//$urandom(); + // transf_id = transaction_id; + //src_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //src_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + //dst_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //dst_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + num_bytes_3 = 0; + num_bytes_3[15: 0] = size; + src_addr_3 = src_add; + dst_addr_3 = dst_add; + + oned_launch_3(transf_id_3, src_addr_3, dst_addr_3, num_bytes_3, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 4) begin + transf_id_4 = 4;//$urandom(); + // transf_id = transaction_id; + //src_addr_0[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //src_addr_0[(AddrWidth/2)-1: 0] = $urandom(); + //dst_addr_0[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //dst_addr_0[(AddrWidth/2)-1: 0] = $urandom(); + num_bytes_4 = 0; + num_bytes_4[15: 0] = size; + src_addr_4 = src_add; + dst_addr_4 = dst_add; + + oned_launch_4(transf_id_4, src_addr_4, dst_addr_4, num_bytes_4, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 5) begin + transf_id_5 = 5;//$urandom(); + // transf_id = transaction_id; + //src_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //src_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + //dst_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //dst_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + num_bytes_5 = 0; + num_bytes_5[15: 0] = size; + src_addr_5 = src_add; + dst_addr_5 = dst_add; + + oned_launch_5(transf_id_5, src_addr_5, dst_addr_5, num_bytes_5, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 6) begin + transf_id_6 = 6;//$urandom(); + // transf_id = transaction_id; + //src_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //src_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + //dst_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //dst_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + num_bytes_6 = 0; + num_bytes_6[15: 0] = size; + src_addr_6 = src_add; + dst_addr_6 = dst_add; + + oned_launch_6(transf_id_6, src_addr_6, dst_addr_6, num_bytes_6, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 7) begin + transf_id_7 = 7;//$urandom(); + // transf_id = transaction_id; + //src_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //src_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + //dst_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //dst_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + num_bytes_7 = 0; + num_bytes_7[15: 0] = size; + src_addr_7 = src_add; + dst_addr_7 = dst_add; + + oned_launch_7(transf_id_7, src_addr_7, dst_addr_7, num_bytes_7, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 8) begin + transf_id_8 = 8;//$urandom(); + // transf_id = transaction_id; + //src_addr_0[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //src_addr_0[(AddrWidth/2)-1: 0] = $urandom(); + //dst_addr_0[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //dst_addr_0[(AddrWidth/2)-1: 0] = $urandom(); + num_bytes_8 = 0; + num_bytes_8[15: 0] = size; + src_addr_8 = src_add; + dst_addr_8 = dst_add; + + oned_launch_8(transf_id_8, src_addr_8, dst_addr_8, num_bytes_8, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 9) begin + transf_id_9 = 9;//$urandom(); + // transf_id = transaction_id; + //src_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //src_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + //dst_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //dst_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + num_bytes_9 = 0; + num_bytes_9[15: 0] = size; + src_addr_9 = src_add; + dst_addr_9 = dst_add; + + oned_launch_9(transf_id_9, src_addr_9, dst_addr_9, num_bytes_9, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 10) begin + transf_id_10 = 10;//$urandom(); + // transf_id = transaction_id; + //src_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //src_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + //dst_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //dst_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + num_bytes_10 = 0; + num_bytes_10[15: 0] = size; + src_addr_10 = src_add; + dst_addr_10 = dst_add; + + oned_launch_10(transf_id_10, src_addr_10, dst_addr_10, num_bytes_10, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 11) begin + transf_id_11 = 11;//$urandom(); + // transf_id = transaction_id; + //src_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //src_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + //dst_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //dst_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + num_bytes_11 = 0; + num_bytes_11[15: 0] = size; + src_addr_11 = src_add; + dst_addr_11 = dst_add; + + oned_launch_11(transf_id_11, src_addr_11, dst_addr_11, num_bytes_11, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 12) begin + transf_id_12 = 12;//$urandom(); + // transf_id = transaction_id; + //src_addr_0[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //src_addr_0[(AddrWidth/2)-1: 0] = $urandom(); + //dst_addr_0[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //dst_addr_0[(AddrWidth/2)-1: 0] = $urandom(); + num_bytes_12 = 0; + num_bytes_12[15: 0] = size; + src_addr_12 = src_add; + dst_addr_12 = dst_add; + + oned_launch_12(transf_id_12, src_addr_12, dst_addr_12, num_bytes_12, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 13) begin + transf_id_13 = 13;//$urandom(); + // transf_id = transaction_id; + //src_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //src_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + //dst_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //dst_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + num_bytes_13 = 0; + num_bytes_13[15: 0] = size; + src_addr_13 = src_add; + dst_addr_13 = dst_add; + + oned_launch_13(transf_id_13, src_addr_13, dst_addr_13, num_bytes_13, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 14) begin + transf_id_14 = 14;//$urandom(); + // transf_id = transaction_id; + //src_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //src_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + //dst_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //dst_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + num_bytes_14 = 0; + num_bytes_14[15: 0] = size; + src_addr_14 = src_add; + dst_addr_14 = dst_add; + + oned_launch_14(transf_id_14, src_addr_14, dst_addr_14, num_bytes_14, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 15) begin + transf_id_15 = 15;//$urandom(); + // transf_id = transaction_id; + //src_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //src_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + //dst_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //dst_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + num_bytes_15 = 0; + num_bytes_15[15: 0] = size; + src_addr_15 = src_add; + dst_addr_15 = dst_add; + + oned_launch_15(transf_id_15, src_addr_15, dst_addr_15, num_bytes_15, decouple_rw, deburst, serialize, wait_for_completion); + + end + + // transaction_id = transaction_id + 1; + + + endtask + +endmodule : fixture_axi_dma_backend diff --git a/test/fixture_axi_dma_backend_1xp.sv b/test/fixture_axi_dma_backend_1xp.sv new file mode 100644 index 000000000..b6d001d3d --- /dev/null +++ b/test/fixture_axi_dma_backend_1xp.sv @@ -0,0 +1,777 @@ +// Copyright (c) 2019 ETH Zurich, University of Bologna +// All rights reserved. +// +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// +// Thomas Benz + +// fixture for the AXi DMA backend +// the fixture instantiates the DMA backend, a golden model of the backend , and tasks controlling +// both. + +`timescale 1ns/1ns +module fixture_axi_dma_backend(); + + // `include "../axi/include/axi/assign.svh" + `define MEM_DEBUG 1 + `include "axi/assign.svh" + `include "axi/typedef.svh" + + //-------------------------------------- + // Parameters + //-------------------------------------- + localparam TA = 0.2ns; // must be nonzero to avoid Snitch load fifo double pop glitch + localparam TT = 0.8ns; + localparam HalfPeriod = 50ns; + localparam Reset = 75ns; + + localparam DataWidth = 512; + localparam AddrWidth = 64; + localparam StrbWidth = DataWidth / 8; + localparam IdWidth = 6; + localparam UserWidth = 1; + + // DUT parameters + localparam bit ATOPs = 0; + localparam int unsigned NoSlvPorts = 2; + localparam int unsigned NoMstPorts = 1; + localparam bit [NoSlvPorts-1:0][NoMstPorts-1:0] Connectivity = '1; + localparam int unsigned AxiSlvPortMaxUniqIds = 32'd16; + localparam int unsigned AxiSlvPortMaxTxnsPerId = 32'd128; + localparam int unsigned AxiSlvPortMaxTxns = 32'd31; + localparam int unsigned AxiMstPortMaxUniqIds = 32'd4; + localparam int unsigned AxiMstPortMaxTxnsPerId = 32'd7; + localparam int unsigned NoAddrRules = 32'd2; + + typedef axi_pkg::xbar_rule_64_t rule_t; // Has to be the same width as axi addr + + // axi configuration + localparam int unsigned AxiIdWidthMasters = IdWidth; + localparam int unsigned AxiIdUsed = IdWidth-1; // Has to be <= AxiIdWidthMasters + localparam int unsigned AxiIdWidthSlaves = AxiIdWidthMasters + $clog2(NoMstPorts); + localparam int unsigned AxiAddrWidth = AddrWidth; // Axi Address Width + localparam int unsigned AxiDataWidth = DataWidth; // Axi Data Width + localparam int unsigned AxiStrbWidth = StrbWidth; + localparam int unsigned AxiUserWidth = UserWidth; + localparam int unsigned AxiIdWidth = IdWidth; + // in the bench can change this variables which are set here freely + localparam axi_pkg::xbar_cfg_t xbar_cfg = '{ + NoSlvPorts: NoMstPorts, + NoMstPorts: NoSlvPorts, + MaxMstTrans: AxiSlvPortMaxTxns, + MaxSlvTrans: AxiSlvPortMaxTxnsPerId, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_AX, + AxiIdWidthSlvPorts: AxiIdWidthMasters, + AxiIdUsedSlvPorts: AxiIdUsed, + UniqueIds: 1'b0, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: NoAddrRules + }; + + localparam rule_t [xbar_cfg.NoAddrRules-1:0] AddrMap = '{ + '{idx: 32'd1 % NoSlvPorts, start_addr: {1'b0, {(AddrWidth-1){1'b1}}}, end_addr: {(AddrWidth){1'b1}}}, + '{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {1'b0, {(AddrWidth-1){1'b1}}}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + typedef union packed { + logic [StrbWidth-1:0][7:0] bytes; + logic [DataWidth-1:0] data; + } block_t; + + /// Address Type + typedef logic [ AddrWidth-1:0] addr_t; + /// Data Type + typedef logic [ DataWidth-1:0] data_t; + /// Strobe Type + typedef logic [ StrbWidth-1:0] strb_t; + /// AXI ID Type + typedef logic [ IdWidth-1:0] axi_id_t; + /// AXI USER Type + typedef logic [ UserWidth-1:0] user_t; + /// 1D burst request + typedef struct packed { + axi_id_t id; + addr_t src, dst, num_bytes; + axi_pkg::cache_t cache_src, cache_dst; + axi_pkg::burst_t burst_src, burst_dst; + logic decouple_rw; + logic deburst; + logic serialize; + } burst_req_t; + + // master AXI bus --> DMA + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_dma_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_dma_t, axi_id_t, user_t) + + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_dma_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_dma_t, data_t, axi_id_t, user_t) + + `AXI_TYPEDEF_REQ_T(dma_req_t, aw_chan_dma_t, w_chan_t, ar_chan_dma_t) + `AXI_TYPEDEF_RESP_T(dma_resp_t, b_chan_dma_t, r_chan_dma_t) + + // slave AXI bus --> mem + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_mem_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_mem_t, axi_id_t, user_t) + + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_mem_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_mem_t, data_t, axi_id_t, user_t) + + `AXI_TYPEDEF_REQ_T(mem_req_t, aw_chan_mem_t, w_chan_t, ar_chan_mem_t) + `AXI_TYPEDEF_RESP_T(mem_resp_t, b_chan_mem_t, r_chan_mem_t) + + //-------------------------------------- + // Clock and Reset + //-------------------------------------- + logic clk; + initial begin + forever begin + clk = 0; + #HalfPeriod; + clk = 1; + #HalfPeriod; + end + end + + logic rst_n; + initial begin + rst_n = 0; + #Reset; + rst_n = 1; + end + + task wait_for_reset; + @(posedge rst_n); + @(posedge clk); + endtask + + //-------------------------------------- + // DUT Axi busses + //-------------------------------------- + dma_req_t [NoMstPorts-1:0] axi_dma_req; + dma_resp_t [NoMstPorts-1:0] axi_dma_res; + + //dma_req_t [NoMstPorts-1:0] axi_dma_sync_req; + //dma_resp_t [NoMstPorts-1:0] axi_dma_sync_res; + + mem_req_t [NoSlvPorts-1:0] axi_mem_req; + mem_resp_t [NoSlvPorts-1:0] axi_mem_res; + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) dma [NoMstPorts-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) dma_sync [NoMstPorts-1:0] (); + + AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) dma_dv [NoMstPorts-1:0] (clk); + + for (genvar i = 0; i < NoMstPorts; i++) begin : gen_conn_dv_masters + //`AXI_ASSIGN (dma_dv[i], dma[i]) + `AXI_ASSIGN_FROM_REQ(dma[i], axi_dma_req[i]) + `AXI_ASSIGN_TO_RESP(axi_dma_res[i], dma[i]) + end + + AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) mem_dv [NoSlvPorts-1:0] (clk); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) mem [NoSlvPorts-1:0] (); + + for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_conn_dv_slaves + `AXI_ASSIGN (mem_dv[i], mem[i]) + `AXI_ASSIGN_TO_REQ(axi_mem_req[i], mem_dv[i]) + `AXI_ASSIGN_TO_RESP(axi_mem_res[i], mem_dv[i]) + end + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma1_t; + + driver_dma_t driver_dma = new(mem_dv[0]); + driver_dma1_t driver_dma1 = new(mem_dv[1]); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem0 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[0]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem1 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[1]) + ); + + // initial begin + // $readmemh("sim_mem0.mem", i_sim_mem0.mem); + // $readmemh("sim_mem1.mem", i_sim_mem1.mem); + // end + + //-------------------------------------- + // DUT AXI Memory System + //-------------------------------------- + // lfsr + logic [784:0] lfsr_dut_q, lfsr_dut_d; + + // transaction id + logic [ 7:0] transaction_id = 0; + + // Memory + block_t dma_memory [bit [AddrWidth-$clog2($bits(block_t))-1:0]]; + block_t dma_memory1 [bit [AddrWidth-$clog2($bits(block_t))-1:0]]; + + // Handle the data output from dma. Model of the memory acting as AXI slave. +// typedef axi_test::axi_driver #(.AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(1), .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod)) driver_dma_t; +// typedef axi_test::axi_driver #(.AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(1), .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod)) driver_dma1_t; +// driver_dma_t driver_dma = new(mem_dv[0]); +// driver_dma_t driver_dma1 = new(mem_dv[1]); +// initial begin +// automatic driver_dma_t::ax_beat_t aw_dma_queue[$], ar_dma_queue[$]; +// automatic driver_dma_t::b_beat_t b_dma_queue[$]; + +// automatic driver_dma1_t::ax_beat_t aw_dma1_queue[$], ar_dma1_queue[$]; +// automatic driver_dma1_t::b_beat_t b_dma1_queue[$]; +// automatic string sb = ""; + +// event ar_dma_received, aw_dma_received, b_dma_ready; +// event ar_dma1_received, aw_dma1_received, b_dma1_ready; +// event lfsr_dut_read; +// event lfsr_dut_read_completed; + +// driver_dma.reset_slave(); +// driver_dma1.reset_slave(); +// @(posedge rst_n); +// $display("AXI reset done"); + +// fork +// // AW mem 0 +// forever begin +// automatic driver_dma_t::ax_beat_t dma_tx; +// driver_dma.recv_aw(dma_tx); +// `ifdef MEM_DEBUG +// $display("Mem0: %d: AW - id: %4d - addr: %d - len: %4d - size: %4d - burst: %b", +// $time(), dma_tx.ax_id, dma_tx.ax_addr, dma_tx.ax_len, dma_tx.ax_size, dma_tx.ax_burst ); +// `endif +// aw_dma_queue.push_back(dma_tx); +// -> aw_dma_received; +// end +// // AW mem 1 +// forever begin +// automatic driver_dma1_t::ax_beat_t dma1_tx; +// driver_dma1.recv_aw(dma1_tx); +// `ifdef MEM_DEBUG +// $display("Mem1: %d: AW - id: %4d - addr: %d - len: %4d - size: %4d - burst: %b", +// $time(), dma1_tx.ax_id, dma1_tx.ax_addr, dma1_tx.ax_len, dma1_tx.ax_size, dma1_tx.ax_burst ); +// `endif +// aw_dma1_queue.push_back(dma1_tx); +// -> aw_dma1_received; +// end +// // AR mem 0 +// forever begin +// automatic driver_dma_t::ax_beat_t dma_tx; +// driver_dma.recv_ar(dma_tx); +// `ifdef MEM_DEBUG +// $display("Mem0: %d: AR - id: %4d - addr: %d - len: %4d - size: %4d - burst: %b", +// $time(), dma_tx.ax_id, dma_tx.ax_addr, dma_tx.ax_len, dma_tx.ax_size, dma_tx.ax_burst ); +// `endif +// ar_dma_queue.push_back(dma_tx); +// -> ar_dma_received; +// end +// // AR mem 1 +// forever begin +// automatic driver_dma1_t::ax_beat_t dma1_tx; +// driver_dma1.recv_ar(dma1_tx); +// `ifdef MEM_DEBUG +// $display("Mem1: %d: AR - id: %4d - addr: %d - len: %4d - size: %4d - burst: %b", +// $time(), dma1_tx.ax_id, dma1_tx.ax_addr, dma1_tx.ax_len, dma1_tx.ax_size, dma1_tx.ax_burst ); +// `endif +// ar_dma1_queue.push_back(dma1_tx); +// -> ar_dma1_received; +// end +// // R mem 0 +// forever begin +// automatic driver_dma_t::r_beat_t dma_tx = new(); +// automatic driver_dma_t::ax_beat_t dma_ax; +// automatic bit [AddrWidth-1:0] word; +// while (ar_dma_queue.size() == 0) @ar_dma_received; +// dma_ax = ar_dma_queue[0]; +// word = dma_ax.ax_addr >> $clog2(AddrWidth); +// dma_tx.r_id = dma_ax.ax_id; +// // if (!dma_memory.exists(word)) begin +// // dma_memory[word].data = lfsr_dut_q[784:273]; +// // //shift 513x +// // repeat(513) begin +// // // next state +// // for (int i = 1; i < 785; i = i +1) lfsr_dut_d[i-1] = lfsr_dut_q[i]; +// // lfsr_dut_d[784] = lfsr_dut_q[0]; +// // lfsr_dut_d[692] = lfsr_dut_q[0] ^ lfsr_dut_q[693]; +// // lfsr_dut_q = lfsr_dut_d; +// // end +// // end +// // dma_tx.r_data = dma_memory[word].data; +// dma_tx.r_resp = axi_pkg::RESP_OKAY; +// dma_tx.r_last = (dma_ax.ax_len == 0); +// `ifdef MEM_DEBUG +// $display("Mem0: %d: R - id: %4d - data: %x - resp: %x - last: %b (0x%x)", +// $time(), dma_tx.r_id, dma_tx.r_data, dma_tx.r_resp, dma_tx.r_last, word << $clog2(AddrWidth)); +// `endif +// dma_ax.ax_addr >>= dma_ax.ax_size; +// dma_ax.ax_addr += (dma_ax.ax_burst !== 0); +// dma_ax.ax_addr <<= dma_ax.ax_size; +// dma_ax.ax_len -= 1; +// if (dma_tx.r_last) begin +// ar_dma_queue.pop_front(); +// end +// driver_dma.send_r(dma_tx); +// end +// // R mem 1 +// forever begin +// automatic driver_dma1_t::r_beat_t dma1_tx = new(); +// automatic driver_dma1_t::ax_beat_t dma1_ax; +// automatic bit [AddrWidth-1:0] word; +// while (ar_dma1_queue.size() == 0) @ar_dma1_received; +// dma1_ax = ar_dma1_queue[0]; +// word = dma1_ax.ax_addr >> $clog2(AddrWidth); +// dma1_tx.r_id = dma1_ax.ax_id; +// // if (!dma_memory1.exists(word)) begin +// // dma_memory1[word].data = lfsr_dut_q[784:273]; +// // //shift 513x +// // repeat(513) begin +// // // next state +// // for (int i = 1; i < 785; i = i +1) lfsr_dut_d[i-1] = lfsr_dut_q[i]; +// // lfsr_dut_d[784] = lfsr_dut_q[0]; +// // lfsr_dut_d[692] = lfsr_dut_q[0] ^ lfsr_dut_q[693]; +// // lfsr_dut_q = lfsr_dut_d; +// // end +// // end +// // dma1_tx.r_data = dma_memory1[word].data; +// dma1_tx.r_resp = axi_pkg::RESP_OKAY; +// dma1_tx.r_last = (dma1_ax.ax_len == 0); +// `ifdef MEM_DEBUG +// $display("Mem1: %d: R - id: %4d - data: %x - resp: %x - last: %b (0x%x)", +// $time(), dma1_tx.r_id, dma1_tx.r_data, dma1_tx.r_resp, dma1_tx.r_last, word << $clog2(AddrWidth)); +// `endif +// dma1_ax.ax_addr >>= dma1_ax.ax_size; +// dma1_ax.ax_addr += (dma1_ax.ax_burst !== 0); +// dma1_ax.ax_addr <<= dma1_ax.ax_size; +// dma1_ax.ax_len -= 1; +// if (dma1_tx.r_last) begin +// ar_dma1_queue.pop_front(); +// end +// driver_dma1.send_r(dma1_tx); +// end +// // W mem 0 +// forever begin +// automatic driver_dma_t::w_beat_t dma_tx; +// automatic driver_dma_t::ax_beat_t dma_ax; +// automatic bit [AddrWidth-1:0] word; +// driver_dma.recv_w(dma_tx); +// while (aw_dma_queue.size() == 0) @ar_dma_received; +// dma_ax = aw_dma_queue[0]; +// word = dma_ax.ax_addr >> $clog2(AddrWidth); +// //$display("Ready to write"); +// //$display("%x", word); +// // for (int i = 0; i < StrbWidth; i++) begin +// // if (dma_tx.w_strb[i]) begin +// // dma_memory[word].bytes[i] = dma_tx.w_data[i*8+:8]; +// // end +// // end +// `ifdef MEM_DEBUG +// $display("Mem0: %d: W - data: %x - strb: %x - last: %b (0x%x)", +// $time(), dma_tx.w_data, dma_tx.w_strb, dma_tx.w_last, word << $clog2(AddrWidth)); +// `endif +// dma_ax.ax_addr >>= dma_ax.ax_size; +// dma_ax.ax_addr += (dma_ax.ax_burst !== 0); +// dma_ax.ax_addr <<= dma_ax.ax_size; +// dma_ax.ax_len -= 1; +// if (dma_tx.w_last) begin +// automatic driver_dma_t::b_beat_t dma_tx = new(); +// dma_tx.b_id = dma_ax.ax_id; +// dma_tx.b_user = dma_ax.ax_user; +// aw_dma_queue.pop_front(); +// b_dma_queue.push_back(dma_tx); +// -> b_dma_ready; +// end +// end +// // W mem 1 +// forever begin +// automatic driver_dma1_t::w_beat_t dma1_tx; +// automatic driver_dma1_t::ax_beat_t dma1_ax; +// automatic bit [AddrWidth-1:0] word; +// driver_dma1.recv_w(dma1_tx); +// while (aw_dma1_queue.size() == 0) @ar_dma1_received; +// dma1_ax = aw_dma1_queue[0]; +// word = dma1_ax.ax_addr >> $clog2(AddrWidth); +// //$display("Ready to write"); +// //$display("%x", word); +// // for (int i = 0; i < StrbWidth; i++) begin +// // if (dma1_tx.w_strb[i]) begin +// // dma_memory1[word].bytes[i] = dma1_tx.w_data[i*8+:8]; +// // end +// // end +// `ifdef MEM_DEBUG +// $display("Mem1: %d: W - data: %x - strb: %x - last: %b (0x%x)", +// $time(), dma1_tx.w_data, dma1_tx.w_strb, dma1_tx.w_last, word << $clog2(AddrWidth)); +// `endif +// dma1_ax.ax_addr >>= dma1_ax.ax_size; +// dma1_ax.ax_addr += (dma1_ax.ax_burst !== 0); +// dma1_ax.ax_addr <<= dma1_ax.ax_size; +// dma1_ax.ax_len -= 1; +// if (dma1_tx.w_last) begin +// automatic driver_dma1_t::b_beat_t dma1_tx = new(); +// dma1_tx.b_id = dma1_ax.ax_id; +// dma1_tx.b_user = dma1_ax.ax_user; +// aw_dma1_queue.pop_front(); +// b_dma1_queue.push_back(dma1_tx); +// -> b_dma1_ready; +// end +// end +// // B mem 0 +// forever begin +// automatic driver_dma_t::b_beat_t dma_tx; +// while (b_dma_queue.size() == 0) @b_dma_ready; +// driver_dma.send_b(b_dma_queue[0]); +// b_dma_queue.pop_front(); +// end +// // B mem 1 +// forever begin +// automatic driver_dma1_t::b_beat_t dma1_tx; +// while (b_dma1_queue.size() == 0) @b_dma1_ready; +// driver_dma1.send_b(b_dma1_queue[0]); +// b_dma1_queue.pop_front(); +// end +// join_any +// end + + //-------------------------------------- + // DMA instantiation + //-------------------------------------- + burst_req_t burst_req; + logic burst_req_valid; + logic burst_req_ready; + logic backend_idle; + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[0] ), + .axi_dma_res_i ( axi_dma_res[0] ), + .burst_req_i ( burst_req ), + .valid_i ( burst_req_valid ), + .ready_o ( burst_req_ready ), + .backend_idle_o ( backend_idle ), + .trans_complete_o ( ), + .dma_id_i ( '0 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[0] ), + .out ( dma_sync[0] ) + ); + + //----------------------------------- + // DUT + //----------------------------------- + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg ), + .NoSlvPorts ( xbar_cfg.NoSlvPorts ), + .NoMstPorts ( xbar_cfg.NoMstPorts ), + .Connectivity ( Connectivity ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( dma_sync ), + .mst_ports ( mem ), + .addr_map_i ( AddrMap ) + ); + + //-------------------------------------- + // DMA DUT tasks + //-------------------------------------- + task oned_dut_launch ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst_req_valid <= 1'b0; + burst_req <= '0; + @(posedge clk); + while (burst_req_ready !== 1) @(posedge clk); + // write data + burst_req.id <= transf_id_i; + burst_req.src <= src_addr_i; + burst_req.dst <= dst_addr_i; + burst_req.num_bytes <= num_bytes_i; + burst_req.cache_src <= src_cache_i; + burst_req.cache_dst <= dst_cache_i; + burst_req.burst_src <= src_burst_i; + burst_req.burst_dst <= dst_burst_i; + burst_req.decouple_rw <= decouple_rw_i; + burst_req.deburst <= deburst_i; + burst_req.serialize <= serialize_i; + burst_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst_req_valid <= 1'b0; + burst_req <= '0; + endtask + + task oned_reset (); + burst_req_valid <= 1'b0; + burst_req <= '0; + endtask + + task wait_for_dut_completion (); + repeat(10) @(posedge clk); + while (backend_idle === 0) @(posedge clk); + repeat(50) @(posedge clk); + endtask + + task clear_dut_memory (); + dma_memory.delete(); + dma_memory1.delete(); + endtask + + task reset_dut_lfsr (); + lfsr_dut_q <= 'hc0a232c162b2bab5b960668030f4efce27940bd0de965f0b8d4315f15b79704195e4e0a6b495fc269f65ae17e10e9ca98510fc143327a292b418597f9dd175fc91c3d61be287d5462a23e00fa7ae906ae9eb339ab5225021356138cd46b6e5a73540c5591116b6b5e08d2c0e54eaf0d5143b33b2186b6cf841c076a98c412a63981f0e323dce93481ed1c37e4f1d7553b6c2fba1a3af6c3ad88b15ad58812ba07d1753917ac4e6ab1e8c4f67a47b4b0f48a34f42a52c546e979f4e4968e80a732a0a5e7a51146cf08482f349f94336752b765c0b1d70803d883d5058d127264335213da4163c62f65a4e65501b90fa5f177675c0747cfca328e131bfb3f7bcc5c27680c7bf86491f4ed3d36c25531edfa74b1e32fafe426958ae356eb8ef0fd818eaca4227a667b7c934ebfa282ab6bfc6db89b927c91a41e63a9554dced774f30268d0725a1a565368703b9f81d5c027ba196ef8b803a51c639c7ead834e1d6bc537d33800fe5eb12f1ed67758f1dfe85ffdbae56e8ef27f2ecedcee75b8dbb5f5f1a629ba3b755; + endtask + + //-------------------------------------- + // Osmium Model + //-------------------------------------- + // Memory + block_t osmium_memory [bit [AddrWidth-$clog2($bits(block_t))-1:0]]; + // lfsr + logic [784:0] lfsr_osmium_q,lfsr_osmium_d; + + task oned_osmium_launch ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i + ); + logic [AddrWidth-1:0] read_addr, write_addr; + logic [AddrWidth-1:0] read_word, write_word; + logic [$clog2(AddrWidth):0] read_offset, write_offset; + // perform the transfer + for(int i = 0; i < num_bytes_i; i = i + 1) begin + read_addr = src_addr_i + i; + write_addr = dst_addr_i + i; + read_word = src_burst_i == 2'b00 ? src_addr_i >> $clog2(AddrWidth) : read_addr >> $clog2(AddrWidth); + write_word = dst_burst_i == 2'b00 ? dst_addr_i >> $clog2(AddrWidth) : write_addr >> $clog2(AddrWidth); + read_offset = read_addr [$clog2(AddrWidth)-1:0]; + write_offset = write_addr[$clog2(AddrWidth)-1:0]; + + // do the read + if (!osmium_memory.exists(read_word) === 1) begin + osmium_memory[read_word].data = lfsr_osmium_q[784:273]; + //shift 513x + repeat(513) begin + // next state + for (int i = 1; i < 785; i = i +1) lfsr_osmium_d[i-1] = lfsr_osmium_q[i]; + lfsr_osmium_d[784] = lfsr_osmium_q[0]; + lfsr_osmium_d[692] = lfsr_osmium_q[0] ^ lfsr_osmium_q[693]; + lfsr_osmium_q = lfsr_osmium_d; + end + end + // do the write + osmium_memory[write_word].bytes[write_offset] = osmium_memory[read_word].bytes[read_offset]; + // $display("W: %d - %d R: %d - %d", write_word, write_offset, read_word, read_offset); + end + + endtask + + task clear_osmium_memory (); + osmium_memory.delete(); + endtask + + task reset_osmium_lfsr (); + lfsr_osmium_q = 'hc0a232c162b2bab5b960668030f4efce27940bd0de965f0b8d4315f15b79704195e4e0a6b495fc269f65ae17e10e9ca98510fc143327a292b418597f9dd175fc91c3d61be287d5462a23e00fa7ae906ae9eb339ab5225021356138cd46b6e5a73540c5591116b6b5e08d2c0e54eaf0d5143b33b2186b6cf841c076a98c412a63981f0e323dce93481ed1c37e4f1d7553b6c2fba1a3af6c3ad88b15ad58812ba07d1753917ac4e6ab1e8c4f67a47b4b0f48a34f42a52c546e979f4e4968e80a732a0a5e7a51146cf08482f349f94336752b765c0b1d70803d883d5058d127264335213da4163c62f65a4e65501b90fa5f177675c0747cfca328e131bfb3f7bcc5c27680c7bf86491f4ed3d36c25531edfa74b1e32fafe426958ae356eb8ef0fd818eaca4227a667b7c934ebfa282ab6bfc6db89b927c91a41e63a9554dced774f30268d0725a1a565368703b9f81d5c027ba196ef8b803a51c639c7ead834e1d6bc537d33800fe5eb12f1ed67758f1dfe85ffdbae56e8ef27f2ecedcee75b8dbb5f5f1a629ba3b755; + endtask + + //-------------------------------------- + // Compare Memory content + //-------------------------------------- + task compare_memories (); + + // go through osmium memory and compare contents + foreach(osmium_memory[i]) begin + if (osmium_memory[i] !== dma_memory[i]) $fatal("Memory mismatch @ %x\nexpect: %x\ngot :%x\n", i << $clog2(AddrWidth), osmium_memory[i], dma_memory[i]); + end + // go through dma memory and compare contents + foreach(dma_memory[i]) begin + if (osmium_memory[i] !== dma_memory[i]) $fatal("Memory mismatch @ %x\nexpect: %x\ngot :%x\n", i << $clog2(AddrWidth), osmium_memory[i], dma_memory[i]); + end + + // it worked :P + $display(" - :D"); + + endtask + + //-------------------------------------- + // Master tasks + //-------------------------------------- + + task clear_memory (); + clear_dut_memory(); + clear_osmium_memory(); + endtask + + task reset_lfsr (); + reset_dut_lfsr(); + reset_osmium_lfsr(); + endtask + + task oned_launch ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task reset (); + int my_file; + oned_reset(); + wait_for_reset(); + // clear trace file + my_file = $fopen("dma_transfers.txt", "w"); + $fwrite(my_file, "Transfers launched:\n"); + $fclose(my_file); + endtask + + task oned_random_launch( + input logic [15:0] max_len, + input logic wait_for_completion + ); + + logic [ IdWidth-1:0] transf_id; + logic [ AddrWidth-1:0] src_addr, dst_addr, num_bytes; + logic decouple_rw; + logic deburst; + logic serialize; + + transf_id = 0;//$urandom(); + // transf_id = transaction_id; + src_addr[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr[(AddrWidth/2)-1: 0] = $urandom(); + num_bytes = 0; + num_bytes[15: 0] = $urandom_range(max_len, 1); + decouple_rw = 0;//$urandom(); + deburst = 0;//$urandom(); + serialize = 0;//$urandom(); + + // transaction_id = transaction_id + 1; + + oned_launch(transf_id, src_addr, dst_addr, num_bytes, decouple_rw, deburst, serialize, wait_for_completion); + + endtask + +endmodule : fixture_axi_dma_backend diff --git a/test/fixture_axi_dma_backend_2x2_2M2S.sv b/test/fixture_axi_dma_backend_2x2_2M2S.sv new file mode 100644 index 000000000..60810d9a0 --- /dev/null +++ b/test/fixture_axi_dma_backend_2x2_2M2S.sv @@ -0,0 +1,1069 @@ +// Copyright (c) 2019 ETH Zurich, University of Bologna +// All rights reserved. +// +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// +// Thomas Benz + +// fixture for the AXi DMA backend +// the fixture instantiates the DMA backend, a golden model of the backend , and tasks controlling +// both. + +`timescale 1ns/1ns +module fixture_axi_dma_backend(); + + // `include "../axi/include/axi/assign.svh" + `define MEM_DEBUG 1 + `include "axi/assign.svh" + `include "axi/typedef.svh" + + //-------------------------------------- + // Parameters + //-------------------------------------- + localparam TA = 0.2ns; // must be nonzero to avoid Snitch load fifo double pop glitch + localparam TT = 0.8ns; + localparam HalfPeriod = 50ns; + localparam Reset = 75ns; + + localparam DataWidth = 512; + localparam AddrWidth = 32; + localparam StrbWidth = DataWidth / 8; + localparam IdWidth = 6; + localparam UserWidth = 1; + + // DUT parameters + localparam bit ATOPs = 0; + localparam int unsigned NoMst = 2; + localparam int unsigned NoSlv = 2; + localparam int unsigned NoSlvPorts_1 = 2; + localparam int unsigned NoMstPorts_1 = 2; + localparam int unsigned NoSlvPorts_0 = 1; + localparam int unsigned NoMstPorts_0 = 1; + localparam bit [NoSlvPorts_1-1:0][NoMstPorts_1-1:0] Connectivity_1 = '1; + localparam bit [NoSlvPorts_0-1:0][NoMstPorts_0-1:0] Connectivity_0 = '1; + localparam int unsigned AxiSlvPortMaxUniqIds = 32'd16; + localparam int unsigned AxiSlvPortMaxTxnsPerId = 32'd128; + localparam int unsigned AxiSlvPortMaxTxns = 32'd31; + localparam int unsigned AxiMstPortMaxUniqIds = 32'd4; + localparam int unsigned AxiMstPortMaxTxnsPerId = 32'd7; + localparam int unsigned NoAddrRules_1 = 32'd2; + localparam int unsigned NoAddrRules_0 = 32'd1; + + typedef axi_pkg::xbar_rule_32_t rule_t; // Has to be the same width as axi addr + + // axi configuration + localparam int unsigned AxiIdWidthMasters = IdWidth; + localparam int unsigned AxiIdUsed = IdWidth-1; // Has to be <= AxiIdWidthMasters + localparam int unsigned AxiIdWidthSlaves = AxiIdWidthMasters + $clog2(NoMstPorts_1); + localparam int unsigned AxiAddrWidth = AddrWidth; // Axi Address Width + localparam int unsigned AxiDataWidth = DataWidth; // Axi Data Width + localparam int unsigned AxiStrbWidth = StrbWidth; + localparam int unsigned AxiUserWidth = UserWidth; + localparam int unsigned AxiIdWidth = IdWidth; + // in the bench can change this variables which are set here freely + localparam axi_pkg::xbar_cfg_t xbar_cfg_2 = '{ + NoSlvPorts: NoMstPorts_1, + NoMstPorts: NoSlvPorts_1, + MaxMstTrans: AxiSlvPortMaxTxns, + MaxSlvTrans: AxiSlvPortMaxTxnsPerId, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_PORTS, + AxiIdWidthSlvPorts: AxiIdWidthMasters, + AxiIdUsedSlvPorts: AxiIdUsed, + UniqueIds: 1'b0, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: NoAddrRules_1 + }; + + localparam axi_pkg::xbar_cfg_t xbar_cfg_1 = '{ + NoSlvPorts: NoMstPorts_1, + NoMstPorts: NoSlvPorts_1, + MaxMstTrans: AxiSlvPortMaxTxns, + MaxSlvTrans: AxiSlvPortMaxTxnsPerId, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_PORTS, + AxiIdWidthSlvPorts: AxiIdWidthMasters, + AxiIdUsedSlvPorts: AxiIdUsed, + UniqueIds: 1'b0, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: NoAddrRules_1 + }; + + localparam axi_pkg::xbar_cfg_t xbar_cfg_0 = '{ + NoSlvPorts: NoMstPorts_0, + NoMstPorts: NoSlvPorts_0, + MaxMstTrans: AxiSlvPortMaxTxns, + MaxSlvTrans: AxiSlvPortMaxTxnsPerId, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_PORTS, + AxiIdWidthSlvPorts: AxiIdWidthMasters, + AxiIdUsedSlvPorts: AxiIdUsed, + UniqueIds: 1'b0, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: NoAddrRules_0 + }; + + localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2 = '{ + '{idx: 32'd1 % NoSlvPorts_1, start_addr: {AddrWidth{1'b0}}, end_addr: {1'b0, {(AddrWidth-1){1'b1}}}}, + '{idx: 32'd0 % NoSlvPorts_1, start_addr: {1'b0, {(AddrWidth-1){1'b1}}}, end_addr: {(AddrWidth){1'b1}}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp1 = '{ + '{idx: 32'd1 % NoSlvPorts_1, start_addr: {1'b0, {(AddrWidth-1){1'b1}}}, end_addr: {(AddrWidth){1'b1}}}, + '{idx: 32'd0 % NoSlvPorts_1, start_addr: {AddrWidth{1'b0}}, end_addr: {1'b0, {(AddrWidth-1){1'b1}}}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_0.NoAddrRules-1:0] AddrMap_xp0 = '{ + '{idx: 32'd0 % NoSlvPorts_0, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + typedef union packed { + logic [StrbWidth-1:0][7:0] bytes; + logic [DataWidth-1:0] data; + } block_t; + + /// Address Type + typedef logic [ AddrWidth-1:0] addr_t; + /// Data Type + typedef logic [ DataWidth-1:0] data_t; + /// Strobe Type + typedef logic [ StrbWidth-1:0] strb_t; + /// AXI ID Type + typedef logic [ IdWidth-1:0] axi_id_t; + /// AXI USER Type + typedef logic [ UserWidth-1:0] user_t; + /// 1D burst request + typedef struct packed { + axi_id_t id; + addr_t src, dst, num_bytes; + axi_pkg::cache_t cache_src, cache_dst; + axi_pkg::burst_t burst_src, burst_dst; + logic decouple_rw; + logic deburst; + logic serialize; + } burst_req_t; + + // master AXI bus --> DMA + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_dma_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_dma_t, axi_id_t, user_t) + + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_dma_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_dma_t, data_t, axi_id_t, user_t) + + `AXI_TYPEDEF_REQ_T(dma_req_t, aw_chan_dma_t, w_chan_t, ar_chan_dma_t) + `AXI_TYPEDEF_RESP_T(dma_resp_t, b_chan_dma_t, r_chan_dma_t) + + // slave AXI bus --> mem + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_mem_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_mem_t, axi_id_t, user_t) + + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_mem_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_mem_t, data_t, axi_id_t, user_t) + + `AXI_TYPEDEF_REQ_T(mem_req_t, aw_chan_mem_t, w_chan_t, ar_chan_mem_t) + `AXI_TYPEDEF_RESP_T(mem_resp_t, b_chan_mem_t, r_chan_mem_t) + + //-------------------------------------- + // Clock and Reset + //-------------------------------------- + logic clk; + initial begin + forever begin + clk = 0; + #HalfPeriod; + clk = 1; + #HalfPeriod; + end + end + + logic rst_n; + initial begin + rst_n = 0; + #Reset; + rst_n = 1; + end + + task wait_for_reset; + @(posedge rst_n); + @(posedge clk); + endtask + + //-------------------------------------- + // DUT Axi busses + //-------------------------------------- + dma_req_t [NoMstPorts_1-1:0] axi_dma_req; + dma_resp_t [NoMstPorts_1-1:0] axi_dma_res; + + //dma_req_t [NoMstPorts-1:0] axi_dma_sync_req; + //dma_resp_t [NoMstPorts-1:0] axi_dma_sync_res; + + mem_req_t [NoSlvPorts_1-1:0] axi_mem_req; + mem_resp_t [NoSlvPorts_1-1:0] axi_mem_res; + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) dma [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) dma_sync [NoMstPorts_1-1:0] (); + + AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) dma_dv [NoMstPorts_1-1:0] (clk); + + for (genvar i = 0; i < NoMstPorts_1; i++) begin : gen_conn_dv_masters + //`AXI_ASSIGN (dma_dv[i], dma[i]) + `AXI_ASSIGN_FROM_REQ(dma[i], axi_dma_req[i]) + `AXI_ASSIGN_TO_RESP(axi_dma_res[i], dma[i]) + end + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_slv_0 [NoSlvPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_slv_1 [NoSlvPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_slv [NoSlvPorts_0-1:0] (); + + `AXI_ASSIGN (xp0_slv_0[0], xp0_slv[0]) + `AXI_ASSIGN (xp0_slv_1[0], xp0_slv[1]) + + AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) mem_dv [NoSlvPorts_1-1:0] (clk); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) mem_0 [NoSlvPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) mem_1 [NoSlvPorts_0-1:0] (); + + for (genvar i = 0; i < NoSlvPorts_1; i++) begin : gen_conn_dv_slaves + //`AXI_ASSIGN (mem_dv[i], mem[i]) + `AXI_ASSIGN_TO_REQ(axi_mem_req[i], mem_dv[i]) + `AXI_ASSIGN_TO_RESP(axi_mem_res[i], mem_dv[i]) + end + + `AXI_ASSIGN (mem_dv[0], mem_0[0]) + `AXI_ASSIGN (mem_dv[1], mem_1[0]) + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma1_t; + + driver_dma_t driver_dma = new(mem_dv[0]); + driver_dma1_t driver_dma1 = new(mem_dv[1]); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem0 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[0]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem1 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[1]) + ); + + // initial begin + // $readmemh("sim_mem0.mem", i_sim_mem0.mem); + // $readmemh("sim_mem1.mem", i_sim_mem1.mem); + // end + + //-------------------------------------- + // DUT AXI Memory System + //-------------------------------------- + // lfsr + logic [784:0] lfsr_dut_q, lfsr_dut_d; + + // transaction id + logic [ 7:0] transaction_id = 0; + + // Memory + block_t dma_memory [bit [AddrWidth-$clog2($bits(block_t))-1:0]]; + block_t dma_memory1 [bit [AddrWidth-$clog2($bits(block_t))-1:0]]; + + // Handle the data output from dma. Model of the memory acting as AXI slave. +// typedef axi_test::axi_driver #(.AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(1), .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod)) driver_dma_t; +// typedef axi_test::axi_driver #(.AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(1), .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod)) driver_dma1_t; +// driver_dma_t driver_dma = new(mem_dv[0]); +// driver_dma_t driver_dma1 = new(mem_dv[1]); +// initial begin +// automatic driver_dma_t::ax_beat_t aw_dma_queue[$], ar_dma_queue[$]; +// automatic driver_dma_t::b_beat_t b_dma_queue[$]; + +// automatic driver_dma1_t::ax_beat_t aw_dma1_queue[$], ar_dma1_queue[$]; +// automatic driver_dma1_t::b_beat_t b_dma1_queue[$]; +// automatic string sb = ""; + +// event ar_dma_received, aw_dma_received, b_dma_ready; +// event ar_dma1_received, aw_dma1_received, b_dma1_ready; +// event lfsr_dut_read; +// event lfsr_dut_read_completed; + +// driver_dma.reset_slave(); +// driver_dma1.reset_slave(); +// @(posedge rst_n); +// $display("AXI reset done"); + +// fork +// // AW mem 0 +// forever begin +// automatic driver_dma_t::ax_beat_t dma_tx; +// driver_dma.recv_aw(dma_tx); +// `ifdef MEM_DEBUG +// $display("Mem0: %d: AW - id: %4d - addr: %d - len: %4d - size: %4d - burst: %b", +// $time(), dma_tx.ax_id, dma_tx.ax_addr, dma_tx.ax_len, dma_tx.ax_size, dma_tx.ax_burst ); +// `endif +// aw_dma_queue.push_back(dma_tx); +// -> aw_dma_received; +// end +// // AW mem 1 +// forever begin +// automatic driver_dma1_t::ax_beat_t dma1_tx; +// driver_dma1.recv_aw(dma1_tx); +// `ifdef MEM_DEBUG +// $display("Mem1: %d: AW - id: %4d - addr: %d - len: %4d - size: %4d - burst: %b", +// $time(), dma1_tx.ax_id, dma1_tx.ax_addr, dma1_tx.ax_len, dma1_tx.ax_size, dma1_tx.ax_burst ); +// `endif +// aw_dma1_queue.push_back(dma1_tx); +// -> aw_dma1_received; +// end +// // AR mem 0 +// forever begin +// automatic driver_dma_t::ax_beat_t dma_tx; +// driver_dma.recv_ar(dma_tx); +// `ifdef MEM_DEBUG +// $display("Mem0: %d: AR - id: %4d - addr: %d - len: %4d - size: %4d - burst: %b", +// $time(), dma_tx.ax_id, dma_tx.ax_addr, dma_tx.ax_len, dma_tx.ax_size, dma_tx.ax_burst ); +// `endif +// ar_dma_queue.push_back(dma_tx); +// -> ar_dma_received; +// end +// // AR mem 1 +// forever begin +// automatic driver_dma1_t::ax_beat_t dma1_tx; +// driver_dma1.recv_ar(dma1_tx); +// `ifdef MEM_DEBUG +// $display("Mem1: %d: AR - id: %4d - addr: %d - len: %4d - size: %4d - burst: %b", +// $time(), dma1_tx.ax_id, dma1_tx.ax_addr, dma1_tx.ax_len, dma1_tx.ax_size, dma1_tx.ax_burst ); +// `endif +// ar_dma1_queue.push_back(dma1_tx); +// -> ar_dma1_received; +// end +// // R mem 0 +// forever begin +// automatic driver_dma_t::r_beat_t dma_tx = new(); +// automatic driver_dma_t::ax_beat_t dma_ax; +// automatic bit [AddrWidth-1:0] word; +// while (ar_dma_queue.size() == 0) @ar_dma_received; +// dma_ax = ar_dma_queue[0]; +// word = dma_ax.ax_addr >> $clog2(AddrWidth); +// dma_tx.r_id = dma_ax.ax_id; +// // if (!dma_memory.exists(word)) begin +// // dma_memory[word].data = lfsr_dut_q[784:273]; +// // //shift 513x +// // repeat(513) begin +// // // next state +// // for (int i = 1; i < 785; i = i +1) lfsr_dut_d[i-1] = lfsr_dut_q[i]; +// // lfsr_dut_d[784] = lfsr_dut_q[0]; +// // lfsr_dut_d[692] = lfsr_dut_q[0] ^ lfsr_dut_q[693]; +// // lfsr_dut_q = lfsr_dut_d; +// // end +// // end +// // dma_tx.r_data = dma_memory[word].data; +// dma_tx.r_resp = axi_pkg::RESP_OKAY; +// dma_tx.r_last = (dma_ax.ax_len == 0); +// `ifdef MEM_DEBUG +// $display("Mem0: %d: R - id: %4d - data: %x - resp: %x - last: %b (0x%x)", +// $time(), dma_tx.r_id, dma_tx.r_data, dma_tx.r_resp, dma_tx.r_last, word << $clog2(AddrWidth)); +// `endif +// dma_ax.ax_addr >>= dma_ax.ax_size; +// dma_ax.ax_addr += (dma_ax.ax_burst !== 0); +// dma_ax.ax_addr <<= dma_ax.ax_size; +// dma_ax.ax_len -= 1; +// if (dma_tx.r_last) begin +// ar_dma_queue.pop_front(); +// end +// driver_dma.send_r(dma_tx); +// end +// // R mem 1 +// forever begin +// automatic driver_dma1_t::r_beat_t dma1_tx = new(); +// automatic driver_dma1_t::ax_beat_t dma1_ax; +// automatic bit [AddrWidth-1:0] word; +// while (ar_dma1_queue.size() == 0) @ar_dma1_received; +// dma1_ax = ar_dma1_queue[0]; +// word = dma1_ax.ax_addr >> $clog2(AddrWidth); +// dma1_tx.r_id = dma1_ax.ax_id; +// // if (!dma_memory1.exists(word)) begin +// // dma_memory1[word].data = lfsr_dut_q[784:273]; +// // //shift 513x +// // repeat(513) begin +// // // next state +// // for (int i = 1; i < 785; i = i +1) lfsr_dut_d[i-1] = lfsr_dut_q[i]; +// // lfsr_dut_d[784] = lfsr_dut_q[0]; +// // lfsr_dut_d[692] = lfsr_dut_q[0] ^ lfsr_dut_q[693]; +// // lfsr_dut_q = lfsr_dut_d; +// // end +// // end +// // dma1_tx.r_data = dma_memory1[word].data; +// dma1_tx.r_resp = axi_pkg::RESP_OKAY; +// dma1_tx.r_last = (dma1_ax.ax_len == 0); +// `ifdef MEM_DEBUG +// $display("Mem1: %d: R - id: %4d - data: %x - resp: %x - last: %b (0x%x)", +// $time(), dma1_tx.r_id, dma1_tx.r_data, dma1_tx.r_resp, dma1_tx.r_last, word << $clog2(AddrWidth)); +// `endif +// dma1_ax.ax_addr >>= dma1_ax.ax_size; +// dma1_ax.ax_addr += (dma1_ax.ax_burst !== 0); +// dma1_ax.ax_addr <<= dma1_ax.ax_size; +// dma1_ax.ax_len -= 1; +// if (dma1_tx.r_last) begin +// ar_dma1_queue.pop_front(); +// end +// driver_dma1.send_r(dma1_tx); +// end +// // W mem 0 +// forever begin +// automatic driver_dma_t::w_beat_t dma_tx; +// automatic driver_dma_t::ax_beat_t dma_ax; +// automatic bit [AddrWidth-1:0] word; +// driver_dma.recv_w(dma_tx); +// while (aw_dma_queue.size() == 0) @ar_dma_received; +// dma_ax = aw_dma_queue[0]; +// word = dma_ax.ax_addr >> $clog2(AddrWidth); +// //$display("Ready to write"); +// //$display("%x", word); +// // for (int i = 0; i < StrbWidth; i++) begin +// // if (dma_tx.w_strb[i]) begin +// // dma_memory[word].bytes[i] = dma_tx.w_data[i*8+:8]; +// // end +// // end +// `ifdef MEM_DEBUG +// $display("Mem0: %d: W - data: %x - strb: %x - last: %b (0x%x)", +// $time(), dma_tx.w_data, dma_tx.w_strb, dma_tx.w_last, word << $clog2(AddrWidth)); +// `endif +// dma_ax.ax_addr >>= dma_ax.ax_size; +// dma_ax.ax_addr += (dma_ax.ax_burst !== 0); +// dma_ax.ax_addr <<= dma_ax.ax_size; +// dma_ax.ax_len -= 1; +// if (dma_tx.w_last) begin +// automatic driver_dma_t::b_beat_t dma_tx = new(); +// dma_tx.b_id = dma_ax.ax_id; +// dma_tx.b_user = dma_ax.ax_user; +// aw_dma_queue.pop_front(); +// b_dma_queue.push_back(dma_tx); +// -> b_dma_ready; +// end +// end +// // W mem 1 +// forever begin +// automatic driver_dma1_t::w_beat_t dma1_tx; +// automatic driver_dma1_t::ax_beat_t dma1_ax; +// automatic bit [AddrWidth-1:0] word; +// driver_dma1.recv_w(dma1_tx); +// while (aw_dma1_queue.size() == 0) @ar_dma1_received; +// dma1_ax = aw_dma1_queue[0]; +// word = dma1_ax.ax_addr >> $clog2(AddrWidth); +// //$display("Ready to write"); +// //$display("%x", word); +// // for (int i = 0; i < StrbWidth; i++) begin +// // if (dma1_tx.w_strb[i]) begin +// // dma_memory1[word].bytes[i] = dma1_tx.w_data[i*8+:8]; +// // end +// // end +// `ifdef MEM_DEBUG +// $display("Mem1: %d: W - data: %x - strb: %x - last: %b (0x%x)", +// $time(), dma1_tx.w_data, dma1_tx.w_strb, dma1_tx.w_last, word << $clog2(AddrWidth)); +// `endif +// dma1_ax.ax_addr >>= dma1_ax.ax_size; +// dma1_ax.ax_addr += (dma1_ax.ax_burst !== 0); +// dma1_ax.ax_addr <<= dma1_ax.ax_size; +// dma1_ax.ax_len -= 1; +// if (dma1_tx.w_last) begin +// automatic driver_dma1_t::b_beat_t dma1_tx = new(); +// dma1_tx.b_id = dma1_ax.ax_id; +// dma1_tx.b_user = dma1_ax.ax_user; +// aw_dma1_queue.pop_front(); +// b_dma1_queue.push_back(dma1_tx); +// -> b_dma1_ready; +// end +// end +// // B mem 0 +// forever begin +// automatic driver_dma_t::b_beat_t dma_tx; +// while (b_dma_queue.size() == 0) @b_dma_ready; +// driver_dma.send_b(b_dma_queue[0]); +// b_dma_queue.pop_front(); +// end +// // B mem 1 +// forever begin +// automatic driver_dma1_t::b_beat_t dma1_tx; +// while (b_dma1_queue.size() == 0) @b_dma1_ready; +// driver_dma1.send_b(b_dma1_queue[0]); +// b_dma1_queue.pop_front(); +// end +// join_any +// end + + //-------------------------------------- + // DMA instantiation + //-------------------------------------- + burst_req_t burst0_req; + burst_req_t burst1_req; + logic burst0_req_valid; + logic burst1_req_valid; + logic burst0_req_ready; + logic burst1_req_ready; + logic backend_idle_0; + logic backend_idle_1; + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_1 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[1] ), + .axi_dma_res_i ( axi_dma_res[1] ), + .burst_req_i ( burst1_req ), + .valid_i ( burst1_req_valid ), + .ready_o ( burst1_req_ready ), + .backend_idle_o ( backend_idle_1 ), + .trans_complete_o ( ), + .dma_id_i ( '1 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_1 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[1] ), + .out ( dma_sync[1] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_0 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[0] ), + .axi_dma_res_i ( axi_dma_res[0] ), + .burst_req_i ( burst0_req ), + .valid_i ( burst0_req_valid ), + .ready_o ( burst0_req_ready ), + .backend_idle_o ( backend_idle_0 ), + .trans_complete_o ( ), + .dma_id_i ( '0 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_0 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[0] ), + .out ( dma_sync[0] ) + ); + + //----------------------------------- + // DUT + //----------------------------------- + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_0 ), + .NoSlvPorts ( xbar_cfg_0.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_0.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_0.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_3 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp1_slv ), + .mst_ports ( mem_0 ), + .addr_map_i ( AddrMap_xp0 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_0 ), + .NoSlvPorts ( xbar_cfg_0.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_0.NoMstPorts ), + .Connectivity ( Connectivity_0 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_0.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_2 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp0_slv_1 ), + .mst_ports ( mem_1 ), + .addr_map_i ( AddrMap_xp0 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_0 ), + .NoSlvPorts ( xbar_cfg_0.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_0.NoMstPorts ), + .Connectivity ( Connectivity_0 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_0.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_1 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp0_slv_0 ), + .mst_ports ( xp1_slv ), + .addr_map_i ( AddrMap_xp0 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_0 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( dma_sync ), + .mst_ports ( xp0_slv ), + .addr_map_i ( AddrMap_xp1 ) + ); + + //-------------------------------------- + // DMA DUT tasks + //-------------------------------------- + task oned_dut_launch_1 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst1_req_valid <= 1'b0; + burst1_req <= '0; + @(posedge clk); + while (burst1_req_ready !== 1) @(posedge clk); + // write data + burst1_req.id <= transf_id_i; + burst1_req.src <= src_addr_i; + burst1_req.dst <= dst_addr_i; + burst1_req.num_bytes <= num_bytes_i; + burst1_req.cache_src <= src_cache_i; + burst1_req.cache_dst <= dst_cache_i; + burst1_req.burst_src <= src_burst_i; + burst1_req.burst_dst <= dst_burst_i; + burst1_req.decouple_rw <= decouple_rw_i; + burst1_req.deburst <= deburst_i; + burst1_req.serialize <= serialize_i; + burst1_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst1_req_valid <= 1'b0; + burst1_req <= '0; + endtask + + task oned_dut_launch_0 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst0_req_valid <= 1'b0; + burst0_req <= '0; + @(posedge clk); + while (burst0_req_ready !== 1) @(posedge clk); + // write data + burst0_req.id <= transf_id_i; + burst0_req.src <= src_addr_i; + burst0_req.dst <= dst_addr_i; + burst0_req.num_bytes <= num_bytes_i; + burst0_req.cache_src <= src_cache_i; + burst0_req.cache_dst <= dst_cache_i; + burst0_req.burst_src <= src_burst_i; + burst0_req.burst_dst <= dst_burst_i; + burst0_req.decouple_rw <= decouple_rw_i; + burst0_req.deburst <= deburst_i; + burst0_req.serialize <= serialize_i; + burst0_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst0_req_valid <= 1'b0; + burst0_req <= '0; + endtask + + task oned_reset (); + burst0_req_valid <= 1'b0; + burst0_req <= '0; + burst1_req_valid <= 1'b0; + burst1_req <= '0; + endtask + + task wait_for_dut_completion (); + repeat(10) @(posedge clk); + while (backend_idle_0 === 0) @(posedge clk); + while (backend_idle_1 === 0) @(posedge clk); + repeat(50) @(posedge clk); + endtask + + task clear_dut_memory (); + dma_memory.delete(); + dma_memory1.delete(); + endtask + + task reset_dut_lfsr (); + lfsr_dut_q <= 'hc0a232c162b2bab5b960668030f4efce27940bd0de965f0b8d4315f15b79704195e4e0a6b495fc269f65ae17e10e9ca98510fc143327a292b418597f9dd175fc91c3d61be287d5462a23e00fa7ae906ae9eb339ab5225021356138cd46b6e5a73540c5591116b6b5e08d2c0e54eaf0d5143b33b2186b6cf841c076a98c412a63981f0e323dce93481ed1c37e4f1d7553b6c2fba1a3af6c3ad88b15ad58812ba07d1753917ac4e6ab1e8c4f67a47b4b0f48a34f42a52c546e979f4e4968e80a732a0a5e7a51146cf08482f349f94336752b765c0b1d70803d883d5058d127264335213da4163c62f65a4e65501b90fa5f177675c0747cfca328e131bfb3f7bcc5c27680c7bf86491f4ed3d36c25531edfa74b1e32fafe426958ae356eb8ef0fd818eaca4227a667b7c934ebfa282ab6bfc6db89b927c91a41e63a9554dced774f30268d0725a1a565368703b9f81d5c027ba196ef8b803a51c639c7ead834e1d6bc537d33800fe5eb12f1ed67758f1dfe85ffdbae56e8ef27f2ecedcee75b8dbb5f5f1a629ba3b755; + endtask + + //-------------------------------------- + // Osmium Model + //-------------------------------------- + // Memory + block_t osmium_memory [bit [AddrWidth-$clog2($bits(block_t))-1:0]]; + // lfsr + logic [784:0] lfsr_osmium_q,lfsr_osmium_d; + + task oned_osmium_launch ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i + ); + logic [AddrWidth-1:0] read_addr, write_addr; + logic [AddrWidth-1:0] read_word, write_word; + logic [$clog2(AddrWidth):0] read_offset, write_offset; + // perform the transfer + for(int i = 0; i < num_bytes_i; i = i + 1) begin + read_addr = src_addr_i + i; + write_addr = dst_addr_i + i; + read_word = src_burst_i == 2'b00 ? src_addr_i >> $clog2(AddrWidth) : read_addr >> $clog2(AddrWidth); + write_word = dst_burst_i == 2'b00 ? dst_addr_i >> $clog2(AddrWidth) : write_addr >> $clog2(AddrWidth); + read_offset = read_addr [$clog2(AddrWidth)-1:0]; + write_offset = write_addr[$clog2(AddrWidth)-1:0]; + + // do the read + if (!osmium_memory.exists(read_word) === 1) begin + osmium_memory[read_word].data = lfsr_osmium_q[784:273]; + //shift 513x + repeat(513) begin + // next state + for (int i = 1; i < 785; i = i +1) lfsr_osmium_d[i-1] = lfsr_osmium_q[i]; + lfsr_osmium_d[784] = lfsr_osmium_q[0]; + lfsr_osmium_d[692] = lfsr_osmium_q[0] ^ lfsr_osmium_q[693]; + lfsr_osmium_q = lfsr_osmium_d; + end + end + // do the write + osmium_memory[write_word].bytes[write_offset] = osmium_memory[read_word].bytes[read_offset]; + // $display("W: %d - %d R: %d - %d", write_word, write_offset, read_word, read_offset); + end + + endtask + + task clear_osmium_memory (); + osmium_memory.delete(); + endtask + + task reset_osmium_lfsr (); + lfsr_osmium_q = 'hc0a232c162b2bab5b960668030f4efce27940bd0de965f0b8d4315f15b79704195e4e0a6b495fc269f65ae17e10e9ca98510fc143327a292b418597f9dd175fc91c3d61be287d5462a23e00fa7ae906ae9eb339ab5225021356138cd46b6e5a73540c5591116b6b5e08d2c0e54eaf0d5143b33b2186b6cf841c076a98c412a63981f0e323dce93481ed1c37e4f1d7553b6c2fba1a3af6c3ad88b15ad58812ba07d1753917ac4e6ab1e8c4f67a47b4b0f48a34f42a52c546e979f4e4968e80a732a0a5e7a51146cf08482f349f94336752b765c0b1d70803d883d5058d127264335213da4163c62f65a4e65501b90fa5f177675c0747cfca328e131bfb3f7bcc5c27680c7bf86491f4ed3d36c25531edfa74b1e32fafe426958ae356eb8ef0fd818eaca4227a667b7c934ebfa282ab6bfc6db89b927c91a41e63a9554dced774f30268d0725a1a565368703b9f81d5c027ba196ef8b803a51c639c7ead834e1d6bc537d33800fe5eb12f1ed67758f1dfe85ffdbae56e8ef27f2ecedcee75b8dbb5f5f1a629ba3b755; + endtask + + //-------------------------------------- + // Compare Memory content + //-------------------------------------- + task compare_memories (); + + // go through osmium memory and compare contents + foreach(osmium_memory[i]) begin + if (osmium_memory[i] !== dma_memory[i]) $fatal("Memory mismatch @ %x\nexpect: %x\ngot :%x\n", i << $clog2(AddrWidth), osmium_memory[i], dma_memory[i]); + end + // go through dma memory and compare contents + foreach(dma_memory[i]) begin + if (osmium_memory[i] !== dma_memory[i]) $fatal("Memory mismatch @ %x\nexpect: %x\ngot :%x\n", i << $clog2(AddrWidth), osmium_memory[i], dma_memory[i]); + end + + // it worked :P + $display(" - :D"); + + endtask + + //-------------------------------------- + // Master tasks + //-------------------------------------- + + task clear_memory (); + clear_dut_memory(); + clear_osmium_memory(); + endtask + + task reset_lfsr (); + reset_dut_lfsr(); + reset_osmium_lfsr(); + endtask + + task oned_launch_1 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma1_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_1(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_0 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma0_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_0(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task reset (); + int my_file; + oned_reset(); + wait_for_reset(); + // clear trace file + my_file = $fopen("dma_transfers.txt", "w"); + $fwrite(my_file, "Transfers launched:\n"); + $fclose(my_file); + endtask + + task oned_random_launch( + input logic [15:0] max_len, + input logic [31:0] src_add, + input logic [31:0] dst_add, + input logic [15:0] master_id, + input logic [15:0] size, + input logic wait_for_completion + ); + + logic [ IdWidth-1:0] transf_id_0; + logic [ AddrWidth-1:0] src_addr_0, dst_addr_0, num_bytes_0; + logic [ IdWidth-1:0] transf_id_1; + logic [ AddrWidth-1:0] src_addr_1, dst_addr_1, num_bytes_1; + logic decouple_rw; + logic deburst; + logic serialize; + + decouple_rw = 0;//$urandom(); + deburst = 0;//$urandom(); + serialize = 0;//$urandom(); + + if (master_id == 0) begin + transf_id_0 = 0;//$urandom(); + // transf_id = transaction_id; + //src_addr_0[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //src_addr_0[(AddrWidth/2)-1: 0] = $urandom(); + //dst_addr_0[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //dst_addr_0[(AddrWidth/2)-1: 0] = $urandom(); + num_bytes_0 = 0; + num_bytes_0[15: 0] = size; + src_addr_0 = src_add; + dst_addr_0 = dst_add; + + oned_launch_0(transf_id_0, src_addr_0, dst_addr_0, num_bytes_0, decouple_rw, deburst, serialize, wait_for_completion); + + end else begin + transf_id_1 = 1;//$urandom(); + // transf_id = transaction_id; + //src_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //src_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + //dst_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //dst_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + num_bytes_1 = 0; + num_bytes_1[15: 0] = size; + src_addr_1 = src_add; + dst_addr_1 = dst_add; + + oned_launch_1(transf_id_1, src_addr_1, dst_addr_1, num_bytes_1, decouple_rw, deburst, serialize, wait_for_completion); + + end + + // transaction_id = transaction_id + 1; + + + endtask + +endmodule : fixture_axi_dma_backend diff --git a/test/fixture_axi_dma_backend_2x2_4M4S.sv b/test/fixture_axi_dma_backend_2x2_4M4S.sv new file mode 100644 index 000000000..7cb2547e8 --- /dev/null +++ b/test/fixture_axi_dma_backend_2x2_4M4S.sv @@ -0,0 +1,1364 @@ +// Copyright (c) 2019 ETH Zurich, University of Bologna +// All rights reserved. +// +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// +// Thomas Benz + +// fixture for the AXi DMA backend +// the fixture instantiates the DMA backend, a golden model of the backend , and tasks controlling +// both. + +`timescale 1ns/1ns +module fixture_axi_dma_backend(); + + // `include "../axi/include/axi/assign.svh" + `define MEM_DEBUG 1 + `include "axi/assign.svh" + `include "axi/typedef.svh" + + //-------------------------------------- + // Parameters + //-------------------------------------- + localparam TA = 0.2ns; // must be nonzero to avoid Snitch load fifo double pop glitch + localparam TT = 0.8ns; + localparam HalfPeriod = 50ns; + localparam Reset = 75ns; + + localparam DataWidth = 512; + localparam AddrWidth = 32; + localparam StrbWidth = DataWidth / 8; + localparam IdWidth = 6; + localparam UserWidth = 1; + + // DUT parameters + localparam bit ATOPs = 0; + localparam int unsigned NoMst = 4; + localparam int unsigned NoSlv = 4; + localparam int unsigned NoSlvPorts_1 = 3; + localparam int unsigned NoMstPorts_1 = 3; + localparam int unsigned NoSlvPorts_0 = 3; + localparam int unsigned NoMstPorts_0 = 3; + localparam bit [NoSlvPorts_1-1:0][NoMstPorts_1-1:0] Connectivity_1 = '1; + localparam bit [NoSlvPorts_0-1:0][NoMstPorts_0-1:0] Connectivity_0 = '1; + localparam int unsigned AxiSlvPortMaxUniqIds = 32'd16; + localparam int unsigned AxiSlvPortMaxTxnsPerId = 32'd128; + localparam int unsigned AxiSlvPortMaxTxns = 32'd31; + localparam int unsigned AxiMstPortMaxUniqIds = 32'd4; + localparam int unsigned AxiMstPortMaxTxnsPerId = 32'd7; + localparam int unsigned NoAddrRules_1 = 32'd3; + localparam int unsigned NoAddrRules_0 = 32'd3; + + typedef axi_pkg::xbar_rule_32_t rule_t; // Has to be the same width as axi addr + + // axi configuration + localparam int unsigned AxiIdWidthMasters = IdWidth; + localparam int unsigned AxiIdUsed = IdWidth-1; // Has to be <= AxiIdWidthMasters + localparam int unsigned AxiIdWidthSlaves = AxiIdWidthMasters + $clog2(NoMstPorts_1); + localparam int unsigned AxiAddrWidth = AddrWidth; // Axi Address Width + localparam int unsigned AxiDataWidth = DataWidth; // Axi Data Width + localparam int unsigned AxiStrbWidth = StrbWidth; + localparam int unsigned AxiUserWidth = UserWidth; + localparam int unsigned AxiIdWidth = IdWidth; + // in the bench can change this variables which are set here freely + localparam axi_pkg::xbar_cfg_t xbar_cfg_2 = '{ + NoSlvPorts: NoMstPorts_1, + NoMstPorts: NoSlvPorts_1, + MaxMstTrans: AxiSlvPortMaxTxns, + MaxSlvTrans: AxiSlvPortMaxTxnsPerId, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_PORTS, + AxiIdWidthSlvPorts: AxiIdWidthMasters, + AxiIdUsedSlvPorts: AxiIdUsed, + UniqueIds: 1'b0, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: NoAddrRules_1 + }; + + localparam axi_pkg::xbar_cfg_t xbar_cfg_1 = '{ + NoSlvPorts: NoMstPorts_1, + NoMstPorts: NoSlvPorts_1, + MaxMstTrans: AxiSlvPortMaxTxns, + MaxSlvTrans: AxiSlvPortMaxTxnsPerId, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_PORTS, + AxiIdWidthSlvPorts: AxiIdWidthMasters, + AxiIdUsedSlvPorts: AxiIdUsed, + UniqueIds: 1'b0, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: NoAddrRules_1 + }; + + localparam axi_pkg::xbar_cfg_t xbar_cfg_0 = '{ + NoSlvPorts: NoMstPorts_0, + NoMstPorts: NoSlvPorts_0, + MaxMstTrans: AxiSlvPortMaxTxns, + MaxSlvTrans: AxiSlvPortMaxTxnsPerId, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_PORTS, + AxiIdWidthSlvPorts: AxiIdWidthMasters, + AxiIdUsedSlvPorts: AxiIdUsed, + UniqueIds: 1'b0, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: NoAddrRules_0 + }; + + //localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2 = '{ + // '{idx: 32'd1 % NoSlvPorts_1, start_addr: {AddrWidth{1'b0}}, end_addr: {1'b0, {(AddrWidth-1){1'b1}}}}, + // '{idx: 32'd0 % NoSlvPorts_1, start_addr: {1'b0, {(AddrWidth-1){1'b1}}}, end_addr: {(AddrWidth){1'b1}}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + //}; + + localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp0 = '{ + '{idx: 32'd2 % NoSlvPorts_1, start_addr: {32'h0fffffff}, end_addr: {32'hffffffff}}, + '{idx: 32'd1 % NoSlvPorts_1, start_addr: {32'h0000ffff}, end_addr: {32'h0fffffff}}, + '{idx: 32'd0 % NoSlvPorts_1, start_addr: {32'b0}, end_addr: {32'h0000ffff}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp1 = '{ + '{idx: 32'd2 % NoSlvPorts_1, start_addr: {32'b0}, end_addr: {32'h0000ffff}}, + '{idx: 32'd1 % NoSlvPorts_1, start_addr: {32'h0000ffff}, end_addr: {32'h0fffffff}}, + '{idx: 32'd0 % NoSlvPorts_1, start_addr: {32'h0fffffff}, end_addr: {32'hffffffff}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp2 = '{ + '{idx: 32'd2 % NoSlvPorts_1, start_addr: {32'b0}, end_addr: {32'h0000ffff}}, + '{idx: 32'd1 % NoSlvPorts_1, start_addr: {32'h0fffffff}, end_addr: {32'hffffffff}}, + '{idx: 32'd0 % NoSlvPorts_1, start_addr: {32'h0000ffff}, end_addr: {32'h0fffffff}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + //localparam rule_t [xbar_cfg_0.NoAddrRules-1:0] AddrMap_xp0 = '{ + // '{idx: 32'd0 % NoSlvPorts_0, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + //}; + + typedef union packed { + logic [StrbWidth-1:0][7:0] bytes; + logic [DataWidth-1:0] data; + } block_t; + + /// Address Type + typedef logic [ AddrWidth-1:0] addr_t; + /// Data Type + typedef logic [ DataWidth-1:0] data_t; + /// Strobe Type + typedef logic [ StrbWidth-1:0] strb_t; + /// AXI ID Type + typedef logic [ IdWidth-1:0] axi_id_t; + /// AXI USER Type + typedef logic [ UserWidth-1:0] user_t; + /// 1D burst request + typedef struct packed { + axi_id_t id; + addr_t src, dst, num_bytes; + axi_pkg::cache_t cache_src, cache_dst; + axi_pkg::burst_t burst_src, burst_dst; + logic decouple_rw; + logic deburst; + logic serialize; + } burst_req_t; + + // master AXI bus --> DMA + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_dma_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_dma_t, axi_id_t, user_t) + + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_dma_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_dma_t, data_t, axi_id_t, user_t) + + `AXI_TYPEDEF_REQ_T(dma_req_t, aw_chan_dma_t, w_chan_t, ar_chan_dma_t) + `AXI_TYPEDEF_RESP_T(dma_resp_t, b_chan_dma_t, r_chan_dma_t) + + // slave AXI bus --> mem + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_mem_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_mem_t, axi_id_t, user_t) + + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_mem_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_mem_t, data_t, axi_id_t, user_t) + + `AXI_TYPEDEF_REQ_T(mem_req_t, aw_chan_mem_t, w_chan_t, ar_chan_mem_t) + `AXI_TYPEDEF_RESP_T(mem_resp_t, b_chan_mem_t, r_chan_mem_t) + + //-------------------------------------- + // Clock and Reset + //-------------------------------------- + logic clk; + initial begin + forever begin + clk = 0; + #HalfPeriod; + clk = 1; + #HalfPeriod; + end + end + + logic rst_n; + initial begin + rst_n = 0; + #Reset; + rst_n = 1; + end + + task wait_for_reset; + @(posedge rst_n); + @(posedge clk); + endtask + + //-------------------------------------- + // DUT Axi busses + //-------------------------------------- + + dma_req_t [NoMst-1:0] axi_dma_req; + dma_resp_t [NoMst-1:0] axi_dma_res; + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) dma [NoMst-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) dma_sync [NoMst-1:0] (); + + AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) dma_dv [NoMst-1:0] (clk); + + for (genvar i = 0; i < NoMst; i++) begin : gen_conn_dv_masters + //`AXI_ASSIGN (dma_dv[i], dma[i]) + `AXI_ASSIGN_FROM_REQ(dma[i], axi_dma_req[i]) + `AXI_ASSIGN_TO_RESP(axi_dma_res[i], dma[i]) + end + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_mst [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_mst_2 [0:0] (); + + `AXI_ASSIGN (mem_0[0], xp0_mst[0]) + `AXI_ASSIGN (xp0_mst_1[0], xp0_mst[1]) + `AXI_ASSIGN (xp0_mst_2[0], xp0_mst[2]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_slv_2 [0:0] (); + + `AXI_ASSIGN (xp0_slv[0], dma_sync[0]) + `AXI_ASSIGN (xp0_slv[1], xp0_slv_1[0]) + `AXI_ASSIGN (xp0_slv[2], xp0_slv_2[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_mst [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_mst_2 [0:0] (); + + `AXI_ASSIGN (mem_0[1], xp1_mst[0]) + `AXI_ASSIGN (xp1_mst_1[0], xp1_mst[1]) + `AXI_ASSIGN (xp1_mst_2[0], xp1_mst[2]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_slv_2 [0:0] (); + + `AXI_ASSIGN (xp1_slv[0], dma_sync[1]) + `AXI_ASSIGN (xp1_slv[1], xp1_slv_1[0]) + `AXI_ASSIGN (xp1_slv[2], xp1_slv_2[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_mst [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_mst_2 [0:0] (); + + `AXI_ASSIGN (mem_0[2], xp2_mst[0]) + `AXI_ASSIGN (xp2_mst_1[0], xp2_mst[1]) + `AXI_ASSIGN (xp2_mst_2[0], xp2_mst[2]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_slv_2 [0:0] (); + + `AXI_ASSIGN (xp2_slv[0], dma_sync[2]) + `AXI_ASSIGN (xp2_slv[1], xp2_slv_1[0]) + `AXI_ASSIGN (xp2_slv[2], xp2_slv_2[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_mst [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_mst_2 [0:0] (); + + `AXI_ASSIGN (mem_0[3], xp3_mst[0]) + `AXI_ASSIGN (xp3_mst_1[0], xp3_mst[1]) + `AXI_ASSIGN (xp3_mst_2[0], xp3_mst[2]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_slv_2 [0:0] (); + + `AXI_ASSIGN (xp3_slv[0], dma_sync[3]) + `AXI_ASSIGN (xp3_slv[1], xp3_slv_1[0]) + `AXI_ASSIGN (xp3_slv[2], xp3_slv_2[0]) + + // XP0 <--> XP1 + + `AXI_ASSIGN (xp1_slv_1[0], xp0_mst_1[0]) + `AXI_ASSIGN (xp0_slv_1[0], xp1_mst_1[0]) + + // XP0 <--> XP2 + + `AXI_ASSIGN (xp2_slv_2[0], xp0_mst_2[0]) + `AXI_ASSIGN (xp0_slv_2[0], xp2_mst_2[0]) + + // XP1 <--> XP3 + + `AXI_ASSIGN (xp1_slv_2[0], xp3_mst_2[0]) + `AXI_ASSIGN (xp3_slv_2[0], xp1_mst_2[0]) + + // XP2 <--> XP3 + + `AXI_ASSIGN (xp2_slv_1[0], xp3_mst_1[0]) + `AXI_ASSIGN (xp3_slv_1[0], xp2_mst_1[0]) + + AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) mem_dv [NoSlv-1:0] (clk); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) mem_0 [NoSlv-1:0] (); + + `AXI_ASSIGN (mem_dv[0], mem_0[0]) + `AXI_ASSIGN (mem_dv[1], mem_0[1]) + `AXI_ASSIGN (mem_dv[2], mem_0[2]) + `AXI_ASSIGN (mem_dv[3], mem_0[3]) + + //`AXI_ASSIGN (mem_dv[1], mem_1[0]) + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma1_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma2_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma3_t; + + driver_dma_t driver_dma = new(mem_dv[0]); + driver_dma1_t driver_dma1 = new(mem_dv[1]); + driver_dma2_t driver_dma2 = new(mem_dv[2]); + driver_dma3_t driver_dma3 = new(mem_dv[3]); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem0 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[0]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem1 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[1]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem2 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[2]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem3 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[3]) + ); + + // initial begin + // $readmemh("sim_mem0.mem", i_sim_mem0.mem); + // $readmemh("sim_mem1.mem", i_sim_mem1.mem); + // end + + //-------------------------------------- + // DUT AXI Memory System + //-------------------------------------- + // lfsr + logic [784:0] lfsr_dut_q, lfsr_dut_d; + + // transaction id + logic [ 7:0] transaction_id = 0; + + // Memory + block_t dma_memory [bit [AddrWidth-$clog2($bits(block_t))-1:0]]; + block_t dma_memory1 [bit [AddrWidth-$clog2($bits(block_t))-1:0]]; + + //-------------------------------------- + // DMA instantiation + //-------------------------------------- + burst_req_t burst0_req; + burst_req_t burst1_req; + logic burst0_req_valid; + logic burst1_req_valid; + logic burst0_req_ready; + logic burst1_req_ready; + logic backend_idle_0; + logic backend_idle_1; + burst_req_t burst2_req; + burst_req_t burst3_req; + logic burst2_req_valid; + logic burst3_req_valid; + logic burst2_req_ready; + logic burst3_req_ready; + logic backend_idle_2; + logic backend_idle_3; + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_0 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[0] ), + .axi_dma_res_i ( axi_dma_res[0] ), + .burst_req_i ( burst0_req ), + .valid_i ( burst0_req_valid ), + .ready_o ( burst0_req_ready ), + .backend_idle_o ( backend_idle_0 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000000 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_0 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[0] ), + .out ( dma_sync[0] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_1 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[1] ), + .axi_dma_res_i ( axi_dma_res[1] ), + .burst_req_i ( burst1_req ), + .valid_i ( burst1_req_valid ), + .ready_o ( burst1_req_ready ), + .backend_idle_o ( backend_idle_1 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000001 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_1 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[1] ), + .out ( dma_sync[1] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_2 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[2] ), + .axi_dma_res_i ( axi_dma_res[2] ), + .burst_req_i ( burst2_req ), + .valid_i ( burst2_req_valid ), + .ready_o ( burst2_req_ready ), + .backend_idle_o ( backend_idle_2 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000002 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_2 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[2] ), + .out ( dma_sync[2] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_3 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[3] ), + .axi_dma_res_i ( axi_dma_res[3] ), + .burst_req_i ( burst3_req ), + .valid_i ( burst3_req_valid ), + .ready_o ( burst3_req_ready ), + .backend_idle_o ( backend_idle_3 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000003 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_3 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[3] ), + .out ( dma_sync[3] ) + ); + + //----------------------------------- + // DUT + //----------------------------------- + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_3 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp3_slv ), + .mst_ports ( xp3_mst ), + .addr_map_i ( AddrMap_xp2 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_2 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp2_slv ), + .mst_ports ( xp2_mst ), + .addr_map_i ( AddrMap_xp1 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_1 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp1_slv ), + .mst_ports ( xp1_mst ), + .addr_map_i ( AddrMap_xp1 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_0 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp0_slv ), + .mst_ports ( xp0_mst ), + .addr_map_i ( AddrMap_xp0 ) + ); + //-------------------------------------- + // DMA DUT tasks + //-------------------------------------- + + task oned_dut_launch_3 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst3_req_valid <= 1'b0; + burst3_req <= '0; + @(posedge clk); + while (burst3_req_ready !== 1) @(posedge clk); + // write data + burst3_req.id <= transf_id_i; + burst3_req.src <= src_addr_i; + burst3_req.dst <= dst_addr_i; + burst3_req.num_bytes <= num_bytes_i; + burst3_req.cache_src <= src_cache_i; + burst3_req.cache_dst <= dst_cache_i; + burst3_req.burst_src <= src_burst_i; + burst3_req.burst_dst <= dst_burst_i; + burst3_req.decouple_rw <= decouple_rw_i; + burst3_req.deburst <= deburst_i; + burst3_req.serialize <= serialize_i; + burst3_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst3_req_valid <= 1'b0; + burst3_req <= '0; + endtask + + task oned_dut_launch_2 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst2_req_valid <= 1'b0; + burst2_req <= '0; + @(posedge clk); + while (burst2_req_ready !== 1) @(posedge clk); + // write data + burst2_req.id <= transf_id_i; + burst2_req.src <= src_addr_i; + burst2_req.dst <= dst_addr_i; + burst2_req.num_bytes <= num_bytes_i; + burst2_req.cache_src <= src_cache_i; + burst2_req.cache_dst <= dst_cache_i; + burst2_req.burst_src <= src_burst_i; + burst2_req.burst_dst <= dst_burst_i; + burst2_req.decouple_rw <= decouple_rw_i; + burst2_req.deburst <= deburst_i; + burst2_req.serialize <= serialize_i; + burst2_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst2_req_valid <= 1'b0; + burst2_req <= '0; + endtask + + task oned_dut_launch_1 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst1_req_valid <= 1'b0; + burst1_req <= '0; + @(posedge clk); + while (burst1_req_ready !== 1) @(posedge clk); + // write data + burst1_req.id <= transf_id_i; + burst1_req.src <= src_addr_i; + burst1_req.dst <= dst_addr_i; + burst1_req.num_bytes <= num_bytes_i; + burst1_req.cache_src <= src_cache_i; + burst1_req.cache_dst <= dst_cache_i; + burst1_req.burst_src <= src_burst_i; + burst1_req.burst_dst <= dst_burst_i; + burst1_req.decouple_rw <= decouple_rw_i; + burst1_req.deburst <= deburst_i; + burst1_req.serialize <= serialize_i; + burst1_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst1_req_valid <= 1'b0; + burst1_req <= '0; + endtask + + task oned_dut_launch_0 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst0_req_valid <= 1'b0; + burst0_req <= '0; + @(posedge clk); + while (burst0_req_ready !== 1) @(posedge clk); + // write data + burst0_req.id <= transf_id_i; + burst0_req.src <= src_addr_i; + burst0_req.dst <= dst_addr_i; + burst0_req.num_bytes <= num_bytes_i; + burst0_req.cache_src <= src_cache_i; + burst0_req.cache_dst <= dst_cache_i; + burst0_req.burst_src <= src_burst_i; + burst0_req.burst_dst <= dst_burst_i; + burst0_req.decouple_rw <= decouple_rw_i; + burst0_req.deburst <= deburst_i; + burst0_req.serialize <= serialize_i; + burst0_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst0_req_valid <= 1'b0; + burst0_req <= '0; + endtask + + task oned_reset (); + burst0_req_valid <= 1'b0; + burst0_req <= '0; + burst1_req_valid <= 1'b0; + burst1_req <= '0; + burst2_req_valid <= 1'b0; + burst2_req <= '0; + burst3_req_valid <= 1'b0; + burst3_req <= '0; + endtask + + task wait_for_dut_completion (); + repeat(10) @(posedge clk); + while (backend_idle_0 === 0) @(posedge clk); + while (backend_idle_1 === 0) @(posedge clk); + while (backend_idle_2 === 0) @(posedge clk); + while (backend_idle_3 === 0) @(posedge clk); + repeat(50) @(posedge clk); + endtask + + task clear_dut_memory (); + dma_memory.delete(); + dma_memory1.delete(); + endtask + + task reset_dut_lfsr (); + lfsr_dut_q <= 'hc0a232c162b2bab5b960668030f4efce27940bd0de965f0b8d4315f15b79704195e4e0a6b495fc269f65ae17e10e9ca98510fc143327a292b418597f9dd175fc91c3d61be287d5462a23e00fa7ae906ae9eb339ab5225021356138cd46b6e5a73540c5591116b6b5e08d2c0e54eaf0d5143b33b2186b6cf841c076a98c412a63981f0e323dce93481ed1c37e4f1d7553b6c2fba1a3af6c3ad88b15ad58812ba07d1753917ac4e6ab1e8c4f67a47b4b0f48a34f42a52c546e979f4e4968e80a732a0a5e7a51146cf08482f349f94336752b765c0b1d70803d883d5058d127264335213da4163c62f65a4e65501b90fa5f177675c0747cfca328e131bfb3f7bcc5c27680c7bf86491f4ed3d36c25531edfa74b1e32fafe426958ae356eb8ef0fd818eaca4227a667b7c934ebfa282ab6bfc6db89b927c91a41e63a9554dced774f30268d0725a1a565368703b9f81d5c027ba196ef8b803a51c639c7ead834e1d6bc537d33800fe5eb12f1ed67758f1dfe85ffdbae56e8ef27f2ecedcee75b8dbb5f5f1a629ba3b755; + endtask + + //-------------------------------------- + // Osmium Model + //-------------------------------------- + // Memory + block_t osmium_memory [bit [AddrWidth-$clog2($bits(block_t))-1:0]]; + // lfsr + logic [784:0] lfsr_osmium_q,lfsr_osmium_d; + + task oned_osmium_launch ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i + ); + logic [AddrWidth-1:0] read_addr, write_addr; + logic [AddrWidth-1:0] read_word, write_word; + logic [$clog2(AddrWidth):0] read_offset, write_offset; + // perform the transfer + for(int i = 0; i < num_bytes_i; i = i + 1) begin + read_addr = src_addr_i + i; + write_addr = dst_addr_i + i; + read_word = src_burst_i == 2'b00 ? src_addr_i >> $clog2(AddrWidth) : read_addr >> $clog2(AddrWidth); + write_word = dst_burst_i == 2'b00 ? dst_addr_i >> $clog2(AddrWidth) : write_addr >> $clog2(AddrWidth); + read_offset = read_addr [$clog2(AddrWidth)-1:0]; + write_offset = write_addr[$clog2(AddrWidth)-1:0]; + + // do the read + if (!osmium_memory.exists(read_word) === 1) begin + osmium_memory[read_word].data = lfsr_osmium_q[784:273]; + //shift 513x + repeat(513) begin + // next state + for (int i = 1; i < 785; i = i +1) lfsr_osmium_d[i-1] = lfsr_osmium_q[i]; + lfsr_osmium_d[784] = lfsr_osmium_q[0]; + lfsr_osmium_d[692] = lfsr_osmium_q[0] ^ lfsr_osmium_q[693]; + lfsr_osmium_q = lfsr_osmium_d; + end + end + // do the write + osmium_memory[write_word].bytes[write_offset] = osmium_memory[read_word].bytes[read_offset]; + // $display("W: %d - %d R: %d - %d", write_word, write_offset, read_word, read_offset); + end + + endtask + + task clear_osmium_memory (); + osmium_memory.delete(); + endtask + + task reset_osmium_lfsr (); + lfsr_osmium_q = 'hc0a232c162b2bab5b960668030f4efce27940bd0de965f0b8d4315f15b79704195e4e0a6b495fc269f65ae17e10e9ca98510fc143327a292b418597f9dd175fc91c3d61be287d5462a23e00fa7ae906ae9eb339ab5225021356138cd46b6e5a73540c5591116b6b5e08d2c0e54eaf0d5143b33b2186b6cf841c076a98c412a63981f0e323dce93481ed1c37e4f1d7553b6c2fba1a3af6c3ad88b15ad58812ba07d1753917ac4e6ab1e8c4f67a47b4b0f48a34f42a52c546e979f4e4968e80a732a0a5e7a51146cf08482f349f94336752b765c0b1d70803d883d5058d127264335213da4163c62f65a4e65501b90fa5f177675c0747cfca328e131bfb3f7bcc5c27680c7bf86491f4ed3d36c25531edfa74b1e32fafe426958ae356eb8ef0fd818eaca4227a667b7c934ebfa282ab6bfc6db89b927c91a41e63a9554dced774f30268d0725a1a565368703b9f81d5c027ba196ef8b803a51c639c7ead834e1d6bc537d33800fe5eb12f1ed67758f1dfe85ffdbae56e8ef27f2ecedcee75b8dbb5f5f1a629ba3b755; + endtask + + //-------------------------------------- + // Compare Memory content + //-------------------------------------- + task compare_memories (); + + // go through osmium memory and compare contents + foreach(osmium_memory[i]) begin + if (osmium_memory[i] !== dma_memory[i]) $fatal("Memory mismatch @ %x\nexpect: %x\ngot :%x\n", i << $clog2(AddrWidth), osmium_memory[i], dma_memory[i]); + end + // go through dma memory and compare contents + foreach(dma_memory[i]) begin + if (osmium_memory[i] !== dma_memory[i]) $fatal("Memory mismatch @ %x\nexpect: %x\ngot :%x\n", i << $clog2(AddrWidth), osmium_memory[i], dma_memory[i]); + end + + // it worked :P + $display(" - :D"); + + endtask + + //-------------------------------------- + // Master tasks + //-------------------------------------- + + task clear_memory (); + clear_dut_memory(); + clear_osmium_memory(); + endtask + + task reset_lfsr (); + reset_dut_lfsr(); + reset_osmium_lfsr(); + endtask + + task oned_launch_3 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma3_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_3(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_2 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma2_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_2(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_1 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma1_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_1(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_0 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma0_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_0(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task reset (); + int my_file; + oned_reset(); + wait_for_reset(); + // clear trace file + my_file = $fopen("dma_transfers.txt", "w"); + $fwrite(my_file, "Transfers launched:\n"); + $fclose(my_file); + endtask + + task oned_random_launch( + input logic [15:0] max_len, + input logic [31:0] src_add, + input logic [31:0] dst_add, + input logic [15:0] master_id, + input logic [15:0] size, + input logic wait_for_completion + ); + + logic [ IdWidth-1:0] transf_id_0; + logic [ AddrWidth-1:0] src_addr_0, dst_addr_0, num_bytes_0; + logic [ IdWidth-1:0] transf_id_1; + logic [ AddrWidth-1:0] src_addr_1, dst_addr_1, num_bytes_1; + logic [ IdWidth-1:0] transf_id_2; + logic [ AddrWidth-1:0] src_addr_2, dst_addr_2, num_bytes_2; + logic [ IdWidth-1:0] transf_id_3; + logic [ AddrWidth-1:0] src_addr_3, dst_addr_3, num_bytes_3; + logic decouple_rw; + logic deburst; + logic serialize; + + decouple_rw = 0;//$urandom(); + deburst = 0;//$urandom(); + serialize = 0;//$urandom(); + + if (master_id == 0) begin + transf_id_0 = 0;//$urandom(); + // transf_id = transaction_id; + //src_addr_0[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //src_addr_0[(AddrWidth/2)-1: 0] = $urandom(); + //dst_addr_0[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //dst_addr_0[(AddrWidth/2)-1: 0] = $urandom(); + num_bytes_0 = 0; + num_bytes_0[15: 0] = size; + src_addr_0 = src_add; + dst_addr_0 = dst_add; + + oned_launch_0(transf_id_0, src_addr_0, dst_addr_0, num_bytes_0, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 1) begin + transf_id_1 = 1;//$urandom(); + // transf_id = transaction_id; + //src_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //src_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + //dst_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //dst_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + num_bytes_1 = 0; + num_bytes_1[15: 0] = size; + src_addr_1 = src_add; + dst_addr_1 = dst_add; + + oned_launch_1(transf_id_1, src_addr_1, dst_addr_1, num_bytes_1, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 2) begin + transf_id_2 = 2;//$urandom(); + // transf_id = transaction_id; + //src_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //src_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + //dst_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //dst_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + num_bytes_2 = 0; + num_bytes_2[15: 0] = size; + src_addr_2 = src_add; + dst_addr_2 = dst_add; + + oned_launch_2(transf_id_2, src_addr_2, dst_addr_2, num_bytes_2, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 3) begin + transf_id_3 = 3;//$urandom(); + // transf_id = transaction_id; + //src_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //src_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + //dst_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + //dst_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + num_bytes_3 = 0; + num_bytes_3[15: 0] = size; + src_addr_3 = src_add; + dst_addr_3 = dst_add; + + oned_launch_3(transf_id_3, src_addr_3, dst_addr_3, num_bytes_3, decouple_rw, deburst, serialize, wait_for_completion); + + end + + // transaction_id = transaction_id + 1; + + + endtask + +endmodule : fixture_axi_dma_backend diff --git a/test/fixture_axi_dma_backend_2x2mesh.sv b/test/fixture_axi_dma_backend_2x2mesh.sv new file mode 100644 index 000000000..0409e1257 --- /dev/null +++ b/test/fixture_axi_dma_backend_2x2mesh.sv @@ -0,0 +1,940 @@ +// Copyright (c) 2019 ETH Zurich, University of Bologna +// All rights reserved. +// +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// +// Thomas Benz + +// fixture for the AXi DMA backend +// the fixture instantiates the DMA backend, a golden model of the backend , and tasks controlling +// both. + +`timescale 1ns/1ns +module fixture_axi_dma_backend(); + + // `include "../axi/include/axi/assign.svh" + `define MEM_DEBUG 1 + `include "axi/assign.svh" + `include "axi/typedef.svh" + + //-------------------------------------- + // Parameters + //-------------------------------------- + localparam TA = 0.2ns; // must be nonzero to avoid Snitch load fifo double pop glitch + localparam TT = 0.8ns; + localparam HalfPeriod = 50ns; + localparam Reset = 75ns; + + localparam DataWidth = 512; + localparam AddrWidth = 64; + localparam StrbWidth = DataWidth / 8; + localparam IdWidth = 6; + localparam UserWidth = 1; + + // DUT parameters + localparam bit ATOPs = 0; + localparam int unsigned NoSlvPorts_1 = 2; + localparam int unsigned NoMstPorts_1 = 1; + localparam int unsigned NoSlvPorts_0 = 1; + localparam int unsigned NoMstPorts_0 = 1; + localparam bit [NoSlvPorts_1-1:0][NoMstPorts_1-1:0] Connectivity_1 = '1; + localparam bit [NoSlvPorts_0-1:0][NoMstPorts_0-1:0] Connectivity_0 = '1; + localparam int unsigned AxiSlvPortMaxUniqIds = 32'd16; + localparam int unsigned AxiSlvPortMaxTxnsPerId = 32'd128; + localparam int unsigned AxiSlvPortMaxTxns = 32'd31; + localparam int unsigned AxiMstPortMaxUniqIds = 32'd4; + localparam int unsigned AxiMstPortMaxTxnsPerId = 32'd7; + localparam int unsigned NoAddrRules_1 = 32'd2; + localparam int unsigned NoAddrRules_0 = 32'd1; + + typedef axi_pkg::xbar_rule_64_t rule_t; // Has to be the same width as axi addr + + // axi configuration + localparam int unsigned AxiIdWidthMasters = IdWidth; + localparam int unsigned AxiIdUsed = IdWidth-1; // Has to be <= AxiIdWidthMasters + localparam int unsigned AxiIdWidthSlaves = AxiIdWidthMasters + $clog2(NoMstPorts_0); + localparam int unsigned AxiAddrWidth = AddrWidth; // Axi Address Width + localparam int unsigned AxiDataWidth = DataWidth; // Axi Data Width + localparam int unsigned AxiStrbWidth = StrbWidth; + localparam int unsigned AxiUserWidth = UserWidth; + localparam int unsigned AxiIdWidth = IdWidth; + // in the bench can change this variables which are set here freely + localparam axi_pkg::xbar_cfg_t xbar_cfg_2 = '{ + NoSlvPorts: NoMstPorts_1, + NoMstPorts: NoSlvPorts_1, + MaxMstTrans: AxiSlvPortMaxTxns, + MaxSlvTrans: AxiSlvPortMaxTxnsPerId, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_AX, + AxiIdWidthSlvPorts: AxiIdWidthMasters, + AxiIdUsedSlvPorts: AxiIdUsed, + UniqueIds: 1'b0, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: NoAddrRules_1 + }; + + localparam axi_pkg::xbar_cfg_t xbar_cfg_1 = '{ + NoSlvPorts: NoMstPorts_1, + NoMstPorts: NoSlvPorts_1, + MaxMstTrans: AxiSlvPortMaxTxns, + MaxSlvTrans: AxiSlvPortMaxTxnsPerId, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_AX, + AxiIdWidthSlvPorts: AxiIdWidthMasters, + AxiIdUsedSlvPorts: AxiIdUsed, + UniqueIds: 1'b0, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: NoAddrRules_1 + }; + + localparam axi_pkg::xbar_cfg_t xbar_cfg_0 = '{ + NoSlvPorts: NoMstPorts_0, + NoMstPorts: NoSlvPorts_0, + MaxMstTrans: AxiSlvPortMaxTxns, + MaxSlvTrans: AxiSlvPortMaxTxnsPerId, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_AX, + AxiIdWidthSlvPorts: AxiIdWidthMasters, + AxiIdUsedSlvPorts: AxiIdUsed, + UniqueIds: 1'b0, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: NoAddrRules_0 + }; + + localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2 = '{ + '{idx: 32'd1 % NoSlvPorts_1, start_addr: {AddrWidth{1'b0}}, end_addr: {1'b0, {(AddrWidth-1){1'b1}}}}, + '{idx: 32'd0 % NoSlvPorts_1, start_addr: {1'b0, {(AddrWidth-1){1'b1}}}, end_addr: {(AddrWidth){1'b1}}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp1 = '{ + '{idx: 32'd1 % NoSlvPorts_1, start_addr: {1'b0, {(AddrWidth-1){1'b1}}}, end_addr: {(AddrWidth){1'b1}}}, + '{idx: 32'd0 % NoSlvPorts_1, start_addr: {AddrWidth{1'b0}}, end_addr: {1'b0, {(AddrWidth-1){1'b1}}}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_0.NoAddrRules-1:0] AddrMap_xp0 = '{ + '{idx: 32'd0 % NoSlvPorts_0, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + typedef union packed { + logic [StrbWidth-1:0][7:0] bytes; + logic [DataWidth-1:0] data; + } block_t; + + /// Address Type + typedef logic [ AddrWidth-1:0] addr_t; + /// Data Type + typedef logic [ DataWidth-1:0] data_t; + /// Strobe Type + typedef logic [ StrbWidth-1:0] strb_t; + /// AXI ID Type + typedef logic [ IdWidth-1:0] axi_id_t; + /// AXI USER Type + typedef logic [ UserWidth-1:0] user_t; + /// 1D burst request + typedef struct packed { + axi_id_t id; + addr_t src, dst, num_bytes; + axi_pkg::cache_t cache_src, cache_dst; + axi_pkg::burst_t burst_src, burst_dst; + logic decouple_rw; + logic deburst; + logic serialize; + } burst_req_t; + + // master AXI bus --> DMA + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_dma_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_dma_t, axi_id_t, user_t) + + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_dma_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_dma_t, data_t, axi_id_t, user_t) + + `AXI_TYPEDEF_REQ_T(dma_req_t, aw_chan_dma_t, w_chan_t, ar_chan_dma_t) + `AXI_TYPEDEF_RESP_T(dma_resp_t, b_chan_dma_t, r_chan_dma_t) + + // slave AXI bus --> mem + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_mem_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_mem_t, axi_id_t, user_t) + + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_mem_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_mem_t, data_t, axi_id_t, user_t) + + `AXI_TYPEDEF_REQ_T(mem_req_t, aw_chan_mem_t, w_chan_t, ar_chan_mem_t) + `AXI_TYPEDEF_RESP_T(mem_resp_t, b_chan_mem_t, r_chan_mem_t) + + //-------------------------------------- + // Clock and Reset + //-------------------------------------- + logic clk; + initial begin + forever begin + clk = 0; + #HalfPeriod; + clk = 1; + #HalfPeriod; + end + end + + logic rst_n; + initial begin + rst_n = 0; + #Reset; + rst_n = 1; + end + + task wait_for_reset; + @(posedge rst_n); + @(posedge clk); + endtask + + //-------------------------------------- + // DUT Axi busses + //-------------------------------------- + dma_req_t [NoMstPorts_0-1:0] axi_dma_req; + dma_resp_t [NoMstPorts_0-1:0] axi_dma_res; + + //dma_req_t [NoMstPorts-1:0] axi_dma_sync_req; + //dma_resp_t [NoMstPorts-1:0] axi_dma_sync_res; + + mem_req_t [NoSlvPorts_1-1:0] axi_mem_req; + mem_resp_t [NoSlvPorts_1-1:0] axi_mem_res; + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) dma [NoMstPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) dma_sync [NoMstPorts_0-1:0] (); + + AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) dma_dv [NoMstPorts_0-1:0] (clk); + + for (genvar i = 0; i < NoMstPorts_0; i++) begin : gen_conn_dv_masters + //`AXI_ASSIGN (dma_dv[i], dma[i]) + `AXI_ASSIGN_FROM_REQ(dma[i], axi_dma_req[i]) + `AXI_ASSIGN_TO_RESP(axi_dma_res[i], dma[i]) + end + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_slv_0 [NoSlvPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_slv_1 [NoSlvPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_slv [NoSlvPorts_0-1:0] (); + + `AXI_ASSIGN (xp0_slv_0[0], xp0_slv[0]) + `AXI_ASSIGN (xp0_slv_1[0], xp0_slv[1]) + + AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) mem_dv [NoSlvPorts_1-1:0] (clk); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) mem_0 [NoSlvPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) mem_1 [NoSlvPorts_0-1:0] (); + + for (genvar i = 0; i < NoSlvPorts_1; i++) begin : gen_conn_dv_slaves + //`AXI_ASSIGN (mem_dv[i], mem[i]) + `AXI_ASSIGN_TO_REQ(axi_mem_req[i], mem_dv[i]) + `AXI_ASSIGN_TO_RESP(axi_mem_res[i], mem_dv[i]) + end + + `AXI_ASSIGN (mem_dv[0], mem_0[0]) + `AXI_ASSIGN (mem_dv[1], mem_1[0]) + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma1_t; + + driver_dma_t driver_dma = new(mem_dv[0]); + driver_dma1_t driver_dma1 = new(mem_dv[1]); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem0 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[0]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem1 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[1]) + ); + + // initial begin + // $readmemh("sim_mem0.mem", i_sim_mem0.mem); + // $readmemh("sim_mem1.mem", i_sim_mem1.mem); + // end + + //-------------------------------------- + // DUT AXI Memory System + //-------------------------------------- + // lfsr + logic [784:0] lfsr_dut_q, lfsr_dut_d; + + // transaction id + logic [ 7:0] transaction_id = 0; + + // Memory + block_t dma_memory [bit [AddrWidth-$clog2($bits(block_t))-1:0]]; + block_t dma_memory1 [bit [AddrWidth-$clog2($bits(block_t))-1:0]]; + + // Handle the data output from dma. Model of the memory acting as AXI slave. +// typedef axi_test::axi_driver #(.AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(1), .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod)) driver_dma_t; +// typedef axi_test::axi_driver #(.AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(1), .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod)) driver_dma1_t; +// driver_dma_t driver_dma = new(mem_dv[0]); +// driver_dma_t driver_dma1 = new(mem_dv[1]); +// initial begin +// automatic driver_dma_t::ax_beat_t aw_dma_queue[$], ar_dma_queue[$]; +// automatic driver_dma_t::b_beat_t b_dma_queue[$]; + +// automatic driver_dma1_t::ax_beat_t aw_dma1_queue[$], ar_dma1_queue[$]; +// automatic driver_dma1_t::b_beat_t b_dma1_queue[$]; +// automatic string sb = ""; + +// event ar_dma_received, aw_dma_received, b_dma_ready; +// event ar_dma1_received, aw_dma1_received, b_dma1_ready; +// event lfsr_dut_read; +// event lfsr_dut_read_completed; + +// driver_dma.reset_slave(); +// driver_dma1.reset_slave(); +// @(posedge rst_n); +// $display("AXI reset done"); + +// fork +// // AW mem 0 +// forever begin +// automatic driver_dma_t::ax_beat_t dma_tx; +// driver_dma.recv_aw(dma_tx); +// `ifdef MEM_DEBUG +// $display("Mem0: %d: AW - id: %4d - addr: %d - len: %4d - size: %4d - burst: %b", +// $time(), dma_tx.ax_id, dma_tx.ax_addr, dma_tx.ax_len, dma_tx.ax_size, dma_tx.ax_burst ); +// `endif +// aw_dma_queue.push_back(dma_tx); +// -> aw_dma_received; +// end +// // AW mem 1 +// forever begin +// automatic driver_dma1_t::ax_beat_t dma1_tx; +// driver_dma1.recv_aw(dma1_tx); +// `ifdef MEM_DEBUG +// $display("Mem1: %d: AW - id: %4d - addr: %d - len: %4d - size: %4d - burst: %b", +// $time(), dma1_tx.ax_id, dma1_tx.ax_addr, dma1_tx.ax_len, dma1_tx.ax_size, dma1_tx.ax_burst ); +// `endif +// aw_dma1_queue.push_back(dma1_tx); +// -> aw_dma1_received; +// end +// // AR mem 0 +// forever begin +// automatic driver_dma_t::ax_beat_t dma_tx; +// driver_dma.recv_ar(dma_tx); +// `ifdef MEM_DEBUG +// $display("Mem0: %d: AR - id: %4d - addr: %d - len: %4d - size: %4d - burst: %b", +// $time(), dma_tx.ax_id, dma_tx.ax_addr, dma_tx.ax_len, dma_tx.ax_size, dma_tx.ax_burst ); +// `endif +// ar_dma_queue.push_back(dma_tx); +// -> ar_dma_received; +// end +// // AR mem 1 +// forever begin +// automatic driver_dma1_t::ax_beat_t dma1_tx; +// driver_dma1.recv_ar(dma1_tx); +// `ifdef MEM_DEBUG +// $display("Mem1: %d: AR - id: %4d - addr: %d - len: %4d - size: %4d - burst: %b", +// $time(), dma1_tx.ax_id, dma1_tx.ax_addr, dma1_tx.ax_len, dma1_tx.ax_size, dma1_tx.ax_burst ); +// `endif +// ar_dma1_queue.push_back(dma1_tx); +// -> ar_dma1_received; +// end +// // R mem 0 +// forever begin +// automatic driver_dma_t::r_beat_t dma_tx = new(); +// automatic driver_dma_t::ax_beat_t dma_ax; +// automatic bit [AddrWidth-1:0] word; +// while (ar_dma_queue.size() == 0) @ar_dma_received; +// dma_ax = ar_dma_queue[0]; +// word = dma_ax.ax_addr >> $clog2(AddrWidth); +// dma_tx.r_id = dma_ax.ax_id; +// // if (!dma_memory.exists(word)) begin +// // dma_memory[word].data = lfsr_dut_q[784:273]; +// // //shift 513x +// // repeat(513) begin +// // // next state +// // for (int i = 1; i < 785; i = i +1) lfsr_dut_d[i-1] = lfsr_dut_q[i]; +// // lfsr_dut_d[784] = lfsr_dut_q[0]; +// // lfsr_dut_d[692] = lfsr_dut_q[0] ^ lfsr_dut_q[693]; +// // lfsr_dut_q = lfsr_dut_d; +// // end +// // end +// // dma_tx.r_data = dma_memory[word].data; +// dma_tx.r_resp = axi_pkg::RESP_OKAY; +// dma_tx.r_last = (dma_ax.ax_len == 0); +// `ifdef MEM_DEBUG +// $display("Mem0: %d: R - id: %4d - data: %x - resp: %x - last: %b (0x%x)", +// $time(), dma_tx.r_id, dma_tx.r_data, dma_tx.r_resp, dma_tx.r_last, word << $clog2(AddrWidth)); +// `endif +// dma_ax.ax_addr >>= dma_ax.ax_size; +// dma_ax.ax_addr += (dma_ax.ax_burst !== 0); +// dma_ax.ax_addr <<= dma_ax.ax_size; +// dma_ax.ax_len -= 1; +// if (dma_tx.r_last) begin +// ar_dma_queue.pop_front(); +// end +// driver_dma.send_r(dma_tx); +// end +// // R mem 1 +// forever begin +// automatic driver_dma1_t::r_beat_t dma1_tx = new(); +// automatic driver_dma1_t::ax_beat_t dma1_ax; +// automatic bit [AddrWidth-1:0] word; +// while (ar_dma1_queue.size() == 0) @ar_dma1_received; +// dma1_ax = ar_dma1_queue[0]; +// word = dma1_ax.ax_addr >> $clog2(AddrWidth); +// dma1_tx.r_id = dma1_ax.ax_id; +// // if (!dma_memory1.exists(word)) begin +// // dma_memory1[word].data = lfsr_dut_q[784:273]; +// // //shift 513x +// // repeat(513) begin +// // // next state +// // for (int i = 1; i < 785; i = i +1) lfsr_dut_d[i-1] = lfsr_dut_q[i]; +// // lfsr_dut_d[784] = lfsr_dut_q[0]; +// // lfsr_dut_d[692] = lfsr_dut_q[0] ^ lfsr_dut_q[693]; +// // lfsr_dut_q = lfsr_dut_d; +// // end +// // end +// // dma1_tx.r_data = dma_memory1[word].data; +// dma1_tx.r_resp = axi_pkg::RESP_OKAY; +// dma1_tx.r_last = (dma1_ax.ax_len == 0); +// `ifdef MEM_DEBUG +// $display("Mem1: %d: R - id: %4d - data: %x - resp: %x - last: %b (0x%x)", +// $time(), dma1_tx.r_id, dma1_tx.r_data, dma1_tx.r_resp, dma1_tx.r_last, word << $clog2(AddrWidth)); +// `endif +// dma1_ax.ax_addr >>= dma1_ax.ax_size; +// dma1_ax.ax_addr += (dma1_ax.ax_burst !== 0); +// dma1_ax.ax_addr <<= dma1_ax.ax_size; +// dma1_ax.ax_len -= 1; +// if (dma1_tx.r_last) begin +// ar_dma1_queue.pop_front(); +// end +// driver_dma1.send_r(dma1_tx); +// end +// // W mem 0 +// forever begin +// automatic driver_dma_t::w_beat_t dma_tx; +// automatic driver_dma_t::ax_beat_t dma_ax; +// automatic bit [AddrWidth-1:0] word; +// driver_dma.recv_w(dma_tx); +// while (aw_dma_queue.size() == 0) @ar_dma_received; +// dma_ax = aw_dma_queue[0]; +// word = dma_ax.ax_addr >> $clog2(AddrWidth); +// //$display("Ready to write"); +// //$display("%x", word); +// // for (int i = 0; i < StrbWidth; i++) begin +// // if (dma_tx.w_strb[i]) begin +// // dma_memory[word].bytes[i] = dma_tx.w_data[i*8+:8]; +// // end +// // end +// `ifdef MEM_DEBUG +// $display("Mem0: %d: W - data: %x - strb: %x - last: %b (0x%x)", +// $time(), dma_tx.w_data, dma_tx.w_strb, dma_tx.w_last, word << $clog2(AddrWidth)); +// `endif +// dma_ax.ax_addr >>= dma_ax.ax_size; +// dma_ax.ax_addr += (dma_ax.ax_burst !== 0); +// dma_ax.ax_addr <<= dma_ax.ax_size; +// dma_ax.ax_len -= 1; +// if (dma_tx.w_last) begin +// automatic driver_dma_t::b_beat_t dma_tx = new(); +// dma_tx.b_id = dma_ax.ax_id; +// dma_tx.b_user = dma_ax.ax_user; +// aw_dma_queue.pop_front(); +// b_dma_queue.push_back(dma_tx); +// -> b_dma_ready; +// end +// end +// // W mem 1 +// forever begin +// automatic driver_dma1_t::w_beat_t dma1_tx; +// automatic driver_dma1_t::ax_beat_t dma1_ax; +// automatic bit [AddrWidth-1:0] word; +// driver_dma1.recv_w(dma1_tx); +// while (aw_dma1_queue.size() == 0) @ar_dma1_received; +// dma1_ax = aw_dma1_queue[0]; +// word = dma1_ax.ax_addr >> $clog2(AddrWidth); +// //$display("Ready to write"); +// //$display("%x", word); +// // for (int i = 0; i < StrbWidth; i++) begin +// // if (dma1_tx.w_strb[i]) begin +// // dma_memory1[word].bytes[i] = dma1_tx.w_data[i*8+:8]; +// // end +// // end +// `ifdef MEM_DEBUG +// $display("Mem1: %d: W - data: %x - strb: %x - last: %b (0x%x)", +// $time(), dma1_tx.w_data, dma1_tx.w_strb, dma1_tx.w_last, word << $clog2(AddrWidth)); +// `endif +// dma1_ax.ax_addr >>= dma1_ax.ax_size; +// dma1_ax.ax_addr += (dma1_ax.ax_burst !== 0); +// dma1_ax.ax_addr <<= dma1_ax.ax_size; +// dma1_ax.ax_len -= 1; +// if (dma1_tx.w_last) begin +// automatic driver_dma1_t::b_beat_t dma1_tx = new(); +// dma1_tx.b_id = dma1_ax.ax_id; +// dma1_tx.b_user = dma1_ax.ax_user; +// aw_dma1_queue.pop_front(); +// b_dma1_queue.push_back(dma1_tx); +// -> b_dma1_ready; +// end +// end +// // B mem 0 +// forever begin +// automatic driver_dma_t::b_beat_t dma_tx; +// while (b_dma_queue.size() == 0) @b_dma_ready; +// driver_dma.send_b(b_dma_queue[0]); +// b_dma_queue.pop_front(); +// end +// // B mem 1 +// forever begin +// automatic driver_dma1_t::b_beat_t dma1_tx; +// while (b_dma1_queue.size() == 0) @b_dma1_ready; +// driver_dma1.send_b(b_dma1_queue[0]); +// b_dma1_queue.pop_front(); +// end +// join_any +// end + + //-------------------------------------- + // DMA instantiation + //-------------------------------------- + burst_req_t burst_req; + logic burst_req_valid; + logic burst_req_ready; + logic backend_idle; + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[0] ), + .axi_dma_res_i ( axi_dma_res[0] ), + .burst_req_i ( burst_req ), + .valid_i ( burst_req_valid ), + .ready_o ( burst_req_ready ), + .backend_idle_o ( backend_idle ), + .trans_complete_o ( ), + .dma_id_i ( '0 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[0] ), + .out ( dma_sync[0] ) + ); + + //----------------------------------- + // DUT + //----------------------------------- + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_0 ), + .NoSlvPorts ( xbar_cfg_0.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_0.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_0.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_3 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp1_slv ), + .mst_ports ( mem_0 ), + .addr_map_i ( AddrMap_xp0 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_0 ), + .NoSlvPorts ( xbar_cfg_0.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_0.NoMstPorts ), + .Connectivity ( Connectivity_0 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_0.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_2 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp0_slv_1 ), + .mst_ports ( mem_1 ), + .addr_map_i ( AddrMap_xp0 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_0 ), + .NoSlvPorts ( xbar_cfg_0.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_0.NoMstPorts ), + .Connectivity ( Connectivity_0 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_0.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_1 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp0_slv_0 ), + .mst_ports ( xp1_slv ), + .addr_map_i ( AddrMap_xp0 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_0 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( dma_sync ), + .mst_ports ( xp0_slv ), + .addr_map_i ( AddrMap_xp1 ) + ); + + //-------------------------------------- + // DMA DUT tasks + //-------------------------------------- + task oned_dut_launch ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst_req_valid <= 1'b0; + burst_req <= '0; + @(posedge clk); + while (burst_req_ready !== 1) @(posedge clk); + // write data + burst_req.id <= transf_id_i; + burst_req.src <= src_addr_i; + burst_req.dst <= dst_addr_i; + burst_req.num_bytes <= num_bytes_i; + burst_req.cache_src <= src_cache_i; + burst_req.cache_dst <= dst_cache_i; + burst_req.burst_src <= src_burst_i; + burst_req.burst_dst <= dst_burst_i; + burst_req.decouple_rw <= decouple_rw_i; + burst_req.deburst <= deburst_i; + burst_req.serialize <= serialize_i; + burst_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst_req_valid <= 1'b0; + burst_req <= '0; + endtask + + task oned_reset (); + burst_req_valid <= 1'b0; + burst_req <= '0; + endtask + + task wait_for_dut_completion (); + repeat(10) @(posedge clk); + while (backend_idle === 0) @(posedge clk); + repeat(50) @(posedge clk); + endtask + + task clear_dut_memory (); + dma_memory.delete(); + dma_memory1.delete(); + endtask + + task reset_dut_lfsr (); + lfsr_dut_q <= 'hc0a232c162b2bab5b960668030f4efce27940bd0de965f0b8d4315f15b79704195e4e0a6b495fc269f65ae17e10e9ca98510fc143327a292b418597f9dd175fc91c3d61be287d5462a23e00fa7ae906ae9eb339ab5225021356138cd46b6e5a73540c5591116b6b5e08d2c0e54eaf0d5143b33b2186b6cf841c076a98c412a63981f0e323dce93481ed1c37e4f1d7553b6c2fba1a3af6c3ad88b15ad58812ba07d1753917ac4e6ab1e8c4f67a47b4b0f48a34f42a52c546e979f4e4968e80a732a0a5e7a51146cf08482f349f94336752b765c0b1d70803d883d5058d127264335213da4163c62f65a4e65501b90fa5f177675c0747cfca328e131bfb3f7bcc5c27680c7bf86491f4ed3d36c25531edfa74b1e32fafe426958ae356eb8ef0fd818eaca4227a667b7c934ebfa282ab6bfc6db89b927c91a41e63a9554dced774f30268d0725a1a565368703b9f81d5c027ba196ef8b803a51c639c7ead834e1d6bc537d33800fe5eb12f1ed67758f1dfe85ffdbae56e8ef27f2ecedcee75b8dbb5f5f1a629ba3b755; + endtask + + //-------------------------------------- + // Osmium Model + //-------------------------------------- + // Memory + block_t osmium_memory [bit [AddrWidth-$clog2($bits(block_t))-1:0]]; + // lfsr + logic [784:0] lfsr_osmium_q,lfsr_osmium_d; + + task oned_osmium_launch ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i + ); + logic [AddrWidth-1:0] read_addr, write_addr; + logic [AddrWidth-1:0] read_word, write_word; + logic [$clog2(AddrWidth):0] read_offset, write_offset; + // perform the transfer + for(int i = 0; i < num_bytes_i; i = i + 1) begin + read_addr = src_addr_i + i; + write_addr = dst_addr_i + i; + read_word = src_burst_i == 2'b00 ? src_addr_i >> $clog2(AddrWidth) : read_addr >> $clog2(AddrWidth); + write_word = dst_burst_i == 2'b00 ? dst_addr_i >> $clog2(AddrWidth) : write_addr >> $clog2(AddrWidth); + read_offset = read_addr [$clog2(AddrWidth)-1:0]; + write_offset = write_addr[$clog2(AddrWidth)-1:0]; + + // do the read + if (!osmium_memory.exists(read_word) === 1) begin + osmium_memory[read_word].data = lfsr_osmium_q[784:273]; + //shift 513x + repeat(513) begin + // next state + for (int i = 1; i < 785; i = i +1) lfsr_osmium_d[i-1] = lfsr_osmium_q[i]; + lfsr_osmium_d[784] = lfsr_osmium_q[0]; + lfsr_osmium_d[692] = lfsr_osmium_q[0] ^ lfsr_osmium_q[693]; + lfsr_osmium_q = lfsr_osmium_d; + end + end + // do the write + osmium_memory[write_word].bytes[write_offset] = osmium_memory[read_word].bytes[read_offset]; + // $display("W: %d - %d R: %d - %d", write_word, write_offset, read_word, read_offset); + end + + endtask + + task clear_osmium_memory (); + osmium_memory.delete(); + endtask + + task reset_osmium_lfsr (); + lfsr_osmium_q = 'hc0a232c162b2bab5b960668030f4efce27940bd0de965f0b8d4315f15b79704195e4e0a6b495fc269f65ae17e10e9ca98510fc143327a292b418597f9dd175fc91c3d61be287d5462a23e00fa7ae906ae9eb339ab5225021356138cd46b6e5a73540c5591116b6b5e08d2c0e54eaf0d5143b33b2186b6cf841c076a98c412a63981f0e323dce93481ed1c37e4f1d7553b6c2fba1a3af6c3ad88b15ad58812ba07d1753917ac4e6ab1e8c4f67a47b4b0f48a34f42a52c546e979f4e4968e80a732a0a5e7a51146cf08482f349f94336752b765c0b1d70803d883d5058d127264335213da4163c62f65a4e65501b90fa5f177675c0747cfca328e131bfb3f7bcc5c27680c7bf86491f4ed3d36c25531edfa74b1e32fafe426958ae356eb8ef0fd818eaca4227a667b7c934ebfa282ab6bfc6db89b927c91a41e63a9554dced774f30268d0725a1a565368703b9f81d5c027ba196ef8b803a51c639c7ead834e1d6bc537d33800fe5eb12f1ed67758f1dfe85ffdbae56e8ef27f2ecedcee75b8dbb5f5f1a629ba3b755; + endtask + + //-------------------------------------- + // Compare Memory content + //-------------------------------------- + task compare_memories (); + + // go through osmium memory and compare contents + foreach(osmium_memory[i]) begin + if (osmium_memory[i] !== dma_memory[i]) $fatal("Memory mismatch @ %x\nexpect: %x\ngot :%x\n", i << $clog2(AddrWidth), osmium_memory[i], dma_memory[i]); + end + // go through dma memory and compare contents + foreach(dma_memory[i]) begin + if (osmium_memory[i] !== dma_memory[i]) $fatal("Memory mismatch @ %x\nexpect: %x\ngot :%x\n", i << $clog2(AddrWidth), osmium_memory[i], dma_memory[i]); + end + + // it worked :P + $display(" - :D"); + + endtask + + //-------------------------------------- + // Master tasks + //-------------------------------------- + + task clear_memory (); + clear_dut_memory(); + clear_osmium_memory(); + endtask + + task reset_lfsr (); + reset_dut_lfsr(); + reset_osmium_lfsr(); + endtask + + task oned_launch ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task reset (); + int my_file; + oned_reset(); + wait_for_reset(); + // clear trace file + my_file = $fopen("dma_transfers.txt", "w"); + $fwrite(my_file, "Transfers launched:\n"); + $fclose(my_file); + endtask + + task oned_random_launch( + input logic [15:0] max_len, + input logic wait_for_completion + ); + + logic [ IdWidth-1:0] transf_id; + logic [ AddrWidth-1:0] src_addr, dst_addr, num_bytes; + logic decouple_rw; + logic deburst; + logic serialize; + + transf_id = 0;//$urandom(); + // transf_id = transaction_id; + src_addr[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr[(AddrWidth/2)-1: 0] = $urandom(); + num_bytes = 0; + num_bytes[15: 0] = $urandom_range(max_len, 1); + decouple_rw = 1;//$urandom(); + deburst = 0;//$urandom(); + serialize = 0;//$urandom(); + + // transaction_id = transaction_id + 1; + + oned_launch(transf_id, src_addr, dst_addr, num_bytes, decouple_rw, deburst, serialize, wait_for_completion); + + endtask + +endmodule : fixture_axi_dma_backend diff --git a/test/fixture_axi_dma_backend_2xp.sv b/test/fixture_axi_dma_backend_2xp.sv new file mode 100644 index 000000000..ff5166fb8 --- /dev/null +++ b/test/fixture_axi_dma_backend_2xp.sv @@ -0,0 +1,842 @@ +// Copyright (c) 2019 ETH Zurich, University of Bologna +// All rights reserved. +// +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// +// Thomas Benz + +// fixture for the AXi DMA backend +// the fixture instantiates the DMA backend, a golden model of the backend , and tasks controlling +// both. + +`timescale 1ns/1ns +module fixture_axi_dma_backend(); + + // `include "../axi/include/axi/assign.svh" + `define MEM_DEBUG 1 + `include "axi/assign.svh" + `include "axi/typedef.svh" + + //-------------------------------------- + // Parameters + //-------------------------------------- + localparam TA = 0.2ns; // must be nonzero to avoid Snitch load fifo double pop glitch + localparam TT = 0.8ns; + localparam HalfPeriod = 50ns; + localparam Reset = 75ns; + + localparam DataWidth = 512; + localparam AddrWidth = 64; + localparam StrbWidth = DataWidth / 8; + localparam IdWidth = 6; + localparam UserWidth = 1; + + // DUT parameters + localparam bit ATOPs = 0; + localparam int unsigned NoSlvPorts_1 = 2; + localparam int unsigned NoMstPorts_1 = 1; + localparam int unsigned NoSlvPorts_0 = 1; + localparam int unsigned NoMstPorts_0 = 1; + localparam bit [NoSlvPorts_1-1:0][NoMstPorts_1-1:0] Connectivity_1 = '1; + localparam bit [NoSlvPorts_0-1:0][NoMstPorts_0-1:0] Connectivity_0 = '1; + localparam int unsigned AxiSlvPortMaxUniqIds = 32'd16; + localparam int unsigned AxiSlvPortMaxTxnsPerId = 32'd128; + localparam int unsigned AxiSlvPortMaxTxns = 32'd31; + localparam int unsigned AxiMstPortMaxUniqIds = 32'd4; + localparam int unsigned AxiMstPortMaxTxnsPerId = 32'd7; + localparam int unsigned NoAddrRules_1 = 32'd2; + localparam int unsigned NoAddrRules_0 = 32'd1; + + typedef axi_pkg::xbar_rule_64_t rule_t; // Has to be the same width as axi addr + + // axi configuration + localparam int unsigned AxiIdWidthMasters = IdWidth; + localparam int unsigned AxiIdUsed = IdWidth-1; // Has to be <= AxiIdWidthMasters + localparam int unsigned AxiIdWidthSlaves = AxiIdWidthMasters + $clog2(NoMstPorts_0); + localparam int unsigned AxiAddrWidth = AddrWidth; // Axi Address Width + localparam int unsigned AxiDataWidth = DataWidth; // Axi Data Width + localparam int unsigned AxiStrbWidth = StrbWidth; + localparam int unsigned AxiUserWidth = UserWidth; + localparam int unsigned AxiIdWidth = IdWidth; + // in the bench can change this variables which are set here freely + localparam axi_pkg::xbar_cfg_t xbar_cfg_1 = '{ + NoSlvPorts: NoMstPorts_1, + NoMstPorts: NoSlvPorts_1, + MaxMstTrans: AxiSlvPortMaxTxns, + MaxSlvTrans: AxiSlvPortMaxTxnsPerId, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_AX, + AxiIdWidthSlvPorts: AxiIdWidthMasters, + AxiIdUsedSlvPorts: AxiIdUsed, + UniqueIds: 1'b0, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: NoAddrRules_1 + }; + + localparam axi_pkg::xbar_cfg_t xbar_cfg_0 = '{ + NoSlvPorts: NoMstPorts_0, + NoMstPorts: NoSlvPorts_0, + MaxMstTrans: AxiSlvPortMaxTxns, + MaxSlvTrans: AxiSlvPortMaxTxnsPerId, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_AX, + AxiIdWidthSlvPorts: AxiIdWidthMasters, + AxiIdUsedSlvPorts: AxiIdUsed, + UniqueIds: 1'b0, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: NoAddrRules_0 + }; + + localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp1 = '{ + '{idx: 32'd1 % NoSlvPorts_1, start_addr: {1'b0, {(AddrWidth-1){1'b1}}}, end_addr: {(AddrWidth){1'b1}}}, + '{idx: 32'd0 % NoSlvPorts_1, start_addr: {AddrWidth{1'b0}}, end_addr: {1'b0, {(AddrWidth-1){1'b1}}}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_0.NoAddrRules-1:0] AddrMap_xp0 = '{ + '{idx: 32'd0 % NoSlvPorts_0, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + typedef union packed { + logic [StrbWidth-1:0][7:0] bytes; + logic [DataWidth-1:0] data; + } block_t; + + /// Address Type + typedef logic [ AddrWidth-1:0] addr_t; + /// Data Type + typedef logic [ DataWidth-1:0] data_t; + /// Strobe Type + typedef logic [ StrbWidth-1:0] strb_t; + /// AXI ID Type + typedef logic [ IdWidth-1:0] axi_id_t; + /// AXI USER Type + typedef logic [ UserWidth-1:0] user_t; + /// 1D burst request + typedef struct packed { + axi_id_t id; + addr_t src, dst, num_bytes; + axi_pkg::cache_t cache_src, cache_dst; + axi_pkg::burst_t burst_src, burst_dst; + logic decouple_rw; + logic deburst; + logic serialize; + } burst_req_t; + + // master AXI bus --> DMA + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_dma_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_dma_t, axi_id_t, user_t) + + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_dma_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_dma_t, data_t, axi_id_t, user_t) + + `AXI_TYPEDEF_REQ_T(dma_req_t, aw_chan_dma_t, w_chan_t, ar_chan_dma_t) + `AXI_TYPEDEF_RESP_T(dma_resp_t, b_chan_dma_t, r_chan_dma_t) + + // slave AXI bus --> mem + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_mem_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_mem_t, axi_id_t, user_t) + + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_mem_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_mem_t, data_t, axi_id_t, user_t) + + `AXI_TYPEDEF_REQ_T(mem_req_t, aw_chan_mem_t, w_chan_t, ar_chan_mem_t) + `AXI_TYPEDEF_RESP_T(mem_resp_t, b_chan_mem_t, r_chan_mem_t) + + //-------------------------------------- + // Clock and Reset + //-------------------------------------- + logic clk; + initial begin + forever begin + clk = 0; + #HalfPeriod; + clk = 1; + #HalfPeriod; + end + end + + logic rst_n; + initial begin + rst_n = 0; + #Reset; + rst_n = 1; + end + + task wait_for_reset; + @(posedge rst_n); + @(posedge clk); + endtask + + //-------------------------------------- + // DUT Axi busses + //-------------------------------------- + dma_req_t [NoMstPorts_0-1:0] axi_dma_req; + dma_resp_t [NoMstPorts_0-1:0] axi_dma_res; + + //dma_req_t [NoMstPorts-1:0] axi_dma_sync_req; + //dma_resp_t [NoMstPorts-1:0] axi_dma_sync_res; + + mem_req_t [NoSlvPorts_1-1:0] axi_mem_req; + mem_resp_t [NoSlvPorts_1-1:0] axi_mem_res; + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) dma [NoMstPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) dma_sync [NoMstPorts_0-1:0] (); + + AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) dma_dv [NoMstPorts_0-1:0] (clk); + + for (genvar i = 0; i < NoMstPorts_0; i++) begin : gen_conn_dv_masters + //`AXI_ASSIGN (dma_dv[i], dma[i]) + `AXI_ASSIGN_FROM_REQ(dma[i], axi_dma_req[i]) + `AXI_ASSIGN_TO_RESP(axi_dma_res[i], dma[i]) + end + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_xp1_mst [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_xp1_slv [NoSlvPorts_0-1:0] (); + + //`AXI_ASSIGN (xp0_xp1_slv[0], xp0_xp1_mst[0]) + + AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) mem_dv [NoSlvPorts_1-1:0] (clk); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) mem [NoSlvPorts_1-1:0] (); + + for (genvar i = 0; i < NoSlvPorts_1; i++) begin : gen_conn_dv_slaves + `AXI_ASSIGN (mem_dv[i], mem[i]) + `AXI_ASSIGN_TO_REQ(axi_mem_req[i], mem_dv[i]) + `AXI_ASSIGN_TO_RESP(axi_mem_res[i], mem_dv[i]) + end + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma1_t; + + driver_dma_t driver_dma = new(mem_dv[0]); + driver_dma1_t driver_dma1 = new(mem_dv[1]); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem0 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[0]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem1 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[1]) + ); + + // initial begin + // $readmemh("sim_mem0.mem", i_sim_mem0.mem); + // $readmemh("sim_mem1.mem", i_sim_mem1.mem); + // end + + //-------------------------------------- + // DUT AXI Memory System + //-------------------------------------- + // lfsr + logic [784:0] lfsr_dut_q, lfsr_dut_d; + + // transaction id + logic [ 7:0] transaction_id = 0; + + // Memory + block_t dma_memory [bit [AddrWidth-$clog2($bits(block_t))-1:0]]; + block_t dma_memory1 [bit [AddrWidth-$clog2($bits(block_t))-1:0]]; + + // Handle the data output from dma. Model of the memory acting as AXI slave. +// typedef axi_test::axi_driver #(.AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(1), .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod)) driver_dma_t; +// typedef axi_test::axi_driver #(.AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(1), .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod)) driver_dma1_t; +// driver_dma_t driver_dma = new(mem_dv[0]); +// driver_dma_t driver_dma1 = new(mem_dv[1]); +// initial begin +// automatic driver_dma_t::ax_beat_t aw_dma_queue[$], ar_dma_queue[$]; +// automatic driver_dma_t::b_beat_t b_dma_queue[$]; + +// automatic driver_dma1_t::ax_beat_t aw_dma1_queue[$], ar_dma1_queue[$]; +// automatic driver_dma1_t::b_beat_t b_dma1_queue[$]; +// automatic string sb = ""; + +// event ar_dma_received, aw_dma_received, b_dma_ready; +// event ar_dma1_received, aw_dma1_received, b_dma1_ready; +// event lfsr_dut_read; +// event lfsr_dut_read_completed; + +// driver_dma.reset_slave(); +// driver_dma1.reset_slave(); +// @(posedge rst_n); +// $display("AXI reset done"); + +// fork +// // AW mem 0 +// forever begin +// automatic driver_dma_t::ax_beat_t dma_tx; +// driver_dma.recv_aw(dma_tx); +// `ifdef MEM_DEBUG +// $display("Mem0: %d: AW - id: %4d - addr: %d - len: %4d - size: %4d - burst: %b", +// $time(), dma_tx.ax_id, dma_tx.ax_addr, dma_tx.ax_len, dma_tx.ax_size, dma_tx.ax_burst ); +// `endif +// aw_dma_queue.push_back(dma_tx); +// -> aw_dma_received; +// end +// // AW mem 1 +// forever begin +// automatic driver_dma1_t::ax_beat_t dma1_tx; +// driver_dma1.recv_aw(dma1_tx); +// `ifdef MEM_DEBUG +// $display("Mem1: %d: AW - id: %4d - addr: %d - len: %4d - size: %4d - burst: %b", +// $time(), dma1_tx.ax_id, dma1_tx.ax_addr, dma1_tx.ax_len, dma1_tx.ax_size, dma1_tx.ax_burst ); +// `endif +// aw_dma1_queue.push_back(dma1_tx); +// -> aw_dma1_received; +// end +// // AR mem 0 +// forever begin +// automatic driver_dma_t::ax_beat_t dma_tx; +// driver_dma.recv_ar(dma_tx); +// `ifdef MEM_DEBUG +// $display("Mem0: %d: AR - id: %4d - addr: %d - len: %4d - size: %4d - burst: %b", +// $time(), dma_tx.ax_id, dma_tx.ax_addr, dma_tx.ax_len, dma_tx.ax_size, dma_tx.ax_burst ); +// `endif +// ar_dma_queue.push_back(dma_tx); +// -> ar_dma_received; +// end +// // AR mem 1 +// forever begin +// automatic driver_dma1_t::ax_beat_t dma1_tx; +// driver_dma1.recv_ar(dma1_tx); +// `ifdef MEM_DEBUG +// $display("Mem1: %d: AR - id: %4d - addr: %d - len: %4d - size: %4d - burst: %b", +// $time(), dma1_tx.ax_id, dma1_tx.ax_addr, dma1_tx.ax_len, dma1_tx.ax_size, dma1_tx.ax_burst ); +// `endif +// ar_dma1_queue.push_back(dma1_tx); +// -> ar_dma1_received; +// end +// // R mem 0 +// forever begin +// automatic driver_dma_t::r_beat_t dma_tx = new(); +// automatic driver_dma_t::ax_beat_t dma_ax; +// automatic bit [AddrWidth-1:0] word; +// while (ar_dma_queue.size() == 0) @ar_dma_received; +// dma_ax = ar_dma_queue[0]; +// word = dma_ax.ax_addr >> $clog2(AddrWidth); +// dma_tx.r_id = dma_ax.ax_id; +// // if (!dma_memory.exists(word)) begin +// // dma_memory[word].data = lfsr_dut_q[784:273]; +// // //shift 513x +// // repeat(513) begin +// // // next state +// // for (int i = 1; i < 785; i = i +1) lfsr_dut_d[i-1] = lfsr_dut_q[i]; +// // lfsr_dut_d[784] = lfsr_dut_q[0]; +// // lfsr_dut_d[692] = lfsr_dut_q[0] ^ lfsr_dut_q[693]; +// // lfsr_dut_q = lfsr_dut_d; +// // end +// // end +// // dma_tx.r_data = dma_memory[word].data; +// dma_tx.r_resp = axi_pkg::RESP_OKAY; +// dma_tx.r_last = (dma_ax.ax_len == 0); +// `ifdef MEM_DEBUG +// $display("Mem0: %d: R - id: %4d - data: %x - resp: %x - last: %b (0x%x)", +// $time(), dma_tx.r_id, dma_tx.r_data, dma_tx.r_resp, dma_tx.r_last, word << $clog2(AddrWidth)); +// `endif +// dma_ax.ax_addr >>= dma_ax.ax_size; +// dma_ax.ax_addr += (dma_ax.ax_burst !== 0); +// dma_ax.ax_addr <<= dma_ax.ax_size; +// dma_ax.ax_len -= 1; +// if (dma_tx.r_last) begin +// ar_dma_queue.pop_front(); +// end +// driver_dma.send_r(dma_tx); +// end +// // R mem 1 +// forever begin +// automatic driver_dma1_t::r_beat_t dma1_tx = new(); +// automatic driver_dma1_t::ax_beat_t dma1_ax; +// automatic bit [AddrWidth-1:0] word; +// while (ar_dma1_queue.size() == 0) @ar_dma1_received; +// dma1_ax = ar_dma1_queue[0]; +// word = dma1_ax.ax_addr >> $clog2(AddrWidth); +// dma1_tx.r_id = dma1_ax.ax_id; +// // if (!dma_memory1.exists(word)) begin +// // dma_memory1[word].data = lfsr_dut_q[784:273]; +// // //shift 513x +// // repeat(513) begin +// // // next state +// // for (int i = 1; i < 785; i = i +1) lfsr_dut_d[i-1] = lfsr_dut_q[i]; +// // lfsr_dut_d[784] = lfsr_dut_q[0]; +// // lfsr_dut_d[692] = lfsr_dut_q[0] ^ lfsr_dut_q[693]; +// // lfsr_dut_q = lfsr_dut_d; +// // end +// // end +// // dma1_tx.r_data = dma_memory1[word].data; +// dma1_tx.r_resp = axi_pkg::RESP_OKAY; +// dma1_tx.r_last = (dma1_ax.ax_len == 0); +// `ifdef MEM_DEBUG +// $display("Mem1: %d: R - id: %4d - data: %x - resp: %x - last: %b (0x%x)", +// $time(), dma1_tx.r_id, dma1_tx.r_data, dma1_tx.r_resp, dma1_tx.r_last, word << $clog2(AddrWidth)); +// `endif +// dma1_ax.ax_addr >>= dma1_ax.ax_size; +// dma1_ax.ax_addr += (dma1_ax.ax_burst !== 0); +// dma1_ax.ax_addr <<= dma1_ax.ax_size; +// dma1_ax.ax_len -= 1; +// if (dma1_tx.r_last) begin +// ar_dma1_queue.pop_front(); +// end +// driver_dma1.send_r(dma1_tx); +// end +// // W mem 0 +// forever begin +// automatic driver_dma_t::w_beat_t dma_tx; +// automatic driver_dma_t::ax_beat_t dma_ax; +// automatic bit [AddrWidth-1:0] word; +// driver_dma.recv_w(dma_tx); +// while (aw_dma_queue.size() == 0) @ar_dma_received; +// dma_ax = aw_dma_queue[0]; +// word = dma_ax.ax_addr >> $clog2(AddrWidth); +// //$display("Ready to write"); +// //$display("%x", word); +// // for (int i = 0; i < StrbWidth; i++) begin +// // if (dma_tx.w_strb[i]) begin +// // dma_memory[word].bytes[i] = dma_tx.w_data[i*8+:8]; +// // end +// // end +// `ifdef MEM_DEBUG +// $display("Mem0: %d: W - data: %x - strb: %x - last: %b (0x%x)", +// $time(), dma_tx.w_data, dma_tx.w_strb, dma_tx.w_last, word << $clog2(AddrWidth)); +// `endif +// dma_ax.ax_addr >>= dma_ax.ax_size; +// dma_ax.ax_addr += (dma_ax.ax_burst !== 0); +// dma_ax.ax_addr <<= dma_ax.ax_size; +// dma_ax.ax_len -= 1; +// if (dma_tx.w_last) begin +// automatic driver_dma_t::b_beat_t dma_tx = new(); +// dma_tx.b_id = dma_ax.ax_id; +// dma_tx.b_user = dma_ax.ax_user; +// aw_dma_queue.pop_front(); +// b_dma_queue.push_back(dma_tx); +// -> b_dma_ready; +// end +// end +// // W mem 1 +// forever begin +// automatic driver_dma1_t::w_beat_t dma1_tx; +// automatic driver_dma1_t::ax_beat_t dma1_ax; +// automatic bit [AddrWidth-1:0] word; +// driver_dma1.recv_w(dma1_tx); +// while (aw_dma1_queue.size() == 0) @ar_dma1_received; +// dma1_ax = aw_dma1_queue[0]; +// word = dma1_ax.ax_addr >> $clog2(AddrWidth); +// //$display("Ready to write"); +// //$display("%x", word); +// // for (int i = 0; i < StrbWidth; i++) begin +// // if (dma1_tx.w_strb[i]) begin +// // dma_memory1[word].bytes[i] = dma1_tx.w_data[i*8+:8]; +// // end +// // end +// `ifdef MEM_DEBUG +// $display("Mem1: %d: W - data: %x - strb: %x - last: %b (0x%x)", +// $time(), dma1_tx.w_data, dma1_tx.w_strb, dma1_tx.w_last, word << $clog2(AddrWidth)); +// `endif +// dma1_ax.ax_addr >>= dma1_ax.ax_size; +// dma1_ax.ax_addr += (dma1_ax.ax_burst !== 0); +// dma1_ax.ax_addr <<= dma1_ax.ax_size; +// dma1_ax.ax_len -= 1; +// if (dma1_tx.w_last) begin +// automatic driver_dma1_t::b_beat_t dma1_tx = new(); +// dma1_tx.b_id = dma1_ax.ax_id; +// dma1_tx.b_user = dma1_ax.ax_user; +// aw_dma1_queue.pop_front(); +// b_dma1_queue.push_back(dma1_tx); +// -> b_dma1_ready; +// end +// end +// // B mem 0 +// forever begin +// automatic driver_dma_t::b_beat_t dma_tx; +// while (b_dma_queue.size() == 0) @b_dma_ready; +// driver_dma.send_b(b_dma_queue[0]); +// b_dma_queue.pop_front(); +// end +// // B mem 1 +// forever begin +// automatic driver_dma1_t::b_beat_t dma1_tx; +// while (b_dma1_queue.size() == 0) @b_dma1_ready; +// driver_dma1.send_b(b_dma1_queue[0]); +// b_dma1_queue.pop_front(); +// end +// join_any +// end + + //-------------------------------------- + // DMA instantiation + //-------------------------------------- + burst_req_t burst_req; + logic burst_req_valid; + logic burst_req_ready; + logic backend_idle; + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[0] ), + .axi_dma_res_i ( axi_dma_res[0] ), + .burst_req_i ( burst_req ), + .valid_i ( burst_req_valid ), + .ready_o ( burst_req_ready ), + .backend_idle_o ( backend_idle ), + .trans_complete_o ( ), + .dma_id_i ( '0 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[0] ), + .out ( dma_sync[0] ) + ); + + //----------------------------------- + // DUT + //----------------------------------- + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_1 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp0_xp1_slv ), + .mst_ports ( mem ), + .addr_map_i ( AddrMap_xp1 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_0 ), + .NoSlvPorts ( xbar_cfg_0.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_0.NoMstPorts ), + .Connectivity ( Connectivity_0 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_0.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_0 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( dma_sync ), + .mst_ports ( xp0_xp1_slv ), + .addr_map_i ( AddrMap_xp0 ) + ); + + //-------------------------------------- + // DMA DUT tasks + //-------------------------------------- + task oned_dut_launch ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst_req_valid <= 1'b0; + burst_req <= '0; + @(posedge clk); + while (burst_req_ready !== 1) @(posedge clk); + // write data + burst_req.id <= transf_id_i; + burst_req.src <= src_addr_i; + burst_req.dst <= dst_addr_i; + burst_req.num_bytes <= num_bytes_i; + burst_req.cache_src <= src_cache_i; + burst_req.cache_dst <= dst_cache_i; + burst_req.burst_src <= src_burst_i; + burst_req.burst_dst <= dst_burst_i; + burst_req.decouple_rw <= decouple_rw_i; + burst_req.deburst <= deburst_i; + burst_req.serialize <= serialize_i; + burst_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst_req_valid <= 1'b0; + burst_req <= '0; + endtask + + task oned_reset (); + burst_req_valid <= 1'b0; + burst_req <= '0; + endtask + + task wait_for_dut_completion (); + repeat(10) @(posedge clk); + while (backend_idle === 0) @(posedge clk); + repeat(50) @(posedge clk); + endtask + + task clear_dut_memory (); + dma_memory.delete(); + dma_memory1.delete(); + endtask + + task reset_dut_lfsr (); + lfsr_dut_q <= 'hc0a232c162b2bab5b960668030f4efce27940bd0de965f0b8d4315f15b79704195e4e0a6b495fc269f65ae17e10e9ca98510fc143327a292b418597f9dd175fc91c3d61be287d5462a23e00fa7ae906ae9eb339ab5225021356138cd46b6e5a73540c5591116b6b5e08d2c0e54eaf0d5143b33b2186b6cf841c076a98c412a63981f0e323dce93481ed1c37e4f1d7553b6c2fba1a3af6c3ad88b15ad58812ba07d1753917ac4e6ab1e8c4f67a47b4b0f48a34f42a52c546e979f4e4968e80a732a0a5e7a51146cf08482f349f94336752b765c0b1d70803d883d5058d127264335213da4163c62f65a4e65501b90fa5f177675c0747cfca328e131bfb3f7bcc5c27680c7bf86491f4ed3d36c25531edfa74b1e32fafe426958ae356eb8ef0fd818eaca4227a667b7c934ebfa282ab6bfc6db89b927c91a41e63a9554dced774f30268d0725a1a565368703b9f81d5c027ba196ef8b803a51c639c7ead834e1d6bc537d33800fe5eb12f1ed67758f1dfe85ffdbae56e8ef27f2ecedcee75b8dbb5f5f1a629ba3b755; + endtask + + //-------------------------------------- + // Osmium Model + //-------------------------------------- + // Memory + block_t osmium_memory [bit [AddrWidth-$clog2($bits(block_t))-1:0]]; + // lfsr + logic [784:0] lfsr_osmium_q,lfsr_osmium_d; + + task oned_osmium_launch ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i + ); + logic [AddrWidth-1:0] read_addr, write_addr; + logic [AddrWidth-1:0] read_word, write_word; + logic [$clog2(AddrWidth):0] read_offset, write_offset; + // perform the transfer + for(int i = 0; i < num_bytes_i; i = i + 1) begin + read_addr = src_addr_i + i; + write_addr = dst_addr_i + i; + read_word = src_burst_i == 2'b00 ? src_addr_i >> $clog2(AddrWidth) : read_addr >> $clog2(AddrWidth); + write_word = dst_burst_i == 2'b00 ? dst_addr_i >> $clog2(AddrWidth) : write_addr >> $clog2(AddrWidth); + read_offset = read_addr [$clog2(AddrWidth)-1:0]; + write_offset = write_addr[$clog2(AddrWidth)-1:0]; + + // do the read + if (!osmium_memory.exists(read_word) === 1) begin + osmium_memory[read_word].data = lfsr_osmium_q[784:273]; + //shift 513x + repeat(513) begin + // next state + for (int i = 1; i < 785; i = i +1) lfsr_osmium_d[i-1] = lfsr_osmium_q[i]; + lfsr_osmium_d[784] = lfsr_osmium_q[0]; + lfsr_osmium_d[692] = lfsr_osmium_q[0] ^ lfsr_osmium_q[693]; + lfsr_osmium_q = lfsr_osmium_d; + end + end + // do the write + osmium_memory[write_word].bytes[write_offset] = osmium_memory[read_word].bytes[read_offset]; + // $display("W: %d - %d R: %d - %d", write_word, write_offset, read_word, read_offset); + end + + endtask + + task clear_osmium_memory (); + osmium_memory.delete(); + endtask + + task reset_osmium_lfsr (); + lfsr_osmium_q = 'hc0a232c162b2bab5b960668030f4efce27940bd0de965f0b8d4315f15b79704195e4e0a6b495fc269f65ae17e10e9ca98510fc143327a292b418597f9dd175fc91c3d61be287d5462a23e00fa7ae906ae9eb339ab5225021356138cd46b6e5a73540c5591116b6b5e08d2c0e54eaf0d5143b33b2186b6cf841c076a98c412a63981f0e323dce93481ed1c37e4f1d7553b6c2fba1a3af6c3ad88b15ad58812ba07d1753917ac4e6ab1e8c4f67a47b4b0f48a34f42a52c546e979f4e4968e80a732a0a5e7a51146cf08482f349f94336752b765c0b1d70803d883d5058d127264335213da4163c62f65a4e65501b90fa5f177675c0747cfca328e131bfb3f7bcc5c27680c7bf86491f4ed3d36c25531edfa74b1e32fafe426958ae356eb8ef0fd818eaca4227a667b7c934ebfa282ab6bfc6db89b927c91a41e63a9554dced774f30268d0725a1a565368703b9f81d5c027ba196ef8b803a51c639c7ead834e1d6bc537d33800fe5eb12f1ed67758f1dfe85ffdbae56e8ef27f2ecedcee75b8dbb5f5f1a629ba3b755; + endtask + + //-------------------------------------- + // Compare Memory content + //-------------------------------------- + task compare_memories (); + + // go through osmium memory and compare contents + foreach(osmium_memory[i]) begin + if (osmium_memory[i] !== dma_memory[i]) $fatal("Memory mismatch @ %x\nexpect: %x\ngot :%x\n", i << $clog2(AddrWidth), osmium_memory[i], dma_memory[i]); + end + // go through dma memory and compare contents + foreach(dma_memory[i]) begin + if (osmium_memory[i] !== dma_memory[i]) $fatal("Memory mismatch @ %x\nexpect: %x\ngot :%x\n", i << $clog2(AddrWidth), osmium_memory[i], dma_memory[i]); + end + + // it worked :P + $display(" - :D"); + + endtask + + //-------------------------------------- + // Master tasks + //-------------------------------------- + + task clear_memory (); + clear_dut_memory(); + clear_osmium_memory(); + endtask + + task reset_lfsr (); + reset_dut_lfsr(); + reset_osmium_lfsr(); + endtask + + task oned_launch ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task reset (); + int my_file; + oned_reset(); + wait_for_reset(); + // clear trace file + my_file = $fopen("dma_transfers.txt", "w"); + $fwrite(my_file, "Transfers launched:\n"); + $fclose(my_file); + endtask + + task oned_random_launch( + input logic [15:0] max_len, + input logic wait_for_completion + ); + + logic [ IdWidth-1:0] transf_id; + logic [ AddrWidth-1:0] src_addr, dst_addr, num_bytes; + logic decouple_rw; + logic deburst; + logic serialize; + + transf_id = 0;//$urandom(); + // transf_id = transaction_id; + src_addr[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr[(AddrWidth/2)-1: 0] = $urandom(); + num_bytes = 0; + num_bytes[15: 0] = $urandom_range(max_len, 1); + decouple_rw = 1;//$urandom(); + deburst = 0;//$urandom(); + serialize = 0;//$urandom(); + + // transaction_id = transaction_id + 1; + + oned_launch(transf_id, src_addr, dst_addr, num_bytes, decouple_rw, deburst, serialize, wait_for_completion); + + endtask + +endmodule : fixture_axi_dma_backend diff --git a/test/fixture_axi_dma_backend_4x4_unirand.sv b/test/fixture_axi_dma_backend_4x4_unirand.sv new file mode 100644 index 000000000..7b03e9342 --- /dev/null +++ b/test/fixture_axi_dma_backend_4x4_unirand.sv @@ -0,0 +1,4900 @@ +// Copyright (c) 2019 ETH Zurich, University of Bologna +// All rights reserved. +// +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// +// Thomas Benz + +// fixture for the AXi DMA backend +// the fixture instantiates the DMA backend, a golden model of the backend , and tasks controlling +// both. + +`timescale 1ns/1ns +module fixture_axi_dma_backend(); + + // `include "../axi/include/axi/assign.svh" + `define MASTERS_16 + `define MEM_DEBUG 1 + `include "axi/assign.svh" + `include "axi/typedef.svh" + + //-------------------------------------- + // Parameters + //-------------------------------------- + localparam TA = 0.2ns; // must be nonzero to avoid Snitch load fifo double pop glitch + localparam TT = 0.8ns; + localparam HalfPeriod = 5ns; + localparam Reset = 7.5ns; + + localparam DataWidth = 32; + localparam AddrWidth = 32; + localparam StrbWidth = DataWidth / 8; + localparam IdWidth = 6; + localparam UserWidth = 1; + + // DUT parameters + localparam bit ATOPs = 0; + localparam int unsigned NoMst = 16; + localparam int unsigned NoSlv = 16; + localparam int unsigned NoSlvPorts_2 = 5; + localparam int unsigned NoMstPorts_2 = 5; + localparam int unsigned NoSlvPorts_1 = 4; + localparam int unsigned NoMstPorts_1 = 4; + localparam int unsigned NoSlvPorts_0 = 3; + localparam int unsigned NoMstPorts_0 = 3; + localparam bit [NoSlvPorts_2-1:0][NoMstPorts_2-1:0] Connectivity_2 = {5'h1f,5'h1f,5'h1f,5'h1f,5'h1f}; + localparam bit [NoSlvPorts_1-1:0][NoMstPorts_1-1:0] Connectivity_1 = {4'hf,4'hf,4'hf,4'hf}; + localparam bit [NoSlvPorts_0-1:0][NoMstPorts_0-1:0] Connectivity_0 = '1;//{3'h6,3'h6,3'h6}; + localparam int unsigned AxiSlvPortMaxUniqIds = 32'd16; + localparam int unsigned AxiSlvPortMaxTxnsPerId = 32'd128; + localparam int unsigned AxiSlvPortMaxTxns = 32'd31; + localparam int unsigned AxiMstPortMaxUniqIds = 32'd16; + localparam int unsigned AxiMstPortMaxTxnsPerId = 32'd128; + localparam int unsigned NoAddrRules_2 = 32'd5; + localparam int unsigned NoAddrRules_1 = 32'd4; + localparam int unsigned NoAddrRules_0 = 32'd3; + + typedef axi_pkg::xbar_rule_32_t rule_t; // Has to be the same width as axi addr + + // axi configuration + localparam int unsigned AxiIdWidthMasters = IdWidth; + localparam int unsigned AxiIdUsed = IdWidth-1; // Has to be <= AxiIdWidthMasters + localparam int unsigned AxiIdWidthSlaves = AxiIdWidthMasters + $clog2(NoMstPorts_2); + localparam int unsigned AxiAddrWidth = AddrWidth; // Axi Address Width + localparam int unsigned AxiDataWidth = DataWidth; // Axi Data Width + localparam int unsigned AxiStrbWidth = StrbWidth; + localparam int unsigned AxiUserWidth = UserWidth; + localparam int unsigned AxiIdWidth = IdWidth; + + // in the bench can change this variables which are set here freely + localparam axi_pkg::xbar_cfg_t xbar_cfg_2 = '{ + NoSlvPorts: NoMstPorts_2, + NoMstPorts: NoSlvPorts_2, + MaxMstTrans: AxiSlvPortMaxTxns, + MaxSlvTrans: AxiSlvPortMaxTxnsPerId, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_PORTS, + AxiIdWidthSlvPorts: AxiIdWidthMasters, + AxiIdUsedSlvPorts: AxiIdUsed, + UniqueIds: 1'b0, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: NoAddrRules_2 + }; + + localparam axi_pkg::xbar_cfg_t xbar_cfg_1 = '{ + NoSlvPorts: NoMstPorts_1, + NoMstPorts: NoSlvPorts_1, + MaxMstTrans: AxiSlvPortMaxTxns, + MaxSlvTrans: AxiSlvPortMaxTxnsPerId, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_PORTS, + AxiIdWidthSlvPorts: AxiIdWidthMasters, + AxiIdUsedSlvPorts: AxiIdUsed, + UniqueIds: 1'b0, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: NoAddrRules_1 + }; + + localparam axi_pkg::xbar_cfg_t xbar_cfg_0 = '{ + NoSlvPorts: NoMstPorts_0, + NoMstPorts: NoSlvPorts_0, + MaxMstTrans: AxiSlvPortMaxTxns, + MaxSlvTrans: AxiSlvPortMaxTxnsPerId, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_PORTS, + AxiIdWidthSlvPorts: AxiIdWidthMasters, + AxiIdUsedSlvPorts: AxiIdUsed, + UniqueIds: 1'b0, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: NoAddrRules_0 + }; + + //localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2 = '{ + // '{idx: 32'd1 % NoSlvPorts_1, start_addr: {AddrWidth{1'b0}}, end_addr: {1'b0, {(AddrWidth-1){1'b1}}}}, + // '{idx: 32'd0 % NoSlvPorts_1, start_addr: {1'b0, {(AddrWidth-1){1'b1}}}, end_addr: {(AddrWidth){1'b1}}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + //}; + + // //////////////////////////////// All global accesses start ////////////////////////////////////// + + // localparam rule_t [xbar_cfg_0.NoAddrRules-1:0] AddrMap_xp0 = '{ + // '{idx: 32'd2 % NoSlvPorts_0, start_addr: {32'h0fffffff}, end_addr: {32'hffffffff}}, + // '{idx: 32'd1 % NoSlvPorts_0, start_addr: {32'h000fffff}, end_addr: {32'h0fffffff}}, + // '{idx: 32'd0 % NoSlvPorts_0, start_addr: {32'b0}, end_addr: {32'h000fffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp1 = '{ + // '{idx: 32'd3 % NoSlvPorts_1, start_addr: {32'h000000ff}, end_addr: {32'h0000ffff}}, + // '{idx: 32'd2 % NoSlvPorts_1, start_addr: {32'h0000ffff}, end_addr: {32'h0fffffff}}, + // '{idx: 32'd1 % NoSlvPorts_1, start_addr: {32'h0fffffff}, end_addr: {32'hffffffff}}, + // '{idx: 32'd0 % NoSlvPorts_1, start_addr: {32'h00000000}, end_addr: {32'h000000ff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2 = '{ + // // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'b0}, end_addr: {32'h00000fff}}, + // // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h000fffff}}, + // // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h000fffff}, end_addr: {32'h00ffffff}}, + // // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h00ffffff}, end_addr: {32'h0fffffff}}, + // // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h0fffffff}, end_addr: {32'hffffffff}} + // // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // // }; + + // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2_1 = '{ + // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h00000000}, end_addr: {32'h000000ff}}, + // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h000fffff}, end_addr: {32'hffffffff}}, + // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h000000ff}, end_addr: {32'h00000fff}}, + // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h0000ffff}}, + // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h0000ffff}, end_addr: {32'h000fffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2_2 = '{ + // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h00000000}, end_addr: {32'h000000ff}}, + // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h000000ff}, end_addr: {32'h00000fff}}, + // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h0000ffff}}, + // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h0000ffff}, end_addr: {32'h000fffff}}, + // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h000fffff}, end_addr: {32'hffffffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2_3 = '{ + // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h000fffff}, end_addr: {32'hffffffff}}, + // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h00000000}, end_addr: {32'h000000ff}}, + // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h000000ff}, end_addr: {32'h00000fff}}, + // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h0000ffff}}, + // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h0000ffff}, end_addr: {32'h000fffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // //////////////////////////////// All global accesses end ////////////////////////////////////// + + // //////////////////////////////// All local accesses start ////////////////////////////////////// + + // localparam rule_t [xbar_cfg_0.NoAddrRules-1:0] AddrMap_xp0 = '{ + // '{idx: 32'd2 % NoSlvPorts_0, start_addr: {32'h00000000}, end_addr: {32'h00000001}}, + // '{idx: 32'd1 % NoSlvPorts_0, start_addr: {32'h00000001}, end_addr: {32'h00000002}}, + // '{idx: 32'd0 % NoSlvPorts_0, start_addr: {32'h00000002}, end_addr: {32'hffffffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp1 = '{ + // '{idx: 32'd3 % NoSlvPorts_1, start_addr: {32'h00000000}, end_addr: {32'h000000ff}}, + // '{idx: 32'd2 % NoSlvPorts_1, start_addr: {32'h000000ff}, end_addr: {32'h00000fff}}, + // '{idx: 32'd1 % NoSlvPorts_1, start_addr: {32'h00000fff}, end_addr: {32'h0000ffff}}, + // '{idx: 32'd0 % NoSlvPorts_1, start_addr: {32'h0000ffff}, end_addr: {32'hffffffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2 = '{ + // // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'b0}, end_addr: {32'h00000fff}}, + // // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h000fffff}}, + // // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h000fffff}, end_addr: {32'h00ffffff}}, + // // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h00ffffff}, end_addr: {32'h0fffffff}}, + // // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h0fffffff}, end_addr: {32'hffffffff}} + // // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // // }; + + // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2_1 = '{ + // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h00000000}, end_addr: {32'h0000000f}}, + // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h0000ffff}}, + // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h0000000f}, end_addr: {32'h000000ff}}, + // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h000000ff}, end_addr: {32'h00000fff}}, + // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h0000ffff}, end_addr: {32'hffffffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2_2 = '{ + // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h00000000}, end_addr: {32'h0000000f}}, + // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h0000000f}, end_addr: {32'h000000ff}}, + // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h000000ff}, end_addr: {32'h00000fff}}, + // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h0000ffff}}, + // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h0000ffff}, end_addr: {32'hffffffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2_3 = '{ + // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h0000ffff}}, + // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h00000000}, end_addr: {32'h0000000f}}, + // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h0000000f}, end_addr: {32'h000000ff}}, + // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h000000ff}, end_addr: {32'h00000fff}}, + // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h0000ffff}, end_addr: {32'hffffffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // //////////////////////////////// All local accesses end ////////////////////////////////////// + + // //////////////////////////////// Mixed accesses (max 2 hop) start ////////////////////////////////////// + + // localparam rule_t [xbar_cfg_0.NoAddrRules-1:0] AddrMap_xp0 = '{ + // '{idx: 32'd2 % NoSlvPorts_0, start_addr: {32'h0fffffff}, end_addr: {32'hffffffff}}, + // '{idx: 32'd1 % NoSlvPorts_0, start_addr: {32'h0000ffff}, end_addr: {32'h0fffffff}}, + // '{idx: 32'd0 % NoSlvPorts_0, start_addr: {32'b0}, end_addr: {32'h0000ffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp1 = '{ + // '{idx: 32'd3 % NoSlvPorts_1, start_addr: {32'h000000ff}, end_addr: {32'h0000ffff}}, + // '{idx: 32'd2 % NoSlvPorts_1, start_addr: {32'h0000ffff}, end_addr: {32'h0fffffff}}, + // '{idx: 32'd1 % NoSlvPorts_1, start_addr: {32'h0fffffff}, end_addr: {32'hffffffff}}, + // '{idx: 32'd0 % NoSlvPorts_1, start_addr: {32'h00000000}, end_addr: {32'h000000ff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2 = '{ + // // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'b0}, end_addr: {32'h00000fff}}, + // // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h000fffff}}, + // // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h000fffff}, end_addr: {32'h00ffffff}}, + // // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h00ffffff}, end_addr: {32'h0fffffff}}, + // // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h0fffffff}, end_addr: {32'hffffffff}} + // // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // // }; + + // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2_1 = '{ + // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h00000000}, end_addr: {32'h0000000f}}, + // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h0000ffff}}, + // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h0000000f}, end_addr: {32'h000000ff}}, + // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h000000ff}, end_addr: {32'h00000fff}}, + // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h0000ffff}, end_addr: {32'hffffffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2_2 = '{ + // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h00000000}, end_addr: {32'h0000000f}}, + // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h0000000f}, end_addr: {32'h000000ff}}, + // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h000000ff}, end_addr: {32'h00000fff}}, + // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h0000ffff}}, + // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h0000ffff}, end_addr: {32'hffffffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2_3 = '{ + // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h0000ffff}}, + // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h00000000}, end_addr: {32'h0000000f}}, + // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h0000000f}, end_addr: {32'h000000ff}}, + // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h000000ff}, end_addr: {32'h00000fff}}, + // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h0000ffff}, end_addr: {32'hffffffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // //////////////////////////////// Mixed accesses (max 2 hop) end ////////////////////////////////////// + + // //////////////////////////////// Mixed accesses (max 1 hop) start ////////////////////////////////////// + + // localparam rule_t [xbar_cfg_0.NoAddrRules-1:0] AddrMap_xp0 = '{ + // '{idx: 32'd2 % NoSlvPorts_0, start_addr: {32'h0fffffff}, end_addr: {32'hffffffff}}, + // '{idx: 32'd1 % NoSlvPorts_0, start_addr: {32'h00000fff}, end_addr: {32'h0fffffff}}, + // '{idx: 32'd0 % NoSlvPorts_0, start_addr: {32'h00000000}, end_addr: {32'h00000fff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp1 = '{ + // '{idx: 32'd3 % NoSlvPorts_1, start_addr: {32'h0000000f}, end_addr: {32'h000000ff}}, + // '{idx: 32'd2 % NoSlvPorts_1, start_addr: {32'h000000ff}, end_addr: {32'h00000fff}}, + // '{idx: 32'd1 % NoSlvPorts_1, start_addr: {32'h00000000}, end_addr: {32'h0000000f}}, + // '{idx: 32'd0 % NoSlvPorts_1, start_addr: {32'h00000fff}, end_addr: {32'hffffffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2 = '{ + // // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'b0}, end_addr: {32'h00000fff}}, + // // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h000fffff}}, + // // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h000fffff}, end_addr: {32'h00ffffff}}, + // // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h00ffffff}, end_addr: {32'h0fffffff}}, + // // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h0fffffff}, end_addr: {32'hffffffff}} + // // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // // }; + + // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2_1 = '{ + // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h00000000}, end_addr: {32'h0000000f}}, + // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h0000000f}, end_addr: {32'h000000ff}}, + // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h0000ffff}}, + // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h0000ffff}, end_addr: {32'hffffffff}}, + // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h000000ff}, end_addr: {32'h00000fff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2_2 = '{ + // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h00000000}, end_addr: {32'h0000000f}}, + // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h0000000f}, end_addr: {32'h000000ff}}, + // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h000000ff}, end_addr: {32'h00000fff}}, + // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h0000ffff}, end_addr: {32'hffffffff}}, + // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h0000ffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2_3 = '{ + // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h0000ffff}}, + // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h00000000}, end_addr: {32'h0000000f}}, + // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h0000000f}, end_addr: {32'h000000ff}}, + // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h0000ffff}, end_addr: {32'hffffffff}}, + // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h000000ff}, end_addr: {32'h00000fff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // //////////////////////////////// Mixed accesses (max 1 hop) end ////////////////////////////////////// + + //////////////////////////////// Uniform random start ////////////////////////////////////// + + ////// row 1 + + localparam rule_t [xbar_cfg_0.NoAddrRules-1:0] AddrMap_xp0 = '{ + '{idx: 32'd2 % NoSlvPorts_0, start_addr: {32'h00000000}, end_addr: {32'hc0000000}}, + '{idx: 32'd1 % NoSlvPorts_0, start_addr: {32'hd0000000}, end_addr: {32'hffffffff}}, + '{idx: 32'd0 % NoSlvPorts_0, start_addr: {32'hc0000000}, end_addr: {32'hd0000000}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp1 = '{ + '{idx: 32'd3 % NoSlvPorts_1, start_addr: {32'he0000000}, end_addr: {32'hffffffff}}, + '{idx: 32'd2 % NoSlvPorts_1, start_addr: {32'h00000000}, end_addr: {32'hc0000000}}, + '{idx: 32'd1 % NoSlvPorts_1, start_addr: {32'hc0000000}, end_addr: {32'hd0000000}}, + '{idx: 32'd0 % NoSlvPorts_1, start_addr: {32'hd0000000}, end_addr: {32'he0000000}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp2 = '{ + '{idx: 32'd3 % NoSlvPorts_1, start_addr: {32'hc0000000}, end_addr: {32'he0000000}}, + '{idx: 32'd2 % NoSlvPorts_1, start_addr: {32'h00000000}, end_addr: {32'hc0000000}}, + '{idx: 32'd1 % NoSlvPorts_1, start_addr: {32'hf0000000}, end_addr: {32'hffffffff}}, + '{idx: 32'd0 % NoSlvPorts_1, start_addr: {32'he0000000}, end_addr: {32'hf0000000}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_0.NoAddrRules-1:0] AddrMap_xp3 = '{ + '{idx: 32'd2 % NoSlvPorts_0, start_addr: {32'h00000000}, end_addr: {32'hc0000000}}, + '{idx: 32'd1 % NoSlvPorts_0, start_addr: {32'hc0000000}, end_addr: {32'hf0000000}}, + '{idx: 32'd0 % NoSlvPorts_0, start_addr: {32'hf0000000}, end_addr: {32'hffffffff}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + ////// row 2 + + localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp4 = '{ + '{idx: 32'd3 % NoSlvPorts_1, start_addr: {32'h00000000}, end_addr: {32'h80000000}}, + '{idx: 32'd2 % NoSlvPorts_1, start_addr: {32'hc0000000}, end_addr: {32'hffffffff}}, + '{idx: 32'd1 % NoSlvPorts_1, start_addr: {32'h90000000}, end_addr: {32'hc0000000}}, + '{idx: 32'd0 % NoSlvPorts_1, start_addr: {32'h80000000}, end_addr: {32'h90000000}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp5 = '{ + '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h00000000}, end_addr: {32'h80000000}}, + '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'ha0000000}, end_addr: {32'hc0000000}}, + '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'hc0000000}, end_addr: {32'hffffffff}}, + '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h80000000}, end_addr: {32'h90000000}}, + '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h90000000}, end_addr: {32'ha0000000}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp6 = '{ + '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h00000000}, end_addr: {32'h80000000}}, + '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h80000000}, end_addr: {32'ha0000000}}, + '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'hc0000000}, end_addr: {32'hffffffff}}, + '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'hb0000000}, end_addr: {32'hc0000000}}, + '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'ha0000000}, end_addr: {32'hb0000000}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp7 = '{ + '{idx: 32'd3 % NoSlvPorts_1, start_addr: {32'h00000000}, end_addr: {32'h80000000}}, + '{idx: 32'd2 % NoSlvPorts_1, start_addr: {32'hc0000000}, end_addr: {32'hffffffff}}, + '{idx: 32'd1 % NoSlvPorts_1, start_addr: {32'h80000000}, end_addr: {32'hb0000000}}, + '{idx: 32'd0 % NoSlvPorts_1, start_addr: {32'hb0000000}, end_addr: {32'hc0000000}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + ////// row 3 + + localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp8 = '{ + '{idx: 32'd3 % NoSlvPorts_1, start_addr: {32'h80000000}, end_addr: {32'hffffffff}}, + '{idx: 32'd2 % NoSlvPorts_1, start_addr: {32'h00000000}, end_addr: {32'h40000000}}, + '{idx: 32'd1 % NoSlvPorts_1, start_addr: {32'h50000000}, end_addr: {32'h80000000}}, + '{idx: 32'd0 % NoSlvPorts_1, start_addr: {32'h40000000}, end_addr: {32'h50000000}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp9 = '{ + '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h80000000}, end_addr: {32'hffffffff}}, + '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h60000000}, end_addr: {32'h80000000}}, + '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h00000000}, end_addr: {32'h40000000}}, + '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h40000000}, end_addr: {32'h50000000}}, + '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h50000000}, end_addr: {32'h60000000}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp10 = '{ + '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h80000000}, end_addr: {32'hffffffff}}, + '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h40000000}, end_addr: {32'h60000000}}, + '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h00000000}, end_addr: {32'h40000000}}, + '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h70000000}, end_addr: {32'h80000000}}, + '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h60000000}, end_addr: {32'h70000000}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp11 = '{ + '{idx: 32'd3 % NoSlvPorts_1, start_addr: {32'h80000000}, end_addr: {32'hffffffff}}, + '{idx: 32'd2 % NoSlvPorts_1, start_addr: {32'h00000000}, end_addr: {32'h40000000}}, + '{idx: 32'd1 % NoSlvPorts_1, start_addr: {32'h40000000}, end_addr: {32'h70000000}}, + '{idx: 32'd0 % NoSlvPorts_1, start_addr: {32'h70000000}, end_addr: {32'h80000000}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + ////// row 4 + + localparam rule_t [xbar_cfg_0.NoAddrRules-1:0] AddrMap_xp12 = '{ + '{idx: 32'd2 % NoSlvPorts_0, start_addr: {32'h40000000}, end_addr: {32'hffffffff}}, + '{idx: 32'd1 % NoSlvPorts_0, start_addr: {32'h10000000}, end_addr: {32'h40000000}}, + '{idx: 32'd0 % NoSlvPorts_0, start_addr: {32'h00000000}, end_addr: {32'h10000000}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp13 = '{ + '{idx: 32'd3 % NoSlvPorts_1, start_addr: {32'h20000000}, end_addr: {32'h40000000}}, + '{idx: 32'd2 % NoSlvPorts_1, start_addr: {32'h40000000}, end_addr: {32'hffffffff}}, + '{idx: 32'd1 % NoSlvPorts_1, start_addr: {32'h00000000}, end_addr: {32'h10000000}}, + '{idx: 32'd0 % NoSlvPorts_1, start_addr: {32'h10000000}, end_addr: {32'h20000000}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp14 = '{ + '{idx: 32'd3 % NoSlvPorts_1, start_addr: {32'h00000000}, end_addr: {32'h20000000}}, + '{idx: 32'd2 % NoSlvPorts_1, start_addr: {32'h40000000}, end_addr: {32'hffffffff}}, + '{idx: 32'd1 % NoSlvPorts_1, start_addr: {32'h30000000}, end_addr: {32'h40000000}}, + '{idx: 32'd0 % NoSlvPorts_1, start_addr: {32'h20000000}, end_addr: {32'h30000000}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_0.NoAddrRules-1:0] AddrMap_xp15 = '{ + '{idx: 32'd2 % NoSlvPorts_0, start_addr: {32'h40000000}, end_addr: {32'hffffffff}}, + '{idx: 32'd1 % NoSlvPorts_0, start_addr: {32'h00000000}, end_addr: {32'h30000000}}, + '{idx: 32'd0 % NoSlvPorts_0, start_addr: {32'h30000000}, end_addr: {32'h40000000}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + //////////////////////////////// Uniform random end ////////////////////////////////////// + + //localparam rule_t [xbar_cfg_0.NoAddrRules-1:0] AddrMap_xp0 = '{ + // '{idx: 32'd0 % NoSlvPorts_0, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + //}; + + typedef union packed { + logic [StrbWidth-1:0][7:0] bytes; + logic [DataWidth-1:0] data; + } block_t; + + /// Address Type + typedef logic [ AddrWidth-1:0] addr_t; + /// Data Type + typedef logic [ DataWidth-1:0] data_t; + /// Strobe Type + typedef logic [ StrbWidth-1:0] strb_t; + /// AXI ID Type + typedef logic [ IdWidth-1:0] axi_id_t; + /// AXI USER Type + typedef logic [ UserWidth-1:0] user_t; + /// 1D burst request + typedef struct packed { + axi_id_t id; + addr_t src, dst, num_bytes; + axi_pkg::cache_t cache_src, cache_dst; + axi_pkg::burst_t burst_src, burst_dst; + logic decouple_rw; + logic deburst; + logic serialize; + } burst_req_t; + + // master AXI bus --> DMA + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_dma_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_dma_t, axi_id_t, user_t) + + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_dma_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_dma_t, data_t, axi_id_t, user_t) + + `AXI_TYPEDEF_REQ_T(dma_req_t, aw_chan_dma_t, w_chan_t, ar_chan_dma_t) + `AXI_TYPEDEF_RESP_T(dma_resp_t, b_chan_dma_t, r_chan_dma_t) + + // slave AXI bus --> mem + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_mem_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_mem_t, axi_id_t, user_t) + + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_mem_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_mem_t, data_t, axi_id_t, user_t) + + `AXI_TYPEDEF_REQ_T(mem_req_t, aw_chan_mem_t, w_chan_t, ar_chan_mem_t) + `AXI_TYPEDEF_RESP_T(mem_resp_t, b_chan_mem_t, r_chan_mem_t) + + //-------------------------------------- + // Clock and Reset + //-------------------------------------- + logic clk; + initial begin + forever begin + clk = 0; + #HalfPeriod; + clk = 1; + #HalfPeriod; + end + end + + logic rst_n; + initial begin + rst_n = 0; + #Reset; + rst_n = 1; + end + + task wait_for_reset; + @(posedge rst_n); + @(posedge clk); + endtask + + //-------------------------------------- + // DUT Axi busses + //-------------------------------------- + + dma_req_t [NoMst-1:0] axi_dma_req; + dma_resp_t [NoMst-1:0] axi_dma_res; + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) dma [NoMst-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) dma_sync [NoMst-1:0] (); + + AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) dma_dv [NoMst-1:0] (clk); + + for (genvar i = 0; i < NoMst; i++) begin : gen_conn_dv_masters + //`AXI_ASSIGN (dma_dv[i], dma[i]) + `AXI_ASSIGN_FROM_REQ(dma[i], axi_dma_req[i]) + `AXI_ASSIGN_TO_RESP(axi_dma_res[i], dma[i]) + end + + ////////////////////////////////////////// Row 1 ///////////////////////////////////////// + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_mst [NoMstPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_mst_2 [0:0] (); + + `AXI_ASSIGN (mem_0[0], xp0_mst[0]) + `AXI_ASSIGN (xp0_mst_1[0], xp0_mst[1]) + `AXI_ASSIGN (xp0_mst_2[0], xp0_mst[2]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_slv [NoSlvPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_slv_2 [0:0] (); + + `AXI_ASSIGN (xp0_slv[0], dma_sync[0]) + `AXI_ASSIGN (xp0_slv[1], xp0_slv_1[0]) + `AXI_ASSIGN (xp0_slv[2], xp0_slv_2[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_mst [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_mst_3 [0:0] (); + + `AXI_ASSIGN (mem_0[1], xp1_mst[0]) + `AXI_ASSIGN (xp1_mst_1[0], xp1_mst[1]) + `AXI_ASSIGN (xp1_mst_2[0], xp1_mst[2]) + `AXI_ASSIGN (xp1_mst_3[0], xp1_mst[3]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_slv_3 [0:0] (); + + `AXI_ASSIGN (xp1_slv[0], dma_sync[1]) + `AXI_ASSIGN (xp1_slv[1], xp1_slv_1[0]) + `AXI_ASSIGN (xp1_slv[2], xp1_slv_2[0]) + `AXI_ASSIGN (xp1_slv[3], xp1_slv_3[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_mst [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_mst_3 [0:0] (); + + `AXI_ASSIGN (mem_0[2], xp2_mst[0]) + `AXI_ASSIGN (xp2_mst_1[0], xp2_mst[1]) + `AXI_ASSIGN (xp2_mst_2[0], xp2_mst[2]) + `AXI_ASSIGN (xp2_mst_3[0], xp2_mst[3]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_slv_3 [0:0] (); + + `AXI_ASSIGN (xp2_slv[0], dma_sync[2]) + `AXI_ASSIGN (xp2_slv[1], xp2_slv_1[0]) + `AXI_ASSIGN (xp2_slv[2], xp2_slv_2[0]) + `AXI_ASSIGN (xp2_slv[3], xp2_slv_3[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_mst [NoMstPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_mst_2 [0:0] (); + + `AXI_ASSIGN (mem_0[3], xp3_mst[0]) + `AXI_ASSIGN (xp3_mst_1[0], xp3_mst[1]) + `AXI_ASSIGN (xp3_mst_2[0], xp3_mst[2]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_slv [NoSlvPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_slv_2 [0:0] (); + + `AXI_ASSIGN (xp3_slv[0], dma_sync[3]) + `AXI_ASSIGN (xp3_slv[1], xp3_slv_1[0]) + `AXI_ASSIGN (xp3_slv[2], xp3_slv_2[0]) + + /////////////////////////////////////////// Row 2 //////////////////////////////////////////////// + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp4_mst [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp4_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp4_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp4_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp4_mst_3 [0:0] (); + + `AXI_ASSIGN (mem_0[4], xp4_mst[0]) + `AXI_ASSIGN (xp4_mst_1[0], xp4_mst[1]) + `AXI_ASSIGN (xp4_mst_2[0], xp4_mst[2]) + `AXI_ASSIGN (xp4_mst_3[0], xp4_mst[3]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp4_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp4_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp4_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp4_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp4_slv_3 [0:0] (); + + `AXI_ASSIGN (xp4_slv[0], dma_sync[4]) + `AXI_ASSIGN (xp4_slv[1], xp4_slv_1[0]) + `AXI_ASSIGN (xp4_slv[2], xp4_slv_2[0]) + `AXI_ASSIGN (xp4_slv[3], xp4_slv_3[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_mst [NoMstPorts_2-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_mst_3 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_mst_4 [0:0] (); + + `AXI_ASSIGN (mem_0[5], xp5_mst[0]) + `AXI_ASSIGN (xp5_mst_1[0], xp5_mst[1]) + `AXI_ASSIGN (xp5_mst_2[0], xp5_mst[2]) + `AXI_ASSIGN (xp5_mst_3[0], xp5_mst[3]) + `AXI_ASSIGN (xp5_mst_4[0], xp5_mst[4]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_slv [NoSlvPorts_2-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_slv_3 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_slv_4 [0:0] (); + + `AXI_ASSIGN (xp5_slv[0], dma_sync[5]) + `AXI_ASSIGN (xp5_slv[1], xp5_slv_1[0]) + `AXI_ASSIGN (xp5_slv[2], xp5_slv_2[0]) + `AXI_ASSIGN (xp5_slv[3], xp5_slv_3[0]) + `AXI_ASSIGN (xp5_slv[4], xp5_slv_4[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_mst [NoMstPorts_2-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_mst_3 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_mst_4 [0:0] (); + + `AXI_ASSIGN (mem_0[6], xp6_mst[0]) + `AXI_ASSIGN (xp6_mst_1[0], xp6_mst[1]) + `AXI_ASSIGN (xp6_mst_2[0], xp6_mst[2]) + `AXI_ASSIGN (xp6_mst_3[0], xp6_mst[3]) + `AXI_ASSIGN (xp6_mst_4[0], xp6_mst[4]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_slv [NoSlvPorts_2-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_slv_3 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_slv_4 [0:0] (); + + `AXI_ASSIGN (xp6_slv[0], dma_sync[6]) + `AXI_ASSIGN (xp6_slv[1], xp6_slv_1[0]) + `AXI_ASSIGN (xp6_slv[2], xp6_slv_2[0]) + `AXI_ASSIGN (xp6_slv[3], xp6_slv_3[0]) + `AXI_ASSIGN (xp6_slv[4], xp6_slv_4[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp7_mst [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp7_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp7_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp7_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp7_mst_3 [0:0] (); + + `AXI_ASSIGN (mem_0[7], xp7_mst[0]) + `AXI_ASSIGN (xp7_mst_1[0], xp7_mst[1]) + `AXI_ASSIGN (xp7_mst_2[0], xp7_mst[2]) + `AXI_ASSIGN (xp7_mst_3[0], xp7_mst[3]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp7_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp7_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp7_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp7_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp7_slv_3 [0:0] (); + + `AXI_ASSIGN (xp7_slv[0], dma_sync[7]) + `AXI_ASSIGN (xp7_slv[1], xp7_slv_1[0]) + `AXI_ASSIGN (xp7_slv[2], xp7_slv_2[0]) + `AXI_ASSIGN (xp7_slv[3], xp7_slv_3[0]) + + /////////////////////////////////////////// Row 3 //////////////////////////////////////////////// + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp8_mst [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp8_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp8_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp8_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp8_mst_3 [0:0] (); + + `AXI_ASSIGN (mem_0[8], xp8_mst[0]) + `AXI_ASSIGN (xp8_mst_1[0], xp8_mst[1]) + `AXI_ASSIGN (xp8_mst_2[0], xp8_mst[2]) + `AXI_ASSIGN (xp8_mst_3[0], xp8_mst[3]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp8_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp8_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp8_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp8_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp8_slv_3 [0:0] (); + + `AXI_ASSIGN (xp8_slv[0], dma_sync[8]) + `AXI_ASSIGN (xp8_slv[1], xp8_slv_1[0]) + `AXI_ASSIGN (xp8_slv[2], xp8_slv_2[0]) + `AXI_ASSIGN (xp8_slv[3], xp8_slv_3[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_mst [NoMstPorts_2-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_mst_3 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_mst_4 [0:0] (); + + `AXI_ASSIGN (mem_0[9], xp9_mst[0]) + `AXI_ASSIGN (xp9_mst_1[0], xp9_mst[1]) + `AXI_ASSIGN (xp9_mst_2[0], xp9_mst[2]) + `AXI_ASSIGN (xp9_mst_3[0], xp9_mst[3]) + `AXI_ASSIGN (xp9_mst_4[0], xp9_mst[4]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_slv [NoSlvPorts_2-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_slv_3 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_slv_4 [0:0] (); + + `AXI_ASSIGN (xp9_slv[0], dma_sync[9]) + `AXI_ASSIGN (xp9_slv[1], xp9_slv_1[0]) + `AXI_ASSIGN (xp9_slv[2], xp9_slv_2[0]) + `AXI_ASSIGN (xp9_slv[3], xp9_slv_3[0]) + `AXI_ASSIGN (xp9_slv[4], xp9_slv_4[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_mst [NoMstPorts_2-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_mst_3 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_mst_4 [0:0] (); + + `AXI_ASSIGN (mem_0[10], xp10_mst[0]) + `AXI_ASSIGN (xp10_mst_1[0], xp10_mst[1]) + `AXI_ASSIGN (xp10_mst_2[0], xp10_mst[2]) + `AXI_ASSIGN (xp10_mst_3[0], xp10_mst[3]) + `AXI_ASSIGN (xp10_mst_4[0], xp10_mst[4]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_slv [NoSlvPorts_2-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_slv_3 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_slv_4 [0:0] (); + + `AXI_ASSIGN (xp10_slv[0], dma_sync[10]) + `AXI_ASSIGN (xp10_slv[1], xp10_slv_1[0]) + `AXI_ASSIGN (xp10_slv[2], xp10_slv_2[0]) + `AXI_ASSIGN (xp10_slv[3], xp10_slv_3[0]) + `AXI_ASSIGN (xp10_slv[4], xp10_slv_4[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp11_mst [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp11_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp11_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp11_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp11_mst_3 [0:0] (); + + `AXI_ASSIGN (mem_0[11], xp11_mst[0]) + `AXI_ASSIGN (xp11_mst_1[0], xp11_mst[1]) + `AXI_ASSIGN (xp11_mst_2[0], xp11_mst[2]) + `AXI_ASSIGN (xp11_mst_3[0], xp11_mst[3]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp11_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp11_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp11_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp11_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp11_slv_3 [0:0] (); + + `AXI_ASSIGN (xp11_slv[0], dma_sync[11]) + `AXI_ASSIGN (xp11_slv[1], xp11_slv_1[0]) + `AXI_ASSIGN (xp11_slv[2], xp11_slv_2[0]) + `AXI_ASSIGN (xp11_slv[3], xp11_slv_3[0]) + + ////////////////////////////////////////////// Row 4 /////////////////////////////////////////// + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp12_mst [NoMstPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp12_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp12_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp12_mst_2 [0:0] (); + + `AXI_ASSIGN (mem_0[12], xp12_mst[0]) + `AXI_ASSIGN (xp12_mst_1[0], xp12_mst[1]) + `AXI_ASSIGN (xp12_mst_2[0], xp12_mst[2]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp12_slv [NoSlvPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp12_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp12_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp12_slv_2 [0:0] (); + + `AXI_ASSIGN (xp12_slv[0], dma_sync[12]) + `AXI_ASSIGN (xp12_slv[1], xp12_slv_1[0]) + `AXI_ASSIGN (xp12_slv[2], xp12_slv_2[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp13_mst [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp13_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp13_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp13_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp13_mst_3 [0:0] (); + + `AXI_ASSIGN (mem_0[13], xp13_mst[0]) + `AXI_ASSIGN (xp13_mst_1[0], xp13_mst[1]) + `AXI_ASSIGN (xp13_mst_2[0], xp13_mst[2]) + `AXI_ASSIGN (xp13_mst_3[0], xp13_mst[3]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp13_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp13_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp13_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp13_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp13_slv_3 [0:0] (); + + `AXI_ASSIGN (xp13_slv[0], dma_sync[13]) + `AXI_ASSIGN (xp13_slv[1], xp13_slv_1[0]) + `AXI_ASSIGN (xp13_slv[2], xp13_slv_2[0]) + `AXI_ASSIGN (xp13_slv[3], xp13_slv_3[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp14_mst [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp14_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp14_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp14_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp14_mst_3 [0:0] (); + + `AXI_ASSIGN (mem_0[14], xp14_mst[0]) + `AXI_ASSIGN (xp14_mst_1[0], xp14_mst[1]) + `AXI_ASSIGN (xp14_mst_2[0], xp14_mst[2]) + `AXI_ASSIGN (xp14_mst_3[0], xp14_mst[3]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp14_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp14_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp14_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp14_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp14_slv_3 [0:0] (); + + `AXI_ASSIGN (xp14_slv[0], dma_sync[14]) + `AXI_ASSIGN (xp14_slv[1], xp14_slv_1[0]) + `AXI_ASSIGN (xp14_slv[2], xp14_slv_2[0]) + `AXI_ASSIGN (xp14_slv[3], xp14_slv_3[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp15_mst [NoMstPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp15_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp15_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp15_mst_2 [0:0] (); + + `AXI_ASSIGN (mem_0[15], xp15_mst[0]) + `AXI_ASSIGN (xp15_mst_1[0], xp15_mst[1]) + `AXI_ASSIGN (xp15_mst_2[0], xp15_mst[2]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp15_slv [NoSlvPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp15_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp15_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp15_slv_2 [0:0] (); + + `AXI_ASSIGN (xp15_slv[0], dma_sync[15]) + `AXI_ASSIGN (xp15_slv[1], xp15_slv_1[0]) + `AXI_ASSIGN (xp15_slv[2], xp15_slv_2[0]) + + // XP0 <--> XP1 + + `AXI_ASSIGN (xp1_slv_1[0], xp0_mst_1[0]) + `AXI_ASSIGN (xp0_slv_1[0], xp1_mst_1[0]) + + // XP0 <--> XP4 + + `AXI_ASSIGN (xp4_slv_2[0], xp0_mst_2[0]) + `AXI_ASSIGN (xp0_slv_2[0], xp4_mst_2[0]) + + // XP1 <--> XP2 + + `AXI_ASSIGN (xp2_slv_3[0], xp1_mst_3[0]) + `AXI_ASSIGN (xp1_slv_3[0], xp2_mst_3[0]) + + // XP1 <--> XP5 + + `AXI_ASSIGN (xp5_slv_2[0], xp1_mst_2[0]) + `AXI_ASSIGN (xp1_slv_2[0], xp5_mst_2[0]) + + // XP2 <--> XP3 + + `AXI_ASSIGN (xp2_slv_1[0], xp3_mst_1[0]) + `AXI_ASSIGN (xp3_slv_1[0], xp2_mst_1[0]) + + // XP2 <--> XP6 + + `AXI_ASSIGN (xp6_slv_2[0], xp2_mst_2[0]) + `AXI_ASSIGN (xp2_slv_2[0], xp6_mst_2[0]) + + // XP3 <--> XP7 + + `AXI_ASSIGN (xp7_slv_2[0], xp3_mst_2[0]) + `AXI_ASSIGN (xp3_slv_2[0], xp7_mst_2[0]) + + // XP4 <--> XP5 + + `AXI_ASSIGN (xp5_slv_1[0], xp4_mst_1[0]) + `AXI_ASSIGN (xp4_slv_1[0], xp5_mst_1[0]) + + // XP4 <--> XP8 + + `AXI_ASSIGN (xp8_slv_3[0], xp4_mst_3[0]) + `AXI_ASSIGN (xp4_slv_3[0], xp8_mst_3[0]) + + // XP5 <--> XP6 + + `AXI_ASSIGN (xp6_slv_3[0], xp5_mst_3[0]) + `AXI_ASSIGN (xp5_slv_3[0], xp6_mst_3[0]) + + // XP5 <--> XP9 + + `AXI_ASSIGN (xp9_slv_4[0], xp5_mst_4[0]) + `AXI_ASSIGN (xp5_slv_4[0], xp9_mst_4[0]) + + // XP6 <--> XP7 + + `AXI_ASSIGN (xp7_slv_1[0], xp6_mst_1[0]) + `AXI_ASSIGN (xp6_slv_1[0], xp7_mst_1[0]) + + // XP6 <--> XP10 + + `AXI_ASSIGN (xp10_slv_4[0], xp6_mst_4[0]) + `AXI_ASSIGN (xp6_slv_4[0], xp10_mst_4[0]) + + // XP7 <--> XP11 + + `AXI_ASSIGN (xp11_slv_3[0], xp7_mst_3[0]) + `AXI_ASSIGN (xp7_slv_3[0], xp11_mst_3[0]) + + // XP8 <--> XP9 + + `AXI_ASSIGN (xp9_slv_1[0], xp8_mst_1[0]) + `AXI_ASSIGN (xp8_slv_1[0], xp9_mst_1[0]) + + // XP8 <--> XP12 + + `AXI_ASSIGN (xp12_slv_2[0], xp8_mst_2[0]) + `AXI_ASSIGN (xp8_slv_2[0], xp12_mst_2[0]) + + // XP9 <--> XP10 + + `AXI_ASSIGN (xp10_slv_3[0], xp9_mst_3[0]) + `AXI_ASSIGN (xp9_slv_3[0], xp10_mst_3[0]) + + // XP9 <--> XP13 + + `AXI_ASSIGN (xp13_slv_2[0], xp9_mst_2[0]) + `AXI_ASSIGN (xp9_slv_2[0], xp13_mst_2[0]) + + // XP10 <--> XP11 + + `AXI_ASSIGN (xp11_slv_1[0], xp10_mst_1[0]) + `AXI_ASSIGN (xp10_slv_1[0], xp11_mst_1[0]) + + // XP10 <--> XP14 + + `AXI_ASSIGN (xp14_slv_2[0], xp10_mst_2[0]) + `AXI_ASSIGN (xp10_slv_2[0], xp14_mst_2[0]) + + // XP11 <--> XP15 + + `AXI_ASSIGN (xp15_slv_2[0], xp11_mst_2[0]) + `AXI_ASSIGN (xp11_slv_2[0], xp15_mst_2[0]) + + // XP12 <--> XP13 + + `AXI_ASSIGN (xp13_slv_1[0], xp12_mst_1[0]) + `AXI_ASSIGN (xp12_slv_1[0], xp13_mst_1[0]) + + // XP13 <--> XP14 + + `AXI_ASSIGN (xp14_slv_3[0], xp13_mst_3[0]) + `AXI_ASSIGN (xp13_slv_3[0], xp14_mst_3[0]) + + // XP14 <--> XP15 + + `AXI_ASSIGN (xp15_slv_1[0], xp14_mst_1[0]) + `AXI_ASSIGN (xp14_slv_1[0], xp15_mst_1[0]) + + AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) mem_dv [NoSlv-1:0] (clk); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) mem_0 [NoSlv-1:0] (); + + `AXI_ASSIGN (mem_dv[0], mem_0[0]) + `AXI_ASSIGN (mem_dv[1], mem_0[1]) + `AXI_ASSIGN (mem_dv[2], mem_0[2]) + `AXI_ASSIGN (mem_dv[3], mem_0[3]) + `AXI_ASSIGN (mem_dv[4], mem_0[4]) + `AXI_ASSIGN (mem_dv[5], mem_0[5]) + `AXI_ASSIGN (mem_dv[6], mem_0[6]) + `AXI_ASSIGN (mem_dv[7], mem_0[7]) + `AXI_ASSIGN (mem_dv[8], mem_0[8]) + `AXI_ASSIGN (mem_dv[9], mem_0[9]) + `AXI_ASSIGN (mem_dv[10], mem_0[10]) + `AXI_ASSIGN (mem_dv[11], mem_0[11]) + `AXI_ASSIGN (mem_dv[12], mem_0[12]) + `AXI_ASSIGN (mem_dv[13], mem_0[13]) + `AXI_ASSIGN (mem_dv[14], mem_0[14]) + `AXI_ASSIGN (mem_dv[15], mem_0[15]) + + //`AXI_ASSIGN (mem_dv[1], mem_1[0]) + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma1_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma2_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma3_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma4_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma5_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma6_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma7_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma8_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma9_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma10_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma11_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma12_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma13_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma14_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma15_t; + + driver_dma_t driver_dma = new(mem_dv[0]); + driver_dma1_t driver_dma1 = new(mem_dv[1]); + driver_dma2_t driver_dma2 = new(mem_dv[2]); + driver_dma3_t driver_dma3 = new(mem_dv[3]); + driver_dma4_t driver_dma4 = new(mem_dv[4]); + driver_dma5_t driver_dma5 = new(mem_dv[5]); + driver_dma6_t driver_dma6 = new(mem_dv[6]); + driver_dma7_t driver_dma7 = new(mem_dv[7]); + driver_dma8_t driver_dma8 = new(mem_dv[8]); + driver_dma9_t driver_dma9 = new(mem_dv[9]); + driver_dma10_t driver_dma10 = new(mem_dv[10]); + driver_dma11_t driver_dma11 = new(mem_dv[11]); + driver_dma12_t driver_dma12 = new(mem_dv[12]); + driver_dma13_t driver_dma13 = new(mem_dv[13]); + driver_dma14_t driver_dma14 = new(mem_dv[14]); + driver_dma15_t driver_dma15 = new(mem_dv[15]); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem0 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[0]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem1 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[1]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem2 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[2]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem3 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[3]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem4 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[4]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem5 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[5]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem6 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[6]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem7 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[7]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem8 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[8]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem9 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[9]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem10 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[10]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem11 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[11]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem12 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[12]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem13 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[13]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem14 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[14]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem15 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[15]) + ); + + // initial begin + // $readmemh("sim_mem0.mem", i_sim_mem0.mem); + // $readmemh("sim_mem1.mem", i_sim_mem1.mem); + // end + + //-------------------------------------- + // DUT AXI Memory System + //-------------------------------------- + // lfsr + logic [784:0] lfsr_dut_q, lfsr_dut_d; + + // transaction id + logic [ 7:0] transaction_id = 0; + + // Memory + block_t dma_memory [bit [AddrWidth-$clog2($bits(block_t))-1:0]]; + block_t dma_memory1 [bit [AddrWidth-$clog2($bits(block_t))-1:0]]; + + //-------------------------------------- + // DMA instantiation + //-------------------------------------- + burst_req_t burst0_req; + burst_req_t burst1_req; + logic burst0_req_valid; + logic burst1_req_valid; + logic burst0_req_ready; + logic burst1_req_ready; + logic backend_idle_0; + logic backend_idle_1; + burst_req_t burst2_req; + burst_req_t burst3_req; + logic burst2_req_valid; + logic burst3_req_valid; + logic burst2_req_ready; + logic burst3_req_ready; + logic backend_idle_2; + logic backend_idle_3; + burst_req_t burst4_req; + burst_req_t burst5_req; + logic burst4_req_valid; + logic burst5_req_valid; + logic burst4_req_ready; + logic burst5_req_ready; + logic backend_idle_4; + logic backend_idle_5; + burst_req_t burst6_req; + burst_req_t burst7_req; + logic burst6_req_valid; + logic burst7_req_valid; + logic burst6_req_ready; + logic burst7_req_ready; + logic backend_idle_6; + logic backend_idle_7; + + burst_req_t burst8_req; + burst_req_t burst9_req; + logic burst8_req_valid; + logic burst9_req_valid; + logic burst8_req_ready; + logic burst9_req_ready; + logic backend_idle_8; + logic backend_idle_9; + burst_req_t burst10_req; + burst_req_t burst11_req; + logic burst10_req_valid; + logic burst11_req_valid; + logic burst10_req_ready; + logic burst11_req_ready; + logic backend_idle_10; + logic backend_idle_11; + burst_req_t burst12_req; + burst_req_t burst13_req; + logic burst12_req_valid; + logic burst13_req_valid; + logic burst12_req_ready; + logic burst13_req_ready; + logic backend_idle_12; + logic backend_idle_13; + burst_req_t burst14_req; + burst_req_t burst15_req; + logic burst14_req_valid; + logic burst15_req_valid; + logic burst14_req_ready; + logic burst15_req_ready; + logic backend_idle_14; + logic backend_idle_15; + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_0 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[0] ), + .axi_dma_res_i ( axi_dma_res[0] ), + .burst_req_i ( burst0_req ), + .valid_i ( burst0_req_valid ), + .ready_o ( burst0_req_ready ), + .backend_idle_o ( backend_idle_0 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000000 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_0 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[0] ), + .out ( dma_sync[0] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_1 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[1] ), + .axi_dma_res_i ( axi_dma_res[1] ), + .burst_req_i ( burst1_req ), + .valid_i ( burst1_req_valid ), + .ready_o ( burst1_req_ready ), + .backend_idle_o ( backend_idle_1 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000001 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_1 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[1] ), + .out ( dma_sync[1] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_2 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[2] ), + .axi_dma_res_i ( axi_dma_res[2] ), + .burst_req_i ( burst2_req ), + .valid_i ( burst2_req_valid ), + .ready_o ( burst2_req_ready ), + .backend_idle_o ( backend_idle_2 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000002 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_2 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[2] ), + .out ( dma_sync[2] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_3 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[3] ), + .axi_dma_res_i ( axi_dma_res[3] ), + .burst_req_i ( burst3_req ), + .valid_i ( burst3_req_valid ), + .ready_o ( burst3_req_ready ), + .backend_idle_o ( backend_idle_3 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000003 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_3 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[3] ), + .out ( dma_sync[3] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_4 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[4] ), + .axi_dma_res_i ( axi_dma_res[4] ), + .burst_req_i ( burst4_req ), + .valid_i ( burst4_req_valid ), + .ready_o ( burst4_req_ready ), + .backend_idle_o ( backend_idle_4 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000004 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_4 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[4] ), + .out ( dma_sync[4] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_5 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[5] ), + .axi_dma_res_i ( axi_dma_res[5] ), + .burst_req_i ( burst5_req ), + .valid_i ( burst5_req_valid ), + .ready_o ( burst5_req_ready ), + .backend_idle_o ( backend_idle_5 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000005 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_5 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[5] ), + .out ( dma_sync[5] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_6 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[6] ), + .axi_dma_res_i ( axi_dma_res[6] ), + .burst_req_i ( burst6_req ), + .valid_i ( burst6_req_valid ), + .ready_o ( burst6_req_ready ), + .backend_idle_o ( backend_idle_6 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000006 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_6 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[6] ), + .out ( dma_sync[6] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_7 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[7] ), + .axi_dma_res_i ( axi_dma_res[7] ), + .burst_req_i ( burst7_req ), + .valid_i ( burst7_req_valid ), + .ready_o ( burst7_req_ready ), + .backend_idle_o ( backend_idle_7 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000007 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_7 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[7] ), + .out ( dma_sync[7] ) + ); + + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_8 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[8] ), + .axi_dma_res_i ( axi_dma_res[8] ), + .burst_req_i ( burst8_req ), + .valid_i ( burst8_req_valid ), + .ready_o ( burst8_req_ready ), + .backend_idle_o ( backend_idle_8 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000008 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_8 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[8] ), + .out ( dma_sync[8] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_9 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[9] ), + .axi_dma_res_i ( axi_dma_res[9] ), + .burst_req_i ( burst9_req ), + .valid_i ( burst9_req_valid ), + .ready_o ( burst9_req_ready ), + .backend_idle_o ( backend_idle_9 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000009 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_9 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[9] ), + .out ( dma_sync[9] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_10 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[10] ), + .axi_dma_res_i ( axi_dma_res[10] ), + .burst_req_i ( burst10_req ), + .valid_i ( burst10_req_valid ), + .ready_o ( burst10_req_ready ), + .backend_idle_o ( backend_idle_10 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h0000000a ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_10 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[10] ), + .out ( dma_sync[10] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_11 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[11] ), + .axi_dma_res_i ( axi_dma_res[11] ), + .burst_req_i ( burst11_req ), + .valid_i ( burst11_req_valid ), + .ready_o ( burst11_req_ready ), + .backend_idle_o ( backend_idle_11 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h0000000b ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_11 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[11] ), + .out ( dma_sync[11] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_12 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[12] ), + .axi_dma_res_i ( axi_dma_res[12] ), + .burst_req_i ( burst12_req ), + .valid_i ( burst12_req_valid ), + .ready_o ( burst12_req_ready ), + .backend_idle_o ( backend_idle_12 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h0000000c ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_12 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[12] ), + .out ( dma_sync[12] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_13 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[13] ), + .axi_dma_res_i ( axi_dma_res[13] ), + .burst_req_i ( burst13_req ), + .valid_i ( burst13_req_valid ), + .ready_o ( burst13_req_ready ), + .backend_idle_o ( backend_idle_13 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h0000000d ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_13 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[13] ), + .out ( dma_sync[13] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_14 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[14] ), + .axi_dma_res_i ( axi_dma_res[14] ), + .burst_req_i ( burst14_req ), + .valid_i ( burst14_req_valid ), + .ready_o ( burst14_req_ready ), + .backend_idle_o ( backend_idle_14 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h0000000e ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_14 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[14] ), + .out ( dma_sync[14] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_15 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[15] ), + .axi_dma_res_i ( axi_dma_res[15] ), + .burst_req_i ( burst15_req ), + .valid_i ( burst15_req_valid ), + .ready_o ( burst15_req_ready ), + .backend_idle_o ( backend_idle_15 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h0000000f ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_15 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[15] ), + .out ( dma_sync[15] ) + ); + + //----------------------------------- + // DUT + //----------------------------------- + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_0 ), + .NoSlvPorts ( xbar_cfg_0.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_0.NoMstPorts ), + .Connectivity ( Connectivity_0 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_0.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_15 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp15_slv ), + .mst_ports ( xp15_mst ), + .addr_map_i ( AddrMap_xp15 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_14 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp14_slv ), + .mst_ports ( xp14_mst ), + .addr_map_i ( AddrMap_xp14 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_13 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp13_slv ), + .mst_ports ( xp13_mst ), + .addr_map_i ( AddrMap_xp13 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_0 ), + .NoSlvPorts ( xbar_cfg_0.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_0.NoMstPorts ), + .Connectivity ( Connectivity_0 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_0.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_12 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp12_slv ), + .mst_ports ( xp12_mst ), + .addr_map_i ( AddrMap_xp12 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_11 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp11_slv ), + .mst_ports ( xp11_mst ), + .addr_map_i ( AddrMap_xp11 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_2 ), + .NoSlvPorts ( xbar_cfg_2.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_2.NoMstPorts ), + .Connectivity ( Connectivity_2 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_2.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_10 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp10_slv ), + .mst_ports ( xp10_mst ), + .addr_map_i ( AddrMap_xp10 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_2 ), + .NoSlvPorts ( xbar_cfg_2.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_2.NoMstPorts ), + .Connectivity ( Connectivity_2 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_2.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_9 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp9_slv ), + .mst_ports ( xp9_mst ), + .addr_map_i ( AddrMap_xp9 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_8 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp8_slv ), + .mst_ports ( xp8_mst ), + .addr_map_i ( AddrMap_xp8 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_7 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp7_slv ), + .mst_ports ( xp7_mst ), + .addr_map_i ( AddrMap_xp7 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_2 ), + .NoSlvPorts ( xbar_cfg_2.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_2.NoMstPorts ), + .Connectivity ( Connectivity_2 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_2.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_6 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp6_slv ), + .mst_ports ( xp6_mst ), + .addr_map_i ( AddrMap_xp6 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_2 ), + .NoSlvPorts ( xbar_cfg_2.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_2.NoMstPorts ), + .Connectivity ( Connectivity_2 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_2.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_5 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp5_slv ), + .mst_ports ( xp5_mst ), + .addr_map_i ( AddrMap_xp5 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_4 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp4_slv ), + .mst_ports ( xp4_mst ), + .addr_map_i ( AddrMap_xp4 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_0 ), + .NoSlvPorts ( xbar_cfg_0.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_0.NoMstPorts ), + .Connectivity ( Connectivity_0 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_0.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_3 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp3_slv ), + .mst_ports ( xp3_mst ), + .addr_map_i ( AddrMap_xp3 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_2 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp2_slv ), + .mst_ports ( xp2_mst ), + .addr_map_i ( AddrMap_xp2 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_1 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp1_slv ), + .mst_ports ( xp1_mst ), + .addr_map_i ( AddrMap_xp1 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_0 ), + .NoSlvPorts ( xbar_cfg_0.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_0.NoMstPorts ), + .Connectivity ( Connectivity_0 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_0.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_0 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp0_slv ), + .mst_ports ( xp0_mst ), + .addr_map_i ( AddrMap_xp0 ) + ); + + //-------------------------------------- + // DMA DUT tasks + //-------------------------------------- + + task oned_dut_launch_15 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst15_req_valid <= 1'b0; + burst15_req <= '0; + @(posedge clk); + while (burst15_req_ready !== 1) @(posedge clk); + // write data + burst15_req.id <= transf_id_i; + burst15_req.src <= src_addr_i; + burst15_req.dst <= dst_addr_i; + burst15_req.num_bytes <= num_bytes_i; + burst15_req.cache_src <= src_cache_i; + burst15_req.cache_dst <= dst_cache_i; + burst15_req.burst_src <= src_burst_i; + burst15_req.burst_dst <= dst_burst_i; + burst15_req.decouple_rw <= decouple_rw_i; + burst15_req.deburst <= deburst_i; + burst15_req.serialize <= serialize_i; + burst15_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst15_req_valid <= 1'b0; + burst15_req <= '0; + endtask + + task oned_dut_launch_14 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst14_req_valid <= 1'b0; + burst14_req <= '0; + @(posedge clk); + while (burst14_req_ready !== 1) @(posedge clk); + // write data + burst14_req.id <= transf_id_i; + burst14_req.src <= src_addr_i; + burst14_req.dst <= dst_addr_i; + burst14_req.num_bytes <= num_bytes_i; + burst14_req.cache_src <= src_cache_i; + burst14_req.cache_dst <= dst_cache_i; + burst14_req.burst_src <= src_burst_i; + burst14_req.burst_dst <= dst_burst_i; + burst14_req.decouple_rw <= decouple_rw_i; + burst14_req.deburst <= deburst_i; + burst14_req.serialize <= serialize_i; + burst14_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst14_req_valid <= 1'b0; + burst14_req <= '0; + endtask + + task oned_dut_launch_13 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst13_req_valid <= 1'b0; + burst13_req <= '0; + @(posedge clk); + while (burst13_req_ready !== 1) @(posedge clk); + // write data + burst13_req.id <= transf_id_i; + burst13_req.src <= src_addr_i; + burst13_req.dst <= dst_addr_i; + burst13_req.num_bytes <= num_bytes_i; + burst13_req.cache_src <= src_cache_i; + burst13_req.cache_dst <= dst_cache_i; + burst13_req.burst_src <= src_burst_i; + burst13_req.burst_dst <= dst_burst_i; + burst13_req.decouple_rw <= decouple_rw_i; + burst13_req.deburst <= deburst_i; + burst13_req.serialize <= serialize_i; + burst13_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst13_req_valid <= 1'b0; + burst13_req <= '0; + endtask + + task oned_dut_launch_12 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst12_req_valid <= 1'b0; + burst12_req <= '0; + @(posedge clk); + while (burst12_req_ready !== 1) @(posedge clk); + // write data + burst12_req.id <= transf_id_i; + burst12_req.src <= src_addr_i; + burst12_req.dst <= dst_addr_i; + burst12_req.num_bytes <= num_bytes_i; + burst12_req.cache_src <= src_cache_i; + burst12_req.cache_dst <= dst_cache_i; + burst12_req.burst_src <= src_burst_i; + burst12_req.burst_dst <= dst_burst_i; + burst12_req.decouple_rw <= decouple_rw_i; + burst12_req.deburst <= deburst_i; + burst12_req.serialize <= serialize_i; + burst12_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst12_req_valid <= 1'b0; + burst12_req <= '0; + endtask + + task oned_dut_launch_11 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst11_req_valid <= 1'b0; + burst11_req <= '0; + @(posedge clk); + while (burst11_req_ready !== 1) @(posedge clk); + // write data + burst11_req.id <= transf_id_i; + burst11_req.src <= src_addr_i; + burst11_req.dst <= dst_addr_i; + burst11_req.num_bytes <= num_bytes_i; + burst11_req.cache_src <= src_cache_i; + burst11_req.cache_dst <= dst_cache_i; + burst11_req.burst_src <= src_burst_i; + burst11_req.burst_dst <= dst_burst_i; + burst11_req.decouple_rw <= decouple_rw_i; + burst11_req.deburst <= deburst_i; + burst11_req.serialize <= serialize_i; + burst11_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst11_req_valid <= 1'b0; + burst11_req <= '0; + endtask + + task oned_dut_launch_10 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst10_req_valid <= 1'b0; + burst10_req <= '0; + @(posedge clk); + while (burst10_req_ready !== 1) @(posedge clk); + // write data + burst10_req.id <= transf_id_i; + burst10_req.src <= src_addr_i; + burst10_req.dst <= dst_addr_i; + burst10_req.num_bytes <= num_bytes_i; + burst10_req.cache_src <= src_cache_i; + burst10_req.cache_dst <= dst_cache_i; + burst10_req.burst_src <= src_burst_i; + burst10_req.burst_dst <= dst_burst_i; + burst10_req.decouple_rw <= decouple_rw_i; + burst10_req.deburst <= deburst_i; + burst10_req.serialize <= serialize_i; + burst10_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst10_req_valid <= 1'b0; + burst10_req <= '0; + endtask + + task oned_dut_launch_9 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst9_req_valid <= 1'b0; + burst9_req <= '0; + @(posedge clk); + while (burst9_req_ready !== 1) @(posedge clk); + // write data + burst9_req.id <= transf_id_i; + burst9_req.src <= src_addr_i; + burst9_req.dst <= dst_addr_i; + burst9_req.num_bytes <= num_bytes_i; + burst9_req.cache_src <= src_cache_i; + burst9_req.cache_dst <= dst_cache_i; + burst9_req.burst_src <= src_burst_i; + burst9_req.burst_dst <= dst_burst_i; + burst9_req.decouple_rw <= decouple_rw_i; + burst9_req.deburst <= deburst_i; + burst9_req.serialize <= serialize_i; + burst9_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst9_req_valid <= 1'b0; + burst9_req <= '0; + endtask + + task oned_dut_launch_8 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst8_req_valid <= 1'b0; + burst8_req <= '0; + @(posedge clk); + while (burst8_req_ready !== 1) @(posedge clk); + // write data + burst8_req.id <= transf_id_i; + burst8_req.src <= src_addr_i; + burst8_req.dst <= dst_addr_i; + burst8_req.num_bytes <= num_bytes_i; + burst8_req.cache_src <= src_cache_i; + burst8_req.cache_dst <= dst_cache_i; + burst8_req.burst_src <= src_burst_i; + burst8_req.burst_dst <= dst_burst_i; + burst8_req.decouple_rw <= decouple_rw_i; + burst8_req.deburst <= deburst_i; + burst8_req.serialize <= serialize_i; + burst8_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst8_req_valid <= 1'b0; + burst8_req <= '0; + endtask + + task oned_dut_launch_7 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst7_req_valid <= 1'b0; + burst7_req <= '0; + @(posedge clk); + while (burst7_req_ready !== 1) @(posedge clk); + // write data + burst7_req.id <= transf_id_i; + burst7_req.src <= src_addr_i; + burst7_req.dst <= dst_addr_i; + burst7_req.num_bytes <= num_bytes_i; + burst7_req.cache_src <= src_cache_i; + burst7_req.cache_dst <= dst_cache_i; + burst7_req.burst_src <= src_burst_i; + burst7_req.burst_dst <= dst_burst_i; + burst7_req.decouple_rw <= decouple_rw_i; + burst7_req.deburst <= deburst_i; + burst7_req.serialize <= serialize_i; + burst7_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst7_req_valid <= 1'b0; + burst7_req <= '0; + endtask + + task oned_dut_launch_6 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst6_req_valid <= 1'b0; + burst6_req <= '0; + @(posedge clk); + while (burst6_req_ready !== 1) @(posedge clk); + // write data + burst6_req.id <= transf_id_i; + burst6_req.src <= src_addr_i; + burst6_req.dst <= dst_addr_i; + burst6_req.num_bytes <= num_bytes_i; + burst6_req.cache_src <= src_cache_i; + burst6_req.cache_dst <= dst_cache_i; + burst6_req.burst_src <= src_burst_i; + burst6_req.burst_dst <= dst_burst_i; + burst6_req.decouple_rw <= decouple_rw_i; + burst6_req.deburst <= deburst_i; + burst6_req.serialize <= serialize_i; + burst6_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst6_req_valid <= 1'b0; + burst6_req <= '0; + endtask + + task oned_dut_launch_5 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst5_req_valid <= 1'b0; + burst5_req <= '0; + @(posedge clk); + while (burst5_req_ready !== 1) @(posedge clk); + // write data + burst5_req.id <= transf_id_i; + burst5_req.src <= src_addr_i; + burst5_req.dst <= dst_addr_i; + burst5_req.num_bytes <= num_bytes_i; + burst5_req.cache_src <= src_cache_i; + burst5_req.cache_dst <= dst_cache_i; + burst5_req.burst_src <= src_burst_i; + burst5_req.burst_dst <= dst_burst_i; + burst5_req.decouple_rw <= decouple_rw_i; + burst5_req.deburst <= deburst_i; + burst5_req.serialize <= serialize_i; + burst5_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst5_req_valid <= 1'b0; + burst5_req <= '0; + endtask + + task oned_dut_launch_4 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst4_req_valid <= 1'b0; + burst4_req <= '0; + @(posedge clk); + while (burst4_req_ready !== 1) @(posedge clk); + // write data + burst4_req.id <= transf_id_i; + burst4_req.src <= src_addr_i; + burst4_req.dst <= dst_addr_i; + burst4_req.num_bytes <= num_bytes_i; + burst4_req.cache_src <= src_cache_i; + burst4_req.cache_dst <= dst_cache_i; + burst4_req.burst_src <= src_burst_i; + burst4_req.burst_dst <= dst_burst_i; + burst4_req.decouple_rw <= decouple_rw_i; + burst4_req.deburst <= deburst_i; + burst4_req.serialize <= serialize_i; + burst4_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst4_req_valid <= 1'b0; + burst4_req <= '0; + endtask + + task oned_dut_launch_3 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst3_req_valid <= 1'b0; + burst3_req <= '0; + @(posedge clk); + while (burst3_req_ready !== 1) @(posedge clk); + // write data + burst3_req.id <= transf_id_i; + burst3_req.src <= src_addr_i; + burst3_req.dst <= dst_addr_i; + burst3_req.num_bytes <= num_bytes_i; + burst3_req.cache_src <= src_cache_i; + burst3_req.cache_dst <= dst_cache_i; + burst3_req.burst_src <= src_burst_i; + burst3_req.burst_dst <= dst_burst_i; + burst3_req.decouple_rw <= decouple_rw_i; + burst3_req.deburst <= deburst_i; + burst3_req.serialize <= serialize_i; + burst3_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst3_req_valid <= 1'b0; + burst3_req <= '0; + endtask + + task oned_dut_launch_2 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst2_req_valid <= 1'b0; + burst2_req <= '0; + @(posedge clk); + while (burst2_req_ready !== 1) @(posedge clk); + // write data + burst2_req.id <= transf_id_i; + burst2_req.src <= src_addr_i; + burst2_req.dst <= dst_addr_i; + burst2_req.num_bytes <= num_bytes_i; + burst2_req.cache_src <= src_cache_i; + burst2_req.cache_dst <= dst_cache_i; + burst2_req.burst_src <= src_burst_i; + burst2_req.burst_dst <= dst_burst_i; + burst2_req.decouple_rw <= decouple_rw_i; + burst2_req.deburst <= deburst_i; + burst2_req.serialize <= serialize_i; + burst2_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst2_req_valid <= 1'b0; + burst2_req <= '0; + endtask + + task oned_dut_launch_1 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst1_req_valid <= 1'b0; + burst1_req <= '0; + @(posedge clk); + while (burst1_req_ready !== 1) @(posedge clk); + // write data + burst1_req.id <= transf_id_i; + burst1_req.src <= src_addr_i; + burst1_req.dst <= dst_addr_i; + burst1_req.num_bytes <= num_bytes_i; + burst1_req.cache_src <= src_cache_i; + burst1_req.cache_dst <= dst_cache_i; + burst1_req.burst_src <= src_burst_i; + burst1_req.burst_dst <= dst_burst_i; + burst1_req.decouple_rw <= decouple_rw_i; + burst1_req.deburst <= deburst_i; + burst1_req.serialize <= serialize_i; + burst1_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst1_req_valid <= 1'b0; + burst1_req <= '0; + endtask + + task oned_dut_launch_0 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst0_req_valid <= 1'b0; + burst0_req <= '0; + @(posedge clk); + while (burst0_req_ready !== 1) @(posedge clk); + // write data + burst0_req.id <= transf_id_i; + burst0_req.src <= src_addr_i; + burst0_req.dst <= dst_addr_i; + burst0_req.num_bytes <= num_bytes_i; + burst0_req.cache_src <= src_cache_i; + burst0_req.cache_dst <= dst_cache_i; + burst0_req.burst_src <= src_burst_i; + burst0_req.burst_dst <= dst_burst_i; + burst0_req.decouple_rw <= decouple_rw_i; + burst0_req.deburst <= deburst_i; + burst0_req.serialize <= serialize_i; + burst0_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst0_req_valid <= 1'b0; + burst0_req <= '0; + endtask + + task oned_reset (); + burst0_req_valid <= 1'b0; + burst0_req <= '0; + burst1_req_valid <= 1'b0; + burst1_req <= '0; + burst2_req_valid <= 1'b0; + burst2_req <= '0; + burst3_req_valid <= 1'b0; + burst3_req <= '0; + burst4_req_valid <= 1'b0; + burst4_req <= '0; + burst5_req_valid <= 1'b0; + burst5_req <= '0; + burst6_req_valid <= 1'b0; + burst6_req <= '0; + burst7_req_valid <= 1'b0; + burst7_req <= '0; + burst8_req_valid <= 1'b0; + burst8_req <= '0; + burst9_req_valid <= 1'b0; + burst9_req <= '0; + burst10_req_valid <= 1'b0; + burst10_req <= '0; + burst11_req_valid <= 1'b0; + burst11_req <= '0; + burst12_req_valid <= 1'b0; + burst12_req <= '0; + burst13_req_valid <= 1'b0; + burst13_req <= '0; + burst14_req_valid <= 1'b0; + burst14_req <= '0; + burst15_req_valid <= 1'b0; + burst15_req <= '0; + endtask + + task wait_for_dut_completion (); + repeat(10) @(posedge clk); + while (backend_idle_0 === 0) @(posedge clk); + while (backend_idle_1 === 0) @(posedge clk); + while (backend_idle_2 === 0) @(posedge clk); + while (backend_idle_3 === 0) @(posedge clk); + while (backend_idle_4 === 0) @(posedge clk); + while (backend_idle_5 === 0) @(posedge clk); + while (backend_idle_6 === 0) @(posedge clk); + while (backend_idle_7 === 0) @(posedge clk); + while (backend_idle_8 === 0) @(posedge clk); + while (backend_idle_9 === 0) @(posedge clk); + while (backend_idle_10 === 0) @(posedge clk); + while (backend_idle_11 === 0) @(posedge clk); + while (backend_idle_12 === 0) @(posedge clk); + while (backend_idle_13 === 0) @(posedge clk); + while (backend_idle_14 === 0) @(posedge clk); + while (backend_idle_15 === 0) @(posedge clk); + repeat(50) @(posedge clk); + endtask + + task clear_dut_memory (); + dma_memory.delete(); + dma_memory1.delete(); + endtask + + task reset_dut_lfsr (); + lfsr_dut_q <= 'hc0a232c162b2bab5b960668030f4efce27940bd0de965f0b8d4315f15b79704195e4e0a6b495fc269f65ae17e10e9ca98510fc143327a292b418597f9dd175fc91c3d61be287d5462a23e00fa7ae906ae9eb339ab5225021356138cd46b6e5a73540c5591116b6b5e08d2c0e54eaf0d5143b33b2186b6cf841c076a98c412a63981f0e323dce93481ed1c37e4f1d7553b6c2fba1a3af6c3ad88b15ad58812ba07d1753917ac4e6ab1e8c4f67a47b4b0f48a34f42a52c546e979f4e4968e80a732a0a5e7a51146cf08482f349f94336752b765c0b1d70803d883d5058d127264335213da4163c62f65a4e65501b90fa5f177675c0747cfca328e131bfb3f7bcc5c27680c7bf86491f4ed3d36c25531edfa74b1e32fafe426958ae356eb8ef0fd818eaca4227a667b7c934ebfa282ab6bfc6db89b927c91a41e63a9554dced774f30268d0725a1a565368703b9f81d5c027ba196ef8b803a51c639c7ead834e1d6bc537d33800fe5eb12f1ed67758f1dfe85ffdbae56e8ef27f2ecedcee75b8dbb5f5f1a629ba3b755; + endtask + + //-------------------------------------- + // Osmium Model + //-------------------------------------- + // Memory + block_t osmium_memory [bit [AddrWidth-$clog2($bits(block_t))-1:0]]; + // lfsr + logic [784:0] lfsr_osmium_q,lfsr_osmium_d; + + task oned_osmium_launch ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i + ); + logic [AddrWidth-1:0] read_addr, write_addr; + logic [AddrWidth-1:0] read_word, write_word; + logic [$clog2(AddrWidth):0] read_offset, write_offset; + // perform the transfer + for(int i = 0; i < num_bytes_i; i = i + 1) begin + read_addr = src_addr_i + i; + write_addr = dst_addr_i + i; + read_word = src_burst_i == 2'b00 ? src_addr_i >> $clog2(AddrWidth) : read_addr >> $clog2(AddrWidth); + write_word = dst_burst_i == 2'b00 ? dst_addr_i >> $clog2(AddrWidth) : write_addr >> $clog2(AddrWidth); + read_offset = read_addr [$clog2(AddrWidth)-1:0]; + write_offset = write_addr[$clog2(AddrWidth)-1:0]; + + // do the read + if (!osmium_memory.exists(read_word) === 1) begin + osmium_memory[read_word].data = lfsr_osmium_q[784:273]; + //shift 513x + repeat(513) begin + // next state + for (int i = 1; i < 785; i = i +1) lfsr_osmium_d[i-1] = lfsr_osmium_q[i]; + lfsr_osmium_d[784] = lfsr_osmium_q[0]; + lfsr_osmium_d[692] = lfsr_osmium_q[0] ^ lfsr_osmium_q[693]; + lfsr_osmium_q = lfsr_osmium_d; + end + end + // do the write + osmium_memory[write_word].bytes[write_offset] = osmium_memory[read_word].bytes[read_offset]; + // $display("W: %d - %d R: %d - %d", write_word, write_offset, read_word, read_offset); + end + + endtask + + task clear_osmium_memory (); + osmium_memory.delete(); + endtask + + task reset_osmium_lfsr (); + lfsr_osmium_q = 'hc0a232c162b2bab5b960668030f4efce27940bd0de965f0b8d4315f15b79704195e4e0a6b495fc269f65ae17e10e9ca98510fc143327a292b418597f9dd175fc91c3d61be287d5462a23e00fa7ae906ae9eb339ab5225021356138cd46b6e5a73540c5591116b6b5e08d2c0e54eaf0d5143b33b2186b6cf841c076a98c412a63981f0e323dce93481ed1c37e4f1d7553b6c2fba1a3af6c3ad88b15ad58812ba07d1753917ac4e6ab1e8c4f67a47b4b0f48a34f42a52c546e979f4e4968e80a732a0a5e7a51146cf08482f349f94336752b765c0b1d70803d883d5058d127264335213da4163c62f65a4e65501b90fa5f177675c0747cfca328e131bfb3f7bcc5c27680c7bf86491f4ed3d36c25531edfa74b1e32fafe426958ae356eb8ef0fd818eaca4227a667b7c934ebfa282ab6bfc6db89b927c91a41e63a9554dced774f30268d0725a1a565368703b9f81d5c027ba196ef8b803a51c639c7ead834e1d6bc537d33800fe5eb12f1ed67758f1dfe85ffdbae56e8ef27f2ecedcee75b8dbb5f5f1a629ba3b755; + endtask + + //-------------------------------------- + // Compare Memory content + //-------------------------------------- + task compare_memories (); + + // go through osmium memory and compare contents + foreach(osmium_memory[i]) begin + if (osmium_memory[i] !== dma_memory[i]) $fatal("Memory mismatch @ %x\nexpect: %x\ngot :%x\n", i << $clog2(AddrWidth), osmium_memory[i], dma_memory[i]); + end + // go through dma memory and compare contents + foreach(dma_memory[i]) begin + if (osmium_memory[i] !== dma_memory[i]) $fatal("Memory mismatch @ %x\nexpect: %x\ngot :%x\n", i << $clog2(AddrWidth), osmium_memory[i], dma_memory[i]); + end + + // it worked :P + $display(" - :D"); + + endtask + + //-------------------------------------- + // Master tasks + //-------------------------------------- + + task clear_memory (); + clear_dut_memory(); + clear_osmium_memory(); + endtask + + task reset_lfsr (); + reset_dut_lfsr(); + reset_osmium_lfsr(); + endtask + + task oned_launch_15 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma15_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_15(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_14 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma14_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_14(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_13 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma13_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_13(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_12 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma12_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_12(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_11 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma11_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_11(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_10 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma10_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_10(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_9 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma9_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_9(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_8 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma8_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_8(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_7 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma7_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_7(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_6 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma6_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_6(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_5 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma5_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_5(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_4 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma4_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_4(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_3 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma3_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_3(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_2 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma2_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_2(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_1 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma1_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_1(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_0 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma0_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_0(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task reset (); + int my_file; + oned_reset(); + wait_for_reset(); + // clear trace file + my_file = $fopen("dma_transfers.txt", "w"); + $fwrite(my_file, "Transfers launched:\n"); + $fclose(my_file); + endtask + + task oned_random_launch( + input logic [31:0] max_len, + // input logic [31:0] src_add, + // input logic [31:0] dst_add, + input logic [15:0] master_id, + // input logic [15:0] size, + input logic wait_for_completion + ); + + logic [ IdWidth-1:0] transf_id_0; + logic [ AddrWidth-1:0] src_addr_0, dst_addr_0, num_bytes_0; + logic [ IdWidth-1:0] transf_id_1; + logic [ AddrWidth-1:0] src_addr_1, dst_addr_1, num_bytes_1; + logic [ IdWidth-1:0] transf_id_2; + logic [ AddrWidth-1:0] src_addr_2, dst_addr_2, num_bytes_2; + logic [ IdWidth-1:0] transf_id_3; + logic [ AddrWidth-1:0] src_addr_3, dst_addr_3, num_bytes_3; + logic [ IdWidth-1:0] transf_id_4; + logic [ AddrWidth-1:0] src_addr_4, dst_addr_4, num_bytes_4; + logic [ IdWidth-1:0] transf_id_5; + logic [ AddrWidth-1:0] src_addr_5, dst_addr_5, num_bytes_5; + logic [ IdWidth-1:0] transf_id_6; + logic [ AddrWidth-1:0] src_addr_6, dst_addr_6, num_bytes_6; + logic [ IdWidth-1:0] transf_id_7; + logic [ AddrWidth-1:0] src_addr_7, dst_addr_7, num_bytes_7; + logic [ IdWidth-1:0] transf_id_8; + logic [ AddrWidth-1:0] src_addr_8, dst_addr_8, num_bytes_8; + logic [ IdWidth-1:0] transf_id_9; + logic [ AddrWidth-1:0] src_addr_9, dst_addr_9, num_bytes_9; + logic [ IdWidth-1:0] transf_id_10; + logic [ AddrWidth-1:0] src_addr_10, dst_addr_10, num_bytes_10; + logic [ IdWidth-1:0] transf_id_11; + logic [ AddrWidth-1:0] src_addr_11, dst_addr_11, num_bytes_11; + logic [ IdWidth-1:0] transf_id_12; + logic [ AddrWidth-1:0] src_addr_12, dst_addr_12, num_bytes_12; + logic [ IdWidth-1:0] transf_id_13; + logic [ AddrWidth-1:0] src_addr_13, dst_addr_13, num_bytes_13; + logic [ IdWidth-1:0] transf_id_14; + logic [ AddrWidth-1:0] src_addr_14, dst_addr_14, num_bytes_14; + logic [ IdWidth-1:0] transf_id_15; + logic [ AddrWidth-1:0] src_addr_15, dst_addr_15, num_bytes_15; + logic decouple_rw; + logic deburst; + logic serialize; + + decouple_rw = 0;//$urandom(); + deburst = 0;//$urandom(); + serialize = 0;//$urandom(); + + if (master_id == 0) begin + transf_id_0 = 0;//$urandom(); + // transf_id = transaction_id; + src_addr_0[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_0[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_0[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_0[(AddrWidth/2)-1: 0] = $urandom(); + if (src_addr_0[31:28] == 0) begin + src_addr_0[31:28] = ~(src_addr_0[31:28]); + end + if (dst_addr_0[31:28] == 0) begin + dst_addr_0[31:28] = ~(dst_addr_0[31:28]); + end + //src_addr_0 = $urandom(); + //dst_addr_0 = $urandom(); + //num_bytes_0 = 0; + num_bytes_0 = $urandom_range(max_len, 1); + + oned_launch_0(transf_id_0, src_addr_0, dst_addr_0, num_bytes_0, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 1) begin + transf_id_1 = 1;//$urandom(); + // transf_id = transaction_id; + src_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + if (src_addr_1[31:28] == 1) begin + src_addr_1[31:28] = ~(src_addr_1[31:28]); + end + if (dst_addr_1[31:28] == 1) begin + dst_addr_1[31:28] = ~(dst_addr_1[31:28]); + end + //src_addr_1 = $urandom(); + //dst_addr_1 = $urandom(); + //num_bytes_1 = 0; + num_bytes_1 = $urandom_range(max_len, 1); + + oned_launch_1(transf_id_1, src_addr_1, dst_addr_1, num_bytes_1, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 2) begin + transf_id_2 = 2;//$urandom(); + //transf_id = transaction_id; + src_addr_2[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_2[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_2[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_2[(AddrWidth/2)-1: 0] = $urandom(); + if (src_addr_2[31:28] == 2) begin + src_addr_2[31:28] = ~(src_addr_2[31:28]); + end + if (dst_addr_2[31:28] == 2) begin + dst_addr_2[31:28] = ~(dst_addr_2[31:28]); + end + //src_addr_2 = $urandom(); + //dst_addr_2 = $urandom(); + //num_bytes_2 = 0; + num_bytes_2 = $urandom_range(max_len, 1); + + oned_launch_2(transf_id_2, src_addr_2, dst_addr_2, num_bytes_2, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 3) begin + transf_id_3 = 3;//$urandom(); + // transf_id = transaction_id; + src_addr_3[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_3[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_3[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_3[(AddrWidth/2)-1: 0] = $urandom(); + if (src_addr_3[31:28] == 3) begin + src_addr_3[31:28] = ~(src_addr_3[31:28]); + end + if (dst_addr_3[31:28] == 3) begin + dst_addr_3[31:28] = ~(dst_addr_3[31:28]); + end + //src_addr_3 = $urandom(); + //dst_addr_3 = $urandom(); + //num_bytes_3 = 0; + num_bytes_3 = $urandom_range(max_len, 1); + + oned_launch_3(transf_id_3, src_addr_3, dst_addr_3, num_bytes_3, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 4) begin + transf_id_4 = 4;//$urandom(); + // transf_id = transaction_id; + src_addr_4[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_4[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_4[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_4[(AddrWidth/2)-1: 0] = $urandom(); + if (src_addr_4[31:28] == 4) begin + src_addr_4[31:28] = ~(src_addr_4[31:28]); + end + if (dst_addr_4[31:28] == 4) begin + dst_addr_4[31:28] = ~(dst_addr_4[31:28]); + end + //src_addr_4 = $urandom(); + //dst_addr_4 = $urandom(); + //num_bytes_4 = 0; + num_bytes_4 = $urandom_range(max_len, 1); + + oned_launch_4(transf_id_4, src_addr_4, dst_addr_4, num_bytes_4, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 5) begin + transf_id_5 = 5;//$urandom(); + // transf_id = transaction_id; + src_addr_5[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_5[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_5[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_5[(AddrWidth/2)-1: 0] = $urandom(); + if (src_addr_5[31:28] == 5) begin + src_addr_5[31:28] = ~(src_addr_5[31:28]); + end + if (dst_addr_5[31:28] == 5) begin + dst_addr_5[31:28] = ~(dst_addr_5[31:28]); + end + //src_addr_5 = $urandom(); + //dst_addr_5 = $urandom(); + //num_bytes_5 = 0; + num_bytes_5 = $urandom_range(max_len, 1); + + oned_launch_5(transf_id_5, src_addr_5, dst_addr_5, num_bytes_5, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 6) begin + transf_id_6 = 6;//$urandom(); + // transf_id = transaction_id; + src_addr_6[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_6[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_6[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_6[(AddrWidth/2)-1: 0] = $urandom(); + if (src_addr_6[31:28] == 6) begin + src_addr_6[31:28] = ~(src_addr_6[31:28]); + end + if (dst_addr_6[31:28] == 6) begin + dst_addr_6[31:28] = ~(dst_addr_6[31:28]); + end + //src_addr_6 = $urandom(); + //dst_addr_6 = $urandom(); + //num_bytes_6 = 0; + num_bytes_6 = $urandom_range(max_len, 1); + + oned_launch_6(transf_id_6, src_addr_6, dst_addr_6, num_bytes_6, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 7) begin + transf_id_7 = 7;//$urandom(); + // transf_id = transaction_id; + //src_addr_7[AddrWidth-1:AddrWidth-2] = 1'b1; + src_addr_7[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_7[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_7[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_7[(AddrWidth/2)-1: 0] = $urandom(); + if (src_addr_7[31:28] == 7) begin + src_addr_7[31:28] = ~(src_addr_7[31:28]); + end + if (dst_addr_7[31:28] == 7) begin + dst_addr_7[31:28] = ~(dst_addr_7[31:28]); + end + //src_addr_7 = $urandom(); + //dst_addr_7 = $urandom(); + //num_bytes_7 = 0; + num_bytes_7 = $urandom_range(max_len, 1); + + oned_launch_7(transf_id_7, src_addr_7, dst_addr_7, num_bytes_7, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 8) begin + transf_id_8 = 8;//$urandom(); + // transf_id = transaction_id; + src_addr_8[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_8[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_8[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_8[(AddrWidth/2)-1: 0] = $urandom(); + if (src_addr_8[31:28] == 8) begin + src_addr_8[31:28] = ~(src_addr_8[31:28]); + end + if (dst_addr_8[31:28] == 8) begin + dst_addr_8[31:28] = ~(dst_addr_8[31:28]); + end + //src_addr_8 = $urandom(); + //dst_addr_8 = $urandom(); + //num_bytes_8 = 0; + num_bytes_8 = $urandom_range(max_len, 1); + + oned_launch_8(transf_id_8, src_addr_8, dst_addr_8, num_bytes_8, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 9) begin + transf_id_9 = 9;//$urandom(); + // transf_id = transaction_id; + src_addr_9[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_9[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_9[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_9[(AddrWidth/2)-1: 0] = $urandom(); + if (src_addr_9[31:28] == 9) begin + src_addr_9[31:28] = ~(src_addr_9[31:28]); + end + if (dst_addr_9[31:28] == 9) begin + dst_addr_9[31:28] = ~(dst_addr_9[31:28]); + end + //src_addr_9 = $urandom(); + //dst_addr_9 = $urandom(); + //num_bytes_9 = 0; + num_bytes_9 = $urandom_range(max_len, 1); + + oned_launch_9(transf_id_9, src_addr_9, dst_addr_9, num_bytes_9, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 10) begin + transf_id_10 = 10;//$urandom(); + // transf_id = transaction_id; + src_addr_10[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_10[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_10[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_10[(AddrWidth/2)-1: 0] = $urandom(); + if (src_addr_10[31:28] == 10) begin + src_addr_10[31:28] = ~(src_addr_10[31:28]); + end + if (dst_addr_10[31:28] == 10) begin + dst_addr_10[31:28] = ~(dst_addr_10[31:28]); + end + // src_addr_10 = $urandom(); + // dst_addr_10 = $urandom(); + //num_bytes_10 = 0; + num_bytes_10 = $urandom_range(max_len, 1); + + oned_launch_10(transf_id_10, src_addr_10, dst_addr_10, num_bytes_10, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 11) begin + transf_id_11 = 11;//$urandom(); + // transf_id = transaction_id; + //src_addr_11[AddrWidth-1:AddrWidth-2] = 1'b1; + src_addr_11[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_11[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_11[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_11[(AddrWidth/2)-1: 0] = $urandom(); + if (src_addr_11[31:28] == 11) begin + src_addr_11[31:28] = ~(src_addr_11[31:28]); + end + if (dst_addr_11[31:28] == 11) begin + dst_addr_11[31:28] = ~(dst_addr_11[31:28]); + end + //src_addr_11 = $urandom(); + //dst_addr_11 = $urandom(); + //num_bytes_11 = 0; + num_bytes_11 = $urandom_range(max_len, 1); + + oned_launch_11(transf_id_11, src_addr_11, dst_addr_11, num_bytes_11, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 12) begin + transf_id_12 = 12;//$urandom(); + // transf_id = transaction_id; + src_addr_12[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_12[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_12[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_12[(AddrWidth/2)-1: 0] = $urandom(); + if (src_addr_12[31:28] == 12) begin + src_addr_12[31:28] = ~(src_addr_12[31:28]); + end + if (dst_addr_12[31:28] == 12) begin + dst_addr_12[31:28] = ~(dst_addr_12[31:28]); + end + //src_addr_12 = $urandom(); + //dst_addr_12 = $urandom(); + //num_bytes_12 = 0; + num_bytes_12 = $urandom_range(max_len, 1); + + oned_launch_12(transf_id_12, src_addr_12, dst_addr_12, num_bytes_12, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 13) begin + transf_id_13 = 13;//$urandom(); + // transf_id = transaction_id; + src_addr_13[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_13[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_13[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_13[(AddrWidth/2)-1: 0] = $urandom(); + if (src_addr_13[31:28] == 13) begin + src_addr_13[31:28] = ~(src_addr_13[31:28]); + end + if (dst_addr_13[31:28] == 13) begin + dst_addr_13[31:28] = ~(dst_addr_13[31:28]); + end + //src_addr_13 = $urandom(); + //dst_addr_13 = $urandom(); + //num_bytes_13 = 0; + num_bytes_13 = $urandom_range(max_len, 1); + + oned_launch_13(transf_id_13, src_addr_13, dst_addr_13, num_bytes_13, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 14) begin + transf_id_14 = 14;//$urandom(); + // transf_id = transaction_id; + src_addr_14[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_14[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_14[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_14[(AddrWidth/2)-1: 0] = $urandom(); + if (src_addr_14[31:28] == 14) begin + src_addr_14[31:28] = ~(src_addr_14[31:28]); + end + if (dst_addr_14[31:28] == 14) begin + dst_addr_14[31:28] = ~(dst_addr_14[31:28]); + end + //src_addr_14 = $urandom(); + //dst_addr_14 = $urandom(); + //num_bytes_14 = 0; + num_bytes_14 = $urandom_range(max_len, 1); + + oned_launch_14(transf_id_14, src_addr_14, dst_addr_14, num_bytes_14, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 15) begin + transf_id_15 = 15;//$urandom(); + // transf_id = transaction_id; + //src_addr_15[AddrWidth-1:AddrWidth-2] = 1'b1; + src_addr_15[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_15[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_15[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_15[(AddrWidth/2)-1: 0] = $urandom(); + if (src_addr_15[31:28] == 15) begin + src_addr_15[31:28] = ~(src_addr_15[31:28]); + end + if (dst_addr_15[31:28] == 15) begin + dst_addr_15[31:28] = ~(dst_addr_15[31:28]); + end + //src_addr_15 = $urandom(); + //dst_addr_15 = $urandom(); + //num_bytes_15 = 0; + num_bytes_15 = $urandom_range(max_len, 1); + + oned_launch_15(transf_id_15, src_addr_15, dst_addr_15, num_bytes_15, decouple_rw, deburst, serialize, wait_for_completion); + + end + + // transaction_id = transaction_id + 1; + + + endtask + +endmodule : fixture_axi_dma_backend diff --git a/test/fixture_axi_dma_backend_bkp.sv b/test/fixture_axi_dma_backend_bkp.sv new file mode 100644 index 000000000..cd1aed932 --- /dev/null +++ b/test/fixture_axi_dma_backend_bkp.sv @@ -0,0 +1,1055 @@ +// Copyright (c) 2019 ETH Zurich, University of Bologna +// All rights reserved. +// +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// +// Thomas Benz + +// fixture for the AXi DMA backend +// the fixture instantiates the DMA backend, a golden model of the backend , and tasks controlling +// both. + +`timescale 1ns/1ns +module fixture_axi_dma_backend(); + + // `include "../axi/include/axi/assign.svh" + `define MEM_DEBUG 1 + `include "axi/assign.svh" + `include "axi/typedef.svh" + + //-------------------------------------- + // Parameters + //-------------------------------------- + localparam TA = 0.2ns; // must be nonzero to avoid Snitch load fifo double pop glitch + localparam TT = 0.8ns; + localparam HalfPeriod = 50ns; + localparam Reset = 75ns; + + localparam DataWidth = 512; + localparam AddrWidth = 64; + localparam StrbWidth = DataWidth / 8; + localparam IdWidth = 6; + localparam UserWidth = 1; + + // DUT parameters + localparam bit ATOPs = 0; + localparam int unsigned NoMst = 2; + localparam int unsigned NoSlv = 2; + localparam int unsigned NoSlvPorts_1 = 2; + localparam int unsigned NoMstPorts_1 = 2; + localparam int unsigned NoSlvPorts_0 = 1; + localparam int unsigned NoMstPorts_0 = 1; + localparam bit [NoSlvPorts_1-1:0][NoMstPorts_1-1:0] Connectivity_1 = '1; + localparam bit [NoSlvPorts_0-1:0][NoMstPorts_0-1:0] Connectivity_0 = '1; + localparam int unsigned AxiSlvPortMaxUniqIds = 32'd16; + localparam int unsigned AxiSlvPortMaxTxnsPerId = 32'd128; + localparam int unsigned AxiSlvPortMaxTxns = 32'd31; + localparam int unsigned AxiMstPortMaxUniqIds = 32'd4; + localparam int unsigned AxiMstPortMaxTxnsPerId = 32'd7; + localparam int unsigned NoAddrRules_1 = 32'd2; + localparam int unsigned NoAddrRules_0 = 32'd1; + + typedef axi_pkg::xbar_rule_64_t rule_t; // Has to be the same width as axi addr + + // axi configuration + localparam int unsigned AxiIdWidthMasters = IdWidth; + localparam int unsigned AxiIdUsed = IdWidth-1; // Has to be <= AxiIdWidthMasters + localparam int unsigned AxiIdWidthSlaves = AxiIdWidthMasters + $clog2(NoMstPorts_1); + localparam int unsigned AxiAddrWidth = AddrWidth; // Axi Address Width + localparam int unsigned AxiDataWidth = DataWidth; // Axi Data Width + localparam int unsigned AxiStrbWidth = StrbWidth; + localparam int unsigned AxiUserWidth = UserWidth; + localparam int unsigned AxiIdWidth = IdWidth; + // in the bench can change this variables which are set here freely + localparam axi_pkg::xbar_cfg_t xbar_cfg_2 = '{ + NoSlvPorts: NoMstPorts_1, + NoMstPorts: NoSlvPorts_1, + MaxMstTrans: AxiSlvPortMaxTxns, + MaxSlvTrans: AxiSlvPortMaxTxnsPerId, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_PORTS, + AxiIdWidthSlvPorts: AxiIdWidthMasters, + AxiIdUsedSlvPorts: AxiIdUsed, + UniqueIds: 1'b0, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: NoAddrRules_1 + }; + + localparam axi_pkg::xbar_cfg_t xbar_cfg_1 = '{ + NoSlvPorts: NoMstPorts_1, + NoMstPorts: NoSlvPorts_1, + MaxMstTrans: AxiSlvPortMaxTxns, + MaxSlvTrans: AxiSlvPortMaxTxnsPerId, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_PORTS, + AxiIdWidthSlvPorts: AxiIdWidthMasters, + AxiIdUsedSlvPorts: AxiIdUsed, + UniqueIds: 1'b0, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: NoAddrRules_1 + }; + + localparam axi_pkg::xbar_cfg_t xbar_cfg_0 = '{ + NoSlvPorts: NoMstPorts_0, + NoMstPorts: NoSlvPorts_0, + MaxMstTrans: AxiSlvPortMaxTxns, + MaxSlvTrans: AxiSlvPortMaxTxnsPerId, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_PORTS, + AxiIdWidthSlvPorts: AxiIdWidthMasters, + AxiIdUsedSlvPorts: AxiIdUsed, + UniqueIds: 1'b0, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: NoAddrRules_0 + }; + + localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2 = '{ + '{idx: 32'd1 % NoSlvPorts_1, start_addr: {AddrWidth{1'b0}}, end_addr: {1'b0, {(AddrWidth-1){1'b1}}}}, + '{idx: 32'd0 % NoSlvPorts_1, start_addr: {1'b0, {(AddrWidth-1){1'b1}}}, end_addr: {(AddrWidth){1'b1}}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp1 = '{ + '{idx: 32'd1 % NoSlvPorts_1, start_addr: {1'b0, {(AddrWidth-1){1'b1}}}, end_addr: {(AddrWidth){1'b1}}}, + '{idx: 32'd0 % NoSlvPorts_1, start_addr: {AddrWidth{1'b0}}, end_addr: {1'b0, {(AddrWidth-1){1'b1}}}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_0.NoAddrRules-1:0] AddrMap_xp0 = '{ + '{idx: 32'd0 % NoSlvPorts_0, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + typedef union packed { + logic [StrbWidth-1:0][7:0] bytes; + logic [DataWidth-1:0] data; + } block_t; + + /// Address Type + typedef logic [ AddrWidth-1:0] addr_t; + /// Data Type + typedef logic [ DataWidth-1:0] data_t; + /// Strobe Type + typedef logic [ StrbWidth-1:0] strb_t; + /// AXI ID Type + typedef logic [ IdWidth-1:0] axi_id_t; + /// AXI USER Type + typedef logic [ UserWidth-1:0] user_t; + /// 1D burst request + typedef struct packed { + axi_id_t id; + addr_t src, dst, num_bytes; + axi_pkg::cache_t cache_src, cache_dst; + axi_pkg::burst_t burst_src, burst_dst; + logic decouple_rw; + logic deburst; + logic serialize; + } burst_req_t; + + // master AXI bus --> DMA + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_dma_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_dma_t, axi_id_t, user_t) + + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_dma_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_dma_t, data_t, axi_id_t, user_t) + + `AXI_TYPEDEF_REQ_T(dma_req_t, aw_chan_dma_t, w_chan_t, ar_chan_dma_t) + `AXI_TYPEDEF_RESP_T(dma_resp_t, b_chan_dma_t, r_chan_dma_t) + + // slave AXI bus --> mem + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_mem_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_mem_t, axi_id_t, user_t) + + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_mem_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_mem_t, data_t, axi_id_t, user_t) + + `AXI_TYPEDEF_REQ_T(mem_req_t, aw_chan_mem_t, w_chan_t, ar_chan_mem_t) + `AXI_TYPEDEF_RESP_T(mem_resp_t, b_chan_mem_t, r_chan_mem_t) + + //-------------------------------------- + // Clock and Reset + //-------------------------------------- + logic clk; + initial begin + forever begin + clk = 0; + #HalfPeriod; + clk = 1; + #HalfPeriod; + end + end + + logic rst_n; + initial begin + rst_n = 0; + #Reset; + rst_n = 1; + end + + task wait_for_reset; + @(posedge rst_n); + @(posedge clk); + endtask + + //-------------------------------------- + // DUT Axi busses + //-------------------------------------- + dma_req_t [NoMstPorts_1-1:0] axi_dma_req; + dma_resp_t [NoMstPorts_1-1:0] axi_dma_res; + + //dma_req_t [NoMstPorts-1:0] axi_dma_sync_req; + //dma_resp_t [NoMstPorts-1:0] axi_dma_sync_res; + + mem_req_t [NoSlvPorts_1-1:0] axi_mem_req; + mem_resp_t [NoSlvPorts_1-1:0] axi_mem_res; + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) dma [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) dma_sync [NoMstPorts_1-1:0] (); + + AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) dma_dv [NoMstPorts_1-1:0] (clk); + + for (genvar i = 0; i < NoMstPorts_1; i++) begin : gen_conn_dv_masters + //`AXI_ASSIGN (dma_dv[i], dma[i]) + `AXI_ASSIGN_FROM_REQ(dma[i], axi_dma_req[i]) + `AXI_ASSIGN_TO_RESP(axi_dma_res[i], dma[i]) + end + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_slv_0 [NoSlvPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_slv_1 [NoSlvPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_slv [NoSlvPorts_0-1:0] (); + + `AXI_ASSIGN (xp0_slv_0[0], xp0_slv[0]) + `AXI_ASSIGN (xp0_slv_1[0], xp0_slv[1]) + + AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) mem_dv [NoSlvPorts_1-1:0] (clk); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) mem_0 [NoSlvPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) mem_1 [NoSlvPorts_0-1:0] (); + + for (genvar i = 0; i < NoSlvPorts_1; i++) begin : gen_conn_dv_slaves + //`AXI_ASSIGN (mem_dv[i], mem[i]) + `AXI_ASSIGN_TO_REQ(axi_mem_req[i], mem_dv[i]) + `AXI_ASSIGN_TO_RESP(axi_mem_res[i], mem_dv[i]) + end + + `AXI_ASSIGN (mem_dv[0], mem_0[0]) + `AXI_ASSIGN (mem_dv[1], mem_1[0]) + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma1_t; + + driver_dma_t driver_dma = new(mem_dv[0]); + driver_dma1_t driver_dma1 = new(mem_dv[1]); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem0 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[0]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem1 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[1]) + ); + + // initial begin + // $readmemh("sim_mem0.mem", i_sim_mem0.mem); + // $readmemh("sim_mem1.mem", i_sim_mem1.mem); + // end + + //-------------------------------------- + // DUT AXI Memory System + //-------------------------------------- + // lfsr + logic [784:0] lfsr_dut_q, lfsr_dut_d; + + // transaction id + logic [ 7:0] transaction_id = 0; + + // Memory + block_t dma_memory [bit [AddrWidth-$clog2($bits(block_t))-1:0]]; + block_t dma_memory1 [bit [AddrWidth-$clog2($bits(block_t))-1:0]]; + + // Handle the data output from dma. Model of the memory acting as AXI slave. +// typedef axi_test::axi_driver #(.AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(1), .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod)) driver_dma_t; +// typedef axi_test::axi_driver #(.AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(1), .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod)) driver_dma1_t; +// driver_dma_t driver_dma = new(mem_dv[0]); +// driver_dma_t driver_dma1 = new(mem_dv[1]); +// initial begin +// automatic driver_dma_t::ax_beat_t aw_dma_queue[$], ar_dma_queue[$]; +// automatic driver_dma_t::b_beat_t b_dma_queue[$]; + +// automatic driver_dma1_t::ax_beat_t aw_dma1_queue[$], ar_dma1_queue[$]; +// automatic driver_dma1_t::b_beat_t b_dma1_queue[$]; +// automatic string sb = ""; + +// event ar_dma_received, aw_dma_received, b_dma_ready; +// event ar_dma1_received, aw_dma1_received, b_dma1_ready; +// event lfsr_dut_read; +// event lfsr_dut_read_completed; + +// driver_dma.reset_slave(); +// driver_dma1.reset_slave(); +// @(posedge rst_n); +// $display("AXI reset done"); + +// fork +// // AW mem 0 +// forever begin +// automatic driver_dma_t::ax_beat_t dma_tx; +// driver_dma.recv_aw(dma_tx); +// `ifdef MEM_DEBUG +// $display("Mem0: %d: AW - id: %4d - addr: %d - len: %4d - size: %4d - burst: %b", +// $time(), dma_tx.ax_id, dma_tx.ax_addr, dma_tx.ax_len, dma_tx.ax_size, dma_tx.ax_burst ); +// `endif +// aw_dma_queue.push_back(dma_tx); +// -> aw_dma_received; +// end +// // AW mem 1 +// forever begin +// automatic driver_dma1_t::ax_beat_t dma1_tx; +// driver_dma1.recv_aw(dma1_tx); +// `ifdef MEM_DEBUG +// $display("Mem1: %d: AW - id: %4d - addr: %d - len: %4d - size: %4d - burst: %b", +// $time(), dma1_tx.ax_id, dma1_tx.ax_addr, dma1_tx.ax_len, dma1_tx.ax_size, dma1_tx.ax_burst ); +// `endif +// aw_dma1_queue.push_back(dma1_tx); +// -> aw_dma1_received; +// end +// // AR mem 0 +// forever begin +// automatic driver_dma_t::ax_beat_t dma_tx; +// driver_dma.recv_ar(dma_tx); +// `ifdef MEM_DEBUG +// $display("Mem0: %d: AR - id: %4d - addr: %d - len: %4d - size: %4d - burst: %b", +// $time(), dma_tx.ax_id, dma_tx.ax_addr, dma_tx.ax_len, dma_tx.ax_size, dma_tx.ax_burst ); +// `endif +// ar_dma_queue.push_back(dma_tx); +// -> ar_dma_received; +// end +// // AR mem 1 +// forever begin +// automatic driver_dma1_t::ax_beat_t dma1_tx; +// driver_dma1.recv_ar(dma1_tx); +// `ifdef MEM_DEBUG +// $display("Mem1: %d: AR - id: %4d - addr: %d - len: %4d - size: %4d - burst: %b", +// $time(), dma1_tx.ax_id, dma1_tx.ax_addr, dma1_tx.ax_len, dma1_tx.ax_size, dma1_tx.ax_burst ); +// `endif +// ar_dma1_queue.push_back(dma1_tx); +// -> ar_dma1_received; +// end +// // R mem 0 +// forever begin +// automatic driver_dma_t::r_beat_t dma_tx = new(); +// automatic driver_dma_t::ax_beat_t dma_ax; +// automatic bit [AddrWidth-1:0] word; +// while (ar_dma_queue.size() == 0) @ar_dma_received; +// dma_ax = ar_dma_queue[0]; +// word = dma_ax.ax_addr >> $clog2(AddrWidth); +// dma_tx.r_id = dma_ax.ax_id; +// // if (!dma_memory.exists(word)) begin +// // dma_memory[word].data = lfsr_dut_q[784:273]; +// // //shift 513x +// // repeat(513) begin +// // // next state +// // for (int i = 1; i < 785; i = i +1) lfsr_dut_d[i-1] = lfsr_dut_q[i]; +// // lfsr_dut_d[784] = lfsr_dut_q[0]; +// // lfsr_dut_d[692] = lfsr_dut_q[0] ^ lfsr_dut_q[693]; +// // lfsr_dut_q = lfsr_dut_d; +// // end +// // end +// // dma_tx.r_data = dma_memory[word].data; +// dma_tx.r_resp = axi_pkg::RESP_OKAY; +// dma_tx.r_last = (dma_ax.ax_len == 0); +// `ifdef MEM_DEBUG +// $display("Mem0: %d: R - id: %4d - data: %x - resp: %x - last: %b (0x%x)", +// $time(), dma_tx.r_id, dma_tx.r_data, dma_tx.r_resp, dma_tx.r_last, word << $clog2(AddrWidth)); +// `endif +// dma_ax.ax_addr >>= dma_ax.ax_size; +// dma_ax.ax_addr += (dma_ax.ax_burst !== 0); +// dma_ax.ax_addr <<= dma_ax.ax_size; +// dma_ax.ax_len -= 1; +// if (dma_tx.r_last) begin +// ar_dma_queue.pop_front(); +// end +// driver_dma.send_r(dma_tx); +// end +// // R mem 1 +// forever begin +// automatic driver_dma1_t::r_beat_t dma1_tx = new(); +// automatic driver_dma1_t::ax_beat_t dma1_ax; +// automatic bit [AddrWidth-1:0] word; +// while (ar_dma1_queue.size() == 0) @ar_dma1_received; +// dma1_ax = ar_dma1_queue[0]; +// word = dma1_ax.ax_addr >> $clog2(AddrWidth); +// dma1_tx.r_id = dma1_ax.ax_id; +// // if (!dma_memory1.exists(word)) begin +// // dma_memory1[word].data = lfsr_dut_q[784:273]; +// // //shift 513x +// // repeat(513) begin +// // // next state +// // for (int i = 1; i < 785; i = i +1) lfsr_dut_d[i-1] = lfsr_dut_q[i]; +// // lfsr_dut_d[784] = lfsr_dut_q[0]; +// // lfsr_dut_d[692] = lfsr_dut_q[0] ^ lfsr_dut_q[693]; +// // lfsr_dut_q = lfsr_dut_d; +// // end +// // end +// // dma1_tx.r_data = dma_memory1[word].data; +// dma1_tx.r_resp = axi_pkg::RESP_OKAY; +// dma1_tx.r_last = (dma1_ax.ax_len == 0); +// `ifdef MEM_DEBUG +// $display("Mem1: %d: R - id: %4d - data: %x - resp: %x - last: %b (0x%x)", +// $time(), dma1_tx.r_id, dma1_tx.r_data, dma1_tx.r_resp, dma1_tx.r_last, word << $clog2(AddrWidth)); +// `endif +// dma1_ax.ax_addr >>= dma1_ax.ax_size; +// dma1_ax.ax_addr += (dma1_ax.ax_burst !== 0); +// dma1_ax.ax_addr <<= dma1_ax.ax_size; +// dma1_ax.ax_len -= 1; +// if (dma1_tx.r_last) begin +// ar_dma1_queue.pop_front(); +// end +// driver_dma1.send_r(dma1_tx); +// end +// // W mem 0 +// forever begin +// automatic driver_dma_t::w_beat_t dma_tx; +// automatic driver_dma_t::ax_beat_t dma_ax; +// automatic bit [AddrWidth-1:0] word; +// driver_dma.recv_w(dma_tx); +// while (aw_dma_queue.size() == 0) @ar_dma_received; +// dma_ax = aw_dma_queue[0]; +// word = dma_ax.ax_addr >> $clog2(AddrWidth); +// //$display("Ready to write"); +// //$display("%x", word); +// // for (int i = 0; i < StrbWidth; i++) begin +// // if (dma_tx.w_strb[i]) begin +// // dma_memory[word].bytes[i] = dma_tx.w_data[i*8+:8]; +// // end +// // end +// `ifdef MEM_DEBUG +// $display("Mem0: %d: W - data: %x - strb: %x - last: %b (0x%x)", +// $time(), dma_tx.w_data, dma_tx.w_strb, dma_tx.w_last, word << $clog2(AddrWidth)); +// `endif +// dma_ax.ax_addr >>= dma_ax.ax_size; +// dma_ax.ax_addr += (dma_ax.ax_burst !== 0); +// dma_ax.ax_addr <<= dma_ax.ax_size; +// dma_ax.ax_len -= 1; +// if (dma_tx.w_last) begin +// automatic driver_dma_t::b_beat_t dma_tx = new(); +// dma_tx.b_id = dma_ax.ax_id; +// dma_tx.b_user = dma_ax.ax_user; +// aw_dma_queue.pop_front(); +// b_dma_queue.push_back(dma_tx); +// -> b_dma_ready; +// end +// end +// // W mem 1 +// forever begin +// automatic driver_dma1_t::w_beat_t dma1_tx; +// automatic driver_dma1_t::ax_beat_t dma1_ax; +// automatic bit [AddrWidth-1:0] word; +// driver_dma1.recv_w(dma1_tx); +// while (aw_dma1_queue.size() == 0) @ar_dma1_received; +// dma1_ax = aw_dma1_queue[0]; +// word = dma1_ax.ax_addr >> $clog2(AddrWidth); +// //$display("Ready to write"); +// //$display("%x", word); +// // for (int i = 0; i < StrbWidth; i++) begin +// // if (dma1_tx.w_strb[i]) begin +// // dma_memory1[word].bytes[i] = dma1_tx.w_data[i*8+:8]; +// // end +// // end +// `ifdef MEM_DEBUG +// $display("Mem1: %d: W - data: %x - strb: %x - last: %b (0x%x)", +// $time(), dma1_tx.w_data, dma1_tx.w_strb, dma1_tx.w_last, word << $clog2(AddrWidth)); +// `endif +// dma1_ax.ax_addr >>= dma1_ax.ax_size; +// dma1_ax.ax_addr += (dma1_ax.ax_burst !== 0); +// dma1_ax.ax_addr <<= dma1_ax.ax_size; +// dma1_ax.ax_len -= 1; +// if (dma1_tx.w_last) begin +// automatic driver_dma1_t::b_beat_t dma1_tx = new(); +// dma1_tx.b_id = dma1_ax.ax_id; +// dma1_tx.b_user = dma1_ax.ax_user; +// aw_dma1_queue.pop_front(); +// b_dma1_queue.push_back(dma1_tx); +// -> b_dma1_ready; +// end +// end +// // B mem 0 +// forever begin +// automatic driver_dma_t::b_beat_t dma_tx; +// while (b_dma_queue.size() == 0) @b_dma_ready; +// driver_dma.send_b(b_dma_queue[0]); +// b_dma_queue.pop_front(); +// end +// // B mem 1 +// forever begin +// automatic driver_dma1_t::b_beat_t dma1_tx; +// while (b_dma1_queue.size() == 0) @b_dma1_ready; +// driver_dma1.send_b(b_dma1_queue[0]); +// b_dma1_queue.pop_front(); +// end +// join_any +// end + + //-------------------------------------- + // DMA instantiation + //-------------------------------------- + burst_req_t burst0_req; + burst_req_t burst1_req; + logic burst0_req_valid; + logic burst1_req_valid; + logic burst0_req_ready; + logic burst1_req_ready; + logic backend_idle_0; + logic backend_idle_1; + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_1 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[1] ), + .axi_dma_res_i ( axi_dma_res[1] ), + .burst_req_i ( burst1_req ), + .valid_i ( burst1_req_valid ), + .ready_o ( burst1_req_ready ), + .backend_idle_o ( backend_idle_1 ), + .trans_complete_o ( ), + .dma_id_i ( '1 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_1 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[1] ), + .out ( dma_sync[1] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_0 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[0] ), + .axi_dma_res_i ( axi_dma_res[0] ), + .burst_req_i ( burst0_req ), + .valid_i ( burst0_req_valid ), + .ready_o ( burst0_req_ready ), + .backend_idle_o ( backend_idle_0 ), + .trans_complete_o ( ), + .dma_id_i ( '0 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_0 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[0] ), + .out ( dma_sync[0] ) + ); + + //----------------------------------- + // DUT + //----------------------------------- + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_0 ), + .NoSlvPorts ( xbar_cfg_0.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_0.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_0.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_3 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp1_slv ), + .mst_ports ( mem_0 ), + .addr_map_i ( AddrMap_xp0 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_0 ), + .NoSlvPorts ( xbar_cfg_0.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_0.NoMstPorts ), + .Connectivity ( Connectivity_0 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_0.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_2 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp0_slv_1 ), + .mst_ports ( mem_1 ), + .addr_map_i ( AddrMap_xp0 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_0 ), + .NoSlvPorts ( xbar_cfg_0.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_0.NoMstPorts ), + .Connectivity ( Connectivity_0 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_0.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_1 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp0_slv_0 ), + .mst_ports ( xp1_slv ), + .addr_map_i ( AddrMap_xp0 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_0 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( dma_sync ), + .mst_ports ( xp0_slv ), + .addr_map_i ( AddrMap_xp1 ) + ); + + //-------------------------------------- + // DMA DUT tasks + //-------------------------------------- + task oned_dut_launch_1 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst1_req_valid <= 1'b0; + burst1_req <= '0; + @(posedge clk); + while (burst1_req_ready !== 1) @(posedge clk); + // write data + burst1_req.id <= transf_id_i; + burst1_req.src <= src_addr_i; + burst1_req.dst <= dst_addr_i; + burst1_req.num_bytes <= num_bytes_i; + burst1_req.cache_src <= src_cache_i; + burst1_req.cache_dst <= dst_cache_i; + burst1_req.burst_src <= src_burst_i; + burst1_req.burst_dst <= dst_burst_i; + burst1_req.decouple_rw <= decouple_rw_i; + burst1_req.deburst <= deburst_i; + burst1_req.serialize <= serialize_i; + burst1_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst1_req_valid <= 1'b0; + burst1_req <= '0; + endtask + + task oned_dut_launch_0 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst0_req_valid <= 1'b0; + burst0_req <= '0; + @(posedge clk); + while (burst0_req_ready !== 1) @(posedge clk); + // write data + burst0_req.id <= transf_id_i; + burst0_req.src <= src_addr_i; + burst0_req.dst <= dst_addr_i; + burst0_req.num_bytes <= num_bytes_i; + burst0_req.cache_src <= src_cache_i; + burst0_req.cache_dst <= dst_cache_i; + burst0_req.burst_src <= src_burst_i; + burst0_req.burst_dst <= dst_burst_i; + burst0_req.decouple_rw <= decouple_rw_i; + burst0_req.deburst <= deburst_i; + burst0_req.serialize <= serialize_i; + burst0_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst0_req_valid <= 1'b0; + burst0_req <= '0; + endtask + + task oned_reset (); + burst0_req_valid <= 1'b0; + burst0_req <= '0; + burst1_req_valid <= 1'b0; + burst1_req <= '0; + endtask + + task wait_for_dut_completion (); + repeat(10) @(posedge clk); + while (backend_idle_0 === 0) @(posedge clk); + while (backend_idle_1 === 0) @(posedge clk); + repeat(50) @(posedge clk); + endtask + + task clear_dut_memory (); + dma_memory.delete(); + dma_memory1.delete(); + endtask + + task reset_dut_lfsr (); + lfsr_dut_q <= 'hc0a232c162b2bab5b960668030f4efce27940bd0de965f0b8d4315f15b79704195e4e0a6b495fc269f65ae17e10e9ca98510fc143327a292b418597f9dd175fc91c3d61be287d5462a23e00fa7ae906ae9eb339ab5225021356138cd46b6e5a73540c5591116b6b5e08d2c0e54eaf0d5143b33b2186b6cf841c076a98c412a63981f0e323dce93481ed1c37e4f1d7553b6c2fba1a3af6c3ad88b15ad58812ba07d1753917ac4e6ab1e8c4f67a47b4b0f48a34f42a52c546e979f4e4968e80a732a0a5e7a51146cf08482f349f94336752b765c0b1d70803d883d5058d127264335213da4163c62f65a4e65501b90fa5f177675c0747cfca328e131bfb3f7bcc5c27680c7bf86491f4ed3d36c25531edfa74b1e32fafe426958ae356eb8ef0fd818eaca4227a667b7c934ebfa282ab6bfc6db89b927c91a41e63a9554dced774f30268d0725a1a565368703b9f81d5c027ba196ef8b803a51c639c7ead834e1d6bc537d33800fe5eb12f1ed67758f1dfe85ffdbae56e8ef27f2ecedcee75b8dbb5f5f1a629ba3b755; + endtask + + //-------------------------------------- + // Osmium Model + //-------------------------------------- + // Memory + block_t osmium_memory [bit [AddrWidth-$clog2($bits(block_t))-1:0]]; + // lfsr + logic [784:0] lfsr_osmium_q,lfsr_osmium_d; + + task oned_osmium_launch ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i + ); + logic [AddrWidth-1:0] read_addr, write_addr; + logic [AddrWidth-1:0] read_word, write_word; + logic [$clog2(AddrWidth):0] read_offset, write_offset; + // perform the transfer + for(int i = 0; i < num_bytes_i; i = i + 1) begin + read_addr = src_addr_i + i; + write_addr = dst_addr_i + i; + read_word = src_burst_i == 2'b00 ? src_addr_i >> $clog2(AddrWidth) : read_addr >> $clog2(AddrWidth); + write_word = dst_burst_i == 2'b00 ? dst_addr_i >> $clog2(AddrWidth) : write_addr >> $clog2(AddrWidth); + read_offset = read_addr [$clog2(AddrWidth)-1:0]; + write_offset = write_addr[$clog2(AddrWidth)-1:0]; + + // do the read + if (!osmium_memory.exists(read_word) === 1) begin + osmium_memory[read_word].data = lfsr_osmium_q[784:273]; + //shift 513x + repeat(513) begin + // next state + for (int i = 1; i < 785; i = i +1) lfsr_osmium_d[i-1] = lfsr_osmium_q[i]; + lfsr_osmium_d[784] = lfsr_osmium_q[0]; + lfsr_osmium_d[692] = lfsr_osmium_q[0] ^ lfsr_osmium_q[693]; + lfsr_osmium_q = lfsr_osmium_d; + end + end + // do the write + osmium_memory[write_word].bytes[write_offset] = osmium_memory[read_word].bytes[read_offset]; + // $display("W: %d - %d R: %d - %d", write_word, write_offset, read_word, read_offset); + end + + endtask + + task clear_osmium_memory (); + osmium_memory.delete(); + endtask + + task reset_osmium_lfsr (); + lfsr_osmium_q = 'hc0a232c162b2bab5b960668030f4efce27940bd0de965f0b8d4315f15b79704195e4e0a6b495fc269f65ae17e10e9ca98510fc143327a292b418597f9dd175fc91c3d61be287d5462a23e00fa7ae906ae9eb339ab5225021356138cd46b6e5a73540c5591116b6b5e08d2c0e54eaf0d5143b33b2186b6cf841c076a98c412a63981f0e323dce93481ed1c37e4f1d7553b6c2fba1a3af6c3ad88b15ad58812ba07d1753917ac4e6ab1e8c4f67a47b4b0f48a34f42a52c546e979f4e4968e80a732a0a5e7a51146cf08482f349f94336752b765c0b1d70803d883d5058d127264335213da4163c62f65a4e65501b90fa5f177675c0747cfca328e131bfb3f7bcc5c27680c7bf86491f4ed3d36c25531edfa74b1e32fafe426958ae356eb8ef0fd818eaca4227a667b7c934ebfa282ab6bfc6db89b927c91a41e63a9554dced774f30268d0725a1a565368703b9f81d5c027ba196ef8b803a51c639c7ead834e1d6bc537d33800fe5eb12f1ed67758f1dfe85ffdbae56e8ef27f2ecedcee75b8dbb5f5f1a629ba3b755; + endtask + + //-------------------------------------- + // Compare Memory content + //-------------------------------------- + task compare_memories (); + + // go through osmium memory and compare contents + foreach(osmium_memory[i]) begin + if (osmium_memory[i] !== dma_memory[i]) $fatal("Memory mismatch @ %x\nexpect: %x\ngot :%x\n", i << $clog2(AddrWidth), osmium_memory[i], dma_memory[i]); + end + // go through dma memory and compare contents + foreach(dma_memory[i]) begin + if (osmium_memory[i] !== dma_memory[i]) $fatal("Memory mismatch @ %x\nexpect: %x\ngot :%x\n", i << $clog2(AddrWidth), osmium_memory[i], dma_memory[i]); + end + + // it worked :P + $display(" - :D"); + + endtask + + //-------------------------------------- + // Master tasks + //-------------------------------------- + + task clear_memory (); + clear_dut_memory(); + clear_osmium_memory(); + endtask + + task reset_lfsr (); + reset_dut_lfsr(); + reset_osmium_lfsr(); + endtask + + task oned_launch_1 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma1_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_1(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_0 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma0_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_0(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task reset (); + int my_file; + oned_reset(); + wait_for_reset(); + // clear trace file + my_file = $fopen("dma_transfers.txt", "w"); + $fwrite(my_file, "Transfers launched:\n"); + $fclose(my_file); + endtask + + task oned_random_launch( + input logic [15:0] max_len, + input logic wait_for_completion + ); + + logic [ IdWidth-1:0] transf_id_0; + logic [ AddrWidth-1:0] src_addr_0, dst_addr_0, num_bytes_0; + logic [ IdWidth-1:0] transf_id_1; + logic [ AddrWidth-1:0] src_addr_1, dst_addr_1, num_bytes_1; + logic decouple_rw; + logic deburst; + logic serialize; + + transf_id_0 = 0;//$urandom(); + // transf_id = transaction_id; + src_addr_0[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_0[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_0[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_0[(AddrWidth/2)-1: 0] = $urandom(); + num_bytes_0 = 0; + num_bytes_0[15: 0] = $urandom_range(max_len, 1); + + transf_id_1 = 1;//$urandom(); + // transf_id = transaction_id; + src_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + num_bytes_1 = 0; + num_bytes_1[15: 0] = $urandom_range(max_len, 1); + + decouple_rw = 0;//$urandom(); + deburst = 0;//$urandom(); + serialize = 0;//$urandom(); + + // transaction_id = transaction_id + 1; + + oned_launch_0(transf_id_0, src_addr_0, dst_addr_0, num_bytes_0, decouple_rw, deburst, serialize, wait_for_completion); + oned_launch_1(transf_id_1, src_addr_1, dst_addr_1, num_bytes_1, decouple_rw, deburst, serialize, wait_for_completion); + + endtask + +endmodule : fixture_axi_dma_backend diff --git a/test/fixture_axi_dma_backend_rand_traffic.sv b/test/fixture_axi_dma_backend_rand_traffic.sv new file mode 100644 index 000000000..4f723cd57 --- /dev/null +++ b/test/fixture_axi_dma_backend_rand_traffic.sv @@ -0,0 +1,4635 @@ +// Copyright (c) 2019 ETH Zurich, University of Bologna +// All rights reserved. +// +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// +// Thomas Benz + +// fixture for the AXi DMA backend +// the fixture instantiates the DMA backend, a golden model of the backend , and tasks controlling +// both. + +`timescale 1ns/1ns +module fixture_axi_dma_backend(); + + // `include "../axi/include/axi/assign.svh" + `define MASTERS_16 + `define MEM_DEBUG 1 + `include "axi/assign.svh" + `include "axi/typedef.svh" + + //-------------------------------------- + // Parameters + //-------------------------------------- + localparam TA = 0.2ns; // must be nonzero to avoid Snitch load fifo double pop glitch + localparam TT = 0.8ns; + localparam HalfPeriod = 5ns; + localparam Reset = 7.5ns; + + localparam DataWidth = 32; + localparam AddrWidth = 32; + localparam StrbWidth = DataWidth / 8; + localparam IdWidth = 6; + localparam UserWidth = 1; + + // DUT parameters + localparam bit ATOPs = 0; + localparam int unsigned NoMst = 16; + localparam int unsigned NoSlv = 16; + localparam int unsigned NoSlvPorts_2 = 5; + localparam int unsigned NoMstPorts_2 = 5; + localparam int unsigned NoSlvPorts_1 = 4; + localparam int unsigned NoMstPorts_1 = 4; + localparam int unsigned NoSlvPorts_0 = 3; + localparam int unsigned NoMstPorts_0 = 3; + localparam bit [NoSlvPorts_2-1:0][NoMstPorts_2-1:0] Connectivity_2 = {5'h1f,5'h1f,5'h1f,5'h1f,5'h1f}; + localparam bit [NoSlvPorts_1-1:0][NoMstPorts_1-1:0] Connectivity_1 = {4'hf,4'hf,4'hf,4'hf}; + localparam bit [NoSlvPorts_0-1:0][NoMstPorts_0-1:0] Connectivity_0 = '1;//{3'h6,3'h6,3'h6}; + localparam int unsigned AxiSlvPortMaxUniqIds = 32'd16; + localparam int unsigned AxiSlvPortMaxTxnsPerId = 32'd128; + localparam int unsigned AxiSlvPortMaxTxns = 32'd31; + localparam int unsigned AxiMstPortMaxUniqIds = 32'd4; + localparam int unsigned AxiMstPortMaxTxnsPerId = 32'd7; + localparam int unsigned NoAddrRules_2 = 32'd5; + localparam int unsigned NoAddrRules_1 = 32'd4; + localparam int unsigned NoAddrRules_0 = 32'd3; + + typedef axi_pkg::xbar_rule_32_t rule_t; // Has to be the same width as axi addr + + // axi configuration + localparam int unsigned AxiIdWidthMasters = IdWidth; + localparam int unsigned AxiIdUsed = IdWidth-1; // Has to be <= AxiIdWidthMasters + localparam int unsigned AxiIdWidthSlaves = AxiIdWidthMasters + $clog2(NoMstPorts_1); + localparam int unsigned AxiAddrWidth = AddrWidth; // Axi Address Width + localparam int unsigned AxiDataWidth = DataWidth; // Axi Data Width + localparam int unsigned AxiStrbWidth = StrbWidth; + localparam int unsigned AxiUserWidth = UserWidth; + localparam int unsigned AxiIdWidth = IdWidth; + + // in the bench can change this variables which are set here freely + localparam axi_pkg::xbar_cfg_t xbar_cfg_2 = '{ + NoSlvPorts: NoMstPorts_2, + NoMstPorts: NoSlvPorts_2, + MaxMstTrans: AxiSlvPortMaxTxns, + MaxSlvTrans: AxiSlvPortMaxTxnsPerId, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_PORTS, + AxiIdWidthSlvPorts: AxiIdWidthMasters, + AxiIdUsedSlvPorts: AxiIdUsed, + UniqueIds: 1'b0, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: NoAddrRules_2 + }; + + localparam axi_pkg::xbar_cfg_t xbar_cfg_1 = '{ + NoSlvPorts: NoMstPorts_1, + NoMstPorts: NoSlvPorts_1, + MaxMstTrans: AxiSlvPortMaxTxns, + MaxSlvTrans: AxiSlvPortMaxTxnsPerId, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_PORTS, + AxiIdWidthSlvPorts: AxiIdWidthMasters, + AxiIdUsedSlvPorts: AxiIdUsed, + UniqueIds: 1'b0, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: NoAddrRules_1 + }; + + localparam axi_pkg::xbar_cfg_t xbar_cfg_0 = '{ + NoSlvPorts: NoMstPorts_0, + NoMstPorts: NoSlvPorts_0, + MaxMstTrans: AxiSlvPortMaxTxns, + MaxSlvTrans: AxiSlvPortMaxTxnsPerId, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_PORTS, + AxiIdWidthSlvPorts: AxiIdWidthMasters, + AxiIdUsedSlvPorts: AxiIdUsed, + UniqueIds: 1'b0, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: NoAddrRules_0 + }; + + //localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2 = '{ + // '{idx: 32'd1 % NoSlvPorts_1, start_addr: {AddrWidth{1'b0}}, end_addr: {1'b0, {(AddrWidth-1){1'b1}}}}, + // '{idx: 32'd0 % NoSlvPorts_1, start_addr: {1'b0, {(AddrWidth-1){1'b1}}}, end_addr: {(AddrWidth){1'b1}}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + //}; + + // //////////////////////////////// All global accesses start ////////////////////////////////////// + + // localparam rule_t [xbar_cfg_0.NoAddrRules-1:0] AddrMap_xp0 = '{ + // '{idx: 32'd2 % NoSlvPorts_0, start_addr: {32'h0fffffff}, end_addr: {32'hffffffff}}, + // '{idx: 32'd1 % NoSlvPorts_0, start_addr: {32'h000fffff}, end_addr: {32'h0fffffff}}, + // '{idx: 32'd0 % NoSlvPorts_0, start_addr: {32'b0}, end_addr: {32'h000fffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp1 = '{ + // '{idx: 32'd3 % NoSlvPorts_1, start_addr: {32'h000000ff}, end_addr: {32'h0000ffff}}, + // '{idx: 32'd2 % NoSlvPorts_1, start_addr: {32'h0000ffff}, end_addr: {32'h0fffffff}}, + // '{idx: 32'd1 % NoSlvPorts_1, start_addr: {32'h0fffffff}, end_addr: {32'hffffffff}}, + // '{idx: 32'd0 % NoSlvPorts_1, start_addr: {32'h00000000}, end_addr: {32'h000000ff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2 = '{ + // // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'b0}, end_addr: {32'h00000fff}}, + // // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h000fffff}}, + // // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h000fffff}, end_addr: {32'h00ffffff}}, + // // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h00ffffff}, end_addr: {32'h0fffffff}}, + // // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h0fffffff}, end_addr: {32'hffffffff}} + // // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // // }; + + // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2_1 = '{ + // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h00000000}, end_addr: {32'h000000ff}}, + // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h000fffff}, end_addr: {32'hffffffff}}, + // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h000000ff}, end_addr: {32'h00000fff}}, + // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h0000ffff}}, + // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h0000ffff}, end_addr: {32'h000fffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2_2 = '{ + // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h00000000}, end_addr: {32'h000000ff}}, + // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h000000ff}, end_addr: {32'h00000fff}}, + // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h0000ffff}}, + // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h0000ffff}, end_addr: {32'h000fffff}}, + // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h000fffff}, end_addr: {32'hffffffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2_3 = '{ + // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h000fffff}, end_addr: {32'hffffffff}}, + // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h00000000}, end_addr: {32'h000000ff}}, + // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h000000ff}, end_addr: {32'h00000fff}}, + // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h0000ffff}}, + // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h0000ffff}, end_addr: {32'h000fffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // //////////////////////////////// All global accesses end ////////////////////////////////////// + + // //////////////////////////////// All local accesses start ////////////////////////////////////// + + // localparam rule_t [xbar_cfg_0.NoAddrRules-1:0] AddrMap_xp0 = '{ + // '{idx: 32'd2 % NoSlvPorts_0, start_addr: {32'h00000000}, end_addr: {32'h00000001}}, + // '{idx: 32'd1 % NoSlvPorts_0, start_addr: {32'h00000001}, end_addr: {32'h00000002}}, + // '{idx: 32'd0 % NoSlvPorts_0, start_addr: {32'h00000002}, end_addr: {32'hffffffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp1 = '{ + // '{idx: 32'd3 % NoSlvPorts_1, start_addr: {32'h00000000}, end_addr: {32'h000000ff}}, + // '{idx: 32'd2 % NoSlvPorts_1, start_addr: {32'h000000ff}, end_addr: {32'h00000fff}}, + // '{idx: 32'd1 % NoSlvPorts_1, start_addr: {32'h00000fff}, end_addr: {32'h0000ffff}}, + // '{idx: 32'd0 % NoSlvPorts_1, start_addr: {32'h0000ffff}, end_addr: {32'hffffffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2 = '{ + // // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'b0}, end_addr: {32'h00000fff}}, + // // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h000fffff}}, + // // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h000fffff}, end_addr: {32'h00ffffff}}, + // // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h00ffffff}, end_addr: {32'h0fffffff}}, + // // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h0fffffff}, end_addr: {32'hffffffff}} + // // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // // }; + + // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2_1 = '{ + // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h00000000}, end_addr: {32'h0000000f}}, + // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h0000ffff}}, + // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h0000000f}, end_addr: {32'h000000ff}}, + // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h000000ff}, end_addr: {32'h00000fff}}, + // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h0000ffff}, end_addr: {32'hffffffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2_2 = '{ + // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h00000000}, end_addr: {32'h0000000f}}, + // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h0000000f}, end_addr: {32'h000000ff}}, + // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h000000ff}, end_addr: {32'h00000fff}}, + // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h0000ffff}}, + // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h0000ffff}, end_addr: {32'hffffffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2_3 = '{ + // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h0000ffff}}, + // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h00000000}, end_addr: {32'h0000000f}}, + // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h0000000f}, end_addr: {32'h000000ff}}, + // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h000000ff}, end_addr: {32'h00000fff}}, + // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h0000ffff}, end_addr: {32'hffffffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // //////////////////////////////// All local accesses end ////////////////////////////////////// + + //////////////////////////////// Mixed accesses (max 2 hop) start ////////////////////////////////////// + + localparam rule_t [xbar_cfg_0.NoAddrRules-1:0] AddrMap_xp0 = '{ + '{idx: 32'd2 % NoSlvPorts_0, start_addr: {32'h0fffffff}, end_addr: {32'hffffffff}}, + '{idx: 32'd1 % NoSlvPorts_0, start_addr: {32'h0000ffff}, end_addr: {32'h0fffffff}}, + '{idx: 32'd0 % NoSlvPorts_0, start_addr: {32'b0}, end_addr: {32'h0000ffff}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp1 = '{ + '{idx: 32'd3 % NoSlvPorts_1, start_addr: {32'h000000ff}, end_addr: {32'h0000ffff}}, + '{idx: 32'd2 % NoSlvPorts_1, start_addr: {32'h0000ffff}, end_addr: {32'h0fffffff}}, + '{idx: 32'd1 % NoSlvPorts_1, start_addr: {32'h0fffffff}, end_addr: {32'hffffffff}}, + '{idx: 32'd0 % NoSlvPorts_1, start_addr: {32'h00000000}, end_addr: {32'h000000ff}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2 = '{ + // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'b0}, end_addr: {32'h00000fff}}, + // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h000fffff}}, + // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h000fffff}, end_addr: {32'h00ffffff}}, + // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h00ffffff}, end_addr: {32'h0fffffff}}, + // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h0fffffff}, end_addr: {32'hffffffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2_1 = '{ + '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h00000000}, end_addr: {32'h0000000f}}, + '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h0000ffff}}, + '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h0000000f}, end_addr: {32'h000000ff}}, + '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h000000ff}, end_addr: {32'h00000fff}}, + '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h0000ffff}, end_addr: {32'hffffffff}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2_2 = '{ + '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h00000000}, end_addr: {32'h0000000f}}, + '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h0000000f}, end_addr: {32'h000000ff}}, + '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h000000ff}, end_addr: {32'h00000fff}}, + '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h0000ffff}}, + '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h0000ffff}, end_addr: {32'hffffffff}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2_3 = '{ + '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h0000ffff}}, + '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h00000000}, end_addr: {32'h0000000f}}, + '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h0000000f}, end_addr: {32'h000000ff}}, + '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h000000ff}, end_addr: {32'h00000fff}}, + '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h0000ffff}, end_addr: {32'hffffffff}} + //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + }; + + //////////////////////////////// Mixed accesses (max 2 hop) end ////////////////////////////////////// + + // //////////////////////////////// Mixed accesses (max 1 hop) start ////////////////////////////////////// + + // localparam rule_t [xbar_cfg_0.NoAddrRules-1:0] AddrMap_xp0 = '{ + // '{idx: 32'd2 % NoSlvPorts_0, start_addr: {32'h0fffffff}, end_addr: {32'hffffffff}}, + // '{idx: 32'd1 % NoSlvPorts_0, start_addr: {32'h00000fff}, end_addr: {32'h0fffffff}}, + // '{idx: 32'd0 % NoSlvPorts_0, start_addr: {32'h00000000}, end_addr: {32'h00000fff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // localparam rule_t [xbar_cfg_1.NoAddrRules-1:0] AddrMap_xp1 = '{ + // '{idx: 32'd3 % NoSlvPorts_1, start_addr: {32'h0000000f}, end_addr: {32'h000000ff}}, + // '{idx: 32'd2 % NoSlvPorts_1, start_addr: {32'h000000ff}, end_addr: {32'h00000fff}}, + // '{idx: 32'd1 % NoSlvPorts_1, start_addr: {32'h00000000}, end_addr: {32'h0000000f}}, + // '{idx: 32'd0 % NoSlvPorts_1, start_addr: {32'h00000fff}, end_addr: {32'hffffffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2 = '{ + // // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'b0}, end_addr: {32'h00000fff}}, + // // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h000fffff}}, + // // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h000fffff}, end_addr: {32'h00ffffff}}, + // // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h00ffffff}, end_addr: {32'h0fffffff}}, + // // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h0fffffff}, end_addr: {32'hffffffff}} + // // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // // }; + + // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2_1 = '{ + // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h00000000}, end_addr: {32'h0000000f}}, + // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h0000000f}, end_addr: {32'h000000ff}}, + // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h0000ffff}}, + // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h0000ffff}, end_addr: {32'hffffffff}}, + // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h000000ff}, end_addr: {32'h00000fff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2_2 = '{ + // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h00000000}, end_addr: {32'h0000000f}}, + // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h0000000f}, end_addr: {32'h000000ff}}, + // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h000000ff}, end_addr: {32'h00000fff}}, + // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h0000ffff}, end_addr: {32'hffffffff}}, + // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h0000ffff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // localparam rule_t [xbar_cfg_2.NoAddrRules-1:0] AddrMap_xp2_3 = '{ + // '{idx: 32'd4 % NoSlvPorts_2, start_addr: {32'h00000fff}, end_addr: {32'h0000ffff}}, + // '{idx: 32'd3 % NoSlvPorts_2, start_addr: {32'h00000000}, end_addr: {32'h0000000f}}, + // '{idx: 32'd2 % NoSlvPorts_2, start_addr: {32'h0000000f}, end_addr: {32'h000000ff}}, + // '{idx: 32'd1 % NoSlvPorts_2, start_addr: {32'h0000ffff}, end_addr: {32'hffffffff}}, + // '{idx: 32'd0 % NoSlvPorts_2, start_addr: {32'h000000ff}, end_addr: {32'h00000fff}} + // //'{idx: 32'd0 % NoSlvPorts, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + // }; + + // //////////////////////////////// Mixed accesses (max 1 hop) end ////////////////////////////////////// + + //localparam rule_t [xbar_cfg_0.NoAddrRules-1:0] AddrMap_xp0 = '{ + // '{idx: 32'd0 % NoSlvPorts_0, start_addr: {AddrWidth{1'b0}}, end_addr: {(AddrWidth){1'b1}}} + //}; + + typedef union packed { + logic [StrbWidth-1:0][7:0] bytes; + logic [DataWidth-1:0] data; + } block_t; + + /// Address Type + typedef logic [ AddrWidth-1:0] addr_t; + /// Data Type + typedef logic [ DataWidth-1:0] data_t; + /// Strobe Type + typedef logic [ StrbWidth-1:0] strb_t; + /// AXI ID Type + typedef logic [ IdWidth-1:0] axi_id_t; + /// AXI USER Type + typedef logic [ UserWidth-1:0] user_t; + /// 1D burst request + typedef struct packed { + axi_id_t id; + addr_t src, dst, num_bytes; + axi_pkg::cache_t cache_src, cache_dst; + axi_pkg::burst_t burst_src, burst_dst; + logic decouple_rw; + logic deburst; + logic serialize; + } burst_req_t; + + // master AXI bus --> DMA + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_dma_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_dma_t, axi_id_t, user_t) + + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_dma_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_dma_t, data_t, axi_id_t, user_t) + + `AXI_TYPEDEF_REQ_T(dma_req_t, aw_chan_dma_t, w_chan_t, ar_chan_dma_t) + `AXI_TYPEDEF_RESP_T(dma_resp_t, b_chan_dma_t, r_chan_dma_t) + + // slave AXI bus --> mem + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_mem_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_mem_t, axi_id_t, user_t) + + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_mem_t, addr_t, axi_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_mem_t, data_t, axi_id_t, user_t) + + `AXI_TYPEDEF_REQ_T(mem_req_t, aw_chan_mem_t, w_chan_t, ar_chan_mem_t) + `AXI_TYPEDEF_RESP_T(mem_resp_t, b_chan_mem_t, r_chan_mem_t) + + //-------------------------------------- + // Clock and Reset + //-------------------------------------- + logic clk; + initial begin + forever begin + clk = 0; + #HalfPeriod; + clk = 1; + #HalfPeriod; + end + end + + logic rst_n; + initial begin + rst_n = 0; + #Reset; + rst_n = 1; + end + + task wait_for_reset; + @(posedge rst_n); + @(posedge clk); + endtask + + //-------------------------------------- + // DUT Axi busses + //-------------------------------------- + + dma_req_t [NoMst-1:0] axi_dma_req; + dma_resp_t [NoMst-1:0] axi_dma_res; + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) dma [NoMst-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) dma_sync [NoMst-1:0] (); + + AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) dma_dv [NoMst-1:0] (clk); + + for (genvar i = 0; i < NoMst; i++) begin : gen_conn_dv_masters + //`AXI_ASSIGN (dma_dv[i], dma[i]) + `AXI_ASSIGN_FROM_REQ(dma[i], axi_dma_req[i]) + `AXI_ASSIGN_TO_RESP(axi_dma_res[i], dma[i]) + end + + ////////////////////////////////////////// Row 1 ///////////////////////////////////////// + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_mst [NoMstPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_mst_2 [0:0] (); + + `AXI_ASSIGN (mem_0[0], xp0_mst[0]) + `AXI_ASSIGN (xp0_mst_1[0], xp0_mst[1]) + `AXI_ASSIGN (xp0_mst_2[0], xp0_mst[2]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_slv [NoSlvPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp0_slv_2 [0:0] (); + + `AXI_ASSIGN (xp0_slv[0], dma_sync[0]) + `AXI_ASSIGN (xp0_slv[1], xp0_slv_1[0]) + `AXI_ASSIGN (xp0_slv[2], xp0_slv_2[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_mst [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_mst_3 [0:0] (); + + `AXI_ASSIGN (mem_0[1], xp1_mst[0]) + `AXI_ASSIGN (xp1_mst_1[0], xp1_mst[1]) + `AXI_ASSIGN (xp1_mst_2[0], xp1_mst[2]) + `AXI_ASSIGN (xp1_mst_3[0], xp1_mst[3]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp1_slv_3 [0:0] (); + + `AXI_ASSIGN (xp1_slv[0], dma_sync[1]) + `AXI_ASSIGN (xp1_slv[1], xp1_slv_1[0]) + `AXI_ASSIGN (xp1_slv[2], xp1_slv_2[0]) + `AXI_ASSIGN (xp1_slv[3], xp1_slv_3[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_mst [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_mst_3 [0:0] (); + + `AXI_ASSIGN (mem_0[2], xp2_mst[0]) + `AXI_ASSIGN (xp2_mst_1[0], xp2_mst[1]) + `AXI_ASSIGN (xp2_mst_2[0], xp2_mst[2]) + `AXI_ASSIGN (xp2_mst_3[0], xp2_mst[3]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp2_slv_3 [0:0] (); + + `AXI_ASSIGN (xp2_slv[0], dma_sync[2]) + `AXI_ASSIGN (xp2_slv[1], xp2_slv_1[0]) + `AXI_ASSIGN (xp2_slv[2], xp2_slv_2[0]) + `AXI_ASSIGN (xp2_slv[3], xp2_slv_3[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_mst [NoMstPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_mst_2 [0:0] (); + + `AXI_ASSIGN (mem_0[3], xp3_mst[0]) + `AXI_ASSIGN (xp3_mst_1[0], xp3_mst[1]) + `AXI_ASSIGN (xp3_mst_2[0], xp3_mst[2]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_slv [NoSlvPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp3_slv_2 [0:0] (); + + `AXI_ASSIGN (xp3_slv[0], dma_sync[3]) + `AXI_ASSIGN (xp3_slv[1], xp3_slv_1[0]) + `AXI_ASSIGN (xp3_slv[2], xp3_slv_2[0]) + + /////////////////////////////////////////// Row 2 //////////////////////////////////////////////// + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp4_mst [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp4_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp4_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp4_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp4_mst_3 [0:0] (); + + `AXI_ASSIGN (mem_0[4], xp4_mst[0]) + `AXI_ASSIGN (xp4_mst_1[0], xp4_mst[1]) + `AXI_ASSIGN (xp4_mst_2[0], xp4_mst[2]) + `AXI_ASSIGN (xp4_mst_3[0], xp4_mst[3]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp4_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp4_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp4_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp4_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp4_slv_3 [0:0] (); + + `AXI_ASSIGN (xp4_slv[0], dma_sync[4]) + `AXI_ASSIGN (xp4_slv[1], xp4_slv_1[0]) + `AXI_ASSIGN (xp4_slv[2], xp4_slv_2[0]) + `AXI_ASSIGN (xp4_slv[3], xp4_slv_3[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_mst [NoMstPorts_2-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_mst_3 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_mst_4 [0:0] (); + + `AXI_ASSIGN (mem_0[5], xp5_mst[0]) + `AXI_ASSIGN (xp5_mst_1[0], xp5_mst[1]) + `AXI_ASSIGN (xp5_mst_2[0], xp5_mst[2]) + `AXI_ASSIGN (xp5_mst_3[0], xp5_mst[3]) + `AXI_ASSIGN (xp5_mst_4[0], xp5_mst[4]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_slv [NoSlvPorts_2-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_slv_3 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp5_slv_4 [0:0] (); + + `AXI_ASSIGN (xp5_slv[0], dma_sync[5]) + `AXI_ASSIGN (xp5_slv[1], xp5_slv_1[0]) + `AXI_ASSIGN (xp5_slv[2], xp5_slv_2[0]) + `AXI_ASSIGN (xp5_slv[3], xp5_slv_3[0]) + `AXI_ASSIGN (xp5_slv[4], xp5_slv_4[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_mst [NoMstPorts_2-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_mst_3 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_mst_4 [0:0] (); + + `AXI_ASSIGN (mem_0[6], xp6_mst[0]) + `AXI_ASSIGN (xp6_mst_1[0], xp6_mst[1]) + `AXI_ASSIGN (xp6_mst_2[0], xp6_mst[2]) + `AXI_ASSIGN (xp6_mst_3[0], xp6_mst[3]) + `AXI_ASSIGN (xp6_mst_4[0], xp6_mst[4]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_slv [NoSlvPorts_2-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_slv_3 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp6_slv_4 [0:0] (); + + `AXI_ASSIGN (xp6_slv[0], dma_sync[6]) + `AXI_ASSIGN (xp6_slv[1], xp6_slv_1[0]) + `AXI_ASSIGN (xp6_slv[2], xp6_slv_2[0]) + `AXI_ASSIGN (xp6_slv[3], xp6_slv_3[0]) + `AXI_ASSIGN (xp6_slv[4], xp6_slv_4[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp7_mst [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp7_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp7_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp7_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp7_mst_3 [0:0] (); + + `AXI_ASSIGN (mem_0[7], xp7_mst[0]) + `AXI_ASSIGN (xp7_mst_1[0], xp7_mst[1]) + `AXI_ASSIGN (xp7_mst_2[0], xp7_mst[2]) + `AXI_ASSIGN (xp7_mst_3[0], xp7_mst[3]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp7_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp7_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp7_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp7_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp7_slv_3 [0:0] (); + + `AXI_ASSIGN (xp7_slv[0], dma_sync[7]) + `AXI_ASSIGN (xp7_slv[1], xp7_slv_1[0]) + `AXI_ASSIGN (xp7_slv[2], xp7_slv_2[0]) + `AXI_ASSIGN (xp7_slv[3], xp7_slv_3[0]) + + /////////////////////////////////////////// Row 3 //////////////////////////////////////////////// + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp8_mst [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp8_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp8_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp8_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp8_mst_3 [0:0] (); + + `AXI_ASSIGN (mem_0[8], xp8_mst[0]) + `AXI_ASSIGN (xp8_mst_1[0], xp8_mst[1]) + `AXI_ASSIGN (xp8_mst_2[0], xp8_mst[2]) + `AXI_ASSIGN (xp8_mst_3[0], xp8_mst[3]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp8_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp8_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp8_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp8_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp8_slv_3 [0:0] (); + + `AXI_ASSIGN (xp8_slv[0], dma_sync[8]) + `AXI_ASSIGN (xp8_slv[1], xp8_slv_1[0]) + `AXI_ASSIGN (xp8_slv[2], xp8_slv_2[0]) + `AXI_ASSIGN (xp8_slv[3], xp8_slv_3[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_mst [NoMstPorts_2-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_mst_3 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_mst_4 [0:0] (); + + `AXI_ASSIGN (mem_0[9], xp9_mst[0]) + `AXI_ASSIGN (xp9_mst_1[0], xp9_mst[1]) + `AXI_ASSIGN (xp9_mst_2[0], xp9_mst[2]) + `AXI_ASSIGN (xp9_mst_3[0], xp9_mst[3]) + `AXI_ASSIGN (xp9_mst_4[0], xp9_mst[4]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_slv [NoSlvPorts_2-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_slv_3 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp9_slv_4 [0:0] (); + + `AXI_ASSIGN (xp9_slv[0], dma_sync[9]) + `AXI_ASSIGN (xp9_slv[1], xp9_slv_1[0]) + `AXI_ASSIGN (xp9_slv[2], xp9_slv_2[0]) + `AXI_ASSIGN (xp9_slv[3], xp9_slv_3[0]) + `AXI_ASSIGN (xp9_slv[4], xp9_slv_4[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_mst [NoMstPorts_2-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_mst_3 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_mst_4 [0:0] (); + + `AXI_ASSIGN (mem_0[10], xp10_mst[0]) + `AXI_ASSIGN (xp10_mst_1[0], xp10_mst[1]) + `AXI_ASSIGN (xp10_mst_2[0], xp10_mst[2]) + `AXI_ASSIGN (xp10_mst_3[0], xp10_mst[3]) + `AXI_ASSIGN (xp10_mst_4[0], xp10_mst[4]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_slv [NoSlvPorts_2-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_slv_3 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp10_slv_4 [0:0] (); + + `AXI_ASSIGN (xp10_slv[0], dma_sync[10]) + `AXI_ASSIGN (xp10_slv[1], xp10_slv_1[0]) + `AXI_ASSIGN (xp10_slv[2], xp10_slv_2[0]) + `AXI_ASSIGN (xp10_slv[3], xp10_slv_3[0]) + `AXI_ASSIGN (xp10_slv[4], xp10_slv_4[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp11_mst [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp11_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp11_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp11_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp11_mst_3 [0:0] (); + + `AXI_ASSIGN (mem_0[11], xp11_mst[0]) + `AXI_ASSIGN (xp11_mst_1[0], xp11_mst[1]) + `AXI_ASSIGN (xp11_mst_2[0], xp11_mst[2]) + `AXI_ASSIGN (xp11_mst_3[0], xp11_mst[3]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp11_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp11_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp11_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp11_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp11_slv_3 [0:0] (); + + `AXI_ASSIGN (xp11_slv[0], dma_sync[11]) + `AXI_ASSIGN (xp11_slv[1], xp11_slv_1[0]) + `AXI_ASSIGN (xp11_slv[2], xp11_slv_2[0]) + `AXI_ASSIGN (xp11_slv[3], xp11_slv_3[0]) + + ////////////////////////////////////////////// Row 4 /////////////////////////////////////////// + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp12_mst [NoMstPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp12_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp12_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp12_mst_2 [0:0] (); + + `AXI_ASSIGN (mem_0[12], xp12_mst[0]) + `AXI_ASSIGN (xp12_mst_1[0], xp12_mst[1]) + `AXI_ASSIGN (xp12_mst_2[0], xp12_mst[2]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp12_slv [NoSlvPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp12_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp12_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp12_slv_2 [0:0] (); + + `AXI_ASSIGN (xp12_slv[0], dma_sync[12]) + `AXI_ASSIGN (xp12_slv[1], xp12_slv_1[0]) + `AXI_ASSIGN (xp12_slv[2], xp12_slv_2[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp13_mst [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp13_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp13_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp13_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp13_mst_3 [0:0] (); + + `AXI_ASSIGN (mem_0[13], xp13_mst[0]) + `AXI_ASSIGN (xp13_mst_1[0], xp13_mst[1]) + `AXI_ASSIGN (xp13_mst_2[0], xp13_mst[2]) + `AXI_ASSIGN (xp13_mst_3[0], xp13_mst[3]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp13_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp13_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp13_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp13_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp13_slv_3 [0:0] (); + + `AXI_ASSIGN (xp13_slv[0], dma_sync[13]) + `AXI_ASSIGN (xp13_slv[1], xp13_slv_1[0]) + `AXI_ASSIGN (xp13_slv[2], xp13_slv_2[0]) + `AXI_ASSIGN (xp13_slv[3], xp13_slv_3[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp14_mst [NoMstPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp14_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp14_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp14_mst_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp14_mst_3 [0:0] (); + + `AXI_ASSIGN (mem_0[14], xp14_mst[0]) + `AXI_ASSIGN (xp14_mst_1[0], xp14_mst[1]) + `AXI_ASSIGN (xp14_mst_2[0], xp14_mst[2]) + `AXI_ASSIGN (xp14_mst_3[0], xp14_mst[3]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp14_slv [NoSlvPorts_1-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp14_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp14_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp14_slv_2 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp14_slv_3 [0:0] (); + + `AXI_ASSIGN (xp14_slv[0], dma_sync[14]) + `AXI_ASSIGN (xp14_slv[1], xp14_slv_1[0]) + `AXI_ASSIGN (xp14_slv[2], xp14_slv_2[0]) + `AXI_ASSIGN (xp14_slv[3], xp14_slv_3[0]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp15_mst [NoMstPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp15_mst_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp15_mst_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp15_mst_2 [0:0] (); + + `AXI_ASSIGN (mem_0[15], xp15_mst[0]) + `AXI_ASSIGN (xp15_mst_1[0], xp15_mst[1]) + `AXI_ASSIGN (xp15_mst_2[0], xp15_mst[2]) + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp15_slv [NoSlvPorts_0-1:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp15_slv_0 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp15_slv_1 [0:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) xp15_slv_2 [0:0] (); + + `AXI_ASSIGN (xp15_slv[0], dma_sync[15]) + `AXI_ASSIGN (xp15_slv[1], xp15_slv_1[0]) + `AXI_ASSIGN (xp15_slv[2], xp15_slv_2[0]) + + // XP0 <--> XP1 + + `AXI_ASSIGN (xp1_slv_1[0], xp0_mst_1[0]) + `AXI_ASSIGN (xp0_slv_1[0], xp1_mst_1[0]) + + // XP0 <--> XP4 + + `AXI_ASSIGN (xp4_slv_2[0], xp0_mst_2[0]) + `AXI_ASSIGN (xp0_slv_2[0], xp4_mst_2[0]) + + // XP1 <--> XP2 + + `AXI_ASSIGN (xp2_slv_3[0], xp1_mst_3[0]) + `AXI_ASSIGN (xp1_slv_3[0], xp2_mst_3[0]) + + // XP1 <--> XP5 + + `AXI_ASSIGN (xp5_slv_2[0], xp1_mst_2[0]) + `AXI_ASSIGN (xp1_slv_2[0], xp5_mst_2[0]) + + // XP2 <--> XP3 + + `AXI_ASSIGN (xp2_slv_1[0], xp3_mst_1[0]) + `AXI_ASSIGN (xp3_slv_1[0], xp2_mst_1[0]) + + // XP2 <--> XP6 + + `AXI_ASSIGN (xp6_slv_2[0], xp2_mst_2[0]) + `AXI_ASSIGN (xp2_slv_2[0], xp6_mst_2[0]) + + // XP3 <--> XP7 + + `AXI_ASSIGN (xp7_slv_2[0], xp3_mst_2[0]) + `AXI_ASSIGN (xp3_slv_2[0], xp7_mst_2[0]) + + // XP4 <--> XP5 + + `AXI_ASSIGN (xp5_slv_1[0], xp4_mst_1[0]) + `AXI_ASSIGN (xp4_slv_1[0], xp5_mst_1[0]) + + // XP4 <--> XP8 + + `AXI_ASSIGN (xp8_slv_3[0], xp4_mst_3[0]) + `AXI_ASSIGN (xp4_slv_3[0], xp8_mst_3[0]) + + // XP5 <--> XP6 + + `AXI_ASSIGN (xp6_slv_3[0], xp5_mst_3[0]) + `AXI_ASSIGN (xp5_slv_3[0], xp6_mst_3[0]) + + // XP5 <--> XP9 + + `AXI_ASSIGN (xp9_slv_4[0], xp5_mst_4[0]) + `AXI_ASSIGN (xp5_slv_4[0], xp9_mst_4[0]) + + // XP6 <--> XP7 + + `AXI_ASSIGN (xp7_slv_1[0], xp6_mst_1[0]) + `AXI_ASSIGN (xp6_slv_1[0], xp7_mst_1[0]) + + // XP6 <--> XP10 + + `AXI_ASSIGN (xp10_slv_4[0], xp6_mst_4[0]) + `AXI_ASSIGN (xp6_slv_4[0], xp10_mst_4[0]) + + // XP7 <--> XP11 + + `AXI_ASSIGN (xp11_slv_3[0], xp7_mst_3[0]) + `AXI_ASSIGN (xp7_slv_3[0], xp11_mst_3[0]) + + // XP8 <--> XP9 + + `AXI_ASSIGN (xp9_slv_1[0], xp8_mst_1[0]) + `AXI_ASSIGN (xp8_slv_1[0], xp9_mst_1[0]) + + // XP8 <--> XP12 + + `AXI_ASSIGN (xp12_slv_2[0], xp8_mst_2[0]) + `AXI_ASSIGN (xp8_slv_2[0], xp12_mst_2[0]) + + // XP9 <--> XP10 + + `AXI_ASSIGN (xp10_slv_3[0], xp9_mst_3[0]) + `AXI_ASSIGN (xp9_slv_3[0], xp10_mst_3[0]) + + // XP9 <--> XP13 + + `AXI_ASSIGN (xp13_slv_2[0], xp9_mst_2[0]) + `AXI_ASSIGN (xp9_slv_2[0], xp13_mst_2[0]) + + // XP10 <--> XP11 + + `AXI_ASSIGN (xp11_slv_1[0], xp10_mst_1[0]) + `AXI_ASSIGN (xp10_slv_1[0], xp11_mst_1[0]) + + // XP10 <--> XP14 + + `AXI_ASSIGN (xp14_slv_2[0], xp10_mst_2[0]) + `AXI_ASSIGN (xp10_slv_2[0], xp14_mst_2[0]) + + // XP11 <--> XP15 + + `AXI_ASSIGN (xp15_slv_2[0], xp11_mst_2[0]) + `AXI_ASSIGN (xp11_slv_2[0], xp15_mst_2[0]) + + // XP12 <--> XP13 + + `AXI_ASSIGN (xp13_slv_1[0], xp12_mst_1[0]) + `AXI_ASSIGN (xp12_slv_1[0], xp13_mst_1[0]) + + // XP13 <--> XP14 + + `AXI_ASSIGN (xp14_slv_3[0], xp13_mst_3[0]) + `AXI_ASSIGN (xp13_slv_3[0], xp14_mst_3[0]) + + // XP14 <--> XP15 + + `AXI_ASSIGN (xp15_slv_1[0], xp14_mst_1[0]) + `AXI_ASSIGN (xp14_slv_1[0], xp15_mst_1[0]) + + AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) mem_dv [NoSlv-1:0] (clk); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( 1 ) + ) mem_0 [NoSlv-1:0] (); + + `AXI_ASSIGN (mem_dv[0], mem_0[0]) + `AXI_ASSIGN (mem_dv[1], mem_0[1]) + `AXI_ASSIGN (mem_dv[2], mem_0[2]) + `AXI_ASSIGN (mem_dv[3], mem_0[3]) + `AXI_ASSIGN (mem_dv[4], mem_0[4]) + `AXI_ASSIGN (mem_dv[5], mem_0[5]) + `AXI_ASSIGN (mem_dv[6], mem_0[6]) + `AXI_ASSIGN (mem_dv[7], mem_0[7]) + `AXI_ASSIGN (mem_dv[8], mem_0[8]) + `AXI_ASSIGN (mem_dv[9], mem_0[9]) + `AXI_ASSIGN (mem_dv[10], mem_0[10]) + `AXI_ASSIGN (mem_dv[11], mem_0[11]) + `AXI_ASSIGN (mem_dv[12], mem_0[12]) + `AXI_ASSIGN (mem_dv[13], mem_0[13]) + `AXI_ASSIGN (mem_dv[14], mem_0[14]) + `AXI_ASSIGN (mem_dv[15], mem_0[15]) + + //`AXI_ASSIGN (mem_dv[1], mem_1[0]) + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma1_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma2_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma3_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma4_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma5_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma6_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma7_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma8_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma9_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma10_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma11_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma12_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma13_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma14_t; + + typedef axi_test::axi_driver #( + .AW(AddrWidth), .DW(DataWidth), .IW(IdWidth), .UW(UserWidth), + .TA(0.1*2*HalfPeriod), .TT(0.9*2*HalfPeriod) + ) driver_dma15_t; + + driver_dma_t driver_dma = new(mem_dv[0]); + driver_dma1_t driver_dma1 = new(mem_dv[1]); + driver_dma2_t driver_dma2 = new(mem_dv[2]); + driver_dma3_t driver_dma3 = new(mem_dv[3]); + driver_dma4_t driver_dma4 = new(mem_dv[4]); + driver_dma5_t driver_dma5 = new(mem_dv[5]); + driver_dma6_t driver_dma6 = new(mem_dv[6]); + driver_dma7_t driver_dma7 = new(mem_dv[7]); + driver_dma8_t driver_dma8 = new(mem_dv[8]); + driver_dma9_t driver_dma9 = new(mem_dv[9]); + driver_dma10_t driver_dma10 = new(mem_dv[10]); + driver_dma11_t driver_dma11 = new(mem_dv[11]); + driver_dma12_t driver_dma12 = new(mem_dv[12]); + driver_dma13_t driver_dma13 = new(mem_dv[13]); + driver_dma14_t driver_dma14 = new(mem_dv[14]); + driver_dma15_t driver_dma15 = new(mem_dv[15]); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem0 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[0]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem1 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[1]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem2 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[2]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem3 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[3]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem4 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[4]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem5 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[5]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem6 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[6]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem7 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[7]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem8 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[8]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem9 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[9]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem10 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[10]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem11 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[11]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem12 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[12]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem13 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[13]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem14 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[14]) + ); + + axi_sim_mem_intf #( + .AXI_ADDR_WIDTH (AddrWidth), + .AXI_DATA_WIDTH (DataWidth), + .AXI_ID_WIDTH (IdWidth), + .AXI_USER_WIDTH (UserWidth), + .WARN_UNINITIALIZED (1'b0), + .APPL_DELAY (2ns), + .ACQ_DELAY (8ns) + ) i_sim_mem15 ( + .clk_i (clk), + .rst_ni (rst_n), + .axi_slv (mem_dv[15]) + ); + + // initial begin + // $readmemh("sim_mem0.mem", i_sim_mem0.mem); + // $readmemh("sim_mem1.mem", i_sim_mem1.mem); + // end + + //-------------------------------------- + // DUT AXI Memory System + //-------------------------------------- + // lfsr + logic [784:0] lfsr_dut_q, lfsr_dut_d; + + // transaction id + logic [ 7:0] transaction_id = 0; + + // Memory + block_t dma_memory [bit [AddrWidth-$clog2($bits(block_t))-1:0]]; + block_t dma_memory1 [bit [AddrWidth-$clog2($bits(block_t))-1:0]]; + + //-------------------------------------- + // DMA instantiation + //-------------------------------------- + burst_req_t burst0_req; + burst_req_t burst1_req; + logic burst0_req_valid; + logic burst1_req_valid; + logic burst0_req_ready; + logic burst1_req_ready; + logic backend_idle_0; + logic backend_idle_1; + burst_req_t burst2_req; + burst_req_t burst3_req; + logic burst2_req_valid; + logic burst3_req_valid; + logic burst2_req_ready; + logic burst3_req_ready; + logic backend_idle_2; + logic backend_idle_3; + burst_req_t burst4_req; + burst_req_t burst5_req; + logic burst4_req_valid; + logic burst5_req_valid; + logic burst4_req_ready; + logic burst5_req_ready; + logic backend_idle_4; + logic backend_idle_5; + burst_req_t burst6_req; + burst_req_t burst7_req; + logic burst6_req_valid; + logic burst7_req_valid; + logic burst6_req_ready; + logic burst7_req_ready; + logic backend_idle_6; + logic backend_idle_7; + + burst_req_t burst8_req; + burst_req_t burst9_req; + logic burst8_req_valid; + logic burst9_req_valid; + logic burst8_req_ready; + logic burst9_req_ready; + logic backend_idle_8; + logic backend_idle_9; + burst_req_t burst10_req; + burst_req_t burst11_req; + logic burst10_req_valid; + logic burst11_req_valid; + logic burst10_req_ready; + logic burst11_req_ready; + logic backend_idle_10; + logic backend_idle_11; + burst_req_t burst12_req; + burst_req_t burst13_req; + logic burst12_req_valid; + logic burst13_req_valid; + logic burst12_req_ready; + logic burst13_req_ready; + logic backend_idle_12; + logic backend_idle_13; + burst_req_t burst14_req; + burst_req_t burst15_req; + logic burst14_req_valid; + logic burst15_req_valid; + logic burst14_req_ready; + logic burst15_req_ready; + logic backend_idle_14; + logic backend_idle_15; + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_0 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[0] ), + .axi_dma_res_i ( axi_dma_res[0] ), + .burst_req_i ( burst0_req ), + .valid_i ( burst0_req_valid ), + .ready_o ( burst0_req_ready ), + .backend_idle_o ( backend_idle_0 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000000 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_0 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[0] ), + .out ( dma_sync[0] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_1 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[1] ), + .axi_dma_res_i ( axi_dma_res[1] ), + .burst_req_i ( burst1_req ), + .valid_i ( burst1_req_valid ), + .ready_o ( burst1_req_ready ), + .backend_idle_o ( backend_idle_1 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000001 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_1 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[1] ), + .out ( dma_sync[1] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_2 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[2] ), + .axi_dma_res_i ( axi_dma_res[2] ), + .burst_req_i ( burst2_req ), + .valid_i ( burst2_req_valid ), + .ready_o ( burst2_req_ready ), + .backend_idle_o ( backend_idle_2 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000002 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_2 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[2] ), + .out ( dma_sync[2] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_3 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[3] ), + .axi_dma_res_i ( axi_dma_res[3] ), + .burst_req_i ( burst3_req ), + .valid_i ( burst3_req_valid ), + .ready_o ( burst3_req_ready ), + .backend_idle_o ( backend_idle_3 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000003 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_3 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[3] ), + .out ( dma_sync[3] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_4 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[4] ), + .axi_dma_res_i ( axi_dma_res[4] ), + .burst_req_i ( burst4_req ), + .valid_i ( burst4_req_valid ), + .ready_o ( burst4_req_ready ), + .backend_idle_o ( backend_idle_4 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000004 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_4 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[4] ), + .out ( dma_sync[4] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_5 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[5] ), + .axi_dma_res_i ( axi_dma_res[5] ), + .burst_req_i ( burst5_req ), + .valid_i ( burst5_req_valid ), + .ready_o ( burst5_req_ready ), + .backend_idle_o ( backend_idle_5 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000005 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_5 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[5] ), + .out ( dma_sync[5] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_6 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[6] ), + .axi_dma_res_i ( axi_dma_res[6] ), + .burst_req_i ( burst6_req ), + .valid_i ( burst6_req_valid ), + .ready_o ( burst6_req_ready ), + .backend_idle_o ( backend_idle_6 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000006 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_6 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[6] ), + .out ( dma_sync[6] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_7 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[7] ), + .axi_dma_res_i ( axi_dma_res[7] ), + .burst_req_i ( burst7_req ), + .valid_i ( burst7_req_valid ), + .ready_o ( burst7_req_ready ), + .backend_idle_o ( backend_idle_7 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000007 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_7 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[7] ), + .out ( dma_sync[7] ) + ); + + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_8 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[8] ), + .axi_dma_res_i ( axi_dma_res[8] ), + .burst_req_i ( burst8_req ), + .valid_i ( burst8_req_valid ), + .ready_o ( burst8_req_ready ), + .backend_idle_o ( backend_idle_8 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000008 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_8 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[8] ), + .out ( dma_sync[8] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_9 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[9] ), + .axi_dma_res_i ( axi_dma_res[9] ), + .burst_req_i ( burst9_req ), + .valid_i ( burst9_req_valid ), + .ready_o ( burst9_req_ready ), + .backend_idle_o ( backend_idle_9 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h00000009 ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_9 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[9] ), + .out ( dma_sync[9] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_10 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[10] ), + .axi_dma_res_i ( axi_dma_res[10] ), + .burst_req_i ( burst10_req ), + .valid_i ( burst10_req_valid ), + .ready_o ( burst10_req_ready ), + .backend_idle_o ( backend_idle_10 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h0000000a ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_10 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[10] ), + .out ( dma_sync[10] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_11 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[11] ), + .axi_dma_res_i ( axi_dma_res[11] ), + .burst_req_i ( burst11_req ), + .valid_i ( burst11_req_valid ), + .ready_o ( burst11_req_ready ), + .backend_idle_o ( backend_idle_11 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h0000000b ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_11 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[11] ), + .out ( dma_sync[11] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_12 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[12] ), + .axi_dma_res_i ( axi_dma_res[12] ), + .burst_req_i ( burst12_req ), + .valid_i ( burst12_req_valid ), + .ready_o ( burst12_req_ready ), + .backend_idle_o ( backend_idle_12 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h0000000c ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_12 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[12] ), + .out ( dma_sync[12] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_13 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[13] ), + .axi_dma_res_i ( axi_dma_res[13] ), + .burst_req_i ( burst13_req ), + .valid_i ( burst13_req_valid ), + .ready_o ( burst13_req_ready ), + .backend_idle_o ( backend_idle_13 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h0000000d ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_13 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[13] ), + .out ( dma_sync[13] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_14 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[14] ), + .axi_dma_res_i ( axi_dma_res[14] ), + .burst_req_i ( burst14_req ), + .valid_i ( burst14_req_valid ), + .ready_o ( burst14_req_ready ), + .backend_idle_o ( backend_idle_14 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h0000000e ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_14 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[14] ), + .out ( dma_sync[14] ) + ); + + axi_dma_backend #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .DmaIdWidth ( 32 ), + .AxReqFifoDepth ( 3 ), + .TransFifoDepth ( 2 ), + .BufferDepth ( 3 ), + .axi_req_t ( dma_req_t ), + .axi_res_t ( dma_resp_t ), + .burst_req_t ( burst_req_t ), + .DmaTracing ( 1 ) + ) i_dut_axi_backend_15 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_dma_req_o ( axi_dma_req[15] ), + .axi_dma_res_i ( axi_dma_res[15] ), + .burst_req_i ( burst15_req ), + .valid_i ( burst15_req_valid ), + .ready_o ( burst15_req_ready ), + .backend_idle_o ( backend_idle_15 ), + .trans_complete_o ( ), + .dma_id_i ( 32'h0000000f ) + ); + + axi_aw_w_sync_intf #( + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( IdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) i_aw_w_sync_intf_15 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .in ( dma[15] ), + .out ( dma_sync[15] ) + ); + + //----------------------------------- + // DUT + //----------------------------------- + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_0 ), + .NoSlvPorts ( xbar_cfg_0.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_0.NoMstPorts ), + .Connectivity ( Connectivity_0 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_0.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_15 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp15_slv ), + .mst_ports ( xp15_mst ), + .addr_map_i ( AddrMap_xp0 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_14 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp14_slv ), + .mst_ports ( xp14_mst ), + .addr_map_i ( AddrMap_xp1 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_13 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp13_slv ), + .mst_ports ( xp13_mst ), + .addr_map_i ( AddrMap_xp1 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_0 ), + .NoSlvPorts ( xbar_cfg_0.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_0.NoMstPorts ), + .Connectivity ( Connectivity_0 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_0.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_12 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp12_slv ), + .mst_ports ( xp12_mst ), + .addr_map_i ( AddrMap_xp0 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_11 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp11_slv ), + .mst_ports ( xp11_mst ), + .addr_map_i ( AddrMap_xp1 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_2 ), + .NoSlvPorts ( xbar_cfg_2.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_2.NoMstPorts ), + .Connectivity ( Connectivity_2 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_2.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_10 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp10_slv ), + .mst_ports ( xp10_mst ), + .addr_map_i ( AddrMap_xp2_1 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_2 ), + .NoSlvPorts ( xbar_cfg_2.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_2.NoMstPorts ), + .Connectivity ( Connectivity_2 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_2.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_9 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp9_slv ), + .mst_ports ( xp9_mst ), + .addr_map_i ( AddrMap_xp2_3 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_8 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp8_slv ), + .mst_ports ( xp8_mst ), + .addr_map_i ( AddrMap_xp1 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_7 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp7_slv ), + .mst_ports ( xp7_mst ), + .addr_map_i ( AddrMap_xp1 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_2 ), + .NoSlvPorts ( xbar_cfg_2.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_2.NoMstPorts ), + .Connectivity ( Connectivity_2 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_2.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_6 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp6_slv ), + .mst_ports ( xp6_mst ), + .addr_map_i ( AddrMap_xp2_1 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_2 ), + .NoSlvPorts ( xbar_cfg_2.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_2.NoMstPorts ), + .Connectivity ( Connectivity_2 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_2.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_5 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp5_slv ), + .mst_ports ( xp5_mst ), + .addr_map_i ( AddrMap_xp2_2 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_4 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp4_slv ), + .mst_ports ( xp4_mst ), + .addr_map_i ( AddrMap_xp1 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_0 ), + .NoSlvPorts ( xbar_cfg_0.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_0.NoMstPorts ), + .Connectivity ( Connectivity_0 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_0.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_3 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp3_slv ), + .mst_ports ( xp3_mst ), + .addr_map_i ( AddrMap_xp0 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_2 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp2_slv ), + .mst_ports ( xp2_mst ), + .addr_map_i ( AddrMap_xp1 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_1 ), + .NoSlvPorts ( xbar_cfg_1.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_1.NoMstPorts ), + .Connectivity ( Connectivity_1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_1.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_1 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp1_slv ), + .mst_ports ( xp1_mst ), + .addr_map_i ( AddrMap_xp1 ) + ); + + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg_0 ), + .NoSlvPorts ( xbar_cfg_0.NoSlvPorts ), + .NoMstPorts ( xbar_cfg_0.NoMstPorts ), + .Connectivity ( Connectivity_0 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg_0.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut_0 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( xp0_slv ), + .mst_ports ( xp0_mst ), + .addr_map_i ( AddrMap_xp0 ) + ); + + //-------------------------------------- + // DMA DUT tasks + //-------------------------------------- + + task oned_dut_launch_15 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst15_req_valid <= 1'b0; + burst15_req <= '0; + @(posedge clk); + while (burst15_req_ready !== 1) @(posedge clk); + // write data + burst15_req.id <= transf_id_i; + burst15_req.src <= src_addr_i; + burst15_req.dst <= dst_addr_i; + burst15_req.num_bytes <= num_bytes_i; + burst15_req.cache_src <= src_cache_i; + burst15_req.cache_dst <= dst_cache_i; + burst15_req.burst_src <= src_burst_i; + burst15_req.burst_dst <= dst_burst_i; + burst15_req.decouple_rw <= decouple_rw_i; + burst15_req.deburst <= deburst_i; + burst15_req.serialize <= serialize_i; + burst15_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst15_req_valid <= 1'b0; + burst15_req <= '0; + endtask + + task oned_dut_launch_14 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst14_req_valid <= 1'b0; + burst14_req <= '0; + @(posedge clk); + while (burst14_req_ready !== 1) @(posedge clk); + // write data + burst14_req.id <= transf_id_i; + burst14_req.src <= src_addr_i; + burst14_req.dst <= dst_addr_i; + burst14_req.num_bytes <= num_bytes_i; + burst14_req.cache_src <= src_cache_i; + burst14_req.cache_dst <= dst_cache_i; + burst14_req.burst_src <= src_burst_i; + burst14_req.burst_dst <= dst_burst_i; + burst14_req.decouple_rw <= decouple_rw_i; + burst14_req.deburst <= deburst_i; + burst14_req.serialize <= serialize_i; + burst14_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst14_req_valid <= 1'b0; + burst14_req <= '0; + endtask + + task oned_dut_launch_13 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst13_req_valid <= 1'b0; + burst13_req <= '0; + @(posedge clk); + while (burst13_req_ready !== 1) @(posedge clk); + // write data + burst13_req.id <= transf_id_i; + burst13_req.src <= src_addr_i; + burst13_req.dst <= dst_addr_i; + burst13_req.num_bytes <= num_bytes_i; + burst13_req.cache_src <= src_cache_i; + burst13_req.cache_dst <= dst_cache_i; + burst13_req.burst_src <= src_burst_i; + burst13_req.burst_dst <= dst_burst_i; + burst13_req.decouple_rw <= decouple_rw_i; + burst13_req.deburst <= deburst_i; + burst13_req.serialize <= serialize_i; + burst13_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst13_req_valid <= 1'b0; + burst13_req <= '0; + endtask + + task oned_dut_launch_12 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst12_req_valid <= 1'b0; + burst12_req <= '0; + @(posedge clk); + while (burst12_req_ready !== 1) @(posedge clk); + // write data + burst12_req.id <= transf_id_i; + burst12_req.src <= src_addr_i; + burst12_req.dst <= dst_addr_i; + burst12_req.num_bytes <= num_bytes_i; + burst12_req.cache_src <= src_cache_i; + burst12_req.cache_dst <= dst_cache_i; + burst12_req.burst_src <= src_burst_i; + burst12_req.burst_dst <= dst_burst_i; + burst12_req.decouple_rw <= decouple_rw_i; + burst12_req.deburst <= deburst_i; + burst12_req.serialize <= serialize_i; + burst12_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst12_req_valid <= 1'b0; + burst12_req <= '0; + endtask + + task oned_dut_launch_11 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst11_req_valid <= 1'b0; + burst11_req <= '0; + @(posedge clk); + while (burst11_req_ready !== 1) @(posedge clk); + // write data + burst11_req.id <= transf_id_i; + burst11_req.src <= src_addr_i; + burst11_req.dst <= dst_addr_i; + burst11_req.num_bytes <= num_bytes_i; + burst11_req.cache_src <= src_cache_i; + burst11_req.cache_dst <= dst_cache_i; + burst11_req.burst_src <= src_burst_i; + burst11_req.burst_dst <= dst_burst_i; + burst11_req.decouple_rw <= decouple_rw_i; + burst11_req.deburst <= deburst_i; + burst11_req.serialize <= serialize_i; + burst11_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst11_req_valid <= 1'b0; + burst11_req <= '0; + endtask + + task oned_dut_launch_10 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst10_req_valid <= 1'b0; + burst10_req <= '0; + @(posedge clk); + while (burst10_req_ready !== 1) @(posedge clk); + // write data + burst10_req.id <= transf_id_i; + burst10_req.src <= src_addr_i; + burst10_req.dst <= dst_addr_i; + burst10_req.num_bytes <= num_bytes_i; + burst10_req.cache_src <= src_cache_i; + burst10_req.cache_dst <= dst_cache_i; + burst10_req.burst_src <= src_burst_i; + burst10_req.burst_dst <= dst_burst_i; + burst10_req.decouple_rw <= decouple_rw_i; + burst10_req.deburst <= deburst_i; + burst10_req.serialize <= serialize_i; + burst10_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst10_req_valid <= 1'b0; + burst10_req <= '0; + endtask + + task oned_dut_launch_9 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst9_req_valid <= 1'b0; + burst9_req <= '0; + @(posedge clk); + while (burst9_req_ready !== 1) @(posedge clk); + // write data + burst9_req.id <= transf_id_i; + burst9_req.src <= src_addr_i; + burst9_req.dst <= dst_addr_i; + burst9_req.num_bytes <= num_bytes_i; + burst9_req.cache_src <= src_cache_i; + burst9_req.cache_dst <= dst_cache_i; + burst9_req.burst_src <= src_burst_i; + burst9_req.burst_dst <= dst_burst_i; + burst9_req.decouple_rw <= decouple_rw_i; + burst9_req.deburst <= deburst_i; + burst9_req.serialize <= serialize_i; + burst9_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst9_req_valid <= 1'b0; + burst9_req <= '0; + endtask + + task oned_dut_launch_8 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst8_req_valid <= 1'b0; + burst8_req <= '0; + @(posedge clk); + while (burst8_req_ready !== 1) @(posedge clk); + // write data + burst8_req.id <= transf_id_i; + burst8_req.src <= src_addr_i; + burst8_req.dst <= dst_addr_i; + burst8_req.num_bytes <= num_bytes_i; + burst8_req.cache_src <= src_cache_i; + burst8_req.cache_dst <= dst_cache_i; + burst8_req.burst_src <= src_burst_i; + burst8_req.burst_dst <= dst_burst_i; + burst8_req.decouple_rw <= decouple_rw_i; + burst8_req.deburst <= deburst_i; + burst8_req.serialize <= serialize_i; + burst8_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst8_req_valid <= 1'b0; + burst8_req <= '0; + endtask + + task oned_dut_launch_7 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst7_req_valid <= 1'b0; + burst7_req <= '0; + @(posedge clk); + while (burst7_req_ready !== 1) @(posedge clk); + // write data + burst7_req.id <= transf_id_i; + burst7_req.src <= src_addr_i; + burst7_req.dst <= dst_addr_i; + burst7_req.num_bytes <= num_bytes_i; + burst7_req.cache_src <= src_cache_i; + burst7_req.cache_dst <= dst_cache_i; + burst7_req.burst_src <= src_burst_i; + burst7_req.burst_dst <= dst_burst_i; + burst7_req.decouple_rw <= decouple_rw_i; + burst7_req.deburst <= deburst_i; + burst7_req.serialize <= serialize_i; + burst7_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst7_req_valid <= 1'b0; + burst7_req <= '0; + endtask + + task oned_dut_launch_6 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst6_req_valid <= 1'b0; + burst6_req <= '0; + @(posedge clk); + while (burst6_req_ready !== 1) @(posedge clk); + // write data + burst6_req.id <= transf_id_i; + burst6_req.src <= src_addr_i; + burst6_req.dst <= dst_addr_i; + burst6_req.num_bytes <= num_bytes_i; + burst6_req.cache_src <= src_cache_i; + burst6_req.cache_dst <= dst_cache_i; + burst6_req.burst_src <= src_burst_i; + burst6_req.burst_dst <= dst_burst_i; + burst6_req.decouple_rw <= decouple_rw_i; + burst6_req.deburst <= deburst_i; + burst6_req.serialize <= serialize_i; + burst6_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst6_req_valid <= 1'b0; + burst6_req <= '0; + endtask + + task oned_dut_launch_5 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst5_req_valid <= 1'b0; + burst5_req <= '0; + @(posedge clk); + while (burst5_req_ready !== 1) @(posedge clk); + // write data + burst5_req.id <= transf_id_i; + burst5_req.src <= src_addr_i; + burst5_req.dst <= dst_addr_i; + burst5_req.num_bytes <= num_bytes_i; + burst5_req.cache_src <= src_cache_i; + burst5_req.cache_dst <= dst_cache_i; + burst5_req.burst_src <= src_burst_i; + burst5_req.burst_dst <= dst_burst_i; + burst5_req.decouple_rw <= decouple_rw_i; + burst5_req.deburst <= deburst_i; + burst5_req.serialize <= serialize_i; + burst5_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst5_req_valid <= 1'b0; + burst5_req <= '0; + endtask + + task oned_dut_launch_4 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst4_req_valid <= 1'b0; + burst4_req <= '0; + @(posedge clk); + while (burst4_req_ready !== 1) @(posedge clk); + // write data + burst4_req.id <= transf_id_i; + burst4_req.src <= src_addr_i; + burst4_req.dst <= dst_addr_i; + burst4_req.num_bytes <= num_bytes_i; + burst4_req.cache_src <= src_cache_i; + burst4_req.cache_dst <= dst_cache_i; + burst4_req.burst_src <= src_burst_i; + burst4_req.burst_dst <= dst_burst_i; + burst4_req.decouple_rw <= decouple_rw_i; + burst4_req.deburst <= deburst_i; + burst4_req.serialize <= serialize_i; + burst4_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst4_req_valid <= 1'b0; + burst4_req <= '0; + endtask + + task oned_dut_launch_3 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst3_req_valid <= 1'b0; + burst3_req <= '0; + @(posedge clk); + while (burst3_req_ready !== 1) @(posedge clk); + // write data + burst3_req.id <= transf_id_i; + burst3_req.src <= src_addr_i; + burst3_req.dst <= dst_addr_i; + burst3_req.num_bytes <= num_bytes_i; + burst3_req.cache_src <= src_cache_i; + burst3_req.cache_dst <= dst_cache_i; + burst3_req.burst_src <= src_burst_i; + burst3_req.burst_dst <= dst_burst_i; + burst3_req.decouple_rw <= decouple_rw_i; + burst3_req.deburst <= deburst_i; + burst3_req.serialize <= serialize_i; + burst3_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst3_req_valid <= 1'b0; + burst3_req <= '0; + endtask + + task oned_dut_launch_2 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst2_req_valid <= 1'b0; + burst2_req <= '0; + @(posedge clk); + while (burst2_req_ready !== 1) @(posedge clk); + // write data + burst2_req.id <= transf_id_i; + burst2_req.src <= src_addr_i; + burst2_req.dst <= dst_addr_i; + burst2_req.num_bytes <= num_bytes_i; + burst2_req.cache_src <= src_cache_i; + burst2_req.cache_dst <= dst_cache_i; + burst2_req.burst_src <= src_burst_i; + burst2_req.burst_dst <= dst_burst_i; + burst2_req.decouple_rw <= decouple_rw_i; + burst2_req.deburst <= deburst_i; + burst2_req.serialize <= serialize_i; + burst2_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst2_req_valid <= 1'b0; + burst2_req <= '0; + endtask + + task oned_dut_launch_1 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst1_req_valid <= 1'b0; + burst1_req <= '0; + @(posedge clk); + while (burst1_req_ready !== 1) @(posedge clk); + // write data + burst1_req.id <= transf_id_i; + burst1_req.src <= src_addr_i; + burst1_req.dst <= dst_addr_i; + burst1_req.num_bytes <= num_bytes_i; + burst1_req.cache_src <= src_cache_i; + burst1_req.cache_dst <= dst_cache_i; + burst1_req.burst_src <= src_burst_i; + burst1_req.burst_dst <= dst_burst_i; + burst1_req.decouple_rw <= decouple_rw_i; + burst1_req.deburst <= deburst_i; + burst1_req.serialize <= serialize_i; + burst1_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst1_req_valid <= 1'b0; + burst1_req <= '0; + endtask + + task oned_dut_launch_0 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic serialize_i, + input logic deburst_i + ); + burst0_req_valid <= 1'b0; + burst0_req <= '0; + @(posedge clk); + while (burst0_req_ready !== 1) @(posedge clk); + // write data + burst0_req.id <= transf_id_i; + burst0_req.src <= src_addr_i; + burst0_req.dst <= dst_addr_i; + burst0_req.num_bytes <= num_bytes_i; + burst0_req.cache_src <= src_cache_i; + burst0_req.cache_dst <= dst_cache_i; + burst0_req.burst_src <= src_burst_i; + burst0_req.burst_dst <= dst_burst_i; + burst0_req.decouple_rw <= decouple_rw_i; + burst0_req.deburst <= deburst_i; + burst0_req.serialize <= serialize_i; + burst0_req_valid <= 1'b1; + // wait and set to 0 + @(posedge clk); + burst0_req_valid <= 1'b0; + burst0_req <= '0; + endtask + + task oned_reset (); + burst0_req_valid <= 1'b0; + burst0_req <= '0; + burst1_req_valid <= 1'b0; + burst1_req <= '0; + burst2_req_valid <= 1'b0; + burst2_req <= '0; + burst3_req_valid <= 1'b0; + burst3_req <= '0; + burst4_req_valid <= 1'b0; + burst4_req <= '0; + burst5_req_valid <= 1'b0; + burst5_req <= '0; + burst6_req_valid <= 1'b0; + burst6_req <= '0; + burst7_req_valid <= 1'b0; + burst7_req <= '0; + burst8_req_valid <= 1'b0; + burst8_req <= '0; + burst9_req_valid <= 1'b0; + burst9_req <= '0; + burst10_req_valid <= 1'b0; + burst10_req <= '0; + burst11_req_valid <= 1'b0; + burst11_req <= '0; + burst12_req_valid <= 1'b0; + burst12_req <= '0; + burst13_req_valid <= 1'b0; + burst13_req <= '0; + burst14_req_valid <= 1'b0; + burst14_req <= '0; + burst15_req_valid <= 1'b0; + burst15_req <= '0; + endtask + + task wait_for_dut_completion (); + repeat(10) @(posedge clk); + while (backend_idle_0 === 0) @(posedge clk); + while (backend_idle_1 === 0) @(posedge clk); + while (backend_idle_2 === 0) @(posedge clk); + while (backend_idle_3 === 0) @(posedge clk); + while (backend_idle_4 === 0) @(posedge clk); + while (backend_idle_5 === 0) @(posedge clk); + while (backend_idle_6 === 0) @(posedge clk); + while (backend_idle_7 === 0) @(posedge clk); + while (backend_idle_8 === 0) @(posedge clk); + while (backend_idle_9 === 0) @(posedge clk); + while (backend_idle_10 === 0) @(posedge clk); + while (backend_idle_11 === 0) @(posedge clk); + while (backend_idle_12 === 0) @(posedge clk); + while (backend_idle_13 === 0) @(posedge clk); + while (backend_idle_14 === 0) @(posedge clk); + while (backend_idle_15 === 0) @(posedge clk); + repeat(50) @(posedge clk); + endtask + + task clear_dut_memory (); + dma_memory.delete(); + dma_memory1.delete(); + endtask + + task reset_dut_lfsr (); + lfsr_dut_q <= 'hc0a232c162b2bab5b960668030f4efce27940bd0de965f0b8d4315f15b79704195e4e0a6b495fc269f65ae17e10e9ca98510fc143327a292b418597f9dd175fc91c3d61be287d5462a23e00fa7ae906ae9eb339ab5225021356138cd46b6e5a73540c5591116b6b5e08d2c0e54eaf0d5143b33b2186b6cf841c076a98c412a63981f0e323dce93481ed1c37e4f1d7553b6c2fba1a3af6c3ad88b15ad58812ba07d1753917ac4e6ab1e8c4f67a47b4b0f48a34f42a52c546e979f4e4968e80a732a0a5e7a51146cf08482f349f94336752b765c0b1d70803d883d5058d127264335213da4163c62f65a4e65501b90fa5f177675c0747cfca328e131bfb3f7bcc5c27680c7bf86491f4ed3d36c25531edfa74b1e32fafe426958ae356eb8ef0fd818eaca4227a667b7c934ebfa282ab6bfc6db89b927c91a41e63a9554dced774f30268d0725a1a565368703b9f81d5c027ba196ef8b803a51c639c7ead834e1d6bc537d33800fe5eb12f1ed67758f1dfe85ffdbae56e8ef27f2ecedcee75b8dbb5f5f1a629ba3b755; + endtask + + //-------------------------------------- + // Osmium Model + //-------------------------------------- + // Memory + block_t osmium_memory [bit [AddrWidth-$clog2($bits(block_t))-1:0]]; + // lfsr + logic [784:0] lfsr_osmium_q,lfsr_osmium_d; + + task oned_osmium_launch ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic [ 1:0] src_burst_i, dst_burst_i, + input logic [ 3:0] src_cache_i, dst_cache_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i + ); + logic [AddrWidth-1:0] read_addr, write_addr; + logic [AddrWidth-1:0] read_word, write_word; + logic [$clog2(AddrWidth):0] read_offset, write_offset; + // perform the transfer + for(int i = 0; i < num_bytes_i; i = i + 1) begin + read_addr = src_addr_i + i; + write_addr = dst_addr_i + i; + read_word = src_burst_i == 2'b00 ? src_addr_i >> $clog2(AddrWidth) : read_addr >> $clog2(AddrWidth); + write_word = dst_burst_i == 2'b00 ? dst_addr_i >> $clog2(AddrWidth) : write_addr >> $clog2(AddrWidth); + read_offset = read_addr [$clog2(AddrWidth)-1:0]; + write_offset = write_addr[$clog2(AddrWidth)-1:0]; + + // do the read + if (!osmium_memory.exists(read_word) === 1) begin + osmium_memory[read_word].data = lfsr_osmium_q[784:273]; + //shift 513x + repeat(513) begin + // next state + for (int i = 1; i < 785; i = i +1) lfsr_osmium_d[i-1] = lfsr_osmium_q[i]; + lfsr_osmium_d[784] = lfsr_osmium_q[0]; + lfsr_osmium_d[692] = lfsr_osmium_q[0] ^ lfsr_osmium_q[693]; + lfsr_osmium_q = lfsr_osmium_d; + end + end + // do the write + osmium_memory[write_word].bytes[write_offset] = osmium_memory[read_word].bytes[read_offset]; + // $display("W: %d - %d R: %d - %d", write_word, write_offset, read_word, read_offset); + end + + endtask + + task clear_osmium_memory (); + osmium_memory.delete(); + endtask + + task reset_osmium_lfsr (); + lfsr_osmium_q = 'hc0a232c162b2bab5b960668030f4efce27940bd0de965f0b8d4315f15b79704195e4e0a6b495fc269f65ae17e10e9ca98510fc143327a292b418597f9dd175fc91c3d61be287d5462a23e00fa7ae906ae9eb339ab5225021356138cd46b6e5a73540c5591116b6b5e08d2c0e54eaf0d5143b33b2186b6cf841c076a98c412a63981f0e323dce93481ed1c37e4f1d7553b6c2fba1a3af6c3ad88b15ad58812ba07d1753917ac4e6ab1e8c4f67a47b4b0f48a34f42a52c546e979f4e4968e80a732a0a5e7a51146cf08482f349f94336752b765c0b1d70803d883d5058d127264335213da4163c62f65a4e65501b90fa5f177675c0747cfca328e131bfb3f7bcc5c27680c7bf86491f4ed3d36c25531edfa74b1e32fafe426958ae356eb8ef0fd818eaca4227a667b7c934ebfa282ab6bfc6db89b927c91a41e63a9554dced774f30268d0725a1a565368703b9f81d5c027ba196ef8b803a51c639c7ead834e1d6bc537d33800fe5eb12f1ed67758f1dfe85ffdbae56e8ef27f2ecedcee75b8dbb5f5f1a629ba3b755; + endtask + + //-------------------------------------- + // Compare Memory content + //-------------------------------------- + task compare_memories (); + + // go through osmium memory and compare contents + foreach(osmium_memory[i]) begin + if (osmium_memory[i] !== dma_memory[i]) $fatal("Memory mismatch @ %x\nexpect: %x\ngot :%x\n", i << $clog2(AddrWidth), osmium_memory[i], dma_memory[i]); + end + // go through dma memory and compare contents + foreach(dma_memory[i]) begin + if (osmium_memory[i] !== dma_memory[i]) $fatal("Memory mismatch @ %x\nexpect: %x\ngot :%x\n", i << $clog2(AddrWidth), osmium_memory[i], dma_memory[i]); + end + + // it worked :P + $display(" - :D"); + + endtask + + //-------------------------------------- + // Master tasks + //-------------------------------------- + + task clear_memory (); + clear_dut_memory(); + clear_osmium_memory(); + endtask + + task reset_lfsr (); + reset_dut_lfsr(); + reset_osmium_lfsr(); + endtask + + task oned_launch_15 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma15_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_15(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_14 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma14_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_14(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_13 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma13_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_13(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_12 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma12_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_12(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_11 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma11_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_11(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_10 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma10_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_10(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_9 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma9_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_9(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_8 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma8_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_8(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_7 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma7_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_7(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_6 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma6_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_6(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_5 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma5_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_5(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_4 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma4_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_4(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_3 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma3_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_3(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_2 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma2_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_2(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_1 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma1_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_1(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task oned_launch_0 ( + input logic [ IdWidth-1:0] transf_id_i, + input logic [ AddrWidth-1:0] src_addr_i, dst_addr_i, num_bytes_i, + input logic decouple_rw_i, + input logic deburst_i, + input logic serialize_i, + input logic wait_for_completion_i + ); + // keep a log file + int my_file; + my_file = $fopen("dma0_transfers.txt", "a+"); + $write("ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fwrite (my_file, "ID: %d SRC: 0x%x DST: 0x%x LEN: %d DECOUPLE: %1b DEBURST: %1b SERIALIZE: %1b\n", transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, decouple_rw_i, deburst_i, serialize_i ); + $fclose(my_file); + + // cache and burst is ignored + oned_dut_launch_0(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + // wait if requested + if (wait_for_completion_i) + wait_for_dut_completion(); + // run model + //oned_osmium_launch(transf_id_i, src_addr_i, dst_addr_i, num_bytes_i, 2'b01, 2'b01, 4'h0, 4'h0, decouple_rw_i, deburst_i, serialize_i); + endtask + + task reset (); + int my_file; + oned_reset(); + wait_for_reset(); + // clear trace file + my_file = $fopen("dma_transfers.txt", "w"); + $fwrite(my_file, "Transfers launched:\n"); + $fclose(my_file); + endtask + + task oned_random_launch( + input logic [31:0] max_len, + // input logic [31:0] src_add, + // input logic [31:0] dst_add, + input logic [15:0] master_id, + // input logic [15:0] size, + input logic wait_for_completion + ); + + logic [ IdWidth-1:0] transf_id_0; + logic [ AddrWidth-1:0] src_addr_0, dst_addr_0, num_bytes_0; + logic [ IdWidth-1:0] transf_id_1; + logic [ AddrWidth-1:0] src_addr_1, dst_addr_1, num_bytes_1; + logic [ IdWidth-1:0] transf_id_2; + logic [ AddrWidth-1:0] src_addr_2, dst_addr_2, num_bytes_2; + logic [ IdWidth-1:0] transf_id_3; + logic [ AddrWidth-1:0] src_addr_3, dst_addr_3, num_bytes_3; + logic [ IdWidth-1:0] transf_id_4; + logic [ AddrWidth-1:0] src_addr_4, dst_addr_4, num_bytes_4; + logic [ IdWidth-1:0] transf_id_5; + logic [ AddrWidth-1:0] src_addr_5, dst_addr_5, num_bytes_5; + logic [ IdWidth-1:0] transf_id_6; + logic [ AddrWidth-1:0] src_addr_6, dst_addr_6, num_bytes_6; + logic [ IdWidth-1:0] transf_id_7; + logic [ AddrWidth-1:0] src_addr_7, dst_addr_7, num_bytes_7; + logic [ IdWidth-1:0] transf_id_8; + logic [ AddrWidth-1:0] src_addr_8, dst_addr_8, num_bytes_8; + logic [ IdWidth-1:0] transf_id_9; + logic [ AddrWidth-1:0] src_addr_9, dst_addr_9, num_bytes_9; + logic [ IdWidth-1:0] transf_id_10; + logic [ AddrWidth-1:0] src_addr_10, dst_addr_10, num_bytes_10; + logic [ IdWidth-1:0] transf_id_11; + logic [ AddrWidth-1:0] src_addr_11, dst_addr_11, num_bytes_11; + logic [ IdWidth-1:0] transf_id_12; + logic [ AddrWidth-1:0] src_addr_12, dst_addr_12, num_bytes_12; + logic [ IdWidth-1:0] transf_id_13; + logic [ AddrWidth-1:0] src_addr_13, dst_addr_13, num_bytes_13; + logic [ IdWidth-1:0] transf_id_14; + logic [ AddrWidth-1:0] src_addr_14, dst_addr_14, num_bytes_14; + logic [ IdWidth-1:0] transf_id_15; + logic [ AddrWidth-1:0] src_addr_15, dst_addr_15, num_bytes_15; + logic decouple_rw; + logic deburst; + logic serialize; + + decouple_rw = 0;//$urandom(); + deburst = 0;//$urandom(); + serialize = 0;//$urandom(); + + if (master_id == 0) begin + transf_id_0 = 0;//$urandom(); + // transf_id = transaction_id; + src_addr_0[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_0[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_0[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_0[(AddrWidth/2)-1: 0] = $urandom(); + //num_bytes_0 = 0; + num_bytes_0 = $urandom_range(max_len, 1); + + oned_launch_0(transf_id_0, src_addr_0, dst_addr_0, num_bytes_0, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 1) begin + transf_id_1 = 1;//$urandom(); + // transf_id = transaction_id; + src_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_1[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_1[(AddrWidth/2)-1: 0] = $urandom(); + //num_bytes_1 = 0; + num_bytes_1 = $urandom_range(max_len, 1); + + oned_launch_1(transf_id_1, src_addr_1, dst_addr_1, num_bytes_1, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 2) begin + transf_id_2 = 2;//$urandom(); + //transf_id = transaction_id; + src_addr_2[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_2[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_2[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_2[(AddrWidth/2)-1: 0] = $urandom(); + //num_bytes_2 = 0; + num_bytes_2 = $urandom_range(max_len, 1); + + oned_launch_2(transf_id_2, src_addr_2, dst_addr_2, num_bytes_2, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 3) begin + transf_id_3 = 3;//$urandom(); + // transf_id = transaction_id; + src_addr_3[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_3[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_3[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_3[(AddrWidth/2)-1: 0] = $urandom(); + //num_bytes_3 = 0; + num_bytes_3 = $urandom_range(max_len, 1); + + oned_launch_3(transf_id_3, src_addr_3, dst_addr_3, num_bytes_3, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 4) begin + transf_id_4 = 4;//$urandom(); + // transf_id = transaction_id; + src_addr_4[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_4[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_4[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_4[(AddrWidth/2)-1: 0] = $urandom(); + //num_bytes_4 = 0; + num_bytes_4 = $urandom_range(max_len, 1); + + oned_launch_4(transf_id_4, src_addr_4, dst_addr_4, num_bytes_4, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 5) begin + transf_id_5 = 5;//$urandom(); + // transf_id = transaction_id; + src_addr_5[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_5[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_5[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_5[(AddrWidth/2)-1: 0] = $urandom(); + //num_bytes_5 = 0; + num_bytes_5 = $urandom_range(max_len, 1); + + oned_launch_5(transf_id_5, src_addr_5, dst_addr_5, num_bytes_5, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 6) begin + transf_id_6 = 6;//$urandom(); + // transf_id = transaction_id; + src_addr_6[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_6[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_6[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_6[(AddrWidth/2)-1: 0] = $urandom(); + //num_bytes_6 = 0; + num_bytes_6 = $urandom_range(max_len, 1); + + oned_launch_6(transf_id_6, src_addr_6, dst_addr_6, num_bytes_6, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 7) begin + transf_id_7 = 7;//$urandom(); + // transf_id = transaction_id; + //src_addr_7[AddrWidth-1:AddrWidth-2] = 1'b1; + src_addr_7[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_7[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_7[AddrWidth-1:AddrWidth-2] = 1'b1; + dst_addr_7[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_7[(AddrWidth/2)-1: 0] = $urandom(); + //num_bytes_7 = 0; + num_bytes_7 = $urandom_range(max_len, 1); + + oned_launch_7(transf_id_7, src_addr_7, dst_addr_7, num_bytes_7, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 8) begin + transf_id_8 = 8;//$urandom(); + // transf_id = transaction_id; + src_addr_8[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_8[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_8[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_8[(AddrWidth/2)-1: 0] = $urandom(); + //num_bytes_8 = 0; + num_bytes_8 = $urandom_range(max_len, 1); + + oned_launch_8(transf_id_8, src_addr_8, dst_addr_8, num_bytes_8, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 9) begin + transf_id_9 = 9;//$urandom(); + // transf_id = transaction_id; + src_addr_9[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_9[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_9[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_9[(AddrWidth/2)-1: 0] = $urandom(); + //num_bytes_9 = 0; + num_bytes_9 = $urandom_range(max_len, 1); + + oned_launch_9(transf_id_9, src_addr_9, dst_addr_9, num_bytes_9, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 10) begin + transf_id_10 = 10;//$urandom(); + // transf_id = transaction_id; + src_addr_10[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_10[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_10[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_10[(AddrWidth/2)-1: 0] = $urandom(); + //num_bytes_10 = 0; + num_bytes_10 = $urandom_range(max_len, 1); + + oned_launch_10(transf_id_10, src_addr_10, dst_addr_10, num_bytes_10, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 11) begin + transf_id_11 = 11;//$urandom(); + // transf_id = transaction_id; + //src_addr_11[AddrWidth-1:AddrWidth-2] = 1'b1; + src_addr_11[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_11[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_11[AddrWidth-1:AddrWidth-2] = 1'b1; + dst_addr_11[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_11[(AddrWidth/2)-1: 0] = $urandom(); + //num_bytes_11 = 0; + num_bytes_11 = $urandom_range(max_len, 1); + + oned_launch_11(transf_id_11, src_addr_11, dst_addr_11, num_bytes_11, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 12) begin + transf_id_12 = 12;//$urandom(); + // transf_id = transaction_id; + src_addr_12[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_12[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_12[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_12[(AddrWidth/2)-1: 0] = $urandom(); + //num_bytes_12 = 0; + num_bytes_12 = $urandom_range(max_len, 1); + + oned_launch_12(transf_id_12, src_addr_12, dst_addr_12, num_bytes_12, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 13) begin + transf_id_13 = 13;//$urandom(); + // transf_id = transaction_id; + src_addr_13[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_13[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_13[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_13[(AddrWidth/2)-1: 0] = $urandom(); + //num_bytes_13 = 0; + num_bytes_13 = $urandom_range(max_len, 1); + + oned_launch_13(transf_id_13, src_addr_13, dst_addr_13, num_bytes_13, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 14) begin + transf_id_14 = 14;//$urandom(); + // transf_id = transaction_id; + src_addr_14[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_14[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_14[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_14[(AddrWidth/2)-1: 0] = $urandom(); + //num_bytes_14 = 0; + num_bytes_14 = $urandom_range(max_len, 1); + + oned_launch_14(transf_id_14, src_addr_14, dst_addr_14, num_bytes_14, decouple_rw, deburst, serialize, wait_for_completion); + + end else if (master_id == 15) begin + transf_id_15 = 15;//$urandom(); + // transf_id = transaction_id; + //src_addr_15[AddrWidth-1:AddrWidth-2] = 1'b1; + src_addr_15[AddrWidth-1:(AddrWidth/2)] = $urandom(); + src_addr_15[(AddrWidth/2)-1: 0] = $urandom(); + dst_addr_15[AddrWidth-1:AddrWidth-2] = 1'b1; + dst_addr_15[AddrWidth-1:(AddrWidth/2)] = $urandom(); + dst_addr_15[(AddrWidth/2)-1: 0] = $urandom(); + //num_bytes_15 = 0; + num_bytes_15 = $urandom_range(max_len, 1); + + oned_launch_15(transf_id_15, src_addr_15, dst_addr_15, num_bytes_15, decouple_rw, deburst, serialize, wait_for_completion); + + end + + // transaction_id = transaction_id + 1; + + + endtask + +endmodule : fixture_axi_dma_backend diff --git a/test/tb_axi_dma_backend.sv b/test/tb_axi_dma_backend.sv new file mode 100644 index 000000000..e4ecefb2c --- /dev/null +++ b/test/tb_axi_dma_backend.sv @@ -0,0 +1,104 @@ +// Copyright (c) 2019 ETH Zurich, University of Bologna +// All rights reserved. +// +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// +// Thomas Benz + +// top level of the simulation for the AXI DMA backend + +`timescale 1ns/1ns +module tb_axi_dma_backend; + + fixture_axi_dma_backend fix (); + string line; + int fd,code; + int dma_id, src_add, dst_add, size; + + initial begin + + fix.reset(); + fix.clear_memory(); + fix.reset_lfsr(); + + fd = $fopen("/home/jvikram/crosspoint/axi/test/traces_dp_16cl_tb.txt","r"); + while($fgets(line,fd)) begin + if(line.match("(\/\/.*)?$")) + line = line.prematch(); + if (!line.match("[0-f]")) continue; + code = $sscanf(line,"%d %h %h %h", dma_id, src_add, dst_add, size); + //$displayh("%h %h %h %h\n", dma_id, src_add, dst_add, size); + fix.oned_random_launch(4, src_add, dst_add, dma_id, size, 0); + $display(); + end + fix.oned_random_launch(4, src_add, dst_add, dma_id, size, 1); + + $display("\nDone with test 1 :D"); + + $fclose(fd); + + // // ultra short transfers + // for (int i = 0; i < 20000; i = i + 1) begin + // fix.oned_random_launch(4, 0); + // $display(); + // end + // fix.oned_random_launch(4, 1); + // //fix.compare_memories(); + // $display("\nDone with test 1 :D"); + + // // medium short transfers + // for (int i = 0; i < 20000; i = i + 1) begin + // fix.oned_random_launch(10, 0); + // $display(); + // end + // fix.oned_random_launch(10, 1); + // //fix.compare_memories(); + // $display("\nDone with test 2 :D"); + + // // // short transfers + // for (int i = 0; i < 25000; i = i + 1) begin + // fix.oned_random_launch(100, 0); + // $display(); + // end + // fix.oned_random_launch(100, 1); + // //fix.compare_memories(); + // $display("\nDone with test 3 :D"); + + // // // medium transfers + // for (int i = 0; i < 1000; i = i + 1) begin + // fix.oned_random_launch(1000, 0); + // $display(); + // end + // fix.oned_random_launch(1000, 1); + // //fix.compare_memories(); + // $display("\nDone with test 4 :D"); + + // // long transfers + // for (int i = 0; i < 250; i = i + 1) begin + // fix.oned_random_launch(10000, 0); + // $display(); + // end + // fix.oned_random_launch(10000, 1); + // //fix.compare_memories(); + // $display("\nDone with test 5 :D"); + + // // ultra long transfers + // for (int i = 0; i < 100; i = i + 1) begin + // fix.oned_random_launch(65000, 0); + // $display(); + // end + // fix.oned_random_launch(65000, 1); + // //fix.compare_memories(); + // $display("\nDone with test 6 :D"); + + $display("\nDone :D (in %18.9f seconds", $time() / 1000000000.0); + $display("SUCCESS"); + $stop(); + end + +endmodule + diff --git a/test/tb_axi_dma_backend_2x2_2M2S.sv b/test/tb_axi_dma_backend_2x2_2M2S.sv new file mode 100644 index 000000000..066008ca4 --- /dev/null +++ b/test/tb_axi_dma_backend_2x2_2M2S.sv @@ -0,0 +1,104 @@ +// Copyright (c) 2019 ETH Zurich, University of Bologna +// All rights reserved. +// +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// +// Thomas Benz + +// top level of the simulation for the AXI DMA backend + +`timescale 1ns/1ns +module tb_axi_dma_backend; + + fixture_axi_dma_backend fix (); + string line; + int fd,code; + int dma_id, src_add, dst_add, size; + + initial begin + + fix.reset(); + fix.clear_memory(); + fix.reset_lfsr(); + + fd = $fopen("/home/jvikram/crosspoint/axi/test/traces_2cl_tb.txt","r"); + while($fgets(line,fd)) begin + if(line.match("(\/\/.*)?$")) + line = line.prematch(); + if (!line.match("[0-f]")) continue; + code = $sscanf(line,"%h %h %h %h", dma_id, src_add, dst_add, size); + //$displayh("%h %h %h %h\n", dma_id, src_add, dst_add, size); + fix.oned_random_launch(4, src_add, dst_add, dma_id, size, 0); + $display(); + end + fix.oned_random_launch(4, src_add, dst_add, dma_id, size, 1); + + $display("\nDone with test 1 :D"); + + $fclose(fd); + + // // ultra short transfers + // for (int i = 0; i < 20000; i = i + 1) begin + // fix.oned_random_launch(4, 0); + // $display(); + // end + // fix.oned_random_launch(4, 1); + // //fix.compare_memories(); + // $display("\nDone with test 1 :D"); + + // // medium short transfers + // for (int i = 0; i < 20000; i = i + 1) begin + // fix.oned_random_launch(10, 0); + // $display(); + // end + // fix.oned_random_launch(10, 1); + // //fix.compare_memories(); + // $display("\nDone with test 2 :D"); + + // // // short transfers + // for (int i = 0; i < 25000; i = i + 1) begin + // fix.oned_random_launch(100, 0); + // $display(); + // end + // fix.oned_random_launch(100, 1); + // //fix.compare_memories(); + // $display("\nDone with test 3 :D"); + + // // // medium transfers + // for (int i = 0; i < 1000; i = i + 1) begin + // fix.oned_random_launch(1000, 0); + // $display(); + // end + // fix.oned_random_launch(1000, 1); + // //fix.compare_memories(); + // $display("\nDone with test 4 :D"); + + // // long transfers + // for (int i = 0; i < 250; i = i + 1) begin + // fix.oned_random_launch(10000, 0); + // $display(); + // end + // fix.oned_random_launch(10000, 1); + // //fix.compare_memories(); + // $display("\nDone with test 5 :D"); + + // // ultra long transfers + // for (int i = 0; i < 100; i = i + 1) begin + // fix.oned_random_launch(65000, 0); + // $display(); + // end + // fix.oned_random_launch(65000, 1); + // //fix.compare_memories(); + // $display("\nDone with test 6 :D"); + + $display("\nDone :D (in %18.9f seconds", $time() / 1000000000.0); + $display("SUCCESS"); + $stop(); + end + +endmodule + diff --git a/test/tb_axi_dma_backend_2x2_4M4S.sv b/test/tb_axi_dma_backend_2x2_4M4S.sv new file mode 100644 index 000000000..ab1d84c49 --- /dev/null +++ b/test/tb_axi_dma_backend_2x2_4M4S.sv @@ -0,0 +1,104 @@ +// Copyright (c) 2019 ETH Zurich, University of Bologna +// All rights reserved. +// +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// +// Thomas Benz + +// top level of the simulation for the AXI DMA backend + +`timescale 1ns/1ns +module tb_axi_dma_backend; + + fixture_axi_dma_backend fix (); + string line; + int fd,code; + int dma_id, src_add, dst_add, size; + + initial begin + + fix.reset(); + fix.clear_memory(); + fix.reset_lfsr(); + + fd = $fopen("/home/jvikram/crosspoint/axi/test/traces_4cl_tb.txt","r"); + while($fgets(line,fd)) begin + if(line.match("(\/\/.*)?$")) + line = line.prematch(); + if (!line.match("[0-f]")) continue; + code = $sscanf(line,"%h %h %h %h", dma_id, src_add, dst_add, size); + //$displayh("%h %h %h %h\n", dma_id, src_add, dst_add, size); + fix.oned_random_launch(4, src_add, dst_add, dma_id, size, 0); + $display(); + end + fix.oned_random_launch(4, src_add, dst_add, dma_id, size, 1); + + $display("\nDone with test 1 :D"); + + $fclose(fd); + + // // ultra short transfers + // for (int i = 0; i < 20000; i = i + 1) begin + // fix.oned_random_launch(4, 0); + // $display(); + // end + // fix.oned_random_launch(4, 1); + // //fix.compare_memories(); + // $display("\nDone with test 1 :D"); + + // // medium short transfers + // for (int i = 0; i < 20000; i = i + 1) begin + // fix.oned_random_launch(10, 0); + // $display(); + // end + // fix.oned_random_launch(10, 1); + // //fix.compare_memories(); + // $display("\nDone with test 2 :D"); + + // // // short transfers + // for (int i = 0; i < 25000; i = i + 1) begin + // fix.oned_random_launch(100, 0); + // $display(); + // end + // fix.oned_random_launch(100, 1); + // //fix.compare_memories(); + // $display("\nDone with test 3 :D"); + + // // // medium transfers + // for (int i = 0; i < 1000; i = i + 1) begin + // fix.oned_random_launch(1000, 0); + // $display(); + // end + // fix.oned_random_launch(1000, 1); + // //fix.compare_memories(); + // $display("\nDone with test 4 :D"); + + // // long transfers + // for (int i = 0; i < 250; i = i + 1) begin + // fix.oned_random_launch(10000, 0); + // $display(); + // end + // fix.oned_random_launch(10000, 1); + // //fix.compare_memories(); + // $display("\nDone with test 5 :D"); + + // // ultra long transfers + // for (int i = 0; i < 100; i = i + 1) begin + // fix.oned_random_launch(65000, 0); + // $display(); + // end + // fix.oned_random_launch(65000, 1); + // //fix.compare_memories(); + // $display("\nDone with test 6 :D"); + + $display("\nDone :D (in %18.9f seconds", $time() / 1000000000.0); + $display("SUCCESS"); + $stop(); + end + +endmodule + diff --git a/test/tb_axi_dma_backend_bkp.sv b/test/tb_axi_dma_backend_bkp.sv new file mode 100644 index 000000000..399a73262 --- /dev/null +++ b/test/tb_axi_dma_backend_bkp.sv @@ -0,0 +1,86 @@ +// Copyright (c) 2019 ETH Zurich, University of Bologna +// All rights reserved. +// +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// +// Thomas Benz + +// top level of the simulation for the AXI DMA backend + +`timescale 1ns/1ns +module tb_axi_dma_backend; + + fixture_axi_dma_backend fix (); + + initial begin + + fix.reset(); + fix.clear_memory(); + fix.reset_lfsr(); + + // // ultra short transfers + // for (int i = 0; i < 20000; i = i + 1) begin + // fix.oned_random_launch(4, 0); + // $display(); + // end + // fix.oned_random_launch(4, 1); + // //fix.compare_memories(); + // $display("\nDone with test 1 :D"); + + // // medium short transfers + // for (int i = 0; i < 20000; i = i + 1) begin + // fix.oned_random_launch(10, 0); + // $display(); + // end + // fix.oned_random_launch(10, 1); + // //fix.compare_memories(); + // $display("\nDone with test 2 :D"); + + // // // short transfers + // for (int i = 0; i < 25000; i = i + 1) begin + // fix.oned_random_launch(100, 0); + // $display(); + // end + // fix.oned_random_launch(100, 1); + // //fix.compare_memories(); + // $display("\nDone with test 3 :D"); + + // // // medium transfers + // for (int i = 0; i < 1000; i = i + 1) begin + // fix.oned_random_launch(1000, 0); + // $display(); + // end + // fix.oned_random_launch(1000, 1); + // //fix.compare_memories(); + // $display("\nDone with test 4 :D"); + + // // long transfers + // for (int i = 0; i < 250; i = i + 1) begin + // fix.oned_random_launch(10000, 0); + // $display(); + // end + // fix.oned_random_launch(10000, 1); + // //fix.compare_memories(); + // $display("\nDone with test 5 :D"); + + // ultra long transfers + for (int i = 0; i < 1; i = i + 1) begin + //fix.oned_random_launch(65000, 0); + $display(); + end + fix.oned_random_launch(65000, 1); + //fix.compare_memories(); + $display("\nDone with test 6 :D"); + + //$display("%18.9f", $time()); + $display("\nDone :D (in %18.9f seconds", $time() / 1000000000.0); + $display("SUCCESS"); + $stop(); + end + +endmodule + diff --git a/test/tb_axi_dma_backend_rand_traffic.sv b/test/tb_axi_dma_backend_rand_traffic.sv new file mode 100644 index 000000000..fae13a9a4 --- /dev/null +++ b/test/tb_axi_dma_backend_rand_traffic.sv @@ -0,0 +1,133 @@ +// Copyright (c) 2019 ETH Zurich, University of Bologna +// All rights reserved. +// +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// +// Thomas Benz + +// top level of the simulation for the AXI DMA backend + +`timescale 1ns/1ns +module tb_axi_dma_backend; + + fixture_axi_dma_backend fix (); + string line; + int fd,code; + int dma_id, src_add, dst_add, size; + + initial begin + + fix.reset(); + fix.clear_memory(); + fix.reset_lfsr(); + + // fd = $fopen("/home/jvikram/crosspoint/axi/test/traces_16cl_tb.txt","r"); + // while($fgets(line,fd)) begin + // if(line.match("(\/\/.*)?$")) + // line = line.prematch(); + // if (!line.match("[0-f]")) continue; + // code = $sscanf(line,"%d %h %h %h", dma_id, src_add, dst_add, size); + // //$displayh("%h %h %h %h\n", dma_id, src_add, dst_add, size); + // fix.oned_random_launch(4, src_add, dst_add, dma_id, size, 0); + // $display(); + // end + // fix.oned_random_launch(4, src_add, dst_add, dma_id, size, 1); + + // $display("\nDone with test 1 :D"); + + // $fclose(fd); + + // // ultra short transfers + // for (int i = 0; i < 100000; i = i + 1) begin + // dma_id = $urandom_range(15,0); + // fix.oned_random_launch(4, dma_id, 0); + // //$display(); + // end + // fix.oned_random_launch(4, dma_id, 1); + // //fix.compare_memories(); + // $display("\nDone with test 1 :D"); + + // $display("\nDone :D (in %18.9f seconds", $time() / 1000000000.0); + + // // medium short transfers + // for (int i = 0; i < 20000; i = i + 1) begin + // dma_id = $urandom_range(15,0); + // fix.oned_random_launch(10, dma_id, 0); + // //$display(); + // end + // fix.oned_random_launch(10, dma_id, 1); + // //fix.compare_memories(); + // $display("\nDone with test 2 :D"); + + // $display("\nDone :D (in %18.9f seconds", $time() / 1000000000.0); + + // // short transfers + // for (int i = 0; i < 10; i = i + 1) begin + // dma_id = $urandom_range(15,0); + // fix.oned_random_launch(100, dma_id, 0); + // //$display(); + // end + // fix.oned_random_launch(100, dma_id, 1); + // //fix.compare_memories(); + // $display("\nDone with test 3 :D"); + + // $display("\nDone :D (in %18.9f seconds", $time() / 1000000000.0); + + // // medium transfers + // for (int i = 0; i < 10; i = i + 1) begin + // dma_id = $urandom_range(15,0); + // fix.oned_random_launch(1000, dma_id, 0); + // //$display(); + // end + // fix.oned_random_launch(1000, dma_id, 1); + // //fix.compare_memories(); + // $display("\nDone with test 4 :D"); + + // $display("\nDone :D (in %18.9f seconds", $time() / 1000000000.0); + + // // long transfers + // for (int i = 0; i < 10; i = i + 1) begin + // dma_id = $urandom_range(15,0); + // fix.oned_random_launch(10000, dma_id, 0); + // //$display(); + // end + // fix.oned_random_launch(10000, dma_id, 1); + // //fix.compare_memories(); + // $display("\nDone with test 5 :D"); + + // $display("\nDone :D (in %18.9f seconds", $time() / 1000000000.0); + + // // ultra long transfers + // for (int i = 0; i < 1; i = i + 1) begin + // dma_id = $urandom_range(15,0); + // fix.oned_random_launch(64000, dma_id, 0); + // //$display(); + // end + // fix.oned_random_launch(64000, dma_id, 1); + // //fix.compare_memories(); + // $display("\nDone with test 6 :D"); + + // $display("\nDone :D (in %18.9f seconds", $time() / 1000000000.0); + + // ultra ultra long transfers + for (int i = 0; i < 1; i = i + 1) begin + dma_id = $urandom_range(15,0); + fix.oned_random_launch(128000, dma_id, 0); + //$display(); + end + fix.oned_random_launch(128000, dma_id, 1); + //fix.compare_memories(); + $display("\nDone with test 6 :D"); + + $display("\nDone :D (in %18.9f seconds", $time() / 1000000000.0); + + $display("SUCCESS"); + $stop(); + end + +endmodule + diff --git a/test/tb_axi_xp.sv b/test/tb_axi_xp.sv new file mode 100644 index 000000000..d898914c5 --- /dev/null +++ b/test/tb_axi_xp.sv @@ -0,0 +1,470 @@ +// Copyright (c) 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Authors: +// - Florian Zaruba +// - Andreas Kurth +// - Vikram Jain + +// Directed Random Verification Testbench for `axi_xp`: The crosspoint is instantiated with +// a configurable number of random axi master and slave modules. Each random master executes a +// fixed number of writes and reads over the whole addess map. All masters simultaneously issue +// transactions through the crosspoint, thereby saturating it. A monitor, which snoops the +// transactions of each master and slave port and models the crosspoint with a network of FIFOs, +// checks whether each transaction follows the expected route. + +`include "axi/typedef.svh" +`include "axi/assign.svh" + +module tb_axi_xp #( + // Testbench parameters + parameter bit TbEnAtop = 1'b1, // enable atomic operations (ATOPs) + parameter bit TbEnExcl = 1'b0, // enable exclusive accesses + parameter bit TbUniqueIds = 1'b0, // restrict to only unique IDs + parameter int unsigned TbNumMst = 32'd4, // how many AXI masters there are + parameter int unsigned TbNumSlv = 32'd4 // how many AXI slaves there are +); + // Random master no Transactions + localparam int unsigned NoWrites = 80; // How many writes per master + localparam int unsigned NoReads = 80; // How many reads per master + // timing parameters + localparam time CyclTime = 10ns; + localparam time ApplTime = 2ns; + localparam time TestTime = 8ns; + + // DUT parameters + localparam bit ATOPs = TbEnAtop; + localparam int unsigned NoSlvPorts = TbNumSlv; + localparam int unsigned NoMstPorts = TbNumMst; + localparam bit [NoSlvPorts-1:0][NoMstPorts-1:0] Connectivity = '1; + localparam int unsigned AxiSlvPortMaxUniqIds = 32'd16; + localparam int unsigned AxiSlvPortMaxTxnsPerId = 32'd128; + localparam int unsigned AxiSlvPortMaxTxns = 32'd31; + localparam int unsigned AxiMstPortMaxUniqIds = 32'd2; + localparam int unsigned AxiMstPortMaxTxnsPerId = 32'd7; + localparam int unsigned NoAddrRules = 32'd8; + + // axi configuration + localparam int unsigned AxiIdWidthMasters = 4; + localparam int unsigned AxiIdUsed = 3; // Has to be <= AxiIdWidthMasters + localparam int unsigned AxiIdWidthSlaves = AxiIdWidthMasters + $clog2(TbNumMst); + localparam int unsigned AxiAddrWidth = 32; // Axi Address Width + localparam int unsigned AxiDataWidth = 64; // Axi Data Width + localparam int unsigned AxiStrbWidth = AxiDataWidth / 8; + localparam int unsigned AxiUserWidth = 5; + localparam int unsigned AxiIdWidth = AxiIdWidthMasters; + // in the bench can change this variables which are set here freely + localparam axi_pkg::xbar_cfg_t xbar_cfg = '{ + NoSlvPorts: TbNumSlv, + NoMstPorts: TbNumMst, + MaxMstTrans: AxiSlvPortMaxTxns, + MaxSlvTrans: AxiSlvPortMaxTxnsPerId, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_AX, + AxiIdWidthSlvPorts: AxiIdWidthMasters, + AxiIdUsedSlvPorts: AxiIdUsed, + UniqueIds: TbUniqueIds, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: 8 + }; + typedef logic [AxiIdWidthMasters-1:0] id_mst_t; + typedef logic [AxiIdWidthSlaves-1:0] id_slv_t; + typedef logic [AxiAddrWidth-1:0] addr_t; + typedef axi_pkg::xbar_rule_32_t rule_t; // Has to be the same width as axi addr + typedef logic [AxiDataWidth-1:0] data_t; + typedef logic [AxiStrbWidth-1:0] strb_t; + typedef logic [AxiUserWidth-1:0] user_t; + + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_mst_t, addr_t, id_mst_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_slv_t, addr_t, id_slv_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_mst_t, id_mst_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_slv_t, id_slv_t, user_t) + + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_mst_t, addr_t, id_mst_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_slv_t, addr_t, id_slv_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_mst_t, data_t, id_mst_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_slv_t, data_t, id_slv_t, user_t) + + `AXI_TYPEDEF_REQ_T(mst_req_t, aw_chan_mst_t, w_chan_t, ar_chan_mst_t) + `AXI_TYPEDEF_RESP_T(mst_resp_t, b_chan_mst_t, r_chan_mst_t) + `AXI_TYPEDEF_REQ_T(slv_req_t, aw_chan_slv_t, w_chan_t, ar_chan_slv_t) + `AXI_TYPEDEF_RESP_T(slv_resp_t, b_chan_slv_t, r_chan_slv_t) + + localparam rule_t [xbar_cfg.NoAddrRules-1:0] AddrMap = '{ + '{idx: 32'd7 % TbNumSlv, start_addr: 32'h0001_0000, end_addr: 32'h0001_1000}, + '{idx: 32'd6 % TbNumSlv, start_addr: 32'h0000_9000, end_addr: 32'h0001_0000}, + '{idx: 32'd5 % TbNumSlv, start_addr: 32'h0000_8000, end_addr: 32'h0000_9000}, + '{idx: 32'd4 % TbNumSlv, start_addr: 32'h0000_7000, end_addr: 32'h0000_8000}, + '{idx: 32'd3 % TbNumSlv, start_addr: 32'h0000_6300, end_addr: 32'h0000_7000}, + '{idx: 32'd2 % TbNumSlv, start_addr: 32'h0000_4000, end_addr: 32'h0000_6300}, + '{idx: 32'd1 % TbNumSlv, start_addr: 32'h0000_3000, end_addr: 32'h0000_4000}, + '{idx: 32'd0 % TbNumSlv, start_addr: 32'h0000_0000, end_addr: 32'h0000_3000} + }; + + typedef axi_test::axi_rand_master #( + // AXI interface parameters + .AW ( AxiAddrWidth ), + .DW ( AxiDataWidth ), + .IW ( AxiIdWidthMasters ), + .UW ( AxiUserWidth ), + // Stimuli application and test time + .TA ( ApplTime ), + .TT ( TestTime ), + // Maximum number of read and write transactions in flight + .MAX_READ_TXNS ( 20 ), + .MAX_WRITE_TXNS ( 20 ), + .AXI_EXCLS ( TbEnExcl ), + .AXI_ATOPS ( TbEnAtop ), + .UNIQUE_IDS ( TbUniqueIds ) + ) axi_rand_master_t; + typedef axi_test::axi_rand_slave #( + // AXI interface parameters + .AW ( AxiAddrWidth ), + .DW ( AxiDataWidth ), + .IW ( AxiIdWidthSlaves ), + .UW ( AxiUserWidth ), + // Stimuli application and test time + .TA ( ApplTime ), + .TT ( TestTime ) + ) axi_rand_slave_t; + + // ------------- + // DUT signals + // ------------- + logic clk; + // DUT signals + logic rst_n; + logic [TbNumMst-1:0] end_of_sim; + + // master structs + mst_req_t [TbNumMst-1:0] masters_req; + mst_resp_t [TbNumMst-1:0] masters_resp; + + // slave structs + slv_req_t [TbNumSlv-1:0] slaves_req; + slv_resp_t [TbNumSlv-1:0] slaves_resp; + + // ------------------------------- + // AXI Interfaces + // ------------------------------- + AXI_BUS #( + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_ID_WIDTH ( AxiIdWidthMasters ), + .AXI_USER_WIDTH ( AxiUserWidth ) + ) master [TbNumMst-1:0] (); + AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_ID_WIDTH ( AxiIdWidthMasters ), + .AXI_USER_WIDTH ( AxiUserWidth ) + ) master_dv [TbNumMst-1:0] (clk); + AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_ID_WIDTH ( AxiIdWidthMasters ), + .AXI_USER_WIDTH ( AxiUserWidth ) + ) master_monitor_dv [TbNumMst-1:0] (clk); + for (genvar i = 0; i < TbNumMst; i++) begin : gen_conn_dv_masters + `AXI_ASSIGN (master[i], master_dv[i]) + `AXI_ASSIGN_TO_REQ(masters_req[i], master[i]) + `AXI_ASSIGN_TO_RESP(masters_resp[i], master[i]) + end + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_ID_WIDTH ( AxiIdWidthSlaves ), + .AXI_USER_WIDTH ( AxiUserWidth ) + ) slave [TbNumSlv-1:0] (); + AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_ID_WIDTH ( AxiIdWidthSlaves ), + .AXI_USER_WIDTH ( AxiUserWidth ) + ) slave_dv [TbNumSlv-1:0](clk); + AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_ID_WIDTH ( AxiIdWidthSlaves ), + .AXI_USER_WIDTH ( AxiUserWidth ) + ) slave_monitor_dv [TbNumSlv-1:0](clk); + for (genvar i = 0; i < TbNumSlv; i++) begin : gen_conn_dv_slaves + `AXI_ASSIGN(slave_dv[i], slave[i]) + `AXI_ASSIGN_TO_REQ(slaves_req[i], slave[i]) + `AXI_ASSIGN_TO_RESP(slaves_resp[i], slave[i]) + end + // ------------------------------- + // AXI Rand Masters and Slaves + // ------------------------------- + // Masters control simulation run time + axi_rand_master_t axi_rand_master [TbNumMst]; + for (genvar i = 0; i < TbNumMst; i++) begin : gen_rand_master + initial begin + axi_rand_master[i] = new( master_dv[i] ); + end_of_sim[i] <= 1'b0; + axi_rand_master[i].add_memory_region(AddrMap[0].start_addr, + AddrMap[xbar_cfg.NoAddrRules-1].end_addr, + axi_pkg::DEVICE_NONBUFFERABLE); + axi_rand_master[i].reset(); + @(posedge rst_n); + axi_rand_master[i].run(NoReads, NoWrites); + end_of_sim[i] <= 1'b1; + end + end + + axi_rand_slave_t axi_rand_slave [TbNumSlv]; + for (genvar i = 0; i < TbNumSlv; i++) begin : gen_rand_slave + initial begin + axi_rand_slave[i] = new( slave_dv[i] ); + axi_rand_slave[i].reset(); + @(posedge rst_n); + axi_rand_slave[i].run(); + end + end + + initial begin : proc_monitor + static tb_axi_xp_pkg::axi_xp_monitor #( + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidthMasters ( AxiIdWidthMasters ), + .AxiIdWidthSlaves ( AxiIdWidthSlaves ), + .AxiUserWidth ( AxiUserWidth ), + .NoMasters ( TbNumMst ), + .NoSlaves ( TbNumSlv ), + .NoAddrRules ( xbar_cfg.NoAddrRules ), + .rule_t ( rule_t ), + .AddrMap ( AddrMap ), + .TimeTest ( TestTime ) + ) monitor = new( master_monitor_dv, slave_monitor_dv ); + fork + monitor.run(); + do begin + #TestTime; + if(end_of_sim == '1) begin + monitor.print_result(); + $stop(); + end + @(posedge clk); + end while (1'b1); + join + end + + //----------------------------------- + // Clock generator + //----------------------------------- + clk_rst_gen #( + .ClkPeriod ( CyclTime ), + .RstClkCycles ( 5 ) + ) i_clk_gen ( + .clk_o (clk), + .rst_no(rst_n) + ); + + //----------------------------------- + // DUT + //----------------------------------- + axi_xp_intf #( + .ATOPs ( ATOPs ), + .Cfg ( xbar_cfg ), + .NoSlvPorts ( xbar_cfg.NoSlvPorts ), + .NoMstPorts ( xbar_cfg.NoMstPorts ), + .Connectivity ( Connectivity ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), + .AxiSlvPortMaxTxns ( AxiSlvPortMaxTxns ), + .AxiMstPortMaxUniqIds ( AxiMstPortMaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), + .NoAddrRules ( xbar_cfg.NoAddrRules ), + .rule_t ( rule_t ) + ) i_xp_dut ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( 1'b0 ), + .slv_ports ( master ), + .mst_ports ( slave ), + .addr_map_i ( AddrMap ) + ); + + // logger for master modules + for (genvar i = 0; i < TbNumMst; i++) begin : gen_master_logger + axi_chan_logger #( + .TestTime ( TestTime ), // Time after clock, where sampling happens + .LoggerName( $sformatf("axi_logger_master_%0d", i)), + .aw_chan_t ( aw_chan_mst_t ), // axi AW type + .w_chan_t ( w_chan_t ), // axi W type + .b_chan_t ( b_chan_mst_t ), // axi B type + .ar_chan_t ( ar_chan_mst_t ), // axi AR type + .r_chan_t ( r_chan_mst_t ) // axi R type + ) i_mst_channel_logger ( + .clk_i ( clk ), // Clock + .rst_ni ( rst_n ), // Asynchronous reset active low, when `1'b0` no sampling + .end_sim_i ( &end_of_sim ), + // AW channel + .aw_chan_i ( masters_req[i].aw ), + .aw_valid_i ( masters_req[i].aw_valid ), + .aw_ready_i ( masters_resp[i].aw_ready ), + // W channel + .w_chan_i ( masters_req[i].w ), + .w_valid_i ( masters_req[i].w_valid ), + .w_ready_i ( masters_resp[i].w_ready ), + // B channel + .b_chan_i ( masters_resp[i].b ), + .b_valid_i ( masters_resp[i].b_valid ), + .b_ready_i ( masters_req[i].b_ready ), + // AR channel + .ar_chan_i ( masters_req[i].ar ), + .ar_valid_i ( masters_req[i].ar_valid ), + .ar_ready_i ( masters_resp[i].ar_ready ), + // R channel + .r_chan_i ( masters_resp[i].r ), + .r_valid_i ( masters_resp[i].r_valid ), + .r_ready_i ( masters_req[i].r_ready ) + ); + end + // logger for slave modules + for (genvar i = 0; i < TbNumSlv; i++) begin : gen_slave_logger + axi_chan_logger #( + .TestTime ( TestTime ), // Time after clock, where sampling happens + .LoggerName( $sformatf("axi_logger_slave_%0d",i)), + .aw_chan_t ( aw_chan_slv_t ), // axi AW type + .w_chan_t ( w_chan_t ), // axi W type + .b_chan_t ( b_chan_slv_t ), // axi B type + .ar_chan_t ( ar_chan_slv_t ), // axi AR type + .r_chan_t ( r_chan_slv_t ) // axi R type + ) i_slv_channel_logger ( + .clk_i ( clk ), // Clock + .rst_ni ( rst_n ), // Asynchronous reset active low, when `1'b0` no sampling + .end_sim_i ( &end_of_sim ), + // AW channel + .aw_chan_i ( slaves_req[i].aw ), + .aw_valid_i ( slaves_req[i].aw_valid ), + .aw_ready_i ( slaves_resp[i].aw_ready ), + // W channel + .w_chan_i ( slaves_req[i].w ), + .w_valid_i ( slaves_req[i].w_valid ), + .w_ready_i ( slaves_resp[i].w_ready ), + // B channel + .b_chan_i ( slaves_resp[i].b ), + .b_valid_i ( slaves_resp[i].b_valid ), + .b_ready_i ( slaves_req[i].b_ready ), + // AR channel + .ar_chan_i ( slaves_req[i].ar ), + .ar_valid_i ( slaves_req[i].ar_valid ), + .ar_ready_i ( slaves_resp[i].ar_ready ), + // R channel + .r_chan_i ( slaves_resp[i].r ), + .r_valid_i ( slaves_resp[i].r_valid ), + .r_ready_i ( slaves_req[i].r_ready ) + ); + end + + + for (genvar i = 0; i < TbNumMst; i++) begin : gen_connect_master_monitor + assign master_monitor_dv[i].aw_id = master[i].aw_id ; + assign master_monitor_dv[i].aw_addr = master[i].aw_addr ; + assign master_monitor_dv[i].aw_len = master[i].aw_len ; + assign master_monitor_dv[i].aw_size = master[i].aw_size ; + assign master_monitor_dv[i].aw_burst = master[i].aw_burst ; + assign master_monitor_dv[i].aw_lock = master[i].aw_lock ; + assign master_monitor_dv[i].aw_cache = master[i].aw_cache ; + assign master_monitor_dv[i].aw_prot = master[i].aw_prot ; + assign master_monitor_dv[i].aw_qos = master[i].aw_qos ; + assign master_monitor_dv[i].aw_region = master[i].aw_region; + assign master_monitor_dv[i].aw_atop = master[i].aw_atop ; + assign master_monitor_dv[i].aw_user = master[i].aw_user ; + assign master_monitor_dv[i].aw_valid = master[i].aw_valid ; + assign master_monitor_dv[i].aw_ready = master[i].aw_ready ; + assign master_monitor_dv[i].w_data = master[i].w_data ; + assign master_monitor_dv[i].w_strb = master[i].w_strb ; + assign master_monitor_dv[i].w_last = master[i].w_last ; + assign master_monitor_dv[i].w_user = master[i].w_user ; + assign master_monitor_dv[i].w_valid = master[i].w_valid ; + assign master_monitor_dv[i].w_ready = master[i].w_ready ; + assign master_monitor_dv[i].b_id = master[i].b_id ; + assign master_monitor_dv[i].b_resp = master[i].b_resp ; + assign master_monitor_dv[i].b_user = master[i].b_user ; + assign master_monitor_dv[i].b_valid = master[i].b_valid ; + assign master_monitor_dv[i].b_ready = master[i].b_ready ; + assign master_monitor_dv[i].ar_id = master[i].ar_id ; + assign master_monitor_dv[i].ar_addr = master[i].ar_addr ; + assign master_monitor_dv[i].ar_len = master[i].ar_len ; + assign master_monitor_dv[i].ar_size = master[i].ar_size ; + assign master_monitor_dv[i].ar_burst = master[i].ar_burst ; + assign master_monitor_dv[i].ar_lock = master[i].ar_lock ; + assign master_monitor_dv[i].ar_cache = master[i].ar_cache ; + assign master_monitor_dv[i].ar_prot = master[i].ar_prot ; + assign master_monitor_dv[i].ar_qos = master[i].ar_qos ; + assign master_monitor_dv[i].ar_region = master[i].ar_region; + assign master_monitor_dv[i].ar_user = master[i].ar_user ; + assign master_monitor_dv[i].ar_valid = master[i].ar_valid ; + assign master_monitor_dv[i].ar_ready = master[i].ar_ready ; + assign master_monitor_dv[i].r_id = master[i].r_id ; + assign master_monitor_dv[i].r_data = master[i].r_data ; + assign master_monitor_dv[i].r_resp = master[i].r_resp ; + assign master_monitor_dv[i].r_last = master[i].r_last ; + assign master_monitor_dv[i].r_user = master[i].r_user ; + assign master_monitor_dv[i].r_valid = master[i].r_valid ; + assign master_monitor_dv[i].r_ready = master[i].r_ready ; + end + for (genvar i = 0; i < TbNumSlv; i++) begin : gen_connect_slave_monitor + assign slave_monitor_dv[i].aw_id = slave[i].aw_id ; + assign slave_monitor_dv[i].aw_addr = slave[i].aw_addr ; + assign slave_monitor_dv[i].aw_len = slave[i].aw_len ; + assign slave_monitor_dv[i].aw_size = slave[i].aw_size ; + assign slave_monitor_dv[i].aw_burst = slave[i].aw_burst ; + assign slave_monitor_dv[i].aw_lock = slave[i].aw_lock ; + assign slave_monitor_dv[i].aw_cache = slave[i].aw_cache ; + assign slave_monitor_dv[i].aw_prot = slave[i].aw_prot ; + assign slave_monitor_dv[i].aw_qos = slave[i].aw_qos ; + assign slave_monitor_dv[i].aw_region = slave[i].aw_region; + assign slave_monitor_dv[i].aw_atop = slave[i].aw_atop ; + assign slave_monitor_dv[i].aw_user = slave[i].aw_user ; + assign slave_monitor_dv[i].aw_valid = slave[i].aw_valid ; + assign slave_monitor_dv[i].aw_ready = slave[i].aw_ready ; + assign slave_monitor_dv[i].w_data = slave[i].w_data ; + assign slave_monitor_dv[i].w_strb = slave[i].w_strb ; + assign slave_monitor_dv[i].w_last = slave[i].w_last ; + assign slave_monitor_dv[i].w_user = slave[i].w_user ; + assign slave_monitor_dv[i].w_valid = slave[i].w_valid ; + assign slave_monitor_dv[i].w_ready = slave[i].w_ready ; + assign slave_monitor_dv[i].b_id = slave[i].b_id ; + assign slave_monitor_dv[i].b_resp = slave[i].b_resp ; + assign slave_monitor_dv[i].b_user = slave[i].b_user ; + assign slave_monitor_dv[i].b_valid = slave[i].b_valid ; + assign slave_monitor_dv[i].b_ready = slave[i].b_ready ; + assign slave_monitor_dv[i].ar_id = slave[i].ar_id ; + assign slave_monitor_dv[i].ar_addr = slave[i].ar_addr ; + assign slave_monitor_dv[i].ar_len = slave[i].ar_len ; + assign slave_monitor_dv[i].ar_size = slave[i].ar_size ; + assign slave_monitor_dv[i].ar_burst = slave[i].ar_burst ; + assign slave_monitor_dv[i].ar_lock = slave[i].ar_lock ; + assign slave_monitor_dv[i].ar_cache = slave[i].ar_cache ; + assign slave_monitor_dv[i].ar_prot = slave[i].ar_prot ; + assign slave_monitor_dv[i].ar_qos = slave[i].ar_qos ; + assign slave_monitor_dv[i].ar_region = slave[i].ar_region; + assign slave_monitor_dv[i].ar_user = slave[i].ar_user ; + assign slave_monitor_dv[i].ar_valid = slave[i].ar_valid ; + assign slave_monitor_dv[i].ar_ready = slave[i].ar_ready ; + assign slave_monitor_dv[i].r_id = slave[i].r_id ; + assign slave_monitor_dv[i].r_data = slave[i].r_data ; + assign slave_monitor_dv[i].r_resp = slave[i].r_resp ; + assign slave_monitor_dv[i].r_last = slave[i].r_last ; + assign slave_monitor_dv[i].r_user = slave[i].r_user ; + assign slave_monitor_dv[i].r_valid = slave[i].r_valid ; + assign slave_monitor_dv[i].r_ready = slave[i].r_ready ; + end +endmodule diff --git a/test/tb_axi_xp_pkg.sv b/test/tb_axi_xp_pkg.sv new file mode 100644 index 000000000..ee8b440fe --- /dev/null +++ b/test/tb_axi_xp_pkg.sv @@ -0,0 +1,505 @@ +// Copyright (c) 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Authors: +// - Florian Zaruba +// - Wolfgang Roenninger +// - Vikram Jain + +// `axi_xp_monitor` implements an AXI bus monitor that is tuned for the AXI crosspoint. +// It snoops on each of the slaves and master ports of the crosspoint and +// populates FIFOs and ID queues to validate that no AXI beats get +// lost or sent to the wrong destination. It ignores the ID checks for the AW and AR +// channels as they get remapped in the id_remapper + +package tb_axi_xp_pkg; + class axi_xp_monitor #( + parameter int unsigned AxiAddrWidth, + parameter int unsigned AxiDataWidth, + parameter int unsigned AxiIdWidthMasters, + parameter int unsigned AxiIdWidthSlaves, + parameter int unsigned AxiUserWidth, + parameter int unsigned NoMasters, + parameter int unsigned NoSlaves, + parameter int unsigned NoAddrRules, + parameter type rule_t, + parameter rule_t [NoAddrRules-1:0] AddrMap, + // Stimuli application and test time + parameter time TimeTest + ); + typedef logic [AxiIdWidthMasters-1:0] mst_axi_id_t; + typedef logic [AxiIdWidthSlaves-1:0] slv_axi_id_t; + typedef logic [AxiAddrWidth-1:0] axi_addr_t; + + typedef logic [$clog2(NoMasters)-1:0] idx_mst_t; + typedef int unsigned idx_slv_t; // from rule_t + + typedef struct packed { + mst_axi_id_t mst_axi_id; + logic last; + } master_exp_t; + typedef struct packed { + slv_axi_id_t slv_axi_id; + axi_addr_t slv_axi_addr; + axi_pkg::len_t slv_axi_len; + } exp_ax_t; + typedef struct packed { + slv_axi_id_t slv_axi_id; + logic last; + } slave_exp_t; + + typedef rand_id_queue_pkg::rand_id_queue #( + .data_t ( master_exp_t ), + .ID_WIDTH ( AxiIdWidthMasters ) + ) master_exp_queue_t; + typedef rand_id_queue_pkg::rand_id_queue #( + .data_t ( exp_ax_t ), + .ID_WIDTH ( AxiIdWidthSlaves ) + ) ax_queue_t; + + typedef rand_id_queue_pkg::rand_id_queue #( + .data_t ( slave_exp_t ), + .ID_WIDTH ( AxiIdWidthSlaves ) + ) slave_exp_queue_t; + + //----------------------------------------- + // Monitoring virtual interfaces + //----------------------------------------- + virtual AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_ID_WIDTH ( AxiIdWidthMasters ), + .AXI_USER_WIDTH ( AxiUserWidth ) + ) masters_axi [NoMasters-1:0]; + virtual AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_ID_WIDTH ( AxiIdWidthSlaves ), + .AXI_USER_WIDTH ( AxiUserWidth ) + ) slaves_axi [NoSlaves-1:0]; + //----------------------------------------- + // Queues and FIFOs to hold the expected ids + //----------------------------------------- + // Write transactions + ax_queue_t exp_aw_queue [NoSlaves-1:0]; + slave_exp_t exp_w_fifo [NoSlaves-1:0][$]; + slave_exp_t act_w_fifo [NoSlaves-1:0][$]; + master_exp_queue_t exp_b_queue [NoMasters-1:0]; + + // Read transactions + ax_queue_t exp_ar_queue [NoSlaves-1:0]; + master_exp_queue_t exp_r_queue [NoMasters-1:0]; + + //----------------------------------------- + // Bookkeeping + //----------------------------------------- + longint unsigned tests_expected; + longint unsigned tests_conducted; + longint unsigned tests_failed; + semaphore cnt_sem; + + //----------------------------------------- + // Constructor + //----------------------------------------- + function new( + virtual AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_ID_WIDTH ( AxiIdWidthMasters ), + .AXI_USER_WIDTH ( AxiUserWidth ) + ) axi_masters_vif [NoMasters-1:0], + virtual AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_ID_WIDTH ( AxiIdWidthSlaves ), + .AXI_USER_WIDTH ( AxiUserWidth ) + ) axi_slaves_vif [NoSlaves-1:0] + ); + begin + this.masters_axi = axi_masters_vif; + this.slaves_axi = axi_slaves_vif; + this.tests_expected = 0; + this.tests_conducted = 0; + this.tests_failed = 0; + for (int unsigned i = 0; i < NoMasters; i++) begin + this.exp_b_queue[i] = new; + this.exp_r_queue[i] = new; + end + for (int unsigned i = 0; i < NoSlaves; i++) begin + this.exp_aw_queue[i] = new; + this.exp_ar_queue[i] = new; + end + this.cnt_sem = new(1); + end + endfunction + + // when start the testing + task cycle_start; + #TimeTest; + endtask + + // when is cycle finished + task cycle_end; + @(posedge masters_axi[0].clk_i); + endtask + + // This task monitors a slave ports of the crossbar. Every time an AW beat is seen + // it populates an id queue at the right master port (if there is no expected decode error), + // populates the expected b response in its own id_queue and in case when the atomic bit [5] + // is set it also injects an expected response in the R channel. + task automatic monitor_mst_aw(input int unsigned i); + idx_slv_t to_slave_idx; + exp_ax_t exp_aw; + slv_axi_id_t exp_aw_id; + bit decerr; + + master_exp_t exp_b; + + if (masters_axi[i].aw_valid && masters_axi[i].aw_ready) begin + // check if it should go to a decerror + decerr = 1'b1; + for (int unsigned j = 0; j < NoAddrRules; j++) begin + if ((masters_axi[i].aw_addr >= AddrMap[j].start_addr) && + (masters_axi[i].aw_addr < AddrMap[j].end_addr)) begin + to_slave_idx = idx_slv_t'(AddrMap[j].idx); + decerr = 1'b0; + end + end + // send the exp aw beat down into the queue of the slave when no decerror + if (!decerr) begin + exp_aw_id = {idx_mst_t'(i), masters_axi[i].aw_id}; + // $display("Test exp aw_id: %b",exp_aw_id); + exp_aw = '{slv_axi_id: exp_aw_id, + slv_axi_addr: masters_axi[i].aw_addr, + slv_axi_len: masters_axi[i].aw_len }; + this.exp_aw_queue[to_slave_idx].push(exp_aw_id, exp_aw); + incr_expected_tests(3); + $display("%0tns > Master %0d: AW to Slave %0d: Axi ID: %b", + $time, i, to_slave_idx, masters_axi[i].aw_id); + end else begin + $display("%0tns > Master %0d: AW to Decerror: Axi ID: %b", + $time, i, to_slave_idx, masters_axi[i].aw_id); + end + // populate the expected b queue anyway + exp_b = '{mst_axi_id: masters_axi[i].aw_id, last: 1'b1}; + this.exp_b_queue[i].push(masters_axi[i].aw_id, exp_b); + incr_expected_tests(1); + $display(" Expect B response."); + // inject expected r beats on this id, if it is an atop + if(masters_axi[i].aw_atop[5]) begin + // push the required r beats into the right fifo (reuse the exp_b variable) + $display(" Expect R response, len: %0d.", masters_axi[i].aw_len); + for (int unsigned j = 0; j <= masters_axi[i].aw_len; j++) begin + exp_b = (j == masters_axi[i].aw_len) ? + '{mst_axi_id: masters_axi[i].aw_id, last: 1'b1} : + '{mst_axi_id: masters_axi[i].aw_id, last: 1'b0}; + this.exp_r_queue[i].push(masters_axi[i].aw_id, exp_b); + incr_expected_tests(1); + end + end + end + endtask : monitor_mst_aw + + // This task monitors a slave port of the crossbar. Every time there is an AW vector it + // gets checked for its contents and if it was expected. The task then pushes an expected + // amount of W beats in the respective fifo. Emphasis of the last flag. + task automatic monitor_slv_aw(input int unsigned i); + exp_ax_t exp_aw; + slave_exp_t exp_slv_w; + // $display("%0t > Was triggered: aw_valid %b, aw_ready: %b", + // $time(), slaves_axi[i].aw_valid, slaves_axi[i].aw_ready); + if (slaves_axi[i].aw_valid && slaves_axi[i].aw_ready) begin + // test if the aw beat was expected + exp_aw = this.exp_aw_queue[i].pop_id(slaves_axi[i].aw_id); + $display("%0tns > Slave %0d: AW Axi ID: %b", + $time, i, slaves_axi[i].aw_id); + if (exp_aw.slv_axi_id != slaves_axi[i].aw_id) begin + incr_failed_tests(1); + $warning("Slave %0d: Unexpected AW with ID: %b", i, slaves_axi[i].aw_id); + end + if (exp_aw.slv_axi_addr != slaves_axi[i].aw_addr) begin + incr_failed_tests(1); + $warning("Slave %0d: Unexpected AW with ID: %b and ADDR: %h, exp: %h", + i, slaves_axi[i].aw_id, slaves_axi[i].aw_addr, exp_aw.slv_axi_addr); + end + if (exp_aw.slv_axi_len != slaves_axi[i].aw_len) begin + incr_failed_tests(1); + $warning("Slave %0d: Unexpected AW with ID: %b and LEN: %h, exp: %h", + i, slaves_axi[i].aw_id, slaves_axi[i].aw_len, exp_aw.slv_axi_len); + end + incr_conducted_tests(3); + + // push the required w beats into the right fifo + incr_expected_tests(slaves_axi[i].aw_len + 1); + for (int unsigned j = 0; j <= slaves_axi[i].aw_len; j++) begin + exp_slv_w = (j == slaves_axi[i].aw_len) ? + '{slv_axi_id: slaves_axi[i].aw_id, last: 1'b1} : + '{slv_axi_id: slaves_axi[i].aw_id, last: 1'b0}; + this.exp_w_fifo[i].push_back(exp_slv_w); + end + end + endtask : monitor_slv_aw + + // This task just pushes every W beat that gets sent on a master port in its respective fifo. + task automatic monitor_slv_w(input int unsigned i); + slave_exp_t act_slv_w; + if (slaves_axi[i].w_valid && slaves_axi[i].w_ready) begin + // $display("%0t > W beat on Slave %0d, last flag: %b", $time, i, slaves_axi[i].w_last); + act_slv_w = '{last: slaves_axi[i].w_last , default:'0}; + this.act_w_fifo[i].push_back(act_slv_w); + end + endtask : monitor_slv_w + + // This task compares the expected and actual W beats on a master port. The reason that + // this is not done in `monitor_slv_w` is that there can be per protocol W beats on the + // channel, before AW is sent to the slave. + task automatic check_slv_w(input int unsigned i); + slave_exp_t exp_w, act_w; + while (this.exp_w_fifo[i].size() != 0 && this.act_w_fifo[i].size() != 0) begin + + exp_w = this.exp_w_fifo[i].pop_front(); + act_w = this.act_w_fifo[i].pop_front(); + // do the check + incr_conducted_tests(1); + if(exp_w.last != act_w.last) begin + incr_failed_tests(1); + $warning("Slave %d: unexpected W beat last flag %b, expected: %b.", + i, act_w.last, exp_w.last); + end + end + endtask : check_slv_w + + // This task checks if a B response is allowed on a slave port of the crossbar. + task automatic monitor_mst_b(input int unsigned i); + master_exp_t exp_b; + mst_axi_id_t axi_b_id; + if (masters_axi[i].b_valid && masters_axi[i].b_ready) begin + incr_conducted_tests(1); + axi_b_id = masters_axi[i].b_id; + $display("%0tns > Master %0d: Got last B with id: %b", + $time, i, axi_b_id); + if (this.exp_b_queue[i].empty()) begin + incr_failed_tests(1); + $warning("Master %d: unexpected B beat with ID: %b detected!", i, axi_b_id); + end else begin + exp_b = this.exp_b_queue[i].pop_id(axi_b_id); + if (axi_b_id != exp_b.mst_axi_id) begin + incr_failed_tests(1); + $warning("Master: %d got unexpected B with ID: %b", i, axi_b_id); + end + end + end + endtask : monitor_mst_b + + // This task monitors the AR channel of a slave port of the crossbar. For each AR it populates + // the corresponding ID queue with the number of r beats indicated on the `ar_len` field. + // Emphasis on the last flag. We will detect reordering, if the last flags do not match, + // as each `random` burst tend to have a different length. + task automatic monitor_mst_ar(input int unsigned i); + mst_axi_id_t mst_axi_id; + axi_addr_t mst_axi_addr; + axi_pkg::len_t mst_axi_len; + + idx_slv_t exp_slv_idx; + slv_axi_id_t exp_slv_axi_id; + exp_ax_t exp_slv_ar; + master_exp_t exp_mst_r; + + logic exp_decerr; + + if (masters_axi[i].ar_valid && masters_axi[i].ar_ready) begin + exp_decerr = 1'b1; + mst_axi_id = masters_axi[i].ar_id; + mst_axi_addr = masters_axi[i].ar_addr; + mst_axi_len = masters_axi[i].ar_len; + exp_slv_axi_id = {idx_mst_t'(i), mst_axi_id}; + exp_slv_idx = '0; + for (int unsigned j = 0; j < NoAddrRules; j++) begin + if ((mst_axi_addr >= AddrMap[j].start_addr) && (mst_axi_addr < AddrMap[j].end_addr)) begin + exp_slv_idx = AddrMap[j].idx; + exp_decerr = 1'b0; + end + end + if (exp_decerr) begin + $display("%0tns > Master %0d: AR to Decerror: Axi ID: %b", + $time, i, mst_axi_id); + end else begin + $display("%0tns > Master %0d: AR to Slave %0d: Axi ID: %b", + $time, i, exp_slv_idx, mst_axi_id); + // push the expected vectors AW for exp_slv + exp_slv_ar = '{slv_axi_id: exp_slv_axi_id, + slv_axi_addr: mst_axi_addr, + slv_axi_len: mst_axi_len }; + //$display("Expected Slv Axi Id is: %b", exp_slv_axi_id); + this.exp_ar_queue[exp_slv_idx].push(exp_slv_axi_id, exp_slv_ar); + incr_expected_tests(1); + end + // push the required r beats into the right fifo + $display(" Expect R response, len: %0d.", masters_axi[i].ar_len); + for (int unsigned j = 0; j <= mst_axi_len; j++) begin + exp_mst_r = (j == mst_axi_len) ? '{mst_axi_id: mst_axi_id, last: 1'b1} : + '{mst_axi_id: mst_axi_id, last: 1'b0}; + this.exp_r_queue[i].push(mst_axi_id, exp_mst_r); + incr_expected_tests(1); + end + end + endtask : monitor_mst_ar + + // This task monitors a master port of the crossbar and checks if a transmitted AR beat was + // expected. + task automatic monitor_slv_ar(input int unsigned i); + exp_ax_t exp_slv_ar; + slv_axi_id_t slv_axi_id; + if (slaves_axi[i].ar_valid && slaves_axi[i].ar_ready) begin + incr_conducted_tests(1); + slv_axi_id = slaves_axi[i].ar_id; + if (this.exp_ar_queue[i].empty()) begin + incr_failed_tests(1); + end else begin + // check that the ids are the same + exp_slv_ar = this.exp_ar_queue[i].pop_id(slv_axi_id); + $display("%0tns > Slave %0d: AR Axi ID: %b", $time, i, slv_axi_id); + if (exp_slv_ar.slv_axi_id != slv_axi_id) begin + incr_failed_tests(1); + $warning("Slave %d: Unexpected AR with ID: %b", i, slv_axi_id); + end + end + end + endtask : monitor_slv_ar + + // This task does the R channel monitoring on a slave port. It compares the last flags, + // which are determined by the sequence of previously sent AR vectors. + task automatic monitor_mst_r(input int unsigned i); + master_exp_t exp_mst_r; + mst_axi_id_t mst_axi_r_id; + logic mst_axi_r_last; + if (masters_axi[i].r_valid && masters_axi[i].r_ready) begin + incr_conducted_tests(1); + mst_axi_r_id = masters_axi[i].r_id; + mst_axi_r_last = masters_axi[i].r_last; + if (mst_axi_r_last) begin + $display("%0tns > Master %0d: Got last R with id: %b", + $time, i, mst_axi_r_id); + end + if (this.exp_r_queue[i].empty()) begin + incr_failed_tests(1); + $warning("Master %d: unexpected R beat with ID: %b detected!", i, mst_axi_r_id); + end else begin + exp_mst_r = this.exp_r_queue[i].pop_id(mst_axi_r_id); + if (mst_axi_r_id != exp_mst_r.mst_axi_id) begin + incr_failed_tests(1); + $warning("Master: %d got unexpected R with ID: %b", i, mst_axi_r_id); + end + if (mst_axi_r_last != exp_mst_r.last) begin + incr_failed_tests(1); + $warning("Master: %d got unexpected R with ID: %b and last flag: %b", + i, mst_axi_r_id, mst_axi_r_last); + end + end + end + endtask : monitor_mst_r + + // Some tasks to manage bookkeeping of the tests conducted. + task incr_expected_tests(input int unsigned times); + cnt_sem.get(); + this.tests_expected += times; + cnt_sem.put(); + endtask : incr_expected_tests + + task incr_conducted_tests(input int unsigned times); + cnt_sem.get(); + this.tests_conducted += times; + cnt_sem.put(); + endtask : incr_conducted_tests + + task incr_failed_tests(input int unsigned times); + cnt_sem.get(); + this.tests_failed += times; + cnt_sem.put(); + endtask : incr_failed_tests + + // This task invokes the various monitoring tasks. It first forks in two, spitting + // the tasks that should continuously run and the ones that get invoked every clock cycle. + // For the tasks every clock cycle all processes that only push something in the fifo's and + // Queues get run. When they are finished the processes that pop something get run. + task run(); + Continous: fork + begin + do begin + cycle_start(); + // at every cycle span some monitoring processes + // execute all processes that put something into the queues + PushMon: fork + proc_mst_aw: begin + for (int unsigned i = 0; i < NoMasters; i++) begin + monitor_mst_aw(i); + end + end + proc_mst_ar: begin + for (int unsigned i = 0; i < NoMasters; i++) begin + monitor_mst_ar(i); + end + end + join : PushMon + // this one pops and pushes something + proc_slv_aw: begin + for (int unsigned i = 0; i < NoSlaves; i++) begin + monitor_slv_aw(i); + end + end + proc_slv_w: begin + for (int unsigned i = 0; i < NoSlaves; i++) begin + monitor_slv_w(i); + end + end + // These only pop somethong from the queses + PopMon: fork + proc_mst_b: begin + for (int unsigned i = 0; i < NoMasters; i++) begin + monitor_mst_b(i); + end + end + proc_slv_ar: begin + for (int unsigned i = 0; i < NoSlaves; i++) begin + monitor_slv_ar(i); + end + end + proc_mst_r: begin + for (int unsigned i = 0; i < NoMasters; i++) begin + monitor_mst_r(i); + end + end + join : PopMon + // check the slave W fifos last + proc_check_slv_w: begin + for (int unsigned i = 0; i < NoSlaves; i++) begin + check_slv_w(i); + end + end + cycle_end(); + end while (1'b1); + end + join + endtask : run + + task print_result(); + $info("Simulation has ended!"); + $display("Tests Expected: %d", this.tests_expected); + $display("Tests Conducted: %d", this.tests_conducted); + $display("Tests Failed: %d", this.tests_failed); + if(tests_failed > 0) begin + $error("Simulation encountered unexpected Transactions!!!!!!"); + end + if(tests_conducted == 0) begin + $error("Simulation did not conduct any tests!"); + end + endtask : print_result + endclass : axi_xp_monitor +endpackage