PATRONoC source code

Bender.yml

@@ -57,6 +57,13 @@ sources:
   - src/axi_iw_converter.sv
   - src/axi_lite_xbar.sv
   - src/axi_xbar.sv
+  # Level 5
+  - src/axi_xp.sv
+  - src/axi_dma_backend.sv
+  - src/axi_dma_burst_reshaper.sv
+  - src/axi_dma_data_mover.sv
+  - src/axi_dma_data_path.sv
+  - src/axi_aw_w_sync.sv
 
   - target: synth_test
     files:
@@ -72,6 +79,7 @@ sources:
       # Level 0
       - test/tb_axi_dw_pkg.sv
       - test/tb_axi_xbar_pkg.sv
+      - test/tb_axi_xp_pkg.sv
       # Level 1
       - test/tb_axi_addr_test.sv
       - test/tb_axi_atop_filter.sv
@@ -91,3 +99,6 @@ sources:
       - test/tb_axi_sim_mem.sv
       - test/tb_axi_to_axi_lite.sv
       - test/tb_axi_xbar.sv
+      - test/tb_axi_xp.sv
+      - test/tb_axi_dma_backend.sv
+      - test/fixture_axi_dma_backend.sv

CHANGELOG.md

@@ -8,6 +8,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 ## Unreleased
 
 ### Added
+- `axi_xp`: Crosspoint with homomorphous slave and master ports.
 
 ### Changed
 

parse_trace.py

@@ -0,0 +1,31 @@
+#GVSoC trace files input
+f1 = open("traces_pip_16cl.txt", 'r')
+#testbench dma input traces
+f2 = open("traces_pip_16cl_tb.txt", 'w+')
+total_bytes=0
+f1_lines = f1.readlines()
+for l in f1_lines:
+        try:
+                key_word1 = list(l.split())[2]
+                key_word2 = list(l.split())[11]
+                key_word3 = list(l.split())[13]
+                key_word4 = list(l.split())[15]
+                if key_word1[-1] == 'e':
+                        if key_word1[29] == '/':
+                            f2.write('0'+' '+key_word2[:-1]+' '+key_word3[:-1]+' '+key_word4[:-1]+'\n')
+                            total_bytes = total_bytes + int(key_word4[2:-1], base=16)
+                            #print(int(key_word4[2:-1], base=16))
+                        elif key_word1[29] == '_':
+                            if key_word1[31] == '/':
+                                f2.write(key_word1[30]+' '+key_word2[:-1]+' '+key_word3[:-1]+' '+key_word4[:-1]+'\n')
+                                total_bytes = total_bytes + int(key_word4[2:-1], base=16)
+                                #print(int(key_word4[2:-1], base=16))
+                            else:
+                                f2.write(key_word1[30:32]+' '+key_word2[:-1]+' '+key_word3[:-1]+' '+key_word4[:-1]+'\n')
+                                total_bytes = total_bytes + int(key_word4[2:-1], base=16)
+        except:
+                continue
+
+print(total_bytes)
+f1.close()
+f2.close()

scripts/run_vsim.sh

@@ -29,7 +29,7 @@ SEEDS=(0)
 
 call_vsim() {
     for seed in ${SEEDS[@]}; do
-        echo "run -all" | $VSIM -sv_seed $seed "$@" | tee vsim.log 2>&1
+        echo "run -all" | $VSIM -sv_seed $seed "$@" | tee vsim.log 2>&1 #-gui
         grep "Errors: 0," vsim.log
     done
 }
@@ -174,6 +174,24 @@ exec_test() {
                 done
             done
             ;;
+        axi_xp)
+            for NumMst in 1 4; do
+                for NumSlv in 1 4; do
+                    for Atop in 0 1; do
+                        for Exclusive in 0 1; do
+                            for UniqueIds in 0 1; do
+                                call_vsim tb_axi_xp -gTbNumMst=$NumMst -gTbNumSlv=$NumSlv \
+                                        -gTbEnAtop=$Atop -gTbEnExcl=$Exclusive \
+                                        -gTbUniqueIds=$UniqueIds
+                            done
+                        done
+                    done
+                done
+            done
+            ;;
+        axi_dma_backend)
+            call_vsim tb_$1 -voptargs="+acc +cover=bcesfx"
+            ;; 
         *)
             call_vsim tb_$1 -t 1ns -coverage -voptargs="+acc +cover=bcesfx"
             ;;

src/axi_aw_w_sync.sv

@@ -0,0 +1,128 @@
+/* Copyright 2021 ETH Zurich and University of Bologna.
+ * Copyright and related rights are licensed under the Solderpad Hardware
+ * License, Version 0.51 (the “License”); you may not use this file except in
+ * compliance with the License.  You may obtain a copy of the License at
+ * http: //solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+ * or agreed to in writing, software, hardware and materials distributed under
+ * this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
+ * CONDITIONS OF ANY KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations under the License.
+ *
+ * Author: Michael Rogenmoser <michaero@iis.ee.ethz.ch>
+ * Date:   15.02.2022
+ *
+ */
+
+/// Only allows passing of AW if corresponding W is valid.
+/// Only allows passing of W if corresponding AW is valid or sent.
+
+`include "axi/assign.svh"
+`include "common_cells/registers.svh"
+
+module axi_aw_w_sync #(
+  parameter type axi_req_t  = logic,
+  parameter type axi_resp_t = logic
+) (
+  input  logic      clk_i,
+  input  logic      rst_ni,
+
+  input  axi_req_t  slv_req_i,
+  output axi_resp_t slv_resp_o,
+
+  output axi_req_t  mst_req_o,
+  input  axi_resp_t mst_resp_i
+);
+
+  `AXI_ASSIGN_AR_STRUCT(mst_req_o.ar, slv_req_i.ar)
+  assign mst_req_o.ar_valid = slv_req_i.ar_valid;
+  assign slv_resp_o.ar_ready = mst_resp_i.ar_ready;
+  `AXI_ASSIGN_R_STRUCT(slv_resp_o.r, mst_resp_i.r)
+  assign slv_resp_o.r_valid = mst_resp_i.r_valid;
+  assign mst_req_o.r_ready = slv_req_i.r_ready;
+  `AXI_ASSIGN_B_STRUCT(slv_resp_o.b, mst_resp_i.b)
+  assign slv_resp_o.b_valid = mst_resp_i.b_valid;
+  assign mst_req_o.b_ready = slv_req_i.b_ready;
+
+  `AXI_ASSIGN_AW_STRUCT(mst_req_o.aw, slv_req_i.aw)
+  `AXI_ASSIGN_W_STRUCT(mst_req_o.w, slv_req_i.w)
+
+  logic aw_valid, w_valid;
+  logic w_completed_d, w_completed_q;
+  `FF(w_completed_q, w_completed_d, 1'b1)
+
+
+  // AW is valid when previous write completed and current AW and W are valid
+  assign aw_valid = w_completed_q && slv_req_i.aw_valid && slv_req_i.w_valid;
+
+  // W is valid when corresponding AW is valid or sent
+  assign w_valid = slv_req_i.w_valid && (!w_completed_q || (aw_valid && mst_resp_i.aw_ready)); // This is probably pretty bad for timing
+
+  always_comb begin
+    w_completed_d = w_completed_q;
+    // reset w_completed to 0 when a new AW request happens
+    if (aw_valid && mst_resp_i.aw_ready) begin
+      w_completed_d = 1'b0;
+    end
+    // assign w_completed to w_last when W handshake is done and W is ongoing
+    if (slv_req_i.w_valid && slv_resp_o.w_ready) begin
+      w_completed_d = slv_req_i.w.last;
+    end
+  end
+
+  assign mst_req_o.w_valid = w_valid;
+  assign slv_resp_o.w_ready = w_valid && mst_resp_i.w_ready;
+  assign mst_req_o.aw_valid = aw_valid;
+  assign slv_resp_o.aw_ready = aw_valid && mst_resp_i.aw_ready;
+
+endmodule
+
+`include "axi/typedef.svh"
+
+module axi_aw_w_sync_intf #(
+  parameter int unsigned AXI_ADDR_WIDTH = 0,
+  parameter int unsigned AXI_DATA_WIDTH = 0,
+  parameter int unsigned AXI_ID_WIDTH   = 0,
+  parameter int unsigned AXI_USER_WIDTH = 0
+) (
+  input logic    clk_i,
+  input logic    rst_ni,
+  AXI_BUS.Slave  in,
+  AXI_BUS.Master out
+);
+
+  typedef logic [    AXI_ID_WIDTH-1:0] id_t;
+  typedef logic [  AXI_ADDR_WIDTH-1:0] addr_t;
+  typedef logic [  AXI_DATA_WIDTH-1:0] data_t;
+  typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
+  typedef logic [  AXI_USER_WIDTH-1:0] user_t;
+
+  `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
+  `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
+  `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
+  `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
+  `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
+  `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t)
+  `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t)
+
+  axi_req_t  slv_req,  mst_req;
+  axi_resp_t slv_resp, mst_resp;
+
+  `AXI_ASSIGN_TO_REQ(slv_req, in)
+  `AXI_ASSIGN_FROM_RESP(in, slv_resp)
+
+  `AXI_ASSIGN_FROM_REQ(out, mst_req)
+  `AXI_ASSIGN_TO_RESP(mst_resp, out)
+
+  axi_aw_w_sync #(
+    .axi_req_t  ( axi_req_t  ),
+    .axi_resp_t ( axi_resp_t )
+  ) i_axi_aw_w_sync (
+    .clk_i,
+    .rst_ni,
+    .slv_req_i  ( slv_req  ),
+    .slv_resp_o ( slv_resp ),
+    .mst_req_o  ( mst_req  ),
+    .mst_resp_i ( mst_resp )
+  );
+
+endmodule