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coherence: Lint and remove artifacts
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Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
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@niwis
niwis committed Jul 24, 2023
1 parent af62628 commit ed493b4
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Showing 7 changed files with 22 additions and 66 deletions.
4 changes: 2 additions & 2 deletions Makefile
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Expand Up @@ -284,7 +284,7 @@ riscv-torture-bin := java -jar sbt-launch.jar
ifdef batch-mode
questa-flags += -c
questa-cmd := -do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]"
questa-cmd += -do " run -all;"
questa-cmd += -do " log -r /*; run -all;"
else
questa-cmd := -do " log -r /*; run -all;"
endif
Expand Down Expand Up @@ -362,7 +362,7 @@ generate-trace-vsim:

sim: build
$(VSIM) +permissive $(questa-flags) $(questa-cmd) -wlf dump.wlf -lib $(library) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) $(QUESTASIM_FLAGS) +debug_disable +tohost_addr=90000000 -gblso $(SPIKE_ROOT)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) $(QUESTASIM_FLAGS) -gblso $(SPIKE_ROOT)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
${top_level}_optimized +permissive-off ++$(elf-bin) ++$(target-options) | tee sim.log

$(riscv-litmus-tests): $(riscv-litmus-tests-list) build
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22 changes: 0 additions & 22 deletions ci/merge-tests.sh
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18 changes: 0 additions & 18 deletions ci/riscv-litmus-tests.sh
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4 changes: 2 additions & 2 deletions corev_apu/fpga/src/ariane_peripherals_xilinx.sv
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Expand Up @@ -33,7 +33,7 @@ module ariane_peripherals #(
AXI_BUS.Slave gpio ,
AXI_BUS.Slave ethernet ,
AXI_BUS.Slave timer ,
output logic [ (ariane_soc::NumHarts-1) : 0][1:0] irq_o ,
output logic [(ariane_soc::NumHarts-1):0][1:0] irq_o,
// UART
input logic rx_i ,
output logic tx_o ,
Expand Down Expand Up @@ -174,7 +174,7 @@ module ariane_peripherals #(

plic_top #(
.N_SOURCE ( ariane_soc::NumSources ),
.N_TARGET ( (ariane_soc::NumTargets)*(ariane_soc::NumHarts) ),
.N_TARGET ( (ariane_soc::NumTargets)*(ariane_soc::NumHarts) ),
.MAX_PRIO ( ariane_soc::MaxPriority ),
.reg_req_t ( plic_req_t ),
.reg_rsp_t ( plic_rsp_t )
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24 changes: 12 additions & 12 deletions corev_apu/fpga/src/ariane_xilinx.sv
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Expand Up @@ -196,9 +196,9 @@ AXI_BUS #(
logic test_en;
logic ndmreset;
logic ndmreset_n;
logic [ (ariane_soc::NumHarts-1) : 0] debug_req_irq;
logic [ (ariane_soc::NumHarts-1) : 0] timer_irq;
logic [ (ariane_soc::NumHarts-1) : 0] ipi;
logic [(ariane_soc::NumHarts-1):0] debug_req_irq;
logic [(ariane_soc::NumHarts-1):0] timer_irq;
logic [(ariane_soc::NumHarts-1):0] ipi;

logic clk;
logic eth_clk;
Expand Down Expand Up @@ -244,7 +244,7 @@ dm::dmi_resp_t debug_resp;
logic dmactive;

// IRQ
logic [ (ariane_soc::NumHarts-1) : 0][1:0] irq;
logic [(ariane_soc::NumHarts-1):0][1:0] irq;
assign test_en = 1'b0;

logic [NBSlave-1:0] pc_asserted;
Expand Down Expand Up @@ -355,9 +355,9 @@ logic [riscv::XLEN-1:0] dm_master_r_rdata;

// debug module
dm_top #(
.NrHarts (ariane_soc::NumHarts ),
.BusWidth ( riscv::XLEN ),
.SelectableHarts ( {ariane_soc::NumHarts{1'b1}})
.NrHarts ( ariane_soc::NumHarts ),
.BusWidth ( riscv::XLEN ),
.SelectableHarts ( {ariane_soc::NumHarts{1'b1}} )
) i_dm_top (
.clk_i ( clk ),
.rst_ni ( rst_n ), // PoR
Expand All @@ -366,7 +366,7 @@ dm_top #(
.dmactive_o ( dmactive ), // active debug session
.debug_req_o ( debug_req_irq ),
.unavailable_i ( '0 ),
.hartinfo_i ({ariane_soc::NumHarts{ariane_pkg::DebugHartInfo}}),
.hartinfo_i ( {ariane_soc::NumHarts{ariane_pkg::DebugHartInfo}} ),
.slave_req_i ( dm_slave_req ),
.slave_we_i ( dm_slave_we ),
.slave_addr_i ( dm_slave_addr ),
Expand Down Expand Up @@ -699,8 +699,8 @@ end
// ---------------
// Core
// ---------------
ariane_axi::req_t [ (ariane_soc::NumHarts-1) : 0] axi_ariane_req;
ariane_axi::resp_t [ (ariane_soc::NumHarts-1) : 0] axi_ariane_resp;
ariane_axi::req_t [(ariane_soc::NumHarts-1):0] axi_ariane_req;
ariane_axi::resp_t [(ariane_soc::NumHarts-1):0] axi_ariane_resp;

logic [riscv::XLEN-1:0] clint_irqs; // legacy XLEN clint interrupts, RISC-V
// Privilege Spec. v. 20211203, pag. 39
Expand Down Expand Up @@ -986,7 +986,7 @@ clint #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( AxiIdWidthSlaves ),
.NR_CORES ( ariane_soc::NumHarts ),
.NR_CORES ( ariane_soc::NumHarts ),
.axi_req_t ( axi_slave_req_t ),
.axi_resp_t ( axi_slave_resp_t )
) i_clint (
Expand Down Expand Up @@ -1165,7 +1165,7 @@ axi_riscv_atomics_wrap #(
.AXI_ID_WIDTH ( AxiIdWidthSlaves ),
.AXI_USER_WIDTH ( AxiUserWidth ),
.AXI_MAX_WRITE_TXNS ( 1 ),
.AXI_MAX_READ_TXNS ( 1 ),
.AXI_MAX_READ_TXNS ( 1 ),
.RISCV_WORD_WIDTH ( 64 )
) i_axi_riscv_atomics (
.clk_i ( clk ),
Expand Down
4 changes: 2 additions & 2 deletions corev_apu/tb/ariane_peripherals.sv
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Expand Up @@ -30,7 +30,7 @@ module ariane_peripherals #(
AXI_BUS.Slave spi ,
AXI_BUS.Slave ethernet ,
AXI_BUS.Slave timer ,
output logic [(ariane_soc::NumHarts)-1:0][1:0] irq_o ,
output logic [(ariane_soc::NumHarts)-1:0][1:0] irq_o,
// UART
input logic rx_i ,
output logic tx_o ,
Expand Down Expand Up @@ -167,7 +167,7 @@ module ariane_peripherals #(

plic_top #(
.N_SOURCE ( ariane_soc::NumSources ),
.N_TARGET ( (ariane_soc::NumTargets)*(ariane_soc::NumHarts) ),
.N_TARGET ( (ariane_soc::NumTargets)*(ariane_soc::NumHarts) ),
.MAX_PRIO ( ariane_soc::MaxPriority ),
.reg_req_t ( plic_req_t ),
.reg_rsp_t ( plic_rsp_t )
Expand Down
12 changes: 4 additions & 8 deletions corev_apu/tb/ariane_testharness.sv
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Expand Up @@ -33,15 +33,11 @@ module ariane_testharness #(
output logic [31:0] exit_o
);

//localparam int unsigned NumHarts = 2;
/*localparam [7:0] hart_id0 = '0;
localparam [7:0] hart_id1 = 8'b1;*/

// disable test-enable
logic test_en;
logic ndmreset;
logic ndmreset_n;
logic [(ariane_soc::NumHarts-1):0] debug_req_core;
logic [(ariane_soc::NumHarts-1):0] debug_req_core;

int jtag_enable;
logic init_done;
Expand Down Expand Up @@ -399,7 +395,7 @@ module ariane_testharness #(
.AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH ),
.AXI_MAX_WRITE_TXNS ( 1 ),
.AXI_MAX_READ_TXNS ( 1 ),
.AXI_MAX_READ_TXNS ( 1 ),
.RISCV_WORD_WIDTH ( 64 )
) i_axi_riscv_atomics (
.clk_i,
Expand Down Expand Up @@ -527,8 +523,8 @@ module ariane_testharness #(
// ---------------
// CLINT
// ---------------
logic [ (ariane_soc::NumHarts-1) : 0] ipi;
logic [ (ariane_soc::NumHarts-1) : 0] timer_irq;
logic [(ariane_soc::NumHarts-1):0] ipi;
logic [(ariane_soc::NumHarts-1):0] timer_irq;

ariane_axi_soc::req_slv_t axi_clint_req;
ariane_axi_soc::resp_slv_t axi_clint_resp;
Expand Down

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