diff --git a/.bender.yml b/.bender.yml new file mode 100644 index 00000000..c8da405e --- /dev/null +++ b/.bender.yml @@ -0,0 +1,4 @@ +overrides: + gpio: { path: "hw/vendored_ips/gpio" } # Override to use the vendored in copy of + # the GPIO repo to allow reconfiguration + # of the number of GPIO pads. diff --git a/.github/workflows/gitlab-ci.yml b/.github/workflows/gitlab-ci.yml new file mode 100644 index 00000000..15b77c9a --- /dev/null +++ b/.github/workflows/gitlab-ci.yml @@ -0,0 +1,25 @@ +# Copyright 2024 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +# Some CI tests run on our GitLab servers due to licenses and tools +name: gitlab-ci +on: [push, pull_request, workflow_dispatch] +jobs: + gitlab-ci: + name: Internal Gitlab CI + runs-on: ubuntu-22.04 + steps: + - name: Check Gitlab CI + uses: pulp-platform/pulp-actions/gitlab-ci@v2.2.0 + # Skip on forks or pull requests from forks due to missing secrets. + if: + github.repository == 'pulp-platform/pulpissimo' && (github.event_name != 'pull_request' || github.event.pull_request.head.repo.full_name == github.repository) + with: + domain: iis-git.ee.ethz.ch + repo: github-mirror/pulpissimo + token: ${{ secrets.GITLAB_TOKEN }} + poll-period: 20 + poll-count: 1000 + retry-count: 100 + retry-period: 50 diff --git a/.gitignore b/.gitignore index 81234310..fa790fb6 100644 --- a/.gitignore +++ b/.gitignore @@ -3,7 +3,10 @@ xcelium.d/ xrun.history xrun.log .bender -bender +/utils/bin/bender work/ compile.tcl working_dir/ +/utils/bin/padrick +/Bender.local +/build diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 81946bef..e028726c 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -12,7 +12,13 @@ # See the License for the specific language governing permissions and # limitations under the License. - +variables: + GIT_SUBMODULE_STRATEGY: recursive + QUESTA: "questa-2023.4-zr" + VSIM: "$QUESTA vsim" + VSIM_BIN: "$QUESTA vsim" + RISCV: "/usr/pack/riscv-1.0-kgf/pulp-gcc-2.5.0" + PULP_RISCV_GCC_TOOLCHAIN: "/usr/pack/riscv-1.0-kgf/pulp-gcc-2.5.0" before_script: - pwd @@ -26,40 +32,16 @@ stages: - test - sim_questa_multivers -fetch_tests: - stage: fetch - script: - - echo "Fetching tests" - - make test-checkout-gitlab - artifacts: - name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA" - paths: - - tests/* - fetch_ips_bender: stage: fetch script: - echo "Fetching IPs using bender" - - ulimit -Sn 4096 - - BENDER=1 make checkout + - make checkout artifacts: name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA" paths: - # - .bender/* - #- Bender.lock - - bender - - -# This jobs result is too large to produce an artifact -# fetch_sdk: -# stage: fetch -# script: -# - echo "Fetching SDK from releases and setting up paths" -# - make sdk-gitlab -# artifacts: -# paths: -# - pkg/ -# - env/ + - .bender/* + - utils/bin/bender build_rtl: stage: build @@ -68,30 +50,26 @@ build_rtl: - echo "Compiling RTL model and DPI libraries" - make build - echo "Fetching VIPs" - - ./rtl/vip/get-vips.sh --yes --gitlab - - echo "Installing scripts" - - make install + - ./target/sim/vip/get-vips.sh --yes # --gitlab artifacts: name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA" paths: - - tests/* -# - sim/* - - rtl/tb/remote_bitbang/* # we want to reuse bitbang lib - - rtl/vip/* -# - pkg/* # sdk is too large + - target/sim/tb/tb_lib/remote_bitbang/* # we want to reuse bitbang lib + - target/sim/vip/* + - build/questasim/* lint: stage: test script: - echo "Running Spyglass Lint in rtl_handoff methodology with goal lint_rtl" - - make lint + - make lint_rtl artifacts: name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA" paths: - - spyglass/working_dir/* + - build/spyglass/working_dir/* reports: - junit: spyglass/working_dir/reports/lint_rtl.report.xml + junit: build/spyglass/working_dir/reports/lint_rtl.report.xml dependencies: - fetch_ips_bender needs: @@ -101,376 +79,228 @@ lint: # Use sdk-releases to run all tests test_sequential_bare: stage: test - before_script: - - echo "Fetching SDK from releases and setting up paths" - - make sdk-gitlab - - echo "Compiling RTL model and DPI libraries" - - make build - - echo "Installing scripts" - - make install + needs: [ build_rtl ] + parallel: + matrix: + - { TEST: dct } + - { TEST: fft2 } + - { TEST: rijndael } + - { TEST: jacobi-2d-imper } + - { TEST: bitDescriptor } + - { TEST: stencil_vect } + - { TEST: keccak } + - { TEST: fir } + - { TEST: stencil } + - { TEST: ipm } + - { TEST: towerofhanoi } + - { TEST: crc32 } + - { TEST: conv2d } + - { TEST: seidel } + - { TEST: fibonacci } + - { TEST: gauss-2d } + - { TEST: aes_cbc } + - { TEST: bubblesort } + - { TEST: fdtd-1d } + - { TEST: jacobi-1d-imper } + - { TEST: fft } script: - echo "Running sequential bare tests" - - source env/ci-pulpissimo.sh && make test-sequential-bare - - echo "Generating junit test results" - - /usr/sepp/bin/python3.4 -m junit2htmlreport tests/sequential_bare_tests/junit-reports/TEST-*.xml - artifacts: - name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA" - paths: - - tests/sequential_bare_tests/junit-reports/TEST-*.html - - tests/sequential_bare_tests/junit-reports/TEST-*.xml - reports: - junit: tests/sequential_bare_tests/junit-reports/TEST-*.xml - -# test_parallel_bare: -# stage: test -# before_script: -# - echo "Fetching SDK from releases and setting up paths" -# - make sdk-gitlab -# - echo "Compiling RTL model and DPI libraries" -# - make build -# - echo "Installing scripts" -# - make install -# script: -# - echo "Running parallel bare tests" -# - source env/ci-pulpissimo.sh && make test-parallel-bare -# - echo "Generating junit test results" -# - /usr/sepp/bin/python3.4 -m junit2htmlreport tests/parallel_bare_tests/junit-reports/TEST-*.xml -# artifacts: -# name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA" -# paths: -# - tests/parallel_bare_tests/junit-reports/TEST-*.html -# - tests/parallel_bare_tests/junit-reports/TEST-*.xml -# reports: -# junit: tests/parallel_bare_tests/junit-reports/TEST-*.xml - -# test_pulp: -# stage: test -# before_script: -# - echo "Fetching SDK from releases and setting up paths" -# - make sdk-gitlab -# - echo "Compiling RTL model and DPI libraries" -# - make scripts-bender-vsim-vips -# - make build -# - echo "Installing scripts" -# - make install -# script: -# - echo "Running pulp tests" -# - source env/ci-pulpissimo.sh && make test-pulp -# - echo "Generating junit test results" -# - /usr/sepp/bin/python3.4 -m junit2htmlreport tests/pulp_tests/junit-reports/TEST-*.xml -# artifacts: -# name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA" -# paths: -# - tests/pulp_tests/junit-reports/TEST-*.html -# - tests/pulp_tests/junit-reports/TEST-*.xml -# reports: -# junit: tests/pulp_tests/junit-reports/TEST-*.xml - -test_ml: - stage: test - before_script: - - echo "Fetching SDK from releases and setting up paths" - - make sdk-gitlab - - echo "Compiling RTL model and DPI libraries" - - make build - - echo "Installing scripts" - - make install - script: - - echo "Running ml tests" - - source env/ci-pulpissimo.sh && make test-ml - - echo "Generating junit test results" - - /usr/sepp/bin/python3.4 -m junit2htmlreport tests/ml_tests/junit-reports/TEST-*.xml - artifacts: - name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA" - paths: - - tests/ml_tests/junit-reports/TEST-*.html - - tests/ml_tests/junit-reports/TEST-*.xml - reports: - junit: tests/ml_tests/junit-reports/TEST-*.xml + - make relink + - source sw/pulp-runtime/configs/pulpissimo_cv32.sh + - export VSIM_PATH=$PWD/build/questasim + - cd sw/regression_tests/sequential_bare_tests/${TEST} + - make clean all run test_riscv: stage: test - before_script: - - echo "Fetching SDK from releases and setting up paths" - - make sdk-gitlab - - echo "Compiling RTL model and DPI libraries" - - make build - - echo "Installing scripts" - - make install + needs: [ build_rtl ] + parallel: + matrix: + - { TEST: testBitManipulation } + - { TEST: testVecCmp } + - { TEST: testAddSubNorm } + - { TEST: testMisaligned } + - { TEST: testALU } + - { TEST: testMAC3 } + - { TEST: testVecArith } + - { TEST: testDotMul } + - { TEST: testVecLogic } + # - { TEST: testComplex } + - { TEST: testCnt } + - { TEST: testVecRelat } + - { TEST: testShufflePack } + - { TEST: testMUL } + - { TEST: testHWLP } + - { TEST: testMacNorm } + # - { TEST: testDivRem } + - { TEST: testVariadic } + - { TEST: testMAC } + - { TEST: testLoadStore } + - { TEST: testALUExt } + - { TEST: testBuiltins } script: - echo "Running riscv tests" - - source env/ci-pulpissimo.sh && make test-riscv - - echo "Generating junit test results" - - /usr/sepp/bin/python3.4 -m junit2htmlreport tests/riscv_tests/junit-reports/TEST-*.xml - artifacts: - name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA" - paths: - - tests/riscv_tests/junit-reports/TEST-*.html - - tests/riscv_tests/junit-reports/TEST-*.xml - reports: - junit: tests/riscv_tests/junit-reports/TEST-*.xml + - source sw/pulp-runtime/configs/pulpissimo_cv32.sh + - export VSIM_PATH=$PWD/build/questasim + - cd sw/regression_tests/riscv_tests/${TEST} + - make clean all run freertos_helloworld: stage: test before_script: - - export RISCV=/usr/pack/riscv-1.0-kgf/pulp-gcc-2.5.0 - - git clone https://github.com/pulp-platform/pulp-freertos.git - - cd pulp-freertos + - git clone https://github.com/pulp-platform/pulp-freertos.git sw/pulp-freertos + - cd sw/pulp-freertos - git checkout d6966cae9471b7a592bd09b7acfd5b832666e3b5 - git submodule update --init --recursive - - cd .. + - cd ../.. script: - make scripts - make clean build - - source setup/vsim.sh - - cd pulp-freertos + - export VSIM_PATH=$PWD/build/questasim + - cd sw/pulp-freertos - source env/pulpissimo-cv32e40p.sh - cd tests/hello_world_pmsis - - make all run - -# test_rt: -# stage: test -# before_script: -# - echo "Fetching SDK from releases and setting up paths" -# - make sdk-gitlab -# - echo "Compiling RTL model and DPI libraries" -# - make scripts-bender-vsim-vips -# - make build -# - echo "Installing scripts" -# - make install -# script: -# - echo "Running rt tests" -# - source env/ci-pulpissimo.sh && make test-rt -# - echo "Generating junit test results" -# - /usr/sepp/bin/python3.4 -m junit2htmlreport tests/rt-tests/junit-reports/TEST-*.xml -# artifacts: -# name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA" -# paths: -# - tests/rt-tests/junit-reports/TEST-*.html -# - tests/rt-tests/junit-reports/TEST-*.xml -# reports: -# junit: tests/rt-tests/junit-reports/TEST-*.xml - -# Use simplified pulp-runtime to run a subset of tests -# test_simplified_sw: -# stage: test -# before_script: -# - echo "Fetching Runtime" -# - make pulp-runtime -# - echo "Compiling RTL model and DPI libraries" -# - make build -# - echo "Installing scripts" -# - make install -# script: -# - echo "Running software test" -# - source pulp-runtime/configs/pulpissimo.sh && make test-runtime-gitlab -# - echo "Generating junit test results" -# - /usr/sepp/bin/python3.4 -m junit2htmlreport tests/rt-tests/junit-reports/TEST-*.xml -# artifacts: -# name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA" -# paths: -# - tests/*.html -# - tests/*.xml -# reports: -# junit: tests/*.xml - -# Built SDK with the `make sdk` target and run all tests -# test_sw_build_sdk: -# variables: -# PULP_RISCV_GCC_TOOLCHAIN: your-compiler-path -# stage: test -# before_script: -# - echo "Compiling RTL model and DPI libraries" -# - make build -# - echo "Installing scripts" # don't call this, breaks build -# - make install -# - echo "Building SDK" -# - make sdk -# script: -# - echo "Running software tests with built SDK" -# - make test-gitlab2 -# - echo "Generating junit test results" -# - /usr/sepp/bin/python3.4 -m junit2htmlreport tests/junit-reports/TEST-*.xml -# artifacts: -# paths: -# - tests/junit-reports/TEST-*.html -# - tests/junit-reports/TEST-*.xml -# reports: -# junit: tests/junit-reports/TEST-*.xml + - $QUESTA make all run test_dm: stage: test before_script: + - source sw/pulp-runtime/configs/pulpissimo_cv32.sh + - make -C sw/regression_tests/hello clean all script: - echo "(Re)generating scripts with DPI disabled" - make scripts - echo "Setting up vsim path" - - source setup/vsim.sh + - export VSIM_PATH=$PWD/build/questasim - echo "Running debug module testbench" # Note that the program is irrelevant we just put something for it to not complain - - cd sim/ && make all simc VSIM_FLAGS="+jtag_dm_tests +srec=../rtl/tb/srec/min.srec" + - riscv make build run_sim VSIM_USER_PLUSARGS="+jtag_dm_tests +srec_ignore_checksum" EXECUTABLE_PATH=sw/regression_tests/hello/build/test/test fpga_synth_genesys2: stage: test before_script: script: - - echo "(Re)generating scripts" - - make scripts - echo "Starting synthesis with vivado" - - cd fpga/ && make genesys2 VIVADO='vivado-2019.1.1 vivado' + - make genesys2 VIVADO='vitis-2022.1 vivado' artifacts: name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA" paths: - - fpga/pulpissimo_genesys2.bit - - fpga/pulpissimo_genesys2.bin - - fpga/*.jou - - fpga/*.log - - fpga/*.str - - fpga/pulpissimo-genesys2/reports - - fpga/pulpissimo-genesys2/rtl - - fpga/pulpissimo-genesys2/tcl - - fpga/pulpissimo-genesys2/pulpissimo_genesys2.xpr - - fpga/pulpissimo-genesys2/fpga-settings.mk - - fpga/pulpissimo-genesys2/*.log - - fpga/pulpissimo-genesys2/*.cfg - - fpga/pulpissimo-genesys2/*.gdb - - fpga/pulpissimo-genesys2/*.jou - - fpga/pulpissimo-genesys2/*.log + - target/fpga/pulpissimo_genesys2.bit + - target/fpga/pulpissimo_genesys2.bin + - target/fpga/*.jou + - target/fpga/*.log + - target/fpga/*.str + - target/fpga/pulpissimo-genesys2/reports + - target/fpga/pulpissimo-genesys2/rtl + - target/fpga/pulpissimo-genesys2/tcl + - target/fpga/pulpissimo-genesys2/pulpissimo-genesys2.xpr + - target/fpga/pulpissimo-genesys2/fpga-settings.mk + - target/fpga/pulpissimo-genesys2/*.log + - target/fpga/pulpissimo-genesys2/*.cfg + - target/fpga/pulpissimo-genesys2/*.gdb + - target/fpga/pulpissimo-genesys2/*.jou + - target/fpga/pulpissimo-genesys2/*.log fpga_synth_nexys_video: stage: test before_script: script: - - echo "(Re)generating scripts" - - make scripts - echo "Starting synthesis with vivado" - - cd fpga/ && make nexys_video VIVADO='vivado-2019.1.1 vivado' + - make nexys_video VIVADO='vitis-2022.1 vivado' artifacts: name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA" paths: - - fpga/pulpissimo_nexys_video.bit - - fpga/pulpissimo_nexys_video.bin - - fpga/*.jou - - fpga/*.log - - fpga/*.str - - fpga/pulpissimo-nexys_video/reports - - fpga/pulpissimo-nexys_video/rtl - - fpga/pulpissimo-nexys_video/tcl - - fpga/pulpissimo-nexys_video/pulpissimo_nexys_video.xpr - - fpga/pulpissimo-nexys_video/fpga-settings.mk - - fpga/pulpissimo-nexys_video/*.log - - fpga/pulpissimo-nexys_video/*.cfg - - fpga/pulpissimo-nexys_video/*.gdb - - fpga/pulpissimo-nexys_video/*.jou - - fpga/pulpissimo-nexys_video/*.log + - target/fpga/pulpissimo_nexys_video.bit + - target/fpga/pulpissimo_nexys_video.bin + - target/fpga/*.jou + - target/fpga/*.log + - target/fpga/*.str + - target/fpga/pulpissimo-nexys_video/reports + - target/fpga/pulpissimo-nexys_video/rtl + - target/fpga/pulpissimo-nexys_video/tcl + - target/fpga/pulpissimo-nexys_video/pulpissimo-nexys_video.xpr + - target/fpga/pulpissimo-nexys_video/fpga-settings.mk + - target/fpga/pulpissimo-nexys_video/*.log + - target/fpga/pulpissimo-nexys_video/*.cfg + - target/fpga/pulpissimo-nexys_video/*.gdb + - target/fpga/pulpissimo-nexys_video/*.jou + - target/fpga/pulpissimo-nexys_video/*.log fpga_synth_nexys: stage: test before_script: script: - - echo "(Re)generating scripts" - - make scripts - echo "Starting synthesis with vivado" - - cd fpga/ && make nexys rev=nexys4 VIVADO='vivado-2019.1.1 vivado' + - make nexys rev=nexys4 VIVADO='vitis-2022.1 vivado' artifacts: name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA" paths: - - fpga/pulpissimo_nexys.bit - - fpga/pulpissimo_nexys.bin - - fpga/*.jou - - fpga/*.log - - fpga/*.str - - fpga/pulpissimo-nexys/reports - - fpga/pulpissimo-nexys/rtl - - fpga/pulpissimo-nexys/tcl - - fpga/pulpissimo-nexys/pulpissimo_nexys.xpr - - fpga/pulpissimo-nexys/fpga-settings.mk - - fpga/pulpissimo-nexys/*.log - - fpga/pulpissimo-nexys/*.cfg - - fpga/pulpissimo-nexys/*.gdb - - fpga/pulpissimo-nexys/*.jou - - fpga/pulpissimo-nexys/*.log + - target/fpga/pulpissimo_nexys.bit + - target/fpga/pulpissimo_nexys.bin + - target/fpga/*.jou + - target/fpga/*.log + - target/fpga/*.str + - target/fpga/pulpissimo-nexys/reports + - target/fpga/pulpissimo-nexys/rtl + - target/fpga/pulpissimo-nexys/tcl + - target/fpga/pulpissimo-nexys/pulpissimo-nexys.xpr + - target/fpga/pulpissimo-nexys/fpga-settings.mk + - target/fpga/pulpissimo-nexys/*.log + - target/fpga/pulpissimo-nexys/*.cfg + - target/fpga/pulpissimo-nexys/*.gdb + - target/fpga/pulpissimo-nexys/*.jou + - target/fpga/pulpissimo-nexys/*.log -fpga_synth_nexys_zcu104: +fpga_synth_zcu104: stage: test before_script: script: - - echo "(Re)generating scripts" - - make scripts - echo "Starting synthesis with vivado" - - cd fpga/ && make zcu104 VIVADO='vivado-2019.1.1 vivado' + - make zcu104 VIVADO='vitis-2023.2 vivado' artifacts: name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA" paths: - - fpga/pulpissimo_zcu104.bit - - fpga/pulpissimo_zcu104.bin - - fpga/*.jou - - fpga/*.log - - fpga/*.str - - fpga/pulpissimo-zcu104/reports - - fpga/pulpissimo-zcu104/rtl - - fpga/pulpissimo-zcu104/tcl - - fpga/pulpissimo-zcu104/pulpissimo_zcu104.xpr - - fpga/pulpissimo-zcu104/fpga-settings.mk - - fpga/pulpissimo-zcu104/*.log - - fpga/pulpissimo-zcu104/*.cfg - - fpga/pulpissimo-zcu104/*.gdb - - fpga/pulpissimo-zcu104/*.jou - - fpga/pulpissimo-zcu104/*.log - -# fpga_synth_zedboard: -# stage: test -# before_script: -# script: -# - echo "(Re)generating scripts" -# - make scripts -# - echo "Starting synthesis with vivado" -# - cd fpga/ && make zedboard VIVADO='vivado-2019.1.1 vivado' -# artifacts: -# name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA" -# paths: -# - fpga/pulpissimo_zedboard.bit -# - fpga/pulpissimo_zedboard.bin -# - fpga/*.jou -# - fpga/*.log -# - fpga/*.str -# - fpga/pulpissimo-zedboard/reports -# - fpga/pulpissimo-zedboard/rtl -# - fpga/pulpissimo-zedboard/tcl -# - fpga/pulpissimo-zedboard/pulpissimo_zedboard.xpr -# - fpga/pulpissimo-zedboard/fpga-settings.mk -# - fpga/pulpissimo-zedboard/*.log -# - fpga/pulpissimo-zedboard/*.cfg -# - fpga/pulpissimo-zedboard/*.gdb -# - fpga/pulpissimo-zedboard/*.jou -# - fpga/pulpissimo-zedboard/*.log + - target/fpga/pulpissimo_zcu104.bit + - target/fpga/pulpissimo_zcu104.bin + - target/fpga/*.jou + - target/fpga/*.log + - target/fpga/*.str + - target/fpga/pulpissimo-zcu104/reports + - target/fpga/pulpissimo-zcu104/rtl + - target/fpga/pulpissimo-zcu104/tcl + - target/fpga/pulpissimo-zcu104/pulpissimo-zcu104.xpr + - target/fpga/pulpissimo-zcu104/fpga-settings.mk + - target/fpga/pulpissimo-zcu104/*.log + - target/fpga/pulpissimo-zcu104/*.cfg + - target/fpga/pulpissimo-zcu104/*.gdb + - target/fpga/pulpissimo-zcu104/*.jou + - target/fpga/pulpissimo-zcu104/*.log fpga_synth_zcu102: stage: test before_script: + timeout: 5 hours script: - - echo "(Re)generating scripts" - - make scripts - echo "Starting synthesis with vivado" - - cd fpga/ && make zcu102 VIVADO='vivado-2019.1.1 vivado' + - make zcu102 VIVADO='vitis-2020.2 vivado' artifacts: name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA" paths: - - fpga/pulpissimo_zcu102.bit - - fpga/pulpissimo_zcu102.bin - - fpga/*.jou - - fpga/*.log - - fpga/*.str - - fpga/pulpissimo-zcu102/reports - - fpga/pulpissimo-zcu102/rtl - - fpga/pulpissimo-zcu102/tcl - - fpga/pulpissimo-zcu102/pulpissimo_zcu102.xpr - - fpga/pulpissimo-zcu102/fpga-settings.mk - - fpga/pulpissimo-zcu102/*.log - - fpga/pulpissimo-zcu102/*.cfg - - fpga/pulpissimo-zcu102/*.gdb - - fpga/pulpissimo-zcu102/*.jou - - fpga/pulpissimo-zcu102/*.log + - target/fpga/pulpissimo_zcu102.bit + - target/fpga/pulpissimo_zcu102.bin + - target/fpga/*.jou + - target/fpga/*.log + - target/fpga/*.str + - target/fpga/pulpissimo-zcu102/reports + - target/fpga/pulpissimo-zcu102/rtl + - target/fpga/pulpissimo-zcu102/tcl + - target/fpga/pulpissimo-zcu102/pulpissimo-zcu102.xpr + - target/fpga/pulpissimo-zcu102/fpga-settings.mk + - target/fpga/pulpissimo-zcu102/*.log + - target/fpga/pulpissimo-zcu102/*.cfg + - target/fpga/pulpissimo-zcu102/*.gdb + - target/fpga/pulpissimo-zcu102/*.jou + - target/fpga/pulpissimo-zcu102/*.log sim_questa_multivers: stage: sim_questa_multivers @@ -481,37 +311,34 @@ sim_questa_multivers: - QUESTA_PREFIX: - 'vsim' # Default - 'questa-2019.3-kgf vsim' - - 'questa-2020.1-kgf vsim' - - 'questa-2021.1-bt vsim' # Has errors - - 'questa-2021.2-bt vsim' # Has errors - - 'vsim-10.0d-kgf' # Incompatible - - 'vsim-10.1c-kgf' # Incompatible - - 'vsim-10.2c-kgf' # Incompatible - - 'vsim-10.3a-kgf' # Incompatible - - 'vsim-10.3e-kgf' # Incompatible - - 'vsim-10.4c-kgf' # Incompatible - - 'vsim-10.5a-kgf' # Incompatible - - 'vsim-10.5c-kgf' - - 'vsim-10.6b-kgf' + # - 'questa-2020.1-kgf vsim' + # - 'questa-2021.1-bt vsim' # Has errors + # - 'questa-2021.2-bt vsim' # Has errors + - 'questa-2021.3-kgf vsim' + - 'questa-2022.3-bt vsim' + - 'questa-2023.4-zr vsim' + # - 'vsim-10.0d-kgf' # Incompatible + # - 'vsim-10.1c-kgf' # Incompatible + # - 'vsim-10.2c-kgf' # Incompatible + # - 'vsim-10.3a-kgf' # Incompatible + # - 'vsim-10.3e-kgf' # Incompatible + # - 'vsim-10.4c-kgf' # Incompatible + # - 'vsim-10.5a-kgf' # Incompatible + # - 'vsim-10.5c-kgf' + # - 'vsim-10.6b-kgf' - 'vsim-10.7b-kgf' - 'vsim-10.7e-kgf' before_script: - export VSIM="$QUESTA_PREFIX" - - export VLOG="${QUESTA_PREFIX/vsim/vlog}" - - export VOPT="${QUESTA_PREFIX/vsim/vopt}" - - export VLIB="${QUESTA_PREFIX/vsim/vlib}" - - export VMAP="${QUESTA_PREFIX/vsim/vmap}" - - export VCOM="${QUESTA_PREFIX/vsim/vcom}" - - export PULP_RISCV_GCC_TOOLCHAIN=/usr/pack/riscv-1.0-kgf/pulp-gcc-1.0.16 - - git clone https://github.com/pulp-platform/pulp-runtime.git -b v0.0.15 + - export VSIM_BIN="$QUESTA_PREFIX" - mkdir hello - printf "#include \nint main(){\n printf(\"Hello World\\\n\");\n return 0;\n}\n" > hello/hello.c - printf "PULP_APP = hello\nPULP_APP_FC_SRCS = hello.c\nPULP_APP_HOST_SRCS = hello.c\nPULP_CFLAGS = -O3 -g\n\ninclude \$(PULP_SDK_HOME)/install/rules/pulp_rt.mk\n" > hello/Makefile script: - make scripts - make clean build - - source setup/vsim.sh - - source pulp-runtime/configs/pulpissimo_cv32.sh + - export VSIM_PATH=$PWD/build/questasim + - source sw/pulp-runtime/configs/pulpissimo_cv32.sh - make -C hello clean all run dependencies: - fetch_ips_bender @@ -523,11 +350,14 @@ spi_boot: before_script: - git clone https://github.com/pulp-platform/pulp-runtime.git -b v0.0.15 - mkdir hello - - export PULP_RISCV_GCC_TOOLCHAIN=/usr/pack/riscv-1.0-kgf/pulp-gcc-2.5.0 - printf "#include \nint main(){\n printf(\"Hello World\\\n\");\n return 0;\n}\n" > hello/hello.c - printf "PULP_APP = hello\nPULP_APP_FC_SRCS = hello.c\nPULP_APP_HOST_SRCS = hello.c\nPULP_CFLAGS = -O3 -g\n\ninclude \$(PULP_SDK_HOME)/install/rules/pulp_rt.mk\n" > hello/Makefile script: - - make scripts-bender-vsim-vips all - - source setup/vsim.sh + - make clean build USE_VIPS=1 + - export VSIM_PATH=$PWD/build/questasim - source pulp-runtime/configs/pulpissimo_cv32.sh - - make -C hello clean all run bootmode=spi PULP_RUNTIME_GCC_TOOLCHAIN=/usr/pack/riscv-1.0-kgf/pulp-gcc-2.5.0 + - make -C hello clean all run bootmode=spi + dependencies: + - build_rtl + needs: + - build_rtl diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 00000000..45f992e1 --- /dev/null +++ b/.gitmodules @@ -0,0 +1,6 @@ +[submodule "pulp-runtime"] + path = sw/pulp-runtime + url = https://github.com/pulp-platform/pulp-runtime.git +[submodule "regression_tests"] + path = sw/regression_tests + url = https://github.com/pulp-platform/regression_tests.git diff --git a/Bender.lock b/Bender.lock index 011f3a59..2027f987 100644 --- a/Bender.lock +++ b/Bender.lock @@ -1,320 +1,330 @@ ---- packages: adv_dbg_if: revision: 19eeef8cae1cbec7413877b3f29fe0bd078748d7 version: 0.0.2 source: - Git: "https://github.com/pulp-platform/adv_dbg_if.git" + Git: https://github.com/pulp-platform/adv_dbg_if.git dependencies: [] apb: - revision: d077333a7e5cc80008935dc2761440532dfdce81 - version: 0.1.0 + revision: 77ddf073f194d44b9119949d2421be59789e69ae + version: 0.2.4 source: - Git: "https://github.com/pulp-platform/apb.git" - dependencies: [] + Git: https://github.com/pulp-platform/apb.git + dependencies: + - common_cells apb2per: revision: 6fc13fc0bfa71772d91391893e57306d0d95befa version: 0.1.0 source: - Git: "https://github.com/pulp-platform/apb2per.git" + Git: https://github.com/pulp-platform/apb2per.git dependencies: [] apb_adv_timer: revision: c8faec1e1755386d0e0f31a55ebd80612a3dcea9 version: 1.0.4 source: - Git: "https://github.com/pulp-platform/apb_adv_timer.git" + Git: https://github.com/pulp-platform/apb_adv_timer.git dependencies: - - tech_cells_generic + - tech_cells_generic apb_fll_if: - revision: a1f67b624fe379d4d319c809656b672f0267cfc8 - version: 0.1.3 + revision: ce34d65007e05da1f788fcdf7cc1849b5aedaf67 + version: 0.2.1 source: - Git: "https://github.com/pulp-platform/apb_fll_if.git" + Git: https://github.com/pulp-platform/apb_fll_if.git dependencies: - - apb - apb_gpio: - revision: 0e9f142f2f11278445c953ad011fce1c7ed85b66 - version: ~ - source: - Git: "https://github.com/pulp-platform/apb_gpio.git" - dependencies: [] + - apb apb_interrupt_cntrl: - revision: 86d650f590a385cc0d5148125528527377f0527c - version: 0.1.2 - source: - Git: "https://github.com/pulp-platform/apb_interrupt_cntrl.git" - dependencies: - - common_cells - apb_node: - revision: 4e350ef4980141397e3e17ced00e310e30f8dc95 - version: 0.1.1 + revision: 8faeac71f89bca19e5daa14ebac99a81ceb85593 + version: 0.2.0 source: - Git: "https://github.com/pulp-platform/apb_node.git" + Git: https://github.com/pulp-platform/apb_interrupt_cntrl.git dependencies: - - apb + - apb + - common_cells axi: - revision: 527cf64a95f7aea36836b2db76dc4d767e150358 - version: 0.29.2 - source: - Git: "https://github.com/pulp-platform/axi.git" - dependencies: - - common_cells - - common_verification - axi_slice: - revision: a4f72bc21ac4d7da631e8309d9f8d0c34b735c23 - version: 1.1.4 + revision: 9402c8a9ce0a7b5253c3c29e788612d771e8b5d6 + version: 0.39.3 source: - Git: "https://github.com/pulp-platform/axi_slice.git" + Git: https://github.com/pulp-platform/axi.git dependencies: - - common_cells + - common_cells + - common_verification + - tech_cells_generic cluster_interconnect: revision: 7d0a4f8acae71a583a6713cab5554e60b9bb8d27 version: 1.2.1 source: - Git: "https://github.com/pulp-platform/cluster_interconnect.git" + Git: https://github.com/pulp-platform/cluster_interconnect.git dependencies: - - common_cells + - common_cells common_cells: - revision: 88a08fd4e365ec258375a326c30c20726eaa4fa2 - version: 1.24.1 + revision: 0d67563b6b592549542544f1abc0f43e5d4ee8b4 + version: 1.35.0 source: - Git: "https://github.com/pulp-platform/common_cells.git" + Git: https://github.com/pulp-platform/common_cells.git dependencies: - - common_verification - - tech_cells_generic + - common_verification + - tech_cells_generic common_verification: - revision: b616c1a25aea3b76e32dcbed2ec87d057efdcffd - version: 0.2.1 + revision: 9c07fa860593b2caabd9b5681740c25fac04b878 + version: 0.2.3 source: - Git: "https://github.com/pulp-platform/common_verification.git" + Git: https://github.com/pulp-platform/common_verification.git dependencies: [] cv32e40p: - revision: 800a09d97a1e9418e127e8bbf1763c1d1097c92f - version: ~ + revision: 7a49867b2232d97344cde1b8a1e05bcb38634894 + version: null source: - Git: "https://github.com/pulp-platform/cv32e40p.git" + Git: https://github.com/pulp-platform/cv32e40p.git dependencies: - - common_cells - - fpnew - - tech_cells_generic + - common_cells + - fpnew + - tech_cells_generic fpnew: - revision: 8dc44406b1ccbc4487121710c1883e805f893965 - version: 0.6.6 + revision: a8e0cba6dd50f357ece73c2c955d96efc3c6c315 + version: null source: - Git: "https://github.com/pulp-platform/fpnew.git" + Git: https://github.com/pulp-platform/cvfpu.git dependencies: - - common_cells - - fpu_div_sqrt_mvp + - common_cells + - fpu_div_sqrt_mvp fpu_div_sqrt_mvp: revision: 86e1f558b3c95e91577c41b2fc452c86b04e85ac version: 1.0.4 source: - Git: "https://github.com/pulp-platform/fpu_div_sqrt_mvp.git" + Git: https://github.com/pulp-platform/fpu_div_sqrt_mvp.git dependencies: - - common_cells + - common_cells generic_fll: revision: 1c92dc73a940392182fd4cb7b86f35649b349595 - version: ~ + version: 0.2.0 source: - Git: "https://github.com/pulp-platform/generic_FLL.git" + Git: https://github.com/pulp-platform/generic_FLL.git dependencies: [] + gpio: + revision: null + version: null + source: + Path: hw/vendored_ips/gpio + dependencies: + - apb + - axi + - common_cells + - common_verification + - register_interface + - tech_cells_generic hwpe-ctrl: - revision: 4bf1487a463c262bf7d8ffee79d1cf392937daa2 - version: 1.7.1 + revision: 1916c72f024175f1fe351acc3db3c6e9925a117d + version: 1.7.3 source: - Git: "https://github.com/pulp-platform/hwpe-ctrl.git" + Git: https://github.com/pulp-platform/hwpe-ctrl.git dependencies: - - tech_cells_generic + - tech_cells_generic hwpe-mac-engine: revision: cd48c574f1972ecbe02d3f463a0e12a92acde484 version: 1.3.3 source: - Git: "https://github.com/pulp-platform/hwpe-mac-engine.git" + Git: https://github.com/pulp-platform/hwpe-mac-engine.git dependencies: - - hwpe-ctrl - - hwpe-stream + - hwpe-ctrl + - hwpe-stream hwpe-stream: - revision: ddc154424187dff42a8fcec946c768ceb13f13de - version: 1.6.4 + revision: 65c99a4a2f37a79acee800ab0151f67dfb1edef1 + version: 1.8.0 source: - Git: "https://github.com/pulp-platform/hwpe-stream.git" + Git: https://github.com/pulp-platform/hwpe-stream.git dependencies: - - tech_cells_generic + - tech_cells_generic ibex: revision: b18f7ef178ed07f5085051f96042c670a919fd5c - version: ~ + version: null source: - Git: "https://github.com/pulp-platform/ibex.git" + Git: https://github.com/pulp-platform/ibex.git dependencies: - - tech_cells_generic + - tech_cells_generic jtag_pulp: revision: d22e828aef0484c79355d97d12de044c97e1f20f version: 0.2.0 source: - Git: "https://github.com/pulp-platform/jtag_pulp.git" + Git: https://github.com/pulp-platform/jtag_pulp.git dependencies: [] - l2_tcdm_hybrid_interco: - revision: fa55e72859dcfb117a2788a77352193bef94ff2b - version: 1.0.0 + pulp_io: + revision: da6f8817b667f17973ecb19cb1e7aa4347108716 + version: 0.1.0 source: - Git: "https://github.com/pulp-platform/L2_tcdm_hybrid_interco.git" - dependencies: [] + Git: https://github.com/pulp-platform/pulp-io.git + dependencies: + - apb + - common_cells + - gpio + - udma_camera + - udma_core + - udma_filter + - udma_hyper + - udma_i2c + - udma_i2s + - udma_qspi + - udma_sdio + - udma_uart pulp_soc: - revision: 0573a85c8ec502ff5e3ef06946a75eaf567ce16a - version: 4.4.0 + revision: bf65372aab4edd404160170e2a4d2c63b27ab5f2 + version: 5.0.1 + source: + Git: https://github.com/pulp-platform/pulp_soc.git + dependencies: + - adv_dbg_if + - apb + - apb2per + - apb_adv_timer + - apb_interrupt_cntrl + - axi + - cluster_interconnect + - common_cells + - cv32e40p + - fpnew + - hwpe-mac-engine + - ibex + - jtag_pulp + - pulp_io + - register_interface + - riscv-dbg + - scm + - tech_cells_generic + - timer_unit + pulpissimo_optional_vips: + revision: null + version: null + source: + Path: target/sim/vip + dependencies: [] + pulpissimo_padframe_fpga: + revision: null + version: null + source: + Path: hw/padframe/pulpissimo_padframe_fpga_autogen + dependencies: + - common_cells + - register_interface + pulpissimo_padframe_rtl_sim: + revision: null + version: null source: - Git: "https://github.com/pulp-platform/pulp_soc.git" + Path: hw/padframe/pulpissimo_padframe_rtl_sim_autogen dependencies: - - adv_dbg_if - - apb - - apb2per - - apb_adv_timer - - apb_fll_if - - apb_gpio - - apb_interrupt_cntrl - - apb_node - - axi - - axi_slice - - cluster_interconnect - - common_cells - - cv32e40p - - fpnew - - generic_fll - - hwpe-mac-engine - - ibex - - jtag_pulp - - l2_tcdm_hybrid_interco - - register_interface - - riscv-dbg - - scm - - tech_cells_generic - - timer_unit - - udma_camera - - udma_core - - udma_external_per - - udma_filter - - udma_hyper - - udma_i2c - - udma_i2s - - udma_qspi - - udma_sdio - - udma_uart + - common_cells + - register_interface register_interface: - revision: e32e6fde632f3cd21861b2ce47045a8bacb5216f - version: 0.3.2 + revision: ae616e5a1ec2b41e72d200e5ab09c65e94aebd3d + version: 0.4.4 source: - Git: "https://github.com/pulp-platform/register_interface.git" + Git: https://github.com/pulp-platform/register_interface.git dependencies: - - axi - - common_cells + - apb + - axi + - common_cells + - common_verification riscv-dbg: revision: 69be5ddc03ea1688c0eab47d6ed9d0e8725beda1 version: 0.5.1 source: - Git: "https://github.com/pulp-platform/riscv-dbg.git" + Git: https://github.com/pulp-platform/riscv-dbg.git dependencies: - - common_cells - - tech_cells_generic + - common_cells + - tech_cells_generic scm: - revision: e1ad7dffd9d8702430131ec8bc1a0d9ff686ece2 - version: 1.1.0 + revision: 998466d2a3c2d7d572e43d2666d93c4f767d8d60 + version: 1.1.1 source: - Git: "https://github.com/pulp-platform/scm.git" + Git: https://github.com/pulp-platform/scm.git dependencies: [] tbtools: revision: 4bc2c825df8540a0c0210ab7f484533809801fa2 version: 0.2.1 source: - Git: "https://github.com/pulp-platform/tbtools.git" + Git: https://github.com/pulp-platform/tbtools.git dependencies: [] tech_cells_generic: - revision: e6226a6f374eb88fed84d4989bb3f066cb470f33 - version: 0.2.9 + revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf + version: 0.2.13 source: - Git: "https://github.com/pulp-platform/tech_cells_generic.git" + Git: https://github.com/pulp-platform/tech_cells_generic.git dependencies: - - common_verification + - common_verification timer_unit: - revision: 3f4ee3e5b3875a473242de5d0c3ebb5a0fe4b8db - version: 1.0.2 + revision: 4c69615c89db9397a9747d6f6d6a36727854f0bc + version: 1.0.3 source: - Git: "https://github.com/pulp-platform/timer_unit.git" + Git: https://github.com/pulp-platform/timer_unit.git dependencies: [] udma_camera: - revision: cfcd80416ef18f8e8139188b8dfa52a8a7f6f7c8 - version: 1.1.2 + revision: cb4dc897125c823e646f65a9d155e832c763b29d + version: 2.0.0 source: - Git: "https://github.com/pulp-platform/udma_camera.git" + Git: https://github.com/pulp-platform/udma_camera.git dependencies: - - tech_cells_generic - - udma_core + - tech_cells_generic + - udma_core udma_core: - revision: 7af2db5ea8cee3ecfe8e0e647bbdbc7f58ecb73b - version: 1.1.2 - source: - Git: "https://github.com/pulp-platform/udma_core.git" - dependencies: - - common_cells - - tech_cells_generic - udma_external_per: - revision: 8674ecd131a173915a69ee9e4a04edf8745cbcf4 - version: 1.0.4 + revision: 32bcc4f7472c3eeb8ef04612deb9088ffce7eb59 + version: 2.0.0 source: - Git: "https://github.com/pulp-platform/udma_external_per.git" + Git: https://github.com/pulp-platform/udma_core.git dependencies: - - udma_core + - common_cells + - tech_cells_generic udma_filter: - revision: a11e2057e7b21852e978b744714c384de49228cf - version: 1.0.3 + revision: b346c42543fbff5f4146eb8d56c7cb3dd55b19f4 + version: 2.0.0 source: - Git: "https://github.com/pulp-platform/udma_filter.git" + Git: https://github.com/pulp-platform/udma_filter.git dependencies: - - udma_core + - udma_core udma_hyper: - revision: 83ab704f9d1c5f9e5353268c901fe95c36bcea36 - version: ~ + revision: bd41ed10f94621a13ff02bdd631bf64c838a10d4 + version: 0.1.0 source: - Git: "https://github.com/pulp-platform/udma_hyper.git" - dependencies: [] + Git: https://github.com/pulp-platform/udma_hyper.git + dependencies: + - tech_cells_generic + - udma_core udma_i2c: - revision: 47d6892e38eb0e45692c81a5f47d71945098ffa0 - version: 2.0.0 + revision: d0852881b90b9bf10d51409def6d9abf58d46b6a + version: 3.0.0 source: - Git: "https://github.com/pulp-platform/udma_i2c.git" + Git: https://github.com/pulp-platform/udma_i2c.git dependencies: - - udma_core + - udma_core udma_i2s: - revision: f63cb528dbff7d580c87fd4de90dbdf0ab69048e - version: 1.1.2 + revision: aa3e698a56824493da3b9334f7236cc7f85699de + version: 2.0.0 source: - Git: "https://github.com/pulp-platform/udma_i2s.git" + Git: https://github.com/pulp-platform/udma_i2s.git dependencies: - - common_cells - - tech_cells_generic - - udma_core + - common_cells + - tech_cells_generic + - udma_core udma_qspi: - revision: ddbe8a2e530a5edafc93fe1a25f47fb4b8716bd8 - version: 1.0.4 + revision: 505b9d37ba7666962450ea8a45d6abb7b1c4fc03 + version: 2.0.0 source: - Git: "https://github.com/pulp-platform/udma_qspi.git" + Git: https://github.com/pulp-platform/udma_qspi.git dependencies: - - common_cells - - tech_cells_generic - - udma_core + - common_cells + - tech_cells_generic + - udma_core udma_sdio: - revision: e768162ef48ad8fd873daa995ac51269fc82ec4f - version: 1.1.2 + revision: 892ac6f17bb9ad6ad223e27b75809c8163a71900 + version: 2.0.0 source: - Git: "https://github.com/pulp-platform/udma_sdio.git" + Git: https://github.com/pulp-platform/udma_sdio.git dependencies: - - common_cells - - tech_cells_generic - - udma_core + - common_cells + - tech_cells_generic + - udma_core udma_uart: - revision: 18ed1986fd62920b1065005c370fd740995cfd4a - version: 1.0.2 + revision: 15d36f5f1d4459da3fa458a1af3334f1a8447058 + version: 2.0.0 source: - Git: "https://github.com/pulp-platform/udma_uart.git" + Git: https://github.com/pulp-platform/udma_uart.git dependencies: - - common_cells - - udma_core + - common_cells + - udma_core diff --git a/Bender.yml b/Bender.yml index 47b74ff5..77782261 100644 --- a/Bender.yml +++ b/Bender.yml @@ -1,7 +1,8 @@ package: - name: Pulpissimo + name: pulpissimo authors: - "Robert Balas " + - "Manuel Eggimann " - "Pasquale Davide Schiavone " - "Germain Haugou " - "Francesco Conti " @@ -9,78 +10,80 @@ package: - "Stefan Mach " - "Antonio Pullini " - "Gianmarco Ottavi " - - "Manuel Eggimann " - "Luca Valente " dependencies: - common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } - jtag_pulp: { git: "https://github.com/pulp-platform/jtag_pulp.git", version: 0.2.0 } - pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", version: 4.4.0 } - tbtools: { git: "https://github.com/pulp-platform/tbtools.git", version: 0.2.1 } - tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } + common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } + apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } + jtag_pulp: { git: "https://github.com/pulp-platform/jtag_pulp.git", version: 0.2.0 } + pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", version: 5.0.1 } + tbtools: { git: "https://github.com/pulp-platform/tbtools.git", version: 0.2.1 } + tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } + pulpissimo_padframe_rtl_sim: { path: "hw/padframe/pulpissimo_padframe_rtl_sim_autogen" } + pulpissimo_padframe_fpga: { path: "hw/padframe/pulpissimo_padframe_fpga_autogen" } + register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.1 } + generic_FLL: { git: "https://github.com/pulp-platform/generic_FLL.git", version: 0.2.0 } + apb_fll_if: { git: "https://github.com/pulp-platform/apb_fll_if.git", version: 0.2.1 } + + + # Target Specific Dependencies + + + # Simulation Environment specific dependencies + pulpissimo_optional_vips: { path: "target/sim/vip"} -workspace: - # package_links: - # ips/tbtools: tbtools # symlinks for backwards compatibility with IPApprox -# checkout_dir: deps export_include_dirs: - - rtl/includes + - hw/includes +# The default flavor of PULPIssimo is the generic version for RTL simulation. +# For other target platforms, checkout the Bender.yml files in the various +# subdirectories bellow 'hw'. sources: # Source files grouped in levels. Files in level 0 have no dependencies on files in this # package. Files in level 1 only depend on files in level 0, files in level 2 on files in # levels 1 and 0, etc. Files within a level are ordered alphabetically. # Level 0 - - rtl/pulpissimo/jtag_tap_top.sv - - rtl/pulpissimo/pad_frame.sv - - rtl/pulpissimo/pad_control.sv - - rtl/pulpissimo/soc_domain.sv - - rtl/pulpissimo/rtc_date.sv - - rtl/pulpissimo/rtc_clock.sv - - rtl/pulpissimo/safe_domain_reg_if.sv - # Level 1 - - rtl/pulpissimo/safe_domain.sv - - rtl/pulpissimo/pulpissimo.sv - # TB sources - - target: any(test,simulation) + # Common RTL files + - target: not(any(fpga, xilinx)) files: - - rtl/tb/riscv_pkg.sv - - rtl/tb/jtag_pkg.sv - - rtl/tb/pulp_tap_pkg.sv - - rtl/tb/srec/srec_pkg.sv - - rtl/tb/tb_clk_gen.sv - - rtl/tb/tb_pulp.sv - - rtl/tb/SimJTAG.sv - - rtl/tb/SimDTM.sv + - hw/asic_autogen_rom.sv + - hw/soc_domain.sv + - hw/pulpissimo.sv - # Open models - - target: any(test,simulation) - files: - - rtl/vip/spi_master_padframe.sv - - rtl/vip/uart_sim.sv - - rtl/vip/camera/cam_vip.sv - # S25FS256_model (SPI Flash) - - target: all(any(test,simulation), flash_vip) - defines: - SPEEDSIM: ~ + # rtl_sim - Generic version of pulpissimo used for non-verilator RTL simulation + - target: all(rtl_sim, not(verilator)) files: - - rtl/vip/spi_flash/S25fs256s/model/s25fs256s.v + - hw/padframe/padframe_adapter.sv + - hw/clock_gen_generic.sv - # 24FC1025 model (I2C flash) - - target: all(any(test,simulation), i2c_vip) - defines: - SPEEDSIM: ~ + # rtl_sim - Generic version of pulpissimo used for non-verilator RTL simulation + - target: all(fpga, xilinx) files: - - rtl/vip/i2c_eeprom/24FC1025.v + - hw/fpga_autogen_rom.sv + - hw/padframe/padframe_adapter.sv + - hw/clock_gen_fpga.sv - # i2s model - - target: all(any(test,simulation), i2s_vip) - defines: - SPEEDSIM: ~ + - target: simulation files: - - rtl/vip/i2s/i2c_if.v - - rtl/vip/i2s/i2s_vip_channel.sv - - rtl/vip/i2s/i2s_vip.sv + - target/sim/tb/tb_lib/riscv_pkg.sv + - target/sim/tb/tb_lib/jtag_pkg.sv + - target/sim/tb/tb_lib/pulp_tap_pkg.sv + - target/sim/tb/tb_lib/srec/srec_pkg.sv + - target/sim/tb/tb_lib/tb_clk_gen.sv + - target/sim/tb/tb_lib/SimDTM.sv + - target/sim/tb/tb_lib/SimJTAG.sv + - target/sim/tb/tb_pulp.sv + - target/sim/tb/tb_pulp_simple.sv + + +vendor_package: + # Import the GPIO repository directly. Since we have to regenerate the RTL + # when we change the number GPIOs we cannot just depend on it as a regular + # dependency but actually need a modifyable copy in the source tree. + - name: gpio + target_dir: hw/vendored_ips/gpio + upstream: { git: "https://github.com/pulp-platform/gpio.git", rev: "7f5e7b50a3d275fcbdae156ed14b7236ad5d7c0b"} + patch_dir: hw/vendored_ips/patches/gpio diff --git a/CHANGELOG.md b/CHANGELOG.md index 6dd936cc..2606e721 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -7,7 +7,12 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 ## [Unreleased] ### Changed -- Default dependency management is now bender, no longer IPApproX. +- Default dependency management is now bender, IPApproX no longer supported. +- Reorganize folder structure +- Reorganize code structure for simpler design +- Integrate padrick generated padframe +- Update `pulp_soc` to v5.0.0, update various dependencies +- Clock generation now in top level, no longer in `pulp_soc` ### Fixed - fixed support for ibex core from top level diff --git a/Makefile b/Makefile index 8689fed1..bb73cea0 100644 --- a/Makefile +++ b/Makefile @@ -1,285 +1,69 @@ -# Copyright 2020 ETH Zurich and University of Bologna -# +# Copyright 2022 ETH Zurich and University of Bologna +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. +# +# Author: Manuel Eggimann -SHELL=bash - -CTAGS=ctags - -PKG_DIR ?= $(PWD)/install - -export VSIM_PATH=$(PKG_DIR) -export PULP_PATH=$(PWD) - -define declareInstallFile -$(VSIM_PATH)/$(1): sim/$(1) - install -v -D sim/$(1) $$@ - -INSTALL_HEADERS += $(VSIM_PATH)/$(1) -endef - -INSTALL_FILES += modelsim.ini -INSTALL_FILES += $(shell cd sim && find boot -type f) -INSTALL_FILES += $(shell cd sim && find tcl_files -type f) -INSTALL_FILES += $(shell cd sim && find waves -type f) -INSTALL_FILES += $(shell cd sim && find work -type f) -INSTALL_FILES += $(shell cd sim && find fs -type f) - -$(foreach file, $(INSTALL_FILES), $(eval $(call declareInstallFile,$(file)))) - -VLOG_ARGS += -suppress 2583 -suppress 13314 \"+incdir+\$$ROOT/rtl/includes\" -BENDER_SIM_BUILD_DIR = sim -BENDER_FPGA_SCRIPTS_DIR = fpga/pulpissimo/tcl/generated - -# make variables visible in submake -# don't export variable if undefined/empty -define export_if_def - ifneq ($(strip $(1)),) - export $(1) - endif -endef - -export VSIM_PATH - -$(export_if_def VSIM) -$(export_if_def VSIM_FLAGS) -$(export_if_def VLOG) -$(export_if_def VLOG_FLAGS) -$(export_if_def SIM_TOP) -$(export_if_def VERILATOR) -$(export_if_def QUESTA) - -.DEFAULT_GOAL := all - -.PHONY: all -## Checkout, generate scripts and build rtl -all: build - -.PHONY: checkout -## Checkout/update dependencies using IPApprox or Bender -checkout: bender - ./bender checkout - touch Bender.lock - $(MAKE) scripts - -Bender.lock: bender - ./bender checkout - touch Bender.lock - -# generic clean and build targets for the platform -.PHONY: clean -## Remove the RTL model files -clean: - rm -rf $(VSIM_PATH) - $(MAKE) -C sim clean - -.PHONY: scripts -## Generate scripts for all tools -scripts: scripts-bender-vsim scripts-bender-fpga - -scripts-bender-fpga: | Bender.lock - mkdir -p fpga/pulpissimo/tcl/generated - ./bender script vivado -t fpga -t xilinx > $(BENDER_FPGA_SCRIPTS_DIR)/compile.tcl - -scripts-bender-vsim: | Bender.lock - echo 'set ROOT [file normalize [file dirname [info script]]/..]' > $(BENDER_SIM_BUILD_DIR)/compile.tcl - ./bender script vsim \ - --vlog-arg="$(VLOG_ARGS)" --vcom-arg="" \ - -t rtl -t test \ - | grep -v "set ROOT" >> $(BENDER_SIM_BUILD_DIR)/compile.tcl - -scripts-bender-vsim-vips: | Bender.lock - echo 'set ROOT [file normalize [file dirname [info script]]/..]' > $(BENDER_SIM_BUILD_DIR)/compile.tcl - ./bender script vsim \ - --vlog-arg="$(VLOG_ARGS)" --vcom-arg="" \ - -t rtl -t test -t rt_dpi -t i2c_vip -t flash_vip -t i2s_vip -t use_vips \ - | grep -v "set ROOT" >> $(BENDER_SIM_BUILD_DIR)/compile.tcl - -$(BENDER_SIM_BUILD_DIR)/compile.tcl: Bender.lock - echo 'set ROOT [file normalize [file dirname [info script]]/..]' > $(BENDER_SIM_BUILD_DIR)/compile.tcl - ./bender script vsim \ - --vlog-arg="$(VLOG_ARGS)" --vcom-arg="" \ - -t rtl -t test \ - | grep -v "set ROOT" >> $(BENDER_SIM_BUILD_DIR)/compile.tcl - - -.PHONY: build -## Build the RTL model for vsim -build: $(BENDER_SIM_BUILD_DIR)/compile.tcl - @test -f Bender.lock || { echo "ERROR: Bender.lock file does not exist. Did you run make checkout in bender mode?"; exit 1; } - @test -f $(BENDER_SIM_BUILD_DIR)/compile.tcl || { echo "ERROR: sim/compile.tcl file does not exist. Did you run make scripts in bender mode?"; exit 1; } - cd sim && $(MAKE) all - - -# sdk specific targets -install: $(INSTALL_HEADERS) - - -.PHONY: import-bootcode -## Import the latest bootcode. This should not be called by the user. -import-bootcode: boot/boot_code_asic.cde - cp $^ sim/boot/boot_code.cde - -boot_code/boot_code_asic.cde: - $(MAKE) -C boot boot_code.cde - -check-env-pulp-gcc: -ifndef PULP_RISCV_GCC_TOOLCHAIN - $(error PULP_RISCV_GCC_TOOLCHAIN is undefined.\ - You need to set this environment variable to point \ - to your pulp gcc installation) -endif +mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST))) +current_dir := $(notdir $(patsubst %/,%,$(dir $(mkfile_path)))) +PULPISSIMO_ROOT=$(abspath $(current_dir)/..) -check-env-art: -ifndef PULP_ARTIFACTORY_USER - $(error PULP_ARTIFACTORY_USER is undefined.\ - You need to set this environment variable to username:password \ - to be able access the artifactory server to download the sdk) +ifneq (,$(wildcard /etc/iis.version)) + include $(PULPISSIMO_ROOT)/utils/iis-env.mk endif -## Build the pulp SDK from source -build-pulp-sdk: pulp-sdk -pulp-sdk: check-env-pulp-gcc - git clone https://github.com/pulp-platform/pulp-sdk.git -b 2019.12.06; \ - cd pulp-sdk; \ - source configs/pulpissimo.sh; \ - source configs/platform-rtl.sh; \ - make all env - -## Download the latest supported pulp sdk release -pulp-sdk-release: check-env-art sdk-gitlab +include target/sim/questasim/Makefile +include target/lint/spyglass/Makefile +include target/fpga/Makefile +include $(PULPISSIMO_ROOT)/utils/utils.mk -.PHONY: get-tests -## Download pulp tests for local machine. Same as test-checkout -get-tests: test-checkout - -## fetch sdk for local machine -get-sdk: sdk-gitlab - -# GITLAB CI -# continuous integration on gitlab -sdk-gitlab: pkg/sdk/2020.01.01 -pkg/sdk/2020.01.01: - sdk-releases/get-sdk-2020.01.01-CentOS_7.py - cd pkg; \ - for f in ../sdk-releases/patches/*.patch; do patch -p1 < "$$f"; done; \ - -# simplified runtime for PULP that doesn't need the sdk -pulp-runtime: - git clone https://github.com/pulp-platform/pulp-runtime.git -b v0.0.3 - -.PHONY: test-checkout -## Download pulp test for local machine. You need ssh access to the gitlab server. -test-checkout: - ./update-tests - -# the gitlab runner needs a special configuration to be able to access the -# dependent git repositories -.PHONY: test-checkout-gitlab -test-checkout-gitlab: - ./update-tests-gitlab - -# test with sdk release -.PHONY: test-gitlab -## Run tests on gitlab using the latest supported sdk release -test-gitlab: tests - cd tests && plptest --threads 16 --stdout - -.PHONY: test-sequential-bare -## Run only sequential_bare tests -test-sequential-bare: - cd tests/sequential_bare_tests && plptest --threads 32 --stdout - -.PHONY: test-parallel-bare -## Run only parallel_bare tests -test-parallel-bare: - cd tests/parallel_bare_tests && plptest --threads 32 --stdout - -.PHONY: test-pulp -## Run only pulp_tests tests -test-pulp: - cd tests/pulp_tests && plptest --threads 32 --stdout - -.PHONY: test-ml -## Run only ml_tests tests -test-ml: - cd tests/ml_tests && plptest --threads 32 --stdout +.PHONY: checkout +## Checkout all Bender IPs +checkout: $(PULPISSIMO_UTILS)/bender + $(PULPISSIMO_UTILS)/bender checkout -.PHONY: test-riscv -## Run only riscv_tests tests -test-riscv: - cd tests/riscv_tests && plptest --threads 32 --stdout +.PHONY: hw bootrom padframe +## Re-generate generated hardware IPs +hw: bootrom padframe -.PHONY: test-rt -## Run only rt_tests tests -test-rt: - cd tests/rt-tests && plptest --threads 32 --stdout +## Generate the boot rom +bootrom: hw/asic_autogen_rom.sv hw/fpga_autogen_rom.sv -.PHONY: test-runtime-gitlab -## Run simplified runtime tests on gitlab using the latest supported sdk release -test-runtime-gitlab: pulp-runtime - cd tests && ../pulp-runtime/scripts/bwruntests.py --proc-verbose -v \ - --report-junit -t 3600 --yaml \ - -o simplified-runtime.xml runtime-tests.yaml +## Generate the ASIC and simulation boot rom +hw/asic_autogen_rom.sv: + $(MAKE) -C sw/bootcode asic_autogen_rom.sv + cp sw/bootcode/asic_autogen_rom.sv $@ -# test with built sdk -.PHONY: test-gitlab2 -test-gitlab2: - cd pulp-builder; \ - source sdk-setup.sh; \ - source configs/pulpissimo.sh; \ - source configs/rtl.sh; \ - cd ../tests && plptest --threads 16 --stdout +## Generate the FPGA boot rom +hw/fpga_autogen_rom.sv: + $(MAKE) -C sw/bootcode fpga_autogen_rom.sv + cp sw/bootcode/fpga_autogen_rom.sv $@ -.PHONY: lint -## Generate lint reports with Spyglass -lint: - $(MAKE) -C spyglass lint_rtl +padframe: hw/padframe/pulpissimo_padframe_rtl_sim_autogen hw/padframe/pulpissimo_padframe_fpga_autogen -# Bender integration -bender: -ifeq (,$(wildcard ./bender)) - curl --proto '=https' --tlsv1.2 -sSf https://pulp-platform.github.io/bender/init \ - | bash -s -- 0.25.2 - touch bender -endif +hw/padframe/pulpissimo_padframe_rtl_sim_autogen: $(PULPISSIMO_UTILS)/padrick + cd hw/padframe && $(PULPISSIMO_UTILS)/padrick generate -s padrick_generator_settings.yml rtl rtl_sim_padframe_config_top.yml -o pulpissimo_padframe_rtl_sim_autogen -.PHONY: bender-rm -bender-rm: - rm -f bender +hw/padframe/pulpissimo_padframe_fpga_autogen: $(PULPISSIMO_UTILS)/padrick + cd hw/padframe && $(PULPISSIMO_UTILS)/padrick generate -s padrick_generator_settings.yml rtl fpga_padframe_config_top.yml -o pulpissimo_padframe_fpga_autogen -.PHONY: TAGS -## Generate emacs TAGS file -TAGS: - $(CTAGS) -R -e --language=systemverilog --exclude=boot/* \ - --exclude=freertos/* --exclude=fw/* --exclude=pkg/* \ - --exclude=pulp-runtime/* --exclude=pulp-sdk/* \ - --exclude=sdk-releases/* --exclude=tests/* \ - --exclude=util/* --exclude=install/* --exclude=env/* \ - --exclude=synth/* \ - --exclude=*.patch --exclude=*.md --exclude=*.log \ - --exclude=*.vds --exclude=*.adoc . +.PHONY: gpio-reconfigure +## Reconfigure number of GPIOs +## @param GPIO=32 Number of GPIOs to reconfigure +gpio-reconfigure: + $(MAKE) -C hw/vendored_ips/gpio reconfigure -.PHONY: help -help: Makefile - @printf "PULP Platform\n" - @printf "Available targets\n\n" - @awk '/^[a-zA-Z\-\_0-9]+:/ { \ - helpMessage = match(lastLine, /^## (.*)/); \ - if (helpMessage) { \ - helpCommand = substr($$1, 0, index($$1, ":")-1); \ - helpMessage = substr(lastLine, RSTART + 3, RLENGTH); \ - printf "%-15s %s\n", helpCommand, helpMessage; \ - } \ - } \ - { lastLine = $$0 }' $(MAKEFILE_LIST) +HELP_TITLE="PULPissimo Build & SIM Environment" +HELP_DESCRIPTION="Toplevel targets for building and simulating PULPissimo. Please check the make files in the subdirectories for additional targets.." +include $(PULPISSIMO_ROOT)/utils/help.mk +.DEFAULT_GOAL := help diff --git a/README.md b/README.md index 644382fa..09ac3018 100644 --- a/README.md +++ b/README.md @@ -80,6 +80,7 @@ PULPissimo supports I/O on interfaces such as: - Camera Interface (CPI) - I2C - UART +- Hyperbus - JTAG PULPissimo also supports integration of hardware accelerators (Hardware @@ -95,7 +96,7 @@ see `ips/hwpe-stream/doc` and https://arxiv.org/abs/1612.05974. ## Documentation -- The [datasheet](doc/datasheet/datasheet.pdf) contains details about Memory Map, Peripherals, Registers etc. +- The [datasheet](doc/datasheet/datasheet.pdf) contains details about Memory Map, Peripherals, Registers etc. This may not be fully up-to-date. - PULPissimo was presented at the Week of Open Source Hardware (WOSH) 2019 at ETH Zurich. - [Slides](https://pulp-platform.org/docs/riscv_workshop_zurich/schiavone_wosh2019_tutorial.pdf) - [Video](https://www.youtube.com/watch?v=27tndT6cBH0) @@ -144,14 +145,14 @@ export PATH=$PULP_RISCV_GCC_TOOLCHAIN/bin:$PATH ``` -Get the repository for the simple runtime: +The repository for the simple runtime is included as a submodule: ``` -git clone https://github.com/pulp-platform/pulp-runtime/ +git submodule update --init --recursive ``` The simple runtime supports many different hardware configurations. We want PULPissimo. ``` -cd pulp-runtime +cd sw/pulp-runtime ``` Then, to use the CV32E40P (formely RI5CY) core, type: @@ -188,7 +189,7 @@ simulate the hardware design running your program, so go Then get the repository for the pulp-freertos: ``` -git clone https://github.com/pulp-platform/pulp-freertos/ +git clone https://github.com/pulp-platform/pulp-freertos/ sw/pulp-freertos ``` There are multiple hardware configuration supported. Select PULPissimo using the @@ -196,7 +197,7 @@ CV32E40P core. So enter the directory of pulp-freertos: ``` -cd pulp-freertos +cd sw/pulp-freertos ``` and select the correct configuration: @@ -263,14 +264,13 @@ scripts. The dependency management tool is After having access to the SDK, you can build the simulation platform by doing the following: ```bash -source setup/vsim.sh make build ``` This command builds a version of the simulation platform with no dependencies on external models for peripherals. See below (Proprietary verification IPs) for details on how to plug in some models of real SPI, I2C, I2S peripherals. -For more advanced usage have a look at `./bender --help` for bender. +For more advanced usage have a look at `./utils/bin/bender --help` for bender. Also check out the output of `make help` for more useful Makefile targets. @@ -388,10 +388,10 @@ make conf More information is available in the documentation here: pulp-builder/install/doc/vp/index.html ### Updating the bootrom -You can customize the bootrom, have a look at the `boot_code/` directory. To +You can customize the bootrom, have a look at the `sw/bootcode/` directory. To import your changed version of the boot code into PULPissimo, just call ``` -make import-bootcode +make bootrom ``` ## FPGA @@ -413,22 +413,18 @@ follow the section below to generate the bitstreams yourself. ### Bitstream Generation In order to generate the PULPissimo bitstream for a supported target FPGA board -first generate the necessary synthesis include scripts by running the +you can directly generate the bitstream for the desired board by running the corresponding make target. -```Shell -make scripts -``` - This will parse the `Bender.yml` using the PULP bender dependency management tool to generate tcl scripts for all the IPs used in the PULPissimo project. These files are later on sourced by Vivado to generate the bitstream for PULPissimo. -Now switch to the fpga subdirectory and start the apropriate make target to +You can also switch to the fpga subdirectory and start the apropriate make target to generate the bitstream: ```Shell -cd fpga +cd target/fpga make ``` In order to show a list of all available board targets call: @@ -448,7 +444,7 @@ should now contain two files: If your invocation command to start Vivado isn't `vivado` you can use the Make variable `VIVADO` to specify the right command (e.g. `make genesys2 -VIVADO='vivado-2018.3 vivado'` for ETH CentOS machines.) Boot from ROM is not +VIVADO='vitis vivado'` for ETH Almalinux machines.) Boot from ROM is not available yet. The ROM will always return the `jal x0,0` to trap the core until the debug module takes over control and loads the programm into L2 memory. Once the bitstream `pulpissimo_genesys2.bit` is generated in the fpga folder, you can @@ -469,7 +465,7 @@ Now your FPGA is ready to emulate PULPissimo! ### Board Specific Information Have a look at the board specific README.md files in -`fpga/pulpissimo-/README.md` for a description of peripheral +`target/fpga/pulpissimo-/README.md` for a description of peripheral mappings and default clock frequencies. ### Compiling Applications for the FPGA Target @@ -675,8 +671,8 @@ instead which has the same effect. ## Proprietary verification IPs The full simulation platform can take advantage of a few models of commercial SPI, I2C, I2S peripherals to attach to the open-source PULP simulation platform. -In `rtl/vip/spi_flash`, `rtl/vip/i2c_eeprom`, `rtl/vip/i2s` you find the -instructions to install SPI, I2C and I2S models. +In `target/sim/vip/spi_flash`, `target/sim/vip/i2c_eeprom`, `target/sim/vip/i2s` +you find the instructions to install SPI, I2C and I2S models. When the SPI flash model is installed, it will be possible to switch to a more realistic boot simulation, where the internal ROM of PULP is used to perform an @@ -687,27 +683,28 @@ To do this, the `LOAD_L2` parameter of the testbench has to be switched from ## PULP platform structure After being fully setup as explained in the Getting Started section, this root repository is structured as follows: -- `rtl/tb` contains the main platform testbench and the related files. -- `rtl/vip` contains the verification IPs used to emulate external peripherals, +- `target/sim/tb` contains the main platform testbench and the related files. +- `target/sim/vip` contains the verification IPs used to emulate external peripherals, e.g. SPI flash and camera. -- `rtl` could also contain other material (e.g. global includes, top-level +- `hw` could also contain other material (e.g. global includes, top-level files) -- `sim` contains the ModelSim/QuestaSim simulation platform. -- `pulp-sdk` contains the PULP software development kit; `pulp-sdk/tests` - contains all tests released with the SDK. +- `target/sim/questasim` contains the ModelSim/QuestaSim simulation platform. +- `sw/pulp-runtime` contains the PULP runtime; `sw/regression_tests` + contains some tests released with the SDK or runtime. Some tests, especially + parallel tests, are not compatible with PULPissimo. - `Bender.yml` contains the package information used with bender. This includes a list of IPs required and source files contained within this repository. - When using bender, other files may be relevant: `Bender.local` contains configs for bender, including overrides for dependencies, `Bender.lock` is a - generated file used by bender, `bender` is the bender executable fetched by - the makefile, `.bender` directory contains the database and checkouts used by - bender. + generated file used by bender, `utils/bin/bender` is the bender executable + fetched by the makefile, `.bender` directory contains the database and + checkouts used by bender. ## Requirements The RTL platform has the following requirements: -- Relatively recent Linux-based operating system; we tested *Ubuntu 16.04* and - *CentOS 7*. -- Mentor ModelSim in reasonably recent version (we tested it with version *10.6b* +- Relatively recent Linux-based operating system; we tested *Ubuntu 16.04*, + *CentOS 7*, and *Almalinux 8*. +- QuestaSim in reasonably recent version (we tested it with version *2023.4* -- the free version provided by Altera is only partially working, see issue #12). - Python 3.4, with the `pyyaml` module installed (you can get that with `pip3 install pyyaml`). @@ -724,7 +721,7 @@ describe your changes in detail, along with motivations. The pull request will be evaluated and checked with our regression test suite for possible integration. If you want to replace our version of an IP with your GitHub fork, just -update the Bender.yml file and run `./bender update`. +update the Bender.yml file and run `./utils/bin/bender update`. While we are quite relaxed in terms of coding style, please try to follow these recommendations: https://github.com/pulp-platform/ariane/blob/master/CONTRIBUTING.md diff --git a/env/ci-pulpissimo.sh b/env/ci-pulpissimo.sh deleted file mode 100644 index e9e14121..00000000 --- a/env/ci-pulpissimo.sh +++ /dev/null @@ -1,10 +0,0 @@ -# This script is mean to be used in a gitlabci setup -# var that points to this project's root -ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) - -echo "Setting up SDK" -source "$ROOT/env/env-sdk-2020.01.01.sh" -source "$ROOT/pkg/sdk/2020.01.01/configs/pulpissimo.sh" -source "$ROOT/pkg/sdk/2020.01.01/configs/platform-rtl.sh" -echo "Setting up VSIM" -source "$ROOT/setup/vsim.sh" diff --git a/env/pulpissimo.sh b/env/pulpissimo.sh deleted file mode 100644 index 1dd60cb7..00000000 --- a/env/pulpissimo.sh +++ /dev/null @@ -1,12 +0,0 @@ -#!/usr/bin/env bash - -# var that points to this project's root -ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) -[[ -d $ROOT/pulp-sdk ]] || { echo "Error: Make sure you built the sdk with \`make build-pulp-sdk\'"; } -[[ -n $PULP_RISCV_GCC_TOOLCHAIN ]] || { echo "Error: PULP_RISCV_GCC_TOOLCHAIN is not set"; } -echo "Setting up SDK" -source "$ROOT/pulp-sdk/sourceme.sh" -echo "Setting up for RTL simulation" -source "$ROOT/pulp-sdk/configs/platform-rtl.sh" -echo "Setting up VSIM" -source "$ROOT/setup/vsim.sh" diff --git a/fpga/Makefile b/fpga/Makefile deleted file mode 100644 index fb803e38..00000000 --- a/fpga/Makefile +++ /dev/null @@ -1,105 +0,0 @@ -.DEFAULT_GOAL:=help -export BENDER - -all: genesys2 zcu104 nexys_video nexys zedboard zcu102 zcu106 ## Generates the bitstream for all supported boards board. - -clean_all: clean_genesys2 clean_zcu104 clean_nexys_video clean_nexys clean_zedboard clean_zcu102 ## Removes synthesis output and bitstreams for all boards. - -genesys2: ## Generates the bistream for the genesys2 board - $(MAKE) -C pulpissimo-genesys2 all - cp pulpissimo-genesys2/pulpissimo-genesys2.runs/impl_1/xilinx_pulpissimo.bit pulpissimo_genesys2.bit - cp pulpissimo-genesys2/pulpissimo-genesys2.runs/impl_1/xilinx_pulpissimo.bin pulpissimo_genesys2.bin - @echo "Bitstream generation for genesys2 board finished. The bitstream Configuration Memory File was copied to ./pulpissimo_genesys2.bit and ./pulpissimo_genesys2.bin" - -clean_genesys2: ## Removes all bitstreams, *.log files and vivado related files (rm -rf vivado*) for the genesys2 board. - $(MAKE) -C pulpissimo-genesys2 clean - rm -f pulpissimo_genesys2.bit - rm -f pulpissimo_genesys2.bin - -zcu104: ## Generates the bistream for the zcu104 board - $(MAKE) -C pulpissimo-zcu104 all - cp pulpissimo-zcu104/pulpissimo-zcu104.runs/impl_1/xilinx_pulpissimo.bit pulpissimo_zcu104.bit - cp pulpissimo-zcu104/pulpissimo-zcu104.runs/impl_1/xilinx_pulpissimo.bin pulpissimo_zcu104.bin - @echo "Bitstream generation for zcu104 board finished. The bitstream Configuration Memory File was copied to ./pulpissimo_zcu104.bit and ./pulpissimo_zcu104.bin" - -clean_zcu104: ## Removes all bitstreams, *.log files and vivado related files (rm -rf vivado*) for the zcu104 board. - $(MAKE) -C pulpissimo-zcu104 clean - rm -f pulpissimo_zcu104.bit - rm -f pulpissimo_zcu104.bin - -zcu106: ## Generates the bistream for the zcu104 board - $(MAKE) -C pulpissimo-zcu106 all - cp pulpissimo-zcu106/pulpissimo-zcu106.runs/impl_1/xilinx_pulpissimo.bit pulpissimo_zcu106.bit - cp pulpissimo-zcu106/pulpissimo-zcu106.runs/impl_1/xilinx_pulpissimo.bin pulpissimo_zcu106.bin - @echo "Bitstream generation for zcu106 board finished. The bitstream Configuration Memory File was copied to ./pulpissimo_zcu106.bit and ./pulpissimo_zcu106.bin" - -clean_zcu106: ## Removes all bitstreams, *.log files and vivado related files (rm -rf vivado*) for the zcu104 board. - $(MAKE) -C pulpissimo-zcu106 clean - rm -f pulpissimo_zcu106.bit - rm -f pulpissimo_zcu106.bin - -nexys_video: ## Generates the bistream for the nexys_video board - $(MAKE) -C pulpissimo-nexys_video all - cp pulpissimo-nexys_video/pulpissimo-nexys_video.runs/impl_1/xilinx_pulpissimo.bit pulpissimo_nexys_video.bit - cp pulpissimo-nexys_video/pulpissimo-nexys_video.runs/impl_1/xilinx_pulpissimo.bin pulpissimo_nexys_video.bin - @echo "Bitstream generation for nexys_video board finished. The bitstream Configuration Memory File was copied to ./pulpissimo_nexys_video.bit and ./pulpissimo_nexys_video.bin" - -clean_nexys_video: ## Removes all bitstreams, *.log files and vivado related files (rm -rf vivado*) for the nexys_video board. - $(MAKE) -C pulpissimo-nexys_video clean - rm -f pulpissimo_nexys_video.bit - rm -f pulpissimo_nexys_video.bin - -nexys: ## Generates the bistream for the nexys board. Use make nexys rev=[nexys4|nexys4DDR|nexysA7-50T|nexysA7-100T] - $(MAKE) -C pulpissimo-nexys all - cp pulpissimo-nexys/pulpissimo-nexys.runs/impl_1/xilinx_pulpissimo.bit pulpissimo_nexys.bit - cp pulpissimo-nexys/pulpissimo-nexys.runs/impl_1/xilinx_pulpissimo.bin pulpissimo_nexys.bin - @echo "Bitstream generation for nexys board finished. The bitstream Configuration Memory File was copied to ./pulpissimo_nexys.bit and ./pulpissimo_nexys.bin" - -clean_nexys: ## Removes all bitstreams, *.log files and vivado related files (rm -rf vivado*) for the nexys board. - $(MAKE) -C pulpissimo-nexys clean - rm -f pulpissimo_nexys.bit - rm -f pulpissimo_nexys.bin - -vcu108: ## Generates the bistream for the vcu108 board - $(MAKE) -C pulpissimo-vcu108 all - cp pulpissimo-vcu108/pulpissimo-vcu108.runs/impl_1/xilinx_pulpissimo.bit pulpissimo_vcu108.bit - cp pulpissimo-vcu108/pulpissimo-vcu108.runs/impl_1/xilinx_pulpissimo.bin pulpissimo_vcu108.bin - @echo "Bitstream generation for vcu108 board finished. The bitstream Configuration Memory File was copied to ./pulpissimo_vcu108.bit and ./pulpissimo_vcu108.bin" - -clean_vcu108: ## Removes all bitstreams, *.log files and vivado related files (rm -rf vivado*) for the vcu108 board. - $(MAKE) -C pulpissimo-vcu108 clean - rm -f pulpissimo_vcu108.bit - rm -f pulpissimo_vcu108.bin - -zedboard: ## Generates the bistream for the ZedBoard - $(MAKE) -C pulpissimo-zedboard all - cp pulpissimo-zedboard/pulpissimo-zedboard.runs/impl_1/xilinx_pulpissimo.bit pulpissimo_zedboard.bit - cp pulpissimo-zedboard/pulpissimo-zedboard.runs/impl_1/xilinx_pulpissimo.bin pulpissimo_zedboard.bin - @echo "Bitstream generation for ZedBoard finished. The bitstream Configuration Memory File was copied to ./pulpissimo_zedboard.bit and ./pulpissimo_zedboard.bin" - -clean_zedboard: ## Removes all bitstreams, *.log files and vivado related files (rm -rf vivado*) for the ZedBoard. - $(MAKE) -C pulpissimo-zedboard clean - rm -f pulpissimo_zedboard.bit - rm -f pulpissimo_zedboard.bin - -zcu102: ## Generates the bistream for the zcu102 board - $(MAKE) -C pulpissimo-zcu102 all - cp pulpissimo-zcu102/pulpissimo-zcu102.runs/impl_1/xilinx_pulpissimo.bit pulpissimo_zcu102.bit - cp pulpissimo-zcu102/pulpissimo-zcu102.runs/impl_1/xilinx_pulpissimo.bin pulpissimo_zcu102.bin - @echo "Bitstream generation for zcu102 board finished. The bitstream Configuration Memory File was copied to ./pulpissimo_zcu102.bit and ./pulpissimo_zcu102.bin" - -clean_zcu102: ## Removes all bitstreams, *.log files and vivado related files (rm -rf vivado*) for the zcu102 board. - $(MAKE) -C pulpissimo-zcu102 clean - rm -f pulpissimo_zcu102.bit - rm -f pulpissimo_zcu102.bin - - -help: ## Show this help message - @echo "PULPissimo on FPGA" - @echo "" - @echo "Call make with one of the supported FPGA boards as arguments to generate the bitstream in the corresponding folder. " - @echo "E.g. 'make genesys2' to generate the bitstream for the genesys2 board in pulpissimo-genesy2 subdirectory." - @echo "By default make invokes 'vivado' to start Xilinx Vivado. This behaviour can be overriden by setting the make variable 'VIVADO'" - @echo "e.g. make genesys2 VIVADO='vivado-2018.3 vivado' for ETH centos machines." - @echo "" - @grep -E '^[a-zA-Z0-9_-]+:.*?## .*$$' $(MAKEFILE_LIST) | sort | awk 'BEGIN {FS = ":.*?## "}; {printf "\033[36m%-30s\033[0m %s\n", $$1, $$2}' diff --git a/fpga/pulpissimo-genesys2/rtl/xilinx_pulpissimo.v b/fpga/pulpissimo-genesys2/rtl/xilinx_pulpissimo.v deleted file mode 100644 index 49b78d27..00000000 --- a/fpga/pulpissimo-genesys2/rtl/xilinx_pulpissimo.v +++ /dev/null @@ -1,148 +0,0 @@ -//----------------------------------------------------------------------------- -// Title : PULPissimo Verilog Wrapper -//----------------------------------------------------------------------------- -// File : xilinx_pulpissimo.v -// Author : Manuel Eggimann -// Created : 21.05.2019 -//----------------------------------------------------------------------------- -// Description : -// Verilog Wrapper of PULPissimo to use the module within Xilinx IP integrator. -//----------------------------------------------------------------------------- -// Copyright (C) 2013-2019 ETH Zurich, University of Bologna -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. -//----------------------------------------------------------------------------- - -module xilinx_pulpissimo - ( - input wire ref_clk_p, - input wire ref_clk_n, - -// inout wire pad_spim_sdio0, - inout wire pad_spim_sdio1, - inout wire pad_spim_sdio2, - inout wire pad_spim_sdio3, - inout wire pad_spim_csn0, - inout wire pad_spim_sck, - - inout wire pad_uart_rx, - inout wire pad_uart_tx, - - inout wire led0_o, //Mapped to spim_csn1 - inout wire led1_o, //Mapped to cam_pclk - inout wire led2_o, //Mapped to cam_hsync - inout wire led3_o, //Mapped to cam_data0 - - inout wire switch0_i, //Mapped to cam_data1 - inout wire switch1_i, //Mapped to cam_data2 - - inout wire btnc_i, //Mapped to cam_data3 - inout wire btnd_i, //Mapped to cam_data4 - inout wire btnl_i, //Mapped to cam_data5 - inout wire btnr_i, //Mapped to cam_data6 - inout wire btnu_i, //Mapped to cam_data7 - - inout wire oled_spim_sck_o, //Mapped to spim_sck - inout wire oled_spim_mosi_o, //Mapped to spim_sdio0 - inout wire oled_rst_o, //Mapped to i2s0_sck - inout wire oled_dc_o, //Mapped to i2s0_ws - inout wire oled_vbat_o, // Mapped to i2s0_sdi - inout wire oled_vdd_o, // Mapped to i2s1_sdi - - inout wire sdio_reset_o, //Reset signal for SD card need to be driven low to - //power the onboard sd-card. Mapped to cam_vsync. - inout wire pad_sdio_clk, - inout wire pad_sdio_cmd, - inout wire pad_sdio_data0, - inout wire pad_sdio_data1, - inout wire pad_sdio_data2, - inout wire pad_sdio_data3, - - inout wire pad_i2c0_sda, - inout wire pad_i2c0_scl, - - input wire pad_reset_n, - - input wire pad_jtag_tck, - input wire pad_jtag_tdi, - output wire pad_jtag_tdo, - input wire pad_jtag_tms, - input wire pad_jtag_trst - ); - - localparam CORE_TYPE = 0; // 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY) - localparam USE_FPU = 1; - localparam USE_HWPE = 0; - - wire ref_clk; - - - //Differential to single ended clock conversion - IBUFGDS - #( - .IOSTANDARD("LVDS"), - .DIFF_TERM("FALSE"), - .IBUF_LOW_PWR("FALSE")) - i_sysclk_iobuf - ( - .I(ref_clk_p), - .IB(ref_clk_n), - .O(ref_clk) - ); - - pulpissimo - #(.CORE_TYPE(CORE_TYPE), - .USE_FPU(USE_FPU), - .USE_HWPE(USE_HWPE) - ) i_pulpissimo - ( - .pad_spim_sdio0(oled_spim_mosi_o), - .pad_spim_sdio1(pad_spim_sdio1), - .pad_spim_sdio2(pad_spim_sdio2), - .pad_spim_sdio3(pad_spim_sdio3), - .pad_spim_csn0(pad_spim_csn0), - .pad_spim_csn1(led0_o), - .pad_spim_sck(oled_spim_sck_o), - .pad_uart_rx(pad_uart_rx), - .pad_uart_tx(pad_uart_tx), - .pad_cam_pclk(led1_o), - .pad_cam_hsync(led2_o), - .pad_cam_data0(led3_o), - .pad_cam_data1(switch0_i), - .pad_cam_data2(switch1_i), - .pad_cam_data3(btnc_i), - .pad_cam_data4(btnd_i), - .pad_cam_data5(btnl_i), - .pad_cam_data6(btnr_i), - .pad_cam_data7(btnu_i), - .pad_cam_vsync(sdio_reset_o), - .pad_sdio_clk(pad_sdio_clk), - .pad_sdio_cmd(pad_sdio_cmd), - .pad_sdio_data0(pad_sdio_data0), - .pad_sdio_data1(pad_sdio_data1), - .pad_sdio_data2(pad_sdio_data2), - .pad_sdio_data3(pad_sdio_data3), - .pad_i2c0_sda(pad_i2c0_sda), - .pad_i2c0_scl(pad_i2c0_scl), - .pad_i2s0_sck(oled_rst_o), - .pad_i2s0_ws(oled_dc_o), - .pad_i2s0_sdi(oled_vbat_o), - .pad_i2s1_sdi(oled_vdd_o), - .pad_reset_n(pad_reset_n), - .pad_jtag_tck(pad_jtag_tck), - .pad_jtag_tdi(pad_jtag_tdi), - .pad_jtag_tdo(pad_jtag_tdo), - .pad_jtag_tms(pad_jtag_tms), - .pad_jtag_trst(pad_jtag_trst), - .pad_xtal_in(ref_clk), - .pad_bootsel0(), - .pad_bootsel1() - ); - -endmodule diff --git a/fpga/pulpissimo-nexys/rtl/xilinx_pulpissimo.v b/fpga/pulpissimo-nexys/rtl/xilinx_pulpissimo.v deleted file mode 100644 index ca9d236f..00000000 --- a/fpga/pulpissimo-nexys/rtl/xilinx_pulpissimo.v +++ /dev/null @@ -1,181 +0,0 @@ -//----------------------------------------------------------------------------- -// Title : PULPissimo Verilog Wrapper -//----------------------------------------------------------------------------- -// File : xilinx_pulpissimo.v -// Author : Manuel Eggimann -// Created : 21.05.2019 -//----------------------------------------------------------------------------- -// Description : -// Verilog Wrapper of PULPissimo to use the module within Xilinx IP integrator. -//----------------------------------------------------------------------------- -// Copyright (C) 2013-2019 ETH Zurich, University of Bologna -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. -//----------------------------------------------------------------------------- - -module xilinx_pulpissimo - ( - input wire sys_clk, - - inout wire pad_spim_sdio0, - inout wire pad_spim_sdio1, - inout wire pad_spim_sdio2, - inout wire pad_spim_sdio3, - inout wire pad_spim_csn0, - inout wire pad_spim_sck, - - inout wire pad_uart_rx, //Mapped to uart_rx - inout wire pad_uart_tx, //Mapped to uart_tx - //inout wire pad_uart_cts, //Not mapped, optional - //inout wire pad_uart_rts, //Not mapped, optional - - inout wire led0_o, //Mapped to spim_csn1 - inout wire led1_o, //Mapped to cam_pclk - inout wire led2_o, //Mapped to cam_hsync - inout wire led3_o, //Mapped to cam_data0 - - inout wire switch0_i, //Mapped to cam_data1 - inout wire switch1_i, //Mapped to cam_data2 - - inout wire btnc_i, //Mapped to cam_data3 - inout wire btnd_i, //Mapped to cam_data4 - inout wire btnl_i, //Mapped to cam_data5 - inout wire btnr_i, //Mapped to cam_data6 - inout wire btnu_i, //Mapped to cam_data7 - - - inout wire sdio_reset_o, //Reset signal for SD card need to be driven low to - //power the onboard sd-card. Mapped to cam_vsync. - inout wire pad_sdio_clk, - inout wire pad_sdio_cmd, - inout wire pad_sdio_data0, - inout wire pad_sdio_data1, - inout wire pad_sdio_data2, - inout wire pad_sdio_data3, - - inout wire pad_i2c0_sda, - inout wire pad_i2c0_scl, - - inout wire pad_i2s0_sck, - inout wire pad_i2s0_ws, - inout wire pad_i2s0_sdi, - inout wire pad_i2s1_sdi, - - input wire pad_reset_n, - - input wire pad_jtag_tck, - input wire pad_jtag_tdi, - output wire pad_jtag_tdo, - input wire pad_jtag_tms - //input wire pad_jtag_trst - ); - - localparam CORE_TYPE = 0; // 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY) - localparam USE_FPU = 1; - localparam USE_HWPE = 0; - - wire ref_clk; - wire tck_int; - //wire pad_spim_sck; - - // Input clock buffer - IBUFG - #( - .IOSTANDARD("LVCMOS33"), - .IBUF_LOW_PWR("FALSE")) - i_sysclk_iobuf - ( - .I(sys_clk), - .O(ref_clk) - ); - - //JTAG TCK clock buffer (dedicated route is false in constraints) - IBUF i_tck_iobuf ( - .I(pad_jtag_tck), - .O(tck_int) - ); - - // The SPI-Flash SCK Pin P8 is a configuration pin - // Therefore we must use a primitive to access it - // Thes SPI flash is currently not in use as an extended modification of the pad_frame is nessecary - // (IOBUF of the Pads can only drive signal connected to an I/O pin and not a signal to another primitive). - - //wire [3:0] su_nc; // Startup primitive output, no connect - // STARTUPE2 #( - // .PROG_USR("FALSE"), // Activate program event security feature. Requires encrypted bitstreams. - // .SIM_CCLK_FREQ(0.0) // Set the Configuration Clock Frequency(ns) for simulation. - // ) - // STARTUPE2_inst ( - // .CFGCLK(su_nc[0]), // 1-bit output: Configuration main clock output - // .CFGMCLK(su_nc[1]), // 1-bit output: Configuration internal oscillator clock output - // .EOS(su_nc[2]), // 1-bit output: Active high output signal indicating the End Of Startup. - // .PREQ(su_nc[3]), // 1-bit output: PROGRAM request to fabric output - // .CLK(1'b0), // 1-bit input: User start-up clock input - // .GSR(1'b0), // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name) - // .GTS(1'b0), // 1-bit input: Global 3-state input (GTS cannot be used for the port name) - // .KEYCLEARB(1'b0), // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM) - // .PACK(1'b0), // 1-bit input: PROGRAM acknowledge input - // .USRCCLKO(pad_spim_sck), // 1-bit input: User CCLK input -> the access to SPI SCK - // .USRCCLKTS(1'b0), // 1-bit input: User CCLK 3-state enable input - // .USRDONEO(1'b1), // 1-bit input: User DONE pin output control - // .USRDONETS(1'b1) // 1-bit input: User DONE 3-state enable outpu - - // ); - - pulpissimo - #(.CORE_TYPE(CORE_TYPE), - .USE_FPU(USE_FPU), - .USE_HWPE(USE_HWPE) - ) i_pulpissimo - ( - .pad_spim_sdio0(pad_spim_sdio0), - .pad_spim_sdio1(pad_spim_sdio1), - .pad_spim_sdio2(pad_spim_sdio2), - .pad_spim_sdio3(pad_spim_sdio3), - .pad_spim_csn0(pad_spim_csn0), - .pad_spim_csn1(led0_o), - .pad_spim_sck(pad_spim_sck), - .pad_uart_rx(pad_uart_rx), - .pad_uart_tx(pad_uart_tx), - .pad_cam_pclk(led1_o), - .pad_cam_hsync(led2_o), - .pad_cam_data0(led3_o), - .pad_cam_data1(switch0_i), - .pad_cam_data2(switch1_i), - .pad_cam_data3(btnc_i), - .pad_cam_data4(btnd_i), - .pad_cam_data5(btnl_i), - .pad_cam_data6(btnr_i), - .pad_cam_data7(btnu_i), - .pad_cam_vsync(sdio_reset_o), - .pad_sdio_clk(pad_sdio_clk), - .pad_sdio_cmd(pad_sdio_cmd), - .pad_sdio_data0(pad_sdio_data0), - .pad_sdio_data1(pad_sdio_data1), - .pad_sdio_data2(pad_sdio_data2), - .pad_sdio_data3(pad_sdio_data3), - .pad_i2c0_sda(pad_i2c0_sda), - .pad_i2c0_scl(pad_i2c0_scl), - .pad_i2s0_sck(pad_i2s0_sck), - .pad_i2s0_ws(pad_i2s0_ws), - .pad_i2s0_sdi(pad_i2s0_sdi), - .pad_i2s1_sdi(pad_i2s1_sdi), - .pad_reset_n(pad_reset_n), - .pad_jtag_tck(tck_int), - .pad_jtag_tdi(pad_jtag_tdi), - .pad_jtag_tdo(pad_jtag_tdo), - .pad_jtag_tms(pad_jtag_tms), - //.pad_jtag_trst(pad_jtag_trst), - .pad_jtag_trst(1'b1), - .pad_xtal_in(ref_clk), - .pad_bootsel0(), - .pad_bootsel1() - ); - -endmodule diff --git a/fpga/pulpissimo-zcu106/rtl/xilinx_pulpissimo.v b/fpga/pulpissimo-zcu106/rtl/xilinx_pulpissimo.v deleted file mode 100755 index 729b6a37..00000000 --- a/fpga/pulpissimo-zcu106/rtl/xilinx_pulpissimo.v +++ /dev/null @@ -1,144 +0,0 @@ -//----------------------------------------------------------------------------- -// Title : PULPissimo Verilog Wrapper -//----------------------------------------------------------------------------- -// File : xilinx_pulpissimo.v -// Author : Manuel Eggimann -// Created : 21.05.2019 -//----------------------------------------------------------------------------- -// Description : -// Verilog Wrapper of PULPissimo to use the module within Xilinx IP integrator. -//----------------------------------------------------------------------------- -// Copyright (C) 2013-2019 ETH Zurich, University of Bologna -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. -//----------------------------------------------------------------------------- - -module xilinx_pulpissimo - ( - input wire ref_clk_p, - input wire ref_clk_n, - - inout wire pad_uart_rx, - inout wire pad_uart_tx, - inout wire pad_uart_rts, //Mapped to spim_csn0 - inout wire pad_uart_cts, //Mapped to spim_sck - - inout wire led0_o, //Mapped to spim_csn1 - inout wire led1_o, //Mapped to cam_pclk - inout wire led2_o, //Mapped to cam_hsync - inout wire led3_o, //Mapped to cam_data0 - - inout wire switch0_i, //Mapped to cam_data1 - inout wire switch1_i, //Mapped to cam_data2 - inout wire switch2_i, //Mapped to cam_data7 - inout wire switch3_i, //Mapped to cam_vsync - - inout wire btn0_i, //Mapped to cam_data3 - inout wire btn1_i, //Mapped to cam_data4 - inout wire btn2_i, //Mapped to cam_data5 - inout wire btn3_i, //Mapped to cam_data6 - - inout wire pad_i2c0_sda, - inout wire pad_i2c0_scl, - - inout wire pad_pmod0_4, //Mapped to spim_sdio0 - inout wire pad_pmod0_5, //Mapped to spim_sdio1 - inout wire pad_pmod0_6, //Mapped to spim_sdio2 - inout wire pad_pmod0_7, //Mapped to spim_sdio3 - - inout wire pad_pmod1_0, //Mapped to sdio_data0 - inout wire pad_pmod1_1, //Mapped to sdio_data1 - inout wire pad_pmod1_2, //Mapped to sdio_data2 - inout wire pad_pmod1_3, //Mapped to sdio_data3 - inout wire pad_pmod1_4, //Mapped to i2s0_sck - inout wire pad_pmod1_5, //Mapped to i2s0_ws - inout wire pad_pmod1_6, //Mapped to i2s0_sdi - inout wire pad_pmod1_7, //Mapped to i2s1_sdi - - inout wire pad_hdmi_scl, //Mapped to sdio_clk - inout wire pad_hdmi_sda, //Mapped to sdio_cmd - - input wire pad_reset, - - input wire pad_jtag_tck, - input wire pad_jtag_tdi, - output wire pad_jtag_tdo, - input wire pad_jtag_tms - ); - - localparam CORE_TYPE = 0; // 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY) - localparam USE_FPU = 1; - localparam USE_HWPE = 0; - - wire ref_clk; - - - //Differential to single ended clock conversion - IBUFGDS - #( - .IOSTANDARD("LVDS"), - .DIFF_TERM("FALSE"), - .IBUF_LOW_PWR("FALSE")) - i_sysclk_iobuf - ( - .I(ref_clk_p), - .IB(ref_clk_n), - .O(ref_clk) - ); - - pulpissimo - #(.CORE_TYPE(CORE_TYPE), - .USE_FPU(USE_FPU), - .USE_HWPE(USE_HWPE) - ) i_pulpissimo - ( - .pad_spim_sdio0(pad_pmod0_4), - .pad_spim_sdio1(pad_pmod0_5), - .pad_spim_sdio2(pad_pmod0_6), - .pad_spim_sdio3(pad_pmod0_7), - .pad_spim_csn0(pad_uart_rts), - .pad_spim_csn1(led0_o), - .pad_spim_sck(pad_uart_cts), - .pad_uart_rx(pad_uart_rx), - .pad_uart_tx(pad_uart_tx), - .pad_cam_pclk(led1_o), - .pad_cam_hsync(led2_o), - .pad_cam_data0(led3_o), - .pad_cam_data1(switch0_i), - .pad_cam_data2(switch1_i), - .pad_cam_data3(btn0_i), - .pad_cam_data4(btn1_i), - .pad_cam_data5(btn2_i), - .pad_cam_data6(btn3_i), - .pad_cam_data7(switch2_i), - .pad_cam_vsync(switch3_i), - .pad_sdio_clk(pad_hdmi_scl), - .pad_sdio_cmd(pad_hdmi_sda), - .pad_sdio_data0(pad_pmod1_0), - .pad_sdio_data1(pad_pmod1_1), - .pad_sdio_data2(pad_pmod1_2), - .pad_sdio_data3(pad_pmod1_3), - .pad_i2c0_sda(pad_i2c0_sda), - .pad_i2c0_scl(pad_i2c0_scl), - .pad_i2s0_sck(pad_pmod1_4), - .pad_i2s0_ws(pad_pmod1_5), - .pad_i2s0_sdi(pad_pmod1_6), - .pad_i2s1_sdi(pad_pmod1_7), - .pad_reset_n(~pad_reset), - .pad_jtag_tck(pad_jtag_tck), - .pad_jtag_tdi(pad_jtag_tdi), - .pad_jtag_tdo(pad_jtag_tdo), - .pad_jtag_tms(pad_jtag_tms), - .pad_jtag_trst(1'b1), - .pad_xtal_in(ref_clk), - .pad_bootsel0(), - .pad_bootsel1() - ); - -endmodule diff --git a/hw/asic_autogen_rom.sv b/hw/asic_autogen_rom.sv new file mode 100644 index 00000000..3b6a6371 --- /dev/null +++ b/hw/asic_autogen_rom.sv @@ -0,0 +1,2093 @@ +//----------------------------------------------------------------------------- +// Title : ASIC Bootrom for control_pulp +//----------------------------------------------------------------------------- +// File : asic_autogen_rom.sv +//----------------------------------------------------------------------------- +// Description : +// Auto-generated bootrom from gen_bootrom.py +//----------------------------------------------------------------------------- +// Copyright (C) 2013-2021 ETH Zurich, University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +//----------------------------------------------------------------------------- + +// Auto-generated code +module asic_autogen_rom #( + parameter ADDR_WIDTH=32, + parameter DATA_WIDTH=32 +) ( + input logic CLK, + input logic CEN, + input logic [ADDR_WIDTH-1:0] A, + output logic [DATA_WIDTH-1:0] Q +); + + localparam NUM_WORDS = 2**ADDR_WIDTH; + logic [ADDR_WIDTH-1:0] A_Q; + + const logic [NUM_WORDS-1:0][DATA_WIDTH-1:0] MEM = { + 32'b00000000000000000000000000000000, + 32'b00000000000000000000000000000000, + 32'b00000000000000000000000000000000, + 32'b00000000000000000000000000000000, + 32'b00000000000000000000000000000000, + 32'b00000000000000000000000000000000, + 32'b00000000000000000000000000000000, + 32'b00000000000000000000000000000000, + 32'b00000000000000000000000000000000, + 32'b00000000000000000000000000000000, + 32'b00000000000000000000000000000000, + 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clock_gen_fpga.sv +// Author : Manuel Eggimann +// Created : 19.04.2022 +//----------------------------------------------------------------------------- +// Description : +// +// This module wraps Xilinx clock wizard Logicore IPs for FPGA emulation of +// PULPissimo at fixed frequency. +// +//----------------------------------------------------------------------------- +// Copyright (C) 2022 ETH Zurich, University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// SPDX-License-Identifier: SHL-0.51 +//----------------------------------------------------------------------------- + + +module clock_gen #( + // address widht of the of configuration bus + parameter int unsigned APB_ADDR_WIDTH, + localparam int unsigned APB_DATA_WIDTH = 32 +)( + // Reference clock for internal clock generation. The frequency of this clock + // is platform dependent (ASIC/RTL sim -> 32kHz) + input logic ref_clk_i, + + // Asynchronous active-low reset. Shall reset all clock generation config. + // Typically connected to a POR. + input logic rst_ni, + + // DFT signals + input logic dft_test_en_i, + + // Configuration interface for clock generation + input logic cfg_clk_i, + APB.Slave cfg_bus_slave, + + + // Output clocks + // Slow clock is the 32 kHz clock used for the certain timers + input logic slow_byp_clk_i, // The clock used in bypass mode + input logic slow_clk_en_i, + input logic slow_clk_byp_en_i, // feed slow_clk_o directly from ref_clk_i + output logic slow_clk_o, + // The SoC clock drives the complete SoC domain (should be as fast or faster + // than per_clk_o) + input logic soc_byp_clk_i, // The clock used in bypass mode + input logic soc_clk_en_i, + input logic soc_clk_byp_en_i, + output logic soc_clk_o, + + // Clock that drives IO buffers within IO peripherals + input logic per_byp_clk_i, // The clock used in bypass mode + input logic per_clk_en_i, + input logic per_clk_byp_en_i, + output logic per_clk_o +); + + logic s_clk_fll_soc; + logic s_clk_soc_ungated; + logic s_clk_fll_per; + logic s_clk_per_ungated; + logic s_slow_clock; + logic s_slow_clk_ungated; + + // Tie-off APB port with error response + assign cfg_bus_slave.pready = 1'b1; + assign cfg_bus_slave.prdata = 32'hdeadda7a; + assign cfg_bus_slave.pslverr = 1'b1; + + // Instantiate LogiCore clocking mngr IP + xilinx_clk_mngr i_clk_manager ( + .resetn(rst_ni), + .clk_in1(ref_clk_i), + .clk_out1(s_clk_fll_soc), + .clk_out2(s_clk_fll_per), + .locked() + ); + + tc_clk_mux2 i_fll_soc_bypass_mux ( + .clk0_i ( s_clk_fll_soc ), + .clk1_i ( soc_byp_clk_i ), + .clk_sel_i ( soc_clk_byp_en_i ), + .clk_o ( s_clk_soc_ungated ) + ); + + tc_clk_gating #(.IS_FUNCTIONAL(1'b1)) i_soc_clk_en( + .clk_i ( s_clk_soc_ungated ), + .en_i ( soc_clk_en_i ), + .test_en_i ( dft_test_en_i ), + .clk_o ( soc_clk_o ) + ); + + + tc_clk_mux2 i_fll_per_bypass_mux ( + .clk0_i ( s_clk_fll_per ), + .clk1_i ( per_byp_clk_i ), + .clk_sel_i ( per_clk_byp_en_i ), + .clk_o ( s_clk_per_ungated ) + ); + + tc_clk_gating #(.IS_FUNCTIONAL(1'b1)) i_per_clk_en( + .clk_i ( s_clk_per_ungated ), + .en_i ( per_clk_en_i ), + .test_en_i ( dft_test_en_i ), + .clk_o ( per_clk_o ) + ); + + //////////////// + // Slow Clock // + //////////////// + logic s_intermmediate_slow_clock; + xilinx_slow_clk_mngr i_slow_clk_mngr ( + .resetn ( rst_ni ), + .clk_in1 ( ref_clk_i ), + .clk_out1 ( s_intermmediate_slow_clock ) + ); + + // Instantiate clock divider to divide 8.3886 MHz PLL clock down to 32 kHz + clk_int_div #( + .DIV_VALUE_WIDTH ( 9 ), + .DEFAULT_DIV_VALUE ( 256 ), + .ENABLE_CLOCK_IN_RESET ( 1'b1 ) + ) i_slow_clk_div ( + .clk_i ( s_intermmediate_slow_clock ), + .rst_ni, + .en_i ( 1'b1 ), + .test_mode_en_i ( dft_test_en_i ), + .div_i ( 256 ), + .div_valid_i ( 1'b0 ), // We don't use the dynamic config port and only use the + // default div value. Should be optimized away. + .div_ready_o ( ), + .clk_o ( s_slow_clock ), + .cycl_count_o ( ) + ); + + tc_clk_mux2 i_slow_clk_bypass_mux ( + .clk0_i ( s_slow_clock ), + .clk1_i ( ref_clk_i ), + .clk_sel_i ( slow_clk_byp_en_i ), + .clk_o ( s_slow_clk_ungated ) + ); + + tc_clk_gating #(.IS_FUNCTIONAL(1'b1)) i_slow_clk_en( + .clk_i ( s_slow_clk_ungated ), + .en_i ( slow_clk_en_i ), + .test_en_i ( dft_test_en_i ), + .clk_o ( slow_clk_o ) + ); + +endmodule diff --git a/hw/clock_gen_generic.sv b/hw/clock_gen_generic.sv new file mode 100644 index 00000000..d9371ffc --- /dev/null +++ b/hw/clock_gen_generic.sv @@ -0,0 +1,197 @@ +//----------------------------------------------------------------------------- +// Title : Wrapper of ETH custom FLL IP models +//----------------------------------------------------------------------------- +// File : clock_gen_asic.sv +// Author : Manuel Eggimann +// Created : 19.04.2022 +//----------------------------------------------------------------------------- +// Description : +// +// This module wraps the behavioral FLL models for the technology specific FLLs +// used for ETH/Unibo ASIC tapeouts. If you want to port PULPissimo to a +// different, please provide your own implementation of this module. You can use +// the config `register_interface` to connect to internal register files that +// controll your clock generation IP. In that case, you will have to modify the +// pulp-runtime/SDK to use your custom FLL configuration interface (i.e. you +// need to provide a driver on how to talk to your PLL/FLL). Vanila +// pulp-runtime/SDK is developed to communicate with this behavioral model. +// +//----------------------------------------------------------------------------- +// Copyright (C) 2022 ETH Zurich, University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// SPDX-License-Identifier: SHL-0.51 +//----------------------------------------------------------------------------- + + +module clock_gen #( + // address widht of the of configuration bus + parameter int unsigned APB_ADDR_WIDTH, + localparam int unsigned APB_DATA_WIDTH = 32 +)( + // Reference clock for internal clock generation. The frequency of this clock + // is platform dependent (the asic version `clock_gen_asic.sv` requires a + // 32kHz ref clk) + input logic ref_clk_i, + + // Asynchronous active-low reset. Shall reset all clock generation config. + // Typically connected to a POR. + input logic rst_ni, + + // DFT signals + input logic dft_test_en_i, + + // Configuration interface for clock generation + input logic cfg_clk_i, + APB.Slave cfg_bus_slave, + + + // Output clocks + // Slow clock is the 32 kHz clock used for the certain timers + input logic slow_clk_en_i, + input logic slow_clk_byp_en_i, // feed slow_clk_o directly from ref_clk_i, + // this particular implementation already uses + // a ref clock of 32kHz so this port is + // unconnected. + output logic slow_clk_o, + // The SoC clock drives the complete SoC domain (should be as fast or faster + // than per_clk_o) + input logic soc_clk_en_i, + input logic soc_clk_byp_en_i, + output logic soc_clk_o, + + // Clock that drives IO buffers within IO peripherals + input logic per_clk_en_i, + input logic per_clk_byp_en_i, + output logic per_clk_o +); + + logic s_clk_fll_soc; + logic s_clk_soc_ungated; + logic s_clk_fll_per; + logic s_clk_per_ungated; + + // Convert APB interface to FLL native interface + FLL_BUS fll_bus[2](.clk_i(cfg_clk_i)); + + apb_to_fll #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .NR_FLLS(2) + ) apb2fll_if_i ( + .clk_i ( cfg_clk_i ), + .rst_ni, + .apb ( cfg_bus_slave ), + .fll_intf ( fll_bus ) + ); + + + + // FLL model instantiation + + /////////////// + // SoC Clock // + /////////////// + + + // Behavioral model of ETH internal FLL (the name is for legacy reasons, + // interface is the same for all technologies the FLL has been ported to.) + gf22_FLL i_fll_soc ( + .FLLCLK ( s_clk_fll_soc ), + .FLLOE ( 1'b1 ), + .REFCLK ( ref_clk_i ), + .LOCK ( fll_bus[0].lock ), + .CFGREQ ( fll_bus[0].req ), + .CFGACK ( fll_bus[0].ack ), + .CFGAD ( fll_bus[0].addr[1:0] ), + .CFGD ( fll_bus[0].wdata ), + .CFGQ ( fll_bus[0].rdata ), + .CFGWEB ( fll_bus[0].wrn ), + .RSTB ( rst_ni ), + .PWD ( 1'b0 ), + .RET ( 1'b0 ), + .TM ( dft_test_en_i ), + .TE ( 1'b0 ), + .TD ( 1'b0 ), + .TQ ( ), + .JTD ( 1'b0 ), + .JTQ ( ) + ); + + tc_clk_mux2 i_fll_soc_bypass_mux ( + .clk0_i ( s_clk_fll_soc ), + .clk1_i ( ref_clk_i ), + .clk_sel_i ( soc_clk_byp_en_i ), + .clk_o ( s_clk_soc_ungated ) + ); + + tc_clk_gating #(.IS_FUNCTIONAL(1'b1)) i_soc_clk_en( + .clk_i ( s_clk_soc_ungated ), + .en_i ( soc_clk_en_i ), + .test_en_i ( dft_test_en_i ), + .clk_o ( soc_clk_o ) + ); + + + ////////////////////// + // Peripheral Clock // + ////////////////////// + + // Behavioral model of ETH internal FLL (the name is for legacy reasons, + // interface is the same for all technologies the FLL has been ported to.) + gf22_FLL i_fll_per ( + .FLLCLK ( s_clk_fll_per ), + .FLLOE ( 1'b1 ), + .REFCLK ( ref_clk_i ), + .LOCK ( fll_bus[1].lock ), + .CFGREQ ( fll_bus[1].req ), + .CFGACK ( fll_bus[1].ack ), + .CFGAD ( fll_bus[1].addr[1:0] ), + .CFGD ( fll_bus[1].wdata ), + .CFGQ ( fll_bus[1].rdata ), + .CFGWEB ( fll_bus[1].wrn ), + .RSTB ( rst_ni ), + .PWD ( 1'b0 ), + .RET ( 1'b0 ), + .TM ( dft_test_en_i ), + .TE ( 1'b0 ), + .TD ( 1'b0 ), + .TQ ( ), + .JTD ( 1'b0 ), + .JTQ ( ) + ); + + tc_clk_mux2 i_fll_per_bypass_mux ( + .clk0_i ( s_clk_fll_per ), + .clk1_i ( ref_clk_i ), + .clk_sel_i ( per_clk_byp_en_i ), + .clk_o ( s_clk_per_ungated ) + ); + + tc_clk_gating #(.IS_FUNCTIONAL(1'b1)) i_per_clk_en( + .clk_i ( s_clk_per_ungated ), + .en_i ( per_clk_en_i ), + .test_en_i ( dft_test_en_i ), + .clk_o ( per_clk_o ) + ); + + + //////////////// + // Slow Clock // + //////////////// + + tc_clk_gating #(.IS_FUNCTIONAL(1'b1)) i_slow_clk_en( + .clk_i ( ref_clk_i ), + .en_i ( slow_clk_en_i ), + .test_en_i ( dft_test_en_i ), + .clk_o ( slow_clk_o ) + ); + + // This implementation does not need the bypass signal since slow clock already == ref_clk + unread i_unused_slow_clk_bypass_en(.d_i(slow_clk_byp_en_i)); +endmodule diff --git a/hw/fpga_autogen_rom.sv b/hw/fpga_autogen_rom.sv new file mode 100644 index 00000000..8e6f5e80 --- /dev/null +++ b/hw/fpga_autogen_rom.sv @@ -0,0 +1,2093 @@ +//----------------------------------------------------------------------------- +// Title : FPGA Bootrom for control_pulp +//----------------------------------------------------------------------------- +// File : fpga_autogen_rom.sv +//----------------------------------------------------------------------------- +// Description : +// Auto-generated bootrom from gen_bootrom.py +//----------------------------------------------------------------------------- +// Copyright (C) 2013-2021 ETH Zurich, University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +//----------------------------------------------------------------------------- + +// Auto-generated code +module fpga_autogen_rom #( + parameter ADDR_WIDTH=32, + parameter DATA_WIDTH=32 +) ( + input logic CLK, + input logic CEN, + input logic [ADDR_WIDTH-1:0] A, + output logic [DATA_WIDTH-1:0] Q +); + + localparam NUM_WORDS = 2**ADDR_WIDTH; + logic [ADDR_WIDTH-1:0] A_Q; + + const logic [NUM_WORDS-1:0][DATA_WIDTH-1:0] MEM = { + 32'b00000000000000000000000000000000, + 32'b00000000000000000000000000000000, + 32'b00000000000000000000000000000000, + 32'b00000000000000000000000000000000, + 32'b00000000000000000000000000000000, + 32'b00000000000000000000000000000000, + 32'b00000000000000000000000000000000, + 32'b00000000000000000000000000000000, + 32'b00000000000000000000000000000000, + 32'b00000000000000000000000000000000, + 32'b00000000000000000000000000000000, + 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32'b00000101110000000000000001101111, + 32'b00000110000000000000000001101111, + 32'b00000110010000000000000001101111, + 32'b00000110100000000000000001101111, + 32'b00000110110000000000000001101111, + 32'b00000111000000000000000001101111, + 32'b00000111010000000000000001101111, + 32'b00000111100000000000000001101111, + 32'b00000111110000000000000001101111, + 32'b00001000000000000000000001101111, + 32'b00001000010000000000000001101111, + 32'b00001000100000000000000001101111 + }; + + always_ff @(posedge CLK) + begin + if (CEN == 1'b0) + A_Q <= A; + end + + assign Q = MEM[A_Q]; + +endmodule diff --git a/rtl/includes/periph_bus_defines.sv b/hw/includes/periph_bus_defines.sv similarity index 100% rename from rtl/includes/periph_bus_defines.sv rename to hw/includes/periph_bus_defines.sv diff --git a/rtl/includes/pulp_soc_defines.sv b/hw/includes/pulp_soc_defines.sv similarity index 88% rename from rtl/includes/pulp_soc_defines.sv rename to hw/includes/pulp_soc_defines.sv index 733b9458..f36e1628 100644 --- a/rtl/includes/pulp_soc_defines.sv +++ b/hw/includes/pulp_soc_defines.sv @@ -52,19 +52,6 @@ // Hardware Accelerator selection `define HWCRYPT -// Uncomment if the SCM is not present (it will still be in the memory map) -//`define NO_SCM - -`define APU_CLUSTER - -// uncomment if you want to place the DEMUX peripherals (EU, MCHAN) rigth before the Test and set region. -// This will steal 16KB from the 1MB TCDM reegion. -// EU is mapped from 0x10100000 - 0x400 -// MCHAN regs are mapped from 0x10100000 - 0x800 -// remember to change the defines in the pulp.h as well to be coherent with this approach -//`define DEM_PER_BEFORE_TCDM_TS - - // Debugging // Trace CV32E40P core execution //`define CV32E40P_TRACE_EXECUTION diff --git a/hw/includes/soc_mem_map.svh b/hw/includes/soc_mem_map.svh new file mode 100644 index 00000000..27e82fe2 --- /dev/null +++ b/hw/includes/soc_mem_map.svh @@ -0,0 +1,85 @@ +//----------------------------------------------------------------------------- +// Title : SoC Memory Region Definitions +//----------------------------------------------------------------------------- +// File : soc_mem_map.svh +// Author : Manuel Eggimann +// Created : 30.10.2020 +//----------------------------------------------------------------------------- +// Description : +// This file contains start and end address definitions for the soc_interconnect. +//----------------------------------------------------------------------------- +// Copyright (C) 2013-2020 ETH Zurich, University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +//----------------------------------------------------------------------------- + +`define SOC_MEM_MAP_TCDM_START_ADDR 32'h1C01_0000 +`define SOC_MEM_MAP_TCDM_END_ADDR 32'h1C09_0000 + +`define SOC_MEM_MAP_PRIVATE_BANK0_START_ADDR 32'h1C00_0000 +`define SOC_MEM_MAP_PRIVATE_BANK0_END_ADDR 32'h1C00_8000 + +`define SOC_MEM_MAP_PRIVATE_BANK1_START_ADDR 32'h1C00_8000 +`define SOC_MEM_MAP_PRIVATE_BANK1_END_ADDR 32'h1C01_0000 + +`define SOC_MEM_MAP_BOOT_ROM_START_ADDR 32'h1A00_0000 +`define SOC_MEM_MAP_BOOT_ROM_END_ADDR 32'h1A04_0000 + +`define SOC_MEM_MAP_AXI_PLUG_START_ADDR 32'h1000_0000 +`define SOC_MEM_MAP_AXI_PLUG_END_ADDR 32'h1040_0000 + +`define SOC_MEM_MAP_PERIPHERALS_START_ADDR 32'h1A10_0000 +`define SOC_MEM_MAP_PERIPHERALS_END_ADDR 32'h1A40_0000 + +// Peripheral Bus Address Space +`define SOC_MEM_MAP_GPIO_START_ADDR 32'h1A10_1000 +`define SOC_MEM_MAP_GPIO_END_ADDR 32'h1A10_2000 + +`define SOC_MEM_MAP_UDMA_START_ADDR 32'h1A10_2000 +`define SOC_MEM_MAP_UDMA_END_ADDR 32'h1A10_4000 + +`define SOC_MEM_MAP_SOC_CTRL_START_ADDR 32'h1A10_4000 +`define SOC_MEM_MAP_SOC_CTRL_END_ADDR 32'h1A10_5000 + +`define SOC_MEM_MAP_ADV_TIMER_START_ADDR 32'h1A10_5000 +`define SOC_MEM_MAP_ADV_TIMER_END_ADDR 32'h1A10_6000 + +`define SOC_MEM_MAP_SOC_EVENT_GEN_START_ADDR 32'h1A10_6000 +`define SOC_MEM_MAP_SOC_EVENT_GEN_END_ADDR 32'h1A10_7000 + +`define SOC_MEM_MAP_INTERRUPT_CTRL_START_ADDR 32'h1A10_9000 +`define SOC_MEM_MAP_INTERRUPT_CTRL_END_ADDR 32'h1A10_B000 + +`define SOC_MEM_MAP_APB_TIMER_START_ADDR 32'h1A10_B000 +`define SOC_MEM_MAP_APB_TIMER_END_ADDR 32'h1A10_C000 + +`define SOC_MEM_MAP_HWPE_START_ADDR 32'h1A10_C000 +`define SOC_MEM_MAP_HWPE_END_ADDR 32'h1A10_D000 + +`define SOC_MEM_MAP_VIRTUAL_STDOUT_START_ADDR 32'h1A10_F000 +`define SOC_MEM_MAP_VIRTUAL_STDOUT_END_ADDR 32'h1A11_0000 + +`define SOC_MEM_MAP_DEBUG_START_ADDR 32'h1A11_0000 +`define SOC_MEM_MAP_DEBUG_END_ADDR 32'h1A12_0000 + +`define SOC_MEM_MAP_CHIP_CTRL_START_ADDR 32'h1A12_0000 +`define SOC_MEM_MAP_CHIP_CTRL_END_ADDR 32'h1A14_0000 + + +// Chip Control Address Region (This region is implementation specific) +`define SOC_MEM_MAP_CHIP_CTRL_FLL_START_ADDR 32'h1A12_0000 +`define SOC_MEM_MAP_CHIP_CTRL_FLL_END_ADDR 32'h1A12_1000 + +`define SOC_MEM_MAP_CHIP_CTRL_PAD_CFG_START_ADDR 32'h1A12_1000 +`define SOC_MEM_MAP_CHIP_CTRL_PAD_CFG_END_ADDR 32'h1A12_2000 + + +// Cluster Address Regions +`define SOC_MEM_MAP_CLUSTER_START_ADDR 32'h1000_0000 // This define is currently not used in the code and just here for documentation +`define SOC_MEM_MAP_CLUSTER_END_ADDR 32'h2000_0000 // TODO Actually use the define in soc_mem_map.svh for cluster address space definition diff --git a/hw/padframe/common_peripherals.yml b/hw/padframe/common_peripherals.yml new file mode 100644 index 00000000..31b1b479 --- /dev/null +++ b/hw/padframe/common_peripherals.yml @@ -0,0 +1,208 @@ +# This file declares the interface signals of every peripheral in pulpissimo. +- name: gpio + output_defaults: 1'b0 + ports: + - name: gpio{i:2d} + # We use some custom attributes to simplify conversion between individual + # signal names and signal arrays. Padrick does not natively support arrays + # so we use custom attributes to tell our custom_template + # ('assign.svh.mako') how to translate it correctly. + user_attr: + port_signal_aliases: + gpio{i:2d}_out: gpio_out[{i:1d}] + gpio{i:2d}_in: gpio_in[{i:1d}] + gpio{i:2d}_tx_en: gpio_tx_en[{i:1d}] + multiple: !include gpio_count.txt + mux_groups: ["pad_io{i:2d}"] + description: "Bidirectional GPIO{i} signal" + connections: + chip2pad: gpio{i:2d}_out + gpio{i:2d}_in: pad2chip + tx_en: gpio{i:2d}_tx_en + rx_en: ~gpio{i:2d}_tx_en + +- name: i2c{i:1d} + multiple: 1 + mux_groups: [all_muxed_ios] + output_defaults: + sda_i: 1'b1 + scl_i: 1'b1 + ports: + - name: sda + description: "Bidirectional I2C SDA signal" + connections: + chip2pad: sda_o + sda_i: pad2chip + tx_en: sda_oe + rx_en: ~sda_oe + + - name: scl + description: "I2C clock signal" + connections: + chip2pad: scl_o + scl_i: pad2chip + rx_en: scl_oe + tx_en: ~scl_oe + +- name: uart{i:1d} + multiple: 1 + mux_groups: [all_muxed_ios] + output_defaults: + rx_i: 1'b1 + ports: + - name: rx + description: "UART RX signal" + connections: + chip2pad: 1'b1 + rx_i: pad2chip + tx_en: 1'b0 + rx_en: 1'b1 + - name: tx + description: "UART TX signal" + connections: + chip2pad: tx_o + tx_en: 1'b1 + rx_en: 1'b0 + +- name: qspim{i:1d} + multiple: 1 + mux_groups: [all_muxed_ios] + output_defaults: 1'b0 + ports: + - name: sdio{i:1d} + description: "IO data port of the SPI master peripheral" + multiple: 4 + connections: + chip2pad: sd{i:1d}_o + sd{i:1d}_i: pad2chip + tx_en: sd{i:1d}_oe + rx_en: ~sd{i:1d}_oe + - name: sck + connections: + chip2pad: sck_o + tx_en: 1'b1 + rx_en: 1'b0 + - name: csn{i:1d} + description: "IO data port of the SPI master peripheral" + multiple: 4 + connections: + chip2pad: csn{i:1d}_o + tx_en: 1'b1 + rx_en: 1'b0 + +- name: cpi{i:1d} + multiple: 1 + mux_groups: [all_muxed_ios] + output_defaults: 1'b0 + ports: + - name: pclk + description: "input clock of the CPI slave peripheral" # An optional description of the signal + connections: + chip2pad: 1'b0 + pclk_i: pad2chip + - name: hsync + description: "horizontal synchronization input signal" # An optional description of the signal + connections: + chip2pad: 1'b0 + hsync_i: pad2chip + - name: vsync + description: "vertical synchronization input signal" # An optional description of the signal + connections: + chip2pad: 1'b0 + vsync_i: pad2chip + - name: data{i:1d} + description: "Input data line of the CPI slave peripheral" # An optional description of the signal + multiple: 10 + connections: + chip2pad: 1'b0 + data{i:1d}_i: pad2chip + + +- name: sdio{i:1d} + description: "SDIO interface peripheral to communicate with external SD-Cards" + multiple: 1 + mux_groups: [all_muxed_ios] + output_defaults: 1'b0 + ports: + - name: sdclk + description: "Clock signal of the SDIO interface" + connections: + chip2pad: sdclk_out + tx_en: 1'b1 + rx_en: 1'b0 + - name: sdcmd + description: "Bidirection command response siganl" + connections: + chip2pad: sdcmd_out + sdcmd_in: pad2chip + rx_en: sdcmd_oen + tx_en: ~sdcmd_oen + - name: sddata{i:1d} + description: "Bidirectional data bus" + multiple: 4 + user_attr: + port_signal_aliases: + sddata{i:1d}_out: sddata_out[{i}] + sddata{i:1d}_in: sddata_in[{i}] + sddata{i:1d}_oen: sddata_oen[{i}] + connections: + chip2pad: sddata{i:1d}_out + sddata{i:1d}_in: pad2chip + rx_en: sddata{i:1d}_oen + tx_en: ~sddata{i:1d}_oen + +- name: i2s{i:1d} + description: "I2S peripheral to communicate with external audio devices. Supports master and slave mode" + multiple: 1 + mux_groups: [all_muxed_ios] + output_defaults: 1'b0 + ports: + - name: master_sck + connections: + chip2pad: master_sck_out + master_sck_in: pad2chip + rx_en: ~master_sck_oe + tx_en: master_sck_oe + - name: master_ws + connections: + chip2pad: master_ws_out + master_ws_in: pad2chip + rx_en: ~master_ws_oe + tx_en: master_ws_oe + - name: master_sd{i:1d} + multiple: 2 + connections: + chip2pad: master_sd{i:1d}_out + rx_en: 1'b0 + tx_en: 1'b1 + - name: slave_sck + connections: + chip2pad: slave_sck_out + slave_sck_in: pad2chip + rx_en: ~slave_sck_oe + tx_en: slave_sck_oe + - name: slave_ws + connections: + chip2pad: slave_ws_out + slave_ws_in: pad2chip + rx_en: ~slave_ws_oe + tx_en: slave_ws_oe + - name: slave_sd{i:1d} + multiple: 2 + connections: + slave_sd{i:1d}_in: pad2chip + rx_en: 1'b1 + tx_en: 1'b0 + +- name: timer{i} + multiple: 4 + mux_groups: ["all_muxed_ios"] + ports: + - name: out{i} + user_attr: + port_signal_aliases: + timer_out{i}: out[{i}] + multiple: 4 + description: "TIMER 0 out {i}" + connections: + chip2pad: timer_out{i} diff --git a/hw/padframe/custom_templates/driver_templates/regfile.hjson.mako b/hw/padframe/custom_templates/driver_templates/regfile.hjson.mako new file mode 100644 index 00000000..fae9fbbe --- /dev/null +++ b/hw/padframe/custom_templates/driver_templates/regfile.hjson.mako @@ -0,0 +1,159 @@ +## Manuel Eggimann +## +## Copyright (C) 2021-2022 ETH Zürich +## +## Licensed under the Apache License, Version 2.0 (the "License"); +## you may not use this file except in compliance with the License. +## You may obtain a copy of the License at +## +## http://www.apache.org/licenses/LICENSE-2.0 +## +## Unless required by applicable law or agreed to in writing, software +## distributed under the License is distributed on an "AS IS" BASIS, +## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +## See the License for the specific language governing permissions and +## limitations under the License. + +<% + import math + import string + from padrick.Model.PadSignal import SignalDirection + from natsort import natsorted + + def sort_by_name(seq): + return natsorted(seq, lambda x: x.name) + +%> +{ +% for line in header_text.splitlines(): + # ${line} +% endfor + name: "${padframe.name}_${pad_domain.name}_config" + clock_primary: "clk_i" + reset_primary: "rst_ni" + bus_interfaces: [ + { protocol: "reg_iface", direction: "device"} + ] + regwidth: 32, + registers: [ + {skipto: "${start_address_offset}"}, + { + name: INFO + desc: "Read-only IP Information register" + swaccess: "ro" + hwaccess: "hro" + fields: [ + { + bits: "15:0" + name: HW_VERSION + desc: "Hardware version ID." + resval: ${hw_version} + }, + { + bits:"31:16" + name: PADCOUNT + desc: "The number of muxable pads in this IP." + resval: "${len([pad for pad in pad_domain.pad_list if not pad.is_static])}" + } + ] + } +% for pad in pad_domain.pad_list: +% if pad.dynamic_pad_signals_soc2pad: +<% + # Calculate how many config registers we need to accomodate all dynamic + # pad signals that need a register. + total_dynamic_padsignal_bits = sum([signal.size for signal in pad.dynamic_pad_signals]) + num_cfg_regs = total_dynamic_padsignal_bits//32 + 1 + + # Group pad_signals by config register + pad_signals_grouping = [] + current_signal_grouping = [] + current_group_size = 0 + for pad_signal in pad.dynamic_pad_signals_soc2pad: + if current_group_size + pad_signal.size > 32: + # Start new grouping + pad_signals_grouping.append(current_signal_grouping) + current_group_size = 0 + current_signal_grouping = [(pad_signal, (pad_signal.size-1,0))] + else: + current_signal_grouping.append((pad_signal, (current_group_size + pad_signal.size-1, current_group_size))) + current_group_size = current_group_size + pad_signal.size + pad_signals_grouping.append(current_signal_grouping) + + # Convert the config register index to a capital letter index e.g. 1 -> A, 2 -> B, 3->C + # If there are more then 26 config registers needed, use another character + def cfg_suffix(idx: int): + cfg_suffix = "" + if num_cfg_regs > 1: + num_cfg_reg_chars = math.ceil(math.log(num_cfg_regs, 26)) + for k in range(num_cfg_reg_chars): + cfg_suffix = string.ascii_uppercase[idx % 26]+cfg_suffix + idx = idx // 26 + return cfg_suffix +%> \ +% for i, pad_signals in enumerate(pad_signals_grouping): + { + name: ${pad.name.upper()}_CFG${cfg_suffix(i)} + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ +% for pad_signal, (msb, lsb) in pad_signals: + { + bits: "${str(msb)+':'+str(lsb) if msb != lsb else lsb}" + name: ${pad_signal.name} + desc: ''' + ${pad_signal.description if pad_signal.description else ""} + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "${pad.connections.get(pad_signal, pad_signal.default_reset_value) if pad.connections else pad_signal.default_reset_value}" + }, +% endfor + ] + } +% endfor +% endif +% if pad.dynamic_pad_signals: +<% + # The reset value depends on whether the dynamic pad has a default_port or not. If it doesn't the resvalue is + # zero (connect to register file value). If it has one, we need to find the right select value that corresponds + # to the port. + connectable_ports = [] + idx = 0 + reset_value = 0 + for port_group in sort_by_name(pad_domain.port_groups): + for port in sort_by_name(port_group.ports): + if port.mux_groups.intersection(pad.mux_groups): + connectable_ports.append((port_group, port)) + idx += 1 + if pad.default_port and pad.default_port[0].name == port_group.name and pad.default_port[1].name == port.name: + reset_value = idx +%> + { + name: ${pad.name.upper()}_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad ${pad.name}. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: ${reset_value} + fields: [ + { + bits: "${max(0,math.ceil(math.log2(len(pad_domain.get_ports_in_mux_groups(pad.mux_groups))+1))-1)}:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} +%for idx, (port_group, port) in enumerate(connectable_ports): + { value: "${idx+1}", name: "port_${port_group.name}_${port.name.lower()}", desc: "Connect port ${port.name} from port group ${port_group.name} to this pad." } +%endfor + ] + } + ] + } +% endif + +% endfor + ] +} diff --git a/hw/padframe/custom_templates/rtl_templates/Bender.yml.mako b/hw/padframe/custom_templates/rtl_templates/Bender.yml.mako new file mode 100644 index 00000000..0195272b --- /dev/null +++ b/hw/padframe/custom_templates/rtl_templates/Bender.yml.mako @@ -0,0 +1,45 @@ +## Manuel Eggimann +## +## Copyright (C) 2021-2022 ETH Zürich +## +## Licensed under the Apache License, Version 2.0 (the "License"); +## you may not use this file except in compliance with the License. +## You may obtain a copy of the License at +## +## http://www.apache.org/licenses/LICENSE-2.0 +## +## Unless required by applicable law or agreed to in writing, software +## distributed under the License is distributed on an "AS IS" BASIS, +## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +## See the License for the specific language governing permissions and +## limitations under the License. + +% for line in header_text.splitlines(): +# ${line} +% endfor +package: + name: ${padframe.name}_${padframe.user_attr['target_platform']} + authors: + - "Padrick" + +dependencies: + register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.1 } + common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } + +export_include_dirs: +- include + +sources: + - target: ${padframe.user_attr['target_platform']} + files: + - src/pkg_${padframe.name}.sv + % for pad_domain in padframe.pad_domains: + - src/pkg_internal_${padframe.name}_${pad_domain.name}.sv + - src/${padframe.name}_${pad_domain.name}_config_reg_pkg.sv + - src/${padframe.name}_${pad_domain.name}_config_reg_top.sv + - src/${padframe.name}_${pad_domain.name}_pads.sv + - src/${padframe.name}_${pad_domain.name}_muxer.sv + - src/${padframe.name}_${pad_domain.name}.sv + % endfor + - src/${padframe.name}.sv + diff --git a/hw/padframe/custom_templates/rtl_templates/assign.svh.mako b/hw/padframe/custom_templates/rtl_templates/assign.svh.mako new file mode 100644 index 00000000..0d4473c9 --- /dev/null +++ b/hw/padframe/custom_templates/rtl_templates/assign.svh.mako @@ -0,0 +1,58 @@ +## Manuel Eggimann +## +## Copyright (C) 2021-2022 ETH Zürich +## +## Licensed under the Apache License, Version 2.0 (the "License"); +## you may not use this file except in compliance with the License. +## You may obtain a copy of the License at +## +## http://www.apache.org/licenses/LICENSE-2.0 +## +## Unless required by applicable law or agreed to in writing, software +## distributed under the License is distributed on an "AS IS" BASIS, +## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +## See the License for the specific language governing permissions and +## limitations under the License. + +% for line in header_text.splitlines(): +// ${line} +% endfor + +// Assignment Macros +// Assigns all members of port struct to another struct with same names but potentially different order + + +%for pad_domain in padframe.pad_domains: +%for port_group in pad_domain.port_groups: +<% +sig_name_aliases = {} +for port in port_group.ports: + if port.user_attr and 'port_signal_aliases' in port.user_attr: + sig_name_aliases.update(port.user_attr['port_signal_aliases']) +%> + +%if port_group.port_signals_pads2soc: +`define ASSIGN_${port_group.name.upper()}_PAD2SOC(load, driver) ${"\\"} +%for signal in port_group.port_signals_pads2soc: +%if signal.name in sig_name_aliases: + assign load.${sig_name_aliases[signal.name]} = driver.${signal.name}; ${"\\"} +%else: + assign load.${signal.name} = driver.${signal.name}; ${"\\"} +%endif +%endfor +%endif + +%if port_group.port_signals_soc2pads: +`define ASSIGN_${port_group.name.upper()}_SOC2PAD(load, driver) ${"\\"} +%for signal in port_group.port_signals_soc2pads: +%if signal.name in sig_name_aliases: + assign load.${signal.name} = driver.${sig_name_aliases[signal.name]}; ${"\\"} +%else: + assign load.${signal.name} = driver.${signal.name}; ${"\\"} +%endif +%endfor +%endif + +%endfor + +%endfor diff --git a/hw/padframe/custom_templates/rtl_templates/padframe.sv.mako b/hw/padframe/custom_templates/rtl_templates/padframe.sv.mako new file mode 100644 index 00000000..33330606 --- /dev/null +++ b/hw/padframe/custom_templates/rtl_templates/padframe.sv.mako @@ -0,0 +1,162 @@ +## Manuel Eggimann +## +## Copyright (C) 2021-2022 ETH Zürich +## +## Licensed under the Apache License, Version 2.0 (the "License"); +## you may not use this file except in compliance with the License. +## You may obtain a copy of the License at +## +## http://www.apache.org/licenses/LICENSE-2.0 +## +## Unless required by applicable law or agreed to in writing, software +## distributed under the License is distributed on an "AS IS" BASIS, +## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +## See the License for the specific language governing permissions and +## limitations under the License. + +% for line in header_text.splitlines(): +// ${line} +% endfor +module ${padframe.name} + import pkg_${padframe.name}::*; +#( + parameter int unsigned AW = 32, + parameter int unsigned DW = 32, + parameter type req_t = logic, // reg_interface request type + parameter type resp_t = logic, // reg_interface response type + parameter logic [DW-1:0] DecodeErrRespData = 32'hdeadda7a, + localparam int unsigned NGPIO = ${padframe.user_attr['num_gpios']} +)( + input logic clk_i, + input logic rst_ni, +% if any([pad_domain.override_signals for pad_domain in padframe.pad_domains]): + input override_signals_t override_signals, +% endif +% if any([pad_domain.static_connection_signals_pad2soc for pad_domain in padframe.pad_domains]): + output static_connection_signals_pad2soc_t static_connection_signals_pad2soc, +% endif +% if any([pad_domain.static_connection_signals_soc2pad for pad_domain in padframe.pad_domains]): + input static_connection_signals_soc2pad_t static_connection_signals_soc2pad, +% endif +% if any([port_group.port_signals_soc2pads for pad_domain in padframe.pad_domains for port_group in pad_domain.port_groups]): + output port_signals_pad2soc_t port_signals_pad2soc, +% endif +% if any([port_group.port_signals_soc2pads for pad_domain in padframe.pad_domains for port_group in pad_domain.port_groups]): + input port_signals_soc2pad_t port_signals_soc2pad, +% endif + // Landing Pads +% for pad_domain in padframe.pad_domains: +% for pad in pad_domain.pad_list: +% if not(pad.user_attr and 'custom_toplevel_connection' in pad.user_attr and pad.user_attr['custom_toplevel_connection']): +% for signal in pad.landing_pads: + inout wire logic ${pad.name}, +% endfor +% endif +% endfor +% endfor +## The muxed IO pads in PULPissimo are treated specially. We render them as an array of wires to make the connections easier. + inout wire [NGPIO-1:0] pad_io, + // Config Interface + input req_t config_req_i, + output resp_t config_rsp_o + ); + + +% for pad_domain in padframe.pad_domains: + req_t ${pad_domain.name}_config_req; + resp_t ${pad_domain.name}_config_resp; + ${padframe.name}_${pad_domain.name} #( + .req_t(req_t), + .resp_t(resp_t) + ) i_${pad_domain.name} ( + .clk_i, + .rst_ni, +% if pad_domain.override_signals: + .override_signals_i(override_signals.${pad_domain.name}), +% endif +% if pad_domain.static_connection_signals_pad2soc: + .static_connection_signals_pad2soc(static_connection_signals_pad2soc.${pad_domain.name}), +% endif +% if pad_domain.static_connection_signals_soc2pad: + .static_connection_signals_soc2pad(static_connection_signals_soc2pad.${pad_domain.name}), +% endif +% if any([port_group.port_signals_pads2soc for port_group in pad_domain.port_groups]): + .port_signals_pad2soc_o(port_signals_pad2soc.${pad_domain.name}), +% endif +% if any([port_group.port_signals_soc2pads for port_group in pad_domain.port_groups]): + .port_signals_soc2pad_i(port_signals_soc2pad.${pad_domain.name}), +% endif +% for pad in pad_domain.pad_list: +% if not(pad.user_attr and 'custom_toplevel_connection' in pad.user_attr and pad.user_attr['custom_toplevel_connection']): +% for signal in pad.landing_pads: + .pad_${pad.name}_${signal.name}(${pad.name}), +% endfor +% endif +% endfor +% for i in range(padframe.user_attr['num_gpios']): + .pad_pad_io${f'{i:02d}'}_${signal.name}(pad_io[${i}]), +% endfor + .config_req_i(${pad_domain.name}_config_req), + .config_rsp_o(${pad_domain.name}_config_resp) + ); + +% endfor +<% + import math + config_req_o_collection = ", ".join(f"{pad_domain.name}_config_req" for pad_domain in reversed(padframe.pad_domains)) + config_resp_i_collection = ", ".join(f"{pad_domain.name}_config_resp" for pad_domain in reversed(padframe.pad_domains)) + reg_addr_width = math.ceil(math.log2(address_space_size+1)) + num_pad_domains = len(padframe.pad_domains) +%> + localparam int unsigned NUM_PAD_DOMAINS = ${num_pad_domains}; + localparam int unsigned REG_ADDR_WIDTH = ${reg_addr_width}; + typedef struct packed { + int unsigned idx; + logic [REG_ADDR_WIDTH-1:0] start_addr; + logic [REG_ADDR_WIDTH-1:0] end_addr; + } addr_rule_t; + + localparam addr_rule_t[NUM_PAD_DOMAINS-1:0] ADDR_DEMUX_RULES = '{ +% for idx, pad_domain in enumerate(padframe.pad_domains): + '{ idx: ${idx}, start_addr: ${reg_addr_width}'d${address_ranges[pad_domain.name][0]}, end_addr: ${reg_addr_width}'d${address_ranges[pad_domain.name][1]}}${"," if idx != num_pad_domains-1 else ""} +% endfor + }; + logic[$clog2(NUM_PAD_DOMAINS+1)-1:0] pad_domain_sel; // +1 since there is an additional error slave + addr_decode #( + .NoIndices(NUM_PAD_DOMAINS+1), + .NoRules(NUM_PAD_DOMAINS), + .addr_t(logic[REG_ADDR_WIDTH-1:0]), + .rule_t(addr_rule_t) + ) i_addr_decode( + .addr_i(config_req_i.addr[REG_ADDR_WIDTH-1:0]), + .addr_map_i(ADDR_DEMUX_RULES), + .dec_valid_o(), + .dec_error_o(), + .idx_o(pad_domain_sel), + .en_default_idx_i(1'b1), + .default_idx_i(${math.ceil(math.log2(num_pad_domains+1))}'d${num_pad_domains}) // The last entry is the error slave + ); + + req_t error_slave_req; + resp_t error_slave_rsp; + + // Config Interface demultiplexing + reg_demux #( + .NoPorts(NUM_PAD_DOMAINS+1), //+1 for the error slave + .req_t(req_t), + .rsp_t(resp_t) + ) i_config_demuxer ( + .clk_i, + .rst_ni, + .in_select_i(pad_domain_sel), + .in_req_i(config_req_i), + .in_rsp_o(config_rsp_o), + .out_req_o({error_slave_req, ${config_req_o_collection}}), + .out_rsp_i({error_slave_rsp, ${config_resp_i_collection}}) + ); + + assign error_slave_rsp.error = 1'b1; + assign error_slave_rsp.rdata = DecodeErrRespData; + assign error_slave_rsp.ready = 1'b1; + +endmodule diff --git a/hw/padframe/fpga_config/fpga_pad_signals.yml b/hw/padframe/fpga_config/fpga_pad_signals.yml new file mode 100644 index 00000000..6261d105 --- /dev/null +++ b/hw/padframe/fpga_config/fpga_pad_signals.yml @@ -0,0 +1,43 @@ +# Definition of pad signals that are common to all target platforms. +- name: pad + description: "The inout wire of the IO pad that connect to the toplevel port of the SoC" + size: 1 + kind: pad + +- name: chip2pad + description: "Connects to pad's TX driver" + size: 1 + kind: input + conn_type: dynamic + default_reset_value: 0 + default_static_value: 1'b0 + +- name: pad2chip + description: "The signal that connects to the pad's RX buffer" + size: 1 + kind: output + conn_type: dynamic + +- name: rx_en + description: "RX enable, active high" + size: 1 + kind: input + conn_type: dynamic + default_reset_value: 1 + default_static_value: 1'b1 + +- name: tx_en + description: "TX driver enable, active high" + size: 1 + kind: input + conn_type: dynamic + default_reset_value: 0 + default_static_value: 1'b0 + +# - name: pull_en +# description: "Enable pull up/down (depends on the selected IO pad) resistor, active-high" +# size: 1 +# kind: input +# conn_type: dynamic +# default_reset_value: 0 +# default_static_value: 1'b0 diff --git a/hw/padframe/fpga_config/fpga_pad_types.yml b/hw/padframe/fpga_config/fpga_pad_types.yml new file mode 100644 index 00000000..774dd209 --- /dev/null +++ b/hw/padframe/fpga_config/fpga_pad_types.yml @@ -0,0 +1,51 @@ +# IO pad templates for the Xilinx pads. These are used in FPGA synthesis. + +- name: pull_down_pad # user defined name of the pad. Used to reference + # it in the pad_list + description: | + Generic behavioral model of an IO Pad with pull down resistors. The pad is + defined in the tech_cells_generic repository and only used in simulation. + Define your own pad types for a custom tapeout. + template: | + (* PULLDOWN = "YES" *) + IOBUF ${instance_name} ( + .T ( ~${conn["tx_en"]} ), + .I ( ${conn["chip2pad"]} ), + .O ( ${conn["pad2chip"]} ), + .IO( ${conn["pad"]} ) + ); + + pad_signals: !include fpga_config/fpga_pad_signals.yml + +- name: pull_up_pad # user defined name of the pad. Used to reference + # it in the pad_list + description: | + Generic behavioral model of an IO Pad with pull down resistors. The pad is + defined in the tech_cells_generic repository and only used in simulation. + Define your own pad types for a custom tapeout. + template: | + (* PULLUP = "YES" *) + IOBUF ${instance_name} ( + .T ( ~${conn["tx_en"]} ), + .I ( ${conn["chip2pad"]} ), + .O ( ${conn["pad2chip"]} ), + .IO( ${conn["pad"]} ) + ); + + pad_signals: !include fpga_config/fpga_pad_signals.yml + +- name: direct_input + description: | + Direct connection - no IO pad, requires user to define the IO pad + template: | + assign ${conn["pad2chip"]} = ${conn["pad"]}; + pad_signals: + - name: pad2chip + description: "input signal (output from pad)" + size: 1 + kind: output + conn_type: dynamic + - name: pad + description: "pad signal" + size: 1 + kind: pad diff --git a/hw/padframe/fpga_config/fpga_pads.yml b/hw/padframe/fpga_config/fpga_pads.yml new file mode 100644 index 00000000..b4ac1be3 --- /dev/null +++ b/hw/padframe/fpga_config/fpga_pads.yml @@ -0,0 +1,154 @@ +# Specification of how many and what kind of IO pads to instantiate in the padframe +- name: pad_ref_clk + description: "32kHz reference clock for on-chip PLLs" + pad_type: direct_input + is_static: true + connections: + pad2chip: ref_clk + +- name: pad_clk_byp_en + description: "PLL clock bypass enable, active-high. If asserted the PLLs VCO is bypassed and the system uses the ref_clk directly" + pad_type: direct_input + is_static: true + connections: + pad2chip: clk_byp_en + +- name: pad_reset_n + description: "Active-low asynchronous reset. Internally synchronized to rising edge." + pad_type: direct_input + is_static: true + connections: + pad2chip: rst_n + +- name: pad_bootsel0 + description: "Selects boot behavior of the chip. (0b00 -> boot from SPI flash, 0b01 -> JTAG boot, 0b10 -> Hyperflash boot)" + pad_type: pull_up_pad + is_static: true + connections: + pad2chip: bootsel0 + rx_en: 1'b1 + tx_en: 1'b0 + +- name: pad_bootsel1 + description: "Selects boot behavior of the chip. (0b00 -> boot from SPI flash, 0b01 -> JTAG boot, 0b10 -> Hyperflash boot)" + pad_type: pull_up_pad + is_static: true + connections: + pad2chip: bootsel1 + rx_en: 1'b1 + tx_en: 1'b0 + +- name: pad_jtag_tck + description: "JTAG clock input" + pad_type: pull_up_pad + is_static: true + connections: + pad2chip: jtag_tck + rx_en: 1'b1 + tx_en: 1'b0 + +- name: pad_jtag_trstn + description: "JTAG interface reset (active-low)" + pad_type: pull_up_pad + is_static: true + connections: + pad2chip: jtag_trstn + rx_en: 1'b1 + tx_en: 1'b0 + +- name: pad_jtag_tms + description: "JTAG test mode select" + pad_type: pull_up_pad + is_static: true + connections: + pad2chip: jtag_tms + rx_en: 1'b1 + tx_en: 1'b0 + +- name: pad_jtag_tdi + description: "JTAG interface data input" + pad_type: pull_up_pad + is_static: true + connections: + pad2chip: jtag_tdi + rx_en: 1'b1 + tx_en: 1'b0 + +- name: pad_jtag_tdo + description: "JTAG interface data output" + pad_type: pull_up_pad + is_static: true + connections: + chip2pad: jtag_tdo + rx_en: 1'b0 + tx_en: 1'b1 + +- name: pad_hyper_csn{i:1d} + description: "Hyperbus chip select (active-low)" + pad_type: pull_up_pad + multiple: 2 + is_static: true + connections: + chip2pad: hyper_cs{i:1d}_no + rx_en: 1'b0 + tx_en: 1'b1 + +- name: pad_hyper_reset_n + description: "Hyperbus reset (active-low)" + pad_type: pull_up_pad + is_static: true + connections: + chip2pad: hyper_reset_no + rx_en: 1'b0 + tx_en: 1'b1 + +- name: pad_hyper_ck + description: "Hyperbus differential clock" + pad_type: pull_up_pad + is_static: true + connections: + chip2pad: hyper_ck + rx_en: 1'b0 + tx_en: 1'b1 + +- name: pad_hyper_ckn + description: "Hyperbus differential clock" + pad_type: pull_up_pad + is_static: true + connections: + chip2pad: hyper_ckn + rx_en: 1'b0 + tx_en: 1'b1 + +- name: pad_hyper_dq{i} + description: "Hyperbus data line" + multiple: 8 + pad_type: pull_up_pad + is_static: true + connections: + pad2chip: hyper_dq{i}_i + chip2pad: hyper_dq{i}_o + tx_en: hyper_dq_oe + rx_en: ~hyper_dq_oe + +- name: pad_hyper_rwds + description: "Hyperbus read/write data strobe" + pad_type: pull_up_pad + is_static: true + connections: + chip2pad: hyper_rwds_o + pad2chip: hyper_rwds_i + rx_en: ~hyper_rwds_oe + tx_en: hyper_rwds_oe + +- name: pad_io{i:2d} + mux_groups: [all_muxed_ios, self] + description: "General purpose pad that can expose various internal peripherals" + multiple: !include gpio_count.txt + pad_type: pull_up_pad + is_static: false + default_port: gpio.gpio{i:2d} + user_attr: + custom_toplevel_connection: True + + diff --git a/hw/padframe/fpga_padframe_config_top.yml b/hw/padframe/fpga_padframe_config_top.yml new file mode 100644 index 00000000..711c19bf --- /dev/null +++ b/hw/padframe/fpga_padframe_config_top.yml @@ -0,0 +1,48 @@ +#----------------------------------------------------------------------------- +# Title : Padframe Configuration File +# ----------------------------------------------------------------------------- +# File : padframe_config_generic.yml +# Author : Manuel Eggimann +# Created : 04.12.2022 +# ----------------------------------------------------------------------------- +# Description : +# +# This file descibes the padframe and IO multiplexing strategy of PULPissimo. +# The file is parsed by a CLI tool called padrick that auto-generates the IO +# multiplexing and pad instantation IP automatically. This files is intended to +# be used with the generic IO pad models from the pulp tech_cells_generic +# repository. You can use this file as a template to create a tape-out specific +# config file for your target technology. +# +# You can find more information about the syntax of this file on +# https://padrick.readthedocs.io/en/latest/ +# +#----------------------------------------------------------------------------- +# Copyright (C) 2022 ETH Zurich, University of Bologna Copyright and related +# rights are licensed under the Solderpad Hardware License, Version 0.51 (the +# "License"); you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law or +# agreed to in writing, software, hardware and materials distributed under this +# License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS +# OF ANY KIND, either express or implied. See the License for the specific +# language governing permissions and limitations under the License. +# SPDX-License-Identifier: SHL-0.51 +# ----------------------------------------------------------------------------- + +manifest_version: 3 +name: pulpissimo_padframe +user_attr: + target_platform: fpga + num_gpios: !include gpio_count.txt +pad_domains: + - name: all_pads + pad_types: + !include fpga_config/fpga_pad_types.yml + + pad_list: + !include fpga_config/fpga_pads.yml + + port_groups: + !include common_peripherals.yml + diff --git a/hw/padframe/gpio_count.txt b/hw/padframe/gpio_count.txt new file mode 100644 index 00000000..f5c89552 --- /dev/null +++ b/hw/padframe/gpio_count.txt @@ -0,0 +1 @@ +32 diff --git a/hw/padframe/padframe_adapter.sv b/hw/padframe/padframe_adapter.sv new file mode 100644 index 00000000..e2fd57d1 --- /dev/null +++ b/hw/padframe/padframe_adapter.sv @@ -0,0 +1,300 @@ +//----------------------------------------------------------------------------- +// Title : Wrapper for the auto-generate padframe +//----------------------------------------------------------------------------- +// File : padframe_wrap.sv +// Author : Manuel Eggimann +// Created : 05.12.2022 +//----------------------------------------------------------------------------- +// Description : +// This module wraps the auto-generates padframe and assigns the control/IO +// signals from the udam structs to the padframe generated structs. +//----------------------------------------------------------------------------- +// Copyright (C) 2013-2022 ETH Zurich, University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +//----------------------------------------------------------------------------- + +module padframe_adapter #( + /// Have a look at the README in the GPIO repo in order to change the number of GPIOs. + localparam int unsigned NGPIO = gpio_reg_pkg::GPIOCount +)( + input logic soc_clk_i, + input logic soc_rstn_synced_i, + APB.Slave apb_cfg_slave, + // IO Pad Signals + inout wire pad_ref_clk, + inout wire pad_clk_byp_en, + inout wire pad_reset_n, + inout wire pad_bootsel0, + inout wire pad_bootsel1, + inout wire pad_jtag_tck, + inout wire pad_jtag_trstn, + inout wire pad_jtag_tms, + inout wire pad_jtag_tdi, + inout wire pad_jtag_tdo, + inout wire [1:0] pad_hyper_csn, + inout wire pad_hyper_reset_n, + inout wire pad_hyper_ck, + inout wire pad_hyper_ckn, + inout wire [7:0] pad_hyper_dq, + inout wire pad_hyper_rwds, + inout wire [NGPIO-1:0] pad_io, + // SoC IO Signals + output logic ref_clk_o, + output logic global_rst_no, + output logic global_clk_byp_o, + output logic [1:0] bootsel_o, + output logic jtag_tck_o, + output logic jtag_trst_no, + output logic jtag_tms_o, + output logic jtag_tdi_o, + input logic jtag_tdo_i, + + // Timer PWM output signals (4 channels per timer) + input logic [3:0] timer_ch0_i, + input logic [3:0] timer_ch1_i, + input logic [3:0] timer_ch2_i, + input logic [3:0] timer_ch3_i, + + // GPIO + output logic [NGPIO-1:0] gpio_o, + input logic [NGPIO-1:0] gpio_i, + input logic [NGPIO-1:0] gpio_tx_en_i, + + // uDMA Peripherals + // UART + input uart_pkg::uart_to_pad_t [udma_cfg_pkg::N_UART-1:0] uart_to_pad_i, + output uart_pkg::pad_to_uart_t [udma_cfg_pkg::N_UART-1:0] pad_to_uart_o, + // I2C + input i2c_pkg::i2c_to_pad_t [udma_cfg_pkg::N_I2C-1:0] i2c_to_pad_i, + output i2c_pkg::pad_to_i2c_t [udma_cfg_pkg::N_I2C-1:0] pad_to_i2c_o, + // SDIO + input sdio_pkg::sdio_to_pad_t [udma_cfg_pkg::N_SDIO-1:0] sdio_to_pad_i, + output sdio_pkg::pad_to_sdio_t [udma_cfg_pkg::N_SDIO-1:0] pad_to_sdio_o, + // I2S + input i2s_pkg::i2s_to_pad_t [udma_cfg_pkg::N_I2S-1:0] i2s_to_pad_i, + output i2s_pkg::pad_to_i2s_t [udma_cfg_pkg::N_I2S-1:0] pad_to_i2s_o, + // QSPI + input qspi_pkg::qspi_to_pad_t [udma_cfg_pkg::N_QSPIM-1:0] qspi_to_pad_i, + output qspi_pkg::pad_to_qspi_t [udma_cfg_pkg::N_QSPIM-1:0] pad_to_qspi_o, + // CPI + output cpi_pkg::pad_to_cpi_t [udma_cfg_pkg::N_CPI-1:0] pad_to_cpi_o, + // HYPER + input hyper_pkg::hyper_to_pad_t [udma_cfg_pkg::N_HYPER-1:0] hyper_to_pad_i, + output hyper_pkg::pad_to_hyper_t [udma_cfg_pkg::N_HYPER-1:0] pad_to_hyper_o +); + import pkg_pulpissimo_padframe::*; + `include "pulpissimo_padframe/assign.svh" + `include "register_interface/typedef.svh" + `include "register_interface/assign.svh" + + // Convert APB to regbus + typedef logic [31:0] addr_t; + typedef logic [31:0] data_t; + typedef logic [3:0] strb_t; + `REG_BUS_TYPEDEF_ALL(regbus, addr_t, data_t, strb_t); + regbus_req_t s_cfg_regbus_req; + regbus_rsp_t s_cfg_regbus_rsp; + + REG_BUS #(.ADDR_WIDTH(32), .DATA_WIDTH(32)) s_cfg_regbus(.clk_i(soc_clk_i)); + apb_to_reg i_apb_to_regbus ( + .clk_i ( soc_clk_i ), + .rst_ni ( soc_rstn_synced_i ), + .penable_i ( apb_cfg_slave.penable ), + .pwrite_i ( apb_cfg_slave.pwrite ), + .paddr_i ( apb_cfg_slave.paddr ), + .psel_i ( apb_cfg_slave.psel ), + .pwdata_i ( apb_cfg_slave.pwdata ), + .prdata_o ( apb_cfg_slave.prdata ), + .pready_o ( apb_cfg_slave.pready ), + .pslverr_o ( apb_cfg_slave.pslverr ), + .reg_o ( s_cfg_regbus.out ) + ); + + `REG_BUS_ASSIGN_TO_REQ(s_cfg_regbus_req, s_cfg_regbus) + `REG_BUS_ASSIGN_FROM_RSP(s_cfg_regbus, s_cfg_regbus_rsp) + + // Assign signals to structs Here we make use of the autogenerates assign + // macros from padrick. To use them we occasionally have to create + // intermediate helper structs. Unfortunately, there is no easy way to connect + // a parametric number of peripherals to padrick generated IPs because padrick + // does not generate parametric ports (would make the software way more + // complex). We thus only check, if the number of peripherals configured in + // the PULP_IO package matches the number we expect and issue an elaboration + // error if it doesn't. Maybe this part can be improved somehow in the future. + localparam N_CONNECTED_QSPIM = 1; + localparam N_CONNECTED_UART = 1; + localparam N_CONNECTED_I2C = 1; + localparam N_CONNECTED_SDIO = 1; + localparam N_CONNECTED_CPI = 1; + localparam N_CONNECTED_HYPER = 1; + localparam N_CONNECTED_I2S = 0; + + if (udma_cfg_pkg::N_QSPIM != N_CONNECTED_QSPIM) + $error("The number of QSPIM peripherals is %0d but we are only connecting %0d. Please change the padframe wrapper file.", udma_cfg_pkg::N_QSPIM); + if (udma_cfg_pkg::N_UART != N_CONNECTED_UART) + $error("The number of UART is %0d but we are only connecting %0d. Please change the padframe wrapper file.", udma_cfg_pkg::N_UART, N_CONNECTED_UART); + if (udma_cfg_pkg::N_I2C != N_CONNECTED_I2C) + $error("The number of I2C is %0d but we are only connecting %0d. Please change the padframe wrapper file.", udma_cfg_pkg::N_I2C, N_CONNECTED_I2C); + if (udma_cfg_pkg::N_SDIO != N_CONNECTED_SDIO) + $error("The number of SDIO is %0d but we are only connecting %0d. Please change the padframe wrapper file.", udma_cfg_pkg::N_SDIO, N_CONNECTED_SDIO); + if (udma_cfg_pkg::N_CPI != N_CONNECTED_CPI) + $error("The number of CPI is %0d but we are only connecting %0d. Please change the padframe wrapper file.", udma_cfg_pkg::N_CPI, N_CONNECTED_CPI); + if (udma_cfg_pkg::N_HYPER != N_CONNECTED_HYPER) + $error("The number of HYPER is %0d but we are only connecting %0d. Please change the padframe wrapper file.", udma_cfg_pkg::N_HYPER, N_CONNECTED_HYPER); + if (udma_cfg_pkg::N_I2S != N_CONNECTED_I2S) + $error("The number of I2S is %0d but we are only connecting %0d. Please change the padframe wrapper file.", udma_cfg_pkg::N_I2S, N_CONNECTED_I2S); + + static_connection_signals_soc2pad_t s_static_connections_soc2pad; + static_connection_signals_pad2soc_t s_static_connections_pad2soc; + // Static Connections + assign global_clk_byp_o = s_static_connections_pad2soc.all_pads.clk_byp_en; + assign global_rst_no = s_static_connections_pad2soc.all_pads.rst_n; + assign ref_clk_o = s_static_connections_pad2soc.all_pads.ref_clk; + assign bootsel_o[0] = s_static_connections_pad2soc.all_pads.bootsel0; + assign bootsel_o[1] = s_static_connections_pad2soc.all_pads.bootsel1; + // JTAG + assign jtag_tck_o = s_static_connections_pad2soc.all_pads.jtag_tck; + assign jtag_tdi_o = s_static_connections_pad2soc.all_pads.jtag_tdi; + assign jtag_tms_o = s_static_connections_pad2soc.all_pads.jtag_tms; + assign jtag_trst_no = s_static_connections_pad2soc.all_pads.jtag_trstn; + assign s_static_connections_soc2pad.all_pads.jtag_tdo = jtag_tdo_i; + // HyperFlash/HyperRAM + assign s_static_connections_soc2pad.all_pads.hyper_ck = hyper_to_pad_i[0].hyper_ck_o; + assign s_static_connections_soc2pad.all_pads.hyper_ckn = hyper_to_pad_i[0].hyper_ck_no; + assign s_static_connections_soc2pad.all_pads.hyper_cs0_no = hyper_to_pad_i[0].hyper_cs0_no; + assign s_static_connections_soc2pad.all_pads.hyper_cs1_no = hyper_to_pad_i[0].hyper_cs1_no; + assign s_static_connections_soc2pad.all_pads.hyper_dq0_o = hyper_to_pad_i[0].hyper_dq0_o; + assign s_static_connections_soc2pad.all_pads.hyper_dq1_o = hyper_to_pad_i[0].hyper_dq1_o; + assign s_static_connections_soc2pad.all_pads.hyper_dq2_o = hyper_to_pad_i[0].hyper_dq2_o; + assign s_static_connections_soc2pad.all_pads.hyper_dq3_o = hyper_to_pad_i[0].hyper_dq3_o; + assign s_static_connections_soc2pad.all_pads.hyper_dq4_o = hyper_to_pad_i[0].hyper_dq4_o; + assign s_static_connections_soc2pad.all_pads.hyper_dq5_o = hyper_to_pad_i[0].hyper_dq5_o; + assign s_static_connections_soc2pad.all_pads.hyper_dq6_o = hyper_to_pad_i[0].hyper_dq6_o; + assign s_static_connections_soc2pad.all_pads.hyper_dq7_o = hyper_to_pad_i[0].hyper_dq7_o; + assign s_static_connections_soc2pad.all_pads.hyper_dq_oe = hyper_to_pad_i[0].hyper_dq_oe; + assign s_static_connections_soc2pad.all_pads.hyper_reset_no = hyper_to_pad_i[0].hyper_reset_no; + assign s_static_connections_soc2pad.all_pads.hyper_rwds_o = hyper_to_pad_i[0].hyper_rwds_o; + assign s_static_connections_soc2pad.all_pads.hyper_rwds_oe = hyper_to_pad_i[0].hyper_rwds_oe; + assign pad_to_hyper_o[0].hyper_dq0_i = s_static_connections_pad2soc.all_pads.hyper_dq0_i; + assign pad_to_hyper_o[0].hyper_dq1_i = s_static_connections_pad2soc.all_pads.hyper_dq1_i; + assign pad_to_hyper_o[0].hyper_dq2_i = s_static_connections_pad2soc.all_pads.hyper_dq2_i; + assign pad_to_hyper_o[0].hyper_dq3_i = s_static_connections_pad2soc.all_pads.hyper_dq3_i; + assign pad_to_hyper_o[0].hyper_dq4_i = s_static_connections_pad2soc.all_pads.hyper_dq4_i; + assign pad_to_hyper_o[0].hyper_dq5_i = s_static_connections_pad2soc.all_pads.hyper_dq5_i; + assign pad_to_hyper_o[0].hyper_dq6_i = s_static_connections_pad2soc.all_pads.hyper_dq6_i; + assign pad_to_hyper_o[0].hyper_dq7_i = s_static_connections_pad2soc.all_pads.hyper_dq7_i; + assign pad_to_hyper_o[0].hyper_rwds_i = s_static_connections_pad2soc.all_pads.hyper_rwds_i; + + // Muxed Signals + port_signals_pad2soc_t s_port_signals_pad2soc; + port_signals_soc2pad_t s_port_signals_soc2pad; + + // GPIO Signals + struct packed { + logic [NGPIO-1:0] gpio_in; + } gpio_pad2soc_load; + + `ASSIGN_GPIO_PAD2SOC(gpio_pad2soc_load, s_port_signals_pad2soc.all_pads.gpio) + assign gpio_o = gpio_pad2soc_load.gpio_in; + struct packed { + logic [NGPIO-1:0] gpio_out; + logic [NGPIO-1:0] gpio_tx_en; + } gpio_soc2pad_driver; + + assign gpio_soc2pad_driver.gpio_out = gpio_i; + assign gpio_soc2pad_driver.gpio_tx_en = gpio_tx_en_i; + `ASSIGN_GPIO_SOC2PAD(s_port_signals_soc2pad.all_pads.gpio, gpio_soc2pad_driver) + + // Timer Channels + typedef struct packed { + logic [3:0] out; + } timer_soc2pad_driver_t; + + timer_soc2pad_driver_t[3:0] timer_soc2pad_driver; + assign timer_soc2pad_driver[0].out = timer_ch0_i; + assign timer_soc2pad_driver[1].out = timer_ch1_i; + assign timer_soc2pad_driver[2].out = timer_ch2_i; + assign timer_soc2pad_driver[3].out = timer_ch3_i; + `ASSIGN_TIMER0_SOC2PAD(s_port_signals_soc2pad.all_pads.timer0, timer_soc2pad_driver[0]) + `ASSIGN_TIMER1_SOC2PAD(s_port_signals_soc2pad.all_pads.timer1, timer_soc2pad_driver[1]) + `ASSIGN_TIMER2_SOC2PAD(s_port_signals_soc2pad.all_pads.timer2, timer_soc2pad_driver[2]) + `ASSIGN_TIMER3_SOC2PAD(s_port_signals_soc2pad.all_pads.timer3, timer_soc2pad_driver[3]) + + // UART + assign s_port_signals_soc2pad.all_pads.uart0.tx_o = uart_to_pad_i[0].tx_o; + assign pad_to_uart_o[0].rx_i = s_port_signals_pad2soc.all_pads.uart0.rx_i; + + //I2C + `ASSIGN_I2C0_PAD2SOC(pad_to_i2c_o[0], s_port_signals_pad2soc.all_pads.i2c0) + + //SDIO + `ASSIGN_SDIO0_PAD2SOC(pad_to_sdio_o[0], s_port_signals_pad2soc.all_pads.sdio0) + `ASSIGN_SDIO0_SOC2PAD(s_port_signals_soc2pad.all_pads.sdio0, sdio_to_pad_i[0]) + + //I2S + `ASSIGN_I2S0_PAD2SOC(pad_to_i2s_o[0], s_port_signals_pad2soc.all_pads.i2s0) + `ASSIGN_I2S0_SOC2PAD(s_port_signals_soc2pad.all_pads.i2s0, i2s_to_pad_i[0]) + + //QSPI Master + `ASSIGN_QSPIM0_PAD2SOC(pad_to_qspi_o[0], s_port_signals_pad2soc.all_pads.qspim0) + `ASSIGN_QSPIM0_SOC2PAD(s_port_signals_soc2pad.all_pads.qspim0, qspi_to_pad_i[0]) + + //CPI + `ASSIGN_CPI0_PAD2SOC(pad_to_cpi_o[0], s_port_signals_pad2soc.all_pads.cpi0) + + ///////////////////////////////////////// + // Instantiate Auto-generated Padframe // + ///////////////////////////////////////// + + pulpissimo_padframe #( + .AW ( 32 ), + .DW ( 32 ), + .req_t ( regbus_req_t ), + .resp_t ( regbus_rsp_t ) + ) i_pulpissimo_pads ( + .clk_i ( soc_clk_i ), + .rst_ni ( soc_rstn_synced_i ), + .config_req_i ( s_cfg_regbus_req ), + .config_rsp_o ( s_cfg_regbus_rsp ), + .static_connection_signals_pad2soc ( s_static_connections_pad2soc ), + .static_connection_signals_soc2pad ( s_static_connections_soc2pad ), + .port_signals_pad2soc ( s_port_signals_pad2soc ), + .port_signals_soc2pad ( s_port_signals_soc2pad ), + .pad_ref_clk, + .pad_clk_byp_en, + .pad_reset_n, + .pad_bootsel0, + .pad_bootsel1, + .pad_jtag_tck, + .pad_jtag_trstn, + .pad_jtag_tms, + .pad_jtag_tdi, + .pad_jtag_tdo, + .pad_hyper_csn0 ( pad_hyper_csn[0] ), + .pad_hyper_csn1 ( pad_hyper_csn[1] ), + .pad_hyper_reset_n, + .pad_hyper_ck, + .pad_hyper_ckn, + .pad_hyper_dq0 ( pad_hyper_dq[0] ), + .pad_hyper_dq1 ( pad_hyper_dq[1] ), + .pad_hyper_dq2 ( pad_hyper_dq[2] ), + .pad_hyper_dq3 ( pad_hyper_dq[3] ), + .pad_hyper_dq4 ( pad_hyper_dq[4] ), + .pad_hyper_dq5 ( pad_hyper_dq[5] ), + .pad_hyper_dq6 ( pad_hyper_dq[6] ), + .pad_hyper_dq7 ( pad_hyper_dq[7] ), + .pad_hyper_rwds, + .pad_io + ); + + + + +endmodule diff --git a/hw/padframe/padrick_generator_settings.yml b/hw/padframe/padrick_generator_settings.yml new file mode 100644 index 00000000..b5d93074 --- /dev/null +++ b/hw/padframe/padrick_generator_settings.yml @@ -0,0 +1,44 @@ +manifest_version: 3 +rtl_templates: + bender_project_file: + name: Bender.yml Project file + target_file_name: Bender.yml + template: custom_templates/rtl_templates/Bender.yml.mako + skip_generation: false + ipapprox_src_files_yml: + name: IPApprox src_files.yml + template: "" + target_file_name: "" + skip_generation: True + ipapprox_ips_list_yml: + name: IPApprox ips_list.yml + template: "" + target_file_name: "" + skip_generation: True + assign_header_file: + name: Padframe assignment header file + target_file_name: assign.svh + template: custom_templates/rtl_templates/assign.svh.mako + skip_generation: false + toplevel_module: + name: Padframe Top Module + target_file_name: '{padframe.name}.sv' + template: custom_templates/rtl_templates/padframe.sv.mako + skip_generation: false +driver_templates: + regfile_hjson: + name: Register File Specification for {pad_domain.name} + target_file_name: '{padframe.name}_{pad_domain.name}_regs.hjson' + template: custom_templates/driver_templates/regfile.hjson.mako + skip_generation: false + driver_header: + name: Driver header file + target_file_name: '{padframe.name}.h' + template: "" + skip_generation: true + driver_source: + name: Driver implementation file + target_file_name: '{padframe.name}.c' + template: "" + skip_generation: true + diff --git a/hw/padframe/pulpissimo_padframe_fpga_autogen/Bender.yml b/hw/padframe/pulpissimo_padframe_fpga_autogen/Bender.yml new file mode 100644 index 00000000..0c7c0260 --- /dev/null +++ b/hw/padframe/pulpissimo_padframe_fpga_autogen/Bender.yml @@ -0,0 +1,26 @@ + +# File auto-generated by Padrick unknown +package: + name: pulpissimo_padframe_fpga + authors: + - "Padrick" + +dependencies: + register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.1 } + common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } + +export_include_dirs: +- include + +sources: + - target: fpga + files: + - src/pkg_pulpissimo_padframe.sv + - src/pkg_internal_pulpissimo_padframe_all_pads.sv + - src/pulpissimo_padframe_all_pads_config_reg_pkg.sv + - src/pulpissimo_padframe_all_pads_config_reg_top.sv + - src/pulpissimo_padframe_all_pads_pads.sv + - src/pulpissimo_padframe_all_pads_muxer.sv + - src/pulpissimo_padframe_all_pads.sv + - src/pulpissimo_padframe.sv + diff --git a/hw/padframe/pulpissimo_padframe_fpga_autogen/include/pulpissimo_padframe/assign.svh b/hw/padframe/pulpissimo_padframe_fpga_autogen/include/pulpissimo_padframe/assign.svh new file mode 100644 index 00000000..114c8838 --- /dev/null +++ b/hw/padframe/pulpissimo_padframe_fpga_autogen/include/pulpissimo_padframe/assign.svh @@ -0,0 +1,251 @@ + +// File auto-generated by Padrick unknown + +// Assignment Macros +// Assigns all members of port struct to another struct with same names but potentially different order + + + + +`define ASSIGN_GPIO_PAD2SOC(load, driver) \ + assign load.gpio_in[0] = driver.gpio00_in; \ + assign load.gpio_in[1] = driver.gpio01_in; \ + assign load.gpio_in[2] = driver.gpio02_in; \ + assign load.gpio_in[3] = driver.gpio03_in; \ + assign load.gpio_in[4] = driver.gpio04_in; \ + assign load.gpio_in[5] = driver.gpio05_in; \ + assign load.gpio_in[6] = driver.gpio06_in; \ + assign load.gpio_in[7] = driver.gpio07_in; \ + assign load.gpio_in[8] = driver.gpio08_in; \ + assign load.gpio_in[9] = driver.gpio09_in; \ + assign load.gpio_in[10] = driver.gpio10_in; \ + assign load.gpio_in[11] = driver.gpio11_in; \ + assign load.gpio_in[12] = driver.gpio12_in; \ + assign load.gpio_in[13] = driver.gpio13_in; \ + assign load.gpio_in[14] = driver.gpio14_in; \ + assign load.gpio_in[15] = driver.gpio15_in; \ + assign load.gpio_in[16] = driver.gpio16_in; \ + assign load.gpio_in[17] = driver.gpio17_in; \ + assign load.gpio_in[18] = driver.gpio18_in; \ + assign load.gpio_in[19] = driver.gpio19_in; \ + assign load.gpio_in[20] = driver.gpio20_in; \ + assign load.gpio_in[21] = driver.gpio21_in; \ + assign load.gpio_in[22] = driver.gpio22_in; \ + assign load.gpio_in[23] = driver.gpio23_in; \ + assign load.gpio_in[24] = driver.gpio24_in; \ + assign load.gpio_in[25] = driver.gpio25_in; \ + assign load.gpio_in[26] = driver.gpio26_in; \ + assign load.gpio_in[27] = driver.gpio27_in; \ + assign load.gpio_in[28] = driver.gpio28_in; \ + assign load.gpio_in[29] = driver.gpio29_in; \ + assign load.gpio_in[30] = driver.gpio30_in; \ + assign load.gpio_in[31] = driver.gpio31_in; \ + +`define ASSIGN_GPIO_SOC2PAD(load, driver) \ + assign load.gpio00_out = driver.gpio_out[0]; \ + assign load.gpio00_tx_en = driver.gpio_tx_en[0]; \ + assign load.gpio01_out = driver.gpio_out[1]; \ + assign load.gpio01_tx_en = driver.gpio_tx_en[1]; \ + assign load.gpio02_out = driver.gpio_out[2]; \ + assign load.gpio02_tx_en = driver.gpio_tx_en[2]; \ + assign load.gpio03_out = driver.gpio_out[3]; \ + assign load.gpio03_tx_en = driver.gpio_tx_en[3]; \ + assign load.gpio04_out = driver.gpio_out[4]; \ + assign load.gpio04_tx_en = driver.gpio_tx_en[4]; \ + assign load.gpio05_out = driver.gpio_out[5]; \ + assign load.gpio05_tx_en = driver.gpio_tx_en[5]; \ + assign load.gpio06_out = driver.gpio_out[6]; \ + assign load.gpio06_tx_en = driver.gpio_tx_en[6]; \ + assign load.gpio07_out = driver.gpio_out[7]; \ + assign load.gpio07_tx_en = driver.gpio_tx_en[7]; \ + assign load.gpio08_out = driver.gpio_out[8]; \ + assign load.gpio08_tx_en = driver.gpio_tx_en[8]; \ + assign load.gpio09_out = driver.gpio_out[9]; \ + assign load.gpio09_tx_en = driver.gpio_tx_en[9]; \ + assign load.gpio10_out = driver.gpio_out[10]; \ + assign load.gpio10_tx_en = driver.gpio_tx_en[10]; \ + assign load.gpio11_out = driver.gpio_out[11]; \ + assign load.gpio11_tx_en = driver.gpio_tx_en[11]; \ + assign load.gpio12_out = driver.gpio_out[12]; \ + assign load.gpio12_tx_en = driver.gpio_tx_en[12]; \ + assign load.gpio13_out = driver.gpio_out[13]; \ + assign load.gpio13_tx_en = driver.gpio_tx_en[13]; \ + assign load.gpio14_out = driver.gpio_out[14]; \ + assign load.gpio14_tx_en = driver.gpio_tx_en[14]; \ + assign load.gpio15_out = driver.gpio_out[15]; \ + assign load.gpio15_tx_en = driver.gpio_tx_en[15]; \ + assign load.gpio16_out = driver.gpio_out[16]; \ + assign load.gpio16_tx_en = driver.gpio_tx_en[16]; \ + assign load.gpio17_out = driver.gpio_out[17]; \ + assign load.gpio17_tx_en = driver.gpio_tx_en[17]; \ + assign load.gpio18_out = driver.gpio_out[18]; \ + assign load.gpio18_tx_en = driver.gpio_tx_en[18]; \ + assign load.gpio19_out = driver.gpio_out[19]; \ + assign load.gpio19_tx_en = driver.gpio_tx_en[19]; \ + assign load.gpio20_out = driver.gpio_out[20]; \ + assign load.gpio20_tx_en = driver.gpio_tx_en[20]; \ + assign load.gpio21_out = driver.gpio_out[21]; \ + assign load.gpio21_tx_en = driver.gpio_tx_en[21]; \ + assign load.gpio22_out = driver.gpio_out[22]; \ + assign load.gpio22_tx_en = driver.gpio_tx_en[22]; \ + assign load.gpio23_out = driver.gpio_out[23]; \ + assign load.gpio23_tx_en = driver.gpio_tx_en[23]; \ + assign load.gpio24_out = driver.gpio_out[24]; \ + assign load.gpio24_tx_en = driver.gpio_tx_en[24]; \ + assign load.gpio25_out = driver.gpio_out[25]; \ + assign load.gpio25_tx_en = driver.gpio_tx_en[25]; \ + assign load.gpio26_out = driver.gpio_out[26]; \ + assign load.gpio26_tx_en = driver.gpio_tx_en[26]; \ + assign load.gpio27_out = driver.gpio_out[27]; \ + assign load.gpio27_tx_en = driver.gpio_tx_en[27]; \ + assign load.gpio28_out = driver.gpio_out[28]; \ + assign load.gpio28_tx_en = driver.gpio_tx_en[28]; \ + assign load.gpio29_out = driver.gpio_out[29]; \ + assign load.gpio29_tx_en = driver.gpio_tx_en[29]; \ + assign load.gpio30_out = driver.gpio_out[30]; \ + assign load.gpio30_tx_en = driver.gpio_tx_en[30]; \ + assign load.gpio31_out = driver.gpio_out[31]; \ + assign load.gpio31_tx_en = driver.gpio_tx_en[31]; \ + + + +`define ASSIGN_I2C0_PAD2SOC(load, driver) \ + assign load.scl_i = driver.scl_i; \ + assign load.sda_i = driver.sda_i; \ + +`define ASSIGN_I2C0_SOC2PAD(load, driver) \ + assign load.scl_o = driver.scl_o; \ + assign load.scl_oe = driver.scl_oe; \ + assign load.sda_o = driver.sda_o; \ + assign load.sda_oe = driver.sda_oe; \ + + + +`define ASSIGN_UART0_PAD2SOC(load, driver) \ + assign load.rx_i = driver.rx_i; \ + +`define ASSIGN_UART0_SOC2PAD(load, driver) \ + assign load.tx_o = driver.tx_o; \ + + + +`define ASSIGN_QSPIM0_PAD2SOC(load, driver) \ + assign load.sd0_i = driver.sd0_i; \ + assign load.sd1_i = driver.sd1_i; \ + assign load.sd2_i = driver.sd2_i; \ + assign load.sd3_i = driver.sd3_i; \ + +`define ASSIGN_QSPIM0_SOC2PAD(load, driver) \ + assign load.csn0_o = driver.csn0_o; \ + assign load.csn1_o = driver.csn1_o; \ + assign load.csn2_o = driver.csn2_o; \ + assign load.csn3_o = driver.csn3_o; \ + assign load.sck_o = driver.sck_o; \ + assign load.sd0_o = driver.sd0_o; \ + assign load.sd0_oe = driver.sd0_oe; \ + assign load.sd1_o = driver.sd1_o; \ + assign load.sd1_oe = driver.sd1_oe; \ + assign load.sd2_o = driver.sd2_o; \ + assign load.sd2_oe = driver.sd2_oe; \ + assign load.sd3_o = driver.sd3_o; \ + assign load.sd3_oe = driver.sd3_oe; \ + + + +`define ASSIGN_CPI0_PAD2SOC(load, driver) \ + assign load.data0_i = driver.data0_i; \ + assign load.data1_i = driver.data1_i; \ + assign load.data2_i = driver.data2_i; \ + assign load.data3_i = driver.data3_i; \ + assign load.data4_i = driver.data4_i; \ + assign load.data5_i = driver.data5_i; \ + assign load.data6_i = driver.data6_i; \ + assign load.data7_i = driver.data7_i; \ + assign load.data8_i = driver.data8_i; \ + assign load.data9_i = driver.data9_i; \ + assign load.hsync_i = driver.hsync_i; \ + assign load.pclk_i = driver.pclk_i; \ + assign load.vsync_i = driver.vsync_i; \ + + + + +`define ASSIGN_SDIO0_PAD2SOC(load, driver) \ + assign load.sdcmd_in = driver.sdcmd_in; \ + assign load.sddata_in[0] = driver.sddata0_in; \ + assign load.sddata_in[1] = driver.sddata1_in; \ + assign load.sddata_in[2] = driver.sddata2_in; \ + assign load.sddata_in[3] = driver.sddata3_in; \ + +`define ASSIGN_SDIO0_SOC2PAD(load, driver) \ + assign load.sdclk_out = driver.sdclk_out; \ + assign load.sdcmd_oen = driver.sdcmd_oen; \ + assign load.sdcmd_out = driver.sdcmd_out; \ + assign load.sddata0_oen = driver.sddata_oen[0]; \ + assign load.sddata0_out = driver.sddata_out[0]; \ + assign load.sddata1_oen = driver.sddata_oen[1]; \ + assign load.sddata1_out = driver.sddata_out[1]; \ + assign load.sddata2_oen = driver.sddata_oen[2]; \ + assign load.sddata2_out = driver.sddata_out[2]; \ + assign load.sddata3_oen = driver.sddata_oen[3]; \ + assign load.sddata3_out = driver.sddata_out[3]; \ + + + +`define ASSIGN_I2S0_PAD2SOC(load, driver) \ + assign load.master_sck_in = driver.master_sck_in; \ + assign load.master_ws_in = driver.master_ws_in; \ + assign load.slave_sck_in = driver.slave_sck_in; \ + assign load.slave_sd0_in = driver.slave_sd0_in; \ + assign load.slave_sd1_in = driver.slave_sd1_in; \ + assign load.slave_ws_in = driver.slave_ws_in; \ + +`define ASSIGN_I2S0_SOC2PAD(load, driver) \ + assign load.master_sck_oe = driver.master_sck_oe; \ + assign load.master_sck_out = driver.master_sck_out; \ + assign load.master_sd0_out = driver.master_sd0_out; \ + assign load.master_sd1_out = driver.master_sd1_out; \ + assign load.master_ws_oe = driver.master_ws_oe; \ + assign load.master_ws_out = driver.master_ws_out; \ + assign load.slave_sck_oe = driver.slave_sck_oe; \ + assign load.slave_sck_out = driver.slave_sck_out; \ + assign load.slave_ws_oe = driver.slave_ws_oe; \ + assign load.slave_ws_out = driver.slave_ws_out; \ + + + + +`define ASSIGN_TIMER0_SOC2PAD(load, driver) \ + assign load.timer_out0 = driver.out[0]; \ + assign load.timer_out1 = driver.out[1]; \ + assign load.timer_out2 = driver.out[2]; \ + assign load.timer_out3 = driver.out[3]; \ + + + + +`define ASSIGN_TIMER1_SOC2PAD(load, driver) \ + assign load.timer_out0 = driver.out[0]; \ + assign load.timer_out1 = driver.out[1]; \ + assign load.timer_out2 = driver.out[2]; \ + assign load.timer_out3 = driver.out[3]; \ + + + + +`define ASSIGN_TIMER2_SOC2PAD(load, driver) \ + assign load.timer_out0 = driver.out[0]; \ + assign load.timer_out1 = driver.out[1]; \ + assign load.timer_out2 = driver.out[2]; \ + assign load.timer_out3 = driver.out[3]; \ + + + + +`define ASSIGN_TIMER3_SOC2PAD(load, driver) \ + assign load.timer_out0 = driver.out[0]; \ + assign load.timer_out1 = driver.out[1]; \ + assign load.timer_out2 = driver.out[2]; \ + assign load.timer_out3 = driver.out[3]; \ + + diff --git a/hw/padframe/pulpissimo_padframe_fpga_autogen/src/pkg_internal_pulpissimo_padframe_all_pads.sv b/hw/padframe/pulpissimo_padframe_fpga_autogen/src/pkg_internal_pulpissimo_padframe_all_pads.sv new file mode 100644 index 00000000..0adfbff0 --- /dev/null +++ b/hw/padframe/pulpissimo_padframe_fpga_autogen/src/pkg_internal_pulpissimo_padframe_all_pads.sv @@ -0,0 +1,2449 @@ + +// File auto-generated by Padrick unknown +package pkg_internal_pulpissimo_padframe_all_pads; + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io00_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io00_t; + + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io01_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io01_t; + + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io02_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io02_t; + + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io03_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io03_t; + + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io04_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io04_t; + + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io05_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io05_t; + + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io06_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io06_t; + + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io07_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io07_t; + + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io08_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io08_t; + + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io09_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io09_t; + + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io10_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io10_t; + + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io11_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io11_t; + + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io12_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io12_t; + + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io13_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io13_t; + + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io14_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io14_t; + + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io15_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io15_t; + + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io16_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io16_t; + + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io17_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io17_t; + + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io18_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io18_t; + + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io19_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io19_t; + + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io20_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io20_t; + + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io21_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io21_t; + + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io22_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io22_t; + + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io23_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io23_t; + + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io24_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io24_t; + + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io25_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io25_t; + + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io26_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io26_t; + + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io27_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io27_t; + + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io28_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io28_t; + + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io29_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io29_t; + + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io30_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io30_t; + + typedef struct packed{ + logic chip2pad; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io31_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io31_t; + + typedef struct packed{ + mux_to_pad_pad_io00_t pad_io00; + mux_to_pad_pad_io01_t pad_io01; + mux_to_pad_pad_io02_t pad_io02; + mux_to_pad_pad_io03_t pad_io03; + mux_to_pad_pad_io04_t pad_io04; + mux_to_pad_pad_io05_t pad_io05; + mux_to_pad_pad_io06_t pad_io06; + mux_to_pad_pad_io07_t pad_io07; + mux_to_pad_pad_io08_t pad_io08; + mux_to_pad_pad_io09_t pad_io09; + mux_to_pad_pad_io10_t pad_io10; + mux_to_pad_pad_io11_t pad_io11; + mux_to_pad_pad_io12_t pad_io12; + mux_to_pad_pad_io13_t pad_io13; + mux_to_pad_pad_io14_t pad_io14; + mux_to_pad_pad_io15_t pad_io15; + mux_to_pad_pad_io16_t pad_io16; + mux_to_pad_pad_io17_t pad_io17; + mux_to_pad_pad_io18_t pad_io18; + mux_to_pad_pad_io19_t pad_io19; + mux_to_pad_pad_io20_t pad_io20; + mux_to_pad_pad_io21_t pad_io21; + mux_to_pad_pad_io22_t pad_io22; + mux_to_pad_pad_io23_t pad_io23; + mux_to_pad_pad_io24_t pad_io24; + mux_to_pad_pad_io25_t pad_io25; + mux_to_pad_pad_io26_t pad_io26; + mux_to_pad_pad_io27_t pad_io27; + mux_to_pad_pad_io28_t pad_io28; + mux_to_pad_pad_io29_t pad_io29; + mux_to_pad_pad_io30_t pad_io30; + mux_to_pad_pad_io31_t pad_io31; + } mux_to_pads_t; + + typedef struct packed{ + pad_to_mux_pad_io00_t pad_io00; + pad_to_mux_pad_io01_t pad_io01; + pad_to_mux_pad_io02_t pad_io02; + pad_to_mux_pad_io03_t pad_io03; + pad_to_mux_pad_io04_t pad_io04; + pad_to_mux_pad_io05_t pad_io05; + pad_to_mux_pad_io06_t pad_io06; + pad_to_mux_pad_io07_t pad_io07; + pad_to_mux_pad_io08_t pad_io08; + pad_to_mux_pad_io09_t pad_io09; + pad_to_mux_pad_io10_t pad_io10; + pad_to_mux_pad_io11_t pad_io11; + pad_to_mux_pad_io12_t pad_io12; + pad_to_mux_pad_io13_t pad_io13; + pad_to_mux_pad_io14_t pad_io14; + pad_to_mux_pad_io15_t pad_io15; + pad_to_mux_pad_io16_t pad_io16; + pad_to_mux_pad_io17_t pad_io17; + pad_to_mux_pad_io18_t pad_io18; + pad_to_mux_pad_io19_t pad_io19; + pad_to_mux_pad_io20_t pad_io20; + pad_to_mux_pad_io21_t pad_io21; + pad_to_mux_pad_io22_t pad_io22; + pad_to_mux_pad_io23_t pad_io23; + pad_to_mux_pad_io24_t pad_io24; + pad_to_mux_pad_io25_t pad_io25; + pad_to_mux_pad_io26_t pad_io26; + pad_to_mux_pad_io27_t pad_io27; + pad_to_mux_pad_io28_t pad_io28; + pad_to_mux_pad_io29_t pad_io29; + pad_to_mux_pad_io30_t pad_io30; + pad_to_mux_pad_io31_t pad_io31; + } pads_to_mux_t; + + + + // Indices definitions + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_GPIO_GPIO00 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_GPIO_GPIO01 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_GPIO_GPIO02 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_GPIO_GPIO03 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_GPIO_GPIO04 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_GPIO_GPIO05 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_GPIO_GPIO06 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_GPIO_GPIO07 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_GPIO_GPIO08 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_GPIO_GPIO09 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_GPIO_GPIO10 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_GPIO_GPIO11 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_GPIO_GPIO12 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_GPIO_GPIO13 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_GPIO_GPIO14 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_GPIO_GPIO15 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_GPIO_GPIO16 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_GPIO_GPIO17 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_GPIO_GPIO18 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_GPIO_GPIO19 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_GPIO_GPIO20 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_GPIO_GPIO21 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_GPIO_GPIO22 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_GPIO_GPIO23 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_GPIO_GPIO24 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_GPIO_GPIO25 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_GPIO_GPIO26 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_GPIO_GPIO27 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_GPIO_GPIO28 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_GPIO_GPIO29 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_GPIO_GPIO30 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_GPIO_GPIO31 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_UART0_TX = 6'd57; + + // Dynamic Pad instance index + + parameter PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH = 5; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00 = 5'd0; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01 = 5'd1; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02 = 5'd2; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03 = 5'd3; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04 = 5'd4; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05 = 5'd5; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06 = 5'd6; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07 = 5'd7; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08 = 5'd8; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09 = 5'd9; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10 = 5'd10; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11 = 5'd11; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12 = 5'd12; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13 = 5'd13; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14 = 5'd14; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15 = 5'd15; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16 = 5'd16; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17 = 5'd17; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18 = 5'd18; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19 = 5'd19; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20 = 5'd20; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21 = 5'd21; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22 = 5'd22; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23 = 5'd23; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24 = 5'd24; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25 = 5'd25; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26 = 5'd26; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27 = 5'd27; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28 = 5'd28; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29 = 5'd29; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30 = 5'd30; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31 = 5'd31; + + parameter PORT_MUX_GROUP_PAD_IO00_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO00_SEL_PAD_IO00 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO01_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO01_SEL_PAD_IO01 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO02_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO02_SEL_PAD_IO02 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO03_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO03_SEL_PAD_IO03 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO04_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO04_SEL_PAD_IO04 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO05_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO05_SEL_PAD_IO05 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO06_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO06_SEL_PAD_IO06 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO07_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO07_SEL_PAD_IO07 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO08_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO08_SEL_PAD_IO08 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO09_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO09_SEL_PAD_IO09 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO10_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO10_SEL_PAD_IO10 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO11_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO11_SEL_PAD_IO11 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO12_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO12_SEL_PAD_IO12 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO13_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO13_SEL_PAD_IO13 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO14_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO14_SEL_PAD_IO14 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO15_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO15_SEL_PAD_IO15 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO16_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO16_SEL_PAD_IO16 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO17_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO17_SEL_PAD_IO17 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO18_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO18_SEL_PAD_IO18 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO19_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO19_SEL_PAD_IO19 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO20_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO20_SEL_PAD_IO20 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO21_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO21_SEL_PAD_IO21 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO22_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO22_SEL_PAD_IO22 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO23_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO23_SEL_PAD_IO23 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO24_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO24_SEL_PAD_IO24 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO25_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO25_SEL_PAD_IO25 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO26_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO26_SEL_PAD_IO26 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO27_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO27_SEL_PAD_IO27 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO28_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO28_SEL_PAD_IO28 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO29_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO29_SEL_PAD_IO29 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO30_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO30_SEL_PAD_IO30 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO31_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO31_SEL_PAD_IO31 = 1'd0; +endpackage : pkg_internal_pulpissimo_padframe_all_pads diff --git a/hw/padframe/pulpissimo_padframe_fpga_autogen/src/pkg_pulpissimo_padframe.sv b/hw/padframe/pulpissimo_padframe_fpga_autogen/src/pkg_pulpissimo_padframe.sv new file mode 100644 index 00000000..7b25c961 --- /dev/null +++ b/hw/padframe/pulpissimo_padframe_fpga_autogen/src/pkg_pulpissimo_padframe.sv @@ -0,0 +1,326 @@ + +// File auto-generated by Padrick unknown +package pkg_pulpissimo_padframe; + + //Structs for all_pads + + //Static connections signals + typedef struct packed { + logic hyper_ck; + logic hyper_ckn; + logic hyper_cs0_no; + logic hyper_cs1_no; + logic hyper_dq0_o; + logic hyper_dq1_o; + logic hyper_dq2_o; + logic hyper_dq3_o; + logic hyper_dq4_o; + logic hyper_dq5_o; + logic hyper_dq6_o; + logic hyper_dq7_o; + logic hyper_dq_oe; + logic hyper_reset_no; + logic hyper_rwds_o; + logic hyper_rwds_oe; + logic jtag_tdo; + } pad_domain_all_pads_static_connection_signals_soc2pad_t; + + typedef struct packed { + logic bootsel0; + logic bootsel1; + logic clk_byp_en; + logic hyper_dq0_i; + logic hyper_dq1_i; + logic hyper_dq2_i; + logic hyper_dq3_i; + logic hyper_dq4_i; + logic hyper_dq5_i; + logic hyper_dq6_i; + logic hyper_dq7_i; + logic hyper_rwds_i; + logic jtag_tck; + logic jtag_tdi; + logic jtag_tms; + logic jtag_trstn; + logic ref_clk; + logic rst_n; + } pad_domain_all_pads_static_connection_signals_pad2soc_t; + + // Port Group signals + typedef struct packed { + logic gpio00_out; + logic gpio00_tx_en; + logic gpio01_out; + logic gpio01_tx_en; + logic gpio02_out; + logic gpio02_tx_en; + logic gpio03_out; + logic gpio03_tx_en; + logic gpio04_out; + logic gpio04_tx_en; + logic gpio05_out; + logic gpio05_tx_en; + logic gpio06_out; + logic gpio06_tx_en; + logic gpio07_out; + logic gpio07_tx_en; + logic gpio08_out; + logic gpio08_tx_en; + logic gpio09_out; + logic gpio09_tx_en; + logic gpio10_out; + logic gpio10_tx_en; + logic gpio11_out; + logic gpio11_tx_en; + logic gpio12_out; + logic gpio12_tx_en; + logic gpio13_out; + logic gpio13_tx_en; + logic gpio14_out; + logic gpio14_tx_en; + logic gpio15_out; + logic gpio15_tx_en; + logic gpio16_out; + logic gpio16_tx_en; + logic gpio17_out; + logic gpio17_tx_en; + logic gpio18_out; + logic gpio18_tx_en; + logic gpio19_out; + logic gpio19_tx_en; + logic gpio20_out; + logic gpio20_tx_en; + logic gpio21_out; + logic gpio21_tx_en; + logic gpio22_out; + logic gpio22_tx_en; + logic gpio23_out; + logic gpio23_tx_en; + logic gpio24_out; + logic gpio24_tx_en; + logic gpio25_out; + logic gpio25_tx_en; + logic gpio26_out; + logic gpio26_tx_en; + logic gpio27_out; + logic gpio27_tx_en; + logic gpio28_out; + logic gpio28_tx_en; + logic gpio29_out; + logic gpio29_tx_en; + logic gpio30_out; + logic gpio30_tx_en; + logic gpio31_out; + logic gpio31_tx_en; + } pad_domain_all_pads_port_group_gpio_soc2pad_t; + + typedef struct packed { + logic gpio00_in; + logic gpio01_in; + logic gpio02_in; + logic gpio03_in; + logic gpio04_in; + logic gpio05_in; + logic gpio06_in; + logic gpio07_in; + logic gpio08_in; + logic gpio09_in; + logic gpio10_in; + logic gpio11_in; + logic gpio12_in; + logic gpio13_in; + logic gpio14_in; + logic gpio15_in; + logic gpio16_in; + logic gpio17_in; + logic gpio18_in; + logic gpio19_in; + logic gpio20_in; + logic gpio21_in; + logic gpio22_in; + logic gpio23_in; + logic gpio24_in; + logic gpio25_in; + logic gpio26_in; + logic gpio27_in; + logic gpio28_in; + logic gpio29_in; + logic gpio30_in; + logic gpio31_in; + } pad_domain_all_pads_port_group_gpio_pad2soc_t; + + typedef struct packed { + logic scl_o; + logic scl_oe; + logic sda_o; + logic sda_oe; + } pad_domain_all_pads_port_group_i2c0_soc2pad_t; + + typedef struct packed { + logic scl_i; + logic sda_i; + } pad_domain_all_pads_port_group_i2c0_pad2soc_t; + + typedef struct packed { + logic tx_o; + } pad_domain_all_pads_port_group_uart0_soc2pad_t; + + typedef struct packed { + logic rx_i; + } pad_domain_all_pads_port_group_uart0_pad2soc_t; + + typedef struct packed { + logic csn0_o; + logic csn1_o; + logic csn2_o; + logic csn3_o; + logic sck_o; + logic sd0_o; + logic sd0_oe; + logic sd1_o; + logic sd1_oe; + logic sd2_o; + logic sd2_oe; + logic sd3_o; + logic sd3_oe; + } pad_domain_all_pads_port_group_qspim0_soc2pad_t; + + typedef struct packed { + logic sd0_i; + logic sd1_i; + logic sd2_i; + logic sd3_i; + } pad_domain_all_pads_port_group_qspim0_pad2soc_t; + + typedef struct packed { + logic data0_i; + logic data1_i; + logic data2_i; + logic data3_i; + logic data4_i; + logic data5_i; + logic data6_i; + logic data7_i; + logic data8_i; + logic data9_i; + logic hsync_i; + logic pclk_i; + logic vsync_i; + } pad_domain_all_pads_port_group_cpi0_pad2soc_t; + + typedef struct packed { + logic sdclk_out; + logic sdcmd_oen; + logic sdcmd_out; + logic sddata0_oen; + logic sddata0_out; + logic sddata1_oen; + logic sddata1_out; + logic sddata2_oen; + logic sddata2_out; + logic sddata3_oen; + logic sddata3_out; + } pad_domain_all_pads_port_group_sdio0_soc2pad_t; + + typedef struct packed { + logic sdcmd_in; + logic sddata0_in; + logic sddata1_in; + logic sddata2_in; + logic sddata3_in; + } pad_domain_all_pads_port_group_sdio0_pad2soc_t; + + typedef struct packed { + logic master_sck_oe; + logic master_sck_out; + logic master_sd0_out; + logic master_sd1_out; + logic master_ws_oe; + logic master_ws_out; + logic slave_sck_oe; + logic slave_sck_out; + logic slave_ws_oe; + logic slave_ws_out; + } pad_domain_all_pads_port_group_i2s0_soc2pad_t; + + typedef struct packed { + logic master_sck_in; + logic master_ws_in; + logic slave_sck_in; + logic slave_sd0_in; + logic slave_sd1_in; + logic slave_ws_in; + } pad_domain_all_pads_port_group_i2s0_pad2soc_t; + + typedef struct packed { + logic timer_out0; + logic timer_out1; + logic timer_out2; + logic timer_out3; + } pad_domain_all_pads_port_group_timer0_soc2pad_t; + + typedef struct packed { + logic timer_out0; + logic timer_out1; + logic timer_out2; + logic timer_out3; + } pad_domain_all_pads_port_group_timer1_soc2pad_t; + + typedef struct packed { + logic timer_out0; + logic timer_out1; + logic timer_out2; + logic timer_out3; + } pad_domain_all_pads_port_group_timer2_soc2pad_t; + + typedef struct packed { + logic timer_out0; + logic timer_out1; + logic timer_out2; + logic timer_out3; + } pad_domain_all_pads_port_group_timer3_soc2pad_t; + + typedef struct packed { + pad_domain_all_pads_port_group_gpio_soc2pad_t gpio; + pad_domain_all_pads_port_group_i2c0_soc2pad_t i2c0; + pad_domain_all_pads_port_group_uart0_soc2pad_t uart0; + pad_domain_all_pads_port_group_qspim0_soc2pad_t qspim0; + pad_domain_all_pads_port_group_sdio0_soc2pad_t sdio0; + pad_domain_all_pads_port_group_i2s0_soc2pad_t i2s0; + pad_domain_all_pads_port_group_timer0_soc2pad_t timer0; + pad_domain_all_pads_port_group_timer1_soc2pad_t timer1; + pad_domain_all_pads_port_group_timer2_soc2pad_t timer2; + pad_domain_all_pads_port_group_timer3_soc2pad_t timer3; + } pad_domain_all_pads_ports_soc2pad_t; + + typedef struct packed { + pad_domain_all_pads_port_group_gpio_pad2soc_t gpio; + pad_domain_all_pads_port_group_i2c0_pad2soc_t i2c0; + pad_domain_all_pads_port_group_uart0_pad2soc_t uart0; + pad_domain_all_pads_port_group_qspim0_pad2soc_t qspim0; + pad_domain_all_pads_port_group_cpi0_pad2soc_t cpi0; + pad_domain_all_pads_port_group_sdio0_pad2soc_t sdio0; + pad_domain_all_pads_port_group_i2s0_pad2soc_t i2s0; + } pad_domain_all_pads_ports_pad2soc_t; + + + //Toplevel structs + + typedef struct packed { + pad_domain_all_pads_static_connection_signals_pad2soc_t all_pads; + } static_connection_signals_pad2soc_t; + + typedef struct packed { + pad_domain_all_pads_static_connection_signals_soc2pad_t all_pads; + } static_connection_signals_soc2pad_t; + + typedef struct packed { + pad_domain_all_pads_ports_pad2soc_t all_pads; + } port_signals_pad2soc_t; + + typedef struct packed { + pad_domain_all_pads_ports_soc2pad_t all_pads; + } port_signals_soc2pad_t; + + +endpackage : pkg_pulpissimo_padframe diff --git a/hw/padframe/pulpissimo_padframe_fpga_autogen/src/pulpissimo_padframe.sv b/hw/padframe/pulpissimo_padframe_fpga_autogen/src/pulpissimo_padframe.sv new file mode 100644 index 00000000..9844c485 --- /dev/null +++ b/hw/padframe/pulpissimo_padframe_fpga_autogen/src/pulpissimo_padframe.sv @@ -0,0 +1,173 @@ + +// File auto-generated by Padrick unknown +module pulpissimo_padframe + import pkg_pulpissimo_padframe::*; +#( + parameter int unsigned AW = 32, + parameter int unsigned DW = 32, + parameter type req_t = logic, // reg_interface request type + parameter type resp_t = logic, // reg_interface response type + parameter logic [DW-1:0] DecodeErrRespData = 32'hdeadda7a, + localparam int unsigned NGPIO = 32 +)( + input logic clk_i, + input logic rst_ni, + output static_connection_signals_pad2soc_t static_connection_signals_pad2soc, + input static_connection_signals_soc2pad_t static_connection_signals_soc2pad, + output port_signals_pad2soc_t port_signals_pad2soc, + input port_signals_soc2pad_t port_signals_soc2pad, + // Landing Pads + inout wire logic pad_ref_clk, + inout wire logic pad_clk_byp_en, + inout wire logic pad_reset_n, + inout wire logic pad_bootsel0, + inout wire logic pad_bootsel1, + inout wire logic pad_jtag_tck, + inout wire logic pad_jtag_trstn, + inout wire logic pad_jtag_tms, + inout wire logic pad_jtag_tdi, + inout wire logic pad_jtag_tdo, + inout wire logic pad_hyper_csn0, + inout wire logic pad_hyper_csn1, + inout wire logic pad_hyper_reset_n, + inout wire logic pad_hyper_ck, + inout wire logic pad_hyper_ckn, + inout wire logic pad_hyper_dq0, + inout wire logic pad_hyper_dq1, + inout wire logic pad_hyper_dq2, + inout wire logic pad_hyper_dq3, + inout wire logic pad_hyper_dq4, + inout wire logic pad_hyper_dq5, + inout wire logic pad_hyper_dq6, + inout wire logic pad_hyper_dq7, + inout wire logic pad_hyper_rwds, + inout wire [NGPIO-1:0] pad_io, + // Config Interface + input req_t config_req_i, + output resp_t config_rsp_o + ); + + + req_t all_pads_config_req; + resp_t all_pads_config_resp; + pulpissimo_padframe_all_pads #( + .req_t(req_t), + .resp_t(resp_t) + ) i_all_pads ( + .clk_i, + .rst_ni, + .static_connection_signals_pad2soc(static_connection_signals_pad2soc.all_pads), + .static_connection_signals_soc2pad(static_connection_signals_soc2pad.all_pads), + .port_signals_pad2soc_o(port_signals_pad2soc.all_pads), + .port_signals_soc2pad_i(port_signals_soc2pad.all_pads), + .pad_pad_ref_clk_pad(pad_ref_clk), + .pad_pad_clk_byp_en_pad(pad_clk_byp_en), + .pad_pad_reset_n_pad(pad_reset_n), + .pad_pad_bootsel0_pad(pad_bootsel0), + .pad_pad_bootsel1_pad(pad_bootsel1), + .pad_pad_jtag_tck_pad(pad_jtag_tck), + .pad_pad_jtag_trstn_pad(pad_jtag_trstn), + .pad_pad_jtag_tms_pad(pad_jtag_tms), + .pad_pad_jtag_tdi_pad(pad_jtag_tdi), + .pad_pad_jtag_tdo_pad(pad_jtag_tdo), + .pad_pad_hyper_csn0_pad(pad_hyper_csn0), + .pad_pad_hyper_csn1_pad(pad_hyper_csn1), + .pad_pad_hyper_reset_n_pad(pad_hyper_reset_n), + .pad_pad_hyper_ck_pad(pad_hyper_ck), + .pad_pad_hyper_ckn_pad(pad_hyper_ckn), + .pad_pad_hyper_dq0_pad(pad_hyper_dq0), + .pad_pad_hyper_dq1_pad(pad_hyper_dq1), + .pad_pad_hyper_dq2_pad(pad_hyper_dq2), + .pad_pad_hyper_dq3_pad(pad_hyper_dq3), + .pad_pad_hyper_dq4_pad(pad_hyper_dq4), + .pad_pad_hyper_dq5_pad(pad_hyper_dq5), + .pad_pad_hyper_dq6_pad(pad_hyper_dq6), + .pad_pad_hyper_dq7_pad(pad_hyper_dq7), + .pad_pad_hyper_rwds_pad(pad_hyper_rwds), + .pad_pad_io00_pad(pad_io[0]), + .pad_pad_io01_pad(pad_io[1]), + .pad_pad_io02_pad(pad_io[2]), + .pad_pad_io03_pad(pad_io[3]), + .pad_pad_io04_pad(pad_io[4]), + .pad_pad_io05_pad(pad_io[5]), + .pad_pad_io06_pad(pad_io[6]), + .pad_pad_io07_pad(pad_io[7]), + .pad_pad_io08_pad(pad_io[8]), + .pad_pad_io09_pad(pad_io[9]), + .pad_pad_io10_pad(pad_io[10]), + .pad_pad_io11_pad(pad_io[11]), + .pad_pad_io12_pad(pad_io[12]), + .pad_pad_io13_pad(pad_io[13]), + .pad_pad_io14_pad(pad_io[14]), + .pad_pad_io15_pad(pad_io[15]), + .pad_pad_io16_pad(pad_io[16]), + .pad_pad_io17_pad(pad_io[17]), + .pad_pad_io18_pad(pad_io[18]), + .pad_pad_io19_pad(pad_io[19]), + .pad_pad_io20_pad(pad_io[20]), + .pad_pad_io21_pad(pad_io[21]), + .pad_pad_io22_pad(pad_io[22]), + .pad_pad_io23_pad(pad_io[23]), + .pad_pad_io24_pad(pad_io[24]), + .pad_pad_io25_pad(pad_io[25]), + .pad_pad_io26_pad(pad_io[26]), + .pad_pad_io27_pad(pad_io[27]), + .pad_pad_io28_pad(pad_io[28]), + .pad_pad_io29_pad(pad_io[29]), + .pad_pad_io30_pad(pad_io[30]), + .pad_pad_io31_pad(pad_io[31]), + .config_req_i(all_pads_config_req), + .config_rsp_o(all_pads_config_resp) + ); + + + localparam int unsigned NUM_PAD_DOMAINS = 1; + localparam int unsigned REG_ADDR_WIDTH = 9; + typedef struct packed { + int unsigned idx; + logic [REG_ADDR_WIDTH-1:0] start_addr; + logic [REG_ADDR_WIDTH-1:0] end_addr; + } addr_rule_t; + + localparam addr_rule_t[NUM_PAD_DOMAINS-1:0] ADDR_DEMUX_RULES = '{ + '{ idx: 0, start_addr: 9'd0, end_addr: 9'd260} + }; + logic[$clog2(NUM_PAD_DOMAINS+1)-1:0] pad_domain_sel; // +1 since there is an additional error slave + addr_decode #( + .NoIndices(NUM_PAD_DOMAINS+1), + .NoRules(NUM_PAD_DOMAINS), + .addr_t(logic[REG_ADDR_WIDTH-1:0]), + .rule_t(addr_rule_t) + ) i_addr_decode( + .addr_i(config_req_i.addr[REG_ADDR_WIDTH-1:0]), + .addr_map_i(ADDR_DEMUX_RULES), + .dec_valid_o(), + .dec_error_o(), + .idx_o(pad_domain_sel), + .en_default_idx_i(1'b1), + .default_idx_i(1'd1) // The last entry is the error slave + ); + + req_t error_slave_req; + resp_t error_slave_rsp; + + // Config Interface demultiplexing + reg_demux #( + .NoPorts(NUM_PAD_DOMAINS+1), //+1 for the error slave + .req_t(req_t), + .rsp_t(resp_t) + ) i_config_demuxer ( + .clk_i, + .rst_ni, + .in_select_i(pad_domain_sel), + .in_req_i(config_req_i), + .in_rsp_o(config_rsp_o), + .out_req_o({error_slave_req, all_pads_config_req}), + .out_rsp_i({error_slave_rsp, all_pads_config_resp}) + ); + + assign error_slave_rsp.error = 1'b1; + assign error_slave_rsp.rdata = DecodeErrRespData; + assign error_slave_rsp.ready = 1'b1; + +endmodule diff --git a/hw/padframe/pulpissimo_padframe_fpga_autogen/src/pulpissimo_padframe_all_pads.sv b/hw/padframe/pulpissimo_padframe_fpga_autogen/src/pulpissimo_padframe_all_pads.sv new file mode 100644 index 00000000..73eaeb4b --- /dev/null +++ b/hw/padframe/pulpissimo_padframe_fpga_autogen/src/pulpissimo_padframe_all_pads.sv @@ -0,0 +1,158 @@ + +// File auto-generated by Padrick unknown +module pulpissimo_padframe_all_pads + import pkg_pulpissimo_padframe::*; + import pkg_internal_pulpissimo_padframe_all_pads::*; +#( + parameter type req_t = logic, // reg_interface request type + parameter type resp_t = logic // reg_interface response type +) ( + input logic clk_i, + input logic rst_ni, + output pad_domain_all_pads_static_connection_signals_pad2soc_t static_connection_signals_pad2soc, + input pad_domain_all_pads_static_connection_signals_soc2pad_t static_connection_signals_soc2pad, + output pad_domain_all_pads_ports_pad2soc_t port_signals_pad2soc_o, + input pad_domain_all_pads_ports_soc2pad_t port_signals_soc2pad_i, + inout wire logic pad_pad_ref_clk_pad, + inout wire logic pad_pad_clk_byp_en_pad, + inout wire logic pad_pad_reset_n_pad, + inout wire logic pad_pad_bootsel0_pad, + inout wire logic pad_pad_bootsel1_pad, + inout wire logic pad_pad_jtag_tck_pad, + inout wire logic pad_pad_jtag_trstn_pad, + inout wire logic pad_pad_jtag_tms_pad, + inout wire logic pad_pad_jtag_tdi_pad, + inout wire logic pad_pad_jtag_tdo_pad, + inout wire logic pad_pad_hyper_csn0_pad, + inout wire logic pad_pad_hyper_csn1_pad, + inout wire logic pad_pad_hyper_reset_n_pad, + inout wire logic pad_pad_hyper_ck_pad, + inout wire logic pad_pad_hyper_ckn_pad, + inout wire logic pad_pad_hyper_dq0_pad, + inout wire logic pad_pad_hyper_dq1_pad, + inout wire logic pad_pad_hyper_dq2_pad, + inout wire logic pad_pad_hyper_dq3_pad, + inout wire logic pad_pad_hyper_dq4_pad, + inout wire logic pad_pad_hyper_dq5_pad, + inout wire logic pad_pad_hyper_dq6_pad, + inout wire logic pad_pad_hyper_dq7_pad, + inout wire logic pad_pad_hyper_rwds_pad, + inout wire logic pad_pad_io00_pad, + inout wire logic pad_pad_io01_pad, + inout wire logic pad_pad_io02_pad, + inout wire logic pad_pad_io03_pad, + inout wire logic pad_pad_io04_pad, + inout wire logic pad_pad_io05_pad, + inout wire logic pad_pad_io06_pad, + inout wire logic pad_pad_io07_pad, + inout wire logic pad_pad_io08_pad, + inout wire logic pad_pad_io09_pad, + inout wire logic pad_pad_io10_pad, + inout wire logic pad_pad_io11_pad, + inout wire logic pad_pad_io12_pad, + inout wire logic pad_pad_io13_pad, + inout wire logic pad_pad_io14_pad, + inout wire logic pad_pad_io15_pad, + inout wire logic pad_pad_io16_pad, + inout wire logic pad_pad_io17_pad, + inout wire logic pad_pad_io18_pad, + inout wire logic pad_pad_io19_pad, + inout wire logic pad_pad_io20_pad, + inout wire logic pad_pad_io21_pad, + inout wire logic pad_pad_io22_pad, + inout wire logic pad_pad_io23_pad, + inout wire logic pad_pad_io24_pad, + inout wire logic pad_pad_io25_pad, + inout wire logic pad_pad_io26_pad, + inout wire logic pad_pad_io27_pad, + inout wire logic pad_pad_io28_pad, + inout wire logic pad_pad_io29_pad, + inout wire logic pad_pad_io30_pad, + inout wire logic pad_pad_io31_pad, + input req_t config_req_i, + output resp_t config_rsp_o +); + + mux_to_pads_t s_mux_to_pads; + pads_to_mux_t s_pads_to_mux; + + pulpissimo_padframe_all_pads_pads i_all_pads_pads ( + .static_connection_signals_pad2soc, + .static_connection_signals_soc2pad, + .mux_to_pads_i(s_mux_to_pads), + .pads_to_mux_o(s_pads_to_mux), + .pad_pad_ref_clk_pad, + .pad_pad_clk_byp_en_pad, + .pad_pad_reset_n_pad, + .pad_pad_bootsel0_pad, + .pad_pad_bootsel1_pad, + .pad_pad_jtag_tck_pad, + .pad_pad_jtag_trstn_pad, + .pad_pad_jtag_tms_pad, + .pad_pad_jtag_tdi_pad, + .pad_pad_jtag_tdo_pad, + .pad_pad_hyper_csn0_pad, + .pad_pad_hyper_csn1_pad, + .pad_pad_hyper_reset_n_pad, + .pad_pad_hyper_ck_pad, + .pad_pad_hyper_ckn_pad, + .pad_pad_hyper_dq0_pad, + .pad_pad_hyper_dq1_pad, + .pad_pad_hyper_dq2_pad, + .pad_pad_hyper_dq3_pad, + .pad_pad_hyper_dq4_pad, + .pad_pad_hyper_dq5_pad, + .pad_pad_hyper_dq6_pad, + .pad_pad_hyper_dq7_pad, + .pad_pad_hyper_rwds_pad, + .pad_pad_io00_pad, + .pad_pad_io01_pad, + .pad_pad_io02_pad, + .pad_pad_io03_pad, + .pad_pad_io04_pad, + .pad_pad_io05_pad, + .pad_pad_io06_pad, + .pad_pad_io07_pad, + .pad_pad_io08_pad, + .pad_pad_io09_pad, + .pad_pad_io10_pad, + .pad_pad_io11_pad, + .pad_pad_io12_pad, + .pad_pad_io13_pad, + .pad_pad_io14_pad, + .pad_pad_io15_pad, + .pad_pad_io16_pad, + .pad_pad_io17_pad, + .pad_pad_io18_pad, + .pad_pad_io19_pad, + .pad_pad_io20_pad, + .pad_pad_io21_pad, + .pad_pad_io22_pad, + .pad_pad_io23_pad, + .pad_pad_io24_pad, + .pad_pad_io25_pad, + .pad_pad_io26_pad, + .pad_pad_io27_pad, + .pad_pad_io28_pad, + .pad_pad_io29_pad, + .pad_pad_io30_pad, + .pad_pad_io31_pad + + ); + + pulpissimo_padframe_all_pads_muxer #( + .req_t(req_t), + .resp_t(resp_t) + )i_all_pads_muxer ( + .clk_i, + .rst_ni, + .port_signals_soc2pad_i, + .port_signals_pad2soc_o, + .mux_to_pads_o(s_mux_to_pads), + .pads_to_mux_i(s_pads_to_mux), + // Configuration interface using register_interface protocol + .config_req_i, + .config_rsp_o + ); + +endmodule : pulpissimo_padframe_all_pads diff --git a/hw/padframe/pulpissimo_padframe_fpga_autogen/src/pulpissimo_padframe_all_pads_config_reg_pkg.sv b/hw/padframe/pulpissimo_padframe_fpga_autogen/src/pulpissimo_padframe_all_pads_config_reg_pkg.sv new file mode 100644 index 00000000..b35f85b1 --- /dev/null +++ b/hw/padframe/pulpissimo_padframe_fpga_autogen/src/pulpissimo_padframe_all_pads_config_reg_pkg.sv @@ -0,0 +1,812 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package pulpissimo_padframe_all_pads_config_reg_pkg; + + // Address widths within the block + parameter int BlockAw = 9; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + struct packed { + logic [15:0] q; + } hw_version; + struct packed { + logic [15:0] q; + } padcount; + } pulpissimo_padframe_all_pads_config_reg2hw_info_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io00_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io00_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io01_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io01_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io02_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io02_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io03_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io03_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io04_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io04_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io05_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io05_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io06_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io06_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io07_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io07_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io08_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io08_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io09_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io09_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io10_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io10_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io11_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io11_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io12_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io12_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io13_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io13_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io14_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io14_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io15_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io15_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io16_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io16_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io17_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io17_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io18_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io18_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io19_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io19_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io20_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io20_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io21_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io21_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io22_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io22_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io23_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io23_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io24_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io24_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io25_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io25_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io26_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io26_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io27_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io27_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io28_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io28_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io29_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io29_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io30_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io30_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io31_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io31_mux_sel_reg_t; + + // Register -> HW type + typedef struct packed { + pulpissimo_padframe_all_pads_config_reg2hw_info_reg_t info; // [319:288] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io00_cfg_reg_t pad_io00_cfg; // [287:285] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io00_mux_sel_reg_t pad_io00_mux_sel; // [284:279] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io01_cfg_reg_t pad_io01_cfg; // [278:276] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io01_mux_sel_reg_t pad_io01_mux_sel; // [275:270] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io02_cfg_reg_t pad_io02_cfg; // [269:267] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io02_mux_sel_reg_t pad_io02_mux_sel; // [266:261] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io03_cfg_reg_t pad_io03_cfg; // [260:258] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io03_mux_sel_reg_t pad_io03_mux_sel; // [257:252] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io04_cfg_reg_t pad_io04_cfg; // [251:249] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io04_mux_sel_reg_t pad_io04_mux_sel; // [248:243] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io05_cfg_reg_t pad_io05_cfg; // [242:240] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io05_mux_sel_reg_t pad_io05_mux_sel; // [239:234] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io06_cfg_reg_t pad_io06_cfg; // [233:231] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io06_mux_sel_reg_t pad_io06_mux_sel; // [230:225] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io07_cfg_reg_t pad_io07_cfg; // [224:222] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io07_mux_sel_reg_t pad_io07_mux_sel; // [221:216] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io08_cfg_reg_t pad_io08_cfg; // [215:213] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io08_mux_sel_reg_t pad_io08_mux_sel; // [212:207] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io09_cfg_reg_t pad_io09_cfg; // [206:204] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io09_mux_sel_reg_t pad_io09_mux_sel; // [203:198] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io10_cfg_reg_t pad_io10_cfg; // [197:195] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io10_mux_sel_reg_t pad_io10_mux_sel; // [194:189] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io11_cfg_reg_t pad_io11_cfg; // [188:186] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io11_mux_sel_reg_t pad_io11_mux_sel; // [185:180] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io12_cfg_reg_t pad_io12_cfg; // [179:177] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io12_mux_sel_reg_t pad_io12_mux_sel; // [176:171] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io13_cfg_reg_t pad_io13_cfg; // [170:168] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io13_mux_sel_reg_t pad_io13_mux_sel; // [167:162] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io14_cfg_reg_t pad_io14_cfg; // [161:159] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io14_mux_sel_reg_t pad_io14_mux_sel; // [158:153] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io15_cfg_reg_t pad_io15_cfg; // [152:150] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io15_mux_sel_reg_t pad_io15_mux_sel; // [149:144] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io16_cfg_reg_t pad_io16_cfg; // [143:141] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io16_mux_sel_reg_t pad_io16_mux_sel; // [140:135] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io17_cfg_reg_t pad_io17_cfg; // [134:132] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io17_mux_sel_reg_t pad_io17_mux_sel; // [131:126] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io18_cfg_reg_t pad_io18_cfg; // [125:123] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io18_mux_sel_reg_t pad_io18_mux_sel; // [122:117] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io19_cfg_reg_t pad_io19_cfg; // [116:114] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io19_mux_sel_reg_t pad_io19_mux_sel; // [113:108] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io20_cfg_reg_t pad_io20_cfg; // [107:105] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io20_mux_sel_reg_t pad_io20_mux_sel; // [104:99] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io21_cfg_reg_t pad_io21_cfg; // [98:96] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io21_mux_sel_reg_t pad_io21_mux_sel; // [95:90] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io22_cfg_reg_t pad_io22_cfg; // [89:87] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io22_mux_sel_reg_t pad_io22_mux_sel; // [86:81] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io23_cfg_reg_t pad_io23_cfg; // [80:78] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io23_mux_sel_reg_t pad_io23_mux_sel; // [77:72] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io24_cfg_reg_t pad_io24_cfg; // [71:69] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io24_mux_sel_reg_t pad_io24_mux_sel; // [68:63] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io25_cfg_reg_t pad_io25_cfg; // [62:60] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io25_mux_sel_reg_t pad_io25_mux_sel; // [59:54] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io26_cfg_reg_t pad_io26_cfg; // [53:51] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io26_mux_sel_reg_t pad_io26_mux_sel; // [50:45] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io27_cfg_reg_t pad_io27_cfg; // [44:42] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io27_mux_sel_reg_t pad_io27_mux_sel; // [41:36] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io28_cfg_reg_t pad_io28_cfg; // [35:33] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io28_mux_sel_reg_t pad_io28_mux_sel; // [32:27] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io29_cfg_reg_t pad_io29_cfg; // [26:24] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io29_mux_sel_reg_t pad_io29_mux_sel; // [23:18] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io30_cfg_reg_t pad_io30_cfg; // [17:15] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io30_mux_sel_reg_t pad_io30_mux_sel; // [14:9] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io31_cfg_reg_t pad_io31_cfg; // [8:6] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io31_mux_sel_reg_t pad_io31_mux_sel; // [5:0] + } pulpissimo_padframe_all_pads_config_reg2hw_t; + + // Register offsets + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_OFFSET = 9'h 0; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_OFFSET = 9'h 4; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_OFFSET = 9'h 8; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_CFG_OFFSET = 9'h c; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_OFFSET = 9'h 10; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_CFG_OFFSET = 9'h 14; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_OFFSET = 9'h 18; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_CFG_OFFSET = 9'h 1c; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_OFFSET = 9'h 20; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_CFG_OFFSET = 9'h 24; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_OFFSET = 9'h 28; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_CFG_OFFSET = 9'h 2c; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_OFFSET = 9'h 30; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_CFG_OFFSET = 9'h 34; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_OFFSET = 9'h 38; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_CFG_OFFSET = 9'h 3c; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_OFFSET = 9'h 40; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_CFG_OFFSET = 9'h 44; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_OFFSET = 9'h 48; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_CFG_OFFSET = 9'h 4c; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_OFFSET = 9'h 50; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_CFG_OFFSET = 9'h 54; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_OFFSET = 9'h 58; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_CFG_OFFSET = 9'h 5c; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_OFFSET = 9'h 60; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_CFG_OFFSET = 9'h 64; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_OFFSET = 9'h 68; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_CFG_OFFSET = 9'h 6c; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_OFFSET = 9'h 70; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_CFG_OFFSET = 9'h 74; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_OFFSET = 9'h 78; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_CFG_OFFSET = 9'h 7c; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_OFFSET = 9'h 80; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_CFG_OFFSET = 9'h 84; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_OFFSET = 9'h 88; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_CFG_OFFSET = 9'h 8c; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_OFFSET = 9'h 90; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_CFG_OFFSET = 9'h 94; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_OFFSET = 9'h 98; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_CFG_OFFSET = 9'h 9c; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_OFFSET = 9'h a0; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_CFG_OFFSET = 9'h a4; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_OFFSET = 9'h a8; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_CFG_OFFSET = 9'h ac; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_OFFSET = 9'h b0; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_CFG_OFFSET = 9'h b4; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_OFFSET = 9'h b8; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_CFG_OFFSET = 9'h bc; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_OFFSET = 9'h c0; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_CFG_OFFSET = 9'h c4; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_OFFSET = 9'h c8; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_CFG_OFFSET = 9'h cc; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_OFFSET = 9'h d0; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_CFG_OFFSET = 9'h d4; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_OFFSET = 9'h d8; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_CFG_OFFSET = 9'h dc; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_OFFSET = 9'h e0; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_CFG_OFFSET = 9'h e4; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_OFFSET = 9'h e8; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_CFG_OFFSET = 9'h ec; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_OFFSET = 9'h f0; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_CFG_OFFSET = 9'h f4; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_OFFSET = 9'h f8; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_CFG_OFFSET = 9'h fc; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_OFFSET = 9'h 100; + + // Register index + typedef enum int { + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL + } pulpissimo_padframe_all_pads_config_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT [65] = '{ + 4'b 1111, // index[ 0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO + 4'b 0001, // index[ 1] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG + 4'b 0001, // index[ 2] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL + 4'b 0001, // index[ 3] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_CFG + 4'b 0001, // index[ 4] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL + 4'b 0001, // index[ 5] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_CFG + 4'b 0001, // index[ 6] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL + 4'b 0001, // index[ 7] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_CFG + 4'b 0001, // index[ 8] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL + 4'b 0001, // index[ 9] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_CFG + 4'b 0001, // index[10] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL + 4'b 0001, // index[11] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_CFG + 4'b 0001, // index[12] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL + 4'b 0001, // index[13] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_CFG + 4'b 0001, // index[14] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL + 4'b 0001, // index[15] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_CFG + 4'b 0001, // index[16] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL + 4'b 0001, // index[17] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_CFG + 4'b 0001, // index[18] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL + 4'b 0001, // index[19] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_CFG + 4'b 0001, // index[20] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL + 4'b 0001, // index[21] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_CFG + 4'b 0001, // index[22] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL + 4'b 0001, // index[23] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_CFG + 4'b 0001, // index[24] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL + 4'b 0001, // index[25] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_CFG + 4'b 0001, // index[26] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL + 4'b 0001, // index[27] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_CFG + 4'b 0001, // index[28] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL + 4'b 0001, // index[29] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_CFG + 4'b 0001, // index[30] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL + 4'b 0001, // index[31] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_CFG + 4'b 0001, // index[32] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL + 4'b 0001, // index[33] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_CFG + 4'b 0001, // index[34] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL + 4'b 0001, // index[35] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_CFG + 4'b 0001, // index[36] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL + 4'b 0001, // index[37] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_CFG + 4'b 0001, // index[38] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL + 4'b 0001, // index[39] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_CFG + 4'b 0001, // index[40] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL + 4'b 0001, // index[41] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_CFG + 4'b 0001, // index[42] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL + 4'b 0001, // index[43] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_CFG + 4'b 0001, // index[44] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL + 4'b 0001, // index[45] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_CFG + 4'b 0001, // index[46] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL + 4'b 0001, // index[47] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_CFG + 4'b 0001, // index[48] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL + 4'b 0001, // index[49] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_CFG + 4'b 0001, // index[50] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL + 4'b 0001, // index[51] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_CFG + 4'b 0001, // index[52] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL + 4'b 0001, // index[53] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_CFG + 4'b 0001, // index[54] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL + 4'b 0001, // index[55] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_CFG + 4'b 0001, // index[56] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL + 4'b 0001, // index[57] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_CFG + 4'b 0001, // index[58] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL + 4'b 0001, // index[59] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_CFG + 4'b 0001, // index[60] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL + 4'b 0001, // index[61] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_CFG + 4'b 0001, // index[62] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL + 4'b 0001, // index[63] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_CFG + 4'b 0001 // index[64] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL + }; + +endpackage + diff --git a/hw/padframe/pulpissimo_padframe_fpga_autogen/src/pulpissimo_padframe_all_pads_config_reg_top.sv b/hw/padframe/pulpissimo_padframe_fpga_autogen/src/pulpissimo_padframe_all_pads_config_reg_top.sv new file mode 100644 index 00000000..71b7ba0e --- /dev/null +++ b/hw/padframe/pulpissimo_padframe_fpga_autogen/src/pulpissimo_padframe_all_pads_config_reg_top.sv @@ -0,0 +1,4809 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + + +`include "common_cells/assertions.svh" + +module pulpissimo_padframe_all_pads_config_reg_top #( + parameter type reg_req_t = logic, + parameter type reg_rsp_t = logic, + parameter int AW = 9 +) ( + input clk_i, + input rst_ni, + input reg_req_t reg_req_i, + output reg_rsp_t reg_rsp_o, + // To HW + output pulpissimo_padframe_all_pads_config_reg_pkg::pulpissimo_padframe_all_pads_config_reg2hw_t reg2hw, // Write + + + // Config + input devmode_i // If 1, explicit error return for unmapped register access +); + + import pulpissimo_padframe_all_pads_config_reg_pkg::* ; + + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + + // Below register interface can be changed + reg_req_t reg_intf_req; + reg_rsp_t reg_intf_rsp; + + + assign reg_intf_req = reg_req_i; + assign reg_rsp_o = reg_intf_rsp; + + + assign reg_we = reg_intf_req.valid & reg_intf_req.write; + assign reg_re = reg_intf_req.valid & ~reg_intf_req.write; + assign reg_addr = reg_intf_req.addr; + assign reg_wdata = reg_intf_req.wdata; + assign reg_be = reg_intf_req.wstrb; + assign reg_intf_rsp.rdata = reg_rdata; + assign reg_intf_rsp.error = reg_error; + assign reg_intf_rsp.ready = 1'b1; + + assign reg_rdata = reg_rdata_next ; + assign reg_error = (devmode_i & addrmiss) | wr_err; + + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic [15:0] info_hw_version_qs; + logic [15:0] info_padcount_qs; + logic pad_io00_cfg_chip2pad_qs; + logic pad_io00_cfg_chip2pad_wd; + logic pad_io00_cfg_chip2pad_we; + logic pad_io00_cfg_rx_en_qs; + logic pad_io00_cfg_rx_en_wd; + logic pad_io00_cfg_rx_en_we; + logic pad_io00_cfg_tx_en_qs; + logic pad_io00_cfg_tx_en_wd; + logic pad_io00_cfg_tx_en_we; + logic [5:0] pad_io00_mux_sel_qs; + logic [5:0] pad_io00_mux_sel_wd; + logic pad_io00_mux_sel_we; + logic pad_io01_cfg_chip2pad_qs; + logic pad_io01_cfg_chip2pad_wd; + logic pad_io01_cfg_chip2pad_we; + logic pad_io01_cfg_rx_en_qs; + logic pad_io01_cfg_rx_en_wd; + logic pad_io01_cfg_rx_en_we; + logic pad_io01_cfg_tx_en_qs; + logic pad_io01_cfg_tx_en_wd; + logic pad_io01_cfg_tx_en_we; + logic [5:0] pad_io01_mux_sel_qs; + logic [5:0] pad_io01_mux_sel_wd; + logic pad_io01_mux_sel_we; + logic pad_io02_cfg_chip2pad_qs; + logic pad_io02_cfg_chip2pad_wd; + logic pad_io02_cfg_chip2pad_we; + logic pad_io02_cfg_rx_en_qs; + logic pad_io02_cfg_rx_en_wd; + logic pad_io02_cfg_rx_en_we; + logic pad_io02_cfg_tx_en_qs; + logic pad_io02_cfg_tx_en_wd; + logic pad_io02_cfg_tx_en_we; + logic [5:0] pad_io02_mux_sel_qs; + logic [5:0] pad_io02_mux_sel_wd; + logic pad_io02_mux_sel_we; + logic pad_io03_cfg_chip2pad_qs; + logic pad_io03_cfg_chip2pad_wd; + logic pad_io03_cfg_chip2pad_we; + logic pad_io03_cfg_rx_en_qs; + logic pad_io03_cfg_rx_en_wd; + logic pad_io03_cfg_rx_en_we; + logic pad_io03_cfg_tx_en_qs; + logic pad_io03_cfg_tx_en_wd; + logic pad_io03_cfg_tx_en_we; + logic [5:0] pad_io03_mux_sel_qs; + logic [5:0] pad_io03_mux_sel_wd; + logic pad_io03_mux_sel_we; + logic pad_io04_cfg_chip2pad_qs; + logic pad_io04_cfg_chip2pad_wd; + logic pad_io04_cfg_chip2pad_we; + logic pad_io04_cfg_rx_en_qs; + logic pad_io04_cfg_rx_en_wd; + logic pad_io04_cfg_rx_en_we; + logic pad_io04_cfg_tx_en_qs; + logic pad_io04_cfg_tx_en_wd; + logic pad_io04_cfg_tx_en_we; + logic [5:0] pad_io04_mux_sel_qs; + logic [5:0] pad_io04_mux_sel_wd; + logic pad_io04_mux_sel_we; + logic pad_io05_cfg_chip2pad_qs; + logic pad_io05_cfg_chip2pad_wd; + logic pad_io05_cfg_chip2pad_we; + logic pad_io05_cfg_rx_en_qs; + logic pad_io05_cfg_rx_en_wd; + logic pad_io05_cfg_rx_en_we; + logic pad_io05_cfg_tx_en_qs; + logic pad_io05_cfg_tx_en_wd; + logic pad_io05_cfg_tx_en_we; + logic [5:0] pad_io05_mux_sel_qs; + logic [5:0] pad_io05_mux_sel_wd; + logic pad_io05_mux_sel_we; + logic pad_io06_cfg_chip2pad_qs; + logic pad_io06_cfg_chip2pad_wd; + logic pad_io06_cfg_chip2pad_we; + logic pad_io06_cfg_rx_en_qs; + logic pad_io06_cfg_rx_en_wd; + logic pad_io06_cfg_rx_en_we; + logic pad_io06_cfg_tx_en_qs; + logic pad_io06_cfg_tx_en_wd; + logic pad_io06_cfg_tx_en_we; + logic [5:0] pad_io06_mux_sel_qs; + logic [5:0] pad_io06_mux_sel_wd; + logic pad_io06_mux_sel_we; + logic pad_io07_cfg_chip2pad_qs; + logic pad_io07_cfg_chip2pad_wd; + logic pad_io07_cfg_chip2pad_we; + logic pad_io07_cfg_rx_en_qs; + logic pad_io07_cfg_rx_en_wd; + logic pad_io07_cfg_rx_en_we; + logic pad_io07_cfg_tx_en_qs; + logic pad_io07_cfg_tx_en_wd; + logic pad_io07_cfg_tx_en_we; + logic [5:0] pad_io07_mux_sel_qs; + logic [5:0] pad_io07_mux_sel_wd; + logic pad_io07_mux_sel_we; + logic pad_io08_cfg_chip2pad_qs; + logic pad_io08_cfg_chip2pad_wd; + logic pad_io08_cfg_chip2pad_we; + logic pad_io08_cfg_rx_en_qs; + logic pad_io08_cfg_rx_en_wd; + logic pad_io08_cfg_rx_en_we; + logic pad_io08_cfg_tx_en_qs; + logic pad_io08_cfg_tx_en_wd; + logic pad_io08_cfg_tx_en_we; + logic [5:0] pad_io08_mux_sel_qs; + logic [5:0] pad_io08_mux_sel_wd; + logic pad_io08_mux_sel_we; + logic pad_io09_cfg_chip2pad_qs; + logic pad_io09_cfg_chip2pad_wd; + logic pad_io09_cfg_chip2pad_we; + logic pad_io09_cfg_rx_en_qs; + logic pad_io09_cfg_rx_en_wd; + logic pad_io09_cfg_rx_en_we; + logic pad_io09_cfg_tx_en_qs; + logic pad_io09_cfg_tx_en_wd; + logic pad_io09_cfg_tx_en_we; + logic [5:0] pad_io09_mux_sel_qs; + logic [5:0] pad_io09_mux_sel_wd; + logic pad_io09_mux_sel_we; + logic pad_io10_cfg_chip2pad_qs; + logic pad_io10_cfg_chip2pad_wd; + logic pad_io10_cfg_chip2pad_we; + logic pad_io10_cfg_rx_en_qs; + logic pad_io10_cfg_rx_en_wd; + logic pad_io10_cfg_rx_en_we; + logic pad_io10_cfg_tx_en_qs; + logic pad_io10_cfg_tx_en_wd; + logic pad_io10_cfg_tx_en_we; + logic [5:0] pad_io10_mux_sel_qs; + logic [5:0] pad_io10_mux_sel_wd; + logic pad_io10_mux_sel_we; + logic pad_io11_cfg_chip2pad_qs; + logic pad_io11_cfg_chip2pad_wd; + logic pad_io11_cfg_chip2pad_we; + logic pad_io11_cfg_rx_en_qs; + logic pad_io11_cfg_rx_en_wd; + logic pad_io11_cfg_rx_en_we; + logic pad_io11_cfg_tx_en_qs; + logic pad_io11_cfg_tx_en_wd; + logic pad_io11_cfg_tx_en_we; + logic [5:0] pad_io11_mux_sel_qs; + logic [5:0] pad_io11_mux_sel_wd; + logic pad_io11_mux_sel_we; + logic pad_io12_cfg_chip2pad_qs; + logic pad_io12_cfg_chip2pad_wd; + logic pad_io12_cfg_chip2pad_we; + logic pad_io12_cfg_rx_en_qs; + logic pad_io12_cfg_rx_en_wd; + logic pad_io12_cfg_rx_en_we; + logic pad_io12_cfg_tx_en_qs; + logic pad_io12_cfg_tx_en_wd; + logic pad_io12_cfg_tx_en_we; + logic [5:0] pad_io12_mux_sel_qs; + logic [5:0] pad_io12_mux_sel_wd; + logic pad_io12_mux_sel_we; + logic pad_io13_cfg_chip2pad_qs; + logic pad_io13_cfg_chip2pad_wd; + logic pad_io13_cfg_chip2pad_we; + logic pad_io13_cfg_rx_en_qs; + logic pad_io13_cfg_rx_en_wd; + logic pad_io13_cfg_rx_en_we; + logic pad_io13_cfg_tx_en_qs; + logic pad_io13_cfg_tx_en_wd; + logic pad_io13_cfg_tx_en_we; + logic [5:0] pad_io13_mux_sel_qs; + logic [5:0] pad_io13_mux_sel_wd; + logic pad_io13_mux_sel_we; + logic pad_io14_cfg_chip2pad_qs; + logic pad_io14_cfg_chip2pad_wd; + logic pad_io14_cfg_chip2pad_we; + logic pad_io14_cfg_rx_en_qs; + logic pad_io14_cfg_rx_en_wd; + logic pad_io14_cfg_rx_en_we; + logic pad_io14_cfg_tx_en_qs; + logic pad_io14_cfg_tx_en_wd; + logic pad_io14_cfg_tx_en_we; + logic [5:0] pad_io14_mux_sel_qs; + logic [5:0] pad_io14_mux_sel_wd; + logic pad_io14_mux_sel_we; + logic pad_io15_cfg_chip2pad_qs; + logic pad_io15_cfg_chip2pad_wd; + logic pad_io15_cfg_chip2pad_we; + logic pad_io15_cfg_rx_en_qs; + logic pad_io15_cfg_rx_en_wd; + logic pad_io15_cfg_rx_en_we; + logic pad_io15_cfg_tx_en_qs; + logic pad_io15_cfg_tx_en_wd; + logic pad_io15_cfg_tx_en_we; + logic [5:0] pad_io15_mux_sel_qs; + logic [5:0] pad_io15_mux_sel_wd; + logic pad_io15_mux_sel_we; + logic pad_io16_cfg_chip2pad_qs; + logic pad_io16_cfg_chip2pad_wd; + logic pad_io16_cfg_chip2pad_we; + logic pad_io16_cfg_rx_en_qs; + logic pad_io16_cfg_rx_en_wd; + logic pad_io16_cfg_rx_en_we; + logic pad_io16_cfg_tx_en_qs; + logic pad_io16_cfg_tx_en_wd; + logic pad_io16_cfg_tx_en_we; + logic [5:0] pad_io16_mux_sel_qs; + logic [5:0] pad_io16_mux_sel_wd; + logic pad_io16_mux_sel_we; + logic pad_io17_cfg_chip2pad_qs; + logic pad_io17_cfg_chip2pad_wd; + logic pad_io17_cfg_chip2pad_we; + logic pad_io17_cfg_rx_en_qs; + logic pad_io17_cfg_rx_en_wd; + logic pad_io17_cfg_rx_en_we; + logic pad_io17_cfg_tx_en_qs; + logic pad_io17_cfg_tx_en_wd; + logic pad_io17_cfg_tx_en_we; + logic [5:0] pad_io17_mux_sel_qs; + logic [5:0] pad_io17_mux_sel_wd; + logic pad_io17_mux_sel_we; + logic pad_io18_cfg_chip2pad_qs; + logic pad_io18_cfg_chip2pad_wd; + logic pad_io18_cfg_chip2pad_we; + logic pad_io18_cfg_rx_en_qs; + logic pad_io18_cfg_rx_en_wd; + logic pad_io18_cfg_rx_en_we; + logic pad_io18_cfg_tx_en_qs; + logic pad_io18_cfg_tx_en_wd; + logic pad_io18_cfg_tx_en_we; + logic [5:0] pad_io18_mux_sel_qs; + logic [5:0] pad_io18_mux_sel_wd; + logic pad_io18_mux_sel_we; + logic pad_io19_cfg_chip2pad_qs; + logic pad_io19_cfg_chip2pad_wd; + logic pad_io19_cfg_chip2pad_we; + logic pad_io19_cfg_rx_en_qs; + logic pad_io19_cfg_rx_en_wd; + logic pad_io19_cfg_rx_en_we; + logic pad_io19_cfg_tx_en_qs; + logic pad_io19_cfg_tx_en_wd; + logic pad_io19_cfg_tx_en_we; + logic [5:0] pad_io19_mux_sel_qs; + logic [5:0] pad_io19_mux_sel_wd; + logic pad_io19_mux_sel_we; + logic pad_io20_cfg_chip2pad_qs; + logic pad_io20_cfg_chip2pad_wd; + logic pad_io20_cfg_chip2pad_we; + logic pad_io20_cfg_rx_en_qs; + logic pad_io20_cfg_rx_en_wd; + logic pad_io20_cfg_rx_en_we; + logic pad_io20_cfg_tx_en_qs; + logic pad_io20_cfg_tx_en_wd; + logic pad_io20_cfg_tx_en_we; + logic [5:0] pad_io20_mux_sel_qs; + logic [5:0] pad_io20_mux_sel_wd; + logic pad_io20_mux_sel_we; + logic pad_io21_cfg_chip2pad_qs; + logic pad_io21_cfg_chip2pad_wd; + logic pad_io21_cfg_chip2pad_we; + logic pad_io21_cfg_rx_en_qs; + logic pad_io21_cfg_rx_en_wd; + logic pad_io21_cfg_rx_en_we; + logic pad_io21_cfg_tx_en_qs; + logic pad_io21_cfg_tx_en_wd; + logic pad_io21_cfg_tx_en_we; + logic [5:0] pad_io21_mux_sel_qs; + logic [5:0] pad_io21_mux_sel_wd; + logic pad_io21_mux_sel_we; + logic pad_io22_cfg_chip2pad_qs; + logic pad_io22_cfg_chip2pad_wd; + logic pad_io22_cfg_chip2pad_we; + logic pad_io22_cfg_rx_en_qs; + logic pad_io22_cfg_rx_en_wd; + logic pad_io22_cfg_rx_en_we; + logic pad_io22_cfg_tx_en_qs; + logic pad_io22_cfg_tx_en_wd; + logic pad_io22_cfg_tx_en_we; + logic [5:0] pad_io22_mux_sel_qs; + logic [5:0] pad_io22_mux_sel_wd; + logic pad_io22_mux_sel_we; + logic pad_io23_cfg_chip2pad_qs; + logic pad_io23_cfg_chip2pad_wd; + logic pad_io23_cfg_chip2pad_we; + logic pad_io23_cfg_rx_en_qs; + logic pad_io23_cfg_rx_en_wd; + logic pad_io23_cfg_rx_en_we; + logic pad_io23_cfg_tx_en_qs; + logic pad_io23_cfg_tx_en_wd; + logic pad_io23_cfg_tx_en_we; + logic [5:0] pad_io23_mux_sel_qs; + logic [5:0] pad_io23_mux_sel_wd; + logic pad_io23_mux_sel_we; + logic pad_io24_cfg_chip2pad_qs; + logic pad_io24_cfg_chip2pad_wd; + logic pad_io24_cfg_chip2pad_we; + logic pad_io24_cfg_rx_en_qs; + logic pad_io24_cfg_rx_en_wd; + logic pad_io24_cfg_rx_en_we; + logic pad_io24_cfg_tx_en_qs; + logic pad_io24_cfg_tx_en_wd; + logic pad_io24_cfg_tx_en_we; + logic [5:0] pad_io24_mux_sel_qs; + logic [5:0] pad_io24_mux_sel_wd; + logic pad_io24_mux_sel_we; + logic pad_io25_cfg_chip2pad_qs; + logic pad_io25_cfg_chip2pad_wd; + logic pad_io25_cfg_chip2pad_we; + logic pad_io25_cfg_rx_en_qs; + logic pad_io25_cfg_rx_en_wd; + logic pad_io25_cfg_rx_en_we; + logic pad_io25_cfg_tx_en_qs; + logic pad_io25_cfg_tx_en_wd; + logic pad_io25_cfg_tx_en_we; + logic [5:0] pad_io25_mux_sel_qs; + logic [5:0] pad_io25_mux_sel_wd; + logic pad_io25_mux_sel_we; + logic pad_io26_cfg_chip2pad_qs; + logic pad_io26_cfg_chip2pad_wd; + logic pad_io26_cfg_chip2pad_we; + logic pad_io26_cfg_rx_en_qs; + logic pad_io26_cfg_rx_en_wd; + logic pad_io26_cfg_rx_en_we; + logic pad_io26_cfg_tx_en_qs; + logic pad_io26_cfg_tx_en_wd; + logic pad_io26_cfg_tx_en_we; + logic [5:0] pad_io26_mux_sel_qs; + logic [5:0] pad_io26_mux_sel_wd; + logic pad_io26_mux_sel_we; + logic pad_io27_cfg_chip2pad_qs; + logic pad_io27_cfg_chip2pad_wd; + logic pad_io27_cfg_chip2pad_we; + logic pad_io27_cfg_rx_en_qs; + logic pad_io27_cfg_rx_en_wd; + logic pad_io27_cfg_rx_en_we; + logic pad_io27_cfg_tx_en_qs; + logic pad_io27_cfg_tx_en_wd; + logic pad_io27_cfg_tx_en_we; + logic [5:0] pad_io27_mux_sel_qs; + logic [5:0] pad_io27_mux_sel_wd; + logic pad_io27_mux_sel_we; + logic pad_io28_cfg_chip2pad_qs; + logic pad_io28_cfg_chip2pad_wd; + logic pad_io28_cfg_chip2pad_we; + logic pad_io28_cfg_rx_en_qs; + logic pad_io28_cfg_rx_en_wd; + logic pad_io28_cfg_rx_en_we; + logic pad_io28_cfg_tx_en_qs; + logic pad_io28_cfg_tx_en_wd; + logic pad_io28_cfg_tx_en_we; + logic [5:0] pad_io28_mux_sel_qs; + logic [5:0] pad_io28_mux_sel_wd; + logic pad_io28_mux_sel_we; + logic pad_io29_cfg_chip2pad_qs; + logic pad_io29_cfg_chip2pad_wd; + logic pad_io29_cfg_chip2pad_we; + logic pad_io29_cfg_rx_en_qs; + logic pad_io29_cfg_rx_en_wd; + logic pad_io29_cfg_rx_en_we; + logic pad_io29_cfg_tx_en_qs; + logic pad_io29_cfg_tx_en_wd; + logic pad_io29_cfg_tx_en_we; + logic [5:0] pad_io29_mux_sel_qs; + logic [5:0] pad_io29_mux_sel_wd; + logic pad_io29_mux_sel_we; + logic pad_io30_cfg_chip2pad_qs; + logic pad_io30_cfg_chip2pad_wd; + logic pad_io30_cfg_chip2pad_we; + logic pad_io30_cfg_rx_en_qs; + logic pad_io30_cfg_rx_en_wd; + logic pad_io30_cfg_rx_en_we; + logic pad_io30_cfg_tx_en_qs; + logic pad_io30_cfg_tx_en_wd; + logic pad_io30_cfg_tx_en_we; + logic [5:0] pad_io30_mux_sel_qs; + logic [5:0] pad_io30_mux_sel_wd; + logic pad_io30_mux_sel_we; + logic pad_io31_cfg_chip2pad_qs; + logic pad_io31_cfg_chip2pad_wd; + logic pad_io31_cfg_chip2pad_we; + logic pad_io31_cfg_rx_en_qs; + logic pad_io31_cfg_rx_en_wd; + logic pad_io31_cfg_rx_en_we; + logic pad_io31_cfg_tx_en_qs; + logic pad_io31_cfg_tx_en_wd; + logic pad_io31_cfg_tx_en_we; + logic [5:0] pad_io31_mux_sel_qs; + logic [5:0] pad_io31_mux_sel_wd; + logic pad_io31_mux_sel_we; + + // Register instances + // R[info]: V(False) + + // F[hw_version]: 15:0 + prim_subreg #( + .DW (16), + .SWACCESS("RO"), + .RESVAL (16'h2) + ) u_info_hw_version ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.info.hw_version.q ), + + // to register interface (read) + .qs (info_hw_version_qs) + ); + + + // F[padcount]: 31:16 + prim_subreg #( + .DW (16), + .SWACCESS("RO"), + .RESVAL (16'h20) + ) u_info_padcount ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.info.padcount.q ), + + // to register interface (read) + .qs (info_padcount_qs) + ); + + + // R[pad_io00_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io00_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io00_cfg_chip2pad_we), + .wd (pad_io00_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io00_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io00_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io00_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io00_cfg_rx_en_we), + .wd (pad_io00_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io00_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io00_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io00_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io00_cfg_tx_en_we), + .wd (pad_io00_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io00_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io00_cfg_tx_en_qs) + ); + + + // R[pad_io00_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io00_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io00_mux_sel_we), + .wd (pad_io00_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io00_mux_sel.q ), + + // to register interface (read) + .qs (pad_io00_mux_sel_qs) + ); + + + // R[pad_io01_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io01_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io01_cfg_chip2pad_we), + .wd (pad_io01_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io01_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io01_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io01_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io01_cfg_rx_en_we), + .wd (pad_io01_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io01_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io01_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io01_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io01_cfg_tx_en_we), + .wd (pad_io01_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io01_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io01_cfg_tx_en_qs) + ); + + + // R[pad_io01_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io01_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io01_mux_sel_we), + .wd (pad_io01_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io01_mux_sel.q ), + + // to register interface (read) + .qs (pad_io01_mux_sel_qs) + ); + + + // R[pad_io02_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io02_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io02_cfg_chip2pad_we), + .wd (pad_io02_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io02_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io02_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io02_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io02_cfg_rx_en_we), + .wd (pad_io02_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io02_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io02_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io02_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io02_cfg_tx_en_we), + .wd (pad_io02_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io02_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io02_cfg_tx_en_qs) + ); + + + // R[pad_io02_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io02_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io02_mux_sel_we), + .wd (pad_io02_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io02_mux_sel.q ), + + // to register interface (read) + .qs (pad_io02_mux_sel_qs) + ); + + + // R[pad_io03_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io03_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io03_cfg_chip2pad_we), + .wd (pad_io03_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io03_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io03_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io03_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io03_cfg_rx_en_we), + .wd (pad_io03_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io03_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io03_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io03_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io03_cfg_tx_en_we), + .wd (pad_io03_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io03_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io03_cfg_tx_en_qs) + ); + + + // R[pad_io03_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io03_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io03_mux_sel_we), + .wd (pad_io03_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io03_mux_sel.q ), + + // to register interface (read) + .qs (pad_io03_mux_sel_qs) + ); + + + // R[pad_io04_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io04_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io04_cfg_chip2pad_we), + .wd (pad_io04_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io04_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io04_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io04_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io04_cfg_rx_en_we), + .wd (pad_io04_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io04_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io04_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io04_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io04_cfg_tx_en_we), + .wd (pad_io04_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io04_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io04_cfg_tx_en_qs) + ); + + + // R[pad_io04_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io04_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io04_mux_sel_we), + .wd (pad_io04_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io04_mux_sel.q ), + + // to register interface (read) + .qs (pad_io04_mux_sel_qs) + ); + + + // R[pad_io05_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io05_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io05_cfg_chip2pad_we), + .wd (pad_io05_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io05_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io05_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io05_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io05_cfg_rx_en_we), + .wd (pad_io05_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io05_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io05_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io05_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io05_cfg_tx_en_we), + .wd (pad_io05_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io05_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io05_cfg_tx_en_qs) + ); + + + // R[pad_io05_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io05_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io05_mux_sel_we), + .wd (pad_io05_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io05_mux_sel.q ), + + // to register interface (read) + .qs (pad_io05_mux_sel_qs) + ); + + + // R[pad_io06_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io06_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io06_cfg_chip2pad_we), + .wd (pad_io06_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io06_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io06_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io06_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io06_cfg_rx_en_we), + .wd (pad_io06_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io06_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io06_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io06_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io06_cfg_tx_en_we), + .wd (pad_io06_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io06_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io06_cfg_tx_en_qs) + ); + + + // R[pad_io06_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io06_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io06_mux_sel_we), + .wd (pad_io06_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io06_mux_sel.q ), + + // to register interface (read) + .qs (pad_io06_mux_sel_qs) + ); + + + // R[pad_io07_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io07_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io07_cfg_chip2pad_we), + .wd (pad_io07_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io07_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io07_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io07_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io07_cfg_rx_en_we), + .wd (pad_io07_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io07_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io07_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io07_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io07_cfg_tx_en_we), + .wd (pad_io07_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io07_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io07_cfg_tx_en_qs) + ); + + + // R[pad_io07_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io07_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io07_mux_sel_we), + .wd (pad_io07_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io07_mux_sel.q ), + + // to register interface (read) + .qs (pad_io07_mux_sel_qs) + ); + + + // R[pad_io08_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io08_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io08_cfg_chip2pad_we), + .wd (pad_io08_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io08_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io08_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io08_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io08_cfg_rx_en_we), + .wd (pad_io08_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io08_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io08_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io08_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io08_cfg_tx_en_we), + .wd (pad_io08_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io08_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io08_cfg_tx_en_qs) + ); + + + // R[pad_io08_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io08_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io08_mux_sel_we), + .wd (pad_io08_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io08_mux_sel.q ), + + // to register interface (read) + .qs (pad_io08_mux_sel_qs) + ); + + + // R[pad_io09_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io09_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io09_cfg_chip2pad_we), + .wd (pad_io09_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io09_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io09_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io09_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io09_cfg_rx_en_we), + .wd (pad_io09_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io09_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io09_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io09_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io09_cfg_tx_en_we), + .wd (pad_io09_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io09_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io09_cfg_tx_en_qs) + ); + + + // R[pad_io09_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io09_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io09_mux_sel_we), + .wd (pad_io09_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io09_mux_sel.q ), + + // to register interface (read) + .qs (pad_io09_mux_sel_qs) + ); + + + // R[pad_io10_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io10_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io10_cfg_chip2pad_we), + .wd (pad_io10_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io10_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io10_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io10_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io10_cfg_rx_en_we), + .wd (pad_io10_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io10_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io10_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io10_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io10_cfg_tx_en_we), + .wd (pad_io10_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io10_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io10_cfg_tx_en_qs) + ); + + + // R[pad_io10_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io10_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io10_mux_sel_we), + .wd (pad_io10_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io10_mux_sel.q ), + + // to register interface (read) + .qs (pad_io10_mux_sel_qs) + ); + + + // R[pad_io11_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io11_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io11_cfg_chip2pad_we), + .wd (pad_io11_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io11_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io11_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io11_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io11_cfg_rx_en_we), + .wd (pad_io11_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io11_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io11_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io11_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io11_cfg_tx_en_we), + .wd (pad_io11_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io11_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io11_cfg_tx_en_qs) + ); + + + // R[pad_io11_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io11_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io11_mux_sel_we), + .wd (pad_io11_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io11_mux_sel.q ), + + // to register interface (read) + .qs (pad_io11_mux_sel_qs) + ); + + + // R[pad_io12_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io12_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io12_cfg_chip2pad_we), + .wd (pad_io12_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io12_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io12_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io12_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io12_cfg_rx_en_we), + .wd (pad_io12_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io12_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io12_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io12_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io12_cfg_tx_en_we), + .wd (pad_io12_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io12_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io12_cfg_tx_en_qs) + ); + + + // R[pad_io12_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io12_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io12_mux_sel_we), + .wd (pad_io12_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io12_mux_sel.q ), + + // to register interface (read) + .qs (pad_io12_mux_sel_qs) + ); + + + // R[pad_io13_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io13_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io13_cfg_chip2pad_we), + .wd (pad_io13_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io13_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io13_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io13_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io13_cfg_rx_en_we), + .wd (pad_io13_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io13_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io13_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io13_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io13_cfg_tx_en_we), + .wd (pad_io13_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io13_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io13_cfg_tx_en_qs) + ); + + + // R[pad_io13_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io13_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io13_mux_sel_we), + .wd (pad_io13_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io13_mux_sel.q ), + + // to register interface (read) + .qs (pad_io13_mux_sel_qs) + ); + + + // R[pad_io14_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io14_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io14_cfg_chip2pad_we), + .wd (pad_io14_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io14_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io14_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io14_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io14_cfg_rx_en_we), + .wd (pad_io14_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io14_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io14_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io14_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io14_cfg_tx_en_we), + .wd (pad_io14_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io14_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io14_cfg_tx_en_qs) + ); + + + // R[pad_io14_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io14_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io14_mux_sel_we), + .wd (pad_io14_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io14_mux_sel.q ), + + // to register interface (read) + .qs (pad_io14_mux_sel_qs) + ); + + + // R[pad_io15_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io15_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io15_cfg_chip2pad_we), + .wd (pad_io15_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io15_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io15_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io15_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io15_cfg_rx_en_we), + .wd (pad_io15_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io15_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io15_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io15_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io15_cfg_tx_en_we), + .wd (pad_io15_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io15_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io15_cfg_tx_en_qs) + ); + + + // R[pad_io15_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io15_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io15_mux_sel_we), + .wd (pad_io15_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io15_mux_sel.q ), + + // to register interface (read) + .qs (pad_io15_mux_sel_qs) + ); + + + // R[pad_io16_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io16_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io16_cfg_chip2pad_we), + .wd (pad_io16_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io16_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io16_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io16_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io16_cfg_rx_en_we), + .wd (pad_io16_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io16_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io16_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io16_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io16_cfg_tx_en_we), + .wd (pad_io16_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io16_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io16_cfg_tx_en_qs) + ); + + + // R[pad_io16_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io16_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io16_mux_sel_we), + .wd (pad_io16_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io16_mux_sel.q ), + + // to register interface (read) + .qs (pad_io16_mux_sel_qs) + ); + + + // R[pad_io17_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io17_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io17_cfg_chip2pad_we), + .wd (pad_io17_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io17_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io17_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io17_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io17_cfg_rx_en_we), + .wd (pad_io17_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io17_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io17_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io17_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io17_cfg_tx_en_we), + .wd (pad_io17_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io17_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io17_cfg_tx_en_qs) + ); + + + // R[pad_io17_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io17_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io17_mux_sel_we), + .wd (pad_io17_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io17_mux_sel.q ), + + // to register interface (read) + .qs (pad_io17_mux_sel_qs) + ); + + + // R[pad_io18_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io18_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io18_cfg_chip2pad_we), + .wd (pad_io18_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io18_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io18_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io18_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io18_cfg_rx_en_we), + .wd (pad_io18_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io18_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io18_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io18_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io18_cfg_tx_en_we), + .wd (pad_io18_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io18_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io18_cfg_tx_en_qs) + ); + + + // R[pad_io18_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io18_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io18_mux_sel_we), + .wd (pad_io18_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io18_mux_sel.q ), + + // to register interface (read) + .qs (pad_io18_mux_sel_qs) + ); + + + // R[pad_io19_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io19_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io19_cfg_chip2pad_we), + .wd (pad_io19_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io19_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io19_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io19_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io19_cfg_rx_en_we), + .wd (pad_io19_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io19_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io19_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io19_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io19_cfg_tx_en_we), + .wd (pad_io19_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io19_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io19_cfg_tx_en_qs) + ); + + + // R[pad_io19_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io19_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io19_mux_sel_we), + .wd (pad_io19_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io19_mux_sel.q ), + + // to register interface (read) + .qs (pad_io19_mux_sel_qs) + ); + + + // R[pad_io20_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io20_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io20_cfg_chip2pad_we), + .wd (pad_io20_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io20_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io20_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io20_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io20_cfg_rx_en_we), + .wd (pad_io20_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io20_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io20_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io20_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io20_cfg_tx_en_we), + .wd (pad_io20_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io20_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io20_cfg_tx_en_qs) + ); + + + // R[pad_io20_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io20_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io20_mux_sel_we), + .wd (pad_io20_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io20_mux_sel.q ), + + // to register interface (read) + .qs (pad_io20_mux_sel_qs) + ); + + + // R[pad_io21_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io21_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io21_cfg_chip2pad_we), + .wd (pad_io21_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io21_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io21_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io21_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io21_cfg_rx_en_we), + .wd (pad_io21_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io21_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io21_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io21_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io21_cfg_tx_en_we), + .wd (pad_io21_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io21_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io21_cfg_tx_en_qs) + ); + + + // R[pad_io21_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io21_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io21_mux_sel_we), + .wd (pad_io21_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io21_mux_sel.q ), + + // to register interface (read) + .qs (pad_io21_mux_sel_qs) + ); + + + // R[pad_io22_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io22_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io22_cfg_chip2pad_we), + .wd (pad_io22_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io22_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io22_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io22_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io22_cfg_rx_en_we), + .wd (pad_io22_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io22_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io22_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io22_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io22_cfg_tx_en_we), + .wd (pad_io22_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io22_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io22_cfg_tx_en_qs) + ); + + + // R[pad_io22_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io22_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io22_mux_sel_we), + .wd (pad_io22_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io22_mux_sel.q ), + + // to register interface (read) + .qs (pad_io22_mux_sel_qs) + ); + + + // R[pad_io23_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io23_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io23_cfg_chip2pad_we), + .wd (pad_io23_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io23_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io23_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io23_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io23_cfg_rx_en_we), + .wd (pad_io23_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io23_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io23_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io23_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io23_cfg_tx_en_we), + .wd (pad_io23_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io23_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io23_cfg_tx_en_qs) + ); + + + // R[pad_io23_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io23_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io23_mux_sel_we), + .wd (pad_io23_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io23_mux_sel.q ), + + // to register interface (read) + .qs (pad_io23_mux_sel_qs) + ); + + + // R[pad_io24_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io24_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io24_cfg_chip2pad_we), + .wd (pad_io24_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io24_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io24_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io24_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io24_cfg_rx_en_we), + .wd (pad_io24_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io24_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io24_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io24_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io24_cfg_tx_en_we), + .wd (pad_io24_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io24_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io24_cfg_tx_en_qs) + ); + + + // R[pad_io24_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io24_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io24_mux_sel_we), + .wd (pad_io24_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io24_mux_sel.q ), + + // to register interface (read) + .qs (pad_io24_mux_sel_qs) + ); + + + // R[pad_io25_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io25_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io25_cfg_chip2pad_we), + .wd (pad_io25_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io25_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io25_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io25_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io25_cfg_rx_en_we), + .wd (pad_io25_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io25_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io25_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io25_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io25_cfg_tx_en_we), + .wd (pad_io25_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io25_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io25_cfg_tx_en_qs) + ); + + + // R[pad_io25_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io25_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io25_mux_sel_we), + .wd (pad_io25_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io25_mux_sel.q ), + + // to register interface (read) + .qs (pad_io25_mux_sel_qs) + ); + + + // R[pad_io26_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io26_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io26_cfg_chip2pad_we), + .wd (pad_io26_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io26_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io26_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io26_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io26_cfg_rx_en_we), + .wd (pad_io26_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io26_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io26_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io26_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io26_cfg_tx_en_we), + .wd (pad_io26_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io26_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io26_cfg_tx_en_qs) + ); + + + // R[pad_io26_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io26_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io26_mux_sel_we), + .wd (pad_io26_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io26_mux_sel.q ), + + // to register interface (read) + .qs (pad_io26_mux_sel_qs) + ); + + + // R[pad_io27_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io27_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io27_cfg_chip2pad_we), + .wd (pad_io27_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io27_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io27_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io27_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io27_cfg_rx_en_we), + .wd (pad_io27_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io27_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io27_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io27_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io27_cfg_tx_en_we), + .wd (pad_io27_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io27_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io27_cfg_tx_en_qs) + ); + + + // R[pad_io27_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io27_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io27_mux_sel_we), + .wd (pad_io27_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io27_mux_sel.q ), + + // to register interface (read) + .qs (pad_io27_mux_sel_qs) + ); + + + // R[pad_io28_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io28_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io28_cfg_chip2pad_we), + .wd (pad_io28_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io28_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io28_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io28_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io28_cfg_rx_en_we), + .wd (pad_io28_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io28_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io28_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io28_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io28_cfg_tx_en_we), + .wd (pad_io28_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io28_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io28_cfg_tx_en_qs) + ); + + + // R[pad_io28_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io28_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io28_mux_sel_we), + .wd (pad_io28_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io28_mux_sel.q ), + + // to register interface (read) + .qs (pad_io28_mux_sel_qs) + ); + + + // R[pad_io29_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io29_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io29_cfg_chip2pad_we), + .wd (pad_io29_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io29_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io29_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io29_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io29_cfg_rx_en_we), + .wd (pad_io29_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io29_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io29_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io29_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io29_cfg_tx_en_we), + .wd (pad_io29_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io29_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io29_cfg_tx_en_qs) + ); + + + // R[pad_io29_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io29_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io29_mux_sel_we), + .wd (pad_io29_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io29_mux_sel.q ), + + // to register interface (read) + .qs (pad_io29_mux_sel_qs) + ); + + + // R[pad_io30_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io30_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io30_cfg_chip2pad_we), + .wd (pad_io30_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io30_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io30_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io30_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io30_cfg_rx_en_we), + .wd (pad_io30_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io30_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io30_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io30_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io30_cfg_tx_en_we), + .wd (pad_io30_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io30_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io30_cfg_tx_en_qs) + ); + + + // R[pad_io30_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io30_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io30_mux_sel_we), + .wd (pad_io30_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io30_mux_sel.q ), + + // to register interface (read) + .qs (pad_io30_mux_sel_qs) + ); + + + // R[pad_io31_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io31_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io31_cfg_chip2pad_we), + .wd (pad_io31_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io31_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io31_cfg_chip2pad_qs) + ); + + + // F[rx_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io31_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io31_cfg_rx_en_we), + .wd (pad_io31_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io31_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io31_cfg_rx_en_qs) + ); + + + // F[tx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io31_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io31_cfg_tx_en_we), + .wd (pad_io31_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io31_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io31_cfg_tx_en_qs) + ); + + + // R[pad_io31_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io31_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io31_mux_sel_we), + .wd (pad_io31_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io31_mux_sel.q ), + + // to register interface (read) + .qs (pad_io31_mux_sel_qs) + ); + + + + + logic [64:0] addr_hit; + always_comb begin + addr_hit = '0; + addr_hit[ 0] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_OFFSET); + addr_hit[ 1] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_OFFSET); + addr_hit[ 2] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_OFFSET); + addr_hit[ 3] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_CFG_OFFSET); + addr_hit[ 4] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_OFFSET); + addr_hit[ 5] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_CFG_OFFSET); + addr_hit[ 6] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_OFFSET); + addr_hit[ 7] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_CFG_OFFSET); + addr_hit[ 8] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_OFFSET); + addr_hit[ 9] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_CFG_OFFSET); + addr_hit[10] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_OFFSET); + addr_hit[11] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_CFG_OFFSET); + addr_hit[12] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_OFFSET); + addr_hit[13] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_CFG_OFFSET); + addr_hit[14] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_OFFSET); + addr_hit[15] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_CFG_OFFSET); + addr_hit[16] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_OFFSET); + addr_hit[17] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_CFG_OFFSET); + addr_hit[18] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_OFFSET); + addr_hit[19] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_CFG_OFFSET); + addr_hit[20] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_OFFSET); + addr_hit[21] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_CFG_OFFSET); + addr_hit[22] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_OFFSET); + addr_hit[23] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_CFG_OFFSET); + addr_hit[24] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_OFFSET); + addr_hit[25] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_CFG_OFFSET); + addr_hit[26] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_OFFSET); + addr_hit[27] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_CFG_OFFSET); + addr_hit[28] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_OFFSET); + addr_hit[29] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_CFG_OFFSET); + addr_hit[30] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_OFFSET); + addr_hit[31] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_CFG_OFFSET); + addr_hit[32] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_OFFSET); + addr_hit[33] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_CFG_OFFSET); + addr_hit[34] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_OFFSET); + addr_hit[35] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_CFG_OFFSET); + addr_hit[36] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_OFFSET); + addr_hit[37] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_CFG_OFFSET); + addr_hit[38] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_OFFSET); + addr_hit[39] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_CFG_OFFSET); + addr_hit[40] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_OFFSET); + addr_hit[41] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_CFG_OFFSET); + addr_hit[42] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_OFFSET); + addr_hit[43] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_CFG_OFFSET); + addr_hit[44] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_OFFSET); + addr_hit[45] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_CFG_OFFSET); + addr_hit[46] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_OFFSET); + addr_hit[47] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_CFG_OFFSET); + addr_hit[48] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_OFFSET); + addr_hit[49] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_CFG_OFFSET); + addr_hit[50] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_OFFSET); + addr_hit[51] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_CFG_OFFSET); + addr_hit[52] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_OFFSET); + addr_hit[53] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_CFG_OFFSET); + addr_hit[54] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_OFFSET); + addr_hit[55] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_CFG_OFFSET); + addr_hit[56] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_OFFSET); + addr_hit[57] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_CFG_OFFSET); + addr_hit[58] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_OFFSET); + addr_hit[59] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_CFG_OFFSET); + addr_hit[60] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_OFFSET); + addr_hit[61] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_CFG_OFFSET); + addr_hit[62] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_OFFSET); + addr_hit[63] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_CFG_OFFSET); + addr_hit[64] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[ 9] & ~reg_be))) | + (addr_hit[10] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[10] & ~reg_be))) | + (addr_hit[11] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[11] & ~reg_be))) | + (addr_hit[12] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[12] & ~reg_be))) | + (addr_hit[13] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[13] & ~reg_be))) | + (addr_hit[14] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[14] & ~reg_be))) | + (addr_hit[15] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[15] & ~reg_be))) | + (addr_hit[16] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[16] & ~reg_be))) | + (addr_hit[17] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[17] & ~reg_be))) | + (addr_hit[18] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[18] & ~reg_be))) | + (addr_hit[19] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[19] & ~reg_be))) | + (addr_hit[20] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[20] & ~reg_be))) | + (addr_hit[21] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[21] & ~reg_be))) | + (addr_hit[22] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[22] & ~reg_be))) | + (addr_hit[23] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[23] & ~reg_be))) | + (addr_hit[24] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[24] & ~reg_be))) | + (addr_hit[25] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[25] & ~reg_be))) | + (addr_hit[26] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[26] & ~reg_be))) | + (addr_hit[27] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[27] & ~reg_be))) | + (addr_hit[28] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[28] & ~reg_be))) | + (addr_hit[29] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[29] & ~reg_be))) | + (addr_hit[30] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[30] & ~reg_be))) | + (addr_hit[31] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[31] & ~reg_be))) | + (addr_hit[32] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[32] & ~reg_be))) | + (addr_hit[33] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[33] & ~reg_be))) | + (addr_hit[34] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[34] & ~reg_be))) | + (addr_hit[35] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[35] & ~reg_be))) | + (addr_hit[36] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[36] & ~reg_be))) | + (addr_hit[37] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[37] & ~reg_be))) | + (addr_hit[38] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[38] & ~reg_be))) | + (addr_hit[39] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[39] & ~reg_be))) | + (addr_hit[40] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[40] & ~reg_be))) | + (addr_hit[41] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[41] & ~reg_be))) | + (addr_hit[42] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[42] & ~reg_be))) | + (addr_hit[43] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[43] & ~reg_be))) | + (addr_hit[44] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[44] & ~reg_be))) | + (addr_hit[45] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[45] & ~reg_be))) | + (addr_hit[46] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[46] & ~reg_be))) | + (addr_hit[47] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[47] & ~reg_be))) | + (addr_hit[48] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[48] & ~reg_be))) | + (addr_hit[49] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[49] & ~reg_be))) | + (addr_hit[50] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[50] & ~reg_be))) | + (addr_hit[51] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[51] & ~reg_be))) | + (addr_hit[52] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[52] & ~reg_be))) | + (addr_hit[53] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[53] & ~reg_be))) | + (addr_hit[54] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[54] & ~reg_be))) | + (addr_hit[55] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[55] & ~reg_be))) | + (addr_hit[56] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[56] & ~reg_be))) | + (addr_hit[57] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[57] & ~reg_be))) | + (addr_hit[58] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[58] & ~reg_be))) | + (addr_hit[59] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[59] & ~reg_be))) | + (addr_hit[60] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[60] & ~reg_be))) | + (addr_hit[61] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[61] & ~reg_be))) | + (addr_hit[62] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[62] & ~reg_be))) | + (addr_hit[63] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[63] & ~reg_be))) | + (addr_hit[64] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[64] & ~reg_be))))); + end + + assign pad_io00_cfg_chip2pad_we = addr_hit[1] & reg_we & !reg_error; + assign pad_io00_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io00_cfg_rx_en_we = addr_hit[1] & reg_we & !reg_error; + assign pad_io00_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io00_cfg_tx_en_we = addr_hit[1] & reg_we & !reg_error; + assign pad_io00_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io00_mux_sel_we = addr_hit[2] & reg_we & !reg_error; + assign pad_io00_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io01_cfg_chip2pad_we = addr_hit[3] & reg_we & !reg_error; + assign pad_io01_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io01_cfg_rx_en_we = addr_hit[3] & reg_we & !reg_error; + assign pad_io01_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io01_cfg_tx_en_we = addr_hit[3] & reg_we & !reg_error; + assign pad_io01_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io01_mux_sel_we = addr_hit[4] & reg_we & !reg_error; + assign pad_io01_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io02_cfg_chip2pad_we = addr_hit[5] & reg_we & !reg_error; + assign pad_io02_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io02_cfg_rx_en_we = addr_hit[5] & reg_we & !reg_error; + assign pad_io02_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io02_cfg_tx_en_we = addr_hit[5] & reg_we & !reg_error; + assign pad_io02_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io02_mux_sel_we = addr_hit[6] & reg_we & !reg_error; + assign pad_io02_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io03_cfg_chip2pad_we = addr_hit[7] & reg_we & !reg_error; + assign pad_io03_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io03_cfg_rx_en_we = addr_hit[7] & reg_we & !reg_error; + assign pad_io03_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io03_cfg_tx_en_we = addr_hit[7] & reg_we & !reg_error; + assign pad_io03_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io03_mux_sel_we = addr_hit[8] & reg_we & !reg_error; + assign pad_io03_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io04_cfg_chip2pad_we = addr_hit[9] & reg_we & !reg_error; + assign pad_io04_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io04_cfg_rx_en_we = addr_hit[9] & reg_we & !reg_error; + assign pad_io04_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io04_cfg_tx_en_we = addr_hit[9] & reg_we & !reg_error; + assign pad_io04_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io04_mux_sel_we = addr_hit[10] & reg_we & !reg_error; + assign pad_io04_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io05_cfg_chip2pad_we = addr_hit[11] & reg_we & !reg_error; + assign pad_io05_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io05_cfg_rx_en_we = addr_hit[11] & reg_we & !reg_error; + assign pad_io05_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io05_cfg_tx_en_we = addr_hit[11] & reg_we & !reg_error; + assign pad_io05_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io05_mux_sel_we = addr_hit[12] & reg_we & !reg_error; + assign pad_io05_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io06_cfg_chip2pad_we = addr_hit[13] & reg_we & !reg_error; + assign pad_io06_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io06_cfg_rx_en_we = addr_hit[13] & reg_we & !reg_error; + assign pad_io06_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io06_cfg_tx_en_we = addr_hit[13] & reg_we & !reg_error; + assign pad_io06_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io06_mux_sel_we = addr_hit[14] & reg_we & !reg_error; + assign pad_io06_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io07_cfg_chip2pad_we = addr_hit[15] & reg_we & !reg_error; + assign pad_io07_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io07_cfg_rx_en_we = addr_hit[15] & reg_we & !reg_error; + assign pad_io07_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io07_cfg_tx_en_we = addr_hit[15] & reg_we & !reg_error; + assign pad_io07_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io07_mux_sel_we = addr_hit[16] & reg_we & !reg_error; + assign pad_io07_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io08_cfg_chip2pad_we = addr_hit[17] & reg_we & !reg_error; + assign pad_io08_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io08_cfg_rx_en_we = addr_hit[17] & reg_we & !reg_error; + assign pad_io08_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io08_cfg_tx_en_we = addr_hit[17] & reg_we & !reg_error; + assign pad_io08_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io08_mux_sel_we = addr_hit[18] & reg_we & !reg_error; + assign pad_io08_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io09_cfg_chip2pad_we = addr_hit[19] & reg_we & !reg_error; + assign pad_io09_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io09_cfg_rx_en_we = addr_hit[19] & reg_we & !reg_error; + assign pad_io09_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io09_cfg_tx_en_we = addr_hit[19] & reg_we & !reg_error; + assign pad_io09_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io09_mux_sel_we = addr_hit[20] & reg_we & !reg_error; + assign pad_io09_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io10_cfg_chip2pad_we = addr_hit[21] & reg_we & !reg_error; + assign pad_io10_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io10_cfg_rx_en_we = addr_hit[21] & reg_we & !reg_error; + assign pad_io10_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io10_cfg_tx_en_we = addr_hit[21] & reg_we & !reg_error; + assign pad_io10_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io10_mux_sel_we = addr_hit[22] & reg_we & !reg_error; + assign pad_io10_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io11_cfg_chip2pad_we = addr_hit[23] & reg_we & !reg_error; + assign pad_io11_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io11_cfg_rx_en_we = addr_hit[23] & reg_we & !reg_error; + assign pad_io11_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io11_cfg_tx_en_we = addr_hit[23] & reg_we & !reg_error; + assign pad_io11_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io11_mux_sel_we = addr_hit[24] & reg_we & !reg_error; + assign pad_io11_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io12_cfg_chip2pad_we = addr_hit[25] & reg_we & !reg_error; + assign pad_io12_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io12_cfg_rx_en_we = addr_hit[25] & reg_we & !reg_error; + assign pad_io12_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io12_cfg_tx_en_we = addr_hit[25] & reg_we & !reg_error; + assign pad_io12_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io12_mux_sel_we = addr_hit[26] & reg_we & !reg_error; + assign pad_io12_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io13_cfg_chip2pad_we = addr_hit[27] & reg_we & !reg_error; + assign pad_io13_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io13_cfg_rx_en_we = addr_hit[27] & reg_we & !reg_error; + assign pad_io13_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io13_cfg_tx_en_we = addr_hit[27] & reg_we & !reg_error; + assign pad_io13_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io13_mux_sel_we = addr_hit[28] & reg_we & !reg_error; + assign pad_io13_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io14_cfg_chip2pad_we = addr_hit[29] & reg_we & !reg_error; + assign pad_io14_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io14_cfg_rx_en_we = addr_hit[29] & reg_we & !reg_error; + assign pad_io14_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io14_cfg_tx_en_we = addr_hit[29] & reg_we & !reg_error; + assign pad_io14_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io14_mux_sel_we = addr_hit[30] & reg_we & !reg_error; + assign pad_io14_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io15_cfg_chip2pad_we = addr_hit[31] & reg_we & !reg_error; + assign pad_io15_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io15_cfg_rx_en_we = addr_hit[31] & reg_we & !reg_error; + assign pad_io15_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io15_cfg_tx_en_we = addr_hit[31] & reg_we & !reg_error; + assign pad_io15_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io15_mux_sel_we = addr_hit[32] & reg_we & !reg_error; + assign pad_io15_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io16_cfg_chip2pad_we = addr_hit[33] & reg_we & !reg_error; + assign pad_io16_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io16_cfg_rx_en_we = addr_hit[33] & reg_we & !reg_error; + assign pad_io16_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io16_cfg_tx_en_we = addr_hit[33] & reg_we & !reg_error; + assign pad_io16_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io16_mux_sel_we = addr_hit[34] & reg_we & !reg_error; + assign pad_io16_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io17_cfg_chip2pad_we = addr_hit[35] & reg_we & !reg_error; + assign pad_io17_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io17_cfg_rx_en_we = addr_hit[35] & reg_we & !reg_error; + assign pad_io17_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io17_cfg_tx_en_we = addr_hit[35] & reg_we & !reg_error; + assign pad_io17_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io17_mux_sel_we = addr_hit[36] & reg_we & !reg_error; + assign pad_io17_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io18_cfg_chip2pad_we = addr_hit[37] & reg_we & !reg_error; + assign pad_io18_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io18_cfg_rx_en_we = addr_hit[37] & reg_we & !reg_error; + assign pad_io18_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io18_cfg_tx_en_we = addr_hit[37] & reg_we & !reg_error; + assign pad_io18_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io18_mux_sel_we = addr_hit[38] & reg_we & !reg_error; + assign pad_io18_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io19_cfg_chip2pad_we = addr_hit[39] & reg_we & !reg_error; + assign pad_io19_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io19_cfg_rx_en_we = addr_hit[39] & reg_we & !reg_error; + assign pad_io19_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io19_cfg_tx_en_we = addr_hit[39] & reg_we & !reg_error; + assign pad_io19_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io19_mux_sel_we = addr_hit[40] & reg_we & !reg_error; + assign pad_io19_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io20_cfg_chip2pad_we = addr_hit[41] & reg_we & !reg_error; + assign pad_io20_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io20_cfg_rx_en_we = addr_hit[41] & reg_we & !reg_error; + assign pad_io20_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io20_cfg_tx_en_we = addr_hit[41] & reg_we & !reg_error; + assign pad_io20_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io20_mux_sel_we = addr_hit[42] & reg_we & !reg_error; + assign pad_io20_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io21_cfg_chip2pad_we = addr_hit[43] & reg_we & !reg_error; + assign pad_io21_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io21_cfg_rx_en_we = addr_hit[43] & reg_we & !reg_error; + assign pad_io21_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io21_cfg_tx_en_we = addr_hit[43] & reg_we & !reg_error; + assign pad_io21_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io21_mux_sel_we = addr_hit[44] & reg_we & !reg_error; + assign pad_io21_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io22_cfg_chip2pad_we = addr_hit[45] & reg_we & !reg_error; + assign pad_io22_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io22_cfg_rx_en_we = addr_hit[45] & reg_we & !reg_error; + assign pad_io22_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io22_cfg_tx_en_we = addr_hit[45] & reg_we & !reg_error; + assign pad_io22_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io22_mux_sel_we = addr_hit[46] & reg_we & !reg_error; + assign pad_io22_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io23_cfg_chip2pad_we = addr_hit[47] & reg_we & !reg_error; + assign pad_io23_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io23_cfg_rx_en_we = addr_hit[47] & reg_we & !reg_error; + assign pad_io23_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io23_cfg_tx_en_we = addr_hit[47] & reg_we & !reg_error; + assign pad_io23_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io23_mux_sel_we = addr_hit[48] & reg_we & !reg_error; + assign pad_io23_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io24_cfg_chip2pad_we = addr_hit[49] & reg_we & !reg_error; + assign pad_io24_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io24_cfg_rx_en_we = addr_hit[49] & reg_we & !reg_error; + assign pad_io24_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io24_cfg_tx_en_we = addr_hit[49] & reg_we & !reg_error; + assign pad_io24_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io24_mux_sel_we = addr_hit[50] & reg_we & !reg_error; + assign pad_io24_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io25_cfg_chip2pad_we = addr_hit[51] & reg_we & !reg_error; + assign pad_io25_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io25_cfg_rx_en_we = addr_hit[51] & reg_we & !reg_error; + assign pad_io25_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io25_cfg_tx_en_we = addr_hit[51] & reg_we & !reg_error; + assign pad_io25_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io25_mux_sel_we = addr_hit[52] & reg_we & !reg_error; + assign pad_io25_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io26_cfg_chip2pad_we = addr_hit[53] & reg_we & !reg_error; + assign pad_io26_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io26_cfg_rx_en_we = addr_hit[53] & reg_we & !reg_error; + assign pad_io26_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io26_cfg_tx_en_we = addr_hit[53] & reg_we & !reg_error; + assign pad_io26_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io26_mux_sel_we = addr_hit[54] & reg_we & !reg_error; + assign pad_io26_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io27_cfg_chip2pad_we = addr_hit[55] & reg_we & !reg_error; + assign pad_io27_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io27_cfg_rx_en_we = addr_hit[55] & reg_we & !reg_error; + assign pad_io27_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io27_cfg_tx_en_we = addr_hit[55] & reg_we & !reg_error; + assign pad_io27_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io27_mux_sel_we = addr_hit[56] & reg_we & !reg_error; + assign pad_io27_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io28_cfg_chip2pad_we = addr_hit[57] & reg_we & !reg_error; + assign pad_io28_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io28_cfg_rx_en_we = addr_hit[57] & reg_we & !reg_error; + assign pad_io28_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io28_cfg_tx_en_we = addr_hit[57] & reg_we & !reg_error; + assign pad_io28_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io28_mux_sel_we = addr_hit[58] & reg_we & !reg_error; + assign pad_io28_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io29_cfg_chip2pad_we = addr_hit[59] & reg_we & !reg_error; + assign pad_io29_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io29_cfg_rx_en_we = addr_hit[59] & reg_we & !reg_error; + assign pad_io29_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io29_cfg_tx_en_we = addr_hit[59] & reg_we & !reg_error; + assign pad_io29_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io29_mux_sel_we = addr_hit[60] & reg_we & !reg_error; + assign pad_io29_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io30_cfg_chip2pad_we = addr_hit[61] & reg_we & !reg_error; + assign pad_io30_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io30_cfg_rx_en_we = addr_hit[61] & reg_we & !reg_error; + assign pad_io30_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io30_cfg_tx_en_we = addr_hit[61] & reg_we & !reg_error; + assign pad_io30_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io30_mux_sel_we = addr_hit[62] & reg_we & !reg_error; + assign pad_io30_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io31_cfg_chip2pad_we = addr_hit[63] & reg_we & !reg_error; + assign pad_io31_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io31_cfg_rx_en_we = addr_hit[63] & reg_we & !reg_error; + assign pad_io31_cfg_rx_en_wd = reg_wdata[1]; + + assign pad_io31_cfg_tx_en_we = addr_hit[63] & reg_we & !reg_error; + assign pad_io31_cfg_tx_en_wd = reg_wdata[2]; + + assign pad_io31_mux_sel_we = addr_hit[64] & reg_we & !reg_error; + assign pad_io31_mux_sel_wd = reg_wdata[5:0]; + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[15:0] = info_hw_version_qs; + reg_rdata_next[31:16] = info_padcount_qs; + end + + addr_hit[1]: begin + reg_rdata_next[0] = pad_io00_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io00_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io00_cfg_tx_en_qs; + end + + addr_hit[2]: begin + reg_rdata_next[5:0] = pad_io00_mux_sel_qs; + end + + addr_hit[3]: begin + reg_rdata_next[0] = pad_io01_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io01_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io01_cfg_tx_en_qs; + end + + addr_hit[4]: begin + reg_rdata_next[5:0] = pad_io01_mux_sel_qs; + end + + addr_hit[5]: begin + reg_rdata_next[0] = pad_io02_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io02_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io02_cfg_tx_en_qs; + end + + addr_hit[6]: begin + reg_rdata_next[5:0] = pad_io02_mux_sel_qs; + end + + addr_hit[7]: begin + reg_rdata_next[0] = pad_io03_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io03_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io03_cfg_tx_en_qs; + end + + addr_hit[8]: begin + reg_rdata_next[5:0] = pad_io03_mux_sel_qs; + end + + addr_hit[9]: begin + reg_rdata_next[0] = pad_io04_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io04_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io04_cfg_tx_en_qs; + end + + addr_hit[10]: begin + reg_rdata_next[5:0] = pad_io04_mux_sel_qs; + end + + addr_hit[11]: begin + reg_rdata_next[0] = pad_io05_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io05_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io05_cfg_tx_en_qs; + end + + addr_hit[12]: begin + reg_rdata_next[5:0] = pad_io05_mux_sel_qs; + end + + addr_hit[13]: begin + reg_rdata_next[0] = pad_io06_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io06_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io06_cfg_tx_en_qs; + end + + addr_hit[14]: begin + reg_rdata_next[5:0] = pad_io06_mux_sel_qs; + end + + addr_hit[15]: begin + reg_rdata_next[0] = pad_io07_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io07_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io07_cfg_tx_en_qs; + end + + addr_hit[16]: begin + reg_rdata_next[5:0] = pad_io07_mux_sel_qs; + end + + addr_hit[17]: begin + reg_rdata_next[0] = pad_io08_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io08_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io08_cfg_tx_en_qs; + end + + addr_hit[18]: begin + reg_rdata_next[5:0] = pad_io08_mux_sel_qs; + end + + addr_hit[19]: begin + reg_rdata_next[0] = pad_io09_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io09_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io09_cfg_tx_en_qs; + end + + addr_hit[20]: begin + reg_rdata_next[5:0] = pad_io09_mux_sel_qs; + end + + addr_hit[21]: begin + reg_rdata_next[0] = pad_io10_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io10_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io10_cfg_tx_en_qs; + end + + addr_hit[22]: begin + reg_rdata_next[5:0] = pad_io10_mux_sel_qs; + end + + addr_hit[23]: begin + reg_rdata_next[0] = pad_io11_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io11_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io11_cfg_tx_en_qs; + end + + addr_hit[24]: begin + reg_rdata_next[5:0] = pad_io11_mux_sel_qs; + end + + addr_hit[25]: begin + reg_rdata_next[0] = pad_io12_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io12_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io12_cfg_tx_en_qs; + end + + addr_hit[26]: begin + reg_rdata_next[5:0] = pad_io12_mux_sel_qs; + end + + addr_hit[27]: begin + reg_rdata_next[0] = pad_io13_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io13_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io13_cfg_tx_en_qs; + end + + addr_hit[28]: begin + reg_rdata_next[5:0] = pad_io13_mux_sel_qs; + end + + addr_hit[29]: begin + reg_rdata_next[0] = pad_io14_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io14_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io14_cfg_tx_en_qs; + end + + addr_hit[30]: begin + reg_rdata_next[5:0] = pad_io14_mux_sel_qs; + end + + addr_hit[31]: begin + reg_rdata_next[0] = pad_io15_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io15_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io15_cfg_tx_en_qs; + end + + addr_hit[32]: begin + reg_rdata_next[5:0] = pad_io15_mux_sel_qs; + end + + addr_hit[33]: begin + reg_rdata_next[0] = pad_io16_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io16_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io16_cfg_tx_en_qs; + end + + addr_hit[34]: begin + reg_rdata_next[5:0] = pad_io16_mux_sel_qs; + end + + addr_hit[35]: begin + reg_rdata_next[0] = pad_io17_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io17_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io17_cfg_tx_en_qs; + end + + addr_hit[36]: begin + reg_rdata_next[5:0] = pad_io17_mux_sel_qs; + end + + addr_hit[37]: begin + reg_rdata_next[0] = pad_io18_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io18_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io18_cfg_tx_en_qs; + end + + addr_hit[38]: begin + reg_rdata_next[5:0] = pad_io18_mux_sel_qs; + end + + addr_hit[39]: begin + reg_rdata_next[0] = pad_io19_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io19_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io19_cfg_tx_en_qs; + end + + addr_hit[40]: begin + reg_rdata_next[5:0] = pad_io19_mux_sel_qs; + end + + addr_hit[41]: begin + reg_rdata_next[0] = pad_io20_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io20_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io20_cfg_tx_en_qs; + end + + addr_hit[42]: begin + reg_rdata_next[5:0] = pad_io20_mux_sel_qs; + end + + addr_hit[43]: begin + reg_rdata_next[0] = pad_io21_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io21_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io21_cfg_tx_en_qs; + end + + addr_hit[44]: begin + reg_rdata_next[5:0] = pad_io21_mux_sel_qs; + end + + addr_hit[45]: begin + reg_rdata_next[0] = pad_io22_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io22_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io22_cfg_tx_en_qs; + end + + addr_hit[46]: begin + reg_rdata_next[5:0] = pad_io22_mux_sel_qs; + end + + addr_hit[47]: begin + reg_rdata_next[0] = pad_io23_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io23_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io23_cfg_tx_en_qs; + end + + addr_hit[48]: begin + reg_rdata_next[5:0] = pad_io23_mux_sel_qs; + end + + addr_hit[49]: begin + reg_rdata_next[0] = pad_io24_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io24_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io24_cfg_tx_en_qs; + end + + addr_hit[50]: begin + reg_rdata_next[5:0] = pad_io24_mux_sel_qs; + end + + addr_hit[51]: begin + reg_rdata_next[0] = pad_io25_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io25_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io25_cfg_tx_en_qs; + end + + addr_hit[52]: begin + reg_rdata_next[5:0] = pad_io25_mux_sel_qs; + end + + addr_hit[53]: begin + reg_rdata_next[0] = pad_io26_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io26_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io26_cfg_tx_en_qs; + end + + addr_hit[54]: begin + reg_rdata_next[5:0] = pad_io26_mux_sel_qs; + end + + addr_hit[55]: begin + reg_rdata_next[0] = pad_io27_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io27_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io27_cfg_tx_en_qs; + end + + addr_hit[56]: begin + reg_rdata_next[5:0] = pad_io27_mux_sel_qs; + end + + addr_hit[57]: begin + reg_rdata_next[0] = pad_io28_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io28_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io28_cfg_tx_en_qs; + end + + addr_hit[58]: begin + reg_rdata_next[5:0] = pad_io28_mux_sel_qs; + end + + addr_hit[59]: begin + reg_rdata_next[0] = pad_io29_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io29_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io29_cfg_tx_en_qs; + end + + addr_hit[60]: begin + reg_rdata_next[5:0] = pad_io29_mux_sel_qs; + end + + addr_hit[61]: begin + reg_rdata_next[0] = pad_io30_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io30_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io30_cfg_tx_en_qs; + end + + addr_hit[62]: begin + reg_rdata_next[5:0] = pad_io30_mux_sel_qs; + end + + addr_hit[63]: begin + reg_rdata_next[0] = pad_io31_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io31_cfg_rx_en_qs; + reg_rdata_next[2] = pad_io31_cfg_tx_en_qs; + end + + addr_hit[64]: begin + reg_rdata_next[5:0] = pad_io31_mux_sel_qs; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit)) + +endmodule diff --git a/hw/padframe/pulpissimo_padframe_fpga_autogen/src/pulpissimo_padframe_all_pads_muxer.sv b/hw/padframe/pulpissimo_padframe_fpga_autogen/src/pulpissimo_padframe_all_pads_muxer.sv new file mode 100644 index 00000000..3c25b47a --- /dev/null +++ b/hw/padframe/pulpissimo_padframe_fpga_autogen/src/pulpissimo_padframe_all_pads_muxer.sv @@ -0,0 +1,15549 @@ + +// File auto-generated by Padrick unknown +module pulpissimo_padframe_all_pads_muxer + import pkg_internal_pulpissimo_padframe_all_pads::*; + import pkg_pulpissimo_padframe::*; + import pulpissimo_padframe_all_pads_config_reg_pkg::*; +#( + parameter type req_t = logic, // reg_interface request type + parameter type resp_t = logic // reg_interface response type +) ( + input logic clk_i, + input logic rst_ni, + input pad_domain_all_pads_ports_soc2pad_t port_signals_soc2pad_i, + output pad_domain_all_pads_ports_pad2soc_t port_signals_pad2soc_o, + output mux_to_pads_t mux_to_pads_o, + input pads_to_mux_t pads_to_mux_i, + // Configuration interface using register_interface protocol + input req_t config_req_i, + output resp_t config_rsp_o +); + // Connections between register file and pads + pulpissimo_padframe_all_pads_config_reg2hw_t s_reg2hw; + + // Register File Instantiation + pulpissimo_padframe_all_pads_config_reg_top #( + .reg_req_t(req_t), + .reg_rsp_t(resp_t) + ) i_regfile ( + .clk_i, + .rst_ni, + .reg2hw(s_reg2hw), + .reg_req_i(config_req_i), + .reg_rsp_o(config_rsp_o), + .devmode_i(1'b1) + ); + + + // SoC -> Pad Multiplex Logic + // Pad pad_io00 + always_comb begin + unique case (s_reg2hw.pad_io00_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_DEFAULT: begin + mux_to_pads_o.pad_io00.chip2pad = s_reg2hw.pad_io00_cfg.chip2pad.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_GPIO_GPIO00: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.gpio.gpio00_out; + mux_to_pads_o.pad_io00.rx_en = ~port_signals_soc2pad_i.gpio.gpio00_tx_en; + mux_to_pads_o.pad_io00.tx_en = port_signals_soc2pad_i.gpio.gpio00_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io00.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io00.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io00.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io00.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_UART0_RX: begin + mux_to_pads_o.pad_io00.chip2pad = 1'b1; + mux_to_pads_o.pad_io00.rx_en = 1'b1; + mux_to_pads_o.pad_io00.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_UART0_TX: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io00.rx_en = 1'b0; + mux_to_pads_o.pad_io00.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io00.rx_en = 1'b0; + mux_to_pads_o.pad_io00.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io00.rx_en = 1'b0; + mux_to_pads_o.pad_io00.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io00.rx_en = 1'b0; + mux_to_pads_o.pad_io00.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io00.rx_en = 1'b0; + mux_to_pads_o.pad_io00.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io00.rx_en = 1'b0; + mux_to_pads_o.pad_io00.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io00.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io00.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io00.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io00.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io00.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io00.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io00.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io00.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io00.chip2pad = 1'b0; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io00.chip2pad = 1'b0; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io00.chip2pad = 1'b0; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io00.chip2pad = 1'b0; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io00.chip2pad = 1'b0; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io00.chip2pad = 1'b0; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io00.chip2pad = 1'b0; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io00.chip2pad = 1'b0; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io00.chip2pad = 1'b0; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io00.chip2pad = 1'b0; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io00.chip2pad = 1'b0; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io00.chip2pad = 1'b0; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io00.chip2pad = 1'b0; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io00.rx_en = 1'b0; + mux_to_pads_o.pad_io00.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io00.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io00.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io00.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io00.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io00.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io00.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io00.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io00.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io00.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io00.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io00.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io00.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io00.rx_en = 1'b0; + mux_to_pads_o.pad_io00.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io00.rx_en = 1'b0; + mux_to_pads_o.pad_io00.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io00.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io00.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io00.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io00.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io00.chip2pad = s_reg2hw.pad_io00_cfg.chip2pad.q; + mux_to_pads_o.pad_io00.rx_en = 1'b1; + mux_to_pads_o.pad_io00.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io00.chip2pad = s_reg2hw.pad_io00_cfg.chip2pad.q; + mux_to_pads_o.pad_io00.rx_en = 1'b1; + mux_to_pads_o.pad_io00.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io00.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io00.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io00.chip2pad = s_reg2hw.pad_io00_cfg.chip2pad.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io01 + always_comb begin + unique case (s_reg2hw.pad_io01_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_DEFAULT: begin + mux_to_pads_o.pad_io01.chip2pad = s_reg2hw.pad_io01_cfg.chip2pad.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_GPIO_GPIO01: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.gpio.gpio01_out; + mux_to_pads_o.pad_io01.rx_en = ~port_signals_soc2pad_i.gpio.gpio01_tx_en; + mux_to_pads_o.pad_io01.tx_en = port_signals_soc2pad_i.gpio.gpio01_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io01.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io01.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io01.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io01.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_UART0_RX: begin + mux_to_pads_o.pad_io01.chip2pad = 1'b1; + mux_to_pads_o.pad_io01.rx_en = 1'b1; + mux_to_pads_o.pad_io01.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_UART0_TX: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io01.rx_en = 1'b0; + mux_to_pads_o.pad_io01.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io01.rx_en = 1'b0; + mux_to_pads_o.pad_io01.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io01.rx_en = 1'b0; + mux_to_pads_o.pad_io01.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io01.rx_en = 1'b0; + mux_to_pads_o.pad_io01.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io01.rx_en = 1'b0; + mux_to_pads_o.pad_io01.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io01.rx_en = 1'b0; + mux_to_pads_o.pad_io01.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io01.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io01.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io01.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io01.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io01.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io01.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io01.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io01.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io01.chip2pad = 1'b0; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io01.chip2pad = 1'b0; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io01.chip2pad = 1'b0; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io01.chip2pad = 1'b0; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io01.chip2pad = 1'b0; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io01.chip2pad = 1'b0; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io01.chip2pad = 1'b0; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io01.chip2pad = 1'b0; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io01.chip2pad = 1'b0; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io01.chip2pad = 1'b0; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io01.chip2pad = 1'b0; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io01.chip2pad = 1'b0; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io01.chip2pad = 1'b0; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io01.rx_en = 1'b0; + mux_to_pads_o.pad_io01.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io01.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io01.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io01.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io01.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io01.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io01.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io01.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io01.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io01.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io01.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io01.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io01.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io01.rx_en = 1'b0; + mux_to_pads_o.pad_io01.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io01.rx_en = 1'b0; + mux_to_pads_o.pad_io01.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io01.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io01.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io01.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io01.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io01.chip2pad = s_reg2hw.pad_io01_cfg.chip2pad.q; + mux_to_pads_o.pad_io01.rx_en = 1'b1; + mux_to_pads_o.pad_io01.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io01.chip2pad = s_reg2hw.pad_io01_cfg.chip2pad.q; + mux_to_pads_o.pad_io01.rx_en = 1'b1; + mux_to_pads_o.pad_io01.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io01.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io01.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io01.chip2pad = s_reg2hw.pad_io01_cfg.chip2pad.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io02 + always_comb begin + unique case (s_reg2hw.pad_io02_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_DEFAULT: begin + mux_to_pads_o.pad_io02.chip2pad = s_reg2hw.pad_io02_cfg.chip2pad.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_GPIO_GPIO02: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.gpio.gpio02_out; + mux_to_pads_o.pad_io02.rx_en = ~port_signals_soc2pad_i.gpio.gpio02_tx_en; + mux_to_pads_o.pad_io02.tx_en = port_signals_soc2pad_i.gpio.gpio02_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io02.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io02.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io02.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io02.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_UART0_RX: begin + mux_to_pads_o.pad_io02.chip2pad = 1'b1; + mux_to_pads_o.pad_io02.rx_en = 1'b1; + mux_to_pads_o.pad_io02.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_UART0_TX: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io02.rx_en = 1'b0; + mux_to_pads_o.pad_io02.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io02.rx_en = 1'b0; + mux_to_pads_o.pad_io02.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io02.rx_en = 1'b0; + mux_to_pads_o.pad_io02.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io02.rx_en = 1'b0; + mux_to_pads_o.pad_io02.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io02.rx_en = 1'b0; + mux_to_pads_o.pad_io02.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io02.rx_en = 1'b0; + mux_to_pads_o.pad_io02.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io02.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io02.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io02.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io02.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io02.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io02.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io02.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io02.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io02.chip2pad = 1'b0; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io02.chip2pad = 1'b0; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io02.chip2pad = 1'b0; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io02.chip2pad = 1'b0; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io02.chip2pad = 1'b0; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io02.chip2pad = 1'b0; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io02.chip2pad = 1'b0; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io02.chip2pad = 1'b0; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io02.chip2pad = 1'b0; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io02.chip2pad = 1'b0; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io02.chip2pad = 1'b0; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io02.chip2pad = 1'b0; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io02.chip2pad = 1'b0; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io02.rx_en = 1'b0; + mux_to_pads_o.pad_io02.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io02.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io02.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io02.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io02.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io02.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io02.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io02.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io02.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io02.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io02.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io02.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io02.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io02.rx_en = 1'b0; + mux_to_pads_o.pad_io02.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io02.rx_en = 1'b0; + mux_to_pads_o.pad_io02.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io02.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io02.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io02.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io02.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io02.chip2pad = s_reg2hw.pad_io02_cfg.chip2pad.q; + mux_to_pads_o.pad_io02.rx_en = 1'b1; + mux_to_pads_o.pad_io02.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io02.chip2pad = s_reg2hw.pad_io02_cfg.chip2pad.q; + mux_to_pads_o.pad_io02.rx_en = 1'b1; + mux_to_pads_o.pad_io02.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io02.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io02.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io02.chip2pad = s_reg2hw.pad_io02_cfg.chip2pad.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io03 + always_comb begin + unique case (s_reg2hw.pad_io03_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_DEFAULT: begin + mux_to_pads_o.pad_io03.chip2pad = s_reg2hw.pad_io03_cfg.chip2pad.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_GPIO_GPIO03: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.gpio.gpio03_out; + mux_to_pads_o.pad_io03.rx_en = ~port_signals_soc2pad_i.gpio.gpio03_tx_en; + mux_to_pads_o.pad_io03.tx_en = port_signals_soc2pad_i.gpio.gpio03_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io03.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io03.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io03.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io03.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_UART0_RX: begin + mux_to_pads_o.pad_io03.chip2pad = 1'b1; + mux_to_pads_o.pad_io03.rx_en = 1'b1; + mux_to_pads_o.pad_io03.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_UART0_TX: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io03.rx_en = 1'b0; + mux_to_pads_o.pad_io03.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io03.rx_en = 1'b0; + mux_to_pads_o.pad_io03.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io03.rx_en = 1'b0; + mux_to_pads_o.pad_io03.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io03.rx_en = 1'b0; + mux_to_pads_o.pad_io03.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io03.rx_en = 1'b0; + mux_to_pads_o.pad_io03.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io03.rx_en = 1'b0; + mux_to_pads_o.pad_io03.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io03.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io03.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io03.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io03.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io03.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io03.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io03.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io03.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io03.chip2pad = 1'b0; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io03.chip2pad = 1'b0; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io03.chip2pad = 1'b0; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io03.chip2pad = 1'b0; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io03.chip2pad = 1'b0; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io03.chip2pad = 1'b0; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io03.chip2pad = 1'b0; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io03.chip2pad = 1'b0; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io03.chip2pad = 1'b0; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io03.chip2pad = 1'b0; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io03.chip2pad = 1'b0; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io03.chip2pad = 1'b0; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io03.chip2pad = 1'b0; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io03.rx_en = 1'b0; + mux_to_pads_o.pad_io03.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io03.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io03.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io03.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io03.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io03.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io03.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io03.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io03.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io03.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io03.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io03.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io03.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io03.rx_en = 1'b0; + mux_to_pads_o.pad_io03.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io03.rx_en = 1'b0; + mux_to_pads_o.pad_io03.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io03.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io03.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io03.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io03.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io03.chip2pad = s_reg2hw.pad_io03_cfg.chip2pad.q; + mux_to_pads_o.pad_io03.rx_en = 1'b1; + mux_to_pads_o.pad_io03.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io03.chip2pad = s_reg2hw.pad_io03_cfg.chip2pad.q; + mux_to_pads_o.pad_io03.rx_en = 1'b1; + mux_to_pads_o.pad_io03.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io03.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io03.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io03.chip2pad = s_reg2hw.pad_io03_cfg.chip2pad.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io04 + always_comb begin + unique case (s_reg2hw.pad_io04_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_DEFAULT: begin + mux_to_pads_o.pad_io04.chip2pad = s_reg2hw.pad_io04_cfg.chip2pad.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_GPIO_GPIO04: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.gpio.gpio04_out; + mux_to_pads_o.pad_io04.rx_en = ~port_signals_soc2pad_i.gpio.gpio04_tx_en; + mux_to_pads_o.pad_io04.tx_en = port_signals_soc2pad_i.gpio.gpio04_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io04.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io04.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io04.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io04.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_UART0_RX: begin + mux_to_pads_o.pad_io04.chip2pad = 1'b1; + mux_to_pads_o.pad_io04.rx_en = 1'b1; + mux_to_pads_o.pad_io04.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_UART0_TX: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io04.rx_en = 1'b0; + mux_to_pads_o.pad_io04.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io04.rx_en = 1'b0; + mux_to_pads_o.pad_io04.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io04.rx_en = 1'b0; + mux_to_pads_o.pad_io04.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io04.rx_en = 1'b0; + mux_to_pads_o.pad_io04.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io04.rx_en = 1'b0; + mux_to_pads_o.pad_io04.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io04.rx_en = 1'b0; + mux_to_pads_o.pad_io04.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io04.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io04.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io04.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io04.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io04.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io04.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io04.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io04.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io04.chip2pad = 1'b0; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io04.chip2pad = 1'b0; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io04.chip2pad = 1'b0; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io04.chip2pad = 1'b0; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io04.chip2pad = 1'b0; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io04.chip2pad = 1'b0; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io04.chip2pad = 1'b0; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io04.chip2pad = 1'b0; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io04.chip2pad = 1'b0; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io04.chip2pad = 1'b0; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io04.chip2pad = 1'b0; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io04.chip2pad = 1'b0; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io04.chip2pad = 1'b0; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io04.rx_en = 1'b0; + mux_to_pads_o.pad_io04.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io04.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io04.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io04.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io04.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io04.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io04.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io04.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io04.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io04.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io04.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io04.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io04.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io04.rx_en = 1'b0; + mux_to_pads_o.pad_io04.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io04.rx_en = 1'b0; + mux_to_pads_o.pad_io04.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io04.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io04.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io04.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io04.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io04.chip2pad = s_reg2hw.pad_io04_cfg.chip2pad.q; + mux_to_pads_o.pad_io04.rx_en = 1'b1; + mux_to_pads_o.pad_io04.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io04.chip2pad = s_reg2hw.pad_io04_cfg.chip2pad.q; + mux_to_pads_o.pad_io04.rx_en = 1'b1; + mux_to_pads_o.pad_io04.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io04.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io04.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io04.chip2pad = s_reg2hw.pad_io04_cfg.chip2pad.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io05 + always_comb begin + unique case (s_reg2hw.pad_io05_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_DEFAULT: begin + mux_to_pads_o.pad_io05.chip2pad = s_reg2hw.pad_io05_cfg.chip2pad.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_GPIO_GPIO05: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.gpio.gpio05_out; + mux_to_pads_o.pad_io05.rx_en = ~port_signals_soc2pad_i.gpio.gpio05_tx_en; + mux_to_pads_o.pad_io05.tx_en = port_signals_soc2pad_i.gpio.gpio05_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io05.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io05.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io05.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io05.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_UART0_RX: begin + mux_to_pads_o.pad_io05.chip2pad = 1'b1; + mux_to_pads_o.pad_io05.rx_en = 1'b1; + mux_to_pads_o.pad_io05.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_UART0_TX: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io05.rx_en = 1'b0; + mux_to_pads_o.pad_io05.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io05.rx_en = 1'b0; + mux_to_pads_o.pad_io05.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io05.rx_en = 1'b0; + mux_to_pads_o.pad_io05.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io05.rx_en = 1'b0; + mux_to_pads_o.pad_io05.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io05.rx_en = 1'b0; + mux_to_pads_o.pad_io05.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io05.rx_en = 1'b0; + mux_to_pads_o.pad_io05.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io05.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io05.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io05.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io05.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io05.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io05.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io05.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io05.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io05.chip2pad = 1'b0; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io05.chip2pad = 1'b0; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io05.chip2pad = 1'b0; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io05.chip2pad = 1'b0; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io05.chip2pad = 1'b0; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io05.chip2pad = 1'b0; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io05.chip2pad = 1'b0; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io05.chip2pad = 1'b0; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io05.chip2pad = 1'b0; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io05.chip2pad = 1'b0; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io05.chip2pad = 1'b0; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io05.chip2pad = 1'b0; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io05.chip2pad = 1'b0; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io05.rx_en = 1'b0; + mux_to_pads_o.pad_io05.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io05.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io05.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io05.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io05.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io05.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io05.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io05.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io05.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io05.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io05.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io05.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io05.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io05.rx_en = 1'b0; + mux_to_pads_o.pad_io05.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io05.rx_en = 1'b0; + mux_to_pads_o.pad_io05.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io05.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io05.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io05.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io05.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io05.chip2pad = s_reg2hw.pad_io05_cfg.chip2pad.q; + mux_to_pads_o.pad_io05.rx_en = 1'b1; + mux_to_pads_o.pad_io05.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io05.chip2pad = s_reg2hw.pad_io05_cfg.chip2pad.q; + mux_to_pads_o.pad_io05.rx_en = 1'b1; + mux_to_pads_o.pad_io05.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io05.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io05.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io05.chip2pad = s_reg2hw.pad_io05_cfg.chip2pad.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io06 + always_comb begin + unique case (s_reg2hw.pad_io06_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_DEFAULT: begin + mux_to_pads_o.pad_io06.chip2pad = s_reg2hw.pad_io06_cfg.chip2pad.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_GPIO_GPIO06: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.gpio.gpio06_out; + mux_to_pads_o.pad_io06.rx_en = ~port_signals_soc2pad_i.gpio.gpio06_tx_en; + mux_to_pads_o.pad_io06.tx_en = port_signals_soc2pad_i.gpio.gpio06_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io06.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io06.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io06.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io06.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_UART0_RX: begin + mux_to_pads_o.pad_io06.chip2pad = 1'b1; + mux_to_pads_o.pad_io06.rx_en = 1'b1; + mux_to_pads_o.pad_io06.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_UART0_TX: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io06.rx_en = 1'b0; + mux_to_pads_o.pad_io06.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io06.rx_en = 1'b0; + mux_to_pads_o.pad_io06.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io06.rx_en = 1'b0; + mux_to_pads_o.pad_io06.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io06.rx_en = 1'b0; + mux_to_pads_o.pad_io06.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io06.rx_en = 1'b0; + mux_to_pads_o.pad_io06.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io06.rx_en = 1'b0; + mux_to_pads_o.pad_io06.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io06.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io06.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io06.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io06.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io06.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io06.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io06.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io06.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io06.chip2pad = 1'b0; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io06.chip2pad = 1'b0; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io06.chip2pad = 1'b0; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io06.chip2pad = 1'b0; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io06.chip2pad = 1'b0; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io06.chip2pad = 1'b0; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io06.chip2pad = 1'b0; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io06.chip2pad = 1'b0; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io06.chip2pad = 1'b0; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io06.chip2pad = 1'b0; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io06.chip2pad = 1'b0; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io06.chip2pad = 1'b0; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io06.chip2pad = 1'b0; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io06.rx_en = 1'b0; + mux_to_pads_o.pad_io06.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io06.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io06.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io06.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io06.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io06.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io06.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io06.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io06.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io06.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io06.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io06.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io06.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io06.rx_en = 1'b0; + mux_to_pads_o.pad_io06.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io06.rx_en = 1'b0; + mux_to_pads_o.pad_io06.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io06.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io06.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io06.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io06.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io06.chip2pad = s_reg2hw.pad_io06_cfg.chip2pad.q; + mux_to_pads_o.pad_io06.rx_en = 1'b1; + mux_to_pads_o.pad_io06.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io06.chip2pad = s_reg2hw.pad_io06_cfg.chip2pad.q; + mux_to_pads_o.pad_io06.rx_en = 1'b1; + mux_to_pads_o.pad_io06.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io06.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io06.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io06.chip2pad = s_reg2hw.pad_io06_cfg.chip2pad.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io07 + always_comb begin + unique case (s_reg2hw.pad_io07_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_DEFAULT: begin + mux_to_pads_o.pad_io07.chip2pad = s_reg2hw.pad_io07_cfg.chip2pad.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_GPIO_GPIO07: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.gpio.gpio07_out; + mux_to_pads_o.pad_io07.rx_en = ~port_signals_soc2pad_i.gpio.gpio07_tx_en; + mux_to_pads_o.pad_io07.tx_en = port_signals_soc2pad_i.gpio.gpio07_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io07.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io07.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io07.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io07.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_UART0_RX: begin + mux_to_pads_o.pad_io07.chip2pad = 1'b1; + mux_to_pads_o.pad_io07.rx_en = 1'b1; + mux_to_pads_o.pad_io07.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_UART0_TX: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io07.rx_en = 1'b0; + mux_to_pads_o.pad_io07.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io07.rx_en = 1'b0; + mux_to_pads_o.pad_io07.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io07.rx_en = 1'b0; + mux_to_pads_o.pad_io07.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io07.rx_en = 1'b0; + mux_to_pads_o.pad_io07.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io07.rx_en = 1'b0; + mux_to_pads_o.pad_io07.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io07.rx_en = 1'b0; + mux_to_pads_o.pad_io07.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io07.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io07.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io07.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io07.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io07.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io07.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io07.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io07.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io07.chip2pad = 1'b0; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io07.chip2pad = 1'b0; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io07.chip2pad = 1'b0; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io07.chip2pad = 1'b0; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io07.chip2pad = 1'b0; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io07.chip2pad = 1'b0; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io07.chip2pad = 1'b0; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io07.chip2pad = 1'b0; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io07.chip2pad = 1'b0; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io07.chip2pad = 1'b0; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io07.chip2pad = 1'b0; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io07.chip2pad = 1'b0; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io07.chip2pad = 1'b0; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io07.rx_en = 1'b0; + mux_to_pads_o.pad_io07.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io07.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io07.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io07.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io07.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io07.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io07.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io07.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io07.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io07.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io07.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io07.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io07.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io07.rx_en = 1'b0; + mux_to_pads_o.pad_io07.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io07.rx_en = 1'b0; + mux_to_pads_o.pad_io07.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io07.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io07.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io07.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io07.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io07.chip2pad = s_reg2hw.pad_io07_cfg.chip2pad.q; + mux_to_pads_o.pad_io07.rx_en = 1'b1; + mux_to_pads_o.pad_io07.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io07.chip2pad = s_reg2hw.pad_io07_cfg.chip2pad.q; + mux_to_pads_o.pad_io07.rx_en = 1'b1; + mux_to_pads_o.pad_io07.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io07.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io07.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io07.chip2pad = s_reg2hw.pad_io07_cfg.chip2pad.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io08 + always_comb begin + unique case (s_reg2hw.pad_io08_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_DEFAULT: begin + mux_to_pads_o.pad_io08.chip2pad = s_reg2hw.pad_io08_cfg.chip2pad.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_GPIO_GPIO08: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.gpio.gpio08_out; + mux_to_pads_o.pad_io08.rx_en = ~port_signals_soc2pad_i.gpio.gpio08_tx_en; + mux_to_pads_o.pad_io08.tx_en = port_signals_soc2pad_i.gpio.gpio08_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io08.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io08.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io08.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io08.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_UART0_RX: begin + mux_to_pads_o.pad_io08.chip2pad = 1'b1; + mux_to_pads_o.pad_io08.rx_en = 1'b1; + mux_to_pads_o.pad_io08.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_UART0_TX: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io08.rx_en = 1'b0; + mux_to_pads_o.pad_io08.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io08.rx_en = 1'b0; + mux_to_pads_o.pad_io08.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io08.rx_en = 1'b0; + mux_to_pads_o.pad_io08.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io08.rx_en = 1'b0; + mux_to_pads_o.pad_io08.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io08.rx_en = 1'b0; + mux_to_pads_o.pad_io08.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io08.rx_en = 1'b0; + mux_to_pads_o.pad_io08.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io08.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io08.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io08.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io08.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io08.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io08.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io08.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io08.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io08.chip2pad = 1'b0; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io08.chip2pad = 1'b0; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io08.chip2pad = 1'b0; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io08.chip2pad = 1'b0; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io08.chip2pad = 1'b0; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io08.chip2pad = 1'b0; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io08.chip2pad = 1'b0; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io08.chip2pad = 1'b0; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io08.chip2pad = 1'b0; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io08.chip2pad = 1'b0; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io08.chip2pad = 1'b0; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io08.chip2pad = 1'b0; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io08.chip2pad = 1'b0; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io08.rx_en = 1'b0; + mux_to_pads_o.pad_io08.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io08.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io08.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io08.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io08.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io08.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io08.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io08.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io08.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io08.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io08.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io08.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io08.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io08.rx_en = 1'b0; + mux_to_pads_o.pad_io08.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io08.rx_en = 1'b0; + mux_to_pads_o.pad_io08.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io08.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io08.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io08.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io08.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io08.chip2pad = s_reg2hw.pad_io08_cfg.chip2pad.q; + mux_to_pads_o.pad_io08.rx_en = 1'b1; + mux_to_pads_o.pad_io08.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io08.chip2pad = s_reg2hw.pad_io08_cfg.chip2pad.q; + mux_to_pads_o.pad_io08.rx_en = 1'b1; + mux_to_pads_o.pad_io08.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io08.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io08.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io08.chip2pad = s_reg2hw.pad_io08_cfg.chip2pad.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io09 + always_comb begin + unique case (s_reg2hw.pad_io09_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_DEFAULT: begin + mux_to_pads_o.pad_io09.chip2pad = s_reg2hw.pad_io09_cfg.chip2pad.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_GPIO_GPIO09: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.gpio.gpio09_out; + mux_to_pads_o.pad_io09.rx_en = ~port_signals_soc2pad_i.gpio.gpio09_tx_en; + mux_to_pads_o.pad_io09.tx_en = port_signals_soc2pad_i.gpio.gpio09_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io09.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io09.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io09.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io09.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_UART0_RX: begin + mux_to_pads_o.pad_io09.chip2pad = 1'b1; + mux_to_pads_o.pad_io09.rx_en = 1'b1; + mux_to_pads_o.pad_io09.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_UART0_TX: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io09.rx_en = 1'b0; + mux_to_pads_o.pad_io09.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io09.rx_en = 1'b0; + mux_to_pads_o.pad_io09.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io09.rx_en = 1'b0; + mux_to_pads_o.pad_io09.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io09.rx_en = 1'b0; + mux_to_pads_o.pad_io09.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io09.rx_en = 1'b0; + mux_to_pads_o.pad_io09.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io09.rx_en = 1'b0; + mux_to_pads_o.pad_io09.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io09.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io09.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io09.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io09.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io09.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io09.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io09.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io09.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io09.chip2pad = 1'b0; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io09.chip2pad = 1'b0; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io09.chip2pad = 1'b0; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io09.chip2pad = 1'b0; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io09.chip2pad = 1'b0; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io09.chip2pad = 1'b0; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io09.chip2pad = 1'b0; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io09.chip2pad = 1'b0; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io09.chip2pad = 1'b0; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io09.chip2pad = 1'b0; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io09.chip2pad = 1'b0; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io09.chip2pad = 1'b0; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io09.chip2pad = 1'b0; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io09.rx_en = 1'b0; + mux_to_pads_o.pad_io09.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io09.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io09.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io09.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io09.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io09.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io09.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io09.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io09.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io09.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io09.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io09.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io09.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io09.rx_en = 1'b0; + mux_to_pads_o.pad_io09.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io09.rx_en = 1'b0; + mux_to_pads_o.pad_io09.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io09.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io09.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io09.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io09.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io09.chip2pad = s_reg2hw.pad_io09_cfg.chip2pad.q; + mux_to_pads_o.pad_io09.rx_en = 1'b1; + mux_to_pads_o.pad_io09.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io09.chip2pad = s_reg2hw.pad_io09_cfg.chip2pad.q; + mux_to_pads_o.pad_io09.rx_en = 1'b1; + mux_to_pads_o.pad_io09.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io09.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io09.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io09.chip2pad = s_reg2hw.pad_io09_cfg.chip2pad.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io10 + always_comb begin + unique case (s_reg2hw.pad_io10_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_DEFAULT: begin + mux_to_pads_o.pad_io10.chip2pad = s_reg2hw.pad_io10_cfg.chip2pad.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_GPIO_GPIO10: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.gpio.gpio10_out; + mux_to_pads_o.pad_io10.rx_en = ~port_signals_soc2pad_i.gpio.gpio10_tx_en; + mux_to_pads_o.pad_io10.tx_en = port_signals_soc2pad_i.gpio.gpio10_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io10.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io10.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io10.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io10.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_UART0_RX: begin + mux_to_pads_o.pad_io10.chip2pad = 1'b1; + mux_to_pads_o.pad_io10.rx_en = 1'b1; + mux_to_pads_o.pad_io10.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_UART0_TX: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io10.rx_en = 1'b0; + mux_to_pads_o.pad_io10.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io10.rx_en = 1'b0; + mux_to_pads_o.pad_io10.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io10.rx_en = 1'b0; + mux_to_pads_o.pad_io10.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io10.rx_en = 1'b0; + mux_to_pads_o.pad_io10.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io10.rx_en = 1'b0; + mux_to_pads_o.pad_io10.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io10.rx_en = 1'b0; + mux_to_pads_o.pad_io10.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io10.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io10.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io10.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io10.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io10.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io10.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io10.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io10.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io10.chip2pad = 1'b0; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io10.chip2pad = 1'b0; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io10.chip2pad = 1'b0; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io10.chip2pad = 1'b0; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io10.chip2pad = 1'b0; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io10.chip2pad = 1'b0; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io10.chip2pad = 1'b0; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io10.chip2pad = 1'b0; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io10.chip2pad = 1'b0; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io10.chip2pad = 1'b0; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io10.chip2pad = 1'b0; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io10.chip2pad = 1'b0; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io10.chip2pad = 1'b0; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io10.rx_en = 1'b0; + mux_to_pads_o.pad_io10.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io10.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io10.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io10.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io10.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io10.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io10.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io10.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io10.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io10.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io10.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io10.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io10.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io10.rx_en = 1'b0; + mux_to_pads_o.pad_io10.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io10.rx_en = 1'b0; + mux_to_pads_o.pad_io10.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io10.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io10.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io10.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io10.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io10.chip2pad = s_reg2hw.pad_io10_cfg.chip2pad.q; + mux_to_pads_o.pad_io10.rx_en = 1'b1; + mux_to_pads_o.pad_io10.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io10.chip2pad = s_reg2hw.pad_io10_cfg.chip2pad.q; + mux_to_pads_o.pad_io10.rx_en = 1'b1; + mux_to_pads_o.pad_io10.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io10.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io10.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io10.chip2pad = s_reg2hw.pad_io10_cfg.chip2pad.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io11 + always_comb begin + unique case (s_reg2hw.pad_io11_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_DEFAULT: begin + mux_to_pads_o.pad_io11.chip2pad = s_reg2hw.pad_io11_cfg.chip2pad.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_GPIO_GPIO11: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.gpio.gpio11_out; + mux_to_pads_o.pad_io11.rx_en = ~port_signals_soc2pad_i.gpio.gpio11_tx_en; + mux_to_pads_o.pad_io11.tx_en = port_signals_soc2pad_i.gpio.gpio11_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io11.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io11.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io11.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io11.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_UART0_RX: begin + mux_to_pads_o.pad_io11.chip2pad = 1'b1; + mux_to_pads_o.pad_io11.rx_en = 1'b1; + mux_to_pads_o.pad_io11.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_UART0_TX: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io11.rx_en = 1'b0; + mux_to_pads_o.pad_io11.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io11.rx_en = 1'b0; + mux_to_pads_o.pad_io11.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io11.rx_en = 1'b0; + mux_to_pads_o.pad_io11.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io11.rx_en = 1'b0; + mux_to_pads_o.pad_io11.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io11.rx_en = 1'b0; + mux_to_pads_o.pad_io11.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io11.rx_en = 1'b0; + mux_to_pads_o.pad_io11.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io11.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io11.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io11.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io11.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io11.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io11.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io11.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io11.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io11.chip2pad = 1'b0; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io11.chip2pad = 1'b0; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io11.chip2pad = 1'b0; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io11.chip2pad = 1'b0; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io11.chip2pad = 1'b0; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io11.chip2pad = 1'b0; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io11.chip2pad = 1'b0; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io11.chip2pad = 1'b0; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io11.chip2pad = 1'b0; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io11.chip2pad = 1'b0; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io11.chip2pad = 1'b0; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io11.chip2pad = 1'b0; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io11.chip2pad = 1'b0; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io11.rx_en = 1'b0; + mux_to_pads_o.pad_io11.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io11.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io11.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io11.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io11.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io11.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io11.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io11.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io11.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io11.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io11.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io11.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io11.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io11.rx_en = 1'b0; + mux_to_pads_o.pad_io11.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io11.rx_en = 1'b0; + mux_to_pads_o.pad_io11.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io11.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io11.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io11.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io11.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io11.chip2pad = s_reg2hw.pad_io11_cfg.chip2pad.q; + mux_to_pads_o.pad_io11.rx_en = 1'b1; + mux_to_pads_o.pad_io11.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io11.chip2pad = s_reg2hw.pad_io11_cfg.chip2pad.q; + mux_to_pads_o.pad_io11.rx_en = 1'b1; + mux_to_pads_o.pad_io11.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io11.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io11.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io11.chip2pad = s_reg2hw.pad_io11_cfg.chip2pad.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io12 + always_comb begin + unique case (s_reg2hw.pad_io12_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_DEFAULT: begin + mux_to_pads_o.pad_io12.chip2pad = s_reg2hw.pad_io12_cfg.chip2pad.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_GPIO_GPIO12: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.gpio.gpio12_out; + mux_to_pads_o.pad_io12.rx_en = ~port_signals_soc2pad_i.gpio.gpio12_tx_en; + mux_to_pads_o.pad_io12.tx_en = port_signals_soc2pad_i.gpio.gpio12_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io12.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io12.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io12.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io12.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_UART0_RX: begin + mux_to_pads_o.pad_io12.chip2pad = 1'b1; + mux_to_pads_o.pad_io12.rx_en = 1'b1; + mux_to_pads_o.pad_io12.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_UART0_TX: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io12.rx_en = 1'b0; + mux_to_pads_o.pad_io12.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io12.rx_en = 1'b0; + mux_to_pads_o.pad_io12.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io12.rx_en = 1'b0; + mux_to_pads_o.pad_io12.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io12.rx_en = 1'b0; + mux_to_pads_o.pad_io12.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io12.rx_en = 1'b0; + mux_to_pads_o.pad_io12.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io12.rx_en = 1'b0; + mux_to_pads_o.pad_io12.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io12.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io12.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io12.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io12.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io12.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io12.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io12.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io12.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io12.chip2pad = 1'b0; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io12.chip2pad = 1'b0; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io12.chip2pad = 1'b0; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io12.chip2pad = 1'b0; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io12.chip2pad = 1'b0; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io12.chip2pad = 1'b0; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io12.chip2pad = 1'b0; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io12.chip2pad = 1'b0; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io12.chip2pad = 1'b0; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io12.chip2pad = 1'b0; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io12.chip2pad = 1'b0; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io12.chip2pad = 1'b0; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io12.chip2pad = 1'b0; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io12.rx_en = 1'b0; + mux_to_pads_o.pad_io12.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io12.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io12.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io12.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io12.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io12.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io12.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io12.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io12.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io12.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io12.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io12.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io12.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io12.rx_en = 1'b0; + mux_to_pads_o.pad_io12.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io12.rx_en = 1'b0; + mux_to_pads_o.pad_io12.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io12.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io12.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io12.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io12.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io12.chip2pad = s_reg2hw.pad_io12_cfg.chip2pad.q; + mux_to_pads_o.pad_io12.rx_en = 1'b1; + mux_to_pads_o.pad_io12.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io12.chip2pad = s_reg2hw.pad_io12_cfg.chip2pad.q; + mux_to_pads_o.pad_io12.rx_en = 1'b1; + mux_to_pads_o.pad_io12.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io12.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io12.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io12.chip2pad = s_reg2hw.pad_io12_cfg.chip2pad.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io13 + always_comb begin + unique case (s_reg2hw.pad_io13_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_DEFAULT: begin + mux_to_pads_o.pad_io13.chip2pad = s_reg2hw.pad_io13_cfg.chip2pad.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_GPIO_GPIO13: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.gpio.gpio13_out; + mux_to_pads_o.pad_io13.rx_en = ~port_signals_soc2pad_i.gpio.gpio13_tx_en; + mux_to_pads_o.pad_io13.tx_en = port_signals_soc2pad_i.gpio.gpio13_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io13.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io13.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io13.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io13.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_UART0_RX: begin + mux_to_pads_o.pad_io13.chip2pad = 1'b1; + mux_to_pads_o.pad_io13.rx_en = 1'b1; + mux_to_pads_o.pad_io13.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_UART0_TX: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io13.rx_en = 1'b0; + mux_to_pads_o.pad_io13.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io13.rx_en = 1'b0; + mux_to_pads_o.pad_io13.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io13.rx_en = 1'b0; + mux_to_pads_o.pad_io13.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io13.rx_en = 1'b0; + mux_to_pads_o.pad_io13.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io13.rx_en = 1'b0; + mux_to_pads_o.pad_io13.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io13.rx_en = 1'b0; + mux_to_pads_o.pad_io13.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io13.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io13.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io13.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io13.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io13.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io13.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io13.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io13.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io13.chip2pad = 1'b0; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io13.chip2pad = 1'b0; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io13.chip2pad = 1'b0; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io13.chip2pad = 1'b0; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io13.chip2pad = 1'b0; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io13.chip2pad = 1'b0; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io13.chip2pad = 1'b0; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io13.chip2pad = 1'b0; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io13.chip2pad = 1'b0; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io13.chip2pad = 1'b0; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io13.chip2pad = 1'b0; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io13.chip2pad = 1'b0; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io13.chip2pad = 1'b0; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io13.rx_en = 1'b0; + mux_to_pads_o.pad_io13.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io13.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io13.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io13.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io13.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io13.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io13.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io13.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io13.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io13.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io13.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io13.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io13.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io13.rx_en = 1'b0; + mux_to_pads_o.pad_io13.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io13.rx_en = 1'b0; + mux_to_pads_o.pad_io13.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io13.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io13.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io13.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io13.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io13.chip2pad = s_reg2hw.pad_io13_cfg.chip2pad.q; + mux_to_pads_o.pad_io13.rx_en = 1'b1; + mux_to_pads_o.pad_io13.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io13.chip2pad = s_reg2hw.pad_io13_cfg.chip2pad.q; + mux_to_pads_o.pad_io13.rx_en = 1'b1; + mux_to_pads_o.pad_io13.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io13.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io13.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io13.chip2pad = s_reg2hw.pad_io13_cfg.chip2pad.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io14 + always_comb begin + unique case (s_reg2hw.pad_io14_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_DEFAULT: begin + mux_to_pads_o.pad_io14.chip2pad = s_reg2hw.pad_io14_cfg.chip2pad.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_GPIO_GPIO14: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.gpio.gpio14_out; + mux_to_pads_o.pad_io14.rx_en = ~port_signals_soc2pad_i.gpio.gpio14_tx_en; + mux_to_pads_o.pad_io14.tx_en = port_signals_soc2pad_i.gpio.gpio14_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io14.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io14.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io14.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io14.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_UART0_RX: begin + mux_to_pads_o.pad_io14.chip2pad = 1'b1; + mux_to_pads_o.pad_io14.rx_en = 1'b1; + mux_to_pads_o.pad_io14.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_UART0_TX: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io14.rx_en = 1'b0; + mux_to_pads_o.pad_io14.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io14.rx_en = 1'b0; + mux_to_pads_o.pad_io14.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io14.rx_en = 1'b0; + mux_to_pads_o.pad_io14.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io14.rx_en = 1'b0; + mux_to_pads_o.pad_io14.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io14.rx_en = 1'b0; + mux_to_pads_o.pad_io14.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io14.rx_en = 1'b0; + mux_to_pads_o.pad_io14.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io14.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io14.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io14.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io14.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io14.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io14.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io14.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io14.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io14.chip2pad = 1'b0; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io14.chip2pad = 1'b0; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io14.chip2pad = 1'b0; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io14.chip2pad = 1'b0; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io14.chip2pad = 1'b0; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io14.chip2pad = 1'b0; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io14.chip2pad = 1'b0; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io14.chip2pad = 1'b0; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io14.chip2pad = 1'b0; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io14.chip2pad = 1'b0; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io14.chip2pad = 1'b0; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io14.chip2pad = 1'b0; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io14.chip2pad = 1'b0; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io14.rx_en = 1'b0; + mux_to_pads_o.pad_io14.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io14.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io14.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io14.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io14.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io14.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io14.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io14.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io14.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io14.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io14.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io14.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io14.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io14.rx_en = 1'b0; + mux_to_pads_o.pad_io14.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io14.rx_en = 1'b0; + mux_to_pads_o.pad_io14.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io14.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io14.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io14.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io14.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io14.chip2pad = s_reg2hw.pad_io14_cfg.chip2pad.q; + mux_to_pads_o.pad_io14.rx_en = 1'b1; + mux_to_pads_o.pad_io14.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io14.chip2pad = s_reg2hw.pad_io14_cfg.chip2pad.q; + mux_to_pads_o.pad_io14.rx_en = 1'b1; + mux_to_pads_o.pad_io14.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io14.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io14.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io14.chip2pad = s_reg2hw.pad_io14_cfg.chip2pad.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io15 + always_comb begin + unique case (s_reg2hw.pad_io15_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_DEFAULT: begin + mux_to_pads_o.pad_io15.chip2pad = s_reg2hw.pad_io15_cfg.chip2pad.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_GPIO_GPIO15: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.gpio.gpio15_out; + mux_to_pads_o.pad_io15.rx_en = ~port_signals_soc2pad_i.gpio.gpio15_tx_en; + mux_to_pads_o.pad_io15.tx_en = port_signals_soc2pad_i.gpio.gpio15_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io15.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io15.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io15.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io15.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_UART0_RX: begin + mux_to_pads_o.pad_io15.chip2pad = 1'b1; + mux_to_pads_o.pad_io15.rx_en = 1'b1; + mux_to_pads_o.pad_io15.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_UART0_TX: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io15.rx_en = 1'b0; + mux_to_pads_o.pad_io15.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io15.rx_en = 1'b0; + mux_to_pads_o.pad_io15.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io15.rx_en = 1'b0; + mux_to_pads_o.pad_io15.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io15.rx_en = 1'b0; + mux_to_pads_o.pad_io15.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io15.rx_en = 1'b0; + mux_to_pads_o.pad_io15.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io15.rx_en = 1'b0; + mux_to_pads_o.pad_io15.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io15.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io15.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io15.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io15.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io15.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io15.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io15.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io15.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io15.chip2pad = 1'b0; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io15.chip2pad = 1'b0; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io15.chip2pad = 1'b0; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io15.chip2pad = 1'b0; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io15.chip2pad = 1'b0; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io15.chip2pad = 1'b0; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io15.chip2pad = 1'b0; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io15.chip2pad = 1'b0; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io15.chip2pad = 1'b0; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io15.chip2pad = 1'b0; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io15.chip2pad = 1'b0; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io15.chip2pad = 1'b0; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io15.chip2pad = 1'b0; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io15.rx_en = 1'b0; + mux_to_pads_o.pad_io15.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io15.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io15.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io15.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io15.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io15.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io15.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io15.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io15.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io15.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io15.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io15.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io15.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io15.rx_en = 1'b0; + mux_to_pads_o.pad_io15.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io15.rx_en = 1'b0; + mux_to_pads_o.pad_io15.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io15.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io15.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io15.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io15.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io15.chip2pad = s_reg2hw.pad_io15_cfg.chip2pad.q; + mux_to_pads_o.pad_io15.rx_en = 1'b1; + mux_to_pads_o.pad_io15.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io15.chip2pad = s_reg2hw.pad_io15_cfg.chip2pad.q; + mux_to_pads_o.pad_io15.rx_en = 1'b1; + mux_to_pads_o.pad_io15.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io15.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io15.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io15.chip2pad = s_reg2hw.pad_io15_cfg.chip2pad.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io16 + always_comb begin + unique case (s_reg2hw.pad_io16_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_DEFAULT: begin + mux_to_pads_o.pad_io16.chip2pad = s_reg2hw.pad_io16_cfg.chip2pad.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_GPIO_GPIO16: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.gpio.gpio16_out; + mux_to_pads_o.pad_io16.rx_en = ~port_signals_soc2pad_i.gpio.gpio16_tx_en; + mux_to_pads_o.pad_io16.tx_en = port_signals_soc2pad_i.gpio.gpio16_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io16.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io16.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io16.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io16.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_UART0_RX: begin + mux_to_pads_o.pad_io16.chip2pad = 1'b1; + mux_to_pads_o.pad_io16.rx_en = 1'b1; + mux_to_pads_o.pad_io16.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_UART0_TX: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io16.rx_en = 1'b0; + mux_to_pads_o.pad_io16.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io16.rx_en = 1'b0; + mux_to_pads_o.pad_io16.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io16.rx_en = 1'b0; + mux_to_pads_o.pad_io16.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io16.rx_en = 1'b0; + mux_to_pads_o.pad_io16.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io16.rx_en = 1'b0; + mux_to_pads_o.pad_io16.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io16.rx_en = 1'b0; + mux_to_pads_o.pad_io16.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io16.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io16.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io16.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io16.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io16.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io16.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io16.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io16.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io16.chip2pad = 1'b0; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io16.chip2pad = 1'b0; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io16.chip2pad = 1'b0; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io16.chip2pad = 1'b0; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io16.chip2pad = 1'b0; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io16.chip2pad = 1'b0; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io16.chip2pad = 1'b0; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io16.chip2pad = 1'b0; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io16.chip2pad = 1'b0; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io16.chip2pad = 1'b0; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io16.chip2pad = 1'b0; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io16.chip2pad = 1'b0; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io16.chip2pad = 1'b0; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io16.rx_en = 1'b0; + mux_to_pads_o.pad_io16.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io16.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io16.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io16.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io16.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io16.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io16.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io16.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io16.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io16.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io16.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io16.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io16.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io16.rx_en = 1'b0; + mux_to_pads_o.pad_io16.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io16.rx_en = 1'b0; + mux_to_pads_o.pad_io16.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io16.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io16.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io16.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io16.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io16.chip2pad = s_reg2hw.pad_io16_cfg.chip2pad.q; + mux_to_pads_o.pad_io16.rx_en = 1'b1; + mux_to_pads_o.pad_io16.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io16.chip2pad = s_reg2hw.pad_io16_cfg.chip2pad.q; + mux_to_pads_o.pad_io16.rx_en = 1'b1; + mux_to_pads_o.pad_io16.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io16.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io16.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io16.chip2pad = s_reg2hw.pad_io16_cfg.chip2pad.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io17 + always_comb begin + unique case (s_reg2hw.pad_io17_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_DEFAULT: begin + mux_to_pads_o.pad_io17.chip2pad = s_reg2hw.pad_io17_cfg.chip2pad.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_GPIO_GPIO17: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.gpio.gpio17_out; + mux_to_pads_o.pad_io17.rx_en = ~port_signals_soc2pad_i.gpio.gpio17_tx_en; + mux_to_pads_o.pad_io17.tx_en = port_signals_soc2pad_i.gpio.gpio17_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io17.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io17.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io17.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io17.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_UART0_RX: begin + mux_to_pads_o.pad_io17.chip2pad = 1'b1; + mux_to_pads_o.pad_io17.rx_en = 1'b1; + mux_to_pads_o.pad_io17.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_UART0_TX: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io17.rx_en = 1'b0; + mux_to_pads_o.pad_io17.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io17.rx_en = 1'b0; + mux_to_pads_o.pad_io17.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io17.rx_en = 1'b0; + mux_to_pads_o.pad_io17.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io17.rx_en = 1'b0; + mux_to_pads_o.pad_io17.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io17.rx_en = 1'b0; + mux_to_pads_o.pad_io17.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io17.rx_en = 1'b0; + mux_to_pads_o.pad_io17.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io17.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io17.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io17.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io17.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io17.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io17.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io17.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io17.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io17.chip2pad = 1'b0; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io17.chip2pad = 1'b0; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io17.chip2pad = 1'b0; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io17.chip2pad = 1'b0; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io17.chip2pad = 1'b0; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io17.chip2pad = 1'b0; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io17.chip2pad = 1'b0; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io17.chip2pad = 1'b0; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io17.chip2pad = 1'b0; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io17.chip2pad = 1'b0; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io17.chip2pad = 1'b0; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io17.chip2pad = 1'b0; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io17.chip2pad = 1'b0; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io17.rx_en = 1'b0; + mux_to_pads_o.pad_io17.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io17.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io17.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io17.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io17.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io17.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io17.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io17.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io17.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io17.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io17.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io17.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io17.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io17.rx_en = 1'b0; + mux_to_pads_o.pad_io17.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io17.rx_en = 1'b0; + mux_to_pads_o.pad_io17.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io17.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io17.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io17.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io17.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io17.chip2pad = s_reg2hw.pad_io17_cfg.chip2pad.q; + mux_to_pads_o.pad_io17.rx_en = 1'b1; + mux_to_pads_o.pad_io17.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io17.chip2pad = s_reg2hw.pad_io17_cfg.chip2pad.q; + mux_to_pads_o.pad_io17.rx_en = 1'b1; + mux_to_pads_o.pad_io17.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io17.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io17.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io17.chip2pad = s_reg2hw.pad_io17_cfg.chip2pad.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io18 + always_comb begin + unique case (s_reg2hw.pad_io18_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_DEFAULT: begin + mux_to_pads_o.pad_io18.chip2pad = s_reg2hw.pad_io18_cfg.chip2pad.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_GPIO_GPIO18: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.gpio.gpio18_out; + mux_to_pads_o.pad_io18.rx_en = ~port_signals_soc2pad_i.gpio.gpio18_tx_en; + mux_to_pads_o.pad_io18.tx_en = port_signals_soc2pad_i.gpio.gpio18_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io18.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io18.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io18.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io18.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_UART0_RX: begin + mux_to_pads_o.pad_io18.chip2pad = 1'b1; + mux_to_pads_o.pad_io18.rx_en = 1'b1; + mux_to_pads_o.pad_io18.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_UART0_TX: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io18.rx_en = 1'b0; + mux_to_pads_o.pad_io18.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io18.rx_en = 1'b0; + mux_to_pads_o.pad_io18.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io18.rx_en = 1'b0; + mux_to_pads_o.pad_io18.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io18.rx_en = 1'b0; + mux_to_pads_o.pad_io18.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io18.rx_en = 1'b0; + mux_to_pads_o.pad_io18.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io18.rx_en = 1'b0; + mux_to_pads_o.pad_io18.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io18.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io18.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io18.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io18.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io18.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io18.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io18.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io18.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io18.chip2pad = 1'b0; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io18.chip2pad = 1'b0; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io18.chip2pad = 1'b0; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io18.chip2pad = 1'b0; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io18.chip2pad = 1'b0; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io18.chip2pad = 1'b0; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io18.chip2pad = 1'b0; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io18.chip2pad = 1'b0; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io18.chip2pad = 1'b0; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io18.chip2pad = 1'b0; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io18.chip2pad = 1'b0; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io18.chip2pad = 1'b0; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io18.chip2pad = 1'b0; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io18.rx_en = 1'b0; + mux_to_pads_o.pad_io18.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io18.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io18.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io18.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io18.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io18.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io18.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io18.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io18.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io18.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io18.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io18.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io18.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io18.rx_en = 1'b0; + mux_to_pads_o.pad_io18.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io18.rx_en = 1'b0; + mux_to_pads_o.pad_io18.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io18.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io18.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io18.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io18.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io18.chip2pad = s_reg2hw.pad_io18_cfg.chip2pad.q; + mux_to_pads_o.pad_io18.rx_en = 1'b1; + mux_to_pads_o.pad_io18.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io18.chip2pad = s_reg2hw.pad_io18_cfg.chip2pad.q; + mux_to_pads_o.pad_io18.rx_en = 1'b1; + mux_to_pads_o.pad_io18.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io18.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io18.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io18.chip2pad = s_reg2hw.pad_io18_cfg.chip2pad.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io19 + always_comb begin + unique case (s_reg2hw.pad_io19_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_DEFAULT: begin + mux_to_pads_o.pad_io19.chip2pad = s_reg2hw.pad_io19_cfg.chip2pad.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_GPIO_GPIO19: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.gpio.gpio19_out; + mux_to_pads_o.pad_io19.rx_en = ~port_signals_soc2pad_i.gpio.gpio19_tx_en; + mux_to_pads_o.pad_io19.tx_en = port_signals_soc2pad_i.gpio.gpio19_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io19.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io19.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io19.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io19.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_UART0_RX: begin + mux_to_pads_o.pad_io19.chip2pad = 1'b1; + mux_to_pads_o.pad_io19.rx_en = 1'b1; + mux_to_pads_o.pad_io19.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_UART0_TX: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io19.rx_en = 1'b0; + mux_to_pads_o.pad_io19.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io19.rx_en = 1'b0; + mux_to_pads_o.pad_io19.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io19.rx_en = 1'b0; + mux_to_pads_o.pad_io19.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io19.rx_en = 1'b0; + mux_to_pads_o.pad_io19.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io19.rx_en = 1'b0; + mux_to_pads_o.pad_io19.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io19.rx_en = 1'b0; + mux_to_pads_o.pad_io19.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io19.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io19.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io19.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io19.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io19.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io19.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io19.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io19.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io19.chip2pad = 1'b0; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io19.chip2pad = 1'b0; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io19.chip2pad = 1'b0; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io19.chip2pad = 1'b0; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io19.chip2pad = 1'b0; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io19.chip2pad = 1'b0; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io19.chip2pad = 1'b0; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io19.chip2pad = 1'b0; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io19.chip2pad = 1'b0; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io19.chip2pad = 1'b0; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io19.chip2pad = 1'b0; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io19.chip2pad = 1'b0; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io19.chip2pad = 1'b0; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io19.rx_en = 1'b0; + mux_to_pads_o.pad_io19.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io19.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io19.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io19.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io19.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io19.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io19.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io19.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io19.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io19.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io19.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io19.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io19.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io19.rx_en = 1'b0; + mux_to_pads_o.pad_io19.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io19.rx_en = 1'b0; + mux_to_pads_o.pad_io19.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io19.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io19.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io19.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io19.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io19.chip2pad = s_reg2hw.pad_io19_cfg.chip2pad.q; + mux_to_pads_o.pad_io19.rx_en = 1'b1; + mux_to_pads_o.pad_io19.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io19.chip2pad = s_reg2hw.pad_io19_cfg.chip2pad.q; + mux_to_pads_o.pad_io19.rx_en = 1'b1; + mux_to_pads_o.pad_io19.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io19.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io19.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io19.chip2pad = s_reg2hw.pad_io19_cfg.chip2pad.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io20 + always_comb begin + unique case (s_reg2hw.pad_io20_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_DEFAULT: begin + mux_to_pads_o.pad_io20.chip2pad = s_reg2hw.pad_io20_cfg.chip2pad.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_GPIO_GPIO20: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.gpio.gpio20_out; + mux_to_pads_o.pad_io20.rx_en = ~port_signals_soc2pad_i.gpio.gpio20_tx_en; + mux_to_pads_o.pad_io20.tx_en = port_signals_soc2pad_i.gpio.gpio20_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io20.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io20.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io20.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io20.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_UART0_RX: begin + mux_to_pads_o.pad_io20.chip2pad = 1'b1; + mux_to_pads_o.pad_io20.rx_en = 1'b1; + mux_to_pads_o.pad_io20.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_UART0_TX: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io20.rx_en = 1'b0; + mux_to_pads_o.pad_io20.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io20.rx_en = 1'b0; + mux_to_pads_o.pad_io20.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io20.rx_en = 1'b0; + mux_to_pads_o.pad_io20.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io20.rx_en = 1'b0; + mux_to_pads_o.pad_io20.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io20.rx_en = 1'b0; + mux_to_pads_o.pad_io20.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io20.rx_en = 1'b0; + mux_to_pads_o.pad_io20.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io20.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io20.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io20.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io20.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io20.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io20.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io20.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io20.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io20.chip2pad = 1'b0; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io20.chip2pad = 1'b0; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io20.chip2pad = 1'b0; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io20.chip2pad = 1'b0; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io20.chip2pad = 1'b0; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io20.chip2pad = 1'b0; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io20.chip2pad = 1'b0; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io20.chip2pad = 1'b0; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io20.chip2pad = 1'b0; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io20.chip2pad = 1'b0; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io20.chip2pad = 1'b0; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io20.chip2pad = 1'b0; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io20.chip2pad = 1'b0; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io20.rx_en = 1'b0; + mux_to_pads_o.pad_io20.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io20.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io20.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io20.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io20.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io20.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io20.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io20.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io20.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io20.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io20.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io20.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io20.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io20.rx_en = 1'b0; + mux_to_pads_o.pad_io20.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io20.rx_en = 1'b0; + mux_to_pads_o.pad_io20.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io20.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io20.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io20.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io20.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io20.chip2pad = s_reg2hw.pad_io20_cfg.chip2pad.q; + mux_to_pads_o.pad_io20.rx_en = 1'b1; + mux_to_pads_o.pad_io20.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io20.chip2pad = s_reg2hw.pad_io20_cfg.chip2pad.q; + mux_to_pads_o.pad_io20.rx_en = 1'b1; + mux_to_pads_o.pad_io20.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io20.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io20.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io20.chip2pad = s_reg2hw.pad_io20_cfg.chip2pad.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io21 + always_comb begin + unique case (s_reg2hw.pad_io21_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_DEFAULT: begin + mux_to_pads_o.pad_io21.chip2pad = s_reg2hw.pad_io21_cfg.chip2pad.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_GPIO_GPIO21: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.gpio.gpio21_out; + mux_to_pads_o.pad_io21.rx_en = ~port_signals_soc2pad_i.gpio.gpio21_tx_en; + mux_to_pads_o.pad_io21.tx_en = port_signals_soc2pad_i.gpio.gpio21_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io21.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io21.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io21.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io21.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_UART0_RX: begin + mux_to_pads_o.pad_io21.chip2pad = 1'b1; + mux_to_pads_o.pad_io21.rx_en = 1'b1; + mux_to_pads_o.pad_io21.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_UART0_TX: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io21.rx_en = 1'b0; + mux_to_pads_o.pad_io21.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io21.rx_en = 1'b0; + mux_to_pads_o.pad_io21.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io21.rx_en = 1'b0; + mux_to_pads_o.pad_io21.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io21.rx_en = 1'b0; + mux_to_pads_o.pad_io21.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io21.rx_en = 1'b0; + mux_to_pads_o.pad_io21.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io21.rx_en = 1'b0; + mux_to_pads_o.pad_io21.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io21.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io21.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io21.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io21.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io21.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io21.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io21.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io21.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io21.chip2pad = 1'b0; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io21.chip2pad = 1'b0; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io21.chip2pad = 1'b0; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io21.chip2pad = 1'b0; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io21.chip2pad = 1'b0; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io21.chip2pad = 1'b0; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io21.chip2pad = 1'b0; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io21.chip2pad = 1'b0; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io21.chip2pad = 1'b0; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io21.chip2pad = 1'b0; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io21.chip2pad = 1'b0; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io21.chip2pad = 1'b0; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io21.chip2pad = 1'b0; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io21.rx_en = 1'b0; + mux_to_pads_o.pad_io21.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io21.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io21.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io21.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io21.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io21.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io21.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io21.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io21.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io21.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io21.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io21.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io21.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io21.rx_en = 1'b0; + mux_to_pads_o.pad_io21.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io21.rx_en = 1'b0; + mux_to_pads_o.pad_io21.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io21.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io21.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io21.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io21.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io21.chip2pad = s_reg2hw.pad_io21_cfg.chip2pad.q; + mux_to_pads_o.pad_io21.rx_en = 1'b1; + mux_to_pads_o.pad_io21.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io21.chip2pad = s_reg2hw.pad_io21_cfg.chip2pad.q; + mux_to_pads_o.pad_io21.rx_en = 1'b1; + mux_to_pads_o.pad_io21.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io21.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io21.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io21.chip2pad = s_reg2hw.pad_io21_cfg.chip2pad.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io22 + always_comb begin + unique case (s_reg2hw.pad_io22_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_DEFAULT: begin + mux_to_pads_o.pad_io22.chip2pad = s_reg2hw.pad_io22_cfg.chip2pad.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_GPIO_GPIO22: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.gpio.gpio22_out; + mux_to_pads_o.pad_io22.rx_en = ~port_signals_soc2pad_i.gpio.gpio22_tx_en; + mux_to_pads_o.pad_io22.tx_en = port_signals_soc2pad_i.gpio.gpio22_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io22.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io22.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io22.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io22.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_UART0_RX: begin + mux_to_pads_o.pad_io22.chip2pad = 1'b1; + mux_to_pads_o.pad_io22.rx_en = 1'b1; + mux_to_pads_o.pad_io22.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_UART0_TX: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io22.rx_en = 1'b0; + mux_to_pads_o.pad_io22.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io22.rx_en = 1'b0; + mux_to_pads_o.pad_io22.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io22.rx_en = 1'b0; + mux_to_pads_o.pad_io22.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io22.rx_en = 1'b0; + mux_to_pads_o.pad_io22.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io22.rx_en = 1'b0; + mux_to_pads_o.pad_io22.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io22.rx_en = 1'b0; + mux_to_pads_o.pad_io22.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io22.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io22.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io22.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io22.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io22.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io22.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io22.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io22.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io22.chip2pad = 1'b0; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io22.chip2pad = 1'b0; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io22.chip2pad = 1'b0; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io22.chip2pad = 1'b0; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io22.chip2pad = 1'b0; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io22.chip2pad = 1'b0; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io22.chip2pad = 1'b0; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io22.chip2pad = 1'b0; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io22.chip2pad = 1'b0; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io22.chip2pad = 1'b0; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io22.chip2pad = 1'b0; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io22.chip2pad = 1'b0; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io22.chip2pad = 1'b0; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io22.rx_en = 1'b0; + mux_to_pads_o.pad_io22.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io22.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io22.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io22.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io22.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io22.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io22.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io22.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io22.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io22.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io22.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io22.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io22.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io22.rx_en = 1'b0; + mux_to_pads_o.pad_io22.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io22.rx_en = 1'b0; + mux_to_pads_o.pad_io22.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io22.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io22.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io22.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io22.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io22.chip2pad = s_reg2hw.pad_io22_cfg.chip2pad.q; + mux_to_pads_o.pad_io22.rx_en = 1'b1; + mux_to_pads_o.pad_io22.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io22.chip2pad = s_reg2hw.pad_io22_cfg.chip2pad.q; + mux_to_pads_o.pad_io22.rx_en = 1'b1; + mux_to_pads_o.pad_io22.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io22.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io22.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io22.chip2pad = s_reg2hw.pad_io22_cfg.chip2pad.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io23 + always_comb begin + unique case (s_reg2hw.pad_io23_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_DEFAULT: begin + mux_to_pads_o.pad_io23.chip2pad = s_reg2hw.pad_io23_cfg.chip2pad.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_GPIO_GPIO23: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.gpio.gpio23_out; + mux_to_pads_o.pad_io23.rx_en = ~port_signals_soc2pad_i.gpio.gpio23_tx_en; + mux_to_pads_o.pad_io23.tx_en = port_signals_soc2pad_i.gpio.gpio23_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io23.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io23.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io23.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io23.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_UART0_RX: begin + mux_to_pads_o.pad_io23.chip2pad = 1'b1; + mux_to_pads_o.pad_io23.rx_en = 1'b1; + mux_to_pads_o.pad_io23.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_UART0_TX: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io23.rx_en = 1'b0; + mux_to_pads_o.pad_io23.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io23.rx_en = 1'b0; + mux_to_pads_o.pad_io23.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io23.rx_en = 1'b0; + mux_to_pads_o.pad_io23.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io23.rx_en = 1'b0; + mux_to_pads_o.pad_io23.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io23.rx_en = 1'b0; + mux_to_pads_o.pad_io23.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io23.rx_en = 1'b0; + mux_to_pads_o.pad_io23.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io23.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io23.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io23.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io23.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io23.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io23.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io23.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io23.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io23.chip2pad = 1'b0; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io23.chip2pad = 1'b0; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io23.chip2pad = 1'b0; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io23.chip2pad = 1'b0; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io23.chip2pad = 1'b0; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io23.chip2pad = 1'b0; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io23.chip2pad = 1'b0; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io23.chip2pad = 1'b0; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io23.chip2pad = 1'b0; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io23.chip2pad = 1'b0; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io23.chip2pad = 1'b0; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io23.chip2pad = 1'b0; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io23.chip2pad = 1'b0; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io23.rx_en = 1'b0; + mux_to_pads_o.pad_io23.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io23.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io23.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io23.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io23.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io23.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io23.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io23.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io23.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io23.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io23.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io23.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io23.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io23.rx_en = 1'b0; + mux_to_pads_o.pad_io23.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io23.rx_en = 1'b0; + mux_to_pads_o.pad_io23.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io23.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io23.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io23.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io23.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io23.chip2pad = s_reg2hw.pad_io23_cfg.chip2pad.q; + mux_to_pads_o.pad_io23.rx_en = 1'b1; + mux_to_pads_o.pad_io23.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io23.chip2pad = s_reg2hw.pad_io23_cfg.chip2pad.q; + mux_to_pads_o.pad_io23.rx_en = 1'b1; + mux_to_pads_o.pad_io23.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io23.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io23.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io23.chip2pad = s_reg2hw.pad_io23_cfg.chip2pad.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io24 + always_comb begin + unique case (s_reg2hw.pad_io24_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_DEFAULT: begin + mux_to_pads_o.pad_io24.chip2pad = s_reg2hw.pad_io24_cfg.chip2pad.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_GPIO_GPIO24: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.gpio.gpio24_out; + mux_to_pads_o.pad_io24.rx_en = ~port_signals_soc2pad_i.gpio.gpio24_tx_en; + mux_to_pads_o.pad_io24.tx_en = port_signals_soc2pad_i.gpio.gpio24_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io24.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io24.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io24.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io24.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_UART0_RX: begin + mux_to_pads_o.pad_io24.chip2pad = 1'b1; + mux_to_pads_o.pad_io24.rx_en = 1'b1; + mux_to_pads_o.pad_io24.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_UART0_TX: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io24.rx_en = 1'b0; + mux_to_pads_o.pad_io24.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io24.rx_en = 1'b0; + mux_to_pads_o.pad_io24.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io24.rx_en = 1'b0; + mux_to_pads_o.pad_io24.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io24.rx_en = 1'b0; + mux_to_pads_o.pad_io24.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io24.rx_en = 1'b0; + mux_to_pads_o.pad_io24.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io24.rx_en = 1'b0; + mux_to_pads_o.pad_io24.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io24.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io24.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io24.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io24.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io24.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io24.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io24.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io24.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io24.chip2pad = 1'b0; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io24.chip2pad = 1'b0; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io24.chip2pad = 1'b0; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io24.chip2pad = 1'b0; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io24.chip2pad = 1'b0; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io24.chip2pad = 1'b0; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io24.chip2pad = 1'b0; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io24.chip2pad = 1'b0; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io24.chip2pad = 1'b0; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io24.chip2pad = 1'b0; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io24.chip2pad = 1'b0; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io24.chip2pad = 1'b0; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io24.chip2pad = 1'b0; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io24.rx_en = 1'b0; + mux_to_pads_o.pad_io24.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io24.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io24.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io24.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io24.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io24.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io24.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io24.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io24.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io24.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io24.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io24.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io24.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io24.rx_en = 1'b0; + mux_to_pads_o.pad_io24.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io24.rx_en = 1'b0; + mux_to_pads_o.pad_io24.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io24.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io24.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io24.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io24.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io24.chip2pad = s_reg2hw.pad_io24_cfg.chip2pad.q; + mux_to_pads_o.pad_io24.rx_en = 1'b1; + mux_to_pads_o.pad_io24.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io24.chip2pad = s_reg2hw.pad_io24_cfg.chip2pad.q; + mux_to_pads_o.pad_io24.rx_en = 1'b1; + mux_to_pads_o.pad_io24.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io24.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io24.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io24.chip2pad = s_reg2hw.pad_io24_cfg.chip2pad.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io25 + always_comb begin + unique case (s_reg2hw.pad_io25_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_DEFAULT: begin + mux_to_pads_o.pad_io25.chip2pad = s_reg2hw.pad_io25_cfg.chip2pad.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_GPIO_GPIO25: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.gpio.gpio25_out; + mux_to_pads_o.pad_io25.rx_en = ~port_signals_soc2pad_i.gpio.gpio25_tx_en; + mux_to_pads_o.pad_io25.tx_en = port_signals_soc2pad_i.gpio.gpio25_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io25.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io25.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io25.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io25.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_UART0_RX: begin + mux_to_pads_o.pad_io25.chip2pad = 1'b1; + mux_to_pads_o.pad_io25.rx_en = 1'b1; + mux_to_pads_o.pad_io25.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_UART0_TX: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io25.rx_en = 1'b0; + mux_to_pads_o.pad_io25.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io25.rx_en = 1'b0; + mux_to_pads_o.pad_io25.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io25.rx_en = 1'b0; + mux_to_pads_o.pad_io25.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io25.rx_en = 1'b0; + mux_to_pads_o.pad_io25.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io25.rx_en = 1'b0; + mux_to_pads_o.pad_io25.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io25.rx_en = 1'b0; + mux_to_pads_o.pad_io25.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io25.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io25.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io25.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io25.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io25.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io25.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io25.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io25.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io25.chip2pad = 1'b0; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io25.chip2pad = 1'b0; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io25.chip2pad = 1'b0; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io25.chip2pad = 1'b0; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io25.chip2pad = 1'b0; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io25.chip2pad = 1'b0; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io25.chip2pad = 1'b0; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io25.chip2pad = 1'b0; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io25.chip2pad = 1'b0; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io25.chip2pad = 1'b0; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io25.chip2pad = 1'b0; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io25.chip2pad = 1'b0; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io25.chip2pad = 1'b0; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io25.rx_en = 1'b0; + mux_to_pads_o.pad_io25.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io25.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io25.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io25.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io25.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io25.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io25.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io25.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io25.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io25.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io25.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io25.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io25.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io25.rx_en = 1'b0; + mux_to_pads_o.pad_io25.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io25.rx_en = 1'b0; + mux_to_pads_o.pad_io25.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io25.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io25.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io25.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io25.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io25.chip2pad = s_reg2hw.pad_io25_cfg.chip2pad.q; + mux_to_pads_o.pad_io25.rx_en = 1'b1; + mux_to_pads_o.pad_io25.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io25.chip2pad = s_reg2hw.pad_io25_cfg.chip2pad.q; + mux_to_pads_o.pad_io25.rx_en = 1'b1; + mux_to_pads_o.pad_io25.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io25.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io25.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io25.chip2pad = s_reg2hw.pad_io25_cfg.chip2pad.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io26 + always_comb begin + unique case (s_reg2hw.pad_io26_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_DEFAULT: begin + mux_to_pads_o.pad_io26.chip2pad = s_reg2hw.pad_io26_cfg.chip2pad.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_GPIO_GPIO26: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.gpio.gpio26_out; + mux_to_pads_o.pad_io26.rx_en = ~port_signals_soc2pad_i.gpio.gpio26_tx_en; + mux_to_pads_o.pad_io26.tx_en = port_signals_soc2pad_i.gpio.gpio26_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io26.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io26.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io26.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io26.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_UART0_RX: begin + mux_to_pads_o.pad_io26.chip2pad = 1'b1; + mux_to_pads_o.pad_io26.rx_en = 1'b1; + mux_to_pads_o.pad_io26.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_UART0_TX: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io26.rx_en = 1'b0; + mux_to_pads_o.pad_io26.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io26.rx_en = 1'b0; + mux_to_pads_o.pad_io26.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io26.rx_en = 1'b0; + mux_to_pads_o.pad_io26.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io26.rx_en = 1'b0; + mux_to_pads_o.pad_io26.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io26.rx_en = 1'b0; + mux_to_pads_o.pad_io26.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io26.rx_en = 1'b0; + mux_to_pads_o.pad_io26.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io26.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io26.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io26.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io26.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io26.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io26.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io26.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io26.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io26.chip2pad = 1'b0; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io26.chip2pad = 1'b0; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io26.chip2pad = 1'b0; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io26.chip2pad = 1'b0; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io26.chip2pad = 1'b0; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io26.chip2pad = 1'b0; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io26.chip2pad = 1'b0; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io26.chip2pad = 1'b0; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io26.chip2pad = 1'b0; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io26.chip2pad = 1'b0; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io26.chip2pad = 1'b0; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io26.chip2pad = 1'b0; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io26.chip2pad = 1'b0; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io26.rx_en = 1'b0; + mux_to_pads_o.pad_io26.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io26.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io26.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io26.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io26.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io26.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io26.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io26.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io26.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io26.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io26.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io26.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io26.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io26.rx_en = 1'b0; + mux_to_pads_o.pad_io26.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io26.rx_en = 1'b0; + mux_to_pads_o.pad_io26.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io26.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io26.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io26.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io26.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io26.chip2pad = s_reg2hw.pad_io26_cfg.chip2pad.q; + mux_to_pads_o.pad_io26.rx_en = 1'b1; + mux_to_pads_o.pad_io26.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io26.chip2pad = s_reg2hw.pad_io26_cfg.chip2pad.q; + mux_to_pads_o.pad_io26.rx_en = 1'b1; + mux_to_pads_o.pad_io26.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io26.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io26.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io26.chip2pad = s_reg2hw.pad_io26_cfg.chip2pad.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io27 + always_comb begin + unique case (s_reg2hw.pad_io27_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_DEFAULT: begin + mux_to_pads_o.pad_io27.chip2pad = s_reg2hw.pad_io27_cfg.chip2pad.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_GPIO_GPIO27: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.gpio.gpio27_out; + mux_to_pads_o.pad_io27.rx_en = ~port_signals_soc2pad_i.gpio.gpio27_tx_en; + mux_to_pads_o.pad_io27.tx_en = port_signals_soc2pad_i.gpio.gpio27_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io27.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io27.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io27.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io27.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_UART0_RX: begin + mux_to_pads_o.pad_io27.chip2pad = 1'b1; + mux_to_pads_o.pad_io27.rx_en = 1'b1; + mux_to_pads_o.pad_io27.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_UART0_TX: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io27.rx_en = 1'b0; + mux_to_pads_o.pad_io27.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io27.rx_en = 1'b0; + mux_to_pads_o.pad_io27.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io27.rx_en = 1'b0; + mux_to_pads_o.pad_io27.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io27.rx_en = 1'b0; + mux_to_pads_o.pad_io27.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io27.rx_en = 1'b0; + mux_to_pads_o.pad_io27.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io27.rx_en = 1'b0; + mux_to_pads_o.pad_io27.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io27.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io27.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io27.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io27.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io27.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io27.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io27.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io27.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io27.chip2pad = 1'b0; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io27.chip2pad = 1'b0; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io27.chip2pad = 1'b0; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io27.chip2pad = 1'b0; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io27.chip2pad = 1'b0; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io27.chip2pad = 1'b0; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io27.chip2pad = 1'b0; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io27.chip2pad = 1'b0; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io27.chip2pad = 1'b0; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io27.chip2pad = 1'b0; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io27.chip2pad = 1'b0; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io27.chip2pad = 1'b0; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io27.chip2pad = 1'b0; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io27.rx_en = 1'b0; + mux_to_pads_o.pad_io27.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io27.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io27.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io27.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io27.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io27.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io27.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io27.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io27.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io27.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io27.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io27.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io27.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io27.rx_en = 1'b0; + mux_to_pads_o.pad_io27.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io27.rx_en = 1'b0; + mux_to_pads_o.pad_io27.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io27.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io27.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io27.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io27.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io27.chip2pad = s_reg2hw.pad_io27_cfg.chip2pad.q; + mux_to_pads_o.pad_io27.rx_en = 1'b1; + mux_to_pads_o.pad_io27.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io27.chip2pad = s_reg2hw.pad_io27_cfg.chip2pad.q; + mux_to_pads_o.pad_io27.rx_en = 1'b1; + mux_to_pads_o.pad_io27.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io27.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io27.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io27.chip2pad = s_reg2hw.pad_io27_cfg.chip2pad.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io28 + always_comb begin + unique case (s_reg2hw.pad_io28_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_DEFAULT: begin + mux_to_pads_o.pad_io28.chip2pad = s_reg2hw.pad_io28_cfg.chip2pad.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_GPIO_GPIO28: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.gpio.gpio28_out; + mux_to_pads_o.pad_io28.rx_en = ~port_signals_soc2pad_i.gpio.gpio28_tx_en; + mux_to_pads_o.pad_io28.tx_en = port_signals_soc2pad_i.gpio.gpio28_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io28.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io28.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io28.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io28.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_UART0_RX: begin + mux_to_pads_o.pad_io28.chip2pad = 1'b1; + mux_to_pads_o.pad_io28.rx_en = 1'b1; + mux_to_pads_o.pad_io28.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_UART0_TX: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io28.rx_en = 1'b0; + mux_to_pads_o.pad_io28.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io28.rx_en = 1'b0; + mux_to_pads_o.pad_io28.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io28.rx_en = 1'b0; + mux_to_pads_o.pad_io28.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io28.rx_en = 1'b0; + mux_to_pads_o.pad_io28.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io28.rx_en = 1'b0; + mux_to_pads_o.pad_io28.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io28.rx_en = 1'b0; + mux_to_pads_o.pad_io28.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io28.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io28.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io28.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io28.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io28.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io28.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io28.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io28.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io28.chip2pad = 1'b0; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io28.chip2pad = 1'b0; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io28.chip2pad = 1'b0; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io28.chip2pad = 1'b0; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io28.chip2pad = 1'b0; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io28.chip2pad = 1'b0; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io28.chip2pad = 1'b0; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io28.chip2pad = 1'b0; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io28.chip2pad = 1'b0; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io28.chip2pad = 1'b0; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io28.chip2pad = 1'b0; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io28.chip2pad = 1'b0; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io28.chip2pad = 1'b0; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io28.rx_en = 1'b0; + mux_to_pads_o.pad_io28.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io28.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io28.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io28.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io28.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io28.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io28.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io28.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io28.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io28.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io28.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io28.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io28.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io28.rx_en = 1'b0; + mux_to_pads_o.pad_io28.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io28.rx_en = 1'b0; + mux_to_pads_o.pad_io28.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io28.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io28.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io28.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io28.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io28.chip2pad = s_reg2hw.pad_io28_cfg.chip2pad.q; + mux_to_pads_o.pad_io28.rx_en = 1'b1; + mux_to_pads_o.pad_io28.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io28.chip2pad = s_reg2hw.pad_io28_cfg.chip2pad.q; + mux_to_pads_o.pad_io28.rx_en = 1'b1; + mux_to_pads_o.pad_io28.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io28.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io28.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io28.chip2pad = s_reg2hw.pad_io28_cfg.chip2pad.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io29 + always_comb begin + unique case (s_reg2hw.pad_io29_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_DEFAULT: begin + mux_to_pads_o.pad_io29.chip2pad = s_reg2hw.pad_io29_cfg.chip2pad.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_GPIO_GPIO29: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.gpio.gpio29_out; + mux_to_pads_o.pad_io29.rx_en = ~port_signals_soc2pad_i.gpio.gpio29_tx_en; + mux_to_pads_o.pad_io29.tx_en = port_signals_soc2pad_i.gpio.gpio29_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io29.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io29.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io29.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io29.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_UART0_RX: begin + mux_to_pads_o.pad_io29.chip2pad = 1'b1; + mux_to_pads_o.pad_io29.rx_en = 1'b1; + mux_to_pads_o.pad_io29.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_UART0_TX: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io29.rx_en = 1'b0; + mux_to_pads_o.pad_io29.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io29.rx_en = 1'b0; + mux_to_pads_o.pad_io29.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io29.rx_en = 1'b0; + mux_to_pads_o.pad_io29.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io29.rx_en = 1'b0; + mux_to_pads_o.pad_io29.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io29.rx_en = 1'b0; + mux_to_pads_o.pad_io29.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io29.rx_en = 1'b0; + mux_to_pads_o.pad_io29.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io29.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io29.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io29.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io29.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io29.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io29.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io29.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io29.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io29.chip2pad = 1'b0; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io29.chip2pad = 1'b0; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io29.chip2pad = 1'b0; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io29.chip2pad = 1'b0; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io29.chip2pad = 1'b0; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io29.chip2pad = 1'b0; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io29.chip2pad = 1'b0; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io29.chip2pad = 1'b0; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io29.chip2pad = 1'b0; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io29.chip2pad = 1'b0; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io29.chip2pad = 1'b0; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io29.chip2pad = 1'b0; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io29.chip2pad = 1'b0; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io29.rx_en = 1'b0; + mux_to_pads_o.pad_io29.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io29.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io29.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io29.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io29.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io29.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io29.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io29.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io29.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io29.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io29.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io29.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io29.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io29.rx_en = 1'b0; + mux_to_pads_o.pad_io29.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io29.rx_en = 1'b0; + mux_to_pads_o.pad_io29.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io29.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io29.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io29.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io29.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io29.chip2pad = s_reg2hw.pad_io29_cfg.chip2pad.q; + mux_to_pads_o.pad_io29.rx_en = 1'b1; + mux_to_pads_o.pad_io29.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io29.chip2pad = s_reg2hw.pad_io29_cfg.chip2pad.q; + mux_to_pads_o.pad_io29.rx_en = 1'b1; + mux_to_pads_o.pad_io29.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io29.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io29.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io29.chip2pad = s_reg2hw.pad_io29_cfg.chip2pad.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io30 + always_comb begin + unique case (s_reg2hw.pad_io30_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_DEFAULT: begin + mux_to_pads_o.pad_io30.chip2pad = s_reg2hw.pad_io30_cfg.chip2pad.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_GPIO_GPIO30: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.gpio.gpio30_out; + mux_to_pads_o.pad_io30.rx_en = ~port_signals_soc2pad_i.gpio.gpio30_tx_en; + mux_to_pads_o.pad_io30.tx_en = port_signals_soc2pad_i.gpio.gpio30_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io30.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io30.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io30.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io30.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_UART0_RX: begin + mux_to_pads_o.pad_io30.chip2pad = 1'b1; + mux_to_pads_o.pad_io30.rx_en = 1'b1; + mux_to_pads_o.pad_io30.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_UART0_TX: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io30.rx_en = 1'b0; + mux_to_pads_o.pad_io30.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io30.rx_en = 1'b0; + mux_to_pads_o.pad_io30.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io30.rx_en = 1'b0; + mux_to_pads_o.pad_io30.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io30.rx_en = 1'b0; + mux_to_pads_o.pad_io30.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io30.rx_en = 1'b0; + mux_to_pads_o.pad_io30.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io30.rx_en = 1'b0; + mux_to_pads_o.pad_io30.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io30.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io30.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io30.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io30.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io30.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io30.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io30.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io30.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io30.chip2pad = 1'b0; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io30.chip2pad = 1'b0; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io30.chip2pad = 1'b0; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io30.chip2pad = 1'b0; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io30.chip2pad = 1'b0; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io30.chip2pad = 1'b0; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io30.chip2pad = 1'b0; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io30.chip2pad = 1'b0; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io30.chip2pad = 1'b0; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io30.chip2pad = 1'b0; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io30.chip2pad = 1'b0; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io30.chip2pad = 1'b0; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io30.chip2pad = 1'b0; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io30.rx_en = 1'b0; + mux_to_pads_o.pad_io30.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io30.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io30.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io30.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io30.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io30.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io30.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io30.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io30.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io30.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io30.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io30.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io30.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io30.rx_en = 1'b0; + mux_to_pads_o.pad_io30.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io30.rx_en = 1'b0; + mux_to_pads_o.pad_io30.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io30.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io30.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io30.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io30.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io30.chip2pad = s_reg2hw.pad_io30_cfg.chip2pad.q; + mux_to_pads_o.pad_io30.rx_en = 1'b1; + mux_to_pads_o.pad_io30.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io30.chip2pad = s_reg2hw.pad_io30_cfg.chip2pad.q; + mux_to_pads_o.pad_io30.rx_en = 1'b1; + mux_to_pads_o.pad_io30.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io30.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io30.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io30.chip2pad = s_reg2hw.pad_io30_cfg.chip2pad.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io31 + always_comb begin + unique case (s_reg2hw.pad_io31_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_DEFAULT: begin + mux_to_pads_o.pad_io31.chip2pad = s_reg2hw.pad_io31_cfg.chip2pad.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_GPIO_GPIO31: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.gpio.gpio31_out; + mux_to_pads_o.pad_io31.rx_en = ~port_signals_soc2pad_i.gpio.gpio31_tx_en; + mux_to_pads_o.pad_io31.tx_en = port_signals_soc2pad_i.gpio.gpio31_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io31.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io31.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io31.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io31.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_UART0_RX: begin + mux_to_pads_o.pad_io31.chip2pad = 1'b1; + mux_to_pads_o.pad_io31.rx_en = 1'b1; + mux_to_pads_o.pad_io31.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_UART0_TX: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io31.rx_en = 1'b0; + mux_to_pads_o.pad_io31.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io31.rx_en = 1'b0; + mux_to_pads_o.pad_io31.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io31.rx_en = 1'b0; + mux_to_pads_o.pad_io31.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io31.rx_en = 1'b0; + mux_to_pads_o.pad_io31.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io31.rx_en = 1'b0; + mux_to_pads_o.pad_io31.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io31.rx_en = 1'b0; + mux_to_pads_o.pad_io31.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io31.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io31.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io31.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io31.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io31.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io31.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io31.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io31.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io31.chip2pad = 1'b0; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io31.chip2pad = 1'b0; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io31.chip2pad = 1'b0; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io31.chip2pad = 1'b0; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io31.chip2pad = 1'b0; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io31.chip2pad = 1'b0; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io31.chip2pad = 1'b0; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io31.chip2pad = 1'b0; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io31.chip2pad = 1'b0; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io31.chip2pad = 1'b0; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io31.chip2pad = 1'b0; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io31.chip2pad = 1'b0; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io31.chip2pad = 1'b0; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io31.rx_en = 1'b0; + mux_to_pads_o.pad_io31.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io31.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io31.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io31.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io31.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io31.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io31.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io31.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io31.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io31.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io31.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io31.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io31.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io31.rx_en = 1'b0; + mux_to_pads_o.pad_io31.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io31.rx_en = 1'b0; + mux_to_pads_o.pad_io31.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io31.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io31.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io31.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io31.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io31.chip2pad = s_reg2hw.pad_io31_cfg.chip2pad.q; + mux_to_pads_o.pad_io31.rx_en = 1'b1; + mux_to_pads_o.pad_io31.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io31.chip2pad = s_reg2hw.pad_io31_cfg.chip2pad.q; + mux_to_pads_o.pad_io31.rx_en = 1'b1; + mux_to_pads_o.pad_io31.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io31.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io31.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io31.chip2pad = s_reg2hw.pad_io31_cfg.chip2pad.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + endcase + end // always_comb + + + // Pad -> SoC Multiplex Logic + // Port Group gpio + + // Port Signal gpio00_in + logic [0:0] port_mux_sel_gpio_gpio00_in_req; + logic [PORT_MUX_GROUP_PAD_IO00_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio00_in_arbitrated; + logic port_mux_sel_gpio_gpio00_in_no_connection; + + assign port_mux_sel_gpio_gpio00_in_req[PORT_MUX_GROUP_PAD_IO00_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_GPIO_GPIO00 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio00_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio00_in_req), + .cnt_o(port_mux_sel_gpio_gpio00_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio00_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio00_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio00_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio00_in_arbitrated) + PORT_MUX_GROUP_PAD_IO00_SEL_PAD_IO00: begin + port_signals_pad2soc_o.gpio.gpio00_in = pads_to_mux_i.pad_io00.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio00_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio01_in + logic [0:0] port_mux_sel_gpio_gpio01_in_req; + logic [PORT_MUX_GROUP_PAD_IO01_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio01_in_arbitrated; + logic port_mux_sel_gpio_gpio01_in_no_connection; + + assign port_mux_sel_gpio_gpio01_in_req[PORT_MUX_GROUP_PAD_IO01_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_GPIO_GPIO01 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio01_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio01_in_req), + .cnt_o(port_mux_sel_gpio_gpio01_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio01_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio01_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio01_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio01_in_arbitrated) + PORT_MUX_GROUP_PAD_IO01_SEL_PAD_IO01: begin + port_signals_pad2soc_o.gpio.gpio01_in = pads_to_mux_i.pad_io01.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio01_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio02_in + logic [0:0] port_mux_sel_gpio_gpio02_in_req; + logic [PORT_MUX_GROUP_PAD_IO02_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio02_in_arbitrated; + logic port_mux_sel_gpio_gpio02_in_no_connection; + + assign port_mux_sel_gpio_gpio02_in_req[PORT_MUX_GROUP_PAD_IO02_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_GPIO_GPIO02 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio02_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio02_in_req), + .cnt_o(port_mux_sel_gpio_gpio02_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio02_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio02_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio02_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio02_in_arbitrated) + PORT_MUX_GROUP_PAD_IO02_SEL_PAD_IO02: begin + port_signals_pad2soc_o.gpio.gpio02_in = pads_to_mux_i.pad_io02.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio02_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio03_in + logic [0:0] port_mux_sel_gpio_gpio03_in_req; + logic [PORT_MUX_GROUP_PAD_IO03_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio03_in_arbitrated; + logic port_mux_sel_gpio_gpio03_in_no_connection; + + assign port_mux_sel_gpio_gpio03_in_req[PORT_MUX_GROUP_PAD_IO03_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_GPIO_GPIO03 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio03_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio03_in_req), + .cnt_o(port_mux_sel_gpio_gpio03_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio03_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio03_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio03_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio03_in_arbitrated) + PORT_MUX_GROUP_PAD_IO03_SEL_PAD_IO03: begin + port_signals_pad2soc_o.gpio.gpio03_in = pads_to_mux_i.pad_io03.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio03_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio04_in + logic [0:0] port_mux_sel_gpio_gpio04_in_req; + logic [PORT_MUX_GROUP_PAD_IO04_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio04_in_arbitrated; + logic port_mux_sel_gpio_gpio04_in_no_connection; + + assign port_mux_sel_gpio_gpio04_in_req[PORT_MUX_GROUP_PAD_IO04_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_GPIO_GPIO04 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio04_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio04_in_req), + .cnt_o(port_mux_sel_gpio_gpio04_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio04_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio04_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio04_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio04_in_arbitrated) + PORT_MUX_GROUP_PAD_IO04_SEL_PAD_IO04: begin + port_signals_pad2soc_o.gpio.gpio04_in = pads_to_mux_i.pad_io04.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio04_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio05_in + logic [0:0] port_mux_sel_gpio_gpio05_in_req; + logic [PORT_MUX_GROUP_PAD_IO05_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio05_in_arbitrated; + logic port_mux_sel_gpio_gpio05_in_no_connection; + + assign port_mux_sel_gpio_gpio05_in_req[PORT_MUX_GROUP_PAD_IO05_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_GPIO_GPIO05 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio05_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio05_in_req), + .cnt_o(port_mux_sel_gpio_gpio05_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio05_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio05_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio05_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio05_in_arbitrated) + PORT_MUX_GROUP_PAD_IO05_SEL_PAD_IO05: begin + port_signals_pad2soc_o.gpio.gpio05_in = pads_to_mux_i.pad_io05.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio05_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio06_in + logic [0:0] port_mux_sel_gpio_gpio06_in_req; + logic [PORT_MUX_GROUP_PAD_IO06_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio06_in_arbitrated; + logic port_mux_sel_gpio_gpio06_in_no_connection; + + assign port_mux_sel_gpio_gpio06_in_req[PORT_MUX_GROUP_PAD_IO06_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_GPIO_GPIO06 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio06_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio06_in_req), + .cnt_o(port_mux_sel_gpio_gpio06_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio06_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio06_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio06_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio06_in_arbitrated) + PORT_MUX_GROUP_PAD_IO06_SEL_PAD_IO06: begin + port_signals_pad2soc_o.gpio.gpio06_in = pads_to_mux_i.pad_io06.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio06_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio07_in + logic [0:0] port_mux_sel_gpio_gpio07_in_req; + logic [PORT_MUX_GROUP_PAD_IO07_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio07_in_arbitrated; + logic port_mux_sel_gpio_gpio07_in_no_connection; + + assign port_mux_sel_gpio_gpio07_in_req[PORT_MUX_GROUP_PAD_IO07_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_GPIO_GPIO07 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio07_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio07_in_req), + .cnt_o(port_mux_sel_gpio_gpio07_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio07_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio07_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio07_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio07_in_arbitrated) + PORT_MUX_GROUP_PAD_IO07_SEL_PAD_IO07: begin + port_signals_pad2soc_o.gpio.gpio07_in = pads_to_mux_i.pad_io07.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio07_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio08_in + logic [0:0] port_mux_sel_gpio_gpio08_in_req; + logic [PORT_MUX_GROUP_PAD_IO08_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio08_in_arbitrated; + logic port_mux_sel_gpio_gpio08_in_no_connection; + + assign port_mux_sel_gpio_gpio08_in_req[PORT_MUX_GROUP_PAD_IO08_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_GPIO_GPIO08 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio08_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio08_in_req), + .cnt_o(port_mux_sel_gpio_gpio08_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio08_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio08_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio08_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio08_in_arbitrated) + PORT_MUX_GROUP_PAD_IO08_SEL_PAD_IO08: begin + port_signals_pad2soc_o.gpio.gpio08_in = pads_to_mux_i.pad_io08.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio08_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio09_in + logic [0:0] port_mux_sel_gpio_gpio09_in_req; + logic [PORT_MUX_GROUP_PAD_IO09_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio09_in_arbitrated; + logic port_mux_sel_gpio_gpio09_in_no_connection; + + assign port_mux_sel_gpio_gpio09_in_req[PORT_MUX_GROUP_PAD_IO09_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_GPIO_GPIO09 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio09_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio09_in_req), + .cnt_o(port_mux_sel_gpio_gpio09_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio09_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio09_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio09_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio09_in_arbitrated) + PORT_MUX_GROUP_PAD_IO09_SEL_PAD_IO09: begin + port_signals_pad2soc_o.gpio.gpio09_in = pads_to_mux_i.pad_io09.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio09_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio10_in + logic [0:0] port_mux_sel_gpio_gpio10_in_req; + logic [PORT_MUX_GROUP_PAD_IO10_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio10_in_arbitrated; + logic port_mux_sel_gpio_gpio10_in_no_connection; + + assign port_mux_sel_gpio_gpio10_in_req[PORT_MUX_GROUP_PAD_IO10_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_GPIO_GPIO10 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio10_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio10_in_req), + .cnt_o(port_mux_sel_gpio_gpio10_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio10_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio10_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio10_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio10_in_arbitrated) + PORT_MUX_GROUP_PAD_IO10_SEL_PAD_IO10: begin + port_signals_pad2soc_o.gpio.gpio10_in = pads_to_mux_i.pad_io10.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio10_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio11_in + logic [0:0] port_mux_sel_gpio_gpio11_in_req; + logic [PORT_MUX_GROUP_PAD_IO11_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio11_in_arbitrated; + logic port_mux_sel_gpio_gpio11_in_no_connection; + + assign port_mux_sel_gpio_gpio11_in_req[PORT_MUX_GROUP_PAD_IO11_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_GPIO_GPIO11 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio11_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio11_in_req), + .cnt_o(port_mux_sel_gpio_gpio11_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio11_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio11_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio11_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio11_in_arbitrated) + PORT_MUX_GROUP_PAD_IO11_SEL_PAD_IO11: begin + port_signals_pad2soc_o.gpio.gpio11_in = pads_to_mux_i.pad_io11.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio11_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio12_in + logic [0:0] port_mux_sel_gpio_gpio12_in_req; + logic [PORT_MUX_GROUP_PAD_IO12_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio12_in_arbitrated; + logic port_mux_sel_gpio_gpio12_in_no_connection; + + assign port_mux_sel_gpio_gpio12_in_req[PORT_MUX_GROUP_PAD_IO12_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_GPIO_GPIO12 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio12_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio12_in_req), + .cnt_o(port_mux_sel_gpio_gpio12_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio12_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio12_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio12_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio12_in_arbitrated) + PORT_MUX_GROUP_PAD_IO12_SEL_PAD_IO12: begin + port_signals_pad2soc_o.gpio.gpio12_in = pads_to_mux_i.pad_io12.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio12_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio13_in + logic [0:0] port_mux_sel_gpio_gpio13_in_req; + logic [PORT_MUX_GROUP_PAD_IO13_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio13_in_arbitrated; + logic port_mux_sel_gpio_gpio13_in_no_connection; + + assign port_mux_sel_gpio_gpio13_in_req[PORT_MUX_GROUP_PAD_IO13_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_GPIO_GPIO13 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio13_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio13_in_req), + .cnt_o(port_mux_sel_gpio_gpio13_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio13_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio13_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio13_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio13_in_arbitrated) + PORT_MUX_GROUP_PAD_IO13_SEL_PAD_IO13: begin + port_signals_pad2soc_o.gpio.gpio13_in = pads_to_mux_i.pad_io13.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio13_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio14_in + logic [0:0] port_mux_sel_gpio_gpio14_in_req; + logic [PORT_MUX_GROUP_PAD_IO14_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio14_in_arbitrated; + logic port_mux_sel_gpio_gpio14_in_no_connection; + + assign port_mux_sel_gpio_gpio14_in_req[PORT_MUX_GROUP_PAD_IO14_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_GPIO_GPIO14 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio14_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio14_in_req), + .cnt_o(port_mux_sel_gpio_gpio14_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio14_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio14_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio14_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio14_in_arbitrated) + PORT_MUX_GROUP_PAD_IO14_SEL_PAD_IO14: begin + port_signals_pad2soc_o.gpio.gpio14_in = pads_to_mux_i.pad_io14.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio14_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio15_in + logic [0:0] port_mux_sel_gpio_gpio15_in_req; + logic [PORT_MUX_GROUP_PAD_IO15_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio15_in_arbitrated; + logic port_mux_sel_gpio_gpio15_in_no_connection; + + assign port_mux_sel_gpio_gpio15_in_req[PORT_MUX_GROUP_PAD_IO15_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_GPIO_GPIO15 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio15_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio15_in_req), + .cnt_o(port_mux_sel_gpio_gpio15_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio15_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio15_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio15_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio15_in_arbitrated) + PORT_MUX_GROUP_PAD_IO15_SEL_PAD_IO15: begin + port_signals_pad2soc_o.gpio.gpio15_in = pads_to_mux_i.pad_io15.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio15_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio16_in + logic [0:0] port_mux_sel_gpio_gpio16_in_req; + logic [PORT_MUX_GROUP_PAD_IO16_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio16_in_arbitrated; + logic port_mux_sel_gpio_gpio16_in_no_connection; + + assign port_mux_sel_gpio_gpio16_in_req[PORT_MUX_GROUP_PAD_IO16_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_GPIO_GPIO16 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio16_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio16_in_req), + .cnt_o(port_mux_sel_gpio_gpio16_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio16_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio16_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio16_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio16_in_arbitrated) + PORT_MUX_GROUP_PAD_IO16_SEL_PAD_IO16: begin + port_signals_pad2soc_o.gpio.gpio16_in = pads_to_mux_i.pad_io16.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio16_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio17_in + logic [0:0] port_mux_sel_gpio_gpio17_in_req; + logic [PORT_MUX_GROUP_PAD_IO17_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio17_in_arbitrated; + logic port_mux_sel_gpio_gpio17_in_no_connection; + + assign port_mux_sel_gpio_gpio17_in_req[PORT_MUX_GROUP_PAD_IO17_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_GPIO_GPIO17 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio17_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio17_in_req), + .cnt_o(port_mux_sel_gpio_gpio17_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio17_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio17_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio17_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio17_in_arbitrated) + PORT_MUX_GROUP_PAD_IO17_SEL_PAD_IO17: begin + port_signals_pad2soc_o.gpio.gpio17_in = pads_to_mux_i.pad_io17.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio17_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio18_in + logic [0:0] port_mux_sel_gpio_gpio18_in_req; + logic [PORT_MUX_GROUP_PAD_IO18_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio18_in_arbitrated; + logic port_mux_sel_gpio_gpio18_in_no_connection; + + assign port_mux_sel_gpio_gpio18_in_req[PORT_MUX_GROUP_PAD_IO18_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_GPIO_GPIO18 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio18_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio18_in_req), + .cnt_o(port_mux_sel_gpio_gpio18_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio18_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio18_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio18_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio18_in_arbitrated) + PORT_MUX_GROUP_PAD_IO18_SEL_PAD_IO18: begin + port_signals_pad2soc_o.gpio.gpio18_in = pads_to_mux_i.pad_io18.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio18_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio19_in + logic [0:0] port_mux_sel_gpio_gpio19_in_req; + logic [PORT_MUX_GROUP_PAD_IO19_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio19_in_arbitrated; + logic port_mux_sel_gpio_gpio19_in_no_connection; + + assign port_mux_sel_gpio_gpio19_in_req[PORT_MUX_GROUP_PAD_IO19_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_GPIO_GPIO19 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio19_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio19_in_req), + .cnt_o(port_mux_sel_gpio_gpio19_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio19_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio19_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio19_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio19_in_arbitrated) + PORT_MUX_GROUP_PAD_IO19_SEL_PAD_IO19: begin + port_signals_pad2soc_o.gpio.gpio19_in = pads_to_mux_i.pad_io19.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio19_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio20_in + logic [0:0] port_mux_sel_gpio_gpio20_in_req; + logic [PORT_MUX_GROUP_PAD_IO20_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio20_in_arbitrated; + logic port_mux_sel_gpio_gpio20_in_no_connection; + + assign port_mux_sel_gpio_gpio20_in_req[PORT_MUX_GROUP_PAD_IO20_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_GPIO_GPIO20 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio20_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio20_in_req), + .cnt_o(port_mux_sel_gpio_gpio20_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio20_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio20_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio20_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio20_in_arbitrated) + PORT_MUX_GROUP_PAD_IO20_SEL_PAD_IO20: begin + port_signals_pad2soc_o.gpio.gpio20_in = pads_to_mux_i.pad_io20.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio20_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio21_in + logic [0:0] port_mux_sel_gpio_gpio21_in_req; + logic [PORT_MUX_GROUP_PAD_IO21_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio21_in_arbitrated; + logic port_mux_sel_gpio_gpio21_in_no_connection; + + assign port_mux_sel_gpio_gpio21_in_req[PORT_MUX_GROUP_PAD_IO21_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_GPIO_GPIO21 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio21_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio21_in_req), + .cnt_o(port_mux_sel_gpio_gpio21_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio21_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio21_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio21_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio21_in_arbitrated) + PORT_MUX_GROUP_PAD_IO21_SEL_PAD_IO21: begin + port_signals_pad2soc_o.gpio.gpio21_in = pads_to_mux_i.pad_io21.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio21_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio22_in + logic [0:0] port_mux_sel_gpio_gpio22_in_req; + logic [PORT_MUX_GROUP_PAD_IO22_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio22_in_arbitrated; + logic port_mux_sel_gpio_gpio22_in_no_connection; + + assign port_mux_sel_gpio_gpio22_in_req[PORT_MUX_GROUP_PAD_IO22_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_GPIO_GPIO22 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio22_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio22_in_req), + .cnt_o(port_mux_sel_gpio_gpio22_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio22_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio22_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio22_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio22_in_arbitrated) + PORT_MUX_GROUP_PAD_IO22_SEL_PAD_IO22: begin + port_signals_pad2soc_o.gpio.gpio22_in = pads_to_mux_i.pad_io22.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio22_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio23_in + logic [0:0] port_mux_sel_gpio_gpio23_in_req; + logic [PORT_MUX_GROUP_PAD_IO23_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio23_in_arbitrated; + logic port_mux_sel_gpio_gpio23_in_no_connection; + + assign port_mux_sel_gpio_gpio23_in_req[PORT_MUX_GROUP_PAD_IO23_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_GPIO_GPIO23 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio23_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio23_in_req), + .cnt_o(port_mux_sel_gpio_gpio23_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio23_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio23_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio23_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio23_in_arbitrated) + PORT_MUX_GROUP_PAD_IO23_SEL_PAD_IO23: begin + port_signals_pad2soc_o.gpio.gpio23_in = pads_to_mux_i.pad_io23.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio23_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio24_in + logic [0:0] port_mux_sel_gpio_gpio24_in_req; + logic [PORT_MUX_GROUP_PAD_IO24_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio24_in_arbitrated; + logic port_mux_sel_gpio_gpio24_in_no_connection; + + assign port_mux_sel_gpio_gpio24_in_req[PORT_MUX_GROUP_PAD_IO24_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_GPIO_GPIO24 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio24_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio24_in_req), + .cnt_o(port_mux_sel_gpio_gpio24_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio24_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio24_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio24_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio24_in_arbitrated) + PORT_MUX_GROUP_PAD_IO24_SEL_PAD_IO24: begin + port_signals_pad2soc_o.gpio.gpio24_in = pads_to_mux_i.pad_io24.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio24_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio25_in + logic [0:0] port_mux_sel_gpio_gpio25_in_req; + logic [PORT_MUX_GROUP_PAD_IO25_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio25_in_arbitrated; + logic port_mux_sel_gpio_gpio25_in_no_connection; + + assign port_mux_sel_gpio_gpio25_in_req[PORT_MUX_GROUP_PAD_IO25_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_GPIO_GPIO25 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio25_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio25_in_req), + .cnt_o(port_mux_sel_gpio_gpio25_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio25_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio25_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio25_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio25_in_arbitrated) + PORT_MUX_GROUP_PAD_IO25_SEL_PAD_IO25: begin + port_signals_pad2soc_o.gpio.gpio25_in = pads_to_mux_i.pad_io25.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio25_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio26_in + logic [0:0] port_mux_sel_gpio_gpio26_in_req; + logic [PORT_MUX_GROUP_PAD_IO26_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio26_in_arbitrated; + logic port_mux_sel_gpio_gpio26_in_no_connection; + + assign port_mux_sel_gpio_gpio26_in_req[PORT_MUX_GROUP_PAD_IO26_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_GPIO_GPIO26 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio26_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio26_in_req), + .cnt_o(port_mux_sel_gpio_gpio26_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio26_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio26_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio26_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio26_in_arbitrated) + PORT_MUX_GROUP_PAD_IO26_SEL_PAD_IO26: begin + port_signals_pad2soc_o.gpio.gpio26_in = pads_to_mux_i.pad_io26.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio26_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio27_in + logic [0:0] port_mux_sel_gpio_gpio27_in_req; + logic [PORT_MUX_GROUP_PAD_IO27_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio27_in_arbitrated; + logic port_mux_sel_gpio_gpio27_in_no_connection; + + assign port_mux_sel_gpio_gpio27_in_req[PORT_MUX_GROUP_PAD_IO27_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_GPIO_GPIO27 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio27_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio27_in_req), + .cnt_o(port_mux_sel_gpio_gpio27_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio27_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio27_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio27_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio27_in_arbitrated) + PORT_MUX_GROUP_PAD_IO27_SEL_PAD_IO27: begin + port_signals_pad2soc_o.gpio.gpio27_in = pads_to_mux_i.pad_io27.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio27_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio28_in + logic [0:0] port_mux_sel_gpio_gpio28_in_req; + logic [PORT_MUX_GROUP_PAD_IO28_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio28_in_arbitrated; + logic port_mux_sel_gpio_gpio28_in_no_connection; + + assign port_mux_sel_gpio_gpio28_in_req[PORT_MUX_GROUP_PAD_IO28_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_GPIO_GPIO28 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio28_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio28_in_req), + .cnt_o(port_mux_sel_gpio_gpio28_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio28_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio28_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio28_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio28_in_arbitrated) + PORT_MUX_GROUP_PAD_IO28_SEL_PAD_IO28: begin + port_signals_pad2soc_o.gpio.gpio28_in = pads_to_mux_i.pad_io28.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio28_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio29_in + logic [0:0] port_mux_sel_gpio_gpio29_in_req; + logic [PORT_MUX_GROUP_PAD_IO29_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio29_in_arbitrated; + logic port_mux_sel_gpio_gpio29_in_no_connection; + + assign port_mux_sel_gpio_gpio29_in_req[PORT_MUX_GROUP_PAD_IO29_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_GPIO_GPIO29 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio29_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio29_in_req), + .cnt_o(port_mux_sel_gpio_gpio29_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio29_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio29_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio29_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio29_in_arbitrated) + PORT_MUX_GROUP_PAD_IO29_SEL_PAD_IO29: begin + port_signals_pad2soc_o.gpio.gpio29_in = pads_to_mux_i.pad_io29.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio29_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio30_in + logic [0:0] port_mux_sel_gpio_gpio30_in_req; + logic [PORT_MUX_GROUP_PAD_IO30_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio30_in_arbitrated; + logic port_mux_sel_gpio_gpio30_in_no_connection; + + assign port_mux_sel_gpio_gpio30_in_req[PORT_MUX_GROUP_PAD_IO30_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_GPIO_GPIO30 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio30_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio30_in_req), + .cnt_o(port_mux_sel_gpio_gpio30_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio30_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio30_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio30_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio30_in_arbitrated) + PORT_MUX_GROUP_PAD_IO30_SEL_PAD_IO30: begin + port_signals_pad2soc_o.gpio.gpio30_in = pads_to_mux_i.pad_io30.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio30_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio31_in + logic [0:0] port_mux_sel_gpio_gpio31_in_req; + logic [PORT_MUX_GROUP_PAD_IO31_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio31_in_arbitrated; + logic port_mux_sel_gpio_gpio31_in_no_connection; + + assign port_mux_sel_gpio_gpio31_in_req[PORT_MUX_GROUP_PAD_IO31_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_GPIO_GPIO31 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio31_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio31_in_req), + .cnt_o(port_mux_sel_gpio_gpio31_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio31_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio31_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio31_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio31_in_arbitrated) + PORT_MUX_GROUP_PAD_IO31_SEL_PAD_IO31: begin + port_signals_pad2soc_o.gpio.gpio31_in = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio31_in = 1'b0; + end + endcase + end + end + + // Port Group i2c0 + + // Port Signal sda_i + logic [31:0] port_mux_sel_i2c0_sda_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_i2c0_sda_i_arbitrated; + logic port_mux_sel_i2c0_sda_i_no_connection; + + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2C0_SDA ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_i2c0_sda_i_arbiter ( + .in_i(port_mux_sel_i2c0_sda_i_req), + .cnt_o(port_mux_sel_i2c0_sda_i_arbitrated), + .empty_o(port_mux_sel_i2c0_sda_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_i2c0_sda_i_no_connection) begin + port_signals_pad2soc_o.i2c0.sda_i = 1'b1; + end else begin + unique case (port_mux_sel_i2c0_sda_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.i2c0.sda_i = 1'b1; + end + endcase + end + end + + + // Port Signal scl_i + logic [31:0] port_mux_sel_i2c0_scl_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_i2c0_scl_i_arbitrated; + logic port_mux_sel_i2c0_scl_i_no_connection; + + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2C0_SCL ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_i2c0_scl_i_arbiter ( + .in_i(port_mux_sel_i2c0_scl_i_req), + .cnt_o(port_mux_sel_i2c0_scl_i_arbitrated), + .empty_o(port_mux_sel_i2c0_scl_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_i2c0_scl_i_no_connection) begin + port_signals_pad2soc_o.i2c0.scl_i = 1'b1; + end else begin + unique case (port_mux_sel_i2c0_scl_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.i2c0.scl_i = 1'b1; + end + endcase + end + end + + // Port Group uart0 + + // Port Signal rx_i + logic [31:0] port_mux_sel_uart0_rx_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_uart0_rx_i_arbitrated; + logic port_mux_sel_uart0_rx_i_no_connection; + + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_UART0_RX ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_uart0_rx_i_arbiter ( + .in_i(port_mux_sel_uart0_rx_i_req), + .cnt_o(port_mux_sel_uart0_rx_i_arbitrated), + .empty_o(port_mux_sel_uart0_rx_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_uart0_rx_i_no_connection) begin + port_signals_pad2soc_o.uart0.rx_i = 1'b1; + end else begin + unique case (port_mux_sel_uart0_rx_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.uart0.rx_i = 1'b1; + end + endcase + end + end + + + // Port Group qspim0 + + // Port Signal sd0_i + logic [31:0] port_mux_sel_qspim0_sd0_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_qspim0_sd0_i_arbitrated; + logic port_mux_sel_qspim0_sd0_i_no_connection; + + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_qspim0_sd0_i_arbiter ( + .in_i(port_mux_sel_qspim0_sd0_i_req), + .cnt_o(port_mux_sel_qspim0_sd0_i_arbitrated), + .empty_o(port_mux_sel_qspim0_sd0_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_qspim0_sd0_i_no_connection) begin + port_signals_pad2soc_o.qspim0.sd0_i = 1'b0; + end else begin + unique case (port_mux_sel_qspim0_sd0_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.qspim0.sd0_i = 1'b0; + end + endcase + end + end + + + // Port Signal sd1_i + logic [31:0] port_mux_sel_qspim0_sd1_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_qspim0_sd1_i_arbitrated; + logic port_mux_sel_qspim0_sd1_i_no_connection; + + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_qspim0_sd1_i_arbiter ( + .in_i(port_mux_sel_qspim0_sd1_i_req), + .cnt_o(port_mux_sel_qspim0_sd1_i_arbitrated), + .empty_o(port_mux_sel_qspim0_sd1_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_qspim0_sd1_i_no_connection) begin + port_signals_pad2soc_o.qspim0.sd1_i = 1'b0; + end else begin + unique case (port_mux_sel_qspim0_sd1_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.qspim0.sd1_i = 1'b0; + end + endcase + end + end + + + // Port Signal sd2_i + logic [31:0] port_mux_sel_qspim0_sd2_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_qspim0_sd2_i_arbitrated; + logic port_mux_sel_qspim0_sd2_i_no_connection; + + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_qspim0_sd2_i_arbiter ( + .in_i(port_mux_sel_qspim0_sd2_i_req), + .cnt_o(port_mux_sel_qspim0_sd2_i_arbitrated), + .empty_o(port_mux_sel_qspim0_sd2_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_qspim0_sd2_i_no_connection) begin + port_signals_pad2soc_o.qspim0.sd2_i = 1'b0; + end else begin + unique case (port_mux_sel_qspim0_sd2_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.qspim0.sd2_i = 1'b0; + end + endcase + end + end + + + // Port Signal sd3_i + logic [31:0] port_mux_sel_qspim0_sd3_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_qspim0_sd3_i_arbitrated; + logic port_mux_sel_qspim0_sd3_i_no_connection; + + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_qspim0_sd3_i_arbiter ( + .in_i(port_mux_sel_qspim0_sd3_i_req), + .cnt_o(port_mux_sel_qspim0_sd3_i_arbitrated), + .empty_o(port_mux_sel_qspim0_sd3_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_qspim0_sd3_i_no_connection) begin + port_signals_pad2soc_o.qspim0.sd3_i = 1'b0; + end else begin + unique case (port_mux_sel_qspim0_sd3_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.qspim0.sd3_i = 1'b0; + end + endcase + end + end + + + + + + + // Port Group cpi0 + + // Port Signal pclk_i + logic [31:0] port_mux_sel_cpi0_pclk_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_cpi0_pclk_i_arbitrated; + logic port_mux_sel_cpi0_pclk_i_no_connection; + + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_cpi0_pclk_i_arbiter ( + .in_i(port_mux_sel_cpi0_pclk_i_req), + .cnt_o(port_mux_sel_cpi0_pclk_i_arbitrated), + .empty_o(port_mux_sel_cpi0_pclk_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_cpi0_pclk_i_no_connection) begin + port_signals_pad2soc_o.cpi0.pclk_i = 1'b0; + end else begin + unique case (port_mux_sel_cpi0_pclk_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.cpi0.pclk_i = 1'b0; + end + endcase + end + end + + + // Port Signal hsync_i + logic [31:0] port_mux_sel_cpi0_hsync_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_cpi0_hsync_i_arbitrated; + logic port_mux_sel_cpi0_hsync_i_no_connection; + + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_cpi0_hsync_i_arbiter ( + .in_i(port_mux_sel_cpi0_hsync_i_req), + .cnt_o(port_mux_sel_cpi0_hsync_i_arbitrated), + .empty_o(port_mux_sel_cpi0_hsync_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_cpi0_hsync_i_no_connection) begin + port_signals_pad2soc_o.cpi0.hsync_i = 1'b0; + end else begin + unique case (port_mux_sel_cpi0_hsync_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.cpi0.hsync_i = 1'b0; + end + endcase + end + end + + + // Port Signal vsync_i + logic [31:0] port_mux_sel_cpi0_vsync_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_cpi0_vsync_i_arbitrated; + logic port_mux_sel_cpi0_vsync_i_no_connection; + + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_cpi0_vsync_i_arbiter ( + .in_i(port_mux_sel_cpi0_vsync_i_req), + .cnt_o(port_mux_sel_cpi0_vsync_i_arbitrated), + .empty_o(port_mux_sel_cpi0_vsync_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_cpi0_vsync_i_no_connection) begin + port_signals_pad2soc_o.cpi0.vsync_i = 1'b0; + end else begin + unique case (port_mux_sel_cpi0_vsync_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.cpi0.vsync_i = 1'b0; + end + endcase + end + end + + + // Port Signal data0_i + logic [31:0] port_mux_sel_cpi0_data0_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_cpi0_data0_i_arbitrated; + logic port_mux_sel_cpi0_data0_i_no_connection; + + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_cpi0_data0_i_arbiter ( + .in_i(port_mux_sel_cpi0_data0_i_req), + .cnt_o(port_mux_sel_cpi0_data0_i_arbitrated), + .empty_o(port_mux_sel_cpi0_data0_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_cpi0_data0_i_no_connection) begin + port_signals_pad2soc_o.cpi0.data0_i = 1'b0; + end else begin + unique case (port_mux_sel_cpi0_data0_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.cpi0.data0_i = 1'b0; + end + endcase + end + end + + + // Port Signal data1_i + logic [31:0] port_mux_sel_cpi0_data1_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_cpi0_data1_i_arbitrated; + logic port_mux_sel_cpi0_data1_i_no_connection; + + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_cpi0_data1_i_arbiter ( + .in_i(port_mux_sel_cpi0_data1_i_req), + .cnt_o(port_mux_sel_cpi0_data1_i_arbitrated), + .empty_o(port_mux_sel_cpi0_data1_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_cpi0_data1_i_no_connection) begin + port_signals_pad2soc_o.cpi0.data1_i = 1'b0; + end else begin + unique case (port_mux_sel_cpi0_data1_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.cpi0.data1_i = 1'b0; + end + endcase + end + end + + + // Port Signal data2_i + logic [31:0] port_mux_sel_cpi0_data2_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_cpi0_data2_i_arbitrated; + logic port_mux_sel_cpi0_data2_i_no_connection; + + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_cpi0_data2_i_arbiter ( + .in_i(port_mux_sel_cpi0_data2_i_req), + .cnt_o(port_mux_sel_cpi0_data2_i_arbitrated), + .empty_o(port_mux_sel_cpi0_data2_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_cpi0_data2_i_no_connection) begin + port_signals_pad2soc_o.cpi0.data2_i = 1'b0; + end else begin + unique case (port_mux_sel_cpi0_data2_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.cpi0.data2_i = 1'b0; + end + endcase + end + end + + + // Port Signal data3_i + logic [31:0] port_mux_sel_cpi0_data3_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_cpi0_data3_i_arbitrated; + logic port_mux_sel_cpi0_data3_i_no_connection; + + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_cpi0_data3_i_arbiter ( + .in_i(port_mux_sel_cpi0_data3_i_req), + .cnt_o(port_mux_sel_cpi0_data3_i_arbitrated), + .empty_o(port_mux_sel_cpi0_data3_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_cpi0_data3_i_no_connection) begin + port_signals_pad2soc_o.cpi0.data3_i = 1'b0; + end else begin + unique case (port_mux_sel_cpi0_data3_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.cpi0.data3_i = 1'b0; + end + endcase + end + end + + + // Port Signal data4_i + logic [31:0] port_mux_sel_cpi0_data4_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_cpi0_data4_i_arbitrated; + logic port_mux_sel_cpi0_data4_i_no_connection; + + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_cpi0_data4_i_arbiter ( + .in_i(port_mux_sel_cpi0_data4_i_req), + .cnt_o(port_mux_sel_cpi0_data4_i_arbitrated), + .empty_o(port_mux_sel_cpi0_data4_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_cpi0_data4_i_no_connection) begin + port_signals_pad2soc_o.cpi0.data4_i = 1'b0; + end else begin + unique case (port_mux_sel_cpi0_data4_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.cpi0.data4_i = 1'b0; + end + endcase + end + end + + + // Port Signal data5_i + logic [31:0] port_mux_sel_cpi0_data5_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_cpi0_data5_i_arbitrated; + logic port_mux_sel_cpi0_data5_i_no_connection; + + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_cpi0_data5_i_arbiter ( + .in_i(port_mux_sel_cpi0_data5_i_req), + .cnt_o(port_mux_sel_cpi0_data5_i_arbitrated), + .empty_o(port_mux_sel_cpi0_data5_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_cpi0_data5_i_no_connection) begin + port_signals_pad2soc_o.cpi0.data5_i = 1'b0; + end else begin + unique case (port_mux_sel_cpi0_data5_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.cpi0.data5_i = 1'b0; + end + endcase + end + end + + + // Port Signal data6_i + logic [31:0] port_mux_sel_cpi0_data6_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_cpi0_data6_i_arbitrated; + logic port_mux_sel_cpi0_data6_i_no_connection; + + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_cpi0_data6_i_arbiter ( + .in_i(port_mux_sel_cpi0_data6_i_req), + .cnt_o(port_mux_sel_cpi0_data6_i_arbitrated), + .empty_o(port_mux_sel_cpi0_data6_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_cpi0_data6_i_no_connection) begin + port_signals_pad2soc_o.cpi0.data6_i = 1'b0; + end else begin + unique case (port_mux_sel_cpi0_data6_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.cpi0.data6_i = 1'b0; + end + endcase + end + end + + + // Port Signal data7_i + logic [31:0] port_mux_sel_cpi0_data7_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_cpi0_data7_i_arbitrated; + logic port_mux_sel_cpi0_data7_i_no_connection; + + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_cpi0_data7_i_arbiter ( + .in_i(port_mux_sel_cpi0_data7_i_req), + .cnt_o(port_mux_sel_cpi0_data7_i_arbitrated), + .empty_o(port_mux_sel_cpi0_data7_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_cpi0_data7_i_no_connection) begin + port_signals_pad2soc_o.cpi0.data7_i = 1'b0; + end else begin + unique case (port_mux_sel_cpi0_data7_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.cpi0.data7_i = 1'b0; + end + endcase + end + end + + + // Port Signal data8_i + logic [31:0] port_mux_sel_cpi0_data8_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_cpi0_data8_i_arbitrated; + logic port_mux_sel_cpi0_data8_i_no_connection; + + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_cpi0_data8_i_arbiter ( + .in_i(port_mux_sel_cpi0_data8_i_req), + .cnt_o(port_mux_sel_cpi0_data8_i_arbitrated), + .empty_o(port_mux_sel_cpi0_data8_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_cpi0_data8_i_no_connection) begin + port_signals_pad2soc_o.cpi0.data8_i = 1'b0; + end else begin + unique case (port_mux_sel_cpi0_data8_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.cpi0.data8_i = 1'b0; + end + endcase + end + end + + + // Port Signal data9_i + logic [31:0] port_mux_sel_cpi0_data9_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_cpi0_data9_i_arbitrated; + logic port_mux_sel_cpi0_data9_i_no_connection; + + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_cpi0_data9_i_arbiter ( + .in_i(port_mux_sel_cpi0_data9_i_req), + .cnt_o(port_mux_sel_cpi0_data9_i_arbitrated), + .empty_o(port_mux_sel_cpi0_data9_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_cpi0_data9_i_no_connection) begin + port_signals_pad2soc_o.cpi0.data9_i = 1'b0; + end else begin + unique case (port_mux_sel_cpi0_data9_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.cpi0.data9_i = 1'b0; + end + endcase + end + end + + // Port Group sdio0 + + + // Port Signal sdcmd_in + logic [31:0] port_mux_sel_sdio0_sdcmd_in_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_sdio0_sdcmd_in_arbitrated; + logic port_mux_sel_sdio0_sdcmd_in_no_connection; + + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_sdio0_sdcmd_in_arbiter ( + .in_i(port_mux_sel_sdio0_sdcmd_in_req), + .cnt_o(port_mux_sel_sdio0_sdcmd_in_arbitrated), + .empty_o(port_mux_sel_sdio0_sdcmd_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_sdio0_sdcmd_in_no_connection) begin + port_signals_pad2soc_o.sdio0.sdcmd_in = 1'b0; + end else begin + unique case (port_mux_sel_sdio0_sdcmd_in_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = 1'b0; + end + endcase + end + end + + + // Port Signal sddata0_in + logic [31:0] port_mux_sel_sdio0_sddata0_in_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_sdio0_sddata0_in_arbitrated; + logic port_mux_sel_sdio0_sddata0_in_no_connection; + + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_sdio0_sddata0_in_arbiter ( + .in_i(port_mux_sel_sdio0_sddata0_in_req), + .cnt_o(port_mux_sel_sdio0_sddata0_in_arbitrated), + .empty_o(port_mux_sel_sdio0_sddata0_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_sdio0_sddata0_in_no_connection) begin + port_signals_pad2soc_o.sdio0.sddata0_in = 1'b0; + end else begin + unique case (port_mux_sel_sdio0_sddata0_in_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.sdio0.sddata0_in = 1'b0; + end + endcase + end + end + + + // Port Signal sddata1_in + logic [31:0] port_mux_sel_sdio0_sddata1_in_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_sdio0_sddata1_in_arbitrated; + logic port_mux_sel_sdio0_sddata1_in_no_connection; + + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_sdio0_sddata1_in_arbiter ( + .in_i(port_mux_sel_sdio0_sddata1_in_req), + .cnt_o(port_mux_sel_sdio0_sddata1_in_arbitrated), + .empty_o(port_mux_sel_sdio0_sddata1_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_sdio0_sddata1_in_no_connection) begin + port_signals_pad2soc_o.sdio0.sddata1_in = 1'b0; + end else begin + unique case (port_mux_sel_sdio0_sddata1_in_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.sdio0.sddata1_in = 1'b0; + end + endcase + end + end + + + // Port Signal sddata2_in + logic [31:0] port_mux_sel_sdio0_sddata2_in_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_sdio0_sddata2_in_arbitrated; + logic port_mux_sel_sdio0_sddata2_in_no_connection; + + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_sdio0_sddata2_in_arbiter ( + .in_i(port_mux_sel_sdio0_sddata2_in_req), + .cnt_o(port_mux_sel_sdio0_sddata2_in_arbitrated), + .empty_o(port_mux_sel_sdio0_sddata2_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_sdio0_sddata2_in_no_connection) begin + port_signals_pad2soc_o.sdio0.sddata2_in = 1'b0; + end else begin + unique case (port_mux_sel_sdio0_sddata2_in_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.sdio0.sddata2_in = 1'b0; + end + endcase + end + end + + + // Port Signal sddata3_in + logic [31:0] port_mux_sel_sdio0_sddata3_in_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_sdio0_sddata3_in_arbitrated; + logic port_mux_sel_sdio0_sddata3_in_no_connection; + + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_sdio0_sddata3_in_arbiter ( + .in_i(port_mux_sel_sdio0_sddata3_in_req), + .cnt_o(port_mux_sel_sdio0_sddata3_in_arbitrated), + .empty_o(port_mux_sel_sdio0_sddata3_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_sdio0_sddata3_in_no_connection) begin + port_signals_pad2soc_o.sdio0.sddata3_in = 1'b0; + end else begin + unique case (port_mux_sel_sdio0_sddata3_in_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.sdio0.sddata3_in = 1'b0; + end + endcase + end + end + + // Port Group i2s0 + + // Port Signal master_sck_in + logic [31:0] port_mux_sel_i2s0_master_sck_in_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_i2s0_master_sck_in_arbitrated; + logic port_mux_sel_i2s0_master_sck_in_no_connection; + + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_i2s0_master_sck_in_arbiter ( + .in_i(port_mux_sel_i2s0_master_sck_in_req), + .cnt_o(port_mux_sel_i2s0_master_sck_in_arbitrated), + .empty_o(port_mux_sel_i2s0_master_sck_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_i2s0_master_sck_in_no_connection) begin + port_signals_pad2soc_o.i2s0.master_sck_in = 1'b0; + end else begin + unique case (port_mux_sel_i2s0_master_sck_in_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.i2s0.master_sck_in = 1'b0; + end + endcase + end + end + + + // Port Signal master_ws_in + logic [31:0] port_mux_sel_i2s0_master_ws_in_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_i2s0_master_ws_in_arbitrated; + logic port_mux_sel_i2s0_master_ws_in_no_connection; + + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_i2s0_master_ws_in_arbiter ( + .in_i(port_mux_sel_i2s0_master_ws_in_req), + .cnt_o(port_mux_sel_i2s0_master_ws_in_arbitrated), + .empty_o(port_mux_sel_i2s0_master_ws_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_i2s0_master_ws_in_no_connection) begin + port_signals_pad2soc_o.i2s0.master_ws_in = 1'b0; + end else begin + unique case (port_mux_sel_i2s0_master_ws_in_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.i2s0.master_ws_in = 1'b0; + end + endcase + end + end + + + + + // Port Signal slave_sck_in + logic [31:0] port_mux_sel_i2s0_slave_sck_in_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_i2s0_slave_sck_in_arbitrated; + logic port_mux_sel_i2s0_slave_sck_in_no_connection; + + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_i2s0_slave_sck_in_arbiter ( + .in_i(port_mux_sel_i2s0_slave_sck_in_req), + .cnt_o(port_mux_sel_i2s0_slave_sck_in_arbitrated), + .empty_o(port_mux_sel_i2s0_slave_sck_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_i2s0_slave_sck_in_no_connection) begin + port_signals_pad2soc_o.i2s0.slave_sck_in = 1'b0; + end else begin + unique case (port_mux_sel_i2s0_slave_sck_in_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = 1'b0; + end + endcase + end + end + + + // Port Signal slave_ws_in + logic [31:0] port_mux_sel_i2s0_slave_ws_in_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_i2s0_slave_ws_in_arbitrated; + logic port_mux_sel_i2s0_slave_ws_in_no_connection; + + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_i2s0_slave_ws_in_arbiter ( + .in_i(port_mux_sel_i2s0_slave_ws_in_req), + .cnt_o(port_mux_sel_i2s0_slave_ws_in_arbitrated), + .empty_o(port_mux_sel_i2s0_slave_ws_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_i2s0_slave_ws_in_no_connection) begin + port_signals_pad2soc_o.i2s0.slave_ws_in = 1'b0; + end else begin + unique case (port_mux_sel_i2s0_slave_ws_in_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = 1'b0; + end + endcase + end + end + + + // Port Signal slave_sd0_in + logic [31:0] port_mux_sel_i2s0_slave_sd0_in_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_i2s0_slave_sd0_in_arbitrated; + logic port_mux_sel_i2s0_slave_sd0_in_no_connection; + + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_i2s0_slave_sd0_in_arbiter ( + .in_i(port_mux_sel_i2s0_slave_sd0_in_req), + .cnt_o(port_mux_sel_i2s0_slave_sd0_in_arbitrated), + .empty_o(port_mux_sel_i2s0_slave_sd0_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_i2s0_slave_sd0_in_no_connection) begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = 1'b0; + end else begin + unique case (port_mux_sel_i2s0_slave_sd0_in_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = 1'b0; + end + endcase + end + end + + + // Port Signal slave_sd1_in + logic [31:0] port_mux_sel_i2s0_slave_sd1_in_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_i2s0_slave_sd1_in_arbitrated; + logic port_mux_sel_i2s0_slave_sd1_in_no_connection; + + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_i2s0_slave_sd1_in_arbiter ( + .in_i(port_mux_sel_i2s0_slave_sd1_in_req), + .cnt_o(port_mux_sel_i2s0_slave_sd1_in_arbitrated), + .empty_o(port_mux_sel_i2s0_slave_sd1_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_i2s0_slave_sd1_in_no_connection) begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = 1'b0; + end else begin + unique case (port_mux_sel_i2s0_slave_sd1_in_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = 1'b0; + end + endcase + end + end + +endmodule : pulpissimo_padframe_all_pads_muxer diff --git a/hw/padframe/pulpissimo_padframe_fpga_autogen/src/pulpissimo_padframe_all_pads_pads.sv b/hw/padframe/pulpissimo_padframe_fpga_autogen/src/pulpissimo_padframe_all_pads_pads.sv new file mode 100644 index 00000000..71d0cf1e --- /dev/null +++ b/hw/padframe/pulpissimo_padframe_fpga_autogen/src/pulpissimo_padframe_all_pads_pads.sv @@ -0,0 +1,447 @@ + +// File auto-generated by Padrick unknown +module pulpissimo_padframe_all_pads_pads + import pkg_pulpissimo_padframe::*; + import pkg_internal_pulpissimo_padframe_all_pads::*; +( + output pad_domain_all_pads_static_connection_signals_pad2soc_t static_connection_signals_pad2soc, + input pad_domain_all_pads_static_connection_signals_soc2pad_t static_connection_signals_soc2pad, + // Dynamic Pad control signals, these signals are controlled by the multiplexer in the correpsongin pad_controller module + input mux_to_pads_t mux_to_pads_i, + output pads_to_mux_t pads_to_mux_o, + // Landing Pads + inout wire logic pad_pad_ref_clk_pad, + inout wire logic pad_pad_clk_byp_en_pad, + inout wire logic pad_pad_reset_n_pad, + inout wire logic pad_pad_bootsel0_pad, + inout wire logic pad_pad_bootsel1_pad, + inout wire logic pad_pad_jtag_tck_pad, + inout wire logic pad_pad_jtag_trstn_pad, + inout wire logic pad_pad_jtag_tms_pad, + inout wire logic pad_pad_jtag_tdi_pad, + inout wire logic pad_pad_jtag_tdo_pad, + inout wire logic pad_pad_hyper_csn0_pad, + inout wire logic pad_pad_hyper_csn1_pad, + inout wire logic pad_pad_hyper_reset_n_pad, + inout wire logic pad_pad_hyper_ck_pad, + inout wire logic pad_pad_hyper_ckn_pad, + inout wire logic pad_pad_hyper_dq0_pad, + inout wire logic pad_pad_hyper_dq1_pad, + inout wire logic pad_pad_hyper_dq2_pad, + inout wire logic pad_pad_hyper_dq3_pad, + inout wire logic pad_pad_hyper_dq4_pad, + inout wire logic pad_pad_hyper_dq5_pad, + inout wire logic pad_pad_hyper_dq6_pad, + inout wire logic pad_pad_hyper_dq7_pad, + inout wire logic pad_pad_hyper_rwds_pad, + inout wire logic pad_pad_io00_pad, + inout wire logic pad_pad_io01_pad, + inout wire logic pad_pad_io02_pad, + inout wire logic pad_pad_io03_pad, + inout wire logic pad_pad_io04_pad, + inout wire logic pad_pad_io05_pad, + inout wire logic pad_pad_io06_pad, + inout wire logic pad_pad_io07_pad, + inout wire logic pad_pad_io08_pad, + inout wire logic pad_pad_io09_pad, + inout wire logic pad_pad_io10_pad, + inout wire logic pad_pad_io11_pad, + inout wire logic pad_pad_io12_pad, + inout wire logic pad_pad_io13_pad, + inout wire logic pad_pad_io14_pad, + inout wire logic pad_pad_io15_pad, + inout wire logic pad_pad_io16_pad, + inout wire logic pad_pad_io17_pad, + inout wire logic pad_pad_io18_pad, + inout wire logic pad_pad_io19_pad, + inout wire logic pad_pad_io20_pad, + inout wire logic pad_pad_io21_pad, + inout wire logic pad_pad_io22_pad, + inout wire logic pad_pad_io23_pad, + inout wire logic pad_pad_io24_pad, + inout wire logic pad_pad_io25_pad, + inout wire logic pad_pad_io26_pad, + inout wire logic pad_pad_io27_pad, + inout wire logic pad_pad_io28_pad, + inout wire logic pad_pad_io29_pad, + inout wire logic pad_pad_io30_pad, + inout wire logic pad_pad_io31_pad + ); + + // Pad instantiations + assign static_connection_signals_pad2soc.ref_clk = pad_pad_ref_clk_pad; + assign static_connection_signals_pad2soc.clk_byp_en = pad_pad_clk_byp_en_pad; + assign static_connection_signals_pad2soc.rst_n = pad_pad_reset_n_pad; + (* PULLUP = "YES" *) + IOBUF i_pad_bootsel0 ( + .T ( ~1'b0 ), + .I ( 1'b0 ), + .O ( static_connection_signals_pad2soc.bootsel0 ), + .IO( pad_pad_bootsel0_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_bootsel1 ( + .T ( ~1'b0 ), + .I ( 1'b0 ), + .O ( static_connection_signals_pad2soc.bootsel1 ), + .IO( pad_pad_bootsel1_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_jtag_tck ( + .T ( ~1'b0 ), + .I ( 1'b0 ), + .O ( static_connection_signals_pad2soc.jtag_tck ), + .IO( pad_pad_jtag_tck_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_jtag_trstn ( + .T ( ~1'b0 ), + .I ( 1'b0 ), + .O ( static_connection_signals_pad2soc.jtag_trstn ), + .IO( pad_pad_jtag_trstn_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_jtag_tms ( + .T ( ~1'b0 ), + .I ( 1'b0 ), + .O ( static_connection_signals_pad2soc.jtag_tms ), + .IO( pad_pad_jtag_tms_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_jtag_tdi ( + .T ( ~1'b0 ), + .I ( 1'b0 ), + .O ( static_connection_signals_pad2soc.jtag_tdi ), + .IO( pad_pad_jtag_tdi_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_jtag_tdo ( + .T ( ~1'b1 ), + .I ( static_connection_signals_soc2pad.jtag_tdo ), + .O ( ), + .IO( pad_pad_jtag_tdo_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_hyper_csn0 ( + .T ( ~1'b1 ), + .I ( static_connection_signals_soc2pad.hyper_cs0_no ), + .O ( ), + .IO( pad_pad_hyper_csn0_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_hyper_csn1 ( + .T ( ~1'b1 ), + .I ( static_connection_signals_soc2pad.hyper_cs1_no ), + .O ( ), + .IO( pad_pad_hyper_csn1_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_hyper_reset_n ( + .T ( ~1'b1 ), + .I ( static_connection_signals_soc2pad.hyper_reset_no ), + .O ( ), + .IO( pad_pad_hyper_reset_n_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_hyper_ck ( + .T ( ~1'b1 ), + .I ( static_connection_signals_soc2pad.hyper_ck ), + .O ( ), + .IO( pad_pad_hyper_ck_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_hyper_ckn ( + .T ( ~1'b1 ), + .I ( static_connection_signals_soc2pad.hyper_ckn ), + .O ( ), + .IO( pad_pad_hyper_ckn_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_hyper_dq0 ( + .T ( ~static_connection_signals_soc2pad.hyper_dq_oe ), + .I ( static_connection_signals_soc2pad.hyper_dq0_o ), + .O ( static_connection_signals_pad2soc.hyper_dq0_i ), + .IO( pad_pad_hyper_dq0_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_hyper_dq1 ( + .T ( ~static_connection_signals_soc2pad.hyper_dq_oe ), + .I ( static_connection_signals_soc2pad.hyper_dq1_o ), + .O ( static_connection_signals_pad2soc.hyper_dq1_i ), + .IO( pad_pad_hyper_dq1_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_hyper_dq2 ( + .T ( ~static_connection_signals_soc2pad.hyper_dq_oe ), + .I ( static_connection_signals_soc2pad.hyper_dq2_o ), + .O ( static_connection_signals_pad2soc.hyper_dq2_i ), + .IO( pad_pad_hyper_dq2_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_hyper_dq3 ( + .T ( ~static_connection_signals_soc2pad.hyper_dq_oe ), + .I ( static_connection_signals_soc2pad.hyper_dq3_o ), + .O ( static_connection_signals_pad2soc.hyper_dq3_i ), + .IO( pad_pad_hyper_dq3_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_hyper_dq4 ( + .T ( ~static_connection_signals_soc2pad.hyper_dq_oe ), + .I ( static_connection_signals_soc2pad.hyper_dq4_o ), + .O ( static_connection_signals_pad2soc.hyper_dq4_i ), + .IO( pad_pad_hyper_dq4_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_hyper_dq5 ( + .T ( ~static_connection_signals_soc2pad.hyper_dq_oe ), + .I ( static_connection_signals_soc2pad.hyper_dq5_o ), + .O ( static_connection_signals_pad2soc.hyper_dq5_i ), + .IO( pad_pad_hyper_dq5_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_hyper_dq6 ( + .T ( ~static_connection_signals_soc2pad.hyper_dq_oe ), + .I ( static_connection_signals_soc2pad.hyper_dq6_o ), + .O ( static_connection_signals_pad2soc.hyper_dq6_i ), + .IO( pad_pad_hyper_dq6_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_hyper_dq7 ( + .T ( ~static_connection_signals_soc2pad.hyper_dq_oe ), + .I ( static_connection_signals_soc2pad.hyper_dq7_o ), + .O ( static_connection_signals_pad2soc.hyper_dq7_i ), + .IO( pad_pad_hyper_dq7_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_hyper_rwds ( + .T ( ~static_connection_signals_soc2pad.hyper_rwds_oe ), + .I ( static_connection_signals_soc2pad.hyper_rwds_o ), + .O ( static_connection_signals_pad2soc.hyper_rwds_i ), + .IO( pad_pad_hyper_rwds_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io00 ( + .T ( ~mux_to_pads_i.pad_io00.tx_en ), + .I ( mux_to_pads_i.pad_io00.chip2pad ), + .O ( pads_to_mux_o.pad_io00.pad2chip ), + .IO( pad_pad_io00_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io01 ( + .T ( ~mux_to_pads_i.pad_io01.tx_en ), + .I ( mux_to_pads_i.pad_io01.chip2pad ), + .O ( pads_to_mux_o.pad_io01.pad2chip ), + .IO( pad_pad_io01_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io02 ( + .T ( ~mux_to_pads_i.pad_io02.tx_en ), + .I ( mux_to_pads_i.pad_io02.chip2pad ), + .O ( pads_to_mux_o.pad_io02.pad2chip ), + .IO( pad_pad_io02_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io03 ( + .T ( ~mux_to_pads_i.pad_io03.tx_en ), + .I ( mux_to_pads_i.pad_io03.chip2pad ), + .O ( pads_to_mux_o.pad_io03.pad2chip ), + .IO( pad_pad_io03_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io04 ( + .T ( ~mux_to_pads_i.pad_io04.tx_en ), + .I ( mux_to_pads_i.pad_io04.chip2pad ), + .O ( pads_to_mux_o.pad_io04.pad2chip ), + .IO( pad_pad_io04_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io05 ( + .T ( ~mux_to_pads_i.pad_io05.tx_en ), + .I ( mux_to_pads_i.pad_io05.chip2pad ), + .O ( pads_to_mux_o.pad_io05.pad2chip ), + .IO( pad_pad_io05_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io06 ( + .T ( ~mux_to_pads_i.pad_io06.tx_en ), + .I ( mux_to_pads_i.pad_io06.chip2pad ), + .O ( pads_to_mux_o.pad_io06.pad2chip ), + .IO( pad_pad_io06_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io07 ( + .T ( ~mux_to_pads_i.pad_io07.tx_en ), + .I ( mux_to_pads_i.pad_io07.chip2pad ), + .O ( pads_to_mux_o.pad_io07.pad2chip ), + .IO( pad_pad_io07_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io08 ( + .T ( ~mux_to_pads_i.pad_io08.tx_en ), + .I ( mux_to_pads_i.pad_io08.chip2pad ), + .O ( pads_to_mux_o.pad_io08.pad2chip ), + .IO( pad_pad_io08_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io09 ( + .T ( ~mux_to_pads_i.pad_io09.tx_en ), + .I ( mux_to_pads_i.pad_io09.chip2pad ), + .O ( pads_to_mux_o.pad_io09.pad2chip ), + .IO( pad_pad_io09_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io10 ( + .T ( ~mux_to_pads_i.pad_io10.tx_en ), + .I ( mux_to_pads_i.pad_io10.chip2pad ), + .O ( pads_to_mux_o.pad_io10.pad2chip ), + .IO( pad_pad_io10_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io11 ( + .T ( ~mux_to_pads_i.pad_io11.tx_en ), + .I ( mux_to_pads_i.pad_io11.chip2pad ), + .O ( pads_to_mux_o.pad_io11.pad2chip ), + .IO( pad_pad_io11_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io12 ( + .T ( ~mux_to_pads_i.pad_io12.tx_en ), + .I ( mux_to_pads_i.pad_io12.chip2pad ), + .O ( pads_to_mux_o.pad_io12.pad2chip ), + .IO( pad_pad_io12_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io13 ( + .T ( ~mux_to_pads_i.pad_io13.tx_en ), + .I ( mux_to_pads_i.pad_io13.chip2pad ), + .O ( pads_to_mux_o.pad_io13.pad2chip ), + .IO( pad_pad_io13_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io14 ( + .T ( ~mux_to_pads_i.pad_io14.tx_en ), + .I ( mux_to_pads_i.pad_io14.chip2pad ), + .O ( pads_to_mux_o.pad_io14.pad2chip ), + .IO( pad_pad_io14_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io15 ( + .T ( ~mux_to_pads_i.pad_io15.tx_en ), + .I ( mux_to_pads_i.pad_io15.chip2pad ), + .O ( pads_to_mux_o.pad_io15.pad2chip ), + .IO( pad_pad_io15_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io16 ( + .T ( ~mux_to_pads_i.pad_io16.tx_en ), + .I ( mux_to_pads_i.pad_io16.chip2pad ), + .O ( pads_to_mux_o.pad_io16.pad2chip ), + .IO( pad_pad_io16_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io17 ( + .T ( ~mux_to_pads_i.pad_io17.tx_en ), + .I ( mux_to_pads_i.pad_io17.chip2pad ), + .O ( pads_to_mux_o.pad_io17.pad2chip ), + .IO( pad_pad_io17_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io18 ( + .T ( ~mux_to_pads_i.pad_io18.tx_en ), + .I ( mux_to_pads_i.pad_io18.chip2pad ), + .O ( pads_to_mux_o.pad_io18.pad2chip ), + .IO( pad_pad_io18_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io19 ( + .T ( ~mux_to_pads_i.pad_io19.tx_en ), + .I ( mux_to_pads_i.pad_io19.chip2pad ), + .O ( pads_to_mux_o.pad_io19.pad2chip ), + .IO( pad_pad_io19_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io20 ( + .T ( ~mux_to_pads_i.pad_io20.tx_en ), + .I ( mux_to_pads_i.pad_io20.chip2pad ), + .O ( pads_to_mux_o.pad_io20.pad2chip ), + .IO( pad_pad_io20_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io21 ( + .T ( ~mux_to_pads_i.pad_io21.tx_en ), + .I ( mux_to_pads_i.pad_io21.chip2pad ), + .O ( pads_to_mux_o.pad_io21.pad2chip ), + .IO( pad_pad_io21_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io22 ( + .T ( ~mux_to_pads_i.pad_io22.tx_en ), + .I ( mux_to_pads_i.pad_io22.chip2pad ), + .O ( pads_to_mux_o.pad_io22.pad2chip ), + .IO( pad_pad_io22_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io23 ( + .T ( ~mux_to_pads_i.pad_io23.tx_en ), + .I ( mux_to_pads_i.pad_io23.chip2pad ), + .O ( pads_to_mux_o.pad_io23.pad2chip ), + .IO( pad_pad_io23_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io24 ( + .T ( ~mux_to_pads_i.pad_io24.tx_en ), + .I ( mux_to_pads_i.pad_io24.chip2pad ), + .O ( pads_to_mux_o.pad_io24.pad2chip ), + .IO( pad_pad_io24_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io25 ( + .T ( ~mux_to_pads_i.pad_io25.tx_en ), + .I ( mux_to_pads_i.pad_io25.chip2pad ), + .O ( pads_to_mux_o.pad_io25.pad2chip ), + .IO( pad_pad_io25_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io26 ( + .T ( ~mux_to_pads_i.pad_io26.tx_en ), + .I ( mux_to_pads_i.pad_io26.chip2pad ), + .O ( pads_to_mux_o.pad_io26.pad2chip ), + .IO( pad_pad_io26_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io27 ( + .T ( ~mux_to_pads_i.pad_io27.tx_en ), + .I ( mux_to_pads_i.pad_io27.chip2pad ), + .O ( pads_to_mux_o.pad_io27.pad2chip ), + .IO( pad_pad_io27_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io28 ( + .T ( ~mux_to_pads_i.pad_io28.tx_en ), + .I ( mux_to_pads_i.pad_io28.chip2pad ), + .O ( pads_to_mux_o.pad_io28.pad2chip ), + .IO( pad_pad_io28_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io29 ( + .T ( ~mux_to_pads_i.pad_io29.tx_en ), + .I ( mux_to_pads_i.pad_io29.chip2pad ), + .O ( pads_to_mux_o.pad_io29.pad2chip ), + .IO( pad_pad_io29_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io30 ( + .T ( ~mux_to_pads_i.pad_io30.tx_en ), + .I ( mux_to_pads_i.pad_io30.chip2pad ), + .O ( pads_to_mux_o.pad_io30.pad2chip ), + .IO( pad_pad_io30_pad ) + ); + (* PULLUP = "YES" *) + IOBUF i_pad_io31 ( + .T ( ~mux_to_pads_i.pad_io31.tx_en ), + .I ( mux_to_pads_i.pad_io31.chip2pad ), + .O ( pads_to_mux_o.pad_io31.pad2chip ), + .IO( pad_pad_io31_pad ) + ); + +endmodule : pulpissimo_padframe_all_pads_pads diff --git a/hw/padframe/pulpissimo_padframe_fpga_autogen/src/pulpissimo_padframe_all_pads_regs.hjson b/hw/padframe/pulpissimo_padframe_fpga_autogen/src/pulpissimo_padframe_all_pads_regs.hjson new file mode 100644 index 00000000..63d8b748 --- /dev/null +++ b/hw/padframe/pulpissimo_padframe_fpga_autogen/src/pulpissimo_padframe_all_pads_regs.hjson @@ -0,0 +1,3771 @@ + + +{ + # File auto-generated by Padrick unknown + name: "pulpissimo_padframe_all_pads_config" + clock_primary: "clk_i" + reset_primary: "rst_ni" + bus_interfaces: [ + { protocol: "reg_iface", direction: "device"} + ] + regwidth: 32, + registers: [ + {skipto: "0x0"}, + { + name: INFO + desc: "Read-only IP Information register" + swaccess: "ro" + hwaccess: "hro" + fields: [ + { + bits: "15:0" + name: HW_VERSION + desc: "Hardware version ID." + resval: 2 + }, + { + bits:"31:16" + name: PADCOUNT + desc: "The number of muxable pads in this IP." + resval: "32" + } + ] + } + + + + + + + + + + + + + + + + + + + + + + + + + { + name: PAD_IO00_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO00_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io00. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio00", desc: "Connect port gpio00 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO01_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO01_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io01. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio01", desc: "Connect port gpio01 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO02_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO02_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io02. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio02", desc: "Connect port gpio02 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO03_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO03_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io03. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio03", desc: "Connect port gpio03 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO04_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO04_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io04. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio04", desc: "Connect port gpio04 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO05_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO05_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io05. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio05", desc: "Connect port gpio05 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO06_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO06_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io06. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio06", desc: "Connect port gpio06 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO07_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO07_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io07. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio07", desc: "Connect port gpio07 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO08_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO08_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io08. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio08", desc: "Connect port gpio08 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO09_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO09_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io09. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio09", desc: "Connect port gpio09 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO10_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO10_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io10. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio10", desc: "Connect port gpio10 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO11_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO11_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io11. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio11", desc: "Connect port gpio11 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO12_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO12_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io12. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio12", desc: "Connect port gpio12 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO13_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO13_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io13. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio13", desc: "Connect port gpio13 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO14_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO14_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io14. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio14", desc: "Connect port gpio14 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO15_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO15_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io15. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio15", desc: "Connect port gpio15 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO16_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO16_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io16. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio16", desc: "Connect port gpio16 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO17_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO17_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io17. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio17", desc: "Connect port gpio17 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO18_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO18_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io18. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio18", desc: "Connect port gpio18 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO19_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO19_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io19. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio19", desc: "Connect port gpio19 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO20_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO20_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io20. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio20", desc: "Connect port gpio20 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO21_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO21_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io21. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio21", desc: "Connect port gpio21 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO22_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO22_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io22. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio22", desc: "Connect port gpio22 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO23_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO23_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io23. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio23", desc: "Connect port gpio23 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO24_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO24_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io24. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio24", desc: "Connect port gpio24 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO25_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO25_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io25. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio25", desc: "Connect port gpio25 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO26_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO26_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io26. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio26", desc: "Connect port gpio26 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO27_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO27_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io27. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio27", desc: "Connect port gpio27 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO28_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO28_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io28. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio28", desc: "Connect port gpio28 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO29_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO29_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io29. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio29", desc: "Connect port gpio29 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO30_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO30_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io30. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio30", desc: "Connect port gpio30 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO31_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "2" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO31_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io31. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio31", desc: "Connect port gpio31 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + ] +} diff --git a/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/Bender.yml b/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/Bender.yml new file mode 100644 index 00000000..b5e04123 --- /dev/null +++ b/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/Bender.yml @@ -0,0 +1,26 @@ + +# File auto-generated by Padrick unknown +package: + name: pulpissimo_padframe_rtl_sim + authors: + - "Padrick" + +dependencies: + register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.1 } + common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } + +export_include_dirs: +- include + +sources: + - target: rtl_sim + files: + - src/pkg_pulpissimo_padframe.sv + - src/pkg_internal_pulpissimo_padframe_all_pads.sv + - src/pulpissimo_padframe_all_pads_config_reg_pkg.sv + - src/pulpissimo_padframe_all_pads_config_reg_top.sv + - src/pulpissimo_padframe_all_pads_pads.sv + - src/pulpissimo_padframe_all_pads_muxer.sv + - src/pulpissimo_padframe_all_pads.sv + - src/pulpissimo_padframe.sv + diff --git a/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/include/pulpissimo_padframe/assign.svh b/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/include/pulpissimo_padframe/assign.svh new file mode 100644 index 00000000..114c8838 --- /dev/null +++ b/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/include/pulpissimo_padframe/assign.svh @@ -0,0 +1,251 @@ + +// File auto-generated by Padrick unknown + +// Assignment Macros +// Assigns all members of port struct to another struct with same names but potentially different order + + + + +`define ASSIGN_GPIO_PAD2SOC(load, driver) \ + assign load.gpio_in[0] = driver.gpio00_in; \ + assign load.gpio_in[1] = driver.gpio01_in; \ + assign load.gpio_in[2] = driver.gpio02_in; \ + assign load.gpio_in[3] = driver.gpio03_in; \ + assign load.gpio_in[4] = driver.gpio04_in; \ + assign load.gpio_in[5] = driver.gpio05_in; \ + assign load.gpio_in[6] = driver.gpio06_in; \ + assign load.gpio_in[7] = driver.gpio07_in; \ + assign load.gpio_in[8] = driver.gpio08_in; \ + assign load.gpio_in[9] = driver.gpio09_in; \ + assign load.gpio_in[10] = driver.gpio10_in; \ + assign load.gpio_in[11] = driver.gpio11_in; \ + assign load.gpio_in[12] = driver.gpio12_in; \ + assign load.gpio_in[13] = driver.gpio13_in; \ + assign load.gpio_in[14] = driver.gpio14_in; \ + assign load.gpio_in[15] = driver.gpio15_in; \ + assign load.gpio_in[16] = driver.gpio16_in; \ + assign load.gpio_in[17] = driver.gpio17_in; \ + assign load.gpio_in[18] = driver.gpio18_in; \ + assign load.gpio_in[19] = driver.gpio19_in; \ + assign load.gpio_in[20] = driver.gpio20_in; \ + assign load.gpio_in[21] = driver.gpio21_in; \ + assign load.gpio_in[22] = driver.gpio22_in; \ + assign load.gpio_in[23] = driver.gpio23_in; \ + assign load.gpio_in[24] = driver.gpio24_in; \ + assign load.gpio_in[25] = driver.gpio25_in; \ + assign load.gpio_in[26] = driver.gpio26_in; \ + assign load.gpio_in[27] = driver.gpio27_in; \ + assign load.gpio_in[28] = driver.gpio28_in; \ + assign load.gpio_in[29] = driver.gpio29_in; \ + assign load.gpio_in[30] = driver.gpio30_in; \ + assign load.gpio_in[31] = driver.gpio31_in; \ + +`define ASSIGN_GPIO_SOC2PAD(load, driver) \ + assign load.gpio00_out = driver.gpio_out[0]; \ + assign load.gpio00_tx_en = driver.gpio_tx_en[0]; \ + assign load.gpio01_out = driver.gpio_out[1]; \ + assign load.gpio01_tx_en = driver.gpio_tx_en[1]; \ + assign load.gpio02_out = driver.gpio_out[2]; \ + assign load.gpio02_tx_en = driver.gpio_tx_en[2]; \ + assign load.gpio03_out = driver.gpio_out[3]; \ + assign load.gpio03_tx_en = driver.gpio_tx_en[3]; \ + assign load.gpio04_out = driver.gpio_out[4]; \ + assign load.gpio04_tx_en = driver.gpio_tx_en[4]; \ + assign load.gpio05_out = driver.gpio_out[5]; \ + assign load.gpio05_tx_en = driver.gpio_tx_en[5]; \ + assign load.gpio06_out = driver.gpio_out[6]; \ + assign load.gpio06_tx_en = driver.gpio_tx_en[6]; \ + assign load.gpio07_out = driver.gpio_out[7]; \ + assign load.gpio07_tx_en = driver.gpio_tx_en[7]; \ + assign load.gpio08_out = driver.gpio_out[8]; \ + assign load.gpio08_tx_en = driver.gpio_tx_en[8]; \ + assign load.gpio09_out = driver.gpio_out[9]; \ + assign load.gpio09_tx_en = driver.gpio_tx_en[9]; \ + assign load.gpio10_out = driver.gpio_out[10]; \ + assign load.gpio10_tx_en = driver.gpio_tx_en[10]; \ + assign load.gpio11_out = driver.gpio_out[11]; \ + assign load.gpio11_tx_en = driver.gpio_tx_en[11]; \ + assign load.gpio12_out = driver.gpio_out[12]; \ + assign load.gpio12_tx_en = driver.gpio_tx_en[12]; \ + assign load.gpio13_out = driver.gpio_out[13]; \ + assign load.gpio13_tx_en = driver.gpio_tx_en[13]; \ + assign load.gpio14_out = driver.gpio_out[14]; \ + assign load.gpio14_tx_en = driver.gpio_tx_en[14]; \ + assign load.gpio15_out = driver.gpio_out[15]; \ + assign load.gpio15_tx_en = driver.gpio_tx_en[15]; \ + assign load.gpio16_out = driver.gpio_out[16]; \ + assign load.gpio16_tx_en = driver.gpio_tx_en[16]; \ + assign load.gpio17_out = driver.gpio_out[17]; \ + assign load.gpio17_tx_en = driver.gpio_tx_en[17]; \ + assign load.gpio18_out = driver.gpio_out[18]; \ + assign load.gpio18_tx_en = driver.gpio_tx_en[18]; \ + assign load.gpio19_out = driver.gpio_out[19]; \ + assign load.gpio19_tx_en = driver.gpio_tx_en[19]; \ + assign load.gpio20_out = driver.gpio_out[20]; \ + assign load.gpio20_tx_en = driver.gpio_tx_en[20]; \ + assign load.gpio21_out = driver.gpio_out[21]; \ + assign load.gpio21_tx_en = driver.gpio_tx_en[21]; \ + assign load.gpio22_out = driver.gpio_out[22]; \ + assign load.gpio22_tx_en = driver.gpio_tx_en[22]; \ + assign load.gpio23_out = driver.gpio_out[23]; \ + assign load.gpio23_tx_en = driver.gpio_tx_en[23]; \ + assign load.gpio24_out = driver.gpio_out[24]; \ + assign load.gpio24_tx_en = driver.gpio_tx_en[24]; \ + assign load.gpio25_out = driver.gpio_out[25]; \ + assign load.gpio25_tx_en = driver.gpio_tx_en[25]; \ + assign load.gpio26_out = driver.gpio_out[26]; \ + assign load.gpio26_tx_en = driver.gpio_tx_en[26]; \ + assign load.gpio27_out = driver.gpio_out[27]; \ + assign load.gpio27_tx_en = driver.gpio_tx_en[27]; \ + assign load.gpio28_out = driver.gpio_out[28]; \ + assign load.gpio28_tx_en = driver.gpio_tx_en[28]; \ + assign load.gpio29_out = driver.gpio_out[29]; \ + assign load.gpio29_tx_en = driver.gpio_tx_en[29]; \ + assign load.gpio30_out = driver.gpio_out[30]; \ + assign load.gpio30_tx_en = driver.gpio_tx_en[30]; \ + assign load.gpio31_out = driver.gpio_out[31]; \ + assign load.gpio31_tx_en = driver.gpio_tx_en[31]; \ + + + +`define ASSIGN_I2C0_PAD2SOC(load, driver) \ + assign load.scl_i = driver.scl_i; \ + assign load.sda_i = driver.sda_i; \ + +`define ASSIGN_I2C0_SOC2PAD(load, driver) \ + assign load.scl_o = driver.scl_o; \ + assign load.scl_oe = driver.scl_oe; \ + assign load.sda_o = driver.sda_o; \ + assign load.sda_oe = driver.sda_oe; \ + + + +`define ASSIGN_UART0_PAD2SOC(load, driver) \ + assign load.rx_i = driver.rx_i; \ + +`define ASSIGN_UART0_SOC2PAD(load, driver) \ + assign load.tx_o = driver.tx_o; \ + + + +`define ASSIGN_QSPIM0_PAD2SOC(load, driver) \ + assign load.sd0_i = driver.sd0_i; \ + assign load.sd1_i = driver.sd1_i; \ + assign load.sd2_i = driver.sd2_i; \ + assign load.sd3_i = driver.sd3_i; \ + +`define ASSIGN_QSPIM0_SOC2PAD(load, driver) \ + assign load.csn0_o = driver.csn0_o; \ + assign load.csn1_o = driver.csn1_o; \ + assign load.csn2_o = driver.csn2_o; \ + assign load.csn3_o = driver.csn3_o; \ + assign load.sck_o = driver.sck_o; \ + assign load.sd0_o = driver.sd0_o; \ + assign load.sd0_oe = driver.sd0_oe; \ + assign load.sd1_o = driver.sd1_o; \ + assign load.sd1_oe = driver.sd1_oe; \ + assign load.sd2_o = driver.sd2_o; \ + assign load.sd2_oe = driver.sd2_oe; \ + assign load.sd3_o = driver.sd3_o; \ + assign load.sd3_oe = driver.sd3_oe; \ + + + +`define ASSIGN_CPI0_PAD2SOC(load, driver) \ + assign load.data0_i = driver.data0_i; \ + assign load.data1_i = driver.data1_i; \ + assign load.data2_i = driver.data2_i; \ + assign load.data3_i = driver.data3_i; \ + assign load.data4_i = driver.data4_i; \ + assign load.data5_i = driver.data5_i; \ + assign load.data6_i = driver.data6_i; \ + assign load.data7_i = driver.data7_i; \ + assign load.data8_i = driver.data8_i; \ + assign load.data9_i = driver.data9_i; \ + assign load.hsync_i = driver.hsync_i; \ + assign load.pclk_i = driver.pclk_i; \ + assign load.vsync_i = driver.vsync_i; \ + + + + +`define ASSIGN_SDIO0_PAD2SOC(load, driver) \ + assign load.sdcmd_in = driver.sdcmd_in; \ + assign load.sddata_in[0] = driver.sddata0_in; \ + assign load.sddata_in[1] = driver.sddata1_in; \ + assign load.sddata_in[2] = driver.sddata2_in; \ + assign load.sddata_in[3] = driver.sddata3_in; \ + +`define ASSIGN_SDIO0_SOC2PAD(load, driver) \ + assign load.sdclk_out = driver.sdclk_out; \ + assign load.sdcmd_oen = driver.sdcmd_oen; \ + assign load.sdcmd_out = driver.sdcmd_out; \ + assign load.sddata0_oen = driver.sddata_oen[0]; \ + assign load.sddata0_out = driver.sddata_out[0]; \ + assign load.sddata1_oen = driver.sddata_oen[1]; \ + assign load.sddata1_out = driver.sddata_out[1]; \ + assign load.sddata2_oen = driver.sddata_oen[2]; \ + assign load.sddata2_out = driver.sddata_out[2]; \ + assign load.sddata3_oen = driver.sddata_oen[3]; \ + assign load.sddata3_out = driver.sddata_out[3]; \ + + + +`define ASSIGN_I2S0_PAD2SOC(load, driver) \ + assign load.master_sck_in = driver.master_sck_in; \ + assign load.master_ws_in = driver.master_ws_in; \ + assign load.slave_sck_in = driver.slave_sck_in; \ + assign load.slave_sd0_in = driver.slave_sd0_in; \ + assign load.slave_sd1_in = driver.slave_sd1_in; \ + assign load.slave_ws_in = driver.slave_ws_in; \ + +`define ASSIGN_I2S0_SOC2PAD(load, driver) \ + assign load.master_sck_oe = driver.master_sck_oe; \ + assign load.master_sck_out = driver.master_sck_out; \ + assign load.master_sd0_out = driver.master_sd0_out; \ + assign load.master_sd1_out = driver.master_sd1_out; \ + assign load.master_ws_oe = driver.master_ws_oe; \ + assign load.master_ws_out = driver.master_ws_out; \ + assign load.slave_sck_oe = driver.slave_sck_oe; \ + assign load.slave_sck_out = driver.slave_sck_out; \ + assign load.slave_ws_oe = driver.slave_ws_oe; \ + assign load.slave_ws_out = driver.slave_ws_out; \ + + + + +`define ASSIGN_TIMER0_SOC2PAD(load, driver) \ + assign load.timer_out0 = driver.out[0]; \ + assign load.timer_out1 = driver.out[1]; \ + assign load.timer_out2 = driver.out[2]; \ + assign load.timer_out3 = driver.out[3]; \ + + + + +`define ASSIGN_TIMER1_SOC2PAD(load, driver) \ + assign load.timer_out0 = driver.out[0]; \ + assign load.timer_out1 = driver.out[1]; \ + assign load.timer_out2 = driver.out[2]; \ + assign load.timer_out3 = driver.out[3]; \ + + + + +`define ASSIGN_TIMER2_SOC2PAD(load, driver) \ + assign load.timer_out0 = driver.out[0]; \ + assign load.timer_out1 = driver.out[1]; \ + assign load.timer_out2 = driver.out[2]; \ + assign load.timer_out3 = driver.out[3]; \ + + + + +`define ASSIGN_TIMER3_SOC2PAD(load, driver) \ + assign load.timer_out0 = driver.out[0]; \ + assign load.timer_out1 = driver.out[1]; \ + assign load.timer_out2 = driver.out[2]; \ + assign load.timer_out3 = driver.out[3]; \ + + diff --git a/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/ips_list.yml b/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/ips_list.yml new file mode 100644 index 00000000..09b3d78b --- /dev/null +++ b/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/ips_list.yml @@ -0,0 +1,18 @@ + +# File auto-generated by Padrick 0.3.2.post0.dev5+gfcfdaa2.dirty +# IPApprox dependencies for pulpissimo_padframe +common_cells: + commit: v1.21.0 + domain: [cluster, soc] + server: https://github.com + group: pulp-platform +register_interface: + commit: v0.2.1 + domain: [soc] + server: https://github.com + group: pulp-platform +axi/axi: + commit: v0.27.0 + domain: [cluster, soc] + server: https://github.com + group: pulp-platform diff --git a/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/pulpissimo_padframe.core b/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/pulpissimo_padframe.core new file mode 100644 index 00000000..030293f0 --- /dev/null +++ b/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/pulpissimo_padframe.core @@ -0,0 +1,21 @@ +CAPI=2: +name: test +filesets: + rtl: + files: + - src/pkg_pulpissimo_padframe.sv + - src/pkg_internal_pulpissimo_padframe_all_pads.sv + - src/pulpissimo_padframe_all_pads_config_reg_pkg.sv + - src/pulpissimo_padframe_all_pads_config_reg_top.sv + - src/pulpissimo_padframe_all_pads_pads.sv + - src/pulpissimo_padframe_all_pads_muxer.sv + - src/pulpissimo_padframe_all_pads.sv + - src/pulpissimo_padframe.sv + - src/assign.svh + is_include_file: true + file_type: systemVerilogSource +targets: + default: + filesets: + - rtl + toplevel: pulpissimo_padframe \ No newline at end of file diff --git a/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/src/pkg_internal_pulpissimo_padframe_all_pads.sv b/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/src/pkg_internal_pulpissimo_padframe_all_pads.sv new file mode 100644 index 00000000..862e6e2e --- /dev/null +++ b/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/src/pkg_internal_pulpissimo_padframe_all_pads.sv @@ -0,0 +1,2481 @@ + +// File auto-generated by Padrick unknown +package pkg_internal_pulpissimo_padframe_all_pads; + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io00_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io00_t; + + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io01_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io01_t; + + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io02_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io02_t; + + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io03_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io03_t; + + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io04_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io04_t; + + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io05_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io05_t; + + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io06_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io06_t; + + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io07_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io07_t; + + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io08_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io08_t; + + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io09_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io09_t; + + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io10_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io10_t; + + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io11_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io11_t; + + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io12_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io12_t; + + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io13_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io13_t; + + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io14_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io14_t; + + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io15_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io15_t; + + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io16_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io16_t; + + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io17_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io17_t; + + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io18_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io18_t; + + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io19_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io19_t; + + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io20_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io20_t; + + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io21_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io21_t; + + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io22_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io22_t; + + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io23_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io23_t; + + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io24_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io24_t; + + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io25_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io25_t; + + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io26_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io26_t; + + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io27_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io27_t; + + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io28_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io28_t; + + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io29_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io29_t; + + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io30_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io30_t; + + typedef struct packed{ + logic chip2pad; + logic pull_en; + logic rx_en; + logic tx_en; + } mux_to_pad_pad_io31_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io31_t; + + typedef struct packed{ + mux_to_pad_pad_io00_t pad_io00; + mux_to_pad_pad_io01_t pad_io01; + mux_to_pad_pad_io02_t pad_io02; + mux_to_pad_pad_io03_t pad_io03; + mux_to_pad_pad_io04_t pad_io04; + mux_to_pad_pad_io05_t pad_io05; + mux_to_pad_pad_io06_t pad_io06; + mux_to_pad_pad_io07_t pad_io07; + mux_to_pad_pad_io08_t pad_io08; + mux_to_pad_pad_io09_t pad_io09; + mux_to_pad_pad_io10_t pad_io10; + mux_to_pad_pad_io11_t pad_io11; + mux_to_pad_pad_io12_t pad_io12; + mux_to_pad_pad_io13_t pad_io13; + mux_to_pad_pad_io14_t pad_io14; + mux_to_pad_pad_io15_t pad_io15; + mux_to_pad_pad_io16_t pad_io16; + mux_to_pad_pad_io17_t pad_io17; + mux_to_pad_pad_io18_t pad_io18; + mux_to_pad_pad_io19_t pad_io19; + mux_to_pad_pad_io20_t pad_io20; + mux_to_pad_pad_io21_t pad_io21; + mux_to_pad_pad_io22_t pad_io22; + mux_to_pad_pad_io23_t pad_io23; + mux_to_pad_pad_io24_t pad_io24; + mux_to_pad_pad_io25_t pad_io25; + mux_to_pad_pad_io26_t pad_io26; + mux_to_pad_pad_io27_t pad_io27; + mux_to_pad_pad_io28_t pad_io28; + mux_to_pad_pad_io29_t pad_io29; + mux_to_pad_pad_io30_t pad_io30; + mux_to_pad_pad_io31_t pad_io31; + } mux_to_pads_t; + + typedef struct packed{ + pad_to_mux_pad_io00_t pad_io00; + pad_to_mux_pad_io01_t pad_io01; + pad_to_mux_pad_io02_t pad_io02; + pad_to_mux_pad_io03_t pad_io03; + pad_to_mux_pad_io04_t pad_io04; + pad_to_mux_pad_io05_t pad_io05; + pad_to_mux_pad_io06_t pad_io06; + pad_to_mux_pad_io07_t pad_io07; + pad_to_mux_pad_io08_t pad_io08; + pad_to_mux_pad_io09_t pad_io09; + pad_to_mux_pad_io10_t pad_io10; + pad_to_mux_pad_io11_t pad_io11; + pad_to_mux_pad_io12_t pad_io12; + pad_to_mux_pad_io13_t pad_io13; + pad_to_mux_pad_io14_t pad_io14; + pad_to_mux_pad_io15_t pad_io15; + pad_to_mux_pad_io16_t pad_io16; + pad_to_mux_pad_io17_t pad_io17; + pad_to_mux_pad_io18_t pad_io18; + pad_to_mux_pad_io19_t pad_io19; + pad_to_mux_pad_io20_t pad_io20; + pad_to_mux_pad_io21_t pad_io21; + pad_to_mux_pad_io22_t pad_io22; + pad_to_mux_pad_io23_t pad_io23; + pad_to_mux_pad_io24_t pad_io24; + pad_to_mux_pad_io25_t pad_io25; + pad_to_mux_pad_io26_t pad_io26; + pad_to_mux_pad_io27_t pad_io27; + pad_to_mux_pad_io28_t pad_io28; + pad_to_mux_pad_io29_t pad_io29; + pad_to_mux_pad_io30_t pad_io30; + pad_to_mux_pad_io31_t pad_io31; + } pads_to_mux_t; + + + + // Indices definitions + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_GPIO_GPIO00 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_GPIO_GPIO01 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_GPIO_GPIO02 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_GPIO_GPIO03 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_GPIO_GPIO04 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_GPIO_GPIO05 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_GPIO_GPIO06 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_GPIO_GPIO07 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_GPIO_GPIO08 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_GPIO_GPIO09 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_GPIO_GPIO10 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_GPIO_GPIO11 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_GPIO_GPIO12 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_GPIO_GPIO13 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_GPIO_GPIO14 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_GPIO_GPIO15 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_GPIO_GPIO16 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_GPIO_GPIO17 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_GPIO_GPIO18 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_GPIO_GPIO19 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_GPIO_GPIO20 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_GPIO_GPIO21 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_GPIO_GPIO22 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_GPIO_GPIO23 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_GPIO_GPIO24 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_GPIO_GPIO25 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_GPIO_GPIO26 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_GPIO_GPIO27 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_GPIO_GPIO28 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_GPIO_GPIO29 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_GPIO_GPIO30 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_UART0_TX = 6'd57; + + parameter PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_WIDTH = 6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_DEFAULT = 6'd0; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA0 = 6'd1; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA1 = 6'd2; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA2 = 6'd3; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA3 = 6'd4; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA4 = 6'd5; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA5 = 6'd6; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA6 = 6'd7; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA7 = 6'd8; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA8 = 6'd9; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA9 = 6'd10; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_HSYNC = 6'd11; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_PCLK = 6'd12; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_VSYNC = 6'd13; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_GPIO_GPIO31 = 6'd14; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2C0_SCL = 6'd15; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2C0_SDA = 6'd16; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_MASTER_SCK = 6'd17; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_MASTER_SD0 = 6'd18; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_MASTER_SD1 = 6'd19; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_MASTER_WS = 6'd20; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_SLAVE_SCK = 6'd21; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_SLAVE_SD0 = 6'd22; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_SLAVE_SD1 = 6'd23; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_SLAVE_WS = 6'd24; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_CSN0 = 6'd25; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_CSN1 = 6'd26; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_CSN2 = 6'd27; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_CSN3 = 6'd28; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_SCK = 6'd29; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_SDIO0 = 6'd30; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_SDIO1 = 6'd31; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_SDIO2 = 6'd32; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_SDIO3 = 6'd33; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDCLK = 6'd34; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDCMD = 6'd35; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDDATA0 = 6'd36; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDDATA1 = 6'd37; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDDATA2 = 6'd38; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDDATA3 = 6'd39; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER0_OUT0 = 6'd40; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER0_OUT1 = 6'd41; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER0_OUT2 = 6'd42; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER0_OUT3 = 6'd43; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER1_OUT0 = 6'd44; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER1_OUT1 = 6'd45; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER1_OUT2 = 6'd46; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER1_OUT3 = 6'd47; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER2_OUT0 = 6'd48; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER2_OUT1 = 6'd49; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER2_OUT2 = 6'd50; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER2_OUT3 = 6'd51; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER3_OUT0 = 6'd52; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER3_OUT1 = 6'd53; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER3_OUT2 = 6'd54; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER3_OUT3 = 6'd55; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_UART0_RX = 6'd56; + parameter logic[5:0] PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_UART0_TX = 6'd57; + + // Dynamic Pad instance index + + parameter PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH = 5; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00 = 5'd0; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01 = 5'd1; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02 = 5'd2; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03 = 5'd3; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04 = 5'd4; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05 = 5'd5; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06 = 5'd6; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07 = 5'd7; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08 = 5'd8; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09 = 5'd9; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10 = 5'd10; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11 = 5'd11; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12 = 5'd12; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13 = 5'd13; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14 = 5'd14; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15 = 5'd15; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16 = 5'd16; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17 = 5'd17; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18 = 5'd18; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19 = 5'd19; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20 = 5'd20; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21 = 5'd21; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22 = 5'd22; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23 = 5'd23; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24 = 5'd24; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25 = 5'd25; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26 = 5'd26; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27 = 5'd27; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28 = 5'd28; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29 = 5'd29; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30 = 5'd30; + parameter logic[4:0] PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31 = 5'd31; + + parameter PORT_MUX_GROUP_PAD_IO00_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO00_SEL_PAD_IO00 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO01_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO01_SEL_PAD_IO01 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO02_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO02_SEL_PAD_IO02 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO03_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO03_SEL_PAD_IO03 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO04_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO04_SEL_PAD_IO04 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO05_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO05_SEL_PAD_IO05 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO06_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO06_SEL_PAD_IO06 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO07_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO07_SEL_PAD_IO07 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO08_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO08_SEL_PAD_IO08 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO09_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO09_SEL_PAD_IO09 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO10_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO10_SEL_PAD_IO10 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO11_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO11_SEL_PAD_IO11 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO12_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO12_SEL_PAD_IO12 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO13_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO13_SEL_PAD_IO13 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO14_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO14_SEL_PAD_IO14 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO15_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO15_SEL_PAD_IO15 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO16_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO16_SEL_PAD_IO16 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO17_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO17_SEL_PAD_IO17 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO18_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO18_SEL_PAD_IO18 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO19_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO19_SEL_PAD_IO19 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO20_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO20_SEL_PAD_IO20 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO21_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO21_SEL_PAD_IO21 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO22_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO22_SEL_PAD_IO22 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO23_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO23_SEL_PAD_IO23 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO24_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO24_SEL_PAD_IO24 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO25_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO25_SEL_PAD_IO25 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO26_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO26_SEL_PAD_IO26 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO27_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO27_SEL_PAD_IO27 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO28_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO28_SEL_PAD_IO28 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO29_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO29_SEL_PAD_IO29 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO30_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO30_SEL_PAD_IO30 = 1'd0; + + parameter PORT_MUX_GROUP_PAD_IO31_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD_IO31_SEL_PAD_IO31 = 1'd0; +endpackage : pkg_internal_pulpissimo_padframe_all_pads diff --git a/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/src/pkg_pulpissimo_padframe.sv b/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/src/pkg_pulpissimo_padframe.sv new file mode 100644 index 00000000..7b25c961 --- /dev/null +++ b/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/src/pkg_pulpissimo_padframe.sv @@ -0,0 +1,326 @@ + +// File auto-generated by Padrick unknown +package pkg_pulpissimo_padframe; + + //Structs for all_pads + + //Static connections signals + typedef struct packed { + logic hyper_ck; + logic hyper_ckn; + logic hyper_cs0_no; + logic hyper_cs1_no; + logic hyper_dq0_o; + logic hyper_dq1_o; + logic hyper_dq2_o; + logic hyper_dq3_o; + logic hyper_dq4_o; + logic hyper_dq5_o; + logic hyper_dq6_o; + logic hyper_dq7_o; + logic hyper_dq_oe; + logic hyper_reset_no; + logic hyper_rwds_o; + logic hyper_rwds_oe; + logic jtag_tdo; + } pad_domain_all_pads_static_connection_signals_soc2pad_t; + + typedef struct packed { + logic bootsel0; + logic bootsel1; + logic clk_byp_en; + logic hyper_dq0_i; + logic hyper_dq1_i; + logic hyper_dq2_i; + logic hyper_dq3_i; + logic hyper_dq4_i; + logic hyper_dq5_i; + logic hyper_dq6_i; + logic hyper_dq7_i; + logic hyper_rwds_i; + logic jtag_tck; + logic jtag_tdi; + logic jtag_tms; + logic jtag_trstn; + logic ref_clk; + logic rst_n; + } pad_domain_all_pads_static_connection_signals_pad2soc_t; + + // Port Group signals + typedef struct packed { + logic gpio00_out; + logic gpio00_tx_en; + logic gpio01_out; + logic gpio01_tx_en; + logic gpio02_out; + logic gpio02_tx_en; + logic gpio03_out; + logic gpio03_tx_en; + logic gpio04_out; + logic gpio04_tx_en; + logic gpio05_out; + logic gpio05_tx_en; + logic gpio06_out; + logic gpio06_tx_en; + logic gpio07_out; + logic gpio07_tx_en; + logic gpio08_out; + logic gpio08_tx_en; + logic gpio09_out; + logic gpio09_tx_en; + logic gpio10_out; + logic gpio10_tx_en; + logic gpio11_out; + logic gpio11_tx_en; + logic gpio12_out; + logic gpio12_tx_en; + logic gpio13_out; + logic gpio13_tx_en; + logic gpio14_out; + logic gpio14_tx_en; + logic gpio15_out; + logic gpio15_tx_en; + logic gpio16_out; + logic gpio16_tx_en; + logic gpio17_out; + logic gpio17_tx_en; + logic gpio18_out; + logic gpio18_tx_en; + logic gpio19_out; + logic gpio19_tx_en; + logic gpio20_out; + logic gpio20_tx_en; + logic gpio21_out; + logic gpio21_tx_en; + logic gpio22_out; + logic gpio22_tx_en; + logic gpio23_out; + logic gpio23_tx_en; + logic gpio24_out; + logic gpio24_tx_en; + logic gpio25_out; + logic gpio25_tx_en; + logic gpio26_out; + logic gpio26_tx_en; + logic gpio27_out; + logic gpio27_tx_en; + logic gpio28_out; + logic gpio28_tx_en; + logic gpio29_out; + logic gpio29_tx_en; + logic gpio30_out; + logic gpio30_tx_en; + logic gpio31_out; + logic gpio31_tx_en; + } pad_domain_all_pads_port_group_gpio_soc2pad_t; + + typedef struct packed { + logic gpio00_in; + logic gpio01_in; + logic gpio02_in; + logic gpio03_in; + logic gpio04_in; + logic gpio05_in; + logic gpio06_in; + logic gpio07_in; + logic gpio08_in; + logic gpio09_in; + logic gpio10_in; + logic gpio11_in; + logic gpio12_in; + logic gpio13_in; + logic gpio14_in; + logic gpio15_in; + logic gpio16_in; + logic gpio17_in; + logic gpio18_in; + logic gpio19_in; + logic gpio20_in; + logic gpio21_in; + logic gpio22_in; + logic gpio23_in; + logic gpio24_in; + logic gpio25_in; + logic gpio26_in; + logic gpio27_in; + logic gpio28_in; + logic gpio29_in; + logic gpio30_in; + logic gpio31_in; + } pad_domain_all_pads_port_group_gpio_pad2soc_t; + + typedef struct packed { + logic scl_o; + logic scl_oe; + logic sda_o; + logic sda_oe; + } pad_domain_all_pads_port_group_i2c0_soc2pad_t; + + typedef struct packed { + logic scl_i; + logic sda_i; + } pad_domain_all_pads_port_group_i2c0_pad2soc_t; + + typedef struct packed { + logic tx_o; + } pad_domain_all_pads_port_group_uart0_soc2pad_t; + + typedef struct packed { + logic rx_i; + } pad_domain_all_pads_port_group_uart0_pad2soc_t; + + typedef struct packed { + logic csn0_o; + logic csn1_o; + logic csn2_o; + logic csn3_o; + logic sck_o; + logic sd0_o; + logic sd0_oe; + logic sd1_o; + logic sd1_oe; + logic sd2_o; + logic sd2_oe; + logic sd3_o; + logic sd3_oe; + } pad_domain_all_pads_port_group_qspim0_soc2pad_t; + + typedef struct packed { + logic sd0_i; + logic sd1_i; + logic sd2_i; + logic sd3_i; + } pad_domain_all_pads_port_group_qspim0_pad2soc_t; + + typedef struct packed { + logic data0_i; + logic data1_i; + logic data2_i; + logic data3_i; + logic data4_i; + logic data5_i; + logic data6_i; + logic data7_i; + logic data8_i; + logic data9_i; + logic hsync_i; + logic pclk_i; + logic vsync_i; + } pad_domain_all_pads_port_group_cpi0_pad2soc_t; + + typedef struct packed { + logic sdclk_out; + logic sdcmd_oen; + logic sdcmd_out; + logic sddata0_oen; + logic sddata0_out; + logic sddata1_oen; + logic sddata1_out; + logic sddata2_oen; + logic sddata2_out; + logic sddata3_oen; + logic sddata3_out; + } pad_domain_all_pads_port_group_sdio0_soc2pad_t; + + typedef struct packed { + logic sdcmd_in; + logic sddata0_in; + logic sddata1_in; + logic sddata2_in; + logic sddata3_in; + } pad_domain_all_pads_port_group_sdio0_pad2soc_t; + + typedef struct packed { + logic master_sck_oe; + logic master_sck_out; + logic master_sd0_out; + logic master_sd1_out; + logic master_ws_oe; + logic master_ws_out; + logic slave_sck_oe; + logic slave_sck_out; + logic slave_ws_oe; + logic slave_ws_out; + } pad_domain_all_pads_port_group_i2s0_soc2pad_t; + + typedef struct packed { + logic master_sck_in; + logic master_ws_in; + logic slave_sck_in; + logic slave_sd0_in; + logic slave_sd1_in; + logic slave_ws_in; + } pad_domain_all_pads_port_group_i2s0_pad2soc_t; + + typedef struct packed { + logic timer_out0; + logic timer_out1; + logic timer_out2; + logic timer_out3; + } pad_domain_all_pads_port_group_timer0_soc2pad_t; + + typedef struct packed { + logic timer_out0; + logic timer_out1; + logic timer_out2; + logic timer_out3; + } pad_domain_all_pads_port_group_timer1_soc2pad_t; + + typedef struct packed { + logic timer_out0; + logic timer_out1; + logic timer_out2; + logic timer_out3; + } pad_domain_all_pads_port_group_timer2_soc2pad_t; + + typedef struct packed { + logic timer_out0; + logic timer_out1; + logic timer_out2; + logic timer_out3; + } pad_domain_all_pads_port_group_timer3_soc2pad_t; + + typedef struct packed { + pad_domain_all_pads_port_group_gpio_soc2pad_t gpio; + pad_domain_all_pads_port_group_i2c0_soc2pad_t i2c0; + pad_domain_all_pads_port_group_uart0_soc2pad_t uart0; + pad_domain_all_pads_port_group_qspim0_soc2pad_t qspim0; + pad_domain_all_pads_port_group_sdio0_soc2pad_t sdio0; + pad_domain_all_pads_port_group_i2s0_soc2pad_t i2s0; + pad_domain_all_pads_port_group_timer0_soc2pad_t timer0; + pad_domain_all_pads_port_group_timer1_soc2pad_t timer1; + pad_domain_all_pads_port_group_timer2_soc2pad_t timer2; + pad_domain_all_pads_port_group_timer3_soc2pad_t timer3; + } pad_domain_all_pads_ports_soc2pad_t; + + typedef struct packed { + pad_domain_all_pads_port_group_gpio_pad2soc_t gpio; + pad_domain_all_pads_port_group_i2c0_pad2soc_t i2c0; + pad_domain_all_pads_port_group_uart0_pad2soc_t uart0; + pad_domain_all_pads_port_group_qspim0_pad2soc_t qspim0; + pad_domain_all_pads_port_group_cpi0_pad2soc_t cpi0; + pad_domain_all_pads_port_group_sdio0_pad2soc_t sdio0; + pad_domain_all_pads_port_group_i2s0_pad2soc_t i2s0; + } pad_domain_all_pads_ports_pad2soc_t; + + + //Toplevel structs + + typedef struct packed { + pad_domain_all_pads_static_connection_signals_pad2soc_t all_pads; + } static_connection_signals_pad2soc_t; + + typedef struct packed { + pad_domain_all_pads_static_connection_signals_soc2pad_t all_pads; + } static_connection_signals_soc2pad_t; + + typedef struct packed { + pad_domain_all_pads_ports_pad2soc_t all_pads; + } port_signals_pad2soc_t; + + typedef struct packed { + pad_domain_all_pads_ports_soc2pad_t all_pads; + } port_signals_soc2pad_t; + + +endpackage : pkg_pulpissimo_padframe diff --git a/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/src/pulpissimo_padframe.sv b/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/src/pulpissimo_padframe.sv new file mode 100644 index 00000000..9844c485 --- /dev/null +++ b/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/src/pulpissimo_padframe.sv @@ -0,0 +1,173 @@ + +// File auto-generated by Padrick unknown +module pulpissimo_padframe + import pkg_pulpissimo_padframe::*; +#( + parameter int unsigned AW = 32, + parameter int unsigned DW = 32, + parameter type req_t = logic, // reg_interface request type + parameter type resp_t = logic, // reg_interface response type + parameter logic [DW-1:0] DecodeErrRespData = 32'hdeadda7a, + localparam int unsigned NGPIO = 32 +)( + input logic clk_i, + input logic rst_ni, + output static_connection_signals_pad2soc_t static_connection_signals_pad2soc, + input static_connection_signals_soc2pad_t static_connection_signals_soc2pad, + output port_signals_pad2soc_t port_signals_pad2soc, + input port_signals_soc2pad_t port_signals_soc2pad, + // Landing Pads + inout wire logic pad_ref_clk, + inout wire logic pad_clk_byp_en, + inout wire logic pad_reset_n, + inout wire logic pad_bootsel0, + inout wire logic pad_bootsel1, + inout wire logic pad_jtag_tck, + inout wire logic pad_jtag_trstn, + inout wire logic pad_jtag_tms, + inout wire logic pad_jtag_tdi, + inout wire logic pad_jtag_tdo, + inout wire logic pad_hyper_csn0, + inout wire logic pad_hyper_csn1, + inout wire logic pad_hyper_reset_n, + inout wire logic pad_hyper_ck, + inout wire logic pad_hyper_ckn, + inout wire logic pad_hyper_dq0, + inout wire logic pad_hyper_dq1, + inout wire logic pad_hyper_dq2, + inout wire logic pad_hyper_dq3, + inout wire logic pad_hyper_dq4, + inout wire logic pad_hyper_dq5, + inout wire logic pad_hyper_dq6, + inout wire logic pad_hyper_dq7, + inout wire logic pad_hyper_rwds, + inout wire [NGPIO-1:0] pad_io, + // Config Interface + input req_t config_req_i, + output resp_t config_rsp_o + ); + + + req_t all_pads_config_req; + resp_t all_pads_config_resp; + pulpissimo_padframe_all_pads #( + .req_t(req_t), + .resp_t(resp_t) + ) i_all_pads ( + .clk_i, + .rst_ni, + .static_connection_signals_pad2soc(static_connection_signals_pad2soc.all_pads), + .static_connection_signals_soc2pad(static_connection_signals_soc2pad.all_pads), + .port_signals_pad2soc_o(port_signals_pad2soc.all_pads), + .port_signals_soc2pad_i(port_signals_soc2pad.all_pads), + .pad_pad_ref_clk_pad(pad_ref_clk), + .pad_pad_clk_byp_en_pad(pad_clk_byp_en), + .pad_pad_reset_n_pad(pad_reset_n), + .pad_pad_bootsel0_pad(pad_bootsel0), + .pad_pad_bootsel1_pad(pad_bootsel1), + .pad_pad_jtag_tck_pad(pad_jtag_tck), + .pad_pad_jtag_trstn_pad(pad_jtag_trstn), + .pad_pad_jtag_tms_pad(pad_jtag_tms), + .pad_pad_jtag_tdi_pad(pad_jtag_tdi), + .pad_pad_jtag_tdo_pad(pad_jtag_tdo), + .pad_pad_hyper_csn0_pad(pad_hyper_csn0), + .pad_pad_hyper_csn1_pad(pad_hyper_csn1), + .pad_pad_hyper_reset_n_pad(pad_hyper_reset_n), + .pad_pad_hyper_ck_pad(pad_hyper_ck), + .pad_pad_hyper_ckn_pad(pad_hyper_ckn), + .pad_pad_hyper_dq0_pad(pad_hyper_dq0), + .pad_pad_hyper_dq1_pad(pad_hyper_dq1), + .pad_pad_hyper_dq2_pad(pad_hyper_dq2), + .pad_pad_hyper_dq3_pad(pad_hyper_dq3), + .pad_pad_hyper_dq4_pad(pad_hyper_dq4), + .pad_pad_hyper_dq5_pad(pad_hyper_dq5), + .pad_pad_hyper_dq6_pad(pad_hyper_dq6), + .pad_pad_hyper_dq7_pad(pad_hyper_dq7), + .pad_pad_hyper_rwds_pad(pad_hyper_rwds), + .pad_pad_io00_pad(pad_io[0]), + .pad_pad_io01_pad(pad_io[1]), + .pad_pad_io02_pad(pad_io[2]), + .pad_pad_io03_pad(pad_io[3]), + .pad_pad_io04_pad(pad_io[4]), + .pad_pad_io05_pad(pad_io[5]), + .pad_pad_io06_pad(pad_io[6]), + .pad_pad_io07_pad(pad_io[7]), + .pad_pad_io08_pad(pad_io[8]), + .pad_pad_io09_pad(pad_io[9]), + .pad_pad_io10_pad(pad_io[10]), + .pad_pad_io11_pad(pad_io[11]), + .pad_pad_io12_pad(pad_io[12]), + .pad_pad_io13_pad(pad_io[13]), + .pad_pad_io14_pad(pad_io[14]), + .pad_pad_io15_pad(pad_io[15]), + .pad_pad_io16_pad(pad_io[16]), + .pad_pad_io17_pad(pad_io[17]), + .pad_pad_io18_pad(pad_io[18]), + .pad_pad_io19_pad(pad_io[19]), + .pad_pad_io20_pad(pad_io[20]), + .pad_pad_io21_pad(pad_io[21]), + .pad_pad_io22_pad(pad_io[22]), + .pad_pad_io23_pad(pad_io[23]), + .pad_pad_io24_pad(pad_io[24]), + .pad_pad_io25_pad(pad_io[25]), + .pad_pad_io26_pad(pad_io[26]), + .pad_pad_io27_pad(pad_io[27]), + .pad_pad_io28_pad(pad_io[28]), + .pad_pad_io29_pad(pad_io[29]), + .pad_pad_io30_pad(pad_io[30]), + .pad_pad_io31_pad(pad_io[31]), + .config_req_i(all_pads_config_req), + .config_rsp_o(all_pads_config_resp) + ); + + + localparam int unsigned NUM_PAD_DOMAINS = 1; + localparam int unsigned REG_ADDR_WIDTH = 9; + typedef struct packed { + int unsigned idx; + logic [REG_ADDR_WIDTH-1:0] start_addr; + logic [REG_ADDR_WIDTH-1:0] end_addr; + } addr_rule_t; + + localparam addr_rule_t[NUM_PAD_DOMAINS-1:0] ADDR_DEMUX_RULES = '{ + '{ idx: 0, start_addr: 9'd0, end_addr: 9'd260} + }; + logic[$clog2(NUM_PAD_DOMAINS+1)-1:0] pad_domain_sel; // +1 since there is an additional error slave + addr_decode #( + .NoIndices(NUM_PAD_DOMAINS+1), + .NoRules(NUM_PAD_DOMAINS), + .addr_t(logic[REG_ADDR_WIDTH-1:0]), + .rule_t(addr_rule_t) + ) i_addr_decode( + .addr_i(config_req_i.addr[REG_ADDR_WIDTH-1:0]), + .addr_map_i(ADDR_DEMUX_RULES), + .dec_valid_o(), + .dec_error_o(), + .idx_o(pad_domain_sel), + .en_default_idx_i(1'b1), + .default_idx_i(1'd1) // The last entry is the error slave + ); + + req_t error_slave_req; + resp_t error_slave_rsp; + + // Config Interface demultiplexing + reg_demux #( + .NoPorts(NUM_PAD_DOMAINS+1), //+1 for the error slave + .req_t(req_t), + .rsp_t(resp_t) + ) i_config_demuxer ( + .clk_i, + .rst_ni, + .in_select_i(pad_domain_sel), + .in_req_i(config_req_i), + .in_rsp_o(config_rsp_o), + .out_req_o({error_slave_req, all_pads_config_req}), + .out_rsp_i({error_slave_rsp, all_pads_config_resp}) + ); + + assign error_slave_rsp.error = 1'b1; + assign error_slave_rsp.rdata = DecodeErrRespData; + assign error_slave_rsp.ready = 1'b1; + +endmodule diff --git a/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/src/pulpissimo_padframe_all_pads.sv b/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/src/pulpissimo_padframe_all_pads.sv new file mode 100644 index 00000000..73eaeb4b --- /dev/null +++ b/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/src/pulpissimo_padframe_all_pads.sv @@ -0,0 +1,158 @@ + +// File auto-generated by Padrick unknown +module pulpissimo_padframe_all_pads + import pkg_pulpissimo_padframe::*; + import pkg_internal_pulpissimo_padframe_all_pads::*; +#( + parameter type req_t = logic, // reg_interface request type + parameter type resp_t = logic // reg_interface response type +) ( + input logic clk_i, + input logic rst_ni, + output pad_domain_all_pads_static_connection_signals_pad2soc_t static_connection_signals_pad2soc, + input pad_domain_all_pads_static_connection_signals_soc2pad_t static_connection_signals_soc2pad, + output pad_domain_all_pads_ports_pad2soc_t port_signals_pad2soc_o, + input pad_domain_all_pads_ports_soc2pad_t port_signals_soc2pad_i, + inout wire logic pad_pad_ref_clk_pad, + inout wire logic pad_pad_clk_byp_en_pad, + inout wire logic pad_pad_reset_n_pad, + inout wire logic pad_pad_bootsel0_pad, + inout wire logic pad_pad_bootsel1_pad, + inout wire logic pad_pad_jtag_tck_pad, + inout wire logic pad_pad_jtag_trstn_pad, + inout wire logic pad_pad_jtag_tms_pad, + inout wire logic pad_pad_jtag_tdi_pad, + inout wire logic pad_pad_jtag_tdo_pad, + inout wire logic pad_pad_hyper_csn0_pad, + inout wire logic pad_pad_hyper_csn1_pad, + inout wire logic pad_pad_hyper_reset_n_pad, + inout wire logic pad_pad_hyper_ck_pad, + inout wire logic pad_pad_hyper_ckn_pad, + inout wire logic pad_pad_hyper_dq0_pad, + inout wire logic pad_pad_hyper_dq1_pad, + inout wire logic pad_pad_hyper_dq2_pad, + inout wire logic pad_pad_hyper_dq3_pad, + inout wire logic pad_pad_hyper_dq4_pad, + inout wire logic pad_pad_hyper_dq5_pad, + inout wire logic pad_pad_hyper_dq6_pad, + inout wire logic pad_pad_hyper_dq7_pad, + inout wire logic pad_pad_hyper_rwds_pad, + inout wire logic pad_pad_io00_pad, + inout wire logic pad_pad_io01_pad, + inout wire logic pad_pad_io02_pad, + inout wire logic pad_pad_io03_pad, + inout wire logic pad_pad_io04_pad, + inout wire logic pad_pad_io05_pad, + inout wire logic pad_pad_io06_pad, + inout wire logic pad_pad_io07_pad, + inout wire logic pad_pad_io08_pad, + inout wire logic pad_pad_io09_pad, + inout wire logic pad_pad_io10_pad, + inout wire logic pad_pad_io11_pad, + inout wire logic pad_pad_io12_pad, + inout wire logic pad_pad_io13_pad, + inout wire logic pad_pad_io14_pad, + inout wire logic pad_pad_io15_pad, + inout wire logic pad_pad_io16_pad, + inout wire logic pad_pad_io17_pad, + inout wire logic pad_pad_io18_pad, + inout wire logic pad_pad_io19_pad, + inout wire logic pad_pad_io20_pad, + inout wire logic pad_pad_io21_pad, + inout wire logic pad_pad_io22_pad, + inout wire logic pad_pad_io23_pad, + inout wire logic pad_pad_io24_pad, + inout wire logic pad_pad_io25_pad, + inout wire logic pad_pad_io26_pad, + inout wire logic pad_pad_io27_pad, + inout wire logic pad_pad_io28_pad, + inout wire logic pad_pad_io29_pad, + inout wire logic pad_pad_io30_pad, + inout wire logic pad_pad_io31_pad, + input req_t config_req_i, + output resp_t config_rsp_o +); + + mux_to_pads_t s_mux_to_pads; + pads_to_mux_t s_pads_to_mux; + + pulpissimo_padframe_all_pads_pads i_all_pads_pads ( + .static_connection_signals_pad2soc, + .static_connection_signals_soc2pad, + .mux_to_pads_i(s_mux_to_pads), + .pads_to_mux_o(s_pads_to_mux), + .pad_pad_ref_clk_pad, + .pad_pad_clk_byp_en_pad, + .pad_pad_reset_n_pad, + .pad_pad_bootsel0_pad, + .pad_pad_bootsel1_pad, + .pad_pad_jtag_tck_pad, + .pad_pad_jtag_trstn_pad, + .pad_pad_jtag_tms_pad, + .pad_pad_jtag_tdi_pad, + .pad_pad_jtag_tdo_pad, + .pad_pad_hyper_csn0_pad, + .pad_pad_hyper_csn1_pad, + .pad_pad_hyper_reset_n_pad, + .pad_pad_hyper_ck_pad, + .pad_pad_hyper_ckn_pad, + .pad_pad_hyper_dq0_pad, + .pad_pad_hyper_dq1_pad, + .pad_pad_hyper_dq2_pad, + .pad_pad_hyper_dq3_pad, + .pad_pad_hyper_dq4_pad, + .pad_pad_hyper_dq5_pad, + .pad_pad_hyper_dq6_pad, + .pad_pad_hyper_dq7_pad, + .pad_pad_hyper_rwds_pad, + .pad_pad_io00_pad, + .pad_pad_io01_pad, + .pad_pad_io02_pad, + .pad_pad_io03_pad, + .pad_pad_io04_pad, + .pad_pad_io05_pad, + .pad_pad_io06_pad, + .pad_pad_io07_pad, + .pad_pad_io08_pad, + .pad_pad_io09_pad, + .pad_pad_io10_pad, + .pad_pad_io11_pad, + .pad_pad_io12_pad, + .pad_pad_io13_pad, + .pad_pad_io14_pad, + .pad_pad_io15_pad, + .pad_pad_io16_pad, + .pad_pad_io17_pad, + .pad_pad_io18_pad, + .pad_pad_io19_pad, + .pad_pad_io20_pad, + .pad_pad_io21_pad, + .pad_pad_io22_pad, + .pad_pad_io23_pad, + .pad_pad_io24_pad, + .pad_pad_io25_pad, + .pad_pad_io26_pad, + .pad_pad_io27_pad, + .pad_pad_io28_pad, + .pad_pad_io29_pad, + .pad_pad_io30_pad, + .pad_pad_io31_pad + + ); + + pulpissimo_padframe_all_pads_muxer #( + .req_t(req_t), + .resp_t(resp_t) + )i_all_pads_muxer ( + .clk_i, + .rst_ni, + .port_signals_soc2pad_i, + .port_signals_pad2soc_o, + .mux_to_pads_o(s_mux_to_pads), + .pads_to_mux_i(s_pads_to_mux), + // Configuration interface using register_interface protocol + .config_req_i, + .config_rsp_o + ); + +endmodule : pulpissimo_padframe_all_pads diff --git a/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/src/pulpissimo_padframe_all_pads_config_reg_pkg.sv b/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/src/pulpissimo_padframe_all_pads_config_reg_pkg.sv new file mode 100644 index 00000000..5b5571ea --- /dev/null +++ b/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/src/pulpissimo_padframe_all_pads_config_reg_pkg.sv @@ -0,0 +1,908 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package pulpissimo_padframe_all_pads_config_reg_pkg; + + // Address widths within the block + parameter int BlockAw = 9; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + struct packed { + logic [15:0] q; + } hw_version; + struct packed { + logic [15:0] q; + } padcount; + } pulpissimo_padframe_all_pads_config_reg2hw_info_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io00_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io00_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io01_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io01_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io02_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io02_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io03_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io03_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io04_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io04_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io05_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io05_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io06_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io06_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io07_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io07_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io08_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io08_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io09_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io09_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io10_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io10_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io11_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io11_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io12_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io12_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io13_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io13_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io14_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io14_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io15_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io15_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io16_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io16_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io17_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io17_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io18_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io18_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io19_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io19_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io20_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io20_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io21_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io21_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io22_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io22_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io23_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io23_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io24_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io24_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io25_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io25_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io26_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io26_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io27_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io27_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io28_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io28_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io29_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io29_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io30_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io30_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } rx_en; + struct packed { + logic q; + } tx_en; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io31_cfg_reg_t; + + typedef struct packed { + logic [5:0] q; + } pulpissimo_padframe_all_pads_config_reg2hw_pad_io31_mux_sel_reg_t; + + // Register -> HW type + typedef struct packed { + pulpissimo_padframe_all_pads_config_reg2hw_info_reg_t info; // [351:320] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io00_cfg_reg_t pad_io00_cfg; // [319:316] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io00_mux_sel_reg_t pad_io00_mux_sel; // [315:310] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io01_cfg_reg_t pad_io01_cfg; // [309:306] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io01_mux_sel_reg_t pad_io01_mux_sel; // [305:300] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io02_cfg_reg_t pad_io02_cfg; // [299:296] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io02_mux_sel_reg_t pad_io02_mux_sel; // [295:290] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io03_cfg_reg_t pad_io03_cfg; // [289:286] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io03_mux_sel_reg_t pad_io03_mux_sel; // [285:280] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io04_cfg_reg_t pad_io04_cfg; // [279:276] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io04_mux_sel_reg_t pad_io04_mux_sel; // [275:270] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io05_cfg_reg_t pad_io05_cfg; // [269:266] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io05_mux_sel_reg_t pad_io05_mux_sel; // [265:260] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io06_cfg_reg_t pad_io06_cfg; // [259:256] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io06_mux_sel_reg_t pad_io06_mux_sel; // [255:250] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io07_cfg_reg_t pad_io07_cfg; // [249:246] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io07_mux_sel_reg_t pad_io07_mux_sel; // [245:240] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io08_cfg_reg_t pad_io08_cfg; // [239:236] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io08_mux_sel_reg_t pad_io08_mux_sel; // [235:230] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io09_cfg_reg_t pad_io09_cfg; // [229:226] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io09_mux_sel_reg_t pad_io09_mux_sel; // [225:220] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io10_cfg_reg_t pad_io10_cfg; // [219:216] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io10_mux_sel_reg_t pad_io10_mux_sel; // [215:210] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io11_cfg_reg_t pad_io11_cfg; // [209:206] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io11_mux_sel_reg_t pad_io11_mux_sel; // [205:200] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io12_cfg_reg_t pad_io12_cfg; // [199:196] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io12_mux_sel_reg_t pad_io12_mux_sel; // [195:190] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io13_cfg_reg_t pad_io13_cfg; // [189:186] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io13_mux_sel_reg_t pad_io13_mux_sel; // [185:180] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io14_cfg_reg_t pad_io14_cfg; // [179:176] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io14_mux_sel_reg_t pad_io14_mux_sel; // [175:170] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io15_cfg_reg_t pad_io15_cfg; // [169:166] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io15_mux_sel_reg_t pad_io15_mux_sel; // [165:160] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io16_cfg_reg_t pad_io16_cfg; // [159:156] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io16_mux_sel_reg_t pad_io16_mux_sel; // [155:150] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io17_cfg_reg_t pad_io17_cfg; // [149:146] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io17_mux_sel_reg_t pad_io17_mux_sel; // [145:140] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io18_cfg_reg_t pad_io18_cfg; // [139:136] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io18_mux_sel_reg_t pad_io18_mux_sel; // [135:130] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io19_cfg_reg_t pad_io19_cfg; // [129:126] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io19_mux_sel_reg_t pad_io19_mux_sel; // [125:120] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io20_cfg_reg_t pad_io20_cfg; // [119:116] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io20_mux_sel_reg_t pad_io20_mux_sel; // [115:110] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io21_cfg_reg_t pad_io21_cfg; // [109:106] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io21_mux_sel_reg_t pad_io21_mux_sel; // [105:100] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io22_cfg_reg_t pad_io22_cfg; // [99:96] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io22_mux_sel_reg_t pad_io22_mux_sel; // [95:90] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io23_cfg_reg_t pad_io23_cfg; // [89:86] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io23_mux_sel_reg_t pad_io23_mux_sel; // [85:80] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io24_cfg_reg_t pad_io24_cfg; // [79:76] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io24_mux_sel_reg_t pad_io24_mux_sel; // [75:70] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io25_cfg_reg_t pad_io25_cfg; // [69:66] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io25_mux_sel_reg_t pad_io25_mux_sel; // [65:60] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io26_cfg_reg_t pad_io26_cfg; // [59:56] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io26_mux_sel_reg_t pad_io26_mux_sel; // [55:50] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io27_cfg_reg_t pad_io27_cfg; // [49:46] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io27_mux_sel_reg_t pad_io27_mux_sel; // [45:40] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io28_cfg_reg_t pad_io28_cfg; // [39:36] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io28_mux_sel_reg_t pad_io28_mux_sel; // [35:30] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io29_cfg_reg_t pad_io29_cfg; // [29:26] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io29_mux_sel_reg_t pad_io29_mux_sel; // [25:20] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io30_cfg_reg_t pad_io30_cfg; // [19:16] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io30_mux_sel_reg_t pad_io30_mux_sel; // [15:10] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io31_cfg_reg_t pad_io31_cfg; // [9:6] + pulpissimo_padframe_all_pads_config_reg2hw_pad_io31_mux_sel_reg_t pad_io31_mux_sel; // [5:0] + } pulpissimo_padframe_all_pads_config_reg2hw_t; + + // Register offsets + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_OFFSET = 9'h 0; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_OFFSET = 9'h 4; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_OFFSET = 9'h 8; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_CFG_OFFSET = 9'h c; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_OFFSET = 9'h 10; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_CFG_OFFSET = 9'h 14; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_OFFSET = 9'h 18; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_CFG_OFFSET = 9'h 1c; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_OFFSET = 9'h 20; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_CFG_OFFSET = 9'h 24; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_OFFSET = 9'h 28; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_CFG_OFFSET = 9'h 2c; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_OFFSET = 9'h 30; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_CFG_OFFSET = 9'h 34; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_OFFSET = 9'h 38; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_CFG_OFFSET = 9'h 3c; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_OFFSET = 9'h 40; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_CFG_OFFSET = 9'h 44; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_OFFSET = 9'h 48; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_CFG_OFFSET = 9'h 4c; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_OFFSET = 9'h 50; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_CFG_OFFSET = 9'h 54; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_OFFSET = 9'h 58; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_CFG_OFFSET = 9'h 5c; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_OFFSET = 9'h 60; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_CFG_OFFSET = 9'h 64; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_OFFSET = 9'h 68; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_CFG_OFFSET = 9'h 6c; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_OFFSET = 9'h 70; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_CFG_OFFSET = 9'h 74; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_OFFSET = 9'h 78; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_CFG_OFFSET = 9'h 7c; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_OFFSET = 9'h 80; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_CFG_OFFSET = 9'h 84; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_OFFSET = 9'h 88; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_CFG_OFFSET = 9'h 8c; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_OFFSET = 9'h 90; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_CFG_OFFSET = 9'h 94; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_OFFSET = 9'h 98; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_CFG_OFFSET = 9'h 9c; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_OFFSET = 9'h a0; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_CFG_OFFSET = 9'h a4; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_OFFSET = 9'h a8; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_CFG_OFFSET = 9'h ac; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_OFFSET = 9'h b0; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_CFG_OFFSET = 9'h b4; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_OFFSET = 9'h b8; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_CFG_OFFSET = 9'h bc; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_OFFSET = 9'h c0; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_CFG_OFFSET = 9'h c4; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_OFFSET = 9'h c8; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_CFG_OFFSET = 9'h cc; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_OFFSET = 9'h d0; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_CFG_OFFSET = 9'h d4; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_OFFSET = 9'h d8; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_CFG_OFFSET = 9'h dc; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_OFFSET = 9'h e0; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_CFG_OFFSET = 9'h e4; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_OFFSET = 9'h e8; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_CFG_OFFSET = 9'h ec; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_OFFSET = 9'h f0; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_CFG_OFFSET = 9'h f4; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_OFFSET = 9'h f8; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_CFG_OFFSET = 9'h fc; + parameter logic [BlockAw-1:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_OFFSET = 9'h 100; + + // Register index + typedef enum int { + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_CFG, + PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL + } pulpissimo_padframe_all_pads_config_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT [65] = '{ + 4'b 1111, // index[ 0] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO + 4'b 0001, // index[ 1] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG + 4'b 0001, // index[ 2] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL + 4'b 0001, // index[ 3] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_CFG + 4'b 0001, // index[ 4] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL + 4'b 0001, // index[ 5] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_CFG + 4'b 0001, // index[ 6] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL + 4'b 0001, // index[ 7] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_CFG + 4'b 0001, // index[ 8] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL + 4'b 0001, // index[ 9] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_CFG + 4'b 0001, // index[10] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL + 4'b 0001, // index[11] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_CFG + 4'b 0001, // index[12] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL + 4'b 0001, // index[13] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_CFG + 4'b 0001, // index[14] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL + 4'b 0001, // index[15] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_CFG + 4'b 0001, // index[16] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL + 4'b 0001, // index[17] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_CFG + 4'b 0001, // index[18] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL + 4'b 0001, // index[19] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_CFG + 4'b 0001, // index[20] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL + 4'b 0001, // index[21] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_CFG + 4'b 0001, // index[22] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL + 4'b 0001, // index[23] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_CFG + 4'b 0001, // index[24] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL + 4'b 0001, // index[25] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_CFG + 4'b 0001, // index[26] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL + 4'b 0001, // index[27] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_CFG + 4'b 0001, // index[28] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL + 4'b 0001, // index[29] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_CFG + 4'b 0001, // index[30] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL + 4'b 0001, // index[31] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_CFG + 4'b 0001, // index[32] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL + 4'b 0001, // index[33] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_CFG + 4'b 0001, // index[34] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL + 4'b 0001, // index[35] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_CFG + 4'b 0001, // index[36] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL + 4'b 0001, // index[37] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_CFG + 4'b 0001, // index[38] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL + 4'b 0001, // index[39] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_CFG + 4'b 0001, // index[40] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL + 4'b 0001, // index[41] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_CFG + 4'b 0001, // index[42] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL + 4'b 0001, // index[43] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_CFG + 4'b 0001, // index[44] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL + 4'b 0001, // index[45] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_CFG + 4'b 0001, // index[46] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL + 4'b 0001, // index[47] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_CFG + 4'b 0001, // index[48] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL + 4'b 0001, // index[49] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_CFG + 4'b 0001, // index[50] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL + 4'b 0001, // index[51] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_CFG + 4'b 0001, // index[52] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL + 4'b 0001, // index[53] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_CFG + 4'b 0001, // index[54] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL + 4'b 0001, // index[55] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_CFG + 4'b 0001, // index[56] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL + 4'b 0001, // index[57] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_CFG + 4'b 0001, // index[58] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL + 4'b 0001, // index[59] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_CFG + 4'b 0001, // index[60] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL + 4'b 0001, // index[61] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_CFG + 4'b 0001, // index[62] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL + 4'b 0001, // index[63] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_CFG + 4'b 0001 // index[64] PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL + }; + +endpackage + diff --git a/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/src/pulpissimo_padframe_all_pads_config_reg_top.sv b/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/src/pulpissimo_padframe_all_pads_config_reg_top.sv new file mode 100644 index 00000000..a1f3665b --- /dev/null +++ b/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/src/pulpissimo_padframe_all_pads_config_reg_top.sv @@ -0,0 +1,5865 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + + +`include "common_cells/assertions.svh" + +module pulpissimo_padframe_all_pads_config_reg_top #( + parameter type reg_req_t = logic, + parameter type reg_rsp_t = logic, + parameter int AW = 9 +) ( + input clk_i, + input rst_ni, + input reg_req_t reg_req_i, + output reg_rsp_t reg_rsp_o, + // To HW + output pulpissimo_padframe_all_pads_config_reg_pkg::pulpissimo_padframe_all_pads_config_reg2hw_t reg2hw, // Write + + + // Config + input devmode_i // If 1, explicit error return for unmapped register access +); + + import pulpissimo_padframe_all_pads_config_reg_pkg::* ; + + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + + // Below register interface can be changed + reg_req_t reg_intf_req; + reg_rsp_t reg_intf_rsp; + + + assign reg_intf_req = reg_req_i; + assign reg_rsp_o = reg_intf_rsp; + + + assign reg_we = reg_intf_req.valid & reg_intf_req.write; + assign reg_re = reg_intf_req.valid & ~reg_intf_req.write; + assign reg_addr = reg_intf_req.addr; + assign reg_wdata = reg_intf_req.wdata; + assign reg_be = reg_intf_req.wstrb; + assign reg_intf_rsp.rdata = reg_rdata; + assign reg_intf_rsp.error = reg_error; + assign reg_intf_rsp.ready = 1'b1; + + assign reg_rdata = reg_rdata_next ; + assign reg_error = (devmode_i & addrmiss) | wr_err; + + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic [15:0] info_hw_version_qs; + logic [15:0] info_padcount_qs; + logic pad_io00_cfg_chip2pad_qs; + logic pad_io00_cfg_chip2pad_wd; + logic pad_io00_cfg_chip2pad_we; + logic pad_io00_cfg_pull_en_qs; + logic pad_io00_cfg_pull_en_wd; + logic pad_io00_cfg_pull_en_we; + logic pad_io00_cfg_rx_en_qs; + logic pad_io00_cfg_rx_en_wd; + logic pad_io00_cfg_rx_en_we; + logic pad_io00_cfg_tx_en_qs; + logic pad_io00_cfg_tx_en_wd; + logic pad_io00_cfg_tx_en_we; + logic [5:0] pad_io00_mux_sel_qs; + logic [5:0] pad_io00_mux_sel_wd; + logic pad_io00_mux_sel_we; + logic pad_io01_cfg_chip2pad_qs; + logic pad_io01_cfg_chip2pad_wd; + logic pad_io01_cfg_chip2pad_we; + logic pad_io01_cfg_pull_en_qs; + logic pad_io01_cfg_pull_en_wd; + logic pad_io01_cfg_pull_en_we; + logic pad_io01_cfg_rx_en_qs; + logic pad_io01_cfg_rx_en_wd; + logic pad_io01_cfg_rx_en_we; + logic pad_io01_cfg_tx_en_qs; + logic pad_io01_cfg_tx_en_wd; + logic pad_io01_cfg_tx_en_we; + logic [5:0] pad_io01_mux_sel_qs; + logic [5:0] pad_io01_mux_sel_wd; + logic pad_io01_mux_sel_we; + logic pad_io02_cfg_chip2pad_qs; + logic pad_io02_cfg_chip2pad_wd; + logic pad_io02_cfg_chip2pad_we; + logic pad_io02_cfg_pull_en_qs; + logic pad_io02_cfg_pull_en_wd; + logic pad_io02_cfg_pull_en_we; + logic pad_io02_cfg_rx_en_qs; + logic pad_io02_cfg_rx_en_wd; + logic pad_io02_cfg_rx_en_we; + logic pad_io02_cfg_tx_en_qs; + logic pad_io02_cfg_tx_en_wd; + logic pad_io02_cfg_tx_en_we; + logic [5:0] pad_io02_mux_sel_qs; + logic [5:0] pad_io02_mux_sel_wd; + logic pad_io02_mux_sel_we; + logic pad_io03_cfg_chip2pad_qs; + logic pad_io03_cfg_chip2pad_wd; + logic pad_io03_cfg_chip2pad_we; + logic pad_io03_cfg_pull_en_qs; + logic pad_io03_cfg_pull_en_wd; + logic pad_io03_cfg_pull_en_we; + logic pad_io03_cfg_rx_en_qs; + logic pad_io03_cfg_rx_en_wd; + logic pad_io03_cfg_rx_en_we; + logic pad_io03_cfg_tx_en_qs; + logic pad_io03_cfg_tx_en_wd; + logic pad_io03_cfg_tx_en_we; + logic [5:0] pad_io03_mux_sel_qs; + logic [5:0] pad_io03_mux_sel_wd; + logic pad_io03_mux_sel_we; + logic pad_io04_cfg_chip2pad_qs; + logic pad_io04_cfg_chip2pad_wd; + logic pad_io04_cfg_chip2pad_we; + logic pad_io04_cfg_pull_en_qs; + logic pad_io04_cfg_pull_en_wd; + logic pad_io04_cfg_pull_en_we; + logic pad_io04_cfg_rx_en_qs; + logic pad_io04_cfg_rx_en_wd; + logic pad_io04_cfg_rx_en_we; + logic pad_io04_cfg_tx_en_qs; + logic pad_io04_cfg_tx_en_wd; + logic pad_io04_cfg_tx_en_we; + logic [5:0] pad_io04_mux_sel_qs; + logic [5:0] pad_io04_mux_sel_wd; + logic pad_io04_mux_sel_we; + logic pad_io05_cfg_chip2pad_qs; + logic pad_io05_cfg_chip2pad_wd; + logic pad_io05_cfg_chip2pad_we; + logic pad_io05_cfg_pull_en_qs; + logic pad_io05_cfg_pull_en_wd; + logic pad_io05_cfg_pull_en_we; + logic pad_io05_cfg_rx_en_qs; + logic pad_io05_cfg_rx_en_wd; + logic pad_io05_cfg_rx_en_we; + logic pad_io05_cfg_tx_en_qs; + logic pad_io05_cfg_tx_en_wd; + logic pad_io05_cfg_tx_en_we; + logic [5:0] pad_io05_mux_sel_qs; + logic [5:0] pad_io05_mux_sel_wd; + logic pad_io05_mux_sel_we; + logic pad_io06_cfg_chip2pad_qs; + logic pad_io06_cfg_chip2pad_wd; + logic pad_io06_cfg_chip2pad_we; + logic pad_io06_cfg_pull_en_qs; + logic pad_io06_cfg_pull_en_wd; + logic pad_io06_cfg_pull_en_we; + logic pad_io06_cfg_rx_en_qs; + logic pad_io06_cfg_rx_en_wd; + logic pad_io06_cfg_rx_en_we; + logic pad_io06_cfg_tx_en_qs; + logic pad_io06_cfg_tx_en_wd; + logic pad_io06_cfg_tx_en_we; + logic [5:0] pad_io06_mux_sel_qs; + logic [5:0] pad_io06_mux_sel_wd; + logic pad_io06_mux_sel_we; + logic pad_io07_cfg_chip2pad_qs; + logic pad_io07_cfg_chip2pad_wd; + logic pad_io07_cfg_chip2pad_we; + logic pad_io07_cfg_pull_en_qs; + logic pad_io07_cfg_pull_en_wd; + logic pad_io07_cfg_pull_en_we; + logic pad_io07_cfg_rx_en_qs; + logic pad_io07_cfg_rx_en_wd; + logic pad_io07_cfg_rx_en_we; + logic pad_io07_cfg_tx_en_qs; + logic pad_io07_cfg_tx_en_wd; + logic pad_io07_cfg_tx_en_we; + logic [5:0] pad_io07_mux_sel_qs; + logic [5:0] pad_io07_mux_sel_wd; + logic pad_io07_mux_sel_we; + logic pad_io08_cfg_chip2pad_qs; + logic pad_io08_cfg_chip2pad_wd; + logic pad_io08_cfg_chip2pad_we; + logic pad_io08_cfg_pull_en_qs; + logic pad_io08_cfg_pull_en_wd; + logic pad_io08_cfg_pull_en_we; + logic pad_io08_cfg_rx_en_qs; + logic pad_io08_cfg_rx_en_wd; + logic pad_io08_cfg_rx_en_we; + logic pad_io08_cfg_tx_en_qs; + logic pad_io08_cfg_tx_en_wd; + logic pad_io08_cfg_tx_en_we; + logic [5:0] pad_io08_mux_sel_qs; + logic [5:0] pad_io08_mux_sel_wd; + logic pad_io08_mux_sel_we; + logic pad_io09_cfg_chip2pad_qs; + logic pad_io09_cfg_chip2pad_wd; + logic pad_io09_cfg_chip2pad_we; + logic pad_io09_cfg_pull_en_qs; + logic pad_io09_cfg_pull_en_wd; + logic pad_io09_cfg_pull_en_we; + logic pad_io09_cfg_rx_en_qs; + logic pad_io09_cfg_rx_en_wd; + logic pad_io09_cfg_rx_en_we; + logic pad_io09_cfg_tx_en_qs; + logic pad_io09_cfg_tx_en_wd; + logic pad_io09_cfg_tx_en_we; + logic [5:0] pad_io09_mux_sel_qs; + logic [5:0] pad_io09_mux_sel_wd; + logic pad_io09_mux_sel_we; + logic pad_io10_cfg_chip2pad_qs; + logic pad_io10_cfg_chip2pad_wd; + logic pad_io10_cfg_chip2pad_we; + logic pad_io10_cfg_pull_en_qs; + logic pad_io10_cfg_pull_en_wd; + logic pad_io10_cfg_pull_en_we; + logic pad_io10_cfg_rx_en_qs; + logic pad_io10_cfg_rx_en_wd; + logic pad_io10_cfg_rx_en_we; + logic pad_io10_cfg_tx_en_qs; + logic pad_io10_cfg_tx_en_wd; + logic pad_io10_cfg_tx_en_we; + logic [5:0] pad_io10_mux_sel_qs; + logic [5:0] pad_io10_mux_sel_wd; + logic pad_io10_mux_sel_we; + logic pad_io11_cfg_chip2pad_qs; + logic pad_io11_cfg_chip2pad_wd; + logic pad_io11_cfg_chip2pad_we; + logic pad_io11_cfg_pull_en_qs; + logic pad_io11_cfg_pull_en_wd; + logic pad_io11_cfg_pull_en_we; + logic pad_io11_cfg_rx_en_qs; + logic pad_io11_cfg_rx_en_wd; + logic pad_io11_cfg_rx_en_we; + logic pad_io11_cfg_tx_en_qs; + logic pad_io11_cfg_tx_en_wd; + logic pad_io11_cfg_tx_en_we; + logic [5:0] pad_io11_mux_sel_qs; + logic [5:0] pad_io11_mux_sel_wd; + logic pad_io11_mux_sel_we; + logic pad_io12_cfg_chip2pad_qs; + logic pad_io12_cfg_chip2pad_wd; + logic pad_io12_cfg_chip2pad_we; + logic pad_io12_cfg_pull_en_qs; + logic pad_io12_cfg_pull_en_wd; + logic pad_io12_cfg_pull_en_we; + logic pad_io12_cfg_rx_en_qs; + logic pad_io12_cfg_rx_en_wd; + logic pad_io12_cfg_rx_en_we; + logic pad_io12_cfg_tx_en_qs; + logic pad_io12_cfg_tx_en_wd; + logic pad_io12_cfg_tx_en_we; + logic [5:0] pad_io12_mux_sel_qs; + logic [5:0] pad_io12_mux_sel_wd; + logic pad_io12_mux_sel_we; + logic pad_io13_cfg_chip2pad_qs; + logic pad_io13_cfg_chip2pad_wd; + logic pad_io13_cfg_chip2pad_we; + logic pad_io13_cfg_pull_en_qs; + logic pad_io13_cfg_pull_en_wd; + logic pad_io13_cfg_pull_en_we; + logic pad_io13_cfg_rx_en_qs; + logic pad_io13_cfg_rx_en_wd; + logic pad_io13_cfg_rx_en_we; + logic pad_io13_cfg_tx_en_qs; + logic pad_io13_cfg_tx_en_wd; + logic pad_io13_cfg_tx_en_we; + logic [5:0] pad_io13_mux_sel_qs; + logic [5:0] pad_io13_mux_sel_wd; + logic pad_io13_mux_sel_we; + logic pad_io14_cfg_chip2pad_qs; + logic pad_io14_cfg_chip2pad_wd; + logic pad_io14_cfg_chip2pad_we; + logic pad_io14_cfg_pull_en_qs; + logic pad_io14_cfg_pull_en_wd; + logic pad_io14_cfg_pull_en_we; + logic pad_io14_cfg_rx_en_qs; + logic pad_io14_cfg_rx_en_wd; + logic pad_io14_cfg_rx_en_we; + logic pad_io14_cfg_tx_en_qs; + logic pad_io14_cfg_tx_en_wd; + logic pad_io14_cfg_tx_en_we; + logic [5:0] pad_io14_mux_sel_qs; + logic [5:0] pad_io14_mux_sel_wd; + logic pad_io14_mux_sel_we; + logic pad_io15_cfg_chip2pad_qs; + logic pad_io15_cfg_chip2pad_wd; + logic pad_io15_cfg_chip2pad_we; + logic pad_io15_cfg_pull_en_qs; + logic pad_io15_cfg_pull_en_wd; + logic pad_io15_cfg_pull_en_we; + logic pad_io15_cfg_rx_en_qs; + logic pad_io15_cfg_rx_en_wd; + logic pad_io15_cfg_rx_en_we; + logic pad_io15_cfg_tx_en_qs; + logic pad_io15_cfg_tx_en_wd; + logic pad_io15_cfg_tx_en_we; + logic [5:0] pad_io15_mux_sel_qs; + logic [5:0] pad_io15_mux_sel_wd; + logic pad_io15_mux_sel_we; + logic pad_io16_cfg_chip2pad_qs; + logic pad_io16_cfg_chip2pad_wd; + logic pad_io16_cfg_chip2pad_we; + logic pad_io16_cfg_pull_en_qs; + logic pad_io16_cfg_pull_en_wd; + logic pad_io16_cfg_pull_en_we; + logic pad_io16_cfg_rx_en_qs; + logic pad_io16_cfg_rx_en_wd; + logic pad_io16_cfg_rx_en_we; + logic pad_io16_cfg_tx_en_qs; + logic pad_io16_cfg_tx_en_wd; + logic pad_io16_cfg_tx_en_we; + logic [5:0] pad_io16_mux_sel_qs; + logic [5:0] pad_io16_mux_sel_wd; + logic pad_io16_mux_sel_we; + logic pad_io17_cfg_chip2pad_qs; + logic pad_io17_cfg_chip2pad_wd; + logic pad_io17_cfg_chip2pad_we; + logic pad_io17_cfg_pull_en_qs; + logic pad_io17_cfg_pull_en_wd; + logic pad_io17_cfg_pull_en_we; + logic pad_io17_cfg_rx_en_qs; + logic pad_io17_cfg_rx_en_wd; + logic pad_io17_cfg_rx_en_we; + logic pad_io17_cfg_tx_en_qs; + logic pad_io17_cfg_tx_en_wd; + logic pad_io17_cfg_tx_en_we; + logic [5:0] pad_io17_mux_sel_qs; + logic [5:0] pad_io17_mux_sel_wd; + logic pad_io17_mux_sel_we; + logic pad_io18_cfg_chip2pad_qs; + logic pad_io18_cfg_chip2pad_wd; + logic pad_io18_cfg_chip2pad_we; + logic pad_io18_cfg_pull_en_qs; + logic pad_io18_cfg_pull_en_wd; + logic pad_io18_cfg_pull_en_we; + logic pad_io18_cfg_rx_en_qs; + logic pad_io18_cfg_rx_en_wd; + logic pad_io18_cfg_rx_en_we; + logic pad_io18_cfg_tx_en_qs; + logic pad_io18_cfg_tx_en_wd; + logic pad_io18_cfg_tx_en_we; + logic [5:0] pad_io18_mux_sel_qs; + logic [5:0] pad_io18_mux_sel_wd; + logic pad_io18_mux_sel_we; + logic pad_io19_cfg_chip2pad_qs; + logic pad_io19_cfg_chip2pad_wd; + logic pad_io19_cfg_chip2pad_we; + logic pad_io19_cfg_pull_en_qs; + logic pad_io19_cfg_pull_en_wd; + logic pad_io19_cfg_pull_en_we; + logic pad_io19_cfg_rx_en_qs; + logic pad_io19_cfg_rx_en_wd; + logic pad_io19_cfg_rx_en_we; + logic pad_io19_cfg_tx_en_qs; + logic pad_io19_cfg_tx_en_wd; + logic pad_io19_cfg_tx_en_we; + logic [5:0] pad_io19_mux_sel_qs; + logic [5:0] pad_io19_mux_sel_wd; + logic pad_io19_mux_sel_we; + logic pad_io20_cfg_chip2pad_qs; + logic pad_io20_cfg_chip2pad_wd; + logic pad_io20_cfg_chip2pad_we; + logic pad_io20_cfg_pull_en_qs; + logic pad_io20_cfg_pull_en_wd; + logic pad_io20_cfg_pull_en_we; + logic pad_io20_cfg_rx_en_qs; + logic pad_io20_cfg_rx_en_wd; + logic pad_io20_cfg_rx_en_we; + logic pad_io20_cfg_tx_en_qs; + logic pad_io20_cfg_tx_en_wd; + logic pad_io20_cfg_tx_en_we; + logic [5:0] pad_io20_mux_sel_qs; + logic [5:0] pad_io20_mux_sel_wd; + logic pad_io20_mux_sel_we; + logic pad_io21_cfg_chip2pad_qs; + logic pad_io21_cfg_chip2pad_wd; + logic pad_io21_cfg_chip2pad_we; + logic pad_io21_cfg_pull_en_qs; + logic pad_io21_cfg_pull_en_wd; + logic pad_io21_cfg_pull_en_we; + logic pad_io21_cfg_rx_en_qs; + logic pad_io21_cfg_rx_en_wd; + logic pad_io21_cfg_rx_en_we; + logic pad_io21_cfg_tx_en_qs; + logic pad_io21_cfg_tx_en_wd; + logic pad_io21_cfg_tx_en_we; + logic [5:0] pad_io21_mux_sel_qs; + logic [5:0] pad_io21_mux_sel_wd; + logic pad_io21_mux_sel_we; + logic pad_io22_cfg_chip2pad_qs; + logic pad_io22_cfg_chip2pad_wd; + logic pad_io22_cfg_chip2pad_we; + logic pad_io22_cfg_pull_en_qs; + logic pad_io22_cfg_pull_en_wd; + logic pad_io22_cfg_pull_en_we; + logic pad_io22_cfg_rx_en_qs; + logic pad_io22_cfg_rx_en_wd; + logic pad_io22_cfg_rx_en_we; + logic pad_io22_cfg_tx_en_qs; + logic pad_io22_cfg_tx_en_wd; + logic pad_io22_cfg_tx_en_we; + logic [5:0] pad_io22_mux_sel_qs; + logic [5:0] pad_io22_mux_sel_wd; + logic pad_io22_mux_sel_we; + logic pad_io23_cfg_chip2pad_qs; + logic pad_io23_cfg_chip2pad_wd; + logic pad_io23_cfg_chip2pad_we; + logic pad_io23_cfg_pull_en_qs; + logic pad_io23_cfg_pull_en_wd; + logic pad_io23_cfg_pull_en_we; + logic pad_io23_cfg_rx_en_qs; + logic pad_io23_cfg_rx_en_wd; + logic pad_io23_cfg_rx_en_we; + logic pad_io23_cfg_tx_en_qs; + logic pad_io23_cfg_tx_en_wd; + logic pad_io23_cfg_tx_en_we; + logic [5:0] pad_io23_mux_sel_qs; + logic [5:0] pad_io23_mux_sel_wd; + logic pad_io23_mux_sel_we; + logic pad_io24_cfg_chip2pad_qs; + logic pad_io24_cfg_chip2pad_wd; + logic pad_io24_cfg_chip2pad_we; + logic pad_io24_cfg_pull_en_qs; + logic pad_io24_cfg_pull_en_wd; + logic pad_io24_cfg_pull_en_we; + logic pad_io24_cfg_rx_en_qs; + logic pad_io24_cfg_rx_en_wd; + logic pad_io24_cfg_rx_en_we; + logic pad_io24_cfg_tx_en_qs; + logic pad_io24_cfg_tx_en_wd; + logic pad_io24_cfg_tx_en_we; + logic [5:0] pad_io24_mux_sel_qs; + logic [5:0] pad_io24_mux_sel_wd; + logic pad_io24_mux_sel_we; + logic pad_io25_cfg_chip2pad_qs; + logic pad_io25_cfg_chip2pad_wd; + logic pad_io25_cfg_chip2pad_we; + logic pad_io25_cfg_pull_en_qs; + logic pad_io25_cfg_pull_en_wd; + logic pad_io25_cfg_pull_en_we; + logic pad_io25_cfg_rx_en_qs; + logic pad_io25_cfg_rx_en_wd; + logic pad_io25_cfg_rx_en_we; + logic pad_io25_cfg_tx_en_qs; + logic pad_io25_cfg_tx_en_wd; + logic pad_io25_cfg_tx_en_we; + logic [5:0] pad_io25_mux_sel_qs; + logic [5:0] pad_io25_mux_sel_wd; + logic pad_io25_mux_sel_we; + logic pad_io26_cfg_chip2pad_qs; + logic pad_io26_cfg_chip2pad_wd; + logic pad_io26_cfg_chip2pad_we; + logic pad_io26_cfg_pull_en_qs; + logic pad_io26_cfg_pull_en_wd; + logic pad_io26_cfg_pull_en_we; + logic pad_io26_cfg_rx_en_qs; + logic pad_io26_cfg_rx_en_wd; + logic pad_io26_cfg_rx_en_we; + logic pad_io26_cfg_tx_en_qs; + logic pad_io26_cfg_tx_en_wd; + logic pad_io26_cfg_tx_en_we; + logic [5:0] pad_io26_mux_sel_qs; + logic [5:0] pad_io26_mux_sel_wd; + logic pad_io26_mux_sel_we; + logic pad_io27_cfg_chip2pad_qs; + logic pad_io27_cfg_chip2pad_wd; + logic pad_io27_cfg_chip2pad_we; + logic pad_io27_cfg_pull_en_qs; + logic pad_io27_cfg_pull_en_wd; + logic pad_io27_cfg_pull_en_we; + logic pad_io27_cfg_rx_en_qs; + logic pad_io27_cfg_rx_en_wd; + logic pad_io27_cfg_rx_en_we; + logic pad_io27_cfg_tx_en_qs; + logic pad_io27_cfg_tx_en_wd; + logic pad_io27_cfg_tx_en_we; + logic [5:0] pad_io27_mux_sel_qs; + logic [5:0] pad_io27_mux_sel_wd; + logic pad_io27_mux_sel_we; + logic pad_io28_cfg_chip2pad_qs; + logic pad_io28_cfg_chip2pad_wd; + logic pad_io28_cfg_chip2pad_we; + logic pad_io28_cfg_pull_en_qs; + logic pad_io28_cfg_pull_en_wd; + logic pad_io28_cfg_pull_en_we; + logic pad_io28_cfg_rx_en_qs; + logic pad_io28_cfg_rx_en_wd; + logic pad_io28_cfg_rx_en_we; + logic pad_io28_cfg_tx_en_qs; + logic pad_io28_cfg_tx_en_wd; + logic pad_io28_cfg_tx_en_we; + logic [5:0] pad_io28_mux_sel_qs; + logic [5:0] pad_io28_mux_sel_wd; + logic pad_io28_mux_sel_we; + logic pad_io29_cfg_chip2pad_qs; + logic pad_io29_cfg_chip2pad_wd; + logic pad_io29_cfg_chip2pad_we; + logic pad_io29_cfg_pull_en_qs; + logic pad_io29_cfg_pull_en_wd; + logic pad_io29_cfg_pull_en_we; + logic pad_io29_cfg_rx_en_qs; + logic pad_io29_cfg_rx_en_wd; + logic pad_io29_cfg_rx_en_we; + logic pad_io29_cfg_tx_en_qs; + logic pad_io29_cfg_tx_en_wd; + logic pad_io29_cfg_tx_en_we; + logic [5:0] pad_io29_mux_sel_qs; + logic [5:0] pad_io29_mux_sel_wd; + logic pad_io29_mux_sel_we; + logic pad_io30_cfg_chip2pad_qs; + logic pad_io30_cfg_chip2pad_wd; + logic pad_io30_cfg_chip2pad_we; + logic pad_io30_cfg_pull_en_qs; + logic pad_io30_cfg_pull_en_wd; + logic pad_io30_cfg_pull_en_we; + logic pad_io30_cfg_rx_en_qs; + logic pad_io30_cfg_rx_en_wd; + logic pad_io30_cfg_rx_en_we; + logic pad_io30_cfg_tx_en_qs; + logic pad_io30_cfg_tx_en_wd; + logic pad_io30_cfg_tx_en_we; + logic [5:0] pad_io30_mux_sel_qs; + logic [5:0] pad_io30_mux_sel_wd; + logic pad_io30_mux_sel_we; + logic pad_io31_cfg_chip2pad_qs; + logic pad_io31_cfg_chip2pad_wd; + logic pad_io31_cfg_chip2pad_we; + logic pad_io31_cfg_pull_en_qs; + logic pad_io31_cfg_pull_en_wd; + logic pad_io31_cfg_pull_en_we; + logic pad_io31_cfg_rx_en_qs; + logic pad_io31_cfg_rx_en_wd; + logic pad_io31_cfg_rx_en_we; + logic pad_io31_cfg_tx_en_qs; + logic pad_io31_cfg_tx_en_wd; + logic pad_io31_cfg_tx_en_we; + logic [5:0] pad_io31_mux_sel_qs; + logic [5:0] pad_io31_mux_sel_wd; + logic pad_io31_mux_sel_we; + + // Register instances + // R[info]: V(False) + + // F[hw_version]: 15:0 + prim_subreg #( + .DW (16), + .SWACCESS("RO"), + .RESVAL (16'h2) + ) u_info_hw_version ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.info.hw_version.q ), + + // to register interface (read) + .qs (info_hw_version_qs) + ); + + + // F[padcount]: 31:16 + prim_subreg #( + .DW (16), + .SWACCESS("RO"), + .RESVAL (16'h20) + ) u_info_padcount ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.info.padcount.q ), + + // to register interface (read) + .qs (info_padcount_qs) + ); + + + // R[pad_io00_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io00_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io00_cfg_chip2pad_we), + .wd (pad_io00_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io00_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io00_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io00_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io00_cfg_pull_en_we), + .wd (pad_io00_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io00_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io00_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io00_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io00_cfg_rx_en_we), + .wd (pad_io00_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io00_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io00_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io00_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io00_cfg_tx_en_we), + .wd (pad_io00_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io00_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io00_cfg_tx_en_qs) + ); + + + // R[pad_io00_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io00_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io00_mux_sel_we), + .wd (pad_io00_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io00_mux_sel.q ), + + // to register interface (read) + .qs (pad_io00_mux_sel_qs) + ); + + + // R[pad_io01_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io01_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io01_cfg_chip2pad_we), + .wd (pad_io01_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io01_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io01_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io01_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io01_cfg_pull_en_we), + .wd (pad_io01_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io01_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io01_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io01_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io01_cfg_rx_en_we), + .wd (pad_io01_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io01_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io01_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io01_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io01_cfg_tx_en_we), + .wd (pad_io01_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io01_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io01_cfg_tx_en_qs) + ); + + + // R[pad_io01_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io01_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io01_mux_sel_we), + .wd (pad_io01_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io01_mux_sel.q ), + + // to register interface (read) + .qs (pad_io01_mux_sel_qs) + ); + + + // R[pad_io02_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io02_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io02_cfg_chip2pad_we), + .wd (pad_io02_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io02_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io02_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io02_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io02_cfg_pull_en_we), + .wd (pad_io02_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io02_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io02_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io02_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io02_cfg_rx_en_we), + .wd (pad_io02_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io02_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io02_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io02_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io02_cfg_tx_en_we), + .wd (pad_io02_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io02_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io02_cfg_tx_en_qs) + ); + + + // R[pad_io02_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io02_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io02_mux_sel_we), + .wd (pad_io02_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io02_mux_sel.q ), + + // to register interface (read) + .qs (pad_io02_mux_sel_qs) + ); + + + // R[pad_io03_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io03_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io03_cfg_chip2pad_we), + .wd (pad_io03_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io03_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io03_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io03_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io03_cfg_pull_en_we), + .wd (pad_io03_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io03_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io03_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io03_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io03_cfg_rx_en_we), + .wd (pad_io03_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io03_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io03_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io03_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io03_cfg_tx_en_we), + .wd (pad_io03_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io03_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io03_cfg_tx_en_qs) + ); + + + // R[pad_io03_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io03_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io03_mux_sel_we), + .wd (pad_io03_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io03_mux_sel.q ), + + // to register interface (read) + .qs (pad_io03_mux_sel_qs) + ); + + + // R[pad_io04_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io04_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io04_cfg_chip2pad_we), + .wd (pad_io04_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io04_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io04_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io04_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io04_cfg_pull_en_we), + .wd (pad_io04_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io04_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io04_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io04_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io04_cfg_rx_en_we), + .wd (pad_io04_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io04_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io04_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io04_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io04_cfg_tx_en_we), + .wd (pad_io04_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io04_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io04_cfg_tx_en_qs) + ); + + + // R[pad_io04_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io04_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io04_mux_sel_we), + .wd (pad_io04_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io04_mux_sel.q ), + + // to register interface (read) + .qs (pad_io04_mux_sel_qs) + ); + + + // R[pad_io05_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io05_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io05_cfg_chip2pad_we), + .wd (pad_io05_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io05_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io05_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io05_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io05_cfg_pull_en_we), + .wd (pad_io05_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io05_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io05_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io05_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io05_cfg_rx_en_we), + .wd (pad_io05_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io05_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io05_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io05_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io05_cfg_tx_en_we), + .wd (pad_io05_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io05_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io05_cfg_tx_en_qs) + ); + + + // R[pad_io05_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io05_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io05_mux_sel_we), + .wd (pad_io05_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io05_mux_sel.q ), + + // to register interface (read) + .qs (pad_io05_mux_sel_qs) + ); + + + // R[pad_io06_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io06_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io06_cfg_chip2pad_we), + .wd (pad_io06_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io06_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io06_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io06_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io06_cfg_pull_en_we), + .wd (pad_io06_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io06_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io06_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io06_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io06_cfg_rx_en_we), + .wd (pad_io06_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io06_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io06_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io06_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io06_cfg_tx_en_we), + .wd (pad_io06_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io06_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io06_cfg_tx_en_qs) + ); + + + // R[pad_io06_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io06_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io06_mux_sel_we), + .wd (pad_io06_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io06_mux_sel.q ), + + // to register interface (read) + .qs (pad_io06_mux_sel_qs) + ); + + + // R[pad_io07_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io07_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io07_cfg_chip2pad_we), + .wd (pad_io07_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io07_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io07_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io07_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io07_cfg_pull_en_we), + .wd (pad_io07_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io07_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io07_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io07_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io07_cfg_rx_en_we), + .wd (pad_io07_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io07_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io07_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io07_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io07_cfg_tx_en_we), + .wd (pad_io07_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io07_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io07_cfg_tx_en_qs) + ); + + + // R[pad_io07_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io07_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io07_mux_sel_we), + .wd (pad_io07_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io07_mux_sel.q ), + + // to register interface (read) + .qs (pad_io07_mux_sel_qs) + ); + + + // R[pad_io08_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io08_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io08_cfg_chip2pad_we), + .wd (pad_io08_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io08_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io08_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io08_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io08_cfg_pull_en_we), + .wd (pad_io08_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io08_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io08_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io08_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io08_cfg_rx_en_we), + .wd (pad_io08_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io08_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io08_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io08_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io08_cfg_tx_en_we), + .wd (pad_io08_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io08_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io08_cfg_tx_en_qs) + ); + + + // R[pad_io08_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io08_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io08_mux_sel_we), + .wd (pad_io08_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io08_mux_sel.q ), + + // to register interface (read) + .qs (pad_io08_mux_sel_qs) + ); + + + // R[pad_io09_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io09_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io09_cfg_chip2pad_we), + .wd (pad_io09_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io09_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io09_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io09_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io09_cfg_pull_en_we), + .wd (pad_io09_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io09_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io09_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io09_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io09_cfg_rx_en_we), + .wd (pad_io09_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io09_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io09_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io09_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io09_cfg_tx_en_we), + .wd (pad_io09_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io09_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io09_cfg_tx_en_qs) + ); + + + // R[pad_io09_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io09_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io09_mux_sel_we), + .wd (pad_io09_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io09_mux_sel.q ), + + // to register interface (read) + .qs (pad_io09_mux_sel_qs) + ); + + + // R[pad_io10_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io10_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io10_cfg_chip2pad_we), + .wd (pad_io10_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io10_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io10_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io10_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io10_cfg_pull_en_we), + .wd (pad_io10_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io10_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io10_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io10_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io10_cfg_rx_en_we), + .wd (pad_io10_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io10_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io10_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io10_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io10_cfg_tx_en_we), + .wd (pad_io10_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io10_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io10_cfg_tx_en_qs) + ); + + + // R[pad_io10_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io10_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io10_mux_sel_we), + .wd (pad_io10_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io10_mux_sel.q ), + + // to register interface (read) + .qs (pad_io10_mux_sel_qs) + ); + + + // R[pad_io11_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io11_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io11_cfg_chip2pad_we), + .wd (pad_io11_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io11_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io11_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io11_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io11_cfg_pull_en_we), + .wd (pad_io11_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io11_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io11_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io11_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io11_cfg_rx_en_we), + .wd (pad_io11_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io11_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io11_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io11_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io11_cfg_tx_en_we), + .wd (pad_io11_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io11_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io11_cfg_tx_en_qs) + ); + + + // R[pad_io11_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io11_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io11_mux_sel_we), + .wd (pad_io11_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io11_mux_sel.q ), + + // to register interface (read) + .qs (pad_io11_mux_sel_qs) + ); + + + // R[pad_io12_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io12_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io12_cfg_chip2pad_we), + .wd (pad_io12_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io12_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io12_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io12_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io12_cfg_pull_en_we), + .wd (pad_io12_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io12_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io12_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io12_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io12_cfg_rx_en_we), + .wd (pad_io12_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io12_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io12_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io12_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io12_cfg_tx_en_we), + .wd (pad_io12_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io12_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io12_cfg_tx_en_qs) + ); + + + // R[pad_io12_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io12_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io12_mux_sel_we), + .wd (pad_io12_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io12_mux_sel.q ), + + // to register interface (read) + .qs (pad_io12_mux_sel_qs) + ); + + + // R[pad_io13_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io13_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io13_cfg_chip2pad_we), + .wd (pad_io13_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io13_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io13_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io13_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io13_cfg_pull_en_we), + .wd (pad_io13_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io13_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io13_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io13_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io13_cfg_rx_en_we), + .wd (pad_io13_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io13_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io13_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io13_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io13_cfg_tx_en_we), + .wd (pad_io13_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io13_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io13_cfg_tx_en_qs) + ); + + + // R[pad_io13_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io13_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io13_mux_sel_we), + .wd (pad_io13_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io13_mux_sel.q ), + + // to register interface (read) + .qs (pad_io13_mux_sel_qs) + ); + + + // R[pad_io14_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io14_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io14_cfg_chip2pad_we), + .wd (pad_io14_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io14_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io14_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io14_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io14_cfg_pull_en_we), + .wd (pad_io14_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io14_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io14_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io14_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io14_cfg_rx_en_we), + .wd (pad_io14_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io14_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io14_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io14_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io14_cfg_tx_en_we), + .wd (pad_io14_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io14_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io14_cfg_tx_en_qs) + ); + + + // R[pad_io14_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io14_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io14_mux_sel_we), + .wd (pad_io14_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io14_mux_sel.q ), + + // to register interface (read) + .qs (pad_io14_mux_sel_qs) + ); + + + // R[pad_io15_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io15_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io15_cfg_chip2pad_we), + .wd (pad_io15_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io15_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io15_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io15_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io15_cfg_pull_en_we), + .wd (pad_io15_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io15_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io15_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io15_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io15_cfg_rx_en_we), + .wd (pad_io15_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io15_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io15_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io15_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io15_cfg_tx_en_we), + .wd (pad_io15_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io15_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io15_cfg_tx_en_qs) + ); + + + // R[pad_io15_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io15_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io15_mux_sel_we), + .wd (pad_io15_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io15_mux_sel.q ), + + // to register interface (read) + .qs (pad_io15_mux_sel_qs) + ); + + + // R[pad_io16_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io16_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io16_cfg_chip2pad_we), + .wd (pad_io16_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io16_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io16_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io16_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io16_cfg_pull_en_we), + .wd (pad_io16_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io16_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io16_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io16_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io16_cfg_rx_en_we), + .wd (pad_io16_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io16_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io16_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io16_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io16_cfg_tx_en_we), + .wd (pad_io16_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io16_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io16_cfg_tx_en_qs) + ); + + + // R[pad_io16_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io16_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io16_mux_sel_we), + .wd (pad_io16_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io16_mux_sel.q ), + + // to register interface (read) + .qs (pad_io16_mux_sel_qs) + ); + + + // R[pad_io17_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io17_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io17_cfg_chip2pad_we), + .wd (pad_io17_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io17_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io17_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io17_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io17_cfg_pull_en_we), + .wd (pad_io17_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io17_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io17_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io17_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io17_cfg_rx_en_we), + .wd (pad_io17_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io17_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io17_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io17_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io17_cfg_tx_en_we), + .wd (pad_io17_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io17_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io17_cfg_tx_en_qs) + ); + + + // R[pad_io17_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io17_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io17_mux_sel_we), + .wd (pad_io17_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io17_mux_sel.q ), + + // to register interface (read) + .qs (pad_io17_mux_sel_qs) + ); + + + // R[pad_io18_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io18_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io18_cfg_chip2pad_we), + .wd (pad_io18_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io18_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io18_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io18_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io18_cfg_pull_en_we), + .wd (pad_io18_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io18_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io18_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io18_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io18_cfg_rx_en_we), + .wd (pad_io18_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io18_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io18_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io18_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io18_cfg_tx_en_we), + .wd (pad_io18_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io18_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io18_cfg_tx_en_qs) + ); + + + // R[pad_io18_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io18_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io18_mux_sel_we), + .wd (pad_io18_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io18_mux_sel.q ), + + // to register interface (read) + .qs (pad_io18_mux_sel_qs) + ); + + + // R[pad_io19_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io19_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io19_cfg_chip2pad_we), + .wd (pad_io19_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io19_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io19_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io19_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io19_cfg_pull_en_we), + .wd (pad_io19_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io19_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io19_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io19_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io19_cfg_rx_en_we), + .wd (pad_io19_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io19_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io19_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io19_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io19_cfg_tx_en_we), + .wd (pad_io19_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io19_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io19_cfg_tx_en_qs) + ); + + + // R[pad_io19_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io19_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io19_mux_sel_we), + .wd (pad_io19_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io19_mux_sel.q ), + + // to register interface (read) + .qs (pad_io19_mux_sel_qs) + ); + + + // R[pad_io20_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io20_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io20_cfg_chip2pad_we), + .wd (pad_io20_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io20_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io20_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io20_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io20_cfg_pull_en_we), + .wd (pad_io20_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io20_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io20_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io20_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io20_cfg_rx_en_we), + .wd (pad_io20_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io20_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io20_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io20_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io20_cfg_tx_en_we), + .wd (pad_io20_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io20_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io20_cfg_tx_en_qs) + ); + + + // R[pad_io20_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io20_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io20_mux_sel_we), + .wd (pad_io20_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io20_mux_sel.q ), + + // to register interface (read) + .qs (pad_io20_mux_sel_qs) + ); + + + // R[pad_io21_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io21_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io21_cfg_chip2pad_we), + .wd (pad_io21_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io21_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io21_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io21_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io21_cfg_pull_en_we), + .wd (pad_io21_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io21_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io21_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io21_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io21_cfg_rx_en_we), + .wd (pad_io21_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io21_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io21_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io21_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io21_cfg_tx_en_we), + .wd (pad_io21_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io21_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io21_cfg_tx_en_qs) + ); + + + // R[pad_io21_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io21_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io21_mux_sel_we), + .wd (pad_io21_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io21_mux_sel.q ), + + // to register interface (read) + .qs (pad_io21_mux_sel_qs) + ); + + + // R[pad_io22_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io22_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io22_cfg_chip2pad_we), + .wd (pad_io22_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io22_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io22_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io22_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io22_cfg_pull_en_we), + .wd (pad_io22_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io22_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io22_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io22_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io22_cfg_rx_en_we), + .wd (pad_io22_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io22_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io22_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io22_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io22_cfg_tx_en_we), + .wd (pad_io22_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io22_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io22_cfg_tx_en_qs) + ); + + + // R[pad_io22_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io22_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io22_mux_sel_we), + .wd (pad_io22_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io22_mux_sel.q ), + + // to register interface (read) + .qs (pad_io22_mux_sel_qs) + ); + + + // R[pad_io23_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io23_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io23_cfg_chip2pad_we), + .wd (pad_io23_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io23_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io23_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io23_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io23_cfg_pull_en_we), + .wd (pad_io23_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io23_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io23_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io23_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io23_cfg_rx_en_we), + .wd (pad_io23_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io23_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io23_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io23_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io23_cfg_tx_en_we), + .wd (pad_io23_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io23_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io23_cfg_tx_en_qs) + ); + + + // R[pad_io23_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io23_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io23_mux_sel_we), + .wd (pad_io23_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io23_mux_sel.q ), + + // to register interface (read) + .qs (pad_io23_mux_sel_qs) + ); + + + // R[pad_io24_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io24_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io24_cfg_chip2pad_we), + .wd (pad_io24_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io24_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io24_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io24_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io24_cfg_pull_en_we), + .wd (pad_io24_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io24_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io24_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io24_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io24_cfg_rx_en_we), + .wd (pad_io24_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io24_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io24_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io24_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io24_cfg_tx_en_we), + .wd (pad_io24_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io24_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io24_cfg_tx_en_qs) + ); + + + // R[pad_io24_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io24_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io24_mux_sel_we), + .wd (pad_io24_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io24_mux_sel.q ), + + // to register interface (read) + .qs (pad_io24_mux_sel_qs) + ); + + + // R[pad_io25_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io25_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io25_cfg_chip2pad_we), + .wd (pad_io25_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io25_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io25_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io25_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io25_cfg_pull_en_we), + .wd (pad_io25_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io25_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io25_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io25_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io25_cfg_rx_en_we), + .wd (pad_io25_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io25_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io25_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io25_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io25_cfg_tx_en_we), + .wd (pad_io25_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io25_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io25_cfg_tx_en_qs) + ); + + + // R[pad_io25_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io25_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io25_mux_sel_we), + .wd (pad_io25_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io25_mux_sel.q ), + + // to register interface (read) + .qs (pad_io25_mux_sel_qs) + ); + + + // R[pad_io26_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io26_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io26_cfg_chip2pad_we), + .wd (pad_io26_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io26_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io26_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io26_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io26_cfg_pull_en_we), + .wd (pad_io26_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io26_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io26_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io26_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io26_cfg_rx_en_we), + .wd (pad_io26_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io26_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io26_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io26_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io26_cfg_tx_en_we), + .wd (pad_io26_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io26_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io26_cfg_tx_en_qs) + ); + + + // R[pad_io26_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io26_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io26_mux_sel_we), + .wd (pad_io26_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io26_mux_sel.q ), + + // to register interface (read) + .qs (pad_io26_mux_sel_qs) + ); + + + // R[pad_io27_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io27_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io27_cfg_chip2pad_we), + .wd (pad_io27_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io27_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io27_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io27_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io27_cfg_pull_en_we), + .wd (pad_io27_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io27_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io27_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io27_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io27_cfg_rx_en_we), + .wd (pad_io27_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io27_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io27_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io27_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io27_cfg_tx_en_we), + .wd (pad_io27_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io27_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io27_cfg_tx_en_qs) + ); + + + // R[pad_io27_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io27_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io27_mux_sel_we), + .wd (pad_io27_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io27_mux_sel.q ), + + // to register interface (read) + .qs (pad_io27_mux_sel_qs) + ); + + + // R[pad_io28_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io28_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io28_cfg_chip2pad_we), + .wd (pad_io28_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io28_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io28_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io28_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io28_cfg_pull_en_we), + .wd (pad_io28_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io28_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io28_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io28_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io28_cfg_rx_en_we), + .wd (pad_io28_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io28_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io28_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io28_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io28_cfg_tx_en_we), + .wd (pad_io28_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io28_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io28_cfg_tx_en_qs) + ); + + + // R[pad_io28_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io28_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io28_mux_sel_we), + .wd (pad_io28_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io28_mux_sel.q ), + + // to register interface (read) + .qs (pad_io28_mux_sel_qs) + ); + + + // R[pad_io29_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io29_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io29_cfg_chip2pad_we), + .wd (pad_io29_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io29_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io29_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io29_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io29_cfg_pull_en_we), + .wd (pad_io29_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io29_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io29_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io29_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io29_cfg_rx_en_we), + .wd (pad_io29_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io29_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io29_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io29_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io29_cfg_tx_en_we), + .wd (pad_io29_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io29_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io29_cfg_tx_en_qs) + ); + + + // R[pad_io29_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io29_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io29_mux_sel_we), + .wd (pad_io29_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io29_mux_sel.q ), + + // to register interface (read) + .qs (pad_io29_mux_sel_qs) + ); + + + // R[pad_io30_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io30_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io30_cfg_chip2pad_we), + .wd (pad_io30_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io30_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io30_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io30_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io30_cfg_pull_en_we), + .wd (pad_io30_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io30_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io30_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io30_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io30_cfg_rx_en_we), + .wd (pad_io30_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io30_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io30_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io30_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io30_cfg_tx_en_we), + .wd (pad_io30_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io30_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io30_cfg_tx_en_qs) + ); + + + // R[pad_io30_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io30_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io30_mux_sel_we), + .wd (pad_io30_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io30_mux_sel.q ), + + // to register interface (read) + .qs (pad_io30_mux_sel_qs) + ); + + + // R[pad_io31_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io31_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io31_cfg_chip2pad_we), + .wd (pad_io31_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io31_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io31_cfg_chip2pad_qs) + ); + + + // F[pull_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io31_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io31_cfg_pull_en_we), + .wd (pad_io31_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io31_cfg.pull_en.q ), + + // to register interface (read) + .qs (pad_io31_cfg_pull_en_qs) + ); + + + // F[rx_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io31_cfg_rx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io31_cfg_rx_en_we), + .wd (pad_io31_cfg_rx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io31_cfg.rx_en.q ), + + // to register interface (read) + .qs (pad_io31_cfg_rx_en_qs) + ); + + + // F[tx_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io31_cfg_tx_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io31_cfg_tx_en_we), + .wd (pad_io31_cfg_tx_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io31_cfg.tx_en.q ), + + // to register interface (read) + .qs (pad_io31_cfg_tx_en_qs) + ); + + + // R[pad_io31_mux_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'he) + ) u_pad_io31_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io31_mux_sel_we), + .wd (pad_io31_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io31_mux_sel.q ), + + // to register interface (read) + .qs (pad_io31_mux_sel_qs) + ); + + + + + logic [64:0] addr_hit; + always_comb begin + addr_hit = '0; + addr_hit[ 0] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_OFFSET); + addr_hit[ 1] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_OFFSET); + addr_hit[ 2] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_OFFSET); + addr_hit[ 3] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_CFG_OFFSET); + addr_hit[ 4] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_OFFSET); + addr_hit[ 5] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_CFG_OFFSET); + addr_hit[ 6] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_OFFSET); + addr_hit[ 7] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_CFG_OFFSET); + addr_hit[ 8] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_OFFSET); + addr_hit[ 9] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_CFG_OFFSET); + addr_hit[10] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_OFFSET); + addr_hit[11] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_CFG_OFFSET); + addr_hit[12] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_OFFSET); + addr_hit[13] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_CFG_OFFSET); + addr_hit[14] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_OFFSET); + addr_hit[15] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_CFG_OFFSET); + addr_hit[16] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_OFFSET); + addr_hit[17] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_CFG_OFFSET); + addr_hit[18] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_OFFSET); + addr_hit[19] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_CFG_OFFSET); + addr_hit[20] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_OFFSET); + addr_hit[21] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_CFG_OFFSET); + addr_hit[22] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_OFFSET); + addr_hit[23] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_CFG_OFFSET); + addr_hit[24] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_OFFSET); + addr_hit[25] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_CFG_OFFSET); + addr_hit[26] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_OFFSET); + addr_hit[27] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_CFG_OFFSET); + addr_hit[28] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_OFFSET); + addr_hit[29] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_CFG_OFFSET); + addr_hit[30] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_OFFSET); + addr_hit[31] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_CFG_OFFSET); + addr_hit[32] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_OFFSET); + addr_hit[33] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_CFG_OFFSET); + addr_hit[34] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_OFFSET); + addr_hit[35] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_CFG_OFFSET); + addr_hit[36] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_OFFSET); + addr_hit[37] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_CFG_OFFSET); + addr_hit[38] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_OFFSET); + addr_hit[39] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_CFG_OFFSET); + addr_hit[40] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_OFFSET); + addr_hit[41] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_CFG_OFFSET); + addr_hit[42] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_OFFSET); + addr_hit[43] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_CFG_OFFSET); + addr_hit[44] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_OFFSET); + addr_hit[45] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_CFG_OFFSET); + addr_hit[46] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_OFFSET); + addr_hit[47] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_CFG_OFFSET); + addr_hit[48] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_OFFSET); + addr_hit[49] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_CFG_OFFSET); + addr_hit[50] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_OFFSET); + addr_hit[51] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_CFG_OFFSET); + addr_hit[52] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_OFFSET); + addr_hit[53] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_CFG_OFFSET); + addr_hit[54] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_OFFSET); + addr_hit[55] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_CFG_OFFSET); + addr_hit[56] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_OFFSET); + addr_hit[57] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_CFG_OFFSET); + addr_hit[58] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_OFFSET); + addr_hit[59] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_CFG_OFFSET); + addr_hit[60] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_OFFSET); + addr_hit[61] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_CFG_OFFSET); + addr_hit[62] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_OFFSET); + addr_hit[63] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_CFG_OFFSET); + addr_hit[64] = (reg_addr == PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[ 9] & ~reg_be))) | + (addr_hit[10] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[10] & ~reg_be))) | + (addr_hit[11] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[11] & ~reg_be))) | + (addr_hit[12] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[12] & ~reg_be))) | + (addr_hit[13] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[13] & ~reg_be))) | + (addr_hit[14] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[14] & ~reg_be))) | + (addr_hit[15] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[15] & ~reg_be))) | + (addr_hit[16] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[16] & ~reg_be))) | + (addr_hit[17] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[17] & ~reg_be))) | + (addr_hit[18] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[18] & ~reg_be))) | + (addr_hit[19] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[19] & ~reg_be))) | + (addr_hit[20] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[20] & ~reg_be))) | + (addr_hit[21] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[21] & ~reg_be))) | + (addr_hit[22] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[22] & ~reg_be))) | + (addr_hit[23] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[23] & ~reg_be))) | + (addr_hit[24] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[24] & ~reg_be))) | + (addr_hit[25] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[25] & ~reg_be))) | + (addr_hit[26] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[26] & ~reg_be))) | + (addr_hit[27] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[27] & ~reg_be))) | + (addr_hit[28] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[28] & ~reg_be))) | + (addr_hit[29] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[29] & ~reg_be))) | + (addr_hit[30] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[30] & ~reg_be))) | + (addr_hit[31] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[31] & ~reg_be))) | + (addr_hit[32] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[32] & ~reg_be))) | + (addr_hit[33] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[33] & ~reg_be))) | + (addr_hit[34] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[34] & ~reg_be))) | + (addr_hit[35] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[35] & ~reg_be))) | + (addr_hit[36] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[36] & ~reg_be))) | + (addr_hit[37] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[37] & ~reg_be))) | + (addr_hit[38] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[38] & ~reg_be))) | + (addr_hit[39] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[39] & ~reg_be))) | + (addr_hit[40] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[40] & ~reg_be))) | + (addr_hit[41] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[41] & ~reg_be))) | + (addr_hit[42] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[42] & ~reg_be))) | + (addr_hit[43] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[43] & ~reg_be))) | + (addr_hit[44] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[44] & ~reg_be))) | + (addr_hit[45] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[45] & ~reg_be))) | + (addr_hit[46] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[46] & ~reg_be))) | + (addr_hit[47] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[47] & ~reg_be))) | + (addr_hit[48] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[48] & ~reg_be))) | + (addr_hit[49] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[49] & ~reg_be))) | + (addr_hit[50] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[50] & ~reg_be))) | + (addr_hit[51] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[51] & ~reg_be))) | + (addr_hit[52] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[52] & ~reg_be))) | + (addr_hit[53] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[53] & ~reg_be))) | + (addr_hit[54] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[54] & ~reg_be))) | + (addr_hit[55] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[55] & ~reg_be))) | + (addr_hit[56] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[56] & ~reg_be))) | + (addr_hit[57] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[57] & ~reg_be))) | + (addr_hit[58] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[58] & ~reg_be))) | + (addr_hit[59] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[59] & ~reg_be))) | + (addr_hit[60] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[60] & ~reg_be))) | + (addr_hit[61] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[61] & ~reg_be))) | + (addr_hit[62] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[62] & ~reg_be))) | + (addr_hit[63] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[63] & ~reg_be))) | + (addr_hit[64] & (|(PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PERMIT[64] & ~reg_be))))); + end + + assign pad_io00_cfg_chip2pad_we = addr_hit[1] & reg_we & !reg_error; + assign pad_io00_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io00_cfg_pull_en_we = addr_hit[1] & reg_we & !reg_error; + assign pad_io00_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io00_cfg_rx_en_we = addr_hit[1] & reg_we & !reg_error; + assign pad_io00_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io00_cfg_tx_en_we = addr_hit[1] & reg_we & !reg_error; + assign pad_io00_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io00_mux_sel_we = addr_hit[2] & reg_we & !reg_error; + assign pad_io00_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io01_cfg_chip2pad_we = addr_hit[3] & reg_we & !reg_error; + assign pad_io01_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io01_cfg_pull_en_we = addr_hit[3] & reg_we & !reg_error; + assign pad_io01_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io01_cfg_rx_en_we = addr_hit[3] & reg_we & !reg_error; + assign pad_io01_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io01_cfg_tx_en_we = addr_hit[3] & reg_we & !reg_error; + assign pad_io01_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io01_mux_sel_we = addr_hit[4] & reg_we & !reg_error; + assign pad_io01_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io02_cfg_chip2pad_we = addr_hit[5] & reg_we & !reg_error; + assign pad_io02_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io02_cfg_pull_en_we = addr_hit[5] & reg_we & !reg_error; + assign pad_io02_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io02_cfg_rx_en_we = addr_hit[5] & reg_we & !reg_error; + assign pad_io02_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io02_cfg_tx_en_we = addr_hit[5] & reg_we & !reg_error; + assign pad_io02_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io02_mux_sel_we = addr_hit[6] & reg_we & !reg_error; + assign pad_io02_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io03_cfg_chip2pad_we = addr_hit[7] & reg_we & !reg_error; + assign pad_io03_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io03_cfg_pull_en_we = addr_hit[7] & reg_we & !reg_error; + assign pad_io03_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io03_cfg_rx_en_we = addr_hit[7] & reg_we & !reg_error; + assign pad_io03_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io03_cfg_tx_en_we = addr_hit[7] & reg_we & !reg_error; + assign pad_io03_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io03_mux_sel_we = addr_hit[8] & reg_we & !reg_error; + assign pad_io03_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io04_cfg_chip2pad_we = addr_hit[9] & reg_we & !reg_error; + assign pad_io04_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io04_cfg_pull_en_we = addr_hit[9] & reg_we & !reg_error; + assign pad_io04_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io04_cfg_rx_en_we = addr_hit[9] & reg_we & !reg_error; + assign pad_io04_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io04_cfg_tx_en_we = addr_hit[9] & reg_we & !reg_error; + assign pad_io04_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io04_mux_sel_we = addr_hit[10] & reg_we & !reg_error; + assign pad_io04_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io05_cfg_chip2pad_we = addr_hit[11] & reg_we & !reg_error; + assign pad_io05_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io05_cfg_pull_en_we = addr_hit[11] & reg_we & !reg_error; + assign pad_io05_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io05_cfg_rx_en_we = addr_hit[11] & reg_we & !reg_error; + assign pad_io05_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io05_cfg_tx_en_we = addr_hit[11] & reg_we & !reg_error; + assign pad_io05_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io05_mux_sel_we = addr_hit[12] & reg_we & !reg_error; + assign pad_io05_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io06_cfg_chip2pad_we = addr_hit[13] & reg_we & !reg_error; + assign pad_io06_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io06_cfg_pull_en_we = addr_hit[13] & reg_we & !reg_error; + assign pad_io06_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io06_cfg_rx_en_we = addr_hit[13] & reg_we & !reg_error; + assign pad_io06_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io06_cfg_tx_en_we = addr_hit[13] & reg_we & !reg_error; + assign pad_io06_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io06_mux_sel_we = addr_hit[14] & reg_we & !reg_error; + assign pad_io06_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io07_cfg_chip2pad_we = addr_hit[15] & reg_we & !reg_error; + assign pad_io07_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io07_cfg_pull_en_we = addr_hit[15] & reg_we & !reg_error; + assign pad_io07_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io07_cfg_rx_en_we = addr_hit[15] & reg_we & !reg_error; + assign pad_io07_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io07_cfg_tx_en_we = addr_hit[15] & reg_we & !reg_error; + assign pad_io07_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io07_mux_sel_we = addr_hit[16] & reg_we & !reg_error; + assign pad_io07_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io08_cfg_chip2pad_we = addr_hit[17] & reg_we & !reg_error; + assign pad_io08_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io08_cfg_pull_en_we = addr_hit[17] & reg_we & !reg_error; + assign pad_io08_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io08_cfg_rx_en_we = addr_hit[17] & reg_we & !reg_error; + assign pad_io08_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io08_cfg_tx_en_we = addr_hit[17] & reg_we & !reg_error; + assign pad_io08_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io08_mux_sel_we = addr_hit[18] & reg_we & !reg_error; + assign pad_io08_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io09_cfg_chip2pad_we = addr_hit[19] & reg_we & !reg_error; + assign pad_io09_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io09_cfg_pull_en_we = addr_hit[19] & reg_we & !reg_error; + assign pad_io09_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io09_cfg_rx_en_we = addr_hit[19] & reg_we & !reg_error; + assign pad_io09_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io09_cfg_tx_en_we = addr_hit[19] & reg_we & !reg_error; + assign pad_io09_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io09_mux_sel_we = addr_hit[20] & reg_we & !reg_error; + assign pad_io09_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io10_cfg_chip2pad_we = addr_hit[21] & reg_we & !reg_error; + assign pad_io10_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io10_cfg_pull_en_we = addr_hit[21] & reg_we & !reg_error; + assign pad_io10_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io10_cfg_rx_en_we = addr_hit[21] & reg_we & !reg_error; + assign pad_io10_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io10_cfg_tx_en_we = addr_hit[21] & reg_we & !reg_error; + assign pad_io10_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io10_mux_sel_we = addr_hit[22] & reg_we & !reg_error; + assign pad_io10_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io11_cfg_chip2pad_we = addr_hit[23] & reg_we & !reg_error; + assign pad_io11_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io11_cfg_pull_en_we = addr_hit[23] & reg_we & !reg_error; + assign pad_io11_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io11_cfg_rx_en_we = addr_hit[23] & reg_we & !reg_error; + assign pad_io11_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io11_cfg_tx_en_we = addr_hit[23] & reg_we & !reg_error; + assign pad_io11_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io11_mux_sel_we = addr_hit[24] & reg_we & !reg_error; + assign pad_io11_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io12_cfg_chip2pad_we = addr_hit[25] & reg_we & !reg_error; + assign pad_io12_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io12_cfg_pull_en_we = addr_hit[25] & reg_we & !reg_error; + assign pad_io12_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io12_cfg_rx_en_we = addr_hit[25] & reg_we & !reg_error; + assign pad_io12_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io12_cfg_tx_en_we = addr_hit[25] & reg_we & !reg_error; + assign pad_io12_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io12_mux_sel_we = addr_hit[26] & reg_we & !reg_error; + assign pad_io12_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io13_cfg_chip2pad_we = addr_hit[27] & reg_we & !reg_error; + assign pad_io13_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io13_cfg_pull_en_we = addr_hit[27] & reg_we & !reg_error; + assign pad_io13_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io13_cfg_rx_en_we = addr_hit[27] & reg_we & !reg_error; + assign pad_io13_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io13_cfg_tx_en_we = addr_hit[27] & reg_we & !reg_error; + assign pad_io13_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io13_mux_sel_we = addr_hit[28] & reg_we & !reg_error; + assign pad_io13_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io14_cfg_chip2pad_we = addr_hit[29] & reg_we & !reg_error; + assign pad_io14_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io14_cfg_pull_en_we = addr_hit[29] & reg_we & !reg_error; + assign pad_io14_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io14_cfg_rx_en_we = addr_hit[29] & reg_we & !reg_error; + assign pad_io14_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io14_cfg_tx_en_we = addr_hit[29] & reg_we & !reg_error; + assign pad_io14_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io14_mux_sel_we = addr_hit[30] & reg_we & !reg_error; + assign pad_io14_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io15_cfg_chip2pad_we = addr_hit[31] & reg_we & !reg_error; + assign pad_io15_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io15_cfg_pull_en_we = addr_hit[31] & reg_we & !reg_error; + assign pad_io15_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io15_cfg_rx_en_we = addr_hit[31] & reg_we & !reg_error; + assign pad_io15_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io15_cfg_tx_en_we = addr_hit[31] & reg_we & !reg_error; + assign pad_io15_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io15_mux_sel_we = addr_hit[32] & reg_we & !reg_error; + assign pad_io15_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io16_cfg_chip2pad_we = addr_hit[33] & reg_we & !reg_error; + assign pad_io16_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io16_cfg_pull_en_we = addr_hit[33] & reg_we & !reg_error; + assign pad_io16_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io16_cfg_rx_en_we = addr_hit[33] & reg_we & !reg_error; + assign pad_io16_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io16_cfg_tx_en_we = addr_hit[33] & reg_we & !reg_error; + assign pad_io16_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io16_mux_sel_we = addr_hit[34] & reg_we & !reg_error; + assign pad_io16_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io17_cfg_chip2pad_we = addr_hit[35] & reg_we & !reg_error; + assign pad_io17_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io17_cfg_pull_en_we = addr_hit[35] & reg_we & !reg_error; + assign pad_io17_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io17_cfg_rx_en_we = addr_hit[35] & reg_we & !reg_error; + assign pad_io17_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io17_cfg_tx_en_we = addr_hit[35] & reg_we & !reg_error; + assign pad_io17_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io17_mux_sel_we = addr_hit[36] & reg_we & !reg_error; + assign pad_io17_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io18_cfg_chip2pad_we = addr_hit[37] & reg_we & !reg_error; + assign pad_io18_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io18_cfg_pull_en_we = addr_hit[37] & reg_we & !reg_error; + assign pad_io18_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io18_cfg_rx_en_we = addr_hit[37] & reg_we & !reg_error; + assign pad_io18_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io18_cfg_tx_en_we = addr_hit[37] & reg_we & !reg_error; + assign pad_io18_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io18_mux_sel_we = addr_hit[38] & reg_we & !reg_error; + assign pad_io18_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io19_cfg_chip2pad_we = addr_hit[39] & reg_we & !reg_error; + assign pad_io19_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io19_cfg_pull_en_we = addr_hit[39] & reg_we & !reg_error; + assign pad_io19_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io19_cfg_rx_en_we = addr_hit[39] & reg_we & !reg_error; + assign pad_io19_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io19_cfg_tx_en_we = addr_hit[39] & reg_we & !reg_error; + assign pad_io19_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io19_mux_sel_we = addr_hit[40] & reg_we & !reg_error; + assign pad_io19_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io20_cfg_chip2pad_we = addr_hit[41] & reg_we & !reg_error; + assign pad_io20_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io20_cfg_pull_en_we = addr_hit[41] & reg_we & !reg_error; + assign pad_io20_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io20_cfg_rx_en_we = addr_hit[41] & reg_we & !reg_error; + assign pad_io20_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io20_cfg_tx_en_we = addr_hit[41] & reg_we & !reg_error; + assign pad_io20_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io20_mux_sel_we = addr_hit[42] & reg_we & !reg_error; + assign pad_io20_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io21_cfg_chip2pad_we = addr_hit[43] & reg_we & !reg_error; + assign pad_io21_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io21_cfg_pull_en_we = addr_hit[43] & reg_we & !reg_error; + assign pad_io21_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io21_cfg_rx_en_we = addr_hit[43] & reg_we & !reg_error; + assign pad_io21_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io21_cfg_tx_en_we = addr_hit[43] & reg_we & !reg_error; + assign pad_io21_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io21_mux_sel_we = addr_hit[44] & reg_we & !reg_error; + assign pad_io21_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io22_cfg_chip2pad_we = addr_hit[45] & reg_we & !reg_error; + assign pad_io22_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io22_cfg_pull_en_we = addr_hit[45] & reg_we & !reg_error; + assign pad_io22_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io22_cfg_rx_en_we = addr_hit[45] & reg_we & !reg_error; + assign pad_io22_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io22_cfg_tx_en_we = addr_hit[45] & reg_we & !reg_error; + assign pad_io22_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io22_mux_sel_we = addr_hit[46] & reg_we & !reg_error; + assign pad_io22_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io23_cfg_chip2pad_we = addr_hit[47] & reg_we & !reg_error; + assign pad_io23_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io23_cfg_pull_en_we = addr_hit[47] & reg_we & !reg_error; + assign pad_io23_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io23_cfg_rx_en_we = addr_hit[47] & reg_we & !reg_error; + assign pad_io23_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io23_cfg_tx_en_we = addr_hit[47] & reg_we & !reg_error; + assign pad_io23_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io23_mux_sel_we = addr_hit[48] & reg_we & !reg_error; + assign pad_io23_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io24_cfg_chip2pad_we = addr_hit[49] & reg_we & !reg_error; + assign pad_io24_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io24_cfg_pull_en_we = addr_hit[49] & reg_we & !reg_error; + assign pad_io24_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io24_cfg_rx_en_we = addr_hit[49] & reg_we & !reg_error; + assign pad_io24_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io24_cfg_tx_en_we = addr_hit[49] & reg_we & !reg_error; + assign pad_io24_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io24_mux_sel_we = addr_hit[50] & reg_we & !reg_error; + assign pad_io24_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io25_cfg_chip2pad_we = addr_hit[51] & reg_we & !reg_error; + assign pad_io25_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io25_cfg_pull_en_we = addr_hit[51] & reg_we & !reg_error; + assign pad_io25_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io25_cfg_rx_en_we = addr_hit[51] & reg_we & !reg_error; + assign pad_io25_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io25_cfg_tx_en_we = addr_hit[51] & reg_we & !reg_error; + assign pad_io25_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io25_mux_sel_we = addr_hit[52] & reg_we & !reg_error; + assign pad_io25_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io26_cfg_chip2pad_we = addr_hit[53] & reg_we & !reg_error; + assign pad_io26_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io26_cfg_pull_en_we = addr_hit[53] & reg_we & !reg_error; + assign pad_io26_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io26_cfg_rx_en_we = addr_hit[53] & reg_we & !reg_error; + assign pad_io26_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io26_cfg_tx_en_we = addr_hit[53] & reg_we & !reg_error; + assign pad_io26_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io26_mux_sel_we = addr_hit[54] & reg_we & !reg_error; + assign pad_io26_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io27_cfg_chip2pad_we = addr_hit[55] & reg_we & !reg_error; + assign pad_io27_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io27_cfg_pull_en_we = addr_hit[55] & reg_we & !reg_error; + assign pad_io27_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io27_cfg_rx_en_we = addr_hit[55] & reg_we & !reg_error; + assign pad_io27_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io27_cfg_tx_en_we = addr_hit[55] & reg_we & !reg_error; + assign pad_io27_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io27_mux_sel_we = addr_hit[56] & reg_we & !reg_error; + assign pad_io27_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io28_cfg_chip2pad_we = addr_hit[57] & reg_we & !reg_error; + assign pad_io28_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io28_cfg_pull_en_we = addr_hit[57] & reg_we & !reg_error; + assign pad_io28_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io28_cfg_rx_en_we = addr_hit[57] & reg_we & !reg_error; + assign pad_io28_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io28_cfg_tx_en_we = addr_hit[57] & reg_we & !reg_error; + assign pad_io28_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io28_mux_sel_we = addr_hit[58] & reg_we & !reg_error; + assign pad_io28_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io29_cfg_chip2pad_we = addr_hit[59] & reg_we & !reg_error; + assign pad_io29_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io29_cfg_pull_en_we = addr_hit[59] & reg_we & !reg_error; + assign pad_io29_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io29_cfg_rx_en_we = addr_hit[59] & reg_we & !reg_error; + assign pad_io29_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io29_cfg_tx_en_we = addr_hit[59] & reg_we & !reg_error; + assign pad_io29_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io29_mux_sel_we = addr_hit[60] & reg_we & !reg_error; + assign pad_io29_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io30_cfg_chip2pad_we = addr_hit[61] & reg_we & !reg_error; + assign pad_io30_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io30_cfg_pull_en_we = addr_hit[61] & reg_we & !reg_error; + assign pad_io30_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io30_cfg_rx_en_we = addr_hit[61] & reg_we & !reg_error; + assign pad_io30_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io30_cfg_tx_en_we = addr_hit[61] & reg_we & !reg_error; + assign pad_io30_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io30_mux_sel_we = addr_hit[62] & reg_we & !reg_error; + assign pad_io30_mux_sel_wd = reg_wdata[5:0]; + + assign pad_io31_cfg_chip2pad_we = addr_hit[63] & reg_we & !reg_error; + assign pad_io31_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io31_cfg_pull_en_we = addr_hit[63] & reg_we & !reg_error; + assign pad_io31_cfg_pull_en_wd = reg_wdata[1]; + + assign pad_io31_cfg_rx_en_we = addr_hit[63] & reg_we & !reg_error; + assign pad_io31_cfg_rx_en_wd = reg_wdata[2]; + + assign pad_io31_cfg_tx_en_we = addr_hit[63] & reg_we & !reg_error; + assign pad_io31_cfg_tx_en_wd = reg_wdata[3]; + + assign pad_io31_mux_sel_we = addr_hit[64] & reg_we & !reg_error; + assign pad_io31_mux_sel_wd = reg_wdata[5:0]; + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[15:0] = info_hw_version_qs; + reg_rdata_next[31:16] = info_padcount_qs; + end + + addr_hit[1]: begin + reg_rdata_next[0] = pad_io00_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io00_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io00_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io00_cfg_tx_en_qs; + end + + addr_hit[2]: begin + reg_rdata_next[5:0] = pad_io00_mux_sel_qs; + end + + addr_hit[3]: begin + reg_rdata_next[0] = pad_io01_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io01_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io01_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io01_cfg_tx_en_qs; + end + + addr_hit[4]: begin + reg_rdata_next[5:0] = pad_io01_mux_sel_qs; + end + + addr_hit[5]: begin + reg_rdata_next[0] = pad_io02_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io02_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io02_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io02_cfg_tx_en_qs; + end + + addr_hit[6]: begin + reg_rdata_next[5:0] = pad_io02_mux_sel_qs; + end + + addr_hit[7]: begin + reg_rdata_next[0] = pad_io03_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io03_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io03_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io03_cfg_tx_en_qs; + end + + addr_hit[8]: begin + reg_rdata_next[5:0] = pad_io03_mux_sel_qs; + end + + addr_hit[9]: begin + reg_rdata_next[0] = pad_io04_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io04_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io04_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io04_cfg_tx_en_qs; + end + + addr_hit[10]: begin + reg_rdata_next[5:0] = pad_io04_mux_sel_qs; + end + + addr_hit[11]: begin + reg_rdata_next[0] = pad_io05_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io05_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io05_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io05_cfg_tx_en_qs; + end + + addr_hit[12]: begin + reg_rdata_next[5:0] = pad_io05_mux_sel_qs; + end + + addr_hit[13]: begin + reg_rdata_next[0] = pad_io06_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io06_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io06_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io06_cfg_tx_en_qs; + end + + addr_hit[14]: begin + reg_rdata_next[5:0] = pad_io06_mux_sel_qs; + end + + addr_hit[15]: begin + reg_rdata_next[0] = pad_io07_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io07_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io07_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io07_cfg_tx_en_qs; + end + + addr_hit[16]: begin + reg_rdata_next[5:0] = pad_io07_mux_sel_qs; + end + + addr_hit[17]: begin + reg_rdata_next[0] = pad_io08_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io08_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io08_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io08_cfg_tx_en_qs; + end + + addr_hit[18]: begin + reg_rdata_next[5:0] = pad_io08_mux_sel_qs; + end + + addr_hit[19]: begin + reg_rdata_next[0] = pad_io09_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io09_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io09_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io09_cfg_tx_en_qs; + end + + addr_hit[20]: begin + reg_rdata_next[5:0] = pad_io09_mux_sel_qs; + end + + addr_hit[21]: begin + reg_rdata_next[0] = pad_io10_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io10_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io10_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io10_cfg_tx_en_qs; + end + + addr_hit[22]: begin + reg_rdata_next[5:0] = pad_io10_mux_sel_qs; + end + + addr_hit[23]: begin + reg_rdata_next[0] = pad_io11_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io11_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io11_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io11_cfg_tx_en_qs; + end + + addr_hit[24]: begin + reg_rdata_next[5:0] = pad_io11_mux_sel_qs; + end + + addr_hit[25]: begin + reg_rdata_next[0] = pad_io12_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io12_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io12_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io12_cfg_tx_en_qs; + end + + addr_hit[26]: begin + reg_rdata_next[5:0] = pad_io12_mux_sel_qs; + end + + addr_hit[27]: begin + reg_rdata_next[0] = pad_io13_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io13_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io13_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io13_cfg_tx_en_qs; + end + + addr_hit[28]: begin + reg_rdata_next[5:0] = pad_io13_mux_sel_qs; + end + + addr_hit[29]: begin + reg_rdata_next[0] = pad_io14_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io14_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io14_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io14_cfg_tx_en_qs; + end + + addr_hit[30]: begin + reg_rdata_next[5:0] = pad_io14_mux_sel_qs; + end + + addr_hit[31]: begin + reg_rdata_next[0] = pad_io15_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io15_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io15_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io15_cfg_tx_en_qs; + end + + addr_hit[32]: begin + reg_rdata_next[5:0] = pad_io15_mux_sel_qs; + end + + addr_hit[33]: begin + reg_rdata_next[0] = pad_io16_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io16_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io16_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io16_cfg_tx_en_qs; + end + + addr_hit[34]: begin + reg_rdata_next[5:0] = pad_io16_mux_sel_qs; + end + + addr_hit[35]: begin + reg_rdata_next[0] = pad_io17_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io17_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io17_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io17_cfg_tx_en_qs; + end + + addr_hit[36]: begin + reg_rdata_next[5:0] = pad_io17_mux_sel_qs; + end + + addr_hit[37]: begin + reg_rdata_next[0] = pad_io18_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io18_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io18_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io18_cfg_tx_en_qs; + end + + addr_hit[38]: begin + reg_rdata_next[5:0] = pad_io18_mux_sel_qs; + end + + addr_hit[39]: begin + reg_rdata_next[0] = pad_io19_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io19_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io19_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io19_cfg_tx_en_qs; + end + + addr_hit[40]: begin + reg_rdata_next[5:0] = pad_io19_mux_sel_qs; + end + + addr_hit[41]: begin + reg_rdata_next[0] = pad_io20_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io20_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io20_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io20_cfg_tx_en_qs; + end + + addr_hit[42]: begin + reg_rdata_next[5:0] = pad_io20_mux_sel_qs; + end + + addr_hit[43]: begin + reg_rdata_next[0] = pad_io21_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io21_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io21_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io21_cfg_tx_en_qs; + end + + addr_hit[44]: begin + reg_rdata_next[5:0] = pad_io21_mux_sel_qs; + end + + addr_hit[45]: begin + reg_rdata_next[0] = pad_io22_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io22_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io22_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io22_cfg_tx_en_qs; + end + + addr_hit[46]: begin + reg_rdata_next[5:0] = pad_io22_mux_sel_qs; + end + + addr_hit[47]: begin + reg_rdata_next[0] = pad_io23_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io23_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io23_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io23_cfg_tx_en_qs; + end + + addr_hit[48]: begin + reg_rdata_next[5:0] = pad_io23_mux_sel_qs; + end + + addr_hit[49]: begin + reg_rdata_next[0] = pad_io24_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io24_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io24_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io24_cfg_tx_en_qs; + end + + addr_hit[50]: begin + reg_rdata_next[5:0] = pad_io24_mux_sel_qs; + end + + addr_hit[51]: begin + reg_rdata_next[0] = pad_io25_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io25_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io25_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io25_cfg_tx_en_qs; + end + + addr_hit[52]: begin + reg_rdata_next[5:0] = pad_io25_mux_sel_qs; + end + + addr_hit[53]: begin + reg_rdata_next[0] = pad_io26_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io26_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io26_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io26_cfg_tx_en_qs; + end + + addr_hit[54]: begin + reg_rdata_next[5:0] = pad_io26_mux_sel_qs; + end + + addr_hit[55]: begin + reg_rdata_next[0] = pad_io27_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io27_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io27_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io27_cfg_tx_en_qs; + end + + addr_hit[56]: begin + reg_rdata_next[5:0] = pad_io27_mux_sel_qs; + end + + addr_hit[57]: begin + reg_rdata_next[0] = pad_io28_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io28_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io28_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io28_cfg_tx_en_qs; + end + + addr_hit[58]: begin + reg_rdata_next[5:0] = pad_io28_mux_sel_qs; + end + + addr_hit[59]: begin + reg_rdata_next[0] = pad_io29_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io29_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io29_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io29_cfg_tx_en_qs; + end + + addr_hit[60]: begin + reg_rdata_next[5:0] = pad_io29_mux_sel_qs; + end + + addr_hit[61]: begin + reg_rdata_next[0] = pad_io30_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io30_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io30_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io30_cfg_tx_en_qs; + end + + addr_hit[62]: begin + reg_rdata_next[5:0] = pad_io30_mux_sel_qs; + end + + addr_hit[63]: begin + reg_rdata_next[0] = pad_io31_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io31_cfg_pull_en_qs; + reg_rdata_next[2] = pad_io31_cfg_rx_en_qs; + reg_rdata_next[3] = pad_io31_cfg_tx_en_qs; + end + + addr_hit[64]: begin + reg_rdata_next[5:0] = pad_io31_mux_sel_qs; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit)) + +endmodule diff --git a/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/src/pulpissimo_padframe_all_pads_muxer.sv b/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/src/pulpissimo_padframe_all_pads_muxer.sv new file mode 100644 index 00000000..81963121 --- /dev/null +++ b/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/src/pulpissimo_padframe_all_pads_muxer.sv @@ -0,0 +1,17437 @@ + +// File auto-generated by Padrick unknown +module pulpissimo_padframe_all_pads_muxer + import pkg_internal_pulpissimo_padframe_all_pads::*; + import pkg_pulpissimo_padframe::*; + import pulpissimo_padframe_all_pads_config_reg_pkg::*; +#( + parameter type req_t = logic, // reg_interface request type + parameter type resp_t = logic // reg_interface response type +) ( + input logic clk_i, + input logic rst_ni, + input pad_domain_all_pads_ports_soc2pad_t port_signals_soc2pad_i, + output pad_domain_all_pads_ports_pad2soc_t port_signals_pad2soc_o, + output mux_to_pads_t mux_to_pads_o, + input pads_to_mux_t pads_to_mux_i, + // Configuration interface using register_interface protocol + input req_t config_req_i, + output resp_t config_rsp_o +); + // Connections between register file and pads + pulpissimo_padframe_all_pads_config_reg2hw_t s_reg2hw; + + // Register File Instantiation + pulpissimo_padframe_all_pads_config_reg_top #( + .reg_req_t(req_t), + .reg_rsp_t(resp_t) + ) i_regfile ( + .clk_i, + .rst_ni, + .reg2hw(s_reg2hw), + .reg_req_i(config_req_i), + .reg_rsp_o(config_rsp_o), + .devmode_i(1'b1) + ); + + + // SoC -> Pad Multiplex Logic + // Pad pad_io00 + always_comb begin + unique case (s_reg2hw.pad_io00_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_DEFAULT: begin + mux_to_pads_o.pad_io00.chip2pad = s_reg2hw.pad_io00_cfg.chip2pad.q; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_GPIO_GPIO00: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.gpio.gpio00_out; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = ~port_signals_soc2pad_i.gpio.gpio00_tx_en; + mux_to_pads_o.pad_io00.tx_en = port_signals_soc2pad_i.gpio.gpio00_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io00.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io00.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_UART0_RX: begin + mux_to_pads_o.pad_io00.chip2pad = 1'b1; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = 1'b1; + mux_to_pads_o.pad_io00.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_UART0_TX: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = 1'b0; + mux_to_pads_o.pad_io00.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = 1'b0; + mux_to_pads_o.pad_io00.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = 1'b0; + mux_to_pads_o.pad_io00.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = 1'b0; + mux_to_pads_o.pad_io00.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = 1'b0; + mux_to_pads_o.pad_io00.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = 1'b0; + mux_to_pads_o.pad_io00.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io00.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io00.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io00.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io00.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io00.chip2pad = 1'b0; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io00.chip2pad = 1'b0; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io00.chip2pad = 1'b0; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io00.chip2pad = 1'b0; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io00.chip2pad = 1'b0; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io00.chip2pad = 1'b0; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io00.chip2pad = 1'b0; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io00.chip2pad = 1'b0; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io00.chip2pad = 1'b0; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io00.chip2pad = 1'b0; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io00.chip2pad = 1'b0; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io00.chip2pad = 1'b0; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io00.chip2pad = 1'b0; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = 1'b0; + mux_to_pads_o.pad_io00.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io00.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io00.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io00.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io00.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io00.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io00.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = 1'b0; + mux_to_pads_o.pad_io00.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = 1'b0; + mux_to_pads_o.pad_io00.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io00.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io00.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io00.chip2pad = s_reg2hw.pad_io00_cfg.chip2pad.q; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = 1'b1; + mux_to_pads_o.pad_io00.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io00.chip2pad = s_reg2hw.pad_io00_cfg.chip2pad.q; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = 1'b1; + mux_to_pads_o.pad_io00.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io00.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io00.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io00.chip2pad = s_reg2hw.pad_io00_cfg.chip2pad.q; + mux_to_pads_o.pad_io00.pull_en = s_reg2hw.pad_io00_cfg.pull_en.q; + mux_to_pads_o.pad_io00.rx_en = s_reg2hw.pad_io00_cfg.rx_en.q; + mux_to_pads_o.pad_io00.tx_en = s_reg2hw.pad_io00_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io01 + always_comb begin + unique case (s_reg2hw.pad_io01_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_DEFAULT: begin + mux_to_pads_o.pad_io01.chip2pad = s_reg2hw.pad_io01_cfg.chip2pad.q; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_GPIO_GPIO01: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.gpio.gpio01_out; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = ~port_signals_soc2pad_i.gpio.gpio01_tx_en; + mux_to_pads_o.pad_io01.tx_en = port_signals_soc2pad_i.gpio.gpio01_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io01.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io01.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_UART0_RX: begin + mux_to_pads_o.pad_io01.chip2pad = 1'b1; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = 1'b1; + mux_to_pads_o.pad_io01.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_UART0_TX: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = 1'b0; + mux_to_pads_o.pad_io01.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = 1'b0; + mux_to_pads_o.pad_io01.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = 1'b0; + mux_to_pads_o.pad_io01.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = 1'b0; + mux_to_pads_o.pad_io01.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = 1'b0; + mux_to_pads_o.pad_io01.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = 1'b0; + mux_to_pads_o.pad_io01.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io01.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io01.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io01.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io01.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io01.chip2pad = 1'b0; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io01.chip2pad = 1'b0; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io01.chip2pad = 1'b0; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io01.chip2pad = 1'b0; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io01.chip2pad = 1'b0; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io01.chip2pad = 1'b0; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io01.chip2pad = 1'b0; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io01.chip2pad = 1'b0; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io01.chip2pad = 1'b0; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io01.chip2pad = 1'b0; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io01.chip2pad = 1'b0; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io01.chip2pad = 1'b0; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io01.chip2pad = 1'b0; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = 1'b0; + mux_to_pads_o.pad_io01.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io01.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io01.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io01.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io01.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io01.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io01.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = 1'b0; + mux_to_pads_o.pad_io01.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = 1'b0; + mux_to_pads_o.pad_io01.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io01.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io01.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io01.chip2pad = s_reg2hw.pad_io01_cfg.chip2pad.q; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = 1'b1; + mux_to_pads_o.pad_io01.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io01.chip2pad = s_reg2hw.pad_io01_cfg.chip2pad.q; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = 1'b1; + mux_to_pads_o.pad_io01.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io01.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io01.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io01.chip2pad = s_reg2hw.pad_io01_cfg.chip2pad.q; + mux_to_pads_o.pad_io01.pull_en = s_reg2hw.pad_io01_cfg.pull_en.q; + mux_to_pads_o.pad_io01.rx_en = s_reg2hw.pad_io01_cfg.rx_en.q; + mux_to_pads_o.pad_io01.tx_en = s_reg2hw.pad_io01_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io02 + always_comb begin + unique case (s_reg2hw.pad_io02_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_DEFAULT: begin + mux_to_pads_o.pad_io02.chip2pad = s_reg2hw.pad_io02_cfg.chip2pad.q; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_GPIO_GPIO02: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.gpio.gpio02_out; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = ~port_signals_soc2pad_i.gpio.gpio02_tx_en; + mux_to_pads_o.pad_io02.tx_en = port_signals_soc2pad_i.gpio.gpio02_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io02.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io02.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_UART0_RX: begin + mux_to_pads_o.pad_io02.chip2pad = 1'b1; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = 1'b1; + mux_to_pads_o.pad_io02.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_UART0_TX: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = 1'b0; + mux_to_pads_o.pad_io02.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = 1'b0; + mux_to_pads_o.pad_io02.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = 1'b0; + mux_to_pads_o.pad_io02.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = 1'b0; + mux_to_pads_o.pad_io02.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = 1'b0; + mux_to_pads_o.pad_io02.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = 1'b0; + mux_to_pads_o.pad_io02.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io02.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io02.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io02.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io02.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io02.chip2pad = 1'b0; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io02.chip2pad = 1'b0; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io02.chip2pad = 1'b0; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io02.chip2pad = 1'b0; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io02.chip2pad = 1'b0; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io02.chip2pad = 1'b0; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io02.chip2pad = 1'b0; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io02.chip2pad = 1'b0; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io02.chip2pad = 1'b0; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io02.chip2pad = 1'b0; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io02.chip2pad = 1'b0; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io02.chip2pad = 1'b0; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io02.chip2pad = 1'b0; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = 1'b0; + mux_to_pads_o.pad_io02.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io02.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io02.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io02.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io02.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io02.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io02.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = 1'b0; + mux_to_pads_o.pad_io02.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = 1'b0; + mux_to_pads_o.pad_io02.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io02.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io02.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io02.chip2pad = s_reg2hw.pad_io02_cfg.chip2pad.q; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = 1'b1; + mux_to_pads_o.pad_io02.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io02.chip2pad = s_reg2hw.pad_io02_cfg.chip2pad.q; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = 1'b1; + mux_to_pads_o.pad_io02.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io02.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io02.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io02.chip2pad = s_reg2hw.pad_io02_cfg.chip2pad.q; + mux_to_pads_o.pad_io02.pull_en = s_reg2hw.pad_io02_cfg.pull_en.q; + mux_to_pads_o.pad_io02.rx_en = s_reg2hw.pad_io02_cfg.rx_en.q; + mux_to_pads_o.pad_io02.tx_en = s_reg2hw.pad_io02_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io03 + always_comb begin + unique case (s_reg2hw.pad_io03_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_DEFAULT: begin + mux_to_pads_o.pad_io03.chip2pad = s_reg2hw.pad_io03_cfg.chip2pad.q; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_GPIO_GPIO03: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.gpio.gpio03_out; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = ~port_signals_soc2pad_i.gpio.gpio03_tx_en; + mux_to_pads_o.pad_io03.tx_en = port_signals_soc2pad_i.gpio.gpio03_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io03.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io03.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_UART0_RX: begin + mux_to_pads_o.pad_io03.chip2pad = 1'b1; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = 1'b1; + mux_to_pads_o.pad_io03.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_UART0_TX: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = 1'b0; + mux_to_pads_o.pad_io03.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = 1'b0; + mux_to_pads_o.pad_io03.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = 1'b0; + mux_to_pads_o.pad_io03.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = 1'b0; + mux_to_pads_o.pad_io03.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = 1'b0; + mux_to_pads_o.pad_io03.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = 1'b0; + mux_to_pads_o.pad_io03.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io03.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io03.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io03.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io03.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io03.chip2pad = 1'b0; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io03.chip2pad = 1'b0; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io03.chip2pad = 1'b0; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io03.chip2pad = 1'b0; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io03.chip2pad = 1'b0; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io03.chip2pad = 1'b0; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io03.chip2pad = 1'b0; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io03.chip2pad = 1'b0; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io03.chip2pad = 1'b0; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io03.chip2pad = 1'b0; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io03.chip2pad = 1'b0; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io03.chip2pad = 1'b0; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io03.chip2pad = 1'b0; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = 1'b0; + mux_to_pads_o.pad_io03.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io03.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io03.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io03.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io03.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io03.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io03.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = 1'b0; + mux_to_pads_o.pad_io03.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = 1'b0; + mux_to_pads_o.pad_io03.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io03.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io03.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io03.chip2pad = s_reg2hw.pad_io03_cfg.chip2pad.q; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = 1'b1; + mux_to_pads_o.pad_io03.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io03.chip2pad = s_reg2hw.pad_io03_cfg.chip2pad.q; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = 1'b1; + mux_to_pads_o.pad_io03.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io03.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io03.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io03.chip2pad = s_reg2hw.pad_io03_cfg.chip2pad.q; + mux_to_pads_o.pad_io03.pull_en = s_reg2hw.pad_io03_cfg.pull_en.q; + mux_to_pads_o.pad_io03.rx_en = s_reg2hw.pad_io03_cfg.rx_en.q; + mux_to_pads_o.pad_io03.tx_en = s_reg2hw.pad_io03_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io04 + always_comb begin + unique case (s_reg2hw.pad_io04_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_DEFAULT: begin + mux_to_pads_o.pad_io04.chip2pad = s_reg2hw.pad_io04_cfg.chip2pad.q; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_GPIO_GPIO04: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.gpio.gpio04_out; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = ~port_signals_soc2pad_i.gpio.gpio04_tx_en; + mux_to_pads_o.pad_io04.tx_en = port_signals_soc2pad_i.gpio.gpio04_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io04.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io04.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_UART0_RX: begin + mux_to_pads_o.pad_io04.chip2pad = 1'b1; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = 1'b1; + mux_to_pads_o.pad_io04.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_UART0_TX: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = 1'b0; + mux_to_pads_o.pad_io04.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = 1'b0; + mux_to_pads_o.pad_io04.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = 1'b0; + mux_to_pads_o.pad_io04.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = 1'b0; + mux_to_pads_o.pad_io04.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = 1'b0; + mux_to_pads_o.pad_io04.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = 1'b0; + mux_to_pads_o.pad_io04.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io04.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io04.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io04.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io04.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io04.chip2pad = 1'b0; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io04.chip2pad = 1'b0; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io04.chip2pad = 1'b0; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io04.chip2pad = 1'b0; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io04.chip2pad = 1'b0; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io04.chip2pad = 1'b0; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io04.chip2pad = 1'b0; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io04.chip2pad = 1'b0; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io04.chip2pad = 1'b0; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io04.chip2pad = 1'b0; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io04.chip2pad = 1'b0; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io04.chip2pad = 1'b0; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io04.chip2pad = 1'b0; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = 1'b0; + mux_to_pads_o.pad_io04.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io04.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io04.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io04.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io04.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io04.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io04.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = 1'b0; + mux_to_pads_o.pad_io04.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = 1'b0; + mux_to_pads_o.pad_io04.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io04.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io04.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io04.chip2pad = s_reg2hw.pad_io04_cfg.chip2pad.q; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = 1'b1; + mux_to_pads_o.pad_io04.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io04.chip2pad = s_reg2hw.pad_io04_cfg.chip2pad.q; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = 1'b1; + mux_to_pads_o.pad_io04.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io04.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io04.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io04.chip2pad = s_reg2hw.pad_io04_cfg.chip2pad.q; + mux_to_pads_o.pad_io04.pull_en = s_reg2hw.pad_io04_cfg.pull_en.q; + mux_to_pads_o.pad_io04.rx_en = s_reg2hw.pad_io04_cfg.rx_en.q; + mux_to_pads_o.pad_io04.tx_en = s_reg2hw.pad_io04_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io05 + always_comb begin + unique case (s_reg2hw.pad_io05_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_DEFAULT: begin + mux_to_pads_o.pad_io05.chip2pad = s_reg2hw.pad_io05_cfg.chip2pad.q; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_GPIO_GPIO05: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.gpio.gpio05_out; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = ~port_signals_soc2pad_i.gpio.gpio05_tx_en; + mux_to_pads_o.pad_io05.tx_en = port_signals_soc2pad_i.gpio.gpio05_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io05.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io05.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_UART0_RX: begin + mux_to_pads_o.pad_io05.chip2pad = 1'b1; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = 1'b1; + mux_to_pads_o.pad_io05.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_UART0_TX: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = 1'b0; + mux_to_pads_o.pad_io05.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = 1'b0; + mux_to_pads_o.pad_io05.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = 1'b0; + mux_to_pads_o.pad_io05.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = 1'b0; + mux_to_pads_o.pad_io05.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = 1'b0; + mux_to_pads_o.pad_io05.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = 1'b0; + mux_to_pads_o.pad_io05.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io05.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io05.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io05.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io05.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io05.chip2pad = 1'b0; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io05.chip2pad = 1'b0; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io05.chip2pad = 1'b0; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io05.chip2pad = 1'b0; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io05.chip2pad = 1'b0; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io05.chip2pad = 1'b0; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io05.chip2pad = 1'b0; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io05.chip2pad = 1'b0; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io05.chip2pad = 1'b0; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io05.chip2pad = 1'b0; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io05.chip2pad = 1'b0; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io05.chip2pad = 1'b0; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io05.chip2pad = 1'b0; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = 1'b0; + mux_to_pads_o.pad_io05.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io05.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io05.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io05.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io05.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io05.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io05.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = 1'b0; + mux_to_pads_o.pad_io05.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = 1'b0; + mux_to_pads_o.pad_io05.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io05.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io05.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io05.chip2pad = s_reg2hw.pad_io05_cfg.chip2pad.q; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = 1'b1; + mux_to_pads_o.pad_io05.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io05.chip2pad = s_reg2hw.pad_io05_cfg.chip2pad.q; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = 1'b1; + mux_to_pads_o.pad_io05.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io05.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io05.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io05.chip2pad = s_reg2hw.pad_io05_cfg.chip2pad.q; + mux_to_pads_o.pad_io05.pull_en = s_reg2hw.pad_io05_cfg.pull_en.q; + mux_to_pads_o.pad_io05.rx_en = s_reg2hw.pad_io05_cfg.rx_en.q; + mux_to_pads_o.pad_io05.tx_en = s_reg2hw.pad_io05_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io06 + always_comb begin + unique case (s_reg2hw.pad_io06_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_DEFAULT: begin + mux_to_pads_o.pad_io06.chip2pad = s_reg2hw.pad_io06_cfg.chip2pad.q; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_GPIO_GPIO06: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.gpio.gpio06_out; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = ~port_signals_soc2pad_i.gpio.gpio06_tx_en; + mux_to_pads_o.pad_io06.tx_en = port_signals_soc2pad_i.gpio.gpio06_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io06.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io06.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_UART0_RX: begin + mux_to_pads_o.pad_io06.chip2pad = 1'b1; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = 1'b1; + mux_to_pads_o.pad_io06.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_UART0_TX: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = 1'b0; + mux_to_pads_o.pad_io06.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = 1'b0; + mux_to_pads_o.pad_io06.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = 1'b0; + mux_to_pads_o.pad_io06.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = 1'b0; + mux_to_pads_o.pad_io06.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = 1'b0; + mux_to_pads_o.pad_io06.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = 1'b0; + mux_to_pads_o.pad_io06.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io06.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io06.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io06.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io06.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io06.chip2pad = 1'b0; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io06.chip2pad = 1'b0; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io06.chip2pad = 1'b0; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io06.chip2pad = 1'b0; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io06.chip2pad = 1'b0; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io06.chip2pad = 1'b0; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io06.chip2pad = 1'b0; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io06.chip2pad = 1'b0; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io06.chip2pad = 1'b0; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io06.chip2pad = 1'b0; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io06.chip2pad = 1'b0; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io06.chip2pad = 1'b0; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io06.chip2pad = 1'b0; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = 1'b0; + mux_to_pads_o.pad_io06.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io06.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io06.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io06.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io06.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io06.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io06.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = 1'b0; + mux_to_pads_o.pad_io06.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = 1'b0; + mux_to_pads_o.pad_io06.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io06.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io06.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io06.chip2pad = s_reg2hw.pad_io06_cfg.chip2pad.q; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = 1'b1; + mux_to_pads_o.pad_io06.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io06.chip2pad = s_reg2hw.pad_io06_cfg.chip2pad.q; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = 1'b1; + mux_to_pads_o.pad_io06.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io06.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io06.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io06.chip2pad = s_reg2hw.pad_io06_cfg.chip2pad.q; + mux_to_pads_o.pad_io06.pull_en = s_reg2hw.pad_io06_cfg.pull_en.q; + mux_to_pads_o.pad_io06.rx_en = s_reg2hw.pad_io06_cfg.rx_en.q; + mux_to_pads_o.pad_io06.tx_en = s_reg2hw.pad_io06_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io07 + always_comb begin + unique case (s_reg2hw.pad_io07_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_DEFAULT: begin + mux_to_pads_o.pad_io07.chip2pad = s_reg2hw.pad_io07_cfg.chip2pad.q; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_GPIO_GPIO07: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.gpio.gpio07_out; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = ~port_signals_soc2pad_i.gpio.gpio07_tx_en; + mux_to_pads_o.pad_io07.tx_en = port_signals_soc2pad_i.gpio.gpio07_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io07.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io07.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_UART0_RX: begin + mux_to_pads_o.pad_io07.chip2pad = 1'b1; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = 1'b1; + mux_to_pads_o.pad_io07.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_UART0_TX: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = 1'b0; + mux_to_pads_o.pad_io07.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = 1'b0; + mux_to_pads_o.pad_io07.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = 1'b0; + mux_to_pads_o.pad_io07.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = 1'b0; + mux_to_pads_o.pad_io07.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = 1'b0; + mux_to_pads_o.pad_io07.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = 1'b0; + mux_to_pads_o.pad_io07.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io07.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io07.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io07.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io07.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io07.chip2pad = 1'b0; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io07.chip2pad = 1'b0; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io07.chip2pad = 1'b0; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io07.chip2pad = 1'b0; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io07.chip2pad = 1'b0; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io07.chip2pad = 1'b0; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io07.chip2pad = 1'b0; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io07.chip2pad = 1'b0; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io07.chip2pad = 1'b0; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io07.chip2pad = 1'b0; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io07.chip2pad = 1'b0; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io07.chip2pad = 1'b0; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io07.chip2pad = 1'b0; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = 1'b0; + mux_to_pads_o.pad_io07.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io07.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io07.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io07.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io07.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io07.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io07.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = 1'b0; + mux_to_pads_o.pad_io07.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = 1'b0; + mux_to_pads_o.pad_io07.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io07.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io07.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io07.chip2pad = s_reg2hw.pad_io07_cfg.chip2pad.q; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = 1'b1; + mux_to_pads_o.pad_io07.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io07.chip2pad = s_reg2hw.pad_io07_cfg.chip2pad.q; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = 1'b1; + mux_to_pads_o.pad_io07.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io07.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io07.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io07.chip2pad = s_reg2hw.pad_io07_cfg.chip2pad.q; + mux_to_pads_o.pad_io07.pull_en = s_reg2hw.pad_io07_cfg.pull_en.q; + mux_to_pads_o.pad_io07.rx_en = s_reg2hw.pad_io07_cfg.rx_en.q; + mux_to_pads_o.pad_io07.tx_en = s_reg2hw.pad_io07_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io08 + always_comb begin + unique case (s_reg2hw.pad_io08_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_DEFAULT: begin + mux_to_pads_o.pad_io08.chip2pad = s_reg2hw.pad_io08_cfg.chip2pad.q; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_GPIO_GPIO08: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.gpio.gpio08_out; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = ~port_signals_soc2pad_i.gpio.gpio08_tx_en; + mux_to_pads_o.pad_io08.tx_en = port_signals_soc2pad_i.gpio.gpio08_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io08.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io08.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_UART0_RX: begin + mux_to_pads_o.pad_io08.chip2pad = 1'b1; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = 1'b1; + mux_to_pads_o.pad_io08.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_UART0_TX: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = 1'b0; + mux_to_pads_o.pad_io08.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = 1'b0; + mux_to_pads_o.pad_io08.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = 1'b0; + mux_to_pads_o.pad_io08.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = 1'b0; + mux_to_pads_o.pad_io08.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = 1'b0; + mux_to_pads_o.pad_io08.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = 1'b0; + mux_to_pads_o.pad_io08.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io08.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io08.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io08.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io08.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io08.chip2pad = 1'b0; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io08.chip2pad = 1'b0; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io08.chip2pad = 1'b0; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io08.chip2pad = 1'b0; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io08.chip2pad = 1'b0; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io08.chip2pad = 1'b0; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io08.chip2pad = 1'b0; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io08.chip2pad = 1'b0; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io08.chip2pad = 1'b0; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io08.chip2pad = 1'b0; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io08.chip2pad = 1'b0; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io08.chip2pad = 1'b0; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io08.chip2pad = 1'b0; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = 1'b0; + mux_to_pads_o.pad_io08.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io08.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io08.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io08.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io08.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io08.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io08.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = 1'b0; + mux_to_pads_o.pad_io08.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = 1'b0; + mux_to_pads_o.pad_io08.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io08.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io08.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io08.chip2pad = s_reg2hw.pad_io08_cfg.chip2pad.q; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = 1'b1; + mux_to_pads_o.pad_io08.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io08.chip2pad = s_reg2hw.pad_io08_cfg.chip2pad.q; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = 1'b1; + mux_to_pads_o.pad_io08.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io08.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io08.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io08.chip2pad = s_reg2hw.pad_io08_cfg.chip2pad.q; + mux_to_pads_o.pad_io08.pull_en = s_reg2hw.pad_io08_cfg.pull_en.q; + mux_to_pads_o.pad_io08.rx_en = s_reg2hw.pad_io08_cfg.rx_en.q; + mux_to_pads_o.pad_io08.tx_en = s_reg2hw.pad_io08_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io09 + always_comb begin + unique case (s_reg2hw.pad_io09_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_DEFAULT: begin + mux_to_pads_o.pad_io09.chip2pad = s_reg2hw.pad_io09_cfg.chip2pad.q; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_GPIO_GPIO09: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.gpio.gpio09_out; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = ~port_signals_soc2pad_i.gpio.gpio09_tx_en; + mux_to_pads_o.pad_io09.tx_en = port_signals_soc2pad_i.gpio.gpio09_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io09.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io09.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_UART0_RX: begin + mux_to_pads_o.pad_io09.chip2pad = 1'b1; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = 1'b1; + mux_to_pads_o.pad_io09.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_UART0_TX: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = 1'b0; + mux_to_pads_o.pad_io09.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = 1'b0; + mux_to_pads_o.pad_io09.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = 1'b0; + mux_to_pads_o.pad_io09.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = 1'b0; + mux_to_pads_o.pad_io09.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = 1'b0; + mux_to_pads_o.pad_io09.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = 1'b0; + mux_to_pads_o.pad_io09.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io09.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io09.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io09.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io09.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io09.chip2pad = 1'b0; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io09.chip2pad = 1'b0; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io09.chip2pad = 1'b0; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io09.chip2pad = 1'b0; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io09.chip2pad = 1'b0; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io09.chip2pad = 1'b0; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io09.chip2pad = 1'b0; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io09.chip2pad = 1'b0; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io09.chip2pad = 1'b0; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io09.chip2pad = 1'b0; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io09.chip2pad = 1'b0; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io09.chip2pad = 1'b0; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io09.chip2pad = 1'b0; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = 1'b0; + mux_to_pads_o.pad_io09.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io09.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io09.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io09.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io09.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io09.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io09.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = 1'b0; + mux_to_pads_o.pad_io09.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = 1'b0; + mux_to_pads_o.pad_io09.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io09.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io09.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io09.chip2pad = s_reg2hw.pad_io09_cfg.chip2pad.q; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = 1'b1; + mux_to_pads_o.pad_io09.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io09.chip2pad = s_reg2hw.pad_io09_cfg.chip2pad.q; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = 1'b1; + mux_to_pads_o.pad_io09.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io09.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io09.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io09.chip2pad = s_reg2hw.pad_io09_cfg.chip2pad.q; + mux_to_pads_o.pad_io09.pull_en = s_reg2hw.pad_io09_cfg.pull_en.q; + mux_to_pads_o.pad_io09.rx_en = s_reg2hw.pad_io09_cfg.rx_en.q; + mux_to_pads_o.pad_io09.tx_en = s_reg2hw.pad_io09_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io10 + always_comb begin + unique case (s_reg2hw.pad_io10_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_DEFAULT: begin + mux_to_pads_o.pad_io10.chip2pad = s_reg2hw.pad_io10_cfg.chip2pad.q; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_GPIO_GPIO10: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.gpio.gpio10_out; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = ~port_signals_soc2pad_i.gpio.gpio10_tx_en; + mux_to_pads_o.pad_io10.tx_en = port_signals_soc2pad_i.gpio.gpio10_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io10.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io10.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_UART0_RX: begin + mux_to_pads_o.pad_io10.chip2pad = 1'b1; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = 1'b1; + mux_to_pads_o.pad_io10.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_UART0_TX: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = 1'b0; + mux_to_pads_o.pad_io10.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = 1'b0; + mux_to_pads_o.pad_io10.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = 1'b0; + mux_to_pads_o.pad_io10.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = 1'b0; + mux_to_pads_o.pad_io10.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = 1'b0; + mux_to_pads_o.pad_io10.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = 1'b0; + mux_to_pads_o.pad_io10.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io10.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io10.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io10.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io10.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io10.chip2pad = 1'b0; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io10.chip2pad = 1'b0; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io10.chip2pad = 1'b0; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io10.chip2pad = 1'b0; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io10.chip2pad = 1'b0; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io10.chip2pad = 1'b0; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io10.chip2pad = 1'b0; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io10.chip2pad = 1'b0; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io10.chip2pad = 1'b0; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io10.chip2pad = 1'b0; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io10.chip2pad = 1'b0; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io10.chip2pad = 1'b0; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io10.chip2pad = 1'b0; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = 1'b0; + mux_to_pads_o.pad_io10.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io10.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io10.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io10.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io10.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io10.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io10.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = 1'b0; + mux_to_pads_o.pad_io10.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = 1'b0; + mux_to_pads_o.pad_io10.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io10.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io10.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io10.chip2pad = s_reg2hw.pad_io10_cfg.chip2pad.q; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = 1'b1; + mux_to_pads_o.pad_io10.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io10.chip2pad = s_reg2hw.pad_io10_cfg.chip2pad.q; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = 1'b1; + mux_to_pads_o.pad_io10.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io10.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io10.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io10.chip2pad = s_reg2hw.pad_io10_cfg.chip2pad.q; + mux_to_pads_o.pad_io10.pull_en = s_reg2hw.pad_io10_cfg.pull_en.q; + mux_to_pads_o.pad_io10.rx_en = s_reg2hw.pad_io10_cfg.rx_en.q; + mux_to_pads_o.pad_io10.tx_en = s_reg2hw.pad_io10_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io11 + always_comb begin + unique case (s_reg2hw.pad_io11_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_DEFAULT: begin + mux_to_pads_o.pad_io11.chip2pad = s_reg2hw.pad_io11_cfg.chip2pad.q; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_GPIO_GPIO11: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.gpio.gpio11_out; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = ~port_signals_soc2pad_i.gpio.gpio11_tx_en; + mux_to_pads_o.pad_io11.tx_en = port_signals_soc2pad_i.gpio.gpio11_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io11.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io11.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_UART0_RX: begin + mux_to_pads_o.pad_io11.chip2pad = 1'b1; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = 1'b1; + mux_to_pads_o.pad_io11.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_UART0_TX: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = 1'b0; + mux_to_pads_o.pad_io11.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = 1'b0; + mux_to_pads_o.pad_io11.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = 1'b0; + mux_to_pads_o.pad_io11.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = 1'b0; + mux_to_pads_o.pad_io11.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = 1'b0; + mux_to_pads_o.pad_io11.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = 1'b0; + mux_to_pads_o.pad_io11.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io11.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io11.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io11.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io11.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io11.chip2pad = 1'b0; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io11.chip2pad = 1'b0; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io11.chip2pad = 1'b0; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io11.chip2pad = 1'b0; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io11.chip2pad = 1'b0; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io11.chip2pad = 1'b0; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io11.chip2pad = 1'b0; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io11.chip2pad = 1'b0; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io11.chip2pad = 1'b0; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io11.chip2pad = 1'b0; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io11.chip2pad = 1'b0; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io11.chip2pad = 1'b0; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io11.chip2pad = 1'b0; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = 1'b0; + mux_to_pads_o.pad_io11.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io11.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io11.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io11.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io11.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io11.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io11.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = 1'b0; + mux_to_pads_o.pad_io11.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = 1'b0; + mux_to_pads_o.pad_io11.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io11.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io11.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io11.chip2pad = s_reg2hw.pad_io11_cfg.chip2pad.q; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = 1'b1; + mux_to_pads_o.pad_io11.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io11.chip2pad = s_reg2hw.pad_io11_cfg.chip2pad.q; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = 1'b1; + mux_to_pads_o.pad_io11.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io11.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io11.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io11.chip2pad = s_reg2hw.pad_io11_cfg.chip2pad.q; + mux_to_pads_o.pad_io11.pull_en = s_reg2hw.pad_io11_cfg.pull_en.q; + mux_to_pads_o.pad_io11.rx_en = s_reg2hw.pad_io11_cfg.rx_en.q; + mux_to_pads_o.pad_io11.tx_en = s_reg2hw.pad_io11_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io12 + always_comb begin + unique case (s_reg2hw.pad_io12_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_DEFAULT: begin + mux_to_pads_o.pad_io12.chip2pad = s_reg2hw.pad_io12_cfg.chip2pad.q; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_GPIO_GPIO12: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.gpio.gpio12_out; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = ~port_signals_soc2pad_i.gpio.gpio12_tx_en; + mux_to_pads_o.pad_io12.tx_en = port_signals_soc2pad_i.gpio.gpio12_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io12.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io12.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_UART0_RX: begin + mux_to_pads_o.pad_io12.chip2pad = 1'b1; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = 1'b1; + mux_to_pads_o.pad_io12.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_UART0_TX: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = 1'b0; + mux_to_pads_o.pad_io12.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = 1'b0; + mux_to_pads_o.pad_io12.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = 1'b0; + mux_to_pads_o.pad_io12.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = 1'b0; + mux_to_pads_o.pad_io12.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = 1'b0; + mux_to_pads_o.pad_io12.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = 1'b0; + mux_to_pads_o.pad_io12.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io12.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io12.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io12.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io12.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io12.chip2pad = 1'b0; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io12.chip2pad = 1'b0; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io12.chip2pad = 1'b0; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io12.chip2pad = 1'b0; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io12.chip2pad = 1'b0; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io12.chip2pad = 1'b0; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io12.chip2pad = 1'b0; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io12.chip2pad = 1'b0; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io12.chip2pad = 1'b0; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io12.chip2pad = 1'b0; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io12.chip2pad = 1'b0; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io12.chip2pad = 1'b0; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io12.chip2pad = 1'b0; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = 1'b0; + mux_to_pads_o.pad_io12.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io12.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io12.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io12.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io12.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io12.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io12.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = 1'b0; + mux_to_pads_o.pad_io12.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = 1'b0; + mux_to_pads_o.pad_io12.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io12.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io12.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io12.chip2pad = s_reg2hw.pad_io12_cfg.chip2pad.q; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = 1'b1; + mux_to_pads_o.pad_io12.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io12.chip2pad = s_reg2hw.pad_io12_cfg.chip2pad.q; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = 1'b1; + mux_to_pads_o.pad_io12.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io12.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io12.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io12.chip2pad = s_reg2hw.pad_io12_cfg.chip2pad.q; + mux_to_pads_o.pad_io12.pull_en = s_reg2hw.pad_io12_cfg.pull_en.q; + mux_to_pads_o.pad_io12.rx_en = s_reg2hw.pad_io12_cfg.rx_en.q; + mux_to_pads_o.pad_io12.tx_en = s_reg2hw.pad_io12_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io13 + always_comb begin + unique case (s_reg2hw.pad_io13_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_DEFAULT: begin + mux_to_pads_o.pad_io13.chip2pad = s_reg2hw.pad_io13_cfg.chip2pad.q; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_GPIO_GPIO13: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.gpio.gpio13_out; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = ~port_signals_soc2pad_i.gpio.gpio13_tx_en; + mux_to_pads_o.pad_io13.tx_en = port_signals_soc2pad_i.gpio.gpio13_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io13.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io13.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_UART0_RX: begin + mux_to_pads_o.pad_io13.chip2pad = 1'b1; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = 1'b1; + mux_to_pads_o.pad_io13.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_UART0_TX: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = 1'b0; + mux_to_pads_o.pad_io13.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = 1'b0; + mux_to_pads_o.pad_io13.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = 1'b0; + mux_to_pads_o.pad_io13.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = 1'b0; + mux_to_pads_o.pad_io13.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = 1'b0; + mux_to_pads_o.pad_io13.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = 1'b0; + mux_to_pads_o.pad_io13.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io13.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io13.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io13.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io13.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io13.chip2pad = 1'b0; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io13.chip2pad = 1'b0; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io13.chip2pad = 1'b0; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io13.chip2pad = 1'b0; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io13.chip2pad = 1'b0; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io13.chip2pad = 1'b0; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io13.chip2pad = 1'b0; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io13.chip2pad = 1'b0; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io13.chip2pad = 1'b0; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io13.chip2pad = 1'b0; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io13.chip2pad = 1'b0; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io13.chip2pad = 1'b0; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io13.chip2pad = 1'b0; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = 1'b0; + mux_to_pads_o.pad_io13.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io13.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io13.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io13.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io13.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io13.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io13.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = 1'b0; + mux_to_pads_o.pad_io13.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = 1'b0; + mux_to_pads_o.pad_io13.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io13.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io13.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io13.chip2pad = s_reg2hw.pad_io13_cfg.chip2pad.q; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = 1'b1; + mux_to_pads_o.pad_io13.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io13.chip2pad = s_reg2hw.pad_io13_cfg.chip2pad.q; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = 1'b1; + mux_to_pads_o.pad_io13.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io13.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io13.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io13.chip2pad = s_reg2hw.pad_io13_cfg.chip2pad.q; + mux_to_pads_o.pad_io13.pull_en = s_reg2hw.pad_io13_cfg.pull_en.q; + mux_to_pads_o.pad_io13.rx_en = s_reg2hw.pad_io13_cfg.rx_en.q; + mux_to_pads_o.pad_io13.tx_en = s_reg2hw.pad_io13_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io14 + always_comb begin + unique case (s_reg2hw.pad_io14_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_DEFAULT: begin + mux_to_pads_o.pad_io14.chip2pad = s_reg2hw.pad_io14_cfg.chip2pad.q; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_GPIO_GPIO14: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.gpio.gpio14_out; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = ~port_signals_soc2pad_i.gpio.gpio14_tx_en; + mux_to_pads_o.pad_io14.tx_en = port_signals_soc2pad_i.gpio.gpio14_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io14.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io14.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_UART0_RX: begin + mux_to_pads_o.pad_io14.chip2pad = 1'b1; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = 1'b1; + mux_to_pads_o.pad_io14.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_UART0_TX: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = 1'b0; + mux_to_pads_o.pad_io14.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = 1'b0; + mux_to_pads_o.pad_io14.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = 1'b0; + mux_to_pads_o.pad_io14.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = 1'b0; + mux_to_pads_o.pad_io14.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = 1'b0; + mux_to_pads_o.pad_io14.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = 1'b0; + mux_to_pads_o.pad_io14.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io14.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io14.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io14.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io14.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io14.chip2pad = 1'b0; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io14.chip2pad = 1'b0; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io14.chip2pad = 1'b0; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io14.chip2pad = 1'b0; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io14.chip2pad = 1'b0; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io14.chip2pad = 1'b0; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io14.chip2pad = 1'b0; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io14.chip2pad = 1'b0; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io14.chip2pad = 1'b0; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io14.chip2pad = 1'b0; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io14.chip2pad = 1'b0; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io14.chip2pad = 1'b0; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io14.chip2pad = 1'b0; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = 1'b0; + mux_to_pads_o.pad_io14.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io14.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io14.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io14.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io14.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io14.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io14.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = 1'b0; + mux_to_pads_o.pad_io14.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = 1'b0; + mux_to_pads_o.pad_io14.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io14.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io14.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io14.chip2pad = s_reg2hw.pad_io14_cfg.chip2pad.q; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = 1'b1; + mux_to_pads_o.pad_io14.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io14.chip2pad = s_reg2hw.pad_io14_cfg.chip2pad.q; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = 1'b1; + mux_to_pads_o.pad_io14.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io14.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io14.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io14.chip2pad = s_reg2hw.pad_io14_cfg.chip2pad.q; + mux_to_pads_o.pad_io14.pull_en = s_reg2hw.pad_io14_cfg.pull_en.q; + mux_to_pads_o.pad_io14.rx_en = s_reg2hw.pad_io14_cfg.rx_en.q; + mux_to_pads_o.pad_io14.tx_en = s_reg2hw.pad_io14_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io15 + always_comb begin + unique case (s_reg2hw.pad_io15_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_DEFAULT: begin + mux_to_pads_o.pad_io15.chip2pad = s_reg2hw.pad_io15_cfg.chip2pad.q; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_GPIO_GPIO15: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.gpio.gpio15_out; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = ~port_signals_soc2pad_i.gpio.gpio15_tx_en; + mux_to_pads_o.pad_io15.tx_en = port_signals_soc2pad_i.gpio.gpio15_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io15.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io15.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_UART0_RX: begin + mux_to_pads_o.pad_io15.chip2pad = 1'b1; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = 1'b1; + mux_to_pads_o.pad_io15.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_UART0_TX: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = 1'b0; + mux_to_pads_o.pad_io15.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = 1'b0; + mux_to_pads_o.pad_io15.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = 1'b0; + mux_to_pads_o.pad_io15.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = 1'b0; + mux_to_pads_o.pad_io15.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = 1'b0; + mux_to_pads_o.pad_io15.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = 1'b0; + mux_to_pads_o.pad_io15.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io15.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io15.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io15.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io15.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io15.chip2pad = 1'b0; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io15.chip2pad = 1'b0; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io15.chip2pad = 1'b0; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io15.chip2pad = 1'b0; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io15.chip2pad = 1'b0; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io15.chip2pad = 1'b0; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io15.chip2pad = 1'b0; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io15.chip2pad = 1'b0; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io15.chip2pad = 1'b0; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io15.chip2pad = 1'b0; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io15.chip2pad = 1'b0; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io15.chip2pad = 1'b0; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io15.chip2pad = 1'b0; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = 1'b0; + mux_to_pads_o.pad_io15.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io15.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io15.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io15.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io15.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io15.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io15.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = 1'b0; + mux_to_pads_o.pad_io15.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = 1'b0; + mux_to_pads_o.pad_io15.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io15.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io15.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io15.chip2pad = s_reg2hw.pad_io15_cfg.chip2pad.q; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = 1'b1; + mux_to_pads_o.pad_io15.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io15.chip2pad = s_reg2hw.pad_io15_cfg.chip2pad.q; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = 1'b1; + mux_to_pads_o.pad_io15.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io15.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io15.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io15.chip2pad = s_reg2hw.pad_io15_cfg.chip2pad.q; + mux_to_pads_o.pad_io15.pull_en = s_reg2hw.pad_io15_cfg.pull_en.q; + mux_to_pads_o.pad_io15.rx_en = s_reg2hw.pad_io15_cfg.rx_en.q; + mux_to_pads_o.pad_io15.tx_en = s_reg2hw.pad_io15_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io16 + always_comb begin + unique case (s_reg2hw.pad_io16_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_DEFAULT: begin + mux_to_pads_o.pad_io16.chip2pad = s_reg2hw.pad_io16_cfg.chip2pad.q; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_GPIO_GPIO16: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.gpio.gpio16_out; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = ~port_signals_soc2pad_i.gpio.gpio16_tx_en; + mux_to_pads_o.pad_io16.tx_en = port_signals_soc2pad_i.gpio.gpio16_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io16.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io16.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_UART0_RX: begin + mux_to_pads_o.pad_io16.chip2pad = 1'b1; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = 1'b1; + mux_to_pads_o.pad_io16.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_UART0_TX: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = 1'b0; + mux_to_pads_o.pad_io16.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = 1'b0; + mux_to_pads_o.pad_io16.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = 1'b0; + mux_to_pads_o.pad_io16.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = 1'b0; + mux_to_pads_o.pad_io16.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = 1'b0; + mux_to_pads_o.pad_io16.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = 1'b0; + mux_to_pads_o.pad_io16.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io16.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io16.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io16.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io16.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io16.chip2pad = 1'b0; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io16.chip2pad = 1'b0; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io16.chip2pad = 1'b0; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io16.chip2pad = 1'b0; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io16.chip2pad = 1'b0; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io16.chip2pad = 1'b0; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io16.chip2pad = 1'b0; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io16.chip2pad = 1'b0; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io16.chip2pad = 1'b0; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io16.chip2pad = 1'b0; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io16.chip2pad = 1'b0; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io16.chip2pad = 1'b0; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io16.chip2pad = 1'b0; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = 1'b0; + mux_to_pads_o.pad_io16.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io16.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io16.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io16.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io16.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io16.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io16.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = 1'b0; + mux_to_pads_o.pad_io16.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = 1'b0; + mux_to_pads_o.pad_io16.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io16.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io16.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io16.chip2pad = s_reg2hw.pad_io16_cfg.chip2pad.q; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = 1'b1; + mux_to_pads_o.pad_io16.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io16.chip2pad = s_reg2hw.pad_io16_cfg.chip2pad.q; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = 1'b1; + mux_to_pads_o.pad_io16.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io16.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io16.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io16.chip2pad = s_reg2hw.pad_io16_cfg.chip2pad.q; + mux_to_pads_o.pad_io16.pull_en = s_reg2hw.pad_io16_cfg.pull_en.q; + mux_to_pads_o.pad_io16.rx_en = s_reg2hw.pad_io16_cfg.rx_en.q; + mux_to_pads_o.pad_io16.tx_en = s_reg2hw.pad_io16_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io17 + always_comb begin + unique case (s_reg2hw.pad_io17_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_DEFAULT: begin + mux_to_pads_o.pad_io17.chip2pad = s_reg2hw.pad_io17_cfg.chip2pad.q; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_GPIO_GPIO17: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.gpio.gpio17_out; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = ~port_signals_soc2pad_i.gpio.gpio17_tx_en; + mux_to_pads_o.pad_io17.tx_en = port_signals_soc2pad_i.gpio.gpio17_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io17.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io17.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_UART0_RX: begin + mux_to_pads_o.pad_io17.chip2pad = 1'b1; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = 1'b1; + mux_to_pads_o.pad_io17.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_UART0_TX: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = 1'b0; + mux_to_pads_o.pad_io17.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = 1'b0; + mux_to_pads_o.pad_io17.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = 1'b0; + mux_to_pads_o.pad_io17.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = 1'b0; + mux_to_pads_o.pad_io17.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = 1'b0; + mux_to_pads_o.pad_io17.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = 1'b0; + mux_to_pads_o.pad_io17.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io17.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io17.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io17.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io17.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io17.chip2pad = 1'b0; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io17.chip2pad = 1'b0; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io17.chip2pad = 1'b0; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io17.chip2pad = 1'b0; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io17.chip2pad = 1'b0; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io17.chip2pad = 1'b0; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io17.chip2pad = 1'b0; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io17.chip2pad = 1'b0; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io17.chip2pad = 1'b0; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io17.chip2pad = 1'b0; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io17.chip2pad = 1'b0; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io17.chip2pad = 1'b0; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io17.chip2pad = 1'b0; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = 1'b0; + mux_to_pads_o.pad_io17.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io17.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io17.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io17.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io17.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io17.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io17.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = 1'b0; + mux_to_pads_o.pad_io17.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = 1'b0; + mux_to_pads_o.pad_io17.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io17.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io17.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io17.chip2pad = s_reg2hw.pad_io17_cfg.chip2pad.q; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = 1'b1; + mux_to_pads_o.pad_io17.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io17.chip2pad = s_reg2hw.pad_io17_cfg.chip2pad.q; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = 1'b1; + mux_to_pads_o.pad_io17.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io17.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io17.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io17.chip2pad = s_reg2hw.pad_io17_cfg.chip2pad.q; + mux_to_pads_o.pad_io17.pull_en = s_reg2hw.pad_io17_cfg.pull_en.q; + mux_to_pads_o.pad_io17.rx_en = s_reg2hw.pad_io17_cfg.rx_en.q; + mux_to_pads_o.pad_io17.tx_en = s_reg2hw.pad_io17_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io18 + always_comb begin + unique case (s_reg2hw.pad_io18_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_DEFAULT: begin + mux_to_pads_o.pad_io18.chip2pad = s_reg2hw.pad_io18_cfg.chip2pad.q; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_GPIO_GPIO18: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.gpio.gpio18_out; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = ~port_signals_soc2pad_i.gpio.gpio18_tx_en; + mux_to_pads_o.pad_io18.tx_en = port_signals_soc2pad_i.gpio.gpio18_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io18.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io18.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_UART0_RX: begin + mux_to_pads_o.pad_io18.chip2pad = 1'b1; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = 1'b1; + mux_to_pads_o.pad_io18.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_UART0_TX: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = 1'b0; + mux_to_pads_o.pad_io18.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = 1'b0; + mux_to_pads_o.pad_io18.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = 1'b0; + mux_to_pads_o.pad_io18.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = 1'b0; + mux_to_pads_o.pad_io18.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = 1'b0; + mux_to_pads_o.pad_io18.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = 1'b0; + mux_to_pads_o.pad_io18.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io18.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io18.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io18.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io18.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io18.chip2pad = 1'b0; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io18.chip2pad = 1'b0; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io18.chip2pad = 1'b0; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io18.chip2pad = 1'b0; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io18.chip2pad = 1'b0; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io18.chip2pad = 1'b0; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io18.chip2pad = 1'b0; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io18.chip2pad = 1'b0; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io18.chip2pad = 1'b0; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io18.chip2pad = 1'b0; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io18.chip2pad = 1'b0; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io18.chip2pad = 1'b0; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io18.chip2pad = 1'b0; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = 1'b0; + mux_to_pads_o.pad_io18.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io18.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io18.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io18.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io18.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io18.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io18.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = 1'b0; + mux_to_pads_o.pad_io18.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = 1'b0; + mux_to_pads_o.pad_io18.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io18.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io18.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io18.chip2pad = s_reg2hw.pad_io18_cfg.chip2pad.q; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = 1'b1; + mux_to_pads_o.pad_io18.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io18.chip2pad = s_reg2hw.pad_io18_cfg.chip2pad.q; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = 1'b1; + mux_to_pads_o.pad_io18.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io18.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io18.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io18.chip2pad = s_reg2hw.pad_io18_cfg.chip2pad.q; + mux_to_pads_o.pad_io18.pull_en = s_reg2hw.pad_io18_cfg.pull_en.q; + mux_to_pads_o.pad_io18.rx_en = s_reg2hw.pad_io18_cfg.rx_en.q; + mux_to_pads_o.pad_io18.tx_en = s_reg2hw.pad_io18_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io19 + always_comb begin + unique case (s_reg2hw.pad_io19_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_DEFAULT: begin + mux_to_pads_o.pad_io19.chip2pad = s_reg2hw.pad_io19_cfg.chip2pad.q; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_GPIO_GPIO19: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.gpio.gpio19_out; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = ~port_signals_soc2pad_i.gpio.gpio19_tx_en; + mux_to_pads_o.pad_io19.tx_en = port_signals_soc2pad_i.gpio.gpio19_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io19.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io19.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_UART0_RX: begin + mux_to_pads_o.pad_io19.chip2pad = 1'b1; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = 1'b1; + mux_to_pads_o.pad_io19.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_UART0_TX: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = 1'b0; + mux_to_pads_o.pad_io19.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = 1'b0; + mux_to_pads_o.pad_io19.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = 1'b0; + mux_to_pads_o.pad_io19.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = 1'b0; + mux_to_pads_o.pad_io19.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = 1'b0; + mux_to_pads_o.pad_io19.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = 1'b0; + mux_to_pads_o.pad_io19.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io19.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io19.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io19.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io19.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io19.chip2pad = 1'b0; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io19.chip2pad = 1'b0; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io19.chip2pad = 1'b0; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io19.chip2pad = 1'b0; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io19.chip2pad = 1'b0; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io19.chip2pad = 1'b0; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io19.chip2pad = 1'b0; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io19.chip2pad = 1'b0; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io19.chip2pad = 1'b0; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io19.chip2pad = 1'b0; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io19.chip2pad = 1'b0; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io19.chip2pad = 1'b0; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io19.chip2pad = 1'b0; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = 1'b0; + mux_to_pads_o.pad_io19.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io19.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io19.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io19.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io19.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io19.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io19.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = 1'b0; + mux_to_pads_o.pad_io19.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = 1'b0; + mux_to_pads_o.pad_io19.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io19.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io19.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io19.chip2pad = s_reg2hw.pad_io19_cfg.chip2pad.q; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = 1'b1; + mux_to_pads_o.pad_io19.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io19.chip2pad = s_reg2hw.pad_io19_cfg.chip2pad.q; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = 1'b1; + mux_to_pads_o.pad_io19.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io19.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io19.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io19.chip2pad = s_reg2hw.pad_io19_cfg.chip2pad.q; + mux_to_pads_o.pad_io19.pull_en = s_reg2hw.pad_io19_cfg.pull_en.q; + mux_to_pads_o.pad_io19.rx_en = s_reg2hw.pad_io19_cfg.rx_en.q; + mux_to_pads_o.pad_io19.tx_en = s_reg2hw.pad_io19_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io20 + always_comb begin + unique case (s_reg2hw.pad_io20_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_DEFAULT: begin + mux_to_pads_o.pad_io20.chip2pad = s_reg2hw.pad_io20_cfg.chip2pad.q; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_GPIO_GPIO20: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.gpio.gpio20_out; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = ~port_signals_soc2pad_i.gpio.gpio20_tx_en; + mux_to_pads_o.pad_io20.tx_en = port_signals_soc2pad_i.gpio.gpio20_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io20.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io20.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_UART0_RX: begin + mux_to_pads_o.pad_io20.chip2pad = 1'b1; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = 1'b1; + mux_to_pads_o.pad_io20.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_UART0_TX: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = 1'b0; + mux_to_pads_o.pad_io20.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = 1'b0; + mux_to_pads_o.pad_io20.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = 1'b0; + mux_to_pads_o.pad_io20.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = 1'b0; + mux_to_pads_o.pad_io20.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = 1'b0; + mux_to_pads_o.pad_io20.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = 1'b0; + mux_to_pads_o.pad_io20.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io20.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io20.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io20.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io20.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io20.chip2pad = 1'b0; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io20.chip2pad = 1'b0; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io20.chip2pad = 1'b0; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io20.chip2pad = 1'b0; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io20.chip2pad = 1'b0; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io20.chip2pad = 1'b0; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io20.chip2pad = 1'b0; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io20.chip2pad = 1'b0; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io20.chip2pad = 1'b0; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io20.chip2pad = 1'b0; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io20.chip2pad = 1'b0; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io20.chip2pad = 1'b0; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io20.chip2pad = 1'b0; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = 1'b0; + mux_to_pads_o.pad_io20.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io20.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io20.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io20.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io20.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io20.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io20.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = 1'b0; + mux_to_pads_o.pad_io20.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = 1'b0; + mux_to_pads_o.pad_io20.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io20.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io20.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io20.chip2pad = s_reg2hw.pad_io20_cfg.chip2pad.q; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = 1'b1; + mux_to_pads_o.pad_io20.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io20.chip2pad = s_reg2hw.pad_io20_cfg.chip2pad.q; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = 1'b1; + mux_to_pads_o.pad_io20.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io20.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io20.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io20.chip2pad = s_reg2hw.pad_io20_cfg.chip2pad.q; + mux_to_pads_o.pad_io20.pull_en = s_reg2hw.pad_io20_cfg.pull_en.q; + mux_to_pads_o.pad_io20.rx_en = s_reg2hw.pad_io20_cfg.rx_en.q; + mux_to_pads_o.pad_io20.tx_en = s_reg2hw.pad_io20_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io21 + always_comb begin + unique case (s_reg2hw.pad_io21_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_DEFAULT: begin + mux_to_pads_o.pad_io21.chip2pad = s_reg2hw.pad_io21_cfg.chip2pad.q; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_GPIO_GPIO21: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.gpio.gpio21_out; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = ~port_signals_soc2pad_i.gpio.gpio21_tx_en; + mux_to_pads_o.pad_io21.tx_en = port_signals_soc2pad_i.gpio.gpio21_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io21.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io21.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_UART0_RX: begin + mux_to_pads_o.pad_io21.chip2pad = 1'b1; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = 1'b1; + mux_to_pads_o.pad_io21.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_UART0_TX: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = 1'b0; + mux_to_pads_o.pad_io21.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = 1'b0; + mux_to_pads_o.pad_io21.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = 1'b0; + mux_to_pads_o.pad_io21.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = 1'b0; + mux_to_pads_o.pad_io21.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = 1'b0; + mux_to_pads_o.pad_io21.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = 1'b0; + mux_to_pads_o.pad_io21.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io21.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io21.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io21.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io21.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io21.chip2pad = 1'b0; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io21.chip2pad = 1'b0; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io21.chip2pad = 1'b0; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io21.chip2pad = 1'b0; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io21.chip2pad = 1'b0; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io21.chip2pad = 1'b0; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io21.chip2pad = 1'b0; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io21.chip2pad = 1'b0; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io21.chip2pad = 1'b0; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io21.chip2pad = 1'b0; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io21.chip2pad = 1'b0; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io21.chip2pad = 1'b0; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io21.chip2pad = 1'b0; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = 1'b0; + mux_to_pads_o.pad_io21.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io21.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io21.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io21.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io21.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io21.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io21.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = 1'b0; + mux_to_pads_o.pad_io21.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = 1'b0; + mux_to_pads_o.pad_io21.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io21.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io21.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io21.chip2pad = s_reg2hw.pad_io21_cfg.chip2pad.q; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = 1'b1; + mux_to_pads_o.pad_io21.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io21.chip2pad = s_reg2hw.pad_io21_cfg.chip2pad.q; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = 1'b1; + mux_to_pads_o.pad_io21.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io21.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io21.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io21.chip2pad = s_reg2hw.pad_io21_cfg.chip2pad.q; + mux_to_pads_o.pad_io21.pull_en = s_reg2hw.pad_io21_cfg.pull_en.q; + mux_to_pads_o.pad_io21.rx_en = s_reg2hw.pad_io21_cfg.rx_en.q; + mux_to_pads_o.pad_io21.tx_en = s_reg2hw.pad_io21_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io22 + always_comb begin + unique case (s_reg2hw.pad_io22_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_DEFAULT: begin + mux_to_pads_o.pad_io22.chip2pad = s_reg2hw.pad_io22_cfg.chip2pad.q; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_GPIO_GPIO22: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.gpio.gpio22_out; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = ~port_signals_soc2pad_i.gpio.gpio22_tx_en; + mux_to_pads_o.pad_io22.tx_en = port_signals_soc2pad_i.gpio.gpio22_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io22.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io22.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_UART0_RX: begin + mux_to_pads_o.pad_io22.chip2pad = 1'b1; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = 1'b1; + mux_to_pads_o.pad_io22.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_UART0_TX: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = 1'b0; + mux_to_pads_o.pad_io22.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = 1'b0; + mux_to_pads_o.pad_io22.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = 1'b0; + mux_to_pads_o.pad_io22.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = 1'b0; + mux_to_pads_o.pad_io22.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = 1'b0; + mux_to_pads_o.pad_io22.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = 1'b0; + mux_to_pads_o.pad_io22.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io22.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io22.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io22.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io22.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io22.chip2pad = 1'b0; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io22.chip2pad = 1'b0; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io22.chip2pad = 1'b0; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io22.chip2pad = 1'b0; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io22.chip2pad = 1'b0; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io22.chip2pad = 1'b0; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io22.chip2pad = 1'b0; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io22.chip2pad = 1'b0; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io22.chip2pad = 1'b0; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io22.chip2pad = 1'b0; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io22.chip2pad = 1'b0; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io22.chip2pad = 1'b0; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io22.chip2pad = 1'b0; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = 1'b0; + mux_to_pads_o.pad_io22.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io22.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io22.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io22.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io22.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io22.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io22.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = 1'b0; + mux_to_pads_o.pad_io22.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = 1'b0; + mux_to_pads_o.pad_io22.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io22.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io22.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io22.chip2pad = s_reg2hw.pad_io22_cfg.chip2pad.q; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = 1'b1; + mux_to_pads_o.pad_io22.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io22.chip2pad = s_reg2hw.pad_io22_cfg.chip2pad.q; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = 1'b1; + mux_to_pads_o.pad_io22.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io22.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io22.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io22.chip2pad = s_reg2hw.pad_io22_cfg.chip2pad.q; + mux_to_pads_o.pad_io22.pull_en = s_reg2hw.pad_io22_cfg.pull_en.q; + mux_to_pads_o.pad_io22.rx_en = s_reg2hw.pad_io22_cfg.rx_en.q; + mux_to_pads_o.pad_io22.tx_en = s_reg2hw.pad_io22_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io23 + always_comb begin + unique case (s_reg2hw.pad_io23_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_DEFAULT: begin + mux_to_pads_o.pad_io23.chip2pad = s_reg2hw.pad_io23_cfg.chip2pad.q; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_GPIO_GPIO23: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.gpio.gpio23_out; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = ~port_signals_soc2pad_i.gpio.gpio23_tx_en; + mux_to_pads_o.pad_io23.tx_en = port_signals_soc2pad_i.gpio.gpio23_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io23.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io23.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_UART0_RX: begin + mux_to_pads_o.pad_io23.chip2pad = 1'b1; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = 1'b1; + mux_to_pads_o.pad_io23.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_UART0_TX: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = 1'b0; + mux_to_pads_o.pad_io23.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = 1'b0; + mux_to_pads_o.pad_io23.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = 1'b0; + mux_to_pads_o.pad_io23.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = 1'b0; + mux_to_pads_o.pad_io23.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = 1'b0; + mux_to_pads_o.pad_io23.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = 1'b0; + mux_to_pads_o.pad_io23.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io23.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io23.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io23.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io23.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io23.chip2pad = 1'b0; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io23.chip2pad = 1'b0; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io23.chip2pad = 1'b0; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io23.chip2pad = 1'b0; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io23.chip2pad = 1'b0; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io23.chip2pad = 1'b0; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io23.chip2pad = 1'b0; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io23.chip2pad = 1'b0; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io23.chip2pad = 1'b0; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io23.chip2pad = 1'b0; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io23.chip2pad = 1'b0; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io23.chip2pad = 1'b0; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io23.chip2pad = 1'b0; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = 1'b0; + mux_to_pads_o.pad_io23.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io23.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io23.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io23.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io23.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io23.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io23.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = 1'b0; + mux_to_pads_o.pad_io23.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = 1'b0; + mux_to_pads_o.pad_io23.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io23.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io23.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io23.chip2pad = s_reg2hw.pad_io23_cfg.chip2pad.q; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = 1'b1; + mux_to_pads_o.pad_io23.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io23.chip2pad = s_reg2hw.pad_io23_cfg.chip2pad.q; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = 1'b1; + mux_to_pads_o.pad_io23.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io23.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io23.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io23.chip2pad = s_reg2hw.pad_io23_cfg.chip2pad.q; + mux_to_pads_o.pad_io23.pull_en = s_reg2hw.pad_io23_cfg.pull_en.q; + mux_to_pads_o.pad_io23.rx_en = s_reg2hw.pad_io23_cfg.rx_en.q; + mux_to_pads_o.pad_io23.tx_en = s_reg2hw.pad_io23_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io24 + always_comb begin + unique case (s_reg2hw.pad_io24_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_DEFAULT: begin + mux_to_pads_o.pad_io24.chip2pad = s_reg2hw.pad_io24_cfg.chip2pad.q; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_GPIO_GPIO24: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.gpio.gpio24_out; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = ~port_signals_soc2pad_i.gpio.gpio24_tx_en; + mux_to_pads_o.pad_io24.tx_en = port_signals_soc2pad_i.gpio.gpio24_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io24.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io24.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_UART0_RX: begin + mux_to_pads_o.pad_io24.chip2pad = 1'b1; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = 1'b1; + mux_to_pads_o.pad_io24.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_UART0_TX: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = 1'b0; + mux_to_pads_o.pad_io24.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = 1'b0; + mux_to_pads_o.pad_io24.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = 1'b0; + mux_to_pads_o.pad_io24.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = 1'b0; + mux_to_pads_o.pad_io24.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = 1'b0; + mux_to_pads_o.pad_io24.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = 1'b0; + mux_to_pads_o.pad_io24.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io24.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io24.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io24.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io24.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io24.chip2pad = 1'b0; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io24.chip2pad = 1'b0; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io24.chip2pad = 1'b0; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io24.chip2pad = 1'b0; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io24.chip2pad = 1'b0; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io24.chip2pad = 1'b0; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io24.chip2pad = 1'b0; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io24.chip2pad = 1'b0; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io24.chip2pad = 1'b0; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io24.chip2pad = 1'b0; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io24.chip2pad = 1'b0; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io24.chip2pad = 1'b0; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io24.chip2pad = 1'b0; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = 1'b0; + mux_to_pads_o.pad_io24.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io24.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io24.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io24.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io24.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io24.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io24.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = 1'b0; + mux_to_pads_o.pad_io24.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = 1'b0; + mux_to_pads_o.pad_io24.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io24.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io24.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io24.chip2pad = s_reg2hw.pad_io24_cfg.chip2pad.q; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = 1'b1; + mux_to_pads_o.pad_io24.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io24.chip2pad = s_reg2hw.pad_io24_cfg.chip2pad.q; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = 1'b1; + mux_to_pads_o.pad_io24.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io24.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io24.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io24.chip2pad = s_reg2hw.pad_io24_cfg.chip2pad.q; + mux_to_pads_o.pad_io24.pull_en = s_reg2hw.pad_io24_cfg.pull_en.q; + mux_to_pads_o.pad_io24.rx_en = s_reg2hw.pad_io24_cfg.rx_en.q; + mux_to_pads_o.pad_io24.tx_en = s_reg2hw.pad_io24_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io25 + always_comb begin + unique case (s_reg2hw.pad_io25_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_DEFAULT: begin + mux_to_pads_o.pad_io25.chip2pad = s_reg2hw.pad_io25_cfg.chip2pad.q; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_GPIO_GPIO25: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.gpio.gpio25_out; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = ~port_signals_soc2pad_i.gpio.gpio25_tx_en; + mux_to_pads_o.pad_io25.tx_en = port_signals_soc2pad_i.gpio.gpio25_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io25.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io25.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_UART0_RX: begin + mux_to_pads_o.pad_io25.chip2pad = 1'b1; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = 1'b1; + mux_to_pads_o.pad_io25.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_UART0_TX: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = 1'b0; + mux_to_pads_o.pad_io25.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = 1'b0; + mux_to_pads_o.pad_io25.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = 1'b0; + mux_to_pads_o.pad_io25.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = 1'b0; + mux_to_pads_o.pad_io25.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = 1'b0; + mux_to_pads_o.pad_io25.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = 1'b0; + mux_to_pads_o.pad_io25.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io25.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io25.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io25.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io25.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io25.chip2pad = 1'b0; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io25.chip2pad = 1'b0; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io25.chip2pad = 1'b0; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io25.chip2pad = 1'b0; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io25.chip2pad = 1'b0; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io25.chip2pad = 1'b0; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io25.chip2pad = 1'b0; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io25.chip2pad = 1'b0; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io25.chip2pad = 1'b0; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io25.chip2pad = 1'b0; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io25.chip2pad = 1'b0; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io25.chip2pad = 1'b0; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io25.chip2pad = 1'b0; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = 1'b0; + mux_to_pads_o.pad_io25.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io25.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io25.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io25.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io25.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io25.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io25.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = 1'b0; + mux_to_pads_o.pad_io25.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = 1'b0; + mux_to_pads_o.pad_io25.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io25.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io25.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io25.chip2pad = s_reg2hw.pad_io25_cfg.chip2pad.q; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = 1'b1; + mux_to_pads_o.pad_io25.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io25.chip2pad = s_reg2hw.pad_io25_cfg.chip2pad.q; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = 1'b1; + mux_to_pads_o.pad_io25.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io25.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io25.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io25.chip2pad = s_reg2hw.pad_io25_cfg.chip2pad.q; + mux_to_pads_o.pad_io25.pull_en = s_reg2hw.pad_io25_cfg.pull_en.q; + mux_to_pads_o.pad_io25.rx_en = s_reg2hw.pad_io25_cfg.rx_en.q; + mux_to_pads_o.pad_io25.tx_en = s_reg2hw.pad_io25_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io26 + always_comb begin + unique case (s_reg2hw.pad_io26_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_DEFAULT: begin + mux_to_pads_o.pad_io26.chip2pad = s_reg2hw.pad_io26_cfg.chip2pad.q; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_GPIO_GPIO26: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.gpio.gpio26_out; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = ~port_signals_soc2pad_i.gpio.gpio26_tx_en; + mux_to_pads_o.pad_io26.tx_en = port_signals_soc2pad_i.gpio.gpio26_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io26.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io26.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_UART0_RX: begin + mux_to_pads_o.pad_io26.chip2pad = 1'b1; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = 1'b1; + mux_to_pads_o.pad_io26.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_UART0_TX: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = 1'b0; + mux_to_pads_o.pad_io26.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = 1'b0; + mux_to_pads_o.pad_io26.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = 1'b0; + mux_to_pads_o.pad_io26.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = 1'b0; + mux_to_pads_o.pad_io26.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = 1'b0; + mux_to_pads_o.pad_io26.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = 1'b0; + mux_to_pads_o.pad_io26.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io26.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io26.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io26.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io26.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io26.chip2pad = 1'b0; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io26.chip2pad = 1'b0; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io26.chip2pad = 1'b0; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io26.chip2pad = 1'b0; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io26.chip2pad = 1'b0; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io26.chip2pad = 1'b0; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io26.chip2pad = 1'b0; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io26.chip2pad = 1'b0; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io26.chip2pad = 1'b0; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io26.chip2pad = 1'b0; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io26.chip2pad = 1'b0; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io26.chip2pad = 1'b0; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io26.chip2pad = 1'b0; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = 1'b0; + mux_to_pads_o.pad_io26.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io26.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io26.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io26.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io26.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io26.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io26.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = 1'b0; + mux_to_pads_o.pad_io26.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = 1'b0; + mux_to_pads_o.pad_io26.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io26.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io26.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io26.chip2pad = s_reg2hw.pad_io26_cfg.chip2pad.q; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = 1'b1; + mux_to_pads_o.pad_io26.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io26.chip2pad = s_reg2hw.pad_io26_cfg.chip2pad.q; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = 1'b1; + mux_to_pads_o.pad_io26.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io26.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io26.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io26.chip2pad = s_reg2hw.pad_io26_cfg.chip2pad.q; + mux_to_pads_o.pad_io26.pull_en = s_reg2hw.pad_io26_cfg.pull_en.q; + mux_to_pads_o.pad_io26.rx_en = s_reg2hw.pad_io26_cfg.rx_en.q; + mux_to_pads_o.pad_io26.tx_en = s_reg2hw.pad_io26_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io27 + always_comb begin + unique case (s_reg2hw.pad_io27_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_DEFAULT: begin + mux_to_pads_o.pad_io27.chip2pad = s_reg2hw.pad_io27_cfg.chip2pad.q; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_GPIO_GPIO27: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.gpio.gpio27_out; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = ~port_signals_soc2pad_i.gpio.gpio27_tx_en; + mux_to_pads_o.pad_io27.tx_en = port_signals_soc2pad_i.gpio.gpio27_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io27.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io27.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_UART0_RX: begin + mux_to_pads_o.pad_io27.chip2pad = 1'b1; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = 1'b1; + mux_to_pads_o.pad_io27.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_UART0_TX: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = 1'b0; + mux_to_pads_o.pad_io27.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = 1'b0; + mux_to_pads_o.pad_io27.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = 1'b0; + mux_to_pads_o.pad_io27.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = 1'b0; + mux_to_pads_o.pad_io27.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = 1'b0; + mux_to_pads_o.pad_io27.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = 1'b0; + mux_to_pads_o.pad_io27.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io27.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io27.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io27.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io27.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io27.chip2pad = 1'b0; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io27.chip2pad = 1'b0; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io27.chip2pad = 1'b0; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io27.chip2pad = 1'b0; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io27.chip2pad = 1'b0; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io27.chip2pad = 1'b0; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io27.chip2pad = 1'b0; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io27.chip2pad = 1'b0; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io27.chip2pad = 1'b0; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io27.chip2pad = 1'b0; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io27.chip2pad = 1'b0; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io27.chip2pad = 1'b0; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io27.chip2pad = 1'b0; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = 1'b0; + mux_to_pads_o.pad_io27.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io27.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io27.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io27.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io27.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io27.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io27.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = 1'b0; + mux_to_pads_o.pad_io27.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = 1'b0; + mux_to_pads_o.pad_io27.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io27.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io27.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io27.chip2pad = s_reg2hw.pad_io27_cfg.chip2pad.q; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = 1'b1; + mux_to_pads_o.pad_io27.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io27.chip2pad = s_reg2hw.pad_io27_cfg.chip2pad.q; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = 1'b1; + mux_to_pads_o.pad_io27.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io27.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io27.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io27.chip2pad = s_reg2hw.pad_io27_cfg.chip2pad.q; + mux_to_pads_o.pad_io27.pull_en = s_reg2hw.pad_io27_cfg.pull_en.q; + mux_to_pads_o.pad_io27.rx_en = s_reg2hw.pad_io27_cfg.rx_en.q; + mux_to_pads_o.pad_io27.tx_en = s_reg2hw.pad_io27_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io28 + always_comb begin + unique case (s_reg2hw.pad_io28_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_DEFAULT: begin + mux_to_pads_o.pad_io28.chip2pad = s_reg2hw.pad_io28_cfg.chip2pad.q; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_GPIO_GPIO28: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.gpio.gpio28_out; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = ~port_signals_soc2pad_i.gpio.gpio28_tx_en; + mux_to_pads_o.pad_io28.tx_en = port_signals_soc2pad_i.gpio.gpio28_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io28.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io28.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_UART0_RX: begin + mux_to_pads_o.pad_io28.chip2pad = 1'b1; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = 1'b1; + mux_to_pads_o.pad_io28.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_UART0_TX: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = 1'b0; + mux_to_pads_o.pad_io28.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = 1'b0; + mux_to_pads_o.pad_io28.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = 1'b0; + mux_to_pads_o.pad_io28.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = 1'b0; + mux_to_pads_o.pad_io28.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = 1'b0; + mux_to_pads_o.pad_io28.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = 1'b0; + mux_to_pads_o.pad_io28.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io28.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io28.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io28.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io28.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io28.chip2pad = 1'b0; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io28.chip2pad = 1'b0; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io28.chip2pad = 1'b0; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io28.chip2pad = 1'b0; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io28.chip2pad = 1'b0; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io28.chip2pad = 1'b0; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io28.chip2pad = 1'b0; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io28.chip2pad = 1'b0; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io28.chip2pad = 1'b0; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io28.chip2pad = 1'b0; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io28.chip2pad = 1'b0; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io28.chip2pad = 1'b0; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io28.chip2pad = 1'b0; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = 1'b0; + mux_to_pads_o.pad_io28.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io28.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io28.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io28.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io28.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io28.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io28.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = 1'b0; + mux_to_pads_o.pad_io28.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = 1'b0; + mux_to_pads_o.pad_io28.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io28.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io28.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io28.chip2pad = s_reg2hw.pad_io28_cfg.chip2pad.q; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = 1'b1; + mux_to_pads_o.pad_io28.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io28.chip2pad = s_reg2hw.pad_io28_cfg.chip2pad.q; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = 1'b1; + mux_to_pads_o.pad_io28.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io28.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io28.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io28.chip2pad = s_reg2hw.pad_io28_cfg.chip2pad.q; + mux_to_pads_o.pad_io28.pull_en = s_reg2hw.pad_io28_cfg.pull_en.q; + mux_to_pads_o.pad_io28.rx_en = s_reg2hw.pad_io28_cfg.rx_en.q; + mux_to_pads_o.pad_io28.tx_en = s_reg2hw.pad_io28_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io29 + always_comb begin + unique case (s_reg2hw.pad_io29_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_DEFAULT: begin + mux_to_pads_o.pad_io29.chip2pad = s_reg2hw.pad_io29_cfg.chip2pad.q; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_GPIO_GPIO29: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.gpio.gpio29_out; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = ~port_signals_soc2pad_i.gpio.gpio29_tx_en; + mux_to_pads_o.pad_io29.tx_en = port_signals_soc2pad_i.gpio.gpio29_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io29.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io29.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_UART0_RX: begin + mux_to_pads_o.pad_io29.chip2pad = 1'b1; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = 1'b1; + mux_to_pads_o.pad_io29.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_UART0_TX: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = 1'b0; + mux_to_pads_o.pad_io29.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = 1'b0; + mux_to_pads_o.pad_io29.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = 1'b0; + mux_to_pads_o.pad_io29.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = 1'b0; + mux_to_pads_o.pad_io29.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = 1'b0; + mux_to_pads_o.pad_io29.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = 1'b0; + mux_to_pads_o.pad_io29.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io29.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io29.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io29.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io29.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io29.chip2pad = 1'b0; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io29.chip2pad = 1'b0; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io29.chip2pad = 1'b0; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io29.chip2pad = 1'b0; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io29.chip2pad = 1'b0; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io29.chip2pad = 1'b0; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io29.chip2pad = 1'b0; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io29.chip2pad = 1'b0; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io29.chip2pad = 1'b0; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io29.chip2pad = 1'b0; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io29.chip2pad = 1'b0; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io29.chip2pad = 1'b0; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io29.chip2pad = 1'b0; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = 1'b0; + mux_to_pads_o.pad_io29.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io29.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io29.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io29.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io29.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io29.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io29.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = 1'b0; + mux_to_pads_o.pad_io29.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = 1'b0; + mux_to_pads_o.pad_io29.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io29.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io29.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io29.chip2pad = s_reg2hw.pad_io29_cfg.chip2pad.q; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = 1'b1; + mux_to_pads_o.pad_io29.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io29.chip2pad = s_reg2hw.pad_io29_cfg.chip2pad.q; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = 1'b1; + mux_to_pads_o.pad_io29.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io29.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io29.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io29.chip2pad = s_reg2hw.pad_io29_cfg.chip2pad.q; + mux_to_pads_o.pad_io29.pull_en = s_reg2hw.pad_io29_cfg.pull_en.q; + mux_to_pads_o.pad_io29.rx_en = s_reg2hw.pad_io29_cfg.rx_en.q; + mux_to_pads_o.pad_io29.tx_en = s_reg2hw.pad_io29_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io30 + always_comb begin + unique case (s_reg2hw.pad_io30_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_DEFAULT: begin + mux_to_pads_o.pad_io30.chip2pad = s_reg2hw.pad_io30_cfg.chip2pad.q; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_GPIO_GPIO30: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.gpio.gpio30_out; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = ~port_signals_soc2pad_i.gpio.gpio30_tx_en; + mux_to_pads_o.pad_io30.tx_en = port_signals_soc2pad_i.gpio.gpio30_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io30.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io30.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_UART0_RX: begin + mux_to_pads_o.pad_io30.chip2pad = 1'b1; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = 1'b1; + mux_to_pads_o.pad_io30.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_UART0_TX: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = 1'b0; + mux_to_pads_o.pad_io30.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = 1'b0; + mux_to_pads_o.pad_io30.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = 1'b0; + mux_to_pads_o.pad_io30.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = 1'b0; + mux_to_pads_o.pad_io30.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = 1'b0; + mux_to_pads_o.pad_io30.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = 1'b0; + mux_to_pads_o.pad_io30.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io30.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io30.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io30.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io30.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io30.chip2pad = 1'b0; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io30.chip2pad = 1'b0; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io30.chip2pad = 1'b0; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io30.chip2pad = 1'b0; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io30.chip2pad = 1'b0; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io30.chip2pad = 1'b0; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io30.chip2pad = 1'b0; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io30.chip2pad = 1'b0; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io30.chip2pad = 1'b0; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io30.chip2pad = 1'b0; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io30.chip2pad = 1'b0; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io30.chip2pad = 1'b0; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io30.chip2pad = 1'b0; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = 1'b0; + mux_to_pads_o.pad_io30.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io30.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io30.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io30.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io30.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io30.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io30.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = 1'b0; + mux_to_pads_o.pad_io30.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = 1'b0; + mux_to_pads_o.pad_io30.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io30.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io30.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io30.chip2pad = s_reg2hw.pad_io30_cfg.chip2pad.q; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = 1'b1; + mux_to_pads_o.pad_io30.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io30.chip2pad = s_reg2hw.pad_io30_cfg.chip2pad.q; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = 1'b1; + mux_to_pads_o.pad_io30.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io30.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io30.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io30.chip2pad = s_reg2hw.pad_io30_cfg.chip2pad.q; + mux_to_pads_o.pad_io30.pull_en = s_reg2hw.pad_io30_cfg.pull_en.q; + mux_to_pads_o.pad_io30.rx_en = s_reg2hw.pad_io30_cfg.rx_en.q; + mux_to_pads_o.pad_io30.tx_en = s_reg2hw.pad_io30_cfg.tx_en.q; + end + endcase + end // always_comb + + // Pad pad_io31 + always_comb begin + unique case (s_reg2hw.pad_io31_mux_sel.q) + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_DEFAULT: begin + mux_to_pads_o.pad_io31.chip2pad = s_reg2hw.pad_io31_cfg.chip2pad.q; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_GPIO_GPIO31: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.gpio.gpio31_out; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = ~port_signals_soc2pad_i.gpio.gpio31_tx_en; + mux_to_pads_o.pad_io31.tx_en = port_signals_soc2pad_i.gpio.gpio31_tx_en; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2C0_SCL: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.i2c0.scl_o; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = port_signals_soc2pad_i.i2c0.scl_oe; + mux_to_pads_o.pad_io31.tx_en = ~port_signals_soc2pad_i.i2c0.scl_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2C0_SDA: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.i2c0.sda_o; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = ~port_signals_soc2pad_i.i2c0.sda_oe; + mux_to_pads_o.pad_io31.tx_en = port_signals_soc2pad_i.i2c0.sda_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_UART0_RX: begin + mux_to_pads_o.pad_io31.chip2pad = 1'b1; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = 1'b1; + mux_to_pads_o.pad_io31.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_UART0_TX: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.uart0.tx_o; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = 1'b0; + mux_to_pads_o.pad_io31.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_CSN0: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.qspim0.csn0_o; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = 1'b0; + mux_to_pads_o.pad_io31.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_CSN1: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.qspim0.csn1_o; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = 1'b0; + mux_to_pads_o.pad_io31.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_CSN2: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.qspim0.csn2_o; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = 1'b0; + mux_to_pads_o.pad_io31.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_CSN3: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.qspim0.csn3_o; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = 1'b0; + mux_to_pads_o.pad_io31.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_SCK: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.qspim0.sck_o; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = 1'b0; + mux_to_pads_o.pad_io31.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_SDIO0: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.qspim0.sd0_o; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = ~port_signals_soc2pad_i.qspim0.sd0_oe; + mux_to_pads_o.pad_io31.tx_en = port_signals_soc2pad_i.qspim0.sd0_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_SDIO1: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.qspim0.sd1_o; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = ~port_signals_soc2pad_i.qspim0.sd1_oe; + mux_to_pads_o.pad_io31.tx_en = port_signals_soc2pad_i.qspim0.sd1_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_SDIO2: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.qspim0.sd2_o; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = ~port_signals_soc2pad_i.qspim0.sd2_oe; + mux_to_pads_o.pad_io31.tx_en = port_signals_soc2pad_i.qspim0.sd2_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_SDIO3: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.qspim0.sd3_o; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = ~port_signals_soc2pad_i.qspim0.sd3_oe; + mux_to_pads_o.pad_io31.tx_en = port_signals_soc2pad_i.qspim0.sd3_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA0: begin + mux_to_pads_o.pad_io31.chip2pad = 1'b0; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA1: begin + mux_to_pads_o.pad_io31.chip2pad = 1'b0; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA2: begin + mux_to_pads_o.pad_io31.chip2pad = 1'b0; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA3: begin + mux_to_pads_o.pad_io31.chip2pad = 1'b0; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA4: begin + mux_to_pads_o.pad_io31.chip2pad = 1'b0; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA5: begin + mux_to_pads_o.pad_io31.chip2pad = 1'b0; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA6: begin + mux_to_pads_o.pad_io31.chip2pad = 1'b0; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA7: begin + mux_to_pads_o.pad_io31.chip2pad = 1'b0; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA8: begin + mux_to_pads_o.pad_io31.chip2pad = 1'b0; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA9: begin + mux_to_pads_o.pad_io31.chip2pad = 1'b0; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_HSYNC: begin + mux_to_pads_o.pad_io31.chip2pad = 1'b0; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_PCLK: begin + mux_to_pads_o.pad_io31.chip2pad = 1'b0; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_VSYNC: begin + mux_to_pads_o.pad_io31.chip2pad = 1'b0; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDCLK: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.sdio0.sdclk_out; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = 1'b0; + mux_to_pads_o.pad_io31.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDCMD: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.sdio0.sdcmd_out; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = port_signals_soc2pad_i.sdio0.sdcmd_oen; + mux_to_pads_o.pad_io31.tx_en = ~port_signals_soc2pad_i.sdio0.sdcmd_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDDATA0: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.sdio0.sddata0_out; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = port_signals_soc2pad_i.sdio0.sddata0_oen; + mux_to_pads_o.pad_io31.tx_en = ~port_signals_soc2pad_i.sdio0.sddata0_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDDATA1: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.sdio0.sddata1_out; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = port_signals_soc2pad_i.sdio0.sddata1_oen; + mux_to_pads_o.pad_io31.tx_en = ~port_signals_soc2pad_i.sdio0.sddata1_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDDATA2: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.sdio0.sddata2_out; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = port_signals_soc2pad_i.sdio0.sddata2_oen; + mux_to_pads_o.pad_io31.tx_en = ~port_signals_soc2pad_i.sdio0.sddata2_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDDATA3: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.sdio0.sddata3_out; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = port_signals_soc2pad_i.sdio0.sddata3_oen; + mux_to_pads_o.pad_io31.tx_en = ~port_signals_soc2pad_i.sdio0.sddata3_oen; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_MASTER_SCK: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.i2s0.master_sck_out; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = ~port_signals_soc2pad_i.i2s0.master_sck_oe; + mux_to_pads_o.pad_io31.tx_en = port_signals_soc2pad_i.i2s0.master_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_MASTER_SD0: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.i2s0.master_sd0_out; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = 1'b0; + mux_to_pads_o.pad_io31.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_MASTER_SD1: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.i2s0.master_sd1_out; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = 1'b0; + mux_to_pads_o.pad_io31.tx_en = 1'b1; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_MASTER_WS: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.i2s0.master_ws_out; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = ~port_signals_soc2pad_i.i2s0.master_ws_oe; + mux_to_pads_o.pad_io31.tx_en = port_signals_soc2pad_i.i2s0.master_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_SLAVE_SCK: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.i2s0.slave_sck_out; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = ~port_signals_soc2pad_i.i2s0.slave_sck_oe; + mux_to_pads_o.pad_io31.tx_en = port_signals_soc2pad_i.i2s0.slave_sck_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_SLAVE_SD0: begin + mux_to_pads_o.pad_io31.chip2pad = s_reg2hw.pad_io31_cfg.chip2pad.q; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = 1'b1; + mux_to_pads_o.pad_io31.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_SLAVE_SD1: begin + mux_to_pads_o.pad_io31.chip2pad = s_reg2hw.pad_io31_cfg.chip2pad.q; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = 1'b1; + mux_to_pads_o.pad_io31.tx_en = 1'b0; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_SLAVE_WS: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.i2s0.slave_ws_out; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = ~port_signals_soc2pad_i.i2s0.slave_ws_oe; + mux_to_pads_o.pad_io31.tx_en = port_signals_soc2pad_i.i2s0.slave_ws_oe; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER0_OUT0: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer0.timer_out0; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER0_OUT1: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer0.timer_out1; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER0_OUT2: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer0.timer_out2; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER0_OUT3: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer0.timer_out3; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER1_OUT0: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer1.timer_out0; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER1_OUT1: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer1.timer_out1; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER1_OUT2: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer1.timer_out2; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER1_OUT3: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer1.timer_out3; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER2_OUT0: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer2.timer_out0; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER2_OUT1: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer2.timer_out1; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER2_OUT2: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer2.timer_out2; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER2_OUT3: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer2.timer_out3; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER3_OUT0: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer3.timer_out0; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER3_OUT1: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer3.timer_out1; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER3_OUT2: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer3.timer_out2; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_TIMER3_OUT3: begin + mux_to_pads_o.pad_io31.chip2pad = port_signals_soc2pad_i.timer3.timer_out3; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + default: begin + mux_to_pads_o.pad_io31.chip2pad = s_reg2hw.pad_io31_cfg.chip2pad.q; + mux_to_pads_o.pad_io31.pull_en = s_reg2hw.pad_io31_cfg.pull_en.q; + mux_to_pads_o.pad_io31.rx_en = s_reg2hw.pad_io31_cfg.rx_en.q; + mux_to_pads_o.pad_io31.tx_en = s_reg2hw.pad_io31_cfg.tx_en.q; + end + endcase + end // always_comb + + + // Pad -> SoC Multiplex Logic + // Port Group gpio + + // Port Signal gpio00_in + logic [0:0] port_mux_sel_gpio_gpio00_in_req; + logic [PORT_MUX_GROUP_PAD_IO00_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio00_in_arbitrated; + logic port_mux_sel_gpio_gpio00_in_no_connection; + + assign port_mux_sel_gpio_gpio00_in_req[PORT_MUX_GROUP_PAD_IO00_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_GPIO_GPIO00 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio00_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio00_in_req), + .cnt_o(port_mux_sel_gpio_gpio00_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio00_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio00_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio00_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio00_in_arbitrated) + PORT_MUX_GROUP_PAD_IO00_SEL_PAD_IO00: begin + port_signals_pad2soc_o.gpio.gpio00_in = pads_to_mux_i.pad_io00.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio00_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio01_in + logic [0:0] port_mux_sel_gpio_gpio01_in_req; + logic [PORT_MUX_GROUP_PAD_IO01_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio01_in_arbitrated; + logic port_mux_sel_gpio_gpio01_in_no_connection; + + assign port_mux_sel_gpio_gpio01_in_req[PORT_MUX_GROUP_PAD_IO01_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_GPIO_GPIO01 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio01_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio01_in_req), + .cnt_o(port_mux_sel_gpio_gpio01_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio01_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio01_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio01_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio01_in_arbitrated) + PORT_MUX_GROUP_PAD_IO01_SEL_PAD_IO01: begin + port_signals_pad2soc_o.gpio.gpio01_in = pads_to_mux_i.pad_io01.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio01_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio02_in + logic [0:0] port_mux_sel_gpio_gpio02_in_req; + logic [PORT_MUX_GROUP_PAD_IO02_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio02_in_arbitrated; + logic port_mux_sel_gpio_gpio02_in_no_connection; + + assign port_mux_sel_gpio_gpio02_in_req[PORT_MUX_GROUP_PAD_IO02_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_GPIO_GPIO02 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio02_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio02_in_req), + .cnt_o(port_mux_sel_gpio_gpio02_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio02_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio02_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio02_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio02_in_arbitrated) + PORT_MUX_GROUP_PAD_IO02_SEL_PAD_IO02: begin + port_signals_pad2soc_o.gpio.gpio02_in = pads_to_mux_i.pad_io02.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio02_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio03_in + logic [0:0] port_mux_sel_gpio_gpio03_in_req; + logic [PORT_MUX_GROUP_PAD_IO03_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio03_in_arbitrated; + logic port_mux_sel_gpio_gpio03_in_no_connection; + + assign port_mux_sel_gpio_gpio03_in_req[PORT_MUX_GROUP_PAD_IO03_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_GPIO_GPIO03 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio03_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio03_in_req), + .cnt_o(port_mux_sel_gpio_gpio03_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio03_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio03_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio03_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio03_in_arbitrated) + PORT_MUX_GROUP_PAD_IO03_SEL_PAD_IO03: begin + port_signals_pad2soc_o.gpio.gpio03_in = pads_to_mux_i.pad_io03.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio03_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio04_in + logic [0:0] port_mux_sel_gpio_gpio04_in_req; + logic [PORT_MUX_GROUP_PAD_IO04_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio04_in_arbitrated; + logic port_mux_sel_gpio_gpio04_in_no_connection; + + assign port_mux_sel_gpio_gpio04_in_req[PORT_MUX_GROUP_PAD_IO04_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_GPIO_GPIO04 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio04_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio04_in_req), + .cnt_o(port_mux_sel_gpio_gpio04_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio04_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio04_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio04_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio04_in_arbitrated) + PORT_MUX_GROUP_PAD_IO04_SEL_PAD_IO04: begin + port_signals_pad2soc_o.gpio.gpio04_in = pads_to_mux_i.pad_io04.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio04_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio05_in + logic [0:0] port_mux_sel_gpio_gpio05_in_req; + logic [PORT_MUX_GROUP_PAD_IO05_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio05_in_arbitrated; + logic port_mux_sel_gpio_gpio05_in_no_connection; + + assign port_mux_sel_gpio_gpio05_in_req[PORT_MUX_GROUP_PAD_IO05_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_GPIO_GPIO05 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio05_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio05_in_req), + .cnt_o(port_mux_sel_gpio_gpio05_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio05_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio05_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio05_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio05_in_arbitrated) + PORT_MUX_GROUP_PAD_IO05_SEL_PAD_IO05: begin + port_signals_pad2soc_o.gpio.gpio05_in = pads_to_mux_i.pad_io05.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio05_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio06_in + logic [0:0] port_mux_sel_gpio_gpio06_in_req; + logic [PORT_MUX_GROUP_PAD_IO06_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio06_in_arbitrated; + logic port_mux_sel_gpio_gpio06_in_no_connection; + + assign port_mux_sel_gpio_gpio06_in_req[PORT_MUX_GROUP_PAD_IO06_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_GPIO_GPIO06 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio06_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio06_in_req), + .cnt_o(port_mux_sel_gpio_gpio06_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio06_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio06_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio06_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio06_in_arbitrated) + PORT_MUX_GROUP_PAD_IO06_SEL_PAD_IO06: begin + port_signals_pad2soc_o.gpio.gpio06_in = pads_to_mux_i.pad_io06.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio06_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio07_in + logic [0:0] port_mux_sel_gpio_gpio07_in_req; + logic [PORT_MUX_GROUP_PAD_IO07_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio07_in_arbitrated; + logic port_mux_sel_gpio_gpio07_in_no_connection; + + assign port_mux_sel_gpio_gpio07_in_req[PORT_MUX_GROUP_PAD_IO07_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_GPIO_GPIO07 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio07_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio07_in_req), + .cnt_o(port_mux_sel_gpio_gpio07_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio07_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio07_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio07_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio07_in_arbitrated) + PORT_MUX_GROUP_PAD_IO07_SEL_PAD_IO07: begin + port_signals_pad2soc_o.gpio.gpio07_in = pads_to_mux_i.pad_io07.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio07_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio08_in + logic [0:0] port_mux_sel_gpio_gpio08_in_req; + logic [PORT_MUX_GROUP_PAD_IO08_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio08_in_arbitrated; + logic port_mux_sel_gpio_gpio08_in_no_connection; + + assign port_mux_sel_gpio_gpio08_in_req[PORT_MUX_GROUP_PAD_IO08_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_GPIO_GPIO08 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio08_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio08_in_req), + .cnt_o(port_mux_sel_gpio_gpio08_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio08_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio08_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio08_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio08_in_arbitrated) + PORT_MUX_GROUP_PAD_IO08_SEL_PAD_IO08: begin + port_signals_pad2soc_o.gpio.gpio08_in = pads_to_mux_i.pad_io08.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio08_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio09_in + logic [0:0] port_mux_sel_gpio_gpio09_in_req; + logic [PORT_MUX_GROUP_PAD_IO09_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio09_in_arbitrated; + logic port_mux_sel_gpio_gpio09_in_no_connection; + + assign port_mux_sel_gpio_gpio09_in_req[PORT_MUX_GROUP_PAD_IO09_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_GPIO_GPIO09 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio09_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio09_in_req), + .cnt_o(port_mux_sel_gpio_gpio09_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio09_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio09_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio09_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio09_in_arbitrated) + PORT_MUX_GROUP_PAD_IO09_SEL_PAD_IO09: begin + port_signals_pad2soc_o.gpio.gpio09_in = pads_to_mux_i.pad_io09.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio09_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio10_in + logic [0:0] port_mux_sel_gpio_gpio10_in_req; + logic [PORT_MUX_GROUP_PAD_IO10_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio10_in_arbitrated; + logic port_mux_sel_gpio_gpio10_in_no_connection; + + assign port_mux_sel_gpio_gpio10_in_req[PORT_MUX_GROUP_PAD_IO10_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_GPIO_GPIO10 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio10_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio10_in_req), + .cnt_o(port_mux_sel_gpio_gpio10_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio10_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio10_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio10_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio10_in_arbitrated) + PORT_MUX_GROUP_PAD_IO10_SEL_PAD_IO10: begin + port_signals_pad2soc_o.gpio.gpio10_in = pads_to_mux_i.pad_io10.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio10_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio11_in + logic [0:0] port_mux_sel_gpio_gpio11_in_req; + logic [PORT_MUX_GROUP_PAD_IO11_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio11_in_arbitrated; + logic port_mux_sel_gpio_gpio11_in_no_connection; + + assign port_mux_sel_gpio_gpio11_in_req[PORT_MUX_GROUP_PAD_IO11_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_GPIO_GPIO11 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio11_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio11_in_req), + .cnt_o(port_mux_sel_gpio_gpio11_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio11_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio11_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio11_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio11_in_arbitrated) + PORT_MUX_GROUP_PAD_IO11_SEL_PAD_IO11: begin + port_signals_pad2soc_o.gpio.gpio11_in = pads_to_mux_i.pad_io11.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio11_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio12_in + logic [0:0] port_mux_sel_gpio_gpio12_in_req; + logic [PORT_MUX_GROUP_PAD_IO12_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio12_in_arbitrated; + logic port_mux_sel_gpio_gpio12_in_no_connection; + + assign port_mux_sel_gpio_gpio12_in_req[PORT_MUX_GROUP_PAD_IO12_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_GPIO_GPIO12 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio12_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio12_in_req), + .cnt_o(port_mux_sel_gpio_gpio12_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio12_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio12_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio12_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio12_in_arbitrated) + PORT_MUX_GROUP_PAD_IO12_SEL_PAD_IO12: begin + port_signals_pad2soc_o.gpio.gpio12_in = pads_to_mux_i.pad_io12.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio12_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio13_in + logic [0:0] port_mux_sel_gpio_gpio13_in_req; + logic [PORT_MUX_GROUP_PAD_IO13_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio13_in_arbitrated; + logic port_mux_sel_gpio_gpio13_in_no_connection; + + assign port_mux_sel_gpio_gpio13_in_req[PORT_MUX_GROUP_PAD_IO13_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_GPIO_GPIO13 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio13_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio13_in_req), + .cnt_o(port_mux_sel_gpio_gpio13_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio13_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio13_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio13_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio13_in_arbitrated) + PORT_MUX_GROUP_PAD_IO13_SEL_PAD_IO13: begin + port_signals_pad2soc_o.gpio.gpio13_in = pads_to_mux_i.pad_io13.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio13_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio14_in + logic [0:0] port_mux_sel_gpio_gpio14_in_req; + logic [PORT_MUX_GROUP_PAD_IO14_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio14_in_arbitrated; + logic port_mux_sel_gpio_gpio14_in_no_connection; + + assign port_mux_sel_gpio_gpio14_in_req[PORT_MUX_GROUP_PAD_IO14_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_GPIO_GPIO14 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio14_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio14_in_req), + .cnt_o(port_mux_sel_gpio_gpio14_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio14_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio14_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio14_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio14_in_arbitrated) + PORT_MUX_GROUP_PAD_IO14_SEL_PAD_IO14: begin + port_signals_pad2soc_o.gpio.gpio14_in = pads_to_mux_i.pad_io14.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio14_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio15_in + logic [0:0] port_mux_sel_gpio_gpio15_in_req; + logic [PORT_MUX_GROUP_PAD_IO15_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio15_in_arbitrated; + logic port_mux_sel_gpio_gpio15_in_no_connection; + + assign port_mux_sel_gpio_gpio15_in_req[PORT_MUX_GROUP_PAD_IO15_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_GPIO_GPIO15 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio15_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio15_in_req), + .cnt_o(port_mux_sel_gpio_gpio15_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio15_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio15_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio15_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio15_in_arbitrated) + PORT_MUX_GROUP_PAD_IO15_SEL_PAD_IO15: begin + port_signals_pad2soc_o.gpio.gpio15_in = pads_to_mux_i.pad_io15.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio15_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio16_in + logic [0:0] port_mux_sel_gpio_gpio16_in_req; + logic [PORT_MUX_GROUP_PAD_IO16_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio16_in_arbitrated; + logic port_mux_sel_gpio_gpio16_in_no_connection; + + assign port_mux_sel_gpio_gpio16_in_req[PORT_MUX_GROUP_PAD_IO16_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_GPIO_GPIO16 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio16_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio16_in_req), + .cnt_o(port_mux_sel_gpio_gpio16_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio16_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio16_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio16_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio16_in_arbitrated) + PORT_MUX_GROUP_PAD_IO16_SEL_PAD_IO16: begin + port_signals_pad2soc_o.gpio.gpio16_in = pads_to_mux_i.pad_io16.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio16_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio17_in + logic [0:0] port_mux_sel_gpio_gpio17_in_req; + logic [PORT_MUX_GROUP_PAD_IO17_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio17_in_arbitrated; + logic port_mux_sel_gpio_gpio17_in_no_connection; + + assign port_mux_sel_gpio_gpio17_in_req[PORT_MUX_GROUP_PAD_IO17_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_GPIO_GPIO17 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio17_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio17_in_req), + .cnt_o(port_mux_sel_gpio_gpio17_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio17_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio17_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio17_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio17_in_arbitrated) + PORT_MUX_GROUP_PAD_IO17_SEL_PAD_IO17: begin + port_signals_pad2soc_o.gpio.gpio17_in = pads_to_mux_i.pad_io17.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio17_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio18_in + logic [0:0] port_mux_sel_gpio_gpio18_in_req; + logic [PORT_MUX_GROUP_PAD_IO18_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio18_in_arbitrated; + logic port_mux_sel_gpio_gpio18_in_no_connection; + + assign port_mux_sel_gpio_gpio18_in_req[PORT_MUX_GROUP_PAD_IO18_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_GPIO_GPIO18 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio18_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio18_in_req), + .cnt_o(port_mux_sel_gpio_gpio18_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio18_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio18_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio18_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio18_in_arbitrated) + PORT_MUX_GROUP_PAD_IO18_SEL_PAD_IO18: begin + port_signals_pad2soc_o.gpio.gpio18_in = pads_to_mux_i.pad_io18.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio18_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio19_in + logic [0:0] port_mux_sel_gpio_gpio19_in_req; + logic [PORT_MUX_GROUP_PAD_IO19_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio19_in_arbitrated; + logic port_mux_sel_gpio_gpio19_in_no_connection; + + assign port_mux_sel_gpio_gpio19_in_req[PORT_MUX_GROUP_PAD_IO19_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_GPIO_GPIO19 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio19_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio19_in_req), + .cnt_o(port_mux_sel_gpio_gpio19_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio19_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio19_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio19_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio19_in_arbitrated) + PORT_MUX_GROUP_PAD_IO19_SEL_PAD_IO19: begin + port_signals_pad2soc_o.gpio.gpio19_in = pads_to_mux_i.pad_io19.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio19_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio20_in + logic [0:0] port_mux_sel_gpio_gpio20_in_req; + logic [PORT_MUX_GROUP_PAD_IO20_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio20_in_arbitrated; + logic port_mux_sel_gpio_gpio20_in_no_connection; + + assign port_mux_sel_gpio_gpio20_in_req[PORT_MUX_GROUP_PAD_IO20_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_GPIO_GPIO20 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio20_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio20_in_req), + .cnt_o(port_mux_sel_gpio_gpio20_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio20_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio20_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio20_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio20_in_arbitrated) + PORT_MUX_GROUP_PAD_IO20_SEL_PAD_IO20: begin + port_signals_pad2soc_o.gpio.gpio20_in = pads_to_mux_i.pad_io20.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio20_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio21_in + logic [0:0] port_mux_sel_gpio_gpio21_in_req; + logic [PORT_MUX_GROUP_PAD_IO21_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio21_in_arbitrated; + logic port_mux_sel_gpio_gpio21_in_no_connection; + + assign port_mux_sel_gpio_gpio21_in_req[PORT_MUX_GROUP_PAD_IO21_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_GPIO_GPIO21 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio21_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio21_in_req), + .cnt_o(port_mux_sel_gpio_gpio21_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio21_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio21_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio21_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio21_in_arbitrated) + PORT_MUX_GROUP_PAD_IO21_SEL_PAD_IO21: begin + port_signals_pad2soc_o.gpio.gpio21_in = pads_to_mux_i.pad_io21.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio21_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio22_in + logic [0:0] port_mux_sel_gpio_gpio22_in_req; + logic [PORT_MUX_GROUP_PAD_IO22_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio22_in_arbitrated; + logic port_mux_sel_gpio_gpio22_in_no_connection; + + assign port_mux_sel_gpio_gpio22_in_req[PORT_MUX_GROUP_PAD_IO22_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_GPIO_GPIO22 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio22_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio22_in_req), + .cnt_o(port_mux_sel_gpio_gpio22_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio22_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio22_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio22_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio22_in_arbitrated) + PORT_MUX_GROUP_PAD_IO22_SEL_PAD_IO22: begin + port_signals_pad2soc_o.gpio.gpio22_in = pads_to_mux_i.pad_io22.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio22_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio23_in + logic [0:0] port_mux_sel_gpio_gpio23_in_req; + logic [PORT_MUX_GROUP_PAD_IO23_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio23_in_arbitrated; + logic port_mux_sel_gpio_gpio23_in_no_connection; + + assign port_mux_sel_gpio_gpio23_in_req[PORT_MUX_GROUP_PAD_IO23_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_GPIO_GPIO23 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio23_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio23_in_req), + .cnt_o(port_mux_sel_gpio_gpio23_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio23_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio23_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio23_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio23_in_arbitrated) + PORT_MUX_GROUP_PAD_IO23_SEL_PAD_IO23: begin + port_signals_pad2soc_o.gpio.gpio23_in = pads_to_mux_i.pad_io23.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio23_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio24_in + logic [0:0] port_mux_sel_gpio_gpio24_in_req; + logic [PORT_MUX_GROUP_PAD_IO24_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio24_in_arbitrated; + logic port_mux_sel_gpio_gpio24_in_no_connection; + + assign port_mux_sel_gpio_gpio24_in_req[PORT_MUX_GROUP_PAD_IO24_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_GPIO_GPIO24 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio24_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio24_in_req), + .cnt_o(port_mux_sel_gpio_gpio24_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio24_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio24_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio24_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio24_in_arbitrated) + PORT_MUX_GROUP_PAD_IO24_SEL_PAD_IO24: begin + port_signals_pad2soc_o.gpio.gpio24_in = pads_to_mux_i.pad_io24.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio24_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio25_in + logic [0:0] port_mux_sel_gpio_gpio25_in_req; + logic [PORT_MUX_GROUP_PAD_IO25_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio25_in_arbitrated; + logic port_mux_sel_gpio_gpio25_in_no_connection; + + assign port_mux_sel_gpio_gpio25_in_req[PORT_MUX_GROUP_PAD_IO25_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_GPIO_GPIO25 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio25_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio25_in_req), + .cnt_o(port_mux_sel_gpio_gpio25_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio25_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio25_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio25_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio25_in_arbitrated) + PORT_MUX_GROUP_PAD_IO25_SEL_PAD_IO25: begin + port_signals_pad2soc_o.gpio.gpio25_in = pads_to_mux_i.pad_io25.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio25_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio26_in + logic [0:0] port_mux_sel_gpio_gpio26_in_req; + logic [PORT_MUX_GROUP_PAD_IO26_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio26_in_arbitrated; + logic port_mux_sel_gpio_gpio26_in_no_connection; + + assign port_mux_sel_gpio_gpio26_in_req[PORT_MUX_GROUP_PAD_IO26_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_GPIO_GPIO26 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio26_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio26_in_req), + .cnt_o(port_mux_sel_gpio_gpio26_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio26_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio26_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio26_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio26_in_arbitrated) + PORT_MUX_GROUP_PAD_IO26_SEL_PAD_IO26: begin + port_signals_pad2soc_o.gpio.gpio26_in = pads_to_mux_i.pad_io26.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio26_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio27_in + logic [0:0] port_mux_sel_gpio_gpio27_in_req; + logic [PORT_MUX_GROUP_PAD_IO27_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio27_in_arbitrated; + logic port_mux_sel_gpio_gpio27_in_no_connection; + + assign port_mux_sel_gpio_gpio27_in_req[PORT_MUX_GROUP_PAD_IO27_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_GPIO_GPIO27 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio27_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio27_in_req), + .cnt_o(port_mux_sel_gpio_gpio27_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio27_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio27_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio27_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio27_in_arbitrated) + PORT_MUX_GROUP_PAD_IO27_SEL_PAD_IO27: begin + port_signals_pad2soc_o.gpio.gpio27_in = pads_to_mux_i.pad_io27.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio27_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio28_in + logic [0:0] port_mux_sel_gpio_gpio28_in_req; + logic [PORT_MUX_GROUP_PAD_IO28_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio28_in_arbitrated; + logic port_mux_sel_gpio_gpio28_in_no_connection; + + assign port_mux_sel_gpio_gpio28_in_req[PORT_MUX_GROUP_PAD_IO28_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_GPIO_GPIO28 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio28_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio28_in_req), + .cnt_o(port_mux_sel_gpio_gpio28_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio28_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio28_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio28_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio28_in_arbitrated) + PORT_MUX_GROUP_PAD_IO28_SEL_PAD_IO28: begin + port_signals_pad2soc_o.gpio.gpio28_in = pads_to_mux_i.pad_io28.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio28_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio29_in + logic [0:0] port_mux_sel_gpio_gpio29_in_req; + logic [PORT_MUX_GROUP_PAD_IO29_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio29_in_arbitrated; + logic port_mux_sel_gpio_gpio29_in_no_connection; + + assign port_mux_sel_gpio_gpio29_in_req[PORT_MUX_GROUP_PAD_IO29_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_GPIO_GPIO29 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio29_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio29_in_req), + .cnt_o(port_mux_sel_gpio_gpio29_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio29_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio29_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio29_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio29_in_arbitrated) + PORT_MUX_GROUP_PAD_IO29_SEL_PAD_IO29: begin + port_signals_pad2soc_o.gpio.gpio29_in = pads_to_mux_i.pad_io29.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio29_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio30_in + logic [0:0] port_mux_sel_gpio_gpio30_in_req; + logic [PORT_MUX_GROUP_PAD_IO30_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio30_in_arbitrated; + logic port_mux_sel_gpio_gpio30_in_no_connection; + + assign port_mux_sel_gpio_gpio30_in_req[PORT_MUX_GROUP_PAD_IO30_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_GPIO_GPIO30 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio30_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio30_in_req), + .cnt_o(port_mux_sel_gpio_gpio30_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio30_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio30_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio30_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio30_in_arbitrated) + PORT_MUX_GROUP_PAD_IO30_SEL_PAD_IO30: begin + port_signals_pad2soc_o.gpio.gpio30_in = pads_to_mux_i.pad_io30.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio30_in = 1'b0; + end + endcase + end + end + + + // Port Signal gpio31_in + logic [0:0] port_mux_sel_gpio_gpio31_in_req; + logic [PORT_MUX_GROUP_PAD_IO31_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio31_in_arbitrated; + logic port_mux_sel_gpio_gpio31_in_no_connection; + + assign port_mux_sel_gpio_gpio31_in_req[PORT_MUX_GROUP_PAD_IO31_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_GPIO_GPIO31 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio31_in_arbiter ( + .in_i(port_mux_sel_gpio_gpio31_in_req), + .cnt_o(port_mux_sel_gpio_gpio31_in_arbitrated), + .empty_o(port_mux_sel_gpio_gpio31_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio31_in_no_connection) begin + port_signals_pad2soc_o.gpio.gpio31_in = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio31_in_arbitrated) + PORT_MUX_GROUP_PAD_IO31_SEL_PAD_IO31: begin + port_signals_pad2soc_o.gpio.gpio31_in = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio31_in = 1'b0; + end + endcase + end + end + + // Port Group i2c0 + + // Port Signal sda_i + logic [31:0] port_mux_sel_i2c0_sda_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_i2c0_sda_i_arbitrated; + logic port_mux_sel_i2c0_sda_i_no_connection; + + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2C0_SDA ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_sda_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2C0_SDA ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_i2c0_sda_i_arbiter ( + .in_i(port_mux_sel_i2c0_sda_i_req), + .cnt_o(port_mux_sel_i2c0_sda_i_arbitrated), + .empty_o(port_mux_sel_i2c0_sda_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_i2c0_sda_i_no_connection) begin + port_signals_pad2soc_o.i2c0.sda_i = 1'b1; + end else begin + unique case (port_mux_sel_i2c0_sda_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.i2c0.sda_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.i2c0.sda_i = 1'b1; + end + endcase + end + end + + + // Port Signal scl_i + logic [31:0] port_mux_sel_i2c0_scl_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_i2c0_scl_i_arbitrated; + logic port_mux_sel_i2c0_scl_i_no_connection; + + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2C0_SCL ? 1'b1 : 1'b0; + assign port_mux_sel_i2c0_scl_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2C0_SCL ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_i2c0_scl_i_arbiter ( + .in_i(port_mux_sel_i2c0_scl_i_req), + .cnt_o(port_mux_sel_i2c0_scl_i_arbitrated), + .empty_o(port_mux_sel_i2c0_scl_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_i2c0_scl_i_no_connection) begin + port_signals_pad2soc_o.i2c0.scl_i = 1'b1; + end else begin + unique case (port_mux_sel_i2c0_scl_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.i2c0.scl_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.i2c0.scl_i = 1'b1; + end + endcase + end + end + + // Port Group uart0 + + // Port Signal rx_i + logic [31:0] port_mux_sel_uart0_rx_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_uart0_rx_i_arbitrated; + logic port_mux_sel_uart0_rx_i_no_connection; + + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_UART0_RX ? 1'b1 : 1'b0; + assign port_mux_sel_uart0_rx_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_UART0_RX ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_uart0_rx_i_arbiter ( + .in_i(port_mux_sel_uart0_rx_i_req), + .cnt_o(port_mux_sel_uart0_rx_i_arbitrated), + .empty_o(port_mux_sel_uart0_rx_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_uart0_rx_i_no_connection) begin + port_signals_pad2soc_o.uart0.rx_i = 1'b1; + end else begin + unique case (port_mux_sel_uart0_rx_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.uart0.rx_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.uart0.rx_i = 1'b1; + end + endcase + end + end + + + // Port Group qspim0 + + // Port Signal sd0_i + logic [31:0] port_mux_sel_qspim0_sd0_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_qspim0_sd0_i_arbitrated; + logic port_mux_sel_qspim0_sd0_i_no_connection; + + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_SDIO0 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_qspim0_sd0_i_arbiter ( + .in_i(port_mux_sel_qspim0_sd0_i_req), + .cnt_o(port_mux_sel_qspim0_sd0_i_arbitrated), + .empty_o(port_mux_sel_qspim0_sd0_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_qspim0_sd0_i_no_connection) begin + port_signals_pad2soc_o.qspim0.sd0_i = 1'b0; + end else begin + unique case (port_mux_sel_qspim0_sd0_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.qspim0.sd0_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.qspim0.sd0_i = 1'b0; + end + endcase + end + end + + + // Port Signal sd1_i + logic [31:0] port_mux_sel_qspim0_sd1_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_qspim0_sd1_i_arbitrated; + logic port_mux_sel_qspim0_sd1_i_no_connection; + + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_SDIO1 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_qspim0_sd1_i_arbiter ( + .in_i(port_mux_sel_qspim0_sd1_i_req), + .cnt_o(port_mux_sel_qspim0_sd1_i_arbitrated), + .empty_o(port_mux_sel_qspim0_sd1_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_qspim0_sd1_i_no_connection) begin + port_signals_pad2soc_o.qspim0.sd1_i = 1'b0; + end else begin + unique case (port_mux_sel_qspim0_sd1_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.qspim0.sd1_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.qspim0.sd1_i = 1'b0; + end + endcase + end + end + + + // Port Signal sd2_i + logic [31:0] port_mux_sel_qspim0_sd2_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_qspim0_sd2_i_arbitrated; + logic port_mux_sel_qspim0_sd2_i_no_connection; + + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_SDIO2 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_qspim0_sd2_i_arbiter ( + .in_i(port_mux_sel_qspim0_sd2_i_req), + .cnt_o(port_mux_sel_qspim0_sd2_i_arbitrated), + .empty_o(port_mux_sel_qspim0_sd2_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_qspim0_sd2_i_no_connection) begin + port_signals_pad2soc_o.qspim0.sd2_i = 1'b0; + end else begin + unique case (port_mux_sel_qspim0_sd2_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.qspim0.sd2_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.qspim0.sd2_i = 1'b0; + end + endcase + end + end + + + // Port Signal sd3_i + logic [31:0] port_mux_sel_qspim0_sd3_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_qspim0_sd3_i_arbitrated; + logic port_mux_sel_qspim0_sd3_i_no_connection; + + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + assign port_mux_sel_qspim0_sd3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_QSPIM0_SDIO3 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_qspim0_sd3_i_arbiter ( + .in_i(port_mux_sel_qspim0_sd3_i_req), + .cnt_o(port_mux_sel_qspim0_sd3_i_arbitrated), + .empty_o(port_mux_sel_qspim0_sd3_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_qspim0_sd3_i_no_connection) begin + port_signals_pad2soc_o.qspim0.sd3_i = 1'b0; + end else begin + unique case (port_mux_sel_qspim0_sd3_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.qspim0.sd3_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.qspim0.sd3_i = 1'b0; + end + endcase + end + end + + + + + + + // Port Group cpi0 + + // Port Signal pclk_i + logic [31:0] port_mux_sel_cpi0_pclk_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_cpi0_pclk_i_arbitrated; + logic port_mux_sel_cpi0_pclk_i_no_connection; + + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_pclk_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_PCLK ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_cpi0_pclk_i_arbiter ( + .in_i(port_mux_sel_cpi0_pclk_i_req), + .cnt_o(port_mux_sel_cpi0_pclk_i_arbitrated), + .empty_o(port_mux_sel_cpi0_pclk_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_cpi0_pclk_i_no_connection) begin + port_signals_pad2soc_o.cpi0.pclk_i = 1'b0; + end else begin + unique case (port_mux_sel_cpi0_pclk_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.cpi0.pclk_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.cpi0.pclk_i = 1'b0; + end + endcase + end + end + + + // Port Signal hsync_i + logic [31:0] port_mux_sel_cpi0_hsync_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_cpi0_hsync_i_arbitrated; + logic port_mux_sel_cpi0_hsync_i_no_connection; + + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_hsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_HSYNC ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_cpi0_hsync_i_arbiter ( + .in_i(port_mux_sel_cpi0_hsync_i_req), + .cnt_o(port_mux_sel_cpi0_hsync_i_arbitrated), + .empty_o(port_mux_sel_cpi0_hsync_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_cpi0_hsync_i_no_connection) begin + port_signals_pad2soc_o.cpi0.hsync_i = 1'b0; + end else begin + unique case (port_mux_sel_cpi0_hsync_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.cpi0.hsync_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.cpi0.hsync_i = 1'b0; + end + endcase + end + end + + + // Port Signal vsync_i + logic [31:0] port_mux_sel_cpi0_vsync_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_cpi0_vsync_i_arbitrated; + logic port_mux_sel_cpi0_vsync_i_no_connection; + + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_vsync_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_VSYNC ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_cpi0_vsync_i_arbiter ( + .in_i(port_mux_sel_cpi0_vsync_i_req), + .cnt_o(port_mux_sel_cpi0_vsync_i_arbitrated), + .empty_o(port_mux_sel_cpi0_vsync_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_cpi0_vsync_i_no_connection) begin + port_signals_pad2soc_o.cpi0.vsync_i = 1'b0; + end else begin + unique case (port_mux_sel_cpi0_vsync_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.cpi0.vsync_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.cpi0.vsync_i = 1'b0; + end + endcase + end + end + + + // Port Signal data0_i + logic [31:0] port_mux_sel_cpi0_data0_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_cpi0_data0_i_arbitrated; + logic port_mux_sel_cpi0_data0_i_no_connection; + + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data0_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA0 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_cpi0_data0_i_arbiter ( + .in_i(port_mux_sel_cpi0_data0_i_req), + .cnt_o(port_mux_sel_cpi0_data0_i_arbitrated), + .empty_o(port_mux_sel_cpi0_data0_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_cpi0_data0_i_no_connection) begin + port_signals_pad2soc_o.cpi0.data0_i = 1'b0; + end else begin + unique case (port_mux_sel_cpi0_data0_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.cpi0.data0_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.cpi0.data0_i = 1'b0; + end + endcase + end + end + + + // Port Signal data1_i + logic [31:0] port_mux_sel_cpi0_data1_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_cpi0_data1_i_arbitrated; + logic port_mux_sel_cpi0_data1_i_no_connection; + + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data1_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA1 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_cpi0_data1_i_arbiter ( + .in_i(port_mux_sel_cpi0_data1_i_req), + .cnt_o(port_mux_sel_cpi0_data1_i_arbitrated), + .empty_o(port_mux_sel_cpi0_data1_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_cpi0_data1_i_no_connection) begin + port_signals_pad2soc_o.cpi0.data1_i = 1'b0; + end else begin + unique case (port_mux_sel_cpi0_data1_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.cpi0.data1_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.cpi0.data1_i = 1'b0; + end + endcase + end + end + + + // Port Signal data2_i + logic [31:0] port_mux_sel_cpi0_data2_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_cpi0_data2_i_arbitrated; + logic port_mux_sel_cpi0_data2_i_no_connection; + + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data2_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA2 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_cpi0_data2_i_arbiter ( + .in_i(port_mux_sel_cpi0_data2_i_req), + .cnt_o(port_mux_sel_cpi0_data2_i_arbitrated), + .empty_o(port_mux_sel_cpi0_data2_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_cpi0_data2_i_no_connection) begin + port_signals_pad2soc_o.cpi0.data2_i = 1'b0; + end else begin + unique case (port_mux_sel_cpi0_data2_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.cpi0.data2_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.cpi0.data2_i = 1'b0; + end + endcase + end + end + + + // Port Signal data3_i + logic [31:0] port_mux_sel_cpi0_data3_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_cpi0_data3_i_arbitrated; + logic port_mux_sel_cpi0_data3_i_no_connection; + + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data3_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA3 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_cpi0_data3_i_arbiter ( + .in_i(port_mux_sel_cpi0_data3_i_req), + .cnt_o(port_mux_sel_cpi0_data3_i_arbitrated), + .empty_o(port_mux_sel_cpi0_data3_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_cpi0_data3_i_no_connection) begin + port_signals_pad2soc_o.cpi0.data3_i = 1'b0; + end else begin + unique case (port_mux_sel_cpi0_data3_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.cpi0.data3_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.cpi0.data3_i = 1'b0; + end + endcase + end + end + + + // Port Signal data4_i + logic [31:0] port_mux_sel_cpi0_data4_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_cpi0_data4_i_arbitrated; + logic port_mux_sel_cpi0_data4_i_no_connection; + + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data4_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA4 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_cpi0_data4_i_arbiter ( + .in_i(port_mux_sel_cpi0_data4_i_req), + .cnt_o(port_mux_sel_cpi0_data4_i_arbitrated), + .empty_o(port_mux_sel_cpi0_data4_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_cpi0_data4_i_no_connection) begin + port_signals_pad2soc_o.cpi0.data4_i = 1'b0; + end else begin + unique case (port_mux_sel_cpi0_data4_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.cpi0.data4_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.cpi0.data4_i = 1'b0; + end + endcase + end + end + + + // Port Signal data5_i + logic [31:0] port_mux_sel_cpi0_data5_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_cpi0_data5_i_arbitrated; + logic port_mux_sel_cpi0_data5_i_no_connection; + + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data5_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA5 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_cpi0_data5_i_arbiter ( + .in_i(port_mux_sel_cpi0_data5_i_req), + .cnt_o(port_mux_sel_cpi0_data5_i_arbitrated), + .empty_o(port_mux_sel_cpi0_data5_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_cpi0_data5_i_no_connection) begin + port_signals_pad2soc_o.cpi0.data5_i = 1'b0; + end else begin + unique case (port_mux_sel_cpi0_data5_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.cpi0.data5_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.cpi0.data5_i = 1'b0; + end + endcase + end + end + + + // Port Signal data6_i + logic [31:0] port_mux_sel_cpi0_data6_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_cpi0_data6_i_arbitrated; + logic port_mux_sel_cpi0_data6_i_no_connection; + + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data6_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA6 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_cpi0_data6_i_arbiter ( + .in_i(port_mux_sel_cpi0_data6_i_req), + .cnt_o(port_mux_sel_cpi0_data6_i_arbitrated), + .empty_o(port_mux_sel_cpi0_data6_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_cpi0_data6_i_no_connection) begin + port_signals_pad2soc_o.cpi0.data6_i = 1'b0; + end else begin + unique case (port_mux_sel_cpi0_data6_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.cpi0.data6_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.cpi0.data6_i = 1'b0; + end + endcase + end + end + + + // Port Signal data7_i + logic [31:0] port_mux_sel_cpi0_data7_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_cpi0_data7_i_arbitrated; + logic port_mux_sel_cpi0_data7_i_no_connection; + + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data7_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA7 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_cpi0_data7_i_arbiter ( + .in_i(port_mux_sel_cpi0_data7_i_req), + .cnt_o(port_mux_sel_cpi0_data7_i_arbitrated), + .empty_o(port_mux_sel_cpi0_data7_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_cpi0_data7_i_no_connection) begin + port_signals_pad2soc_o.cpi0.data7_i = 1'b0; + end else begin + unique case (port_mux_sel_cpi0_data7_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.cpi0.data7_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.cpi0.data7_i = 1'b0; + end + endcase + end + end + + + // Port Signal data8_i + logic [31:0] port_mux_sel_cpi0_data8_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_cpi0_data8_i_arbitrated; + logic port_mux_sel_cpi0_data8_i_no_connection; + + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data8_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA8 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_cpi0_data8_i_arbiter ( + .in_i(port_mux_sel_cpi0_data8_i_req), + .cnt_o(port_mux_sel_cpi0_data8_i_arbitrated), + .empty_o(port_mux_sel_cpi0_data8_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_cpi0_data8_i_no_connection) begin + port_signals_pad2soc_o.cpi0.data8_i = 1'b0; + end else begin + unique case (port_mux_sel_cpi0_data8_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.cpi0.data8_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.cpi0.data8_i = 1'b0; + end + endcase + end + end + + + // Port Signal data9_i + logic [31:0] port_mux_sel_cpi0_data9_i_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_cpi0_data9_i_arbitrated; + logic port_mux_sel_cpi0_data9_i_no_connection; + + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + assign port_mux_sel_cpi0_data9_i_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_CPI0_DATA9 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_cpi0_data9_i_arbiter ( + .in_i(port_mux_sel_cpi0_data9_i_req), + .cnt_o(port_mux_sel_cpi0_data9_i_arbitrated), + .empty_o(port_mux_sel_cpi0_data9_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_cpi0_data9_i_no_connection) begin + port_signals_pad2soc_o.cpi0.data9_i = 1'b0; + end else begin + unique case (port_mux_sel_cpi0_data9_i_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.cpi0.data9_i = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.cpi0.data9_i = 1'b0; + end + endcase + end + end + + // Port Group sdio0 + + + // Port Signal sdcmd_in + logic [31:0] port_mux_sel_sdio0_sdcmd_in_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_sdio0_sdcmd_in_arbitrated; + logic port_mux_sel_sdio0_sdcmd_in_no_connection; + + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sdcmd_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDCMD ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_sdio0_sdcmd_in_arbiter ( + .in_i(port_mux_sel_sdio0_sdcmd_in_req), + .cnt_o(port_mux_sel_sdio0_sdcmd_in_arbitrated), + .empty_o(port_mux_sel_sdio0_sdcmd_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_sdio0_sdcmd_in_no_connection) begin + port_signals_pad2soc_o.sdio0.sdcmd_in = 1'b0; + end else begin + unique case (port_mux_sel_sdio0_sdcmd_in_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.sdio0.sdcmd_in = 1'b0; + end + endcase + end + end + + + // Port Signal sddata0_in + logic [31:0] port_mux_sel_sdio0_sddata0_in_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_sdio0_sddata0_in_arbitrated; + logic port_mux_sel_sdio0_sddata0_in_no_connection; + + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDDATA0 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_sdio0_sddata0_in_arbiter ( + .in_i(port_mux_sel_sdio0_sddata0_in_req), + .cnt_o(port_mux_sel_sdio0_sddata0_in_arbitrated), + .empty_o(port_mux_sel_sdio0_sddata0_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_sdio0_sddata0_in_no_connection) begin + port_signals_pad2soc_o.sdio0.sddata0_in = 1'b0; + end else begin + unique case (port_mux_sel_sdio0_sddata0_in_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.sdio0.sddata0_in = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.sdio0.sddata0_in = 1'b0; + end + endcase + end + end + + + // Port Signal sddata1_in + logic [31:0] port_mux_sel_sdio0_sddata1_in_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_sdio0_sddata1_in_arbitrated; + logic port_mux_sel_sdio0_sddata1_in_no_connection; + + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDDATA1 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_sdio0_sddata1_in_arbiter ( + .in_i(port_mux_sel_sdio0_sddata1_in_req), + .cnt_o(port_mux_sel_sdio0_sddata1_in_arbitrated), + .empty_o(port_mux_sel_sdio0_sddata1_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_sdio0_sddata1_in_no_connection) begin + port_signals_pad2soc_o.sdio0.sddata1_in = 1'b0; + end else begin + unique case (port_mux_sel_sdio0_sddata1_in_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.sdio0.sddata1_in = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.sdio0.sddata1_in = 1'b0; + end + endcase + end + end + + + // Port Signal sddata2_in + logic [31:0] port_mux_sel_sdio0_sddata2_in_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_sdio0_sddata2_in_arbitrated; + logic port_mux_sel_sdio0_sddata2_in_no_connection; + + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata2_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDDATA2 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_sdio0_sddata2_in_arbiter ( + .in_i(port_mux_sel_sdio0_sddata2_in_req), + .cnt_o(port_mux_sel_sdio0_sddata2_in_arbitrated), + .empty_o(port_mux_sel_sdio0_sddata2_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_sdio0_sddata2_in_no_connection) begin + port_signals_pad2soc_o.sdio0.sddata2_in = 1'b0; + end else begin + unique case (port_mux_sel_sdio0_sddata2_in_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.sdio0.sddata2_in = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.sdio0.sddata2_in = 1'b0; + end + endcase + end + end + + + // Port Signal sddata3_in + logic [31:0] port_mux_sel_sdio0_sddata3_in_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_sdio0_sddata3_in_arbitrated; + logic port_mux_sel_sdio0_sddata3_in_no_connection; + + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + assign port_mux_sel_sdio0_sddata3_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_SDIO0_SDDATA3 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_sdio0_sddata3_in_arbiter ( + .in_i(port_mux_sel_sdio0_sddata3_in_req), + .cnt_o(port_mux_sel_sdio0_sddata3_in_arbitrated), + .empty_o(port_mux_sel_sdio0_sddata3_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_sdio0_sddata3_in_no_connection) begin + port_signals_pad2soc_o.sdio0.sddata3_in = 1'b0; + end else begin + unique case (port_mux_sel_sdio0_sddata3_in_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.sdio0.sddata3_in = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.sdio0.sddata3_in = 1'b0; + end + endcase + end + end + + // Port Group i2s0 + + // Port Signal master_sck_in + logic [31:0] port_mux_sel_i2s0_master_sck_in_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_i2s0_master_sck_in_arbitrated; + logic port_mux_sel_i2s0_master_sck_in_no_connection; + + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_MASTER_SCK ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_i2s0_master_sck_in_arbiter ( + .in_i(port_mux_sel_i2s0_master_sck_in_req), + .cnt_o(port_mux_sel_i2s0_master_sck_in_arbitrated), + .empty_o(port_mux_sel_i2s0_master_sck_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_i2s0_master_sck_in_no_connection) begin + port_signals_pad2soc_o.i2s0.master_sck_in = 1'b0; + end else begin + unique case (port_mux_sel_i2s0_master_sck_in_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.i2s0.master_sck_in = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.i2s0.master_sck_in = 1'b0; + end + endcase + end + end + + + // Port Signal master_ws_in + logic [31:0] port_mux_sel_i2s0_master_ws_in_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_i2s0_master_ws_in_arbitrated; + logic port_mux_sel_i2s0_master_ws_in_no_connection; + + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_master_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_MASTER_WS ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_i2s0_master_ws_in_arbiter ( + .in_i(port_mux_sel_i2s0_master_ws_in_req), + .cnt_o(port_mux_sel_i2s0_master_ws_in_arbitrated), + .empty_o(port_mux_sel_i2s0_master_ws_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_i2s0_master_ws_in_no_connection) begin + port_signals_pad2soc_o.i2s0.master_ws_in = 1'b0; + end else begin + unique case (port_mux_sel_i2s0_master_ws_in_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.i2s0.master_ws_in = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.i2s0.master_ws_in = 1'b0; + end + endcase + end + end + + + + + // Port Signal slave_sck_in + logic [31:0] port_mux_sel_i2s0_slave_sck_in_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_i2s0_slave_sck_in_arbitrated; + logic port_mux_sel_i2s0_slave_sck_in_no_connection; + + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sck_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_SLAVE_SCK ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_i2s0_slave_sck_in_arbiter ( + .in_i(port_mux_sel_i2s0_slave_sck_in_req), + .cnt_o(port_mux_sel_i2s0_slave_sck_in_arbitrated), + .empty_o(port_mux_sel_i2s0_slave_sck_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_i2s0_slave_sck_in_no_connection) begin + port_signals_pad2soc_o.i2s0.slave_sck_in = 1'b0; + end else begin + unique case (port_mux_sel_i2s0_slave_sck_in_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.i2s0.slave_sck_in = 1'b0; + end + endcase + end + end + + + // Port Signal slave_ws_in + logic [31:0] port_mux_sel_i2s0_slave_ws_in_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_i2s0_slave_ws_in_arbitrated; + logic port_mux_sel_i2s0_slave_ws_in_no_connection; + + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_ws_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_SLAVE_WS ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_i2s0_slave_ws_in_arbiter ( + .in_i(port_mux_sel_i2s0_slave_ws_in_req), + .cnt_o(port_mux_sel_i2s0_slave_ws_in_arbitrated), + .empty_o(port_mux_sel_i2s0_slave_ws_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_i2s0_slave_ws_in_no_connection) begin + port_signals_pad2soc_o.i2s0.slave_ws_in = 1'b0; + end else begin + unique case (port_mux_sel_i2s0_slave_ws_in_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.i2s0.slave_ws_in = 1'b0; + end + endcase + end + end + + + // Port Signal slave_sd0_in + logic [31:0] port_mux_sel_i2s0_slave_sd0_in_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_i2s0_slave_sd0_in_arbitrated; + logic port_mux_sel_i2s0_slave_sd0_in_no_connection; + + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd0_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_SLAVE_SD0 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_i2s0_slave_sd0_in_arbiter ( + .in_i(port_mux_sel_i2s0_slave_sd0_in_req), + .cnt_o(port_mux_sel_i2s0_slave_sd0_in_arbitrated), + .empty_o(port_mux_sel_i2s0_slave_sd0_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_i2s0_slave_sd0_in_no_connection) begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = 1'b0; + end else begin + unique case (port_mux_sel_i2s0_slave_sd0_in_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.i2s0.slave_sd0_in = 1'b0; + end + endcase + end + end + + + // Port Signal slave_sd1_in + logic [31:0] port_mux_sel_i2s0_slave_sd1_in_req; + logic [PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_WIDTH-1:0] port_mux_sel_i2s0_slave_sd1_in_arbitrated; + logic port_mux_sel_i2s0_slave_sd1_in_no_connection; + + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00] = s_reg2hw.pad_io00_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO00_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01] = s_reg2hw.pad_io01_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO01_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02] = s_reg2hw.pad_io02_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO02_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03] = s_reg2hw.pad_io03_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO03_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04] = s_reg2hw.pad_io04_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO04_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05] = s_reg2hw.pad_io05_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO05_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06] = s_reg2hw.pad_io06_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO06_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07] = s_reg2hw.pad_io07_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO07_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08] = s_reg2hw.pad_io08_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO08_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09] = s_reg2hw.pad_io09_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO09_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10] = s_reg2hw.pad_io10_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO10_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11] = s_reg2hw.pad_io11_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO11_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12] = s_reg2hw.pad_io12_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO12_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13] = s_reg2hw.pad_io13_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO13_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14] = s_reg2hw.pad_io14_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO14_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15] = s_reg2hw.pad_io15_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO15_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16] = s_reg2hw.pad_io16_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO16_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17] = s_reg2hw.pad_io17_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO17_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18] = s_reg2hw.pad_io18_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO18_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19] = s_reg2hw.pad_io19_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO19_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20] = s_reg2hw.pad_io20_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO20_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21] = s_reg2hw.pad_io21_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO21_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22] = s_reg2hw.pad_io22_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO22_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23] = s_reg2hw.pad_io23_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO23_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24] = s_reg2hw.pad_io24_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO24_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25] = s_reg2hw.pad_io25_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO25_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26] = s_reg2hw.pad_io26_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO26_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27] = s_reg2hw.pad_io27_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO27_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28] = s_reg2hw.pad_io28_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO28_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29] = s_reg2hw.pad_io29_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO29_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30] = s_reg2hw.pad_io30_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO30_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + assign port_mux_sel_i2s0_slave_sd1_in_req[PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31] = s_reg2hw.pad_io31_mux_sel.q == PAD_MUX_GROUP_ALL_MUXED_IOS_PAD_IO31_SEL_I2S0_SLAVE_SD1 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(32), + .MODE(1'b0) + ) i_port_muxsel_i2s0_slave_sd1_in_arbiter ( + .in_i(port_mux_sel_i2s0_slave_sd1_in_req), + .cnt_o(port_mux_sel_i2s0_slave_sd1_in_arbitrated), + .empty_o(port_mux_sel_i2s0_slave_sd1_in_no_connection) + ); + + always_comb begin + if (port_mux_sel_i2s0_slave_sd1_in_no_connection) begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = 1'b0; + end else begin + unique case (port_mux_sel_i2s0_slave_sd1_in_arbitrated) + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO00: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io00.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO01: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io01.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO02: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io02.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO03: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io03.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO04: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io04.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO05: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io05.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO06: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io06.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO07: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io07.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO08: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io08.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO09: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io09.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO10: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io10.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO11: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io11.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO12: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io12.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO13: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io13.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO14: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io14.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO15: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io15.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO16: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io16.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO17: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io17.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO18: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io18.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO19: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io19.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO20: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io20.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO21: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io21.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO22: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io22.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO23: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io23.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO24: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io24.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO25: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io25.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO26: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io26.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO27: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io27.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO28: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io28.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO29: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io29.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO30: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io30.pad2chip; + end + PORT_MUX_GROUP_ALL_MUXED_IOS_SEL_PAD_IO31: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = pads_to_mux_i.pad_io31.pad2chip; + end + default: begin + port_signals_pad2soc_o.i2s0.slave_sd1_in = 1'b0; + end + endcase + end + end + +endmodule : pulpissimo_padframe_all_pads_muxer diff --git a/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/src/pulpissimo_padframe_all_pads_pads.sv b/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/src/pulpissimo_padframe_all_pads_pads.sv new file mode 100644 index 00000000..e10d7e81 --- /dev/null +++ b/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/src/pulpissimo_padframe_all_pads_pads.sv @@ -0,0 +1,465 @@ + +// File auto-generated by Padrick unknown +module pulpissimo_padframe_all_pads_pads + import pkg_pulpissimo_padframe::*; + import pkg_internal_pulpissimo_padframe_all_pads::*; +( + output pad_domain_all_pads_static_connection_signals_pad2soc_t static_connection_signals_pad2soc, + input pad_domain_all_pads_static_connection_signals_soc2pad_t static_connection_signals_soc2pad, + // Dynamic Pad control signals, these signals are controlled by the multiplexer in the correpsongin pad_controller module + input mux_to_pads_t mux_to_pads_i, + output pads_to_mux_t pads_to_mux_o, + // Landing Pads + inout wire logic pad_pad_ref_clk_pad, + inout wire logic pad_pad_clk_byp_en_pad, + inout wire logic pad_pad_reset_n_pad, + inout wire logic pad_pad_bootsel0_pad, + inout wire logic pad_pad_bootsel1_pad, + inout wire logic pad_pad_jtag_tck_pad, + inout wire logic pad_pad_jtag_trstn_pad, + inout wire logic pad_pad_jtag_tms_pad, + inout wire logic pad_pad_jtag_tdi_pad, + inout wire logic pad_pad_jtag_tdo_pad, + inout wire logic pad_pad_hyper_csn0_pad, + inout wire logic pad_pad_hyper_csn1_pad, + inout wire logic pad_pad_hyper_reset_n_pad, + inout wire logic pad_pad_hyper_ck_pad, + inout wire logic pad_pad_hyper_ckn_pad, + inout wire logic pad_pad_hyper_dq0_pad, + inout wire logic pad_pad_hyper_dq1_pad, + inout wire logic pad_pad_hyper_dq2_pad, + inout wire logic pad_pad_hyper_dq3_pad, + inout wire logic pad_pad_hyper_dq4_pad, + inout wire logic pad_pad_hyper_dq5_pad, + inout wire logic pad_pad_hyper_dq6_pad, + inout wire logic pad_pad_hyper_dq7_pad, + inout wire logic pad_pad_hyper_rwds_pad, + inout wire logic pad_pad_io00_pad, + inout wire logic pad_pad_io01_pad, + inout wire logic pad_pad_io02_pad, + inout wire logic pad_pad_io03_pad, + inout wire logic pad_pad_io04_pad, + inout wire logic pad_pad_io05_pad, + inout wire logic pad_pad_io06_pad, + inout wire logic pad_pad_io07_pad, + inout wire logic pad_pad_io08_pad, + inout wire logic pad_pad_io09_pad, + inout wire logic pad_pad_io10_pad, + inout wire logic pad_pad_io11_pad, + inout wire logic pad_pad_io12_pad, + inout wire logic pad_pad_io13_pad, + inout wire logic pad_pad_io14_pad, + inout wire logic pad_pad_io15_pad, + inout wire logic pad_pad_io16_pad, + inout wire logic pad_pad_io17_pad, + inout wire logic pad_pad_io18_pad, + inout wire logic pad_pad_io19_pad, + inout wire logic pad_pad_io20_pad, + inout wire logic pad_pad_io21_pad, + inout wire logic pad_pad_io22_pad, + inout wire logic pad_pad_io23_pad, + inout wire logic pad_pad_io24_pad, + inout wire logic pad_pad_io25_pad, + inout wire logic pad_pad_io26_pad, + inout wire logic pad_pad_io27_pad, + inout wire logic pad_pad_io28_pad, + inout wire logic pad_pad_io29_pad, + inout wire logic pad_pad_io30_pad, + inout wire logic pad_pad_io31_pad + ); + + // Pad instantiations + pad_functional_pu i_pad_ref_clk ( + .PAD(pad_pad_ref_clk_pad), + .OEN(~1'b0), + .PEN(~1'b0), + .I(1'b0), + .O(static_connection_signals_pad2soc.ref_clk) + ); + pad_functional_pu i_pad_clk_byp_en ( + .PAD(pad_pad_clk_byp_en_pad), + .OEN(~1'b0), + .PEN(~1'b0), + .I(1'b0), + .O(static_connection_signals_pad2soc.clk_byp_en) + ); + pad_functional_pu i_pad_reset_n ( + .PAD(pad_pad_reset_n_pad), + .OEN(~1'b0), + .PEN(~1'b0), + .I(1'b0), + .O(static_connection_signals_pad2soc.rst_n) + ); + pad_functional_pu i_pad_bootsel0 ( + .PAD(pad_pad_bootsel0_pad), + .OEN(~1'b0), + .PEN(~1'b0), + .I(1'b0), + .O(static_connection_signals_pad2soc.bootsel0) + ); + pad_functional_pu i_pad_bootsel1 ( + .PAD(pad_pad_bootsel1_pad), + .OEN(~1'b0), + .PEN(~1'b0), + .I(1'b0), + .O(static_connection_signals_pad2soc.bootsel1) + ); + pad_functional_pu i_pad_jtag_tck ( + .PAD(pad_pad_jtag_tck_pad), + .OEN(~1'b0), + .PEN(~1'b0), + .I(1'b0), + .O(static_connection_signals_pad2soc.jtag_tck) + ); + pad_functional_pu i_pad_jtag_trstn ( + .PAD(pad_pad_jtag_trstn_pad), + .OEN(~1'b0), + .PEN(~1'b0), + .I(1'b0), + .O(static_connection_signals_pad2soc.jtag_trstn) + ); + pad_functional_pu i_pad_jtag_tms ( + .PAD(pad_pad_jtag_tms_pad), + .OEN(~1'b0), + .PEN(~1'b0), + .I(1'b0), + .O(static_connection_signals_pad2soc.jtag_tms) + ); + pad_functional_pu i_pad_jtag_tdi ( + .PAD(pad_pad_jtag_tdi_pad), + .OEN(~1'b0), + .PEN(~1'b0), + .I(1'b0), + .O(static_connection_signals_pad2soc.jtag_tdi) + ); + pad_functional_pu i_pad_jtag_tdo ( + .PAD(pad_pad_jtag_tdo_pad), + .OEN(~1'b1), + .PEN(~1'b0), + .I(static_connection_signals_soc2pad.jtag_tdo), + .O() + ); + pad_functional_pu i_pad_hyper_csn0 ( + .PAD(pad_pad_hyper_csn0_pad), + .OEN(~1'b1), + .PEN(~1'b0), + .I(static_connection_signals_soc2pad.hyper_cs0_no), + .O() + ); + pad_functional_pu i_pad_hyper_csn1 ( + .PAD(pad_pad_hyper_csn1_pad), + .OEN(~1'b1), + .PEN(~1'b0), + .I(static_connection_signals_soc2pad.hyper_cs1_no), + .O() + ); + pad_functional_pu i_pad_hyper_reset_n ( + .PAD(pad_pad_hyper_reset_n_pad), + .OEN(~1'b1), + .PEN(~1'b0), + .I(static_connection_signals_soc2pad.hyper_reset_no), + .O() + ); + pad_functional_pu i_pad_hyper_ck ( + .PAD(pad_pad_hyper_ck_pad), + .OEN(~1'b1), + .PEN(~1'b0), + .I(static_connection_signals_soc2pad.hyper_ck), + .O() + ); + pad_functional_pu i_pad_hyper_ckn ( + .PAD(pad_pad_hyper_ckn_pad), + .OEN(~1'b1), + .PEN(~1'b0), + .I(static_connection_signals_soc2pad.hyper_ckn), + .O() + ); + pad_functional_pu i_pad_hyper_dq0 ( + .PAD(pad_pad_hyper_dq0_pad), + .OEN(~static_connection_signals_soc2pad.hyper_dq_oe), + .PEN(~1'b0), + .I(static_connection_signals_soc2pad.hyper_dq0_o), + .O(static_connection_signals_pad2soc.hyper_dq0_i) + ); + pad_functional_pu i_pad_hyper_dq1 ( + .PAD(pad_pad_hyper_dq1_pad), + .OEN(~static_connection_signals_soc2pad.hyper_dq_oe), + .PEN(~1'b0), + .I(static_connection_signals_soc2pad.hyper_dq1_o), + .O(static_connection_signals_pad2soc.hyper_dq1_i) + ); + pad_functional_pu i_pad_hyper_dq2 ( + .PAD(pad_pad_hyper_dq2_pad), + .OEN(~static_connection_signals_soc2pad.hyper_dq_oe), + .PEN(~1'b0), + .I(static_connection_signals_soc2pad.hyper_dq2_o), + .O(static_connection_signals_pad2soc.hyper_dq2_i) + ); + pad_functional_pu i_pad_hyper_dq3 ( + .PAD(pad_pad_hyper_dq3_pad), + .OEN(~static_connection_signals_soc2pad.hyper_dq_oe), + .PEN(~1'b0), + .I(static_connection_signals_soc2pad.hyper_dq3_o), + .O(static_connection_signals_pad2soc.hyper_dq3_i) + ); + pad_functional_pu i_pad_hyper_dq4 ( + .PAD(pad_pad_hyper_dq4_pad), + .OEN(~static_connection_signals_soc2pad.hyper_dq_oe), + .PEN(~1'b0), + .I(static_connection_signals_soc2pad.hyper_dq4_o), + .O(static_connection_signals_pad2soc.hyper_dq4_i) + ); + pad_functional_pu i_pad_hyper_dq5 ( + .PAD(pad_pad_hyper_dq5_pad), + .OEN(~static_connection_signals_soc2pad.hyper_dq_oe), + .PEN(~1'b0), + .I(static_connection_signals_soc2pad.hyper_dq5_o), + .O(static_connection_signals_pad2soc.hyper_dq5_i) + ); + pad_functional_pu i_pad_hyper_dq6 ( + .PAD(pad_pad_hyper_dq6_pad), + .OEN(~static_connection_signals_soc2pad.hyper_dq_oe), + .PEN(~1'b0), + .I(static_connection_signals_soc2pad.hyper_dq6_o), + .O(static_connection_signals_pad2soc.hyper_dq6_i) + ); + pad_functional_pu i_pad_hyper_dq7 ( + .PAD(pad_pad_hyper_dq7_pad), + .OEN(~static_connection_signals_soc2pad.hyper_dq_oe), + .PEN(~1'b0), + .I(static_connection_signals_soc2pad.hyper_dq7_o), + .O(static_connection_signals_pad2soc.hyper_dq7_i) + ); + pad_functional_pu i_pad_hyper_rwds ( + .PAD(pad_pad_hyper_rwds_pad), + .OEN(~static_connection_signals_soc2pad.hyper_rwds_oe), + .PEN(~1'b0), + .I(static_connection_signals_soc2pad.hyper_rwds_o), + .O(static_connection_signals_pad2soc.hyper_rwds_i) + ); + pad_functional_pu i_pad_io00 ( + .PAD(pad_pad_io00_pad), + .OEN(~mux_to_pads_i.pad_io00.tx_en), + .PEN(~mux_to_pads_i.pad_io00.pull_en), + .I(mux_to_pads_i.pad_io00.chip2pad), + .O(pads_to_mux_o.pad_io00.pad2chip) + ); + pad_functional_pu i_pad_io01 ( + .PAD(pad_pad_io01_pad), + .OEN(~mux_to_pads_i.pad_io01.tx_en), + .PEN(~mux_to_pads_i.pad_io01.pull_en), + .I(mux_to_pads_i.pad_io01.chip2pad), + .O(pads_to_mux_o.pad_io01.pad2chip) + ); + pad_functional_pu i_pad_io02 ( + .PAD(pad_pad_io02_pad), + .OEN(~mux_to_pads_i.pad_io02.tx_en), + .PEN(~mux_to_pads_i.pad_io02.pull_en), + .I(mux_to_pads_i.pad_io02.chip2pad), + .O(pads_to_mux_o.pad_io02.pad2chip) + ); + pad_functional_pu i_pad_io03 ( + .PAD(pad_pad_io03_pad), + .OEN(~mux_to_pads_i.pad_io03.tx_en), + .PEN(~mux_to_pads_i.pad_io03.pull_en), + .I(mux_to_pads_i.pad_io03.chip2pad), + .O(pads_to_mux_o.pad_io03.pad2chip) + ); + pad_functional_pu i_pad_io04 ( + .PAD(pad_pad_io04_pad), + .OEN(~mux_to_pads_i.pad_io04.tx_en), + .PEN(~mux_to_pads_i.pad_io04.pull_en), + .I(mux_to_pads_i.pad_io04.chip2pad), + .O(pads_to_mux_o.pad_io04.pad2chip) + ); + pad_functional_pu i_pad_io05 ( + .PAD(pad_pad_io05_pad), + .OEN(~mux_to_pads_i.pad_io05.tx_en), + .PEN(~mux_to_pads_i.pad_io05.pull_en), + .I(mux_to_pads_i.pad_io05.chip2pad), + .O(pads_to_mux_o.pad_io05.pad2chip) + ); + pad_functional_pu i_pad_io06 ( + .PAD(pad_pad_io06_pad), + .OEN(~mux_to_pads_i.pad_io06.tx_en), + .PEN(~mux_to_pads_i.pad_io06.pull_en), + .I(mux_to_pads_i.pad_io06.chip2pad), + .O(pads_to_mux_o.pad_io06.pad2chip) + ); + pad_functional_pu i_pad_io07 ( + .PAD(pad_pad_io07_pad), + .OEN(~mux_to_pads_i.pad_io07.tx_en), + .PEN(~mux_to_pads_i.pad_io07.pull_en), + .I(mux_to_pads_i.pad_io07.chip2pad), + .O(pads_to_mux_o.pad_io07.pad2chip) + ); + pad_functional_pu i_pad_io08 ( + .PAD(pad_pad_io08_pad), + .OEN(~mux_to_pads_i.pad_io08.tx_en), + .PEN(~mux_to_pads_i.pad_io08.pull_en), + .I(mux_to_pads_i.pad_io08.chip2pad), + .O(pads_to_mux_o.pad_io08.pad2chip) + ); + pad_functional_pu i_pad_io09 ( + .PAD(pad_pad_io09_pad), + .OEN(~mux_to_pads_i.pad_io09.tx_en), + .PEN(~mux_to_pads_i.pad_io09.pull_en), + .I(mux_to_pads_i.pad_io09.chip2pad), + .O(pads_to_mux_o.pad_io09.pad2chip) + ); + pad_functional_pu i_pad_io10 ( + .PAD(pad_pad_io10_pad), + .OEN(~mux_to_pads_i.pad_io10.tx_en), + .PEN(~mux_to_pads_i.pad_io10.pull_en), + .I(mux_to_pads_i.pad_io10.chip2pad), + .O(pads_to_mux_o.pad_io10.pad2chip) + ); + pad_functional_pu i_pad_io11 ( + .PAD(pad_pad_io11_pad), + .OEN(~mux_to_pads_i.pad_io11.tx_en), + .PEN(~mux_to_pads_i.pad_io11.pull_en), + .I(mux_to_pads_i.pad_io11.chip2pad), + .O(pads_to_mux_o.pad_io11.pad2chip) + ); + pad_functional_pu i_pad_io12 ( + .PAD(pad_pad_io12_pad), + .OEN(~mux_to_pads_i.pad_io12.tx_en), + .PEN(~mux_to_pads_i.pad_io12.pull_en), + .I(mux_to_pads_i.pad_io12.chip2pad), + .O(pads_to_mux_o.pad_io12.pad2chip) + ); + pad_functional_pu i_pad_io13 ( + .PAD(pad_pad_io13_pad), + .OEN(~mux_to_pads_i.pad_io13.tx_en), + .PEN(~mux_to_pads_i.pad_io13.pull_en), + .I(mux_to_pads_i.pad_io13.chip2pad), + .O(pads_to_mux_o.pad_io13.pad2chip) + ); + pad_functional_pu i_pad_io14 ( + .PAD(pad_pad_io14_pad), + .OEN(~mux_to_pads_i.pad_io14.tx_en), + .PEN(~mux_to_pads_i.pad_io14.pull_en), + .I(mux_to_pads_i.pad_io14.chip2pad), + .O(pads_to_mux_o.pad_io14.pad2chip) + ); + pad_functional_pu i_pad_io15 ( + .PAD(pad_pad_io15_pad), + .OEN(~mux_to_pads_i.pad_io15.tx_en), + .PEN(~mux_to_pads_i.pad_io15.pull_en), + .I(mux_to_pads_i.pad_io15.chip2pad), + .O(pads_to_mux_o.pad_io15.pad2chip) + ); + pad_functional_pu i_pad_io16 ( + .PAD(pad_pad_io16_pad), + .OEN(~mux_to_pads_i.pad_io16.tx_en), + .PEN(~mux_to_pads_i.pad_io16.pull_en), + .I(mux_to_pads_i.pad_io16.chip2pad), + .O(pads_to_mux_o.pad_io16.pad2chip) + ); + pad_functional_pu i_pad_io17 ( + .PAD(pad_pad_io17_pad), + .OEN(~mux_to_pads_i.pad_io17.tx_en), + .PEN(~mux_to_pads_i.pad_io17.pull_en), + .I(mux_to_pads_i.pad_io17.chip2pad), + .O(pads_to_mux_o.pad_io17.pad2chip) + ); + pad_functional_pu i_pad_io18 ( + .PAD(pad_pad_io18_pad), + .OEN(~mux_to_pads_i.pad_io18.tx_en), + .PEN(~mux_to_pads_i.pad_io18.pull_en), + .I(mux_to_pads_i.pad_io18.chip2pad), + .O(pads_to_mux_o.pad_io18.pad2chip) + ); + pad_functional_pu i_pad_io19 ( + .PAD(pad_pad_io19_pad), + .OEN(~mux_to_pads_i.pad_io19.tx_en), + .PEN(~mux_to_pads_i.pad_io19.pull_en), + .I(mux_to_pads_i.pad_io19.chip2pad), + .O(pads_to_mux_o.pad_io19.pad2chip) + ); + pad_functional_pu i_pad_io20 ( + .PAD(pad_pad_io20_pad), + .OEN(~mux_to_pads_i.pad_io20.tx_en), + .PEN(~mux_to_pads_i.pad_io20.pull_en), + .I(mux_to_pads_i.pad_io20.chip2pad), + .O(pads_to_mux_o.pad_io20.pad2chip) + ); + pad_functional_pu i_pad_io21 ( + .PAD(pad_pad_io21_pad), + .OEN(~mux_to_pads_i.pad_io21.tx_en), + .PEN(~mux_to_pads_i.pad_io21.pull_en), + .I(mux_to_pads_i.pad_io21.chip2pad), + .O(pads_to_mux_o.pad_io21.pad2chip) + ); + pad_functional_pu i_pad_io22 ( + .PAD(pad_pad_io22_pad), + .OEN(~mux_to_pads_i.pad_io22.tx_en), + .PEN(~mux_to_pads_i.pad_io22.pull_en), + .I(mux_to_pads_i.pad_io22.chip2pad), + .O(pads_to_mux_o.pad_io22.pad2chip) + ); + pad_functional_pu i_pad_io23 ( + .PAD(pad_pad_io23_pad), + .OEN(~mux_to_pads_i.pad_io23.tx_en), + .PEN(~mux_to_pads_i.pad_io23.pull_en), + .I(mux_to_pads_i.pad_io23.chip2pad), + .O(pads_to_mux_o.pad_io23.pad2chip) + ); + pad_functional_pu i_pad_io24 ( + .PAD(pad_pad_io24_pad), + .OEN(~mux_to_pads_i.pad_io24.tx_en), + .PEN(~mux_to_pads_i.pad_io24.pull_en), + .I(mux_to_pads_i.pad_io24.chip2pad), + .O(pads_to_mux_o.pad_io24.pad2chip) + ); + pad_functional_pu i_pad_io25 ( + .PAD(pad_pad_io25_pad), + .OEN(~mux_to_pads_i.pad_io25.tx_en), + .PEN(~mux_to_pads_i.pad_io25.pull_en), + .I(mux_to_pads_i.pad_io25.chip2pad), + .O(pads_to_mux_o.pad_io25.pad2chip) + ); + pad_functional_pu i_pad_io26 ( + .PAD(pad_pad_io26_pad), + .OEN(~mux_to_pads_i.pad_io26.tx_en), + .PEN(~mux_to_pads_i.pad_io26.pull_en), + .I(mux_to_pads_i.pad_io26.chip2pad), + .O(pads_to_mux_o.pad_io26.pad2chip) + ); + pad_functional_pu i_pad_io27 ( + .PAD(pad_pad_io27_pad), + .OEN(~mux_to_pads_i.pad_io27.tx_en), + .PEN(~mux_to_pads_i.pad_io27.pull_en), + .I(mux_to_pads_i.pad_io27.chip2pad), + .O(pads_to_mux_o.pad_io27.pad2chip) + ); + pad_functional_pu i_pad_io28 ( + .PAD(pad_pad_io28_pad), + .OEN(~mux_to_pads_i.pad_io28.tx_en), + .PEN(~mux_to_pads_i.pad_io28.pull_en), + .I(mux_to_pads_i.pad_io28.chip2pad), + .O(pads_to_mux_o.pad_io28.pad2chip) + ); + pad_functional_pu i_pad_io29 ( + .PAD(pad_pad_io29_pad), + .OEN(~mux_to_pads_i.pad_io29.tx_en), + .PEN(~mux_to_pads_i.pad_io29.pull_en), + .I(mux_to_pads_i.pad_io29.chip2pad), + .O(pads_to_mux_o.pad_io29.pad2chip) + ); + pad_functional_pu i_pad_io30 ( + .PAD(pad_pad_io30_pad), + .OEN(~mux_to_pads_i.pad_io30.tx_en), + .PEN(~mux_to_pads_i.pad_io30.pull_en), + .I(mux_to_pads_i.pad_io30.chip2pad), + .O(pads_to_mux_o.pad_io30.pad2chip) + ); + pad_functional_pu i_pad_io31 ( + .PAD(pad_pad_io31_pad), + .OEN(~mux_to_pads_i.pad_io31.tx_en), + .PEN(~mux_to_pads_i.pad_io31.pull_en), + .I(mux_to_pads_i.pad_io31.chip2pad), + .O(pads_to_mux_o.pad_io31.pad2chip) + ); + +endmodule : pulpissimo_padframe_all_pads_pads diff --git a/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/src/pulpissimo_padframe_all_pads_regs.hjson b/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/src/pulpissimo_padframe_all_pads_regs.hjson new file mode 100644 index 00000000..634d4356 --- /dev/null +++ b/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/src/pulpissimo_padframe_all_pads_regs.hjson @@ -0,0 +1,4091 @@ + + +{ + # File auto-generated by Padrick unknown + name: "pulpissimo_padframe_all_pads_config" + clock_primary: "clk_i" + reset_primary: "rst_ni" + bus_interfaces: [ + { protocol: "reg_iface", direction: "device"} + ] + regwidth: 32, + registers: [ + {skipto: "0x0"}, + { + name: INFO + desc: "Read-only IP Information register" + swaccess: "ro" + hwaccess: "hro" + fields: [ + { + bits: "15:0" + name: HW_VERSION + desc: "Hardware version ID." + resval: 2 + }, + { + bits:"31:16" + name: PADCOUNT + desc: "The number of muxable pads in this IP." + resval: "32" + } + ] + } + + + + + + + + + + + + + + + + + + + + + + + + + { + name: PAD_IO00_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO00_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io00. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio00", desc: "Connect port gpio00 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO01_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO01_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io01. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio01", desc: "Connect port gpio01 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO02_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO02_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io02. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio02", desc: "Connect port gpio02 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO03_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO03_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io03. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio03", desc: "Connect port gpio03 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO04_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO04_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io04. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio04", desc: "Connect port gpio04 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO05_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO05_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io05. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio05", desc: "Connect port gpio05 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO06_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO06_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io06. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio06", desc: "Connect port gpio06 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO07_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO07_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io07. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio07", desc: "Connect port gpio07 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO08_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO08_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io08. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio08", desc: "Connect port gpio08 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO09_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO09_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io09. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio09", desc: "Connect port gpio09 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO10_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO10_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io10. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio10", desc: "Connect port gpio10 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO11_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO11_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io11. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio11", desc: "Connect port gpio11 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO12_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO12_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io12. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio12", desc: "Connect port gpio12 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO13_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO13_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io13. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio13", desc: "Connect port gpio13 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO14_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO14_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io14. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio14", desc: "Connect port gpio14 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO15_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO15_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io15. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio15", desc: "Connect port gpio15 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO16_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO16_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io16. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio16", desc: "Connect port gpio16 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO17_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO17_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io17. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio17", desc: "Connect port gpio17 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO18_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO18_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io18. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio18", desc: "Connect port gpio18 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO19_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO19_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io19. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio19", desc: "Connect port gpio19 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO20_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO20_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io20. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio20", desc: "Connect port gpio20 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO21_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO21_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io21. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio21", desc: "Connect port gpio21 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO22_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO22_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io22. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio22", desc: "Connect port gpio22 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO23_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO23_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io23. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio23", desc: "Connect port gpio23 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO24_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO24_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io24. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio24", desc: "Connect port gpio24 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO25_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO25_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io25. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio25", desc: "Connect port gpio25 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO26_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO26_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io26. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio26", desc: "Connect port gpio26 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO27_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO27_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io27. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio27", desc: "Connect port gpio27 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO28_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO28_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io28. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio28", desc: "Connect port gpio28 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO29_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO29_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io29. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio29", desc: "Connect port gpio29 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO30_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO30_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io30. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio30", desc: "Connect port gpio30 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO31_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO31_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io31. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio31", desc: "Connect port gpio31 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + ] +} diff --git a/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/src_files.yml b/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/src_files.yml new file mode 100644 index 00000000..6e034ae4 --- /dev/null +++ b/hw/padframe/pulpissimo_padframe_rtl_sim_autogen/src_files.yml @@ -0,0 +1,14 @@ + +# File auto-generated by Padrick 0.3.2.post0.dev5+gfcfdaa2.dirty +pulpissimo_padframe: + files: + - src/pkg_pulpissimo_padframe.sv + - src/pkg_internal_pulpissimo_padframe_all_pads.sv + - src/pulpissimo_padframe_all_pads_config_reg_pkg.sv + - src/pulpissimo_padframe_all_pads_config_reg_top.sv + - src/pulpissimo_padframe_all_pads_pads.sv + - src/pulpissimo_padframe_all_pads_muxer.sv + - src/pulpissimo_padframe_all_pads.sv + - src/pulpissimo_padframe.sv + vlog_opts: + - -L axi_lib \ No newline at end of file diff --git a/hw/padframe/rtl_sim_config/rtl_sim_pad_signals.yml b/hw/padframe/rtl_sim_config/rtl_sim_pad_signals.yml new file mode 100644 index 00000000..fbbb5f9b --- /dev/null +++ b/hw/padframe/rtl_sim_config/rtl_sim_pad_signals.yml @@ -0,0 +1,43 @@ +# Definition of pad signals that are common to all target platforms. +- name: pad + description: "The inout wire of the IO pad that connect to the toplevel port of the SoC" + size: 1 + kind: pad + +- name: chip2pad + description: "Connects to pad's TX driver" + size: 1 + kind: input + conn_type: dynamic + default_reset_value: 0 + default_static_value: 1'b0 + +- name: pad2chip + description: "The signal that connects to the pad's RX buffer" + size: 1 + kind: output + conn_type: dynamic + +- name: rx_en + description: "RX enable, active high" + size: 1 + kind: input + conn_type: dynamic + default_reset_value: 1 + default_static_value: 1'b1 + +- name: tx_en + description: "TX driver enable, active high" + size: 1 + kind: input + conn_type: dynamic + default_reset_value: 0 + default_static_value: 1'b0 + +- name: pull_en + description: "Enable pull up/down (depends on the selected IO pad) resistor, active-high" + size: 1 + kind: input + conn_type: dynamic + default_reset_value: 0 + default_static_value: 1'b0 diff --git a/hw/padframe/rtl_sim_config/rtl_sim_pad_types.yml b/hw/padframe/rtl_sim_config/rtl_sim_pad_types.yml new file mode 100644 index 00000000..9c6c4c05 --- /dev/null +++ b/hw/padframe/rtl_sim_config/rtl_sim_pad_types.yml @@ -0,0 +1,36 @@ +# IO pad templates for the generic padmodels from the tech_cells_generic +# library. These are used in RTL simulation. + +- name: pull_down_pad # user defined name of the pad. Used to reference + # it in the pad_list + description: | + Generic behavioral model of an IO Pad with pull down resistors. The pad is + defined in the tech_cells_generic repository and only used in simulation. + Define your own pad types for a custom tapeout. + template: | + pad_functional_pd ${instance_name} ( + .PAD(${conn["pad"]}), + .OEN(~${conn["tx_en"]}), + .PEN(~${conn["pull_en"]}), + .I(${conn["chip2pad"]}), + .O(${conn["pad2chip"]}) + ); + + pad_signals: !include rtl_sim_config/rtl_sim_pad_signals.yml + +- name: pull_up_pad # user defined name of the pad. Used to reference + # it in the pad_list + description: | + Generic behavioral model of an IO Pad with pull down resistors. The pad is + defined in the tech_cells_generic repository and only used in simulation. + Define your own pad types for a custom tapeout. + template: | + pad_functional_pu ${instance_name} ( + .PAD(${conn["pad"]}), + .OEN(~${conn["tx_en"]}), + .PEN(~${conn["pull_en"]}), + .I(${conn["chip2pad"]}), + .O(${conn["pad2chip"]}) + ); + + pad_signals: !include rtl_sim_config/rtl_sim_pad_signals.yml diff --git a/hw/padframe/rtl_sim_config/rtl_sim_pads.yml b/hw/padframe/rtl_sim_config/rtl_sim_pads.yml new file mode 100644 index 00000000..95c2cdd4 --- /dev/null +++ b/hw/padframe/rtl_sim_config/rtl_sim_pads.yml @@ -0,0 +1,160 @@ +# Specification of how many and what kind of IO pads to instantiate in the padframe +- name: pad_ref_clk + description: "32kHz reference clock for on-chip PLLs" + pad_type: pull_up_pad + is_static: true + connections: + pad2chip: ref_clk + rx_en: 1'b1 + tx_en: 1'b0 + +- name: pad_clk_byp_en + description: "PLL clock bypass enable, active-high. If asserted the PLLs VCO is bypassed and the system uses the ref_clk directly" + pad_type: pull_up_pad + is_static: true + connections: + pad2chip: clk_byp_en + rx_en: 1'b1 + tx_en: 1'b0 + +- name: pad_reset_n + description: "Active-low asynchronous reset. Internally synchronized to rising edge." + pad_type: pull_up_pad + is_static: true + connections: + pad2chip: rst_n + rx_en: 1'b1 + tx_en: 1'b0 + +- name: pad_bootsel0 + description: "Selects boot behavior of the chip. (0b00 -> boot from SPI flash, 0b01 -> JTAG boot, 0b10 -> Hyperflash boot)" + pad_type: pull_up_pad + is_static: true + connections: + pad2chip: bootsel0 + rx_en: 1'b1 + tx_en: 1'b0 + +- name: pad_bootsel1 + description: "Selects boot behavior of the chip. (0b00 -> boot from SPI flash, 0b01 -> JTAG boot, 0b10 -> Hyperflash boot)" + pad_type: pull_up_pad + is_static: true + connections: + pad2chip: bootsel1 + rx_en: 1'b1 + tx_en: 1'b0 + +- name: pad_jtag_tck + description: "JTAG clock input" + pad_type: pull_up_pad + is_static: true + connections: + pad2chip: jtag_tck + rx_en: 1'b1 + tx_en: 1'b0 + +- name: pad_jtag_trstn + description: "JTAG interface reset (active-low)" + pad_type: pull_up_pad + is_static: true + connections: + pad2chip: jtag_trstn + rx_en: 1'b1 + tx_en: 1'b0 + +- name: pad_jtag_tms + description: "JTAG test mode select" + pad_type: pull_up_pad + is_static: true + connections: + pad2chip: jtag_tms + rx_en: 1'b1 + tx_en: 1'b0 + +- name: pad_jtag_tdi + description: "JTAG interface data input" + pad_type: pull_up_pad + is_static: true + connections: + pad2chip: jtag_tdi + rx_en: 1'b1 + tx_en: 1'b0 + +- name: pad_jtag_tdo + description: "JTAG interface data output" + pad_type: pull_up_pad + is_static: true + connections: + chip2pad: jtag_tdo + rx_en: 1'b0 + tx_en: 1'b1 + +- name: pad_hyper_csn{i:1d} + description: "Hyperbus chip select (active-low)" + pad_type: pull_up_pad + multiple: 2 + is_static: true + connections: + chip2pad: hyper_cs{i:1d}_no + rx_en: 1'b0 + tx_en: 1'b1 + +- name: pad_hyper_reset_n + description: "Hyperbus reset (active-low)" + pad_type: pull_up_pad + is_static: true + connections: + chip2pad: hyper_reset_no + rx_en: 1'b0 + tx_en: 1'b1 + +- name: pad_hyper_ck + description: "Hyperbus differential clock" + pad_type: pull_up_pad + is_static: true + connections: + chip2pad: hyper_ck + rx_en: 1'b0 + tx_en: 1'b1 + +- name: pad_hyper_ckn + description: "Hyperbus differential clock" + pad_type: pull_up_pad + is_static: true + connections: + chip2pad: hyper_ckn + rx_en: 1'b0 + tx_en: 1'b1 + +- name: pad_hyper_dq{i} + description: "Hyperbus data line" + multiple: 8 + pad_type: pull_up_pad + is_static: true + connections: + pad2chip: hyper_dq{i}_i + chip2pad: hyper_dq{i}_o + tx_en: hyper_dq_oe + rx_en: ~hyper_dq_oe + +- name: pad_hyper_rwds + description: "Hyperbus read/write data strobe" + pad_type: pull_up_pad + is_static: true + connections: + chip2pad: hyper_rwds_o + pad2chip: hyper_rwds_i + rx_en: ~hyper_rwds_oe + tx_en: hyper_rwds_oe + +- name: pad_io{i:2d} + mux_groups: [all_muxed_ios, self] + description: "General purpose pad that can expose various internal peripherals" + multiple: !include gpio_count.txt + pad_type: pull_up_pad + is_static: false + default_port: gpio.gpio{i:2d} + user_attr: + custom_toplevel_connection: True + + diff --git a/hw/padframe/rtl_sim_padframe_config_top.yml b/hw/padframe/rtl_sim_padframe_config_top.yml new file mode 100644 index 00000000..e7450d8e --- /dev/null +++ b/hw/padframe/rtl_sim_padframe_config_top.yml @@ -0,0 +1,48 @@ +#----------------------------------------------------------------------------- +# Title : Padframe Configuration File +# ----------------------------------------------------------------------------- +# File : padframe_config_generic.yml +# Author : Manuel Eggimann +# Created : 04.12.2022 +# ----------------------------------------------------------------------------- +# Description : +# +# This file descibes the padframe and IO multiplexing strategy of PULPissimo. +# The file is parsed by a CLI tool called padrick that auto-generates the IO +# multiplexing and pad instantation IP automatically. This files is intended to +# be used with the generic IO pad models from the pulp tech_cells_generic +# repository. You can use this file as a template to create a tape-out specific +# config file for your target technology. +# +# You can find more information about the syntax of this file on +# https://padrick.readthedocs.io/en/latest/ +# +#----------------------------------------------------------------------------- +# Copyright (C) 2022 ETH Zurich, University of Bologna Copyright and related +# rights are licensed under the Solderpad Hardware License, Version 0.51 (the +# "License"); you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law or +# agreed to in writing, software, hardware and materials distributed under this +# License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS +# OF ANY KIND, either express or implied. See the License for the specific +# language governing permissions and limitations under the License. +# SPDX-License-Identifier: SHL-0.51 +# ----------------------------------------------------------------------------- + +manifest_version: 3 +name: pulpissimo_padframe +user_attr: + target_platform: rtl_sim + num_gpios: !include gpio_count.txt +pad_domains: + - name: all_pads + pad_types: + !include rtl_sim_config/rtl_sim_pad_types.yml + + pad_list: + !include rtl_sim_config/rtl_sim_pads.yml + + port_groups: + !include common_peripherals.yml + diff --git a/hw/pulpissimo.sv b/hw/pulpissimo.sv new file mode 100644 index 00000000..b09b12ac --- /dev/null +++ b/hw/pulpissimo.sv @@ -0,0 +1,473 @@ +//----------------------------------------------------------------------------- +// Title : PULPissimo Top +// ----------------------------------------------------------------------------- +// File : pulpissimo.sv +// Author : Manuel Eggimann +// Created : 19.04.2022 +// ----------------------------------------------------------------------------- +// Description : +// +// This is the default toplevel of pulpissimo used as the basis for ASIC +// implementations and RTL simulation. It instantiates the following clock +// generation and pad multiplexing IP as well as the `soc_domain` (which wraps +// almost the entire logic of pulpissimo from the external pulp_soc repository). +// The `pulp_soc` repository is shared between the single core variant +// PULPissimo and the multi-core variant pulp-open. +// +//----------------------------------------------------------------------------- +// Copyright (C) 2022 ETH Zurich, University of Bologna Copyright and related +// rights are licensed under the Solderpad Hardware License, Version 0.51 (the +// "License"); you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law or +// agreed to in writing, software, hardware and materials distributed under this +// License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS +// OF ANY KIND, either express or implied. See the License for the specific +// language governing permissions and limitations under the License. +// SPDX-License-Identifier: SHL-0.51 +// ----------------------------------------------------------------------------- + +module pulpissimo #( + /// 0 for CV32E40P with XPULP Extensions, 1 for IBEX RV32IMC (formerly ZERORISCY), + /// 2 for IBEX RV32EC (formerly MICRORISCY) + parameter int unsigned CORE_TYPE = 0, + /// Enable XPULP extensions on CV32E40P. Has no effect if an IBEX core variant is use. + parameter bit USE_XPULP = 1, + /// Mutually exclusive with the use of IBEX. I.e. if an IBEX core variant is used, this parameter + /// is ignored. + parameter bit USE_FPU = 1, + /// Standard RISC-V extension: Reuses the integer regfile for FPU usage instead of requiring a + /// dedicated FPU regfile. Requires correct compiler settings for software to work! + parameter bit USE_ZFINX = 1, + parameter bit USE_HWPE = 0, + /// Enable the virtual stdout interface for communication with simulated testbenches. This + /// parameter must be disabled during any form of physical implementation. + parameter bit SIM_STDOUT = 0, + /// The number of GPIO pads in the system. Check the README on how to modify the pad count + localparam int unsigned IO_PAD_COUNT = gpio_reg_pkg::GPIOCount +)( + // Some platforms (e.g. Verilator) require to feed the clock externally. With + // the EXTERNAL_CLOCK define we remove all internall clock generation logic. +`ifdef EXTERNAL_CLOCK + input logic ext_slow_clk_i, + input logic ext_soc_clk_i, + input logic ext_per_clk_i, +`else + // Reference clock for clock internal clock generation + inout wire pad_ref_clk, +`endif + // Active-low Asynchronous hard-reset + inout wire pad_reset_n, + // Clock Bypass enable. If asserted (active-high) peripheral and soc clock + // domain will be driven directly by pad_refclk_in (or verilator_slow_clk_i if + // in built for VERILATOR). + inout wire pad_clk_byp_en, + // Boot mode selection. Check bootcode repository for mapping of bootsel + // values to actual boot mode. + inout wire pad_bootsel0, + inout wire pad_bootsel1, + // JTAG in-system debug interface + inout wire pad_jtag_tck, + inout wire pad_jtag_tdi, + inout wire pad_jtag_tdo, + inout wire pad_jtag_tms, + inout wire pad_jtag_trstn, + // HyperFlash/HyperRAM Pads + inout wire [1:0] pad_hyper_csn, + inout wire pad_hyper_reset_n, + inout wire pad_hyper_ck, + inout wire pad_hyper_ckn, + inout wire [7:0] pad_hyper_dq, + inout wire pad_hyper_rwds, + // general purpose pads, since PULPissimo v8.0 any peripheral including + // GPIO) can be mapped to any pad any-to-any muxing. Check the latest + // README.md on description and how to modify the pad count) + inout wire [IO_PAD_COUNT-1:0] pad_io +); +`include "soc_mem_map.svh" +`include "apb/assign.svh" +`include "register_interface/typedef.svh" +`include "register_interface/assign.svh" + + //////////////////// + // Wiring Signals // + //////////////////// + // Clock, Bootmode & Reset Signals + logic [1:0] s_bootsel; + logic s_ref_clk; + // Clock bypass control signals + logic s_pad_global_clk_byp_en; // Controlled by dedicated IO Pad + logic s_jtag_global_clk_byp_en; // Controlled by the legacy JTAG Tap in the + // soc_domain + + logic s_global_rst_n; + logic s_soc_clk_en; + logic s_soc_clk_byp_en; + logic s_soc_clk; + logic s_soc_rstn_synced; + logic s_per_clk_en; + logic s_per_clk_byp_en; + logic s_per_clk; + logic s_per_rstn_synced; + logic s_slow_clk_en; + logic s_slow_clk_byp_en; + logic s_slow_clk; + logic s_slow_clk_rstn_synced; + + // DFT Signals + + // These signals remain unsued. We just add them for convenience if someone wants + // to make use of it later on. + logic s_dft_test_en; // Connects to test_en pin of all IPs that expose it. + // This mostly bypasses + assign s_dft_test_en = 1'b0; // This signal connects to all the test_en / + // test_mode_i pins in the system. Many of these + // do not actually do anything and are only ther + // for legacy reason or in order to connect to + // these signals in the DFT setup during + // synthesis. You should check every usage if you + // implement any DFT strategy! + assign s_dft_cg_en = 1'b0; // Same as dft_test_en but connects to all + // dft_cg_en signals. This signal is mostly used + // to force a hierarchical clock gate to enable (active-high) + // the output clock in order to enable scan + // testing. + + // JTAG Signals + logic s_jtag_tck; + logic s_jtag_trst_n; + logic s_jtag_tms; + logic s_jtag_tdi; + logic s_jtag_tdo; + + // Timer Channels + logic [3:0] s_timer_ch0; + logic [3:0] s_timer_ch1; + logic [3:0] s_timer_ch2; + logic [3:0] s_timer_ch3; + + // GPIO + logic [IO_PAD_COUNT-1:0] s_gpio_out; + logic [IO_PAD_COUNT-1:0] s_gpio_tx_en; + logic [IO_PAD_COUNT-1:0] s_gpio_in; + + // UART + uart_pkg::uart_to_pad_t [udma_cfg_pkg::N_UART-1:0] s_uart_to_pad; + uart_pkg::pad_to_uart_t [udma_cfg_pkg::N_UART-1:0] s_pad_to_uart; + // I2C + i2c_pkg::i2c_to_pad_t [udma_cfg_pkg::N_I2C-1:0] s_i2c_to_pad; + i2c_pkg::pad_to_i2c_t [udma_cfg_pkg::N_I2C-1:0] s_pad_to_i2c; + // SDIO + sdio_pkg::sdio_to_pad_t [udma_cfg_pkg::N_SDIO-1:0] s_sdio_to_pad; + sdio_pkg::pad_to_sdio_t [udma_cfg_pkg::N_SDIO-1:0] s_pad_to_sdio; + // I2S + i2s_pkg::i2s_to_pad_t [udma_cfg_pkg::N_I2S-1:0] s_i2s_to_pad; + i2s_pkg::pad_to_i2s_t [udma_cfg_pkg::N_I2S-1:0] s_pad_to_i2s; + // QSPI + qspi_pkg::qspi_to_pad_t [udma_cfg_pkg::N_QSPIM-1:0] s_qspi_to_pad; + qspi_pkg::pad_to_qspi_t [udma_cfg_pkg::N_QSPIM-1:0] s_pad_to_qspi; + // CPI + cpi_pkg::pad_to_cpi_t [udma_cfg_pkg::N_CPI-1:0] s_pad_to_cpi; + // HYPER + hyper_pkg::hyper_to_pad_t [udma_cfg_pkg::N_HYPER-1:0] s_hyper_to_pad; + hyper_pkg::pad_to_hyper_t [udma_cfg_pkg::N_HYPER-1:0] s_pad_to_hyper; + + // Config. Interfaces + APB #(.ADDR_WIDTH(32), .DATA_WIDTH(32)) s_apb_chip_ctrl_bus(); + APB #(.ADDR_WIDTH(6), .DATA_WIDTH(32)) s_apb_fll_ctrl_bus(); + APB #(.ADDR_WIDTH(32), .DATA_WIDTH(32)) s_apb_pads_ctrl_bus(); + + //////////////////////////// + // Chip Control Registers // + //////////////////////////// + // TODO Actually add some register file here to control high level aspects of + // the SoC + assign s_soc_clk_en = 1'b1; + assign s_soc_clk_byp_en =1'b0; + assign s_per_clk_en = 1'b1; + assign s_per_clk_byp_en =1'b0; + assign s_slow_clk_en = 1'b1; + assign s_slow_clk_byp_en =1'b0; + + ////////////////////////////// + // Clock & Reset Generation // + ////////////////////////////// +`ifndef EXTERNAL_CLOCK + clock_gen #( + .APB_ADDR_WIDTH(6) + ) i_clock_gen( + .ref_clk_i ( s_ref_clk ), + .rst_ni ( s_global_rst_n ), + .dft_test_en_i ( s_dft_test_en ), + .cfg_clk_i ( s_soc_clk ), // Interface is synchronous to SoC clock + .cfg_bus_slave ( s_apb_fll_ctrl_bus ), + .slow_clk_en_i ( s_slow_clk_en ), + .slow_clk_byp_en_i ( s_slow_clk_byp_en | s_pad_global_clk_byp_en | s_jtag_global_clk_byp_en ), + .slow_clk_o ( s_slow_clk ), + .soc_clk_en_i ( s_soc_clk_en ), + .soc_clk_byp_en_i ( s_soc_clk_byp_en | s_pad_global_clk_byp_en | s_jtag_global_clk_byp_en ), + .soc_clk_o ( s_soc_clk ), + .per_clk_en_i ( s_per_clk_en ), + .per_clk_byp_en_i ( s_per_clk_byp_en | s_pad_global_clk_byp_en | s_jtag_global_clk_byp_en ), + .per_clk_o ( s_per_clk ) + ); +`else + assign s_soc_clk = ext_soc_clk_i; + assign s_per_clk = ext_per_clk_i; + assign s_slow_clk = ext_slow_clk_i; +`endif // !`ifndef EXTERNAL_CLOCK + + ///////////////////////// + // Reset Synchronizers // + ///////////////////////// + ////////////////////////////////////////////////////////////////////////////// + // TODO Replace this with the digital power management unit to sequence the // + // reset signal assertion.. // + ////////////////////////////////////////////////////////////////////////////// + + // We use the same reset for all clock domains. This means we do not have to + // care about reset_domain crossings. Do not just use seperately controlled + // resets without thinking the reset strategy, its interaction with CDC IPs + // and reset domain crossing through. You will introduce bugs!!! + + + rstgen i_rstgen_slow_clk ( + .clk_i ( s_slow_clk ), + .rst_ni ( s_global_rst_n ), + .test_mode_i ( s_dft_test_en ), + .rst_no ( s_slow_clk_rstn_synced ), // This reset is only needed for IPs + .init_no ( ) // Unused + ); + + rstgen i_rstgen_soc_clk ( + .clk_i ( s_soc_clk ), + .rst_ni ( s_global_rst_n ), + .test_mode_i ( s_dft_test_en ), + .rst_no ( s_soc_rstn_synced ), // This reset is only needed for IPs + .init_no ( ) // Unused + ); + + rstgen i_rstgen_per_clk ( + .clk_i ( s_per_clk ), + .rst_ni ( s_global_rst_n ), + .test_mode_i ( s_dft_test_en ), + .rst_no ( s_per_rstn_synced ), // This reset is only needed for IPs + .init_no ( ) // Unused + ); + + + /////////////////////////////// + // APB Chip Control Demuxing // + /////////////////////////////// + + // Demultiplex the APB bus to 2 regions + // - Clock Control + // - Pad Multiplexer Control + + typedef logic [31:0] addr_t; + typedef logic [31:0] data_t; + + typedef struct packed { + int unsigned idx; + addr_t start_addr; + addr_t end_addr; + } addr_rule_t; + + localparam int unsigned N_CHIP_CTRL_DEMUX_SLAVES = 2; + localparam int unsigned APB_DEMUX_SELECT_WIDTH = $clog2(N_CHIP_CTRL_DEMUX_SLAVES); + localparam addr_rule_t[N_CHIP_CTRL_DEMUX_SLAVES-1:0] APB_DEMUX_ADDR_RULES = '{ + '{ idx: 1, start_addr: `SOC_MEM_MAP_CHIP_CTRL_FLL_START_ADDR, end_addr: `SOC_MEM_MAP_CHIP_CTRL_FLL_END_ADDR}, + '{ idx: 2, start_addr: `SOC_MEM_MAP_CHIP_CTRL_PAD_CFG_START_ADDR, end_addr: `SOC_MEM_MAP_CHIP_CTRL_PAD_CFG_END_ADDR} + }; + + logic [N_CHIP_CTRL_DEMUX_SLAVES-1:0] s_apb_demux_sel; + APB #(.ADDR_WIDTH(32), .DATA_WIDTH(32)) s_apb_demuxed[N_CHIP_CTRL_DEMUX_SLAVES:0](); // +1 for error responses + + addr_decode #( + .NoIndices ( N_CHIP_CTRL_DEMUX_SLAVES+1 ), // + 1 for error slave + .NoRules ( N_CHIP_CTRL_DEMUX_SLAVES ), + .addr_t ( addr_t ), + .rule_t ( addr_rule_t ) + ) i_apb_demux_addr_decode ( + .addr_i ( s_apb_chip_ctrl_bus.paddr ), + .addr_map_i ( APB_DEMUX_ADDR_RULES ), + .idx_o ( s_apb_demux_sel ), + .dec_valid_o ( ), // Ignored + .dec_error_o ( ), // Ignored, we use a default error slave + .en_default_idx_i ( 1'b1 ), + .default_idx_i ( '0 ) + ); + + apb_demux_intf #( + .APB_ADDR_WIDTH ( 32 ), + .APB_DATA_WIDTH ( 32 ), + .NoMstPorts ( N_CHIP_CTRL_DEMUX_SLAVES+1 ) // +1 for the error slave + ) i_demux ( + .slv ( s_apb_chip_ctrl_bus ), + .mst ( s_apb_demuxed ), + .select_i ( s_apb_demux_sel ) + ); + + apb_err_slv_intf #( + .APB_ADDR_WIDTH(32), + .APB_DATA_WIDTH(32) + ) i_err_slv ( + .slv(s_apb_demuxed[0]) + ); + + `APB_ASSIGN(s_apb_fll_ctrl_bus, s_apb_demuxed[1]) + `APB_ASSIGN(s_apb_pads_ctrl_bus, s_apb_demuxed[2]) + + ///////////////////// + // Pad Multiplexer // + ///////////////////// + padframe_adapter i_padframe( + // Config Interface + .soc_clk_i ( s_soc_clk ), + .soc_rstn_synced_i( s_soc_rstn_synced ), + .apb_cfg_slave ( s_apb_pads_ctrl_bus ), + //IO Pads + .pad_ref_clk, + .pad_clk_byp_en, + .pad_reset_n, + .pad_bootsel0, + .pad_bootsel1, + .pad_jtag_tck, + .pad_jtag_trstn, + .pad_jtag_tms, + .pad_jtag_tdi, + .pad_jtag_tdo, + .pad_hyper_csn, + .pad_hyper_reset_n, + .pad_hyper_ck, + .pad_hyper_ckn, + .pad_hyper_dq, + .pad_hyper_rwds, + .pad_io, + // SoC IO Signals + .ref_clk_o ( s_ref_clk ), + .global_rst_no ( s_global_rst_n ), + .global_clk_byp_o ( s_pad_global_clk_byp_en ), + .bootsel_o ( s_bootsel ), + // JTAG + .jtag_tck_o ( s_jtag_tck ), + .jtag_trst_no ( s_jtag_trst_n ), + .jtag_tms_o ( s_jtag_tms ), + .jtag_tdi_o ( s_jtag_tdi ), + .jtag_tdo_i ( s_jtag_tdo ), + // Timers + .timer_ch0_i ( s_timer_ch0 ), + .timer_ch1_i ( s_timer_ch1 ), + .timer_ch2_i ( s_timer_ch2 ), + .timer_ch3_i ( s_timer_ch3 ), + // GPIOs + .gpio_o ( s_gpio_in ), + .gpio_i ( s_gpio_out ), + .gpio_tx_en_i ( s_gpio_tx_en ), + // UART + .uart_to_pad_i ( s_uart_to_pad ), + .pad_to_uart_o ( s_pad_to_uart ), + // I2C + .i2c_to_pad_i ( s_i2c_to_pad ), + .pad_to_i2c_o ( s_pad_to_i2c ), + // SDIO + .sdio_to_pad_i ( s_sdio_to_pad ), + .pad_to_sdio_o ( s_pad_to_sdio ), + // I2S + .i2s_to_pad_i ( s_i2s_to_pad ), + .pad_to_i2s_o ( s_pad_to_i2s ), + // QSPI Master + .qspi_to_pad_i ( s_qspi_to_pad ), + .pad_to_qspi_o ( s_pad_to_qspi ), + // CPI + .pad_to_cpi_o ( s_pad_to_cpi ), + // Hyperflash/Hyper RAM + .hyper_to_pad_i ( s_hyper_to_pad ), + .pad_to_hyper_o ( s_pad_to_hyper ) + ); + + + ///////////////// + // SoC Wrapper // + ///////////////// + soc_domain #( + .CORE_TYPE ( CORE_TYPE ), + .USE_XPULP ( USE_XPULP ), + .USE_FPU ( USE_FPU ), + .USE_ZFINX ( USE_ZFINX ), + .USE_HWPE ( USE_HWPE ), + .SIM_STDOUT ( SIM_STDOUT ) + ) i_soc_domain ( + // Clock and reset signals + .slow_clk_i ( s_slow_clk ), + .slow_clk_rstn_synced_i ( s_slow_clk_rstn_synced ), + .soc_clk_i ( s_soc_clk ), + .soc_rstn_synced_i ( s_soc_rstn_synced ), + .per_clk_i ( s_per_clk ), + .per_rstn_synced_i ( s_per_rstn_synced ), + + // DFT signals (not used but just connected) + .dft_test_mode_i ( s_dft_test_en ), + .dft_cg_enable_i ( s_dft_cg_en ), + + // Boot Mode selection (check bootcode repo for documentation what bootmodes + // are available and how they are mapped) + .bootsel_i ( s_bootsel ), + + // Timer PWM Output signals + .timer_ch0_o ( s_timer_ch0 ), + .timer_ch1_o ( s_timer_ch1 ), + .timer_ch2_o ( s_timer_ch2 ), + .timer_ch3_o ( s_timer_ch3 ), + + // GPIO + .gpio_i ( s_gpio_in ), + .gpio_o ( s_gpio_out ), + .gpio_tx_en_o ( s_gpio_tx_en ), + + // UART + .uart_to_pad_o ( s_uart_to_pad ), + .pad_to_uart_i ( s_pad_to_uart ), + + // I2C + .i2c_to_pad_o ( s_i2c_to_pad ), + .pad_to_i2c_i ( s_pad_to_i2c ), + + // SDIO + .sdio_to_pad_o ( s_sdio_to_pad ), + .pad_to_sdio_i ( s_pad_to_sdio ), + + // I2S + .i2s_to_pad_o ( s_i2s_to_pad ), + .pad_to_i2s_i ( s_pad_to_i2s ), + + // QSPI Master + .qspi_to_pad_o ( s_qspi_to_pad ), + .pad_to_qspi_i ( s_pad_to_qspi ), + + // CPI + .pad_to_cpi_i ( s_pad_to_cpi ), + + // HyperFlash/HyperRAM + .hyper_to_pad_o ( s_hyper_to_pad ), + .pad_to_hyper_i ( s_pad_to_hyper ), + + // fll bypass bit in legacy pulp JTAG TAP. Can be used to control FLL + // bypassing via JTAG instead of dedicated pad + .jtag_tap_bypass_fll_clk_o ( s_jtag_global_clk_byp_en ), + + // APB port to control various aspects of PULPissimo which are platform + // dependent (e.g. pad multiplexer, clock generation etc.). Check + // soc_mem_map.svh for the global address space region which is mapped to + // this port. + .apb_chip_ctrl_master ( s_apb_chip_ctrl_bus ), + + // JTAG Signals (connets to risc-v debug unit legacy pulp debug TAP) + .jtag_tck_i ( s_jtag_tck ), + .jtag_trst_ni ( s_jtag_trst_n ), + .jtag_tms_i ( s_jtag_tms ), + .jtag_tdi_i ( s_jtag_tdi ), + .jtag_tdo_o ( s_jtag_tdo ) + ); + +endmodule diff --git a/hw/soc_domain.sv b/hw/soc_domain.sv new file mode 100644 index 00000000..2a267a14 --- /dev/null +++ b/hw/soc_domain.sv @@ -0,0 +1,221 @@ +//----------------------------------------------------------------------------- +// Title : soc_domain +//----------------------------------------------------------------------------- +// File : soc_domain.sv +// Author : Manuel Eggimann +// Created : 19.04.2022 +//----------------------------------------------------------------------------- +// Description : +// +// PULP SoC Wrapper for PULPissimo. Since `pulp_soc` is shared between the +// single-core SoC variant PULPissimo and the multi-core pulp-open we need a +// pulpissimo specific wrapper that ties of uneccesarry signals and exposes only +// the signals required for pulpissimo. +// +//----------------------------------------------------------------------------- +// Copyright (C) 2022 ETH Zurich, University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// SPDX-License-Identifier: SHL-0.51 +//----------------------------------------------------------------------------- + +`include "pulp_soc_defines.sv" + +module soc_domain #( + parameter CORE_TYPE = 0, + parameter USE_XPULP = 1, + parameter USE_FPU = 1, + parameter USE_ZFINX = 1, + parameter USE_HWPE = 1, + parameter SIM_STDOUT = 1, + localparam NGPIO = gpio_reg_pkg::GPIOCount // Have a look at the README in + // the GPIO repo in order to + // change the number of GPIOs. +)( + // Clock and reset signals + input logic slow_clk_i, + input logic slow_clk_rstn_synced_i, + input logic soc_clk_i, + input logic soc_rstn_synced_i, + input logic per_clk_i, + input logic per_rstn_synced_i, + + // DFT signals + input logic dft_test_mode_i, + input logic dft_cg_enable_i, + // Boot mode selection (check bootcode repo for documentation what bootmodes + // are available and how they are mapped) + input logic [1:0] bootsel_i, + + // Timer PWM output signals (4 channels per timer) + output logic [3:0] timer_ch0_o, + output logic [3:0] timer_ch1_o, + output logic [3:0] timer_ch2_o, + output logic [3:0] timer_ch3_o, + + // GPIO + input logic [NGPIO-1:0] gpio_i, + output logic [NGPIO-1:0] gpio_o, + output logic [NGPIO-1:0] gpio_tx_en_o, + + // uDMA Peripherals + // UART + output uart_pkg::uart_to_pad_t [udma_cfg_pkg::N_UART-1:0] uart_to_pad_o, + input uart_pkg::pad_to_uart_t [udma_cfg_pkg::N_UART-1:0] pad_to_uart_i, + // I2C + output i2c_pkg::i2c_to_pad_t [udma_cfg_pkg::N_I2C-1:0] i2c_to_pad_o, + input i2c_pkg::pad_to_i2c_t [udma_cfg_pkg::N_I2C-1:0] pad_to_i2c_i, + // SDIO + output sdio_pkg::sdio_to_pad_t [udma_cfg_pkg::N_SDIO-1:0] sdio_to_pad_o, + input sdio_pkg::pad_to_sdio_t [udma_cfg_pkg::N_SDIO-1:0] pad_to_sdio_i, + // I2S + output i2s_pkg::i2s_to_pad_t [udma_cfg_pkg::N_I2S-1:0] i2s_to_pad_o, + input i2s_pkg::pad_to_i2s_t [udma_cfg_pkg::N_I2S-1:0] pad_to_i2s_i, + // QSPI + output qspi_pkg::qspi_to_pad_t [udma_cfg_pkg::N_QSPIM-1:0] qspi_to_pad_o, + input qspi_pkg::pad_to_qspi_t [udma_cfg_pkg::N_QSPIM-1:0] pad_to_qspi_i, + // CPI + input cpi_pkg::pad_to_cpi_t [udma_cfg_pkg::N_CPI-1:0] pad_to_cpi_i, + // HYPER + output hyper_pkg::hyper_to_pad_t [udma_cfg_pkg::N_HYPER-1:0] hyper_to_pad_o, + input hyper_pkg::pad_to_hyper_t [udma_cfg_pkg::N_HYPER-1:0] pad_to_hyper_i, + // fll bypass bit in legacy pulp JTAG TAP. Can be used to control FLL + // bypassing via JTAG instead of dedicated pad + output logic jtag_tap_bypass_fll_clk_o, + // APB port to control various aspects of PULPissimo which are platform + // dependent (e.g. pad multiplexer, clock generation etc.). Check + // soc_mem_map.svh for the global address space region which is mapped to + // this port. + APB.Master apb_chip_ctrl_master, + + // JTAG signals (connets to risc-v debug unit legacy pulp debug TAP) + input logic jtag_tck_i, + input logic jtag_trst_ni, + input logic jtag_tms_i, + input logic jtag_tdi_i, + output logic jtag_tdo_o +); + + pulp_soc #( + .CORE_TYPE ( CORE_TYPE ), + .USE_XPULP ( USE_XPULP ), + .USE_FPU ( USE_FPU ), + .USE_HWPE ( USE_HWPE ), + .SIM_STDOUT ( SIM_STDOUT ), + .USE_ZFINX ( USE_ZFINX ), + // We don't really care about the following parameter since they are only + // relevant if you were to attach a cluster to the SoC + .AXI_ADDR_WIDTH ( 32 ), + .AXI_DATA_IN_WIDTH ( 64 ), + .AXI_DATA_OUT_WIDTH ( 32 ), + .AXI_ID_IN_WIDTH ( 6 ), + .AXI_USER_WIDTH ( 6 ), + .CDC_FIFOS_LOG_DEPTH ( 3 ), + .EVNT_WIDTH ( 8 ), + .NB_CORES ( 8 ) + ) i_pulp_soc ( + .slow_clk_i, + .slow_clk_rstn_synced_i, + .soc_clk_i, + .soc_rstn_synced_i, + .per_clk_i, + .per_rstn_synced_i, + .soc_cluster_cdc_rst_ni(soc_rstn_synced_i), // There is no cluster in + // PULPissimo, therefore we are allowed to use + // the same reset for the CDCs and the + // soc_domain itself. DON'T DO THIS IF YOU + // ATTACH SOMETHING TO THE ASYNC CLUSTER PORT! + .dft_test_mode_i, + .dft_cg_enable_i, + .bootsel_i, + // Start booting from bootrom immediately + // after reset + .fc_fetch_en_valid_i(1'b1), + .fc_fetch_en_i(1'b1), + .cluster_rstn_req_o ( ), // PULPissimo doesn't have a cluster + .async_data_slave_aw_wptr_i ( '0 ), // PULPissimo doesn't have a cluster + .async_data_slave_aw_data_i ( '0 ), // PULPissimo doesn't have a cluster + .async_data_slave_aw_rptr_o ( ), // PULPissimo doesn't have a cluster + .async_data_slave_ar_wptr_i ( '0 ), // PULPissimo doesn't have a cluster + .async_data_slave_ar_data_i ( '0 ), // PULPissimo doesn't have a cluster + .async_data_slave_ar_rptr_o ( ), // PULPissimo doesn't have a cluster + .async_data_slave_w_wptr_i ( '0 ), // PULPissimo doesn't have a cluster + .async_data_slave_w_data_i ( '0 ), // PULPissimo doesn't have a cluster + .async_data_slave_w_rptr_o ( ), // PULPissimo doesn't have a cluster + .async_data_slave_r_wptr_o ( ), // PULPissimo doesn't have a cluster + .async_data_slave_r_data_o ( ), // PULPissimo doesn't have a cluster + .async_data_slave_r_rptr_i ( '0 ), // PULPissimo doesn't have a cluster + .async_data_slave_b_wptr_o ( ), // PULPissimo doesn't have a cluster + .async_data_slave_b_data_o ( ), // PULPissimo doesn't have a cluster + .async_data_slave_b_rptr_i ( '0 ), // PULPissimo doesn't have a cluster + .async_data_master_aw_wptr_o ( ), // PULPissimo doesn't have a cluster + .async_data_master_aw_data_o ( ), // PULPissimo doesn't have a cluster + .async_data_master_aw_rptr_i ( '0 ), // PULPissimo doesn't have a cluster + .async_data_master_ar_wptr_o ( ), // PULPissimo doesn't have a cluster + .async_data_master_ar_data_o ( ), // PULPissimo doesn't have a cluster + .async_data_master_ar_rptr_i ( '0 ), // PULPissimo doesn't have a cluster + .async_data_master_w_wptr_o ( ), // PULPissimo doesn't have a cluster + .async_data_master_w_data_o ( ), // PULPissimo doesn't have a cluster + .async_data_master_w_rptr_i ( '0 ), // PULPissimo doesn't have a cluster + .async_data_master_r_wptr_i ( '0 ), // PULPissimo doesn't have a cluster + .async_data_master_r_data_i ( '0 ), // PULPissimo doesn't have a cluster + .async_data_master_r_rptr_o ( ), // PULPissimo doesn't have a cluster + .async_data_master_b_wptr_i ( '0 ), // PULPissimo doesn't have a cluster + .async_data_master_b_data_i ( '0 ), // PULPissimo doesn't have a cluster + .async_data_master_b_rptr_o ( ), // PULPissimo doesn't have a cluster + .async_cluster_events_wptr_o ( ), // PULPissimo doesn't have a cluster + .async_cluster_events_rptr_i ( '0 ), // PULPissimo doesn't have a cluster + .async_cluster_events_data_o ( ), // PULPissimo doesn't have a cluster + .cluster_busy_i ( '0 ), // PULPissimo doesn't have a cluster + .dma_pe_evt_ack_o ( ), // PULPissimo doesn't have a cluster + .dma_pe_evt_valid_i ( '0 ), // PULPissimo doesn't have a cluster + .dma_pe_irq_ack_o ( ), // PULPissimo doesn't have a cluster + .dma_pe_irq_valid_i ( '0 ), // PULPissimo doesn't have a cluster + .pf_evt_ack_o ( ), // PULPissimo doesn't have a cluster + .pf_evt_valid_i ( '0 ), // PULPissimo doesn't have a cluster + .timer_ch0_o, + .timer_ch1_o, + .timer_ch2_o, + .timer_ch3_o, + .uart_to_pad_o, + .pad_to_uart_i, + .i2c_to_pad_o, + .pad_to_i2c_i, + .sdio_to_pad_o, + .pad_to_sdio_i, + .i2s_to_pad_o, + .pad_to_i2s_i, + .qspi_to_pad_o, + .pad_to_qspi_i, + .pad_to_cpi_i, + .hyper_to_pad_o, + .pad_to_hyper_i, + .gpio_i, + .gpio_o, + .gpio_tx_en_o, + .jtag_tap_bypass_fll_clk_o, + .apb_chip_ctrl_master_paddr_o ( apb_chip_ctrl_master.paddr ), + .apb_chip_ctrl_master_pprot_o ( apb_chip_ctrl_master.pprot ), + .apb_chip_ctrl_master_psel_o ( apb_chip_ctrl_master.psel ), + .apb_chip_ctrl_master_penable_o ( apb_chip_ctrl_master.penable ), + .apb_chip_ctrl_master_pwrite_o ( apb_chip_ctrl_master.pwrite ), + .apb_chip_ctrl_master_pwdata_o ( apb_chip_ctrl_master.pwdata ), + .apb_chip_ctrl_master_pstrb_o ( apb_chip_ctrl_master.pstrb ), + .apb_chip_ctrl_master_prdata_i ( apb_chip_ctrl_master.prdata ), + .apb_chip_ctrl_master_pready_i ( apb_chip_ctrl_master.pready ), + .apb_chip_ctrl_master_pslverr_i ( apb_chip_ctrl_master.pslverr ), + .jtag_tck_i, + .jtag_trst_ni, + .jtag_tms_i, + .jtag_tdi_i, + .jtag_tdo_o, + .cluster_dbg_irq_valid_o () // PULPissimo doesn't have a cluster + ); + +endmodule diff --git a/hw/vendored_ips/gpio/.github/verible-lint-matcher.json b/hw/vendored_ips/gpio/.github/verible-lint-matcher.json new file mode 100644 index 00000000..3e0d7966 --- /dev/null +++ b/hw/vendored_ips/gpio/.github/verible-lint-matcher.json @@ -0,0 +1,16 @@ +{ + "problemMatcher": [ + { + "owner": "verible-lint-matcher", + "pattern": [ + { + "regexp": "^(.+):(\\d+):(\\d+):\\s(.+)$", + "file": 1, + "line": 2, + "column": 3, + "message": 4 + } + ] + } + ] +} diff --git a/hw/vendored_ips/gpio/.github/workflows/gitlab-ci.yml b/hw/vendored_ips/gpio/.github/workflows/gitlab-ci.yml new file mode 100644 index 00000000..5c9c8aa4 --- /dev/null +++ b/hw/vendored_ips/gpio/.github/workflows/gitlab-ci.yml @@ -0,0 +1,23 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# Based on https://github.com/pulp-platform/pulp-actions/tree/main/gitlab-ci#action-usage + +# Author: Nils Wistoff + +name: gitlab-ci + +on: [ push, pull_request, workflow_dispatch ] + +jobs: + gitlab-ci: + runs-on: ubuntu-latest + if: github.repository == 'pulp-platform/gpio' && (github.event_name != 'pull_request' || github.event.pull_request.head.repo.full_name == github.repository) + steps: + - name: Check Gitlab CI + uses: pulp-platform/pulp-actions/gitlab-ci@v1 + with: + domain: iis-git.ee.ethz.ch + repo: github-mirror/gpio + token: ${{ secrets.GITLAB_TOKEN }} diff --git a/hw/vendored_ips/gpio/.gitignore b/hw/vendored_ips/gpio/.gitignore new file mode 100644 index 00000000..a78a4414 --- /dev/null +++ b/hw/vendored_ips/gpio/.gitignore @@ -0,0 +1,171 @@ +# Created by https://www.toptal.com/developers/gitignore/api/python +# Edit at https://www.toptal.com/developers/gitignore?templates=python + +### Python ### +# Byte-compiled / optimized / DLL files +__pycache__/ +*.py[cod] +*$py.class + +# C extensions +*.so + +# Distribution / packaging +.Python +build/ +develop-eggs/ +dist/ +downloads/ +eggs/ +.eggs/ +lib/ +lib64/ +parts/ +sdist/ +var/ +wheels/ +share/python-wheels/ +*.egg-info/ +.installed.cfg +*.egg +MANIFEST + +# PyInstaller +# Usually these files are written by a python script from a template +# before PyInstaller builds the exe, so as to inject date/other infos into it. +*.manifest +*.spec + +# Installer logs +pip-log.txt +pip-delete-this-directory.txt + +# Unit test / coverage reports +htmlcov/ +.tox/ +.nox/ +.coverage +.coverage.* +.cache +nosetests.xml +coverage.xml +*.cover +*.py,cover +.hypothesis/ +.pytest_cache/ +cover/ + +# Translations +*.mo +*.pot + +# Django stuff: +*.log +local_settings.py +db.sqlite3 +db.sqlite3-journal + +# Flask stuff: +instance/ +.webassets-cache + +# Scrapy stuff: +.scrapy + +# Sphinx documentation +docs/_build/ + +# PyBuilder +.pybuilder/ +target/ + +# Jupyter Notebook +.ipynb_checkpoints + +# IPython +profile_default/ +ipython_config.py + +# pyenv +# For a library or package, you might want to ignore these files since the code is +# intended to run in multiple environments; otherwise, check them in: +# .python-version + +# pipenv +# According to pypa/pipenv#598, it is recommended to include Pipfile.lock in version control. +# However, in case of collaboration, if having platform-specific dependencies or dependencies +# having no cross-platform support, pipenv may install dependencies that don't work, or not +# install all needed dependencies. +#Pipfile.lock + +# poetry +# Similar to Pipfile.lock, it is generally recommended to include poetry.lock in version control. +# This is especially recommended for binary packages to ensure reproducibility, and is more +# commonly ignored for libraries. +# https://python-poetry.org/docs/basic-usage/#commit-your-poetrylock-file-to-version-control +#poetry.lock + +# pdm +# Similar to Pipfile.lock, it is generally recommended to include pdm.lock in version control. +#pdm.lock +# pdm stores project-wide configurations in .pdm.toml, but it is recommended to not include it +# in version control. +# https://pdm.fming.dev/#use-with-ide +.pdm.toml + +# PEP 582; used by e.g. github.com/David-OConnor/pyflow and github.com/pdm-project/pdm +__pypackages__/ + +# Celery stuff +celerybeat-schedule +celerybeat.pid + +# SageMath parsed files +*.sage.py + +# Environments +.env +.venv +env/ +venv/ +ENV/ +env.bak/ +venv.bak/ + +# Spyder project settings +.spyderproject +.spyproject + +# Rope project settings +.ropeproject + +# mkdocs documentation +/site + +# mypy +.mypy_cache/ +.dmypy.json +dmypy.json + +# Pyre type checker +.pyre/ + +# pytype static type analyzer +.pytype/ + +# Cython debug symbols +cython_debug/ + +# PyCharm +# JetBrains specific template is maintained in a separate JetBrains.gitignore that can +# be found at https://github.com/github/gitignore/blob/main/Global/JetBrains.gitignore +# and can be added to the global gitignore or merged into this file. For a more nuclear +# option (not recommended) you can uncomment the following to ignore the entire idea folder. +#.idea/ + +### Python Patch ### +# Poetry local configuration file - https://python-poetry.org/docs/configuration/#local-configuration +poetry.toml + + +# End of https://www.toptal.com/developers/gitignore/api/python \ No newline at end of file diff --git a/hw/vendored_ips/gpio/.gitlab-ci.yml b/hw/vendored_ips/gpio/.gitlab-ci.yml new file mode 100644 index 00000000..3d208acb --- /dev/null +++ b/hw/vendored_ips/gpio/.gitlab-ci.yml @@ -0,0 +1,24 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + + +variables: + VSIM: questa-2022.3 vsim -64 + VLIB: questa-2022.3 vlib + VMAP: questa-2022.3 vmap + VCOM: questa-2022.3 vcom -64 + VLOG: questa-2022.3 vlog -64 + VOPT: questa-2022.3 vopt -64 + +stages: + - test + +sim: + stage: test + timeout: 5min + script: + - bender script vsim -t test > compile.tcl + - $VSIM -c -do 'exit -code [source compile.tcl]' + - $VSIM -c tb_gpio -do "run -all" + - (! grep -n "Error:" transcript) diff --git a/hw/vendored_ips/gpio/Bender.yml b/hw/vendored_ips/gpio/Bender.yml new file mode 100644 index 00000000..843bd428 --- /dev/null +++ b/hw/vendored_ips/gpio/Bender.yml @@ -0,0 +1,34 @@ +package: + name: gpio + authors: + - "Manuel Eggimann " + +dependencies: + tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.9 } + common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } + common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0} + register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.1} + apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } # To be udpated once PR #6 got merged. + axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.2 } + +sources: + - src/gpio_reg_pkg.sv + - src/gpio_reg_top.sv + - src/gpio.sv + - src/gpio_axi_lite_wrap.sv + - src/gpio_apb_wrap.sv + - target: all(any(test, gpio_include_tb_files), not(gpio_exclude_tb_files)) + files: + - test/tb_gpio.sv + - target: all(any(simulation, asic, gpio_with_clk_gates), not(gpio_no_clk_gates)) + files: + - src/gpio_input_stage.sv + - target: all(any(fpga, gpio_no_clk_gates), not(gpio_with_clk_gates)) + files: + - src/gpio_input_stage_no_clk_gates.sv +vendor_package: + - name: reggen + target_dir: "util" + upstream: { git: "https://github.com/pulp-platform/register_interface.git", rev: "fe3cc459f02a75efed697cf0d6cb73df27763dbe"} + mapping: + - { from: 'vendor/lowrisc_opentitan/util', to: 'reggen'} diff --git a/hw/vendored_ips/gpio/CHANGELOG.md b/hw/vendored_ips/gpio/CHANGELOG.md new file mode 100644 index 00000000..719172c8 --- /dev/null +++ b/hw/vendored_ips/gpio/CHANGELOG.md @@ -0,0 +1,55 @@ +# Changelog +All notable changes to this project will be documented in this file. + +The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/) +and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.html). + +## 0.2.2 - 2023-06-12 +### Added +- Added simple CI +### Changed +- Bump bender dependencies +### Fixed +- Fix typos and errors in documentation + +## 0.2.1 - 2022-12-15 +### Changed +- Simplified reconfiguration flow by using vendored-in regtool.py +### Fixed +- Overlapping bitfield definition in hjson description of the CFG register. +- Remove now obsolete Makefile dependency on bender checkout dir + +## 0.2.0 - 2022-12-09 +### Breaking Changes +- Changed the module interface. ``interrupt_o`` was renamed to + ``global_interrupt_o``. Additionally, the module also exposes pin level + interrupt signals in addition to the single, globally multiplexed gpio + interrupt signal. Existing RTL integrating this IP need to adapt the port + list of their instantiations. +### Changed +- Change default pad count from 56 to 32. +- Use the clock gated input stage by default for simulation targets +- Bump AXI Version +### Fixed +- Fix warning about unconnected interface port + +## 0.1.2 - 2022-12-04 +### Changed +- Added make dependencies to auto-setup python env for reconfiguration + +### Fixed +- Fix some small issues reported by linter + +## 0.1.1 - 2022-10-07 +### Changed +- Bumped AXI version to v0.35.3 +- Added NumRepetitions to tb_gpio to choose test duration +- Refactored TB + +### Fixed +- Fix tx_en inversion bug for open-drain mode 1 +- Fix bug in TB that caused open-drain misbehavior not to be catched + + +## 0.1.0 - 2022-04-14 +Initial release diff --git a/hw/vendored_ips/gpio/LICENSE b/hw/vendored_ips/gpio/LICENSE new file mode 100644 index 00000000..18e4f676 --- /dev/null +++ b/hw/vendored_ips/gpio/LICENSE @@ -0,0 +1,176 @@ +SOLDERPAD HARDWARE LICENSE version 0.51 + +This license is based closely on the Apache License Version 2.0, but is not +approved or endorsed by the Apache Foundation. A copy of the non-modified +Apache License 2.0 can be found at http://www.apache.org/licenses/LICENSE-2.0. + +As this license is not currently OSI or FSF approved, the Licensor permits any +Work licensed under this License, at the option of the Licensee, to be treated +as licensed under the Apache License Version 2.0 (which is so approved). + +This License is licensed under the terms of this License and in particular +clause 7 below (Disclaimer of Warranties) applies in relation to its use. + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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While redistributing the Work or +Derivative Works thereof, You may choose to offer, and charge a fee for, +acceptance of support, warranty, indemnity, or other liability obligations +and/or rights consistent with this License. However, in accepting such +obligations, You may act only on Your own behalf and on Your sole +responsibility, not on behalf of any other Contributor, and only if You agree +to indemnify, defend, and hold each Contributor harmless for any liability +incurred by, or claims asserted against, such Contributor by reason of your +accepting any such warranty or additional liability. + +END OF TERMS AND CONDITIONS diff --git a/hw/vendored_ips/gpio/Makefile b/hw/vendored_ips/gpio/Makefile new file mode 100644 index 00000000..7c5899ee --- /dev/null +++ b/hw/vendored_ips/gpio/Makefile @@ -0,0 +1,32 @@ +.DEFAULT_GOAL := help + +VENVDIR?=$(WORKDIR)/.venv +REQUIREMENTS_TXT?=$(wildcard requirements.txt) +include Makefile.venv + +GPIOS ?= 32 + +## Regenerate the register file and HAL C-header for a different GPIO count. Usage: make reconfigure GPIOS=128 +reconfigure: | venv + @echo Reconfiguring IP to use $(GPIOS) gpios... + @sed -i -r 's/default: "[0-9]+"/default: "${GPIOS}"/g' gpio_regs.hjson +ifeq ($(shell expr $(GPIOS) \<= 16), 1) + @sed -i -r 's|(//)?`define ENABLE_LESS_THAN_16_GPIOS_REG_PKG_WORKAROUND|`define ENABLE_LESS_THAN_16_GPIOS_REG_PKG_WORKAROUND|g' test/tb_gpio.sv +else + @sed -i -r 's|(//)?`define ENABLE_LESS_THAN_16_GPIOS_REG_PKG_WORKAROUND|//`define ENABLE_LESS_THAN_16_GPIOS_REG_PKG_WORKAROUND|g' test/tb_gpio.sv +endif +ifeq ($(shell expr $(GPIOS) \<= 32), 1) + @sed -i -r 's|(//)?`define ENABLE_LESS_THAN_32_GPIOS_REG_PKG_WORKAROUND|`define ENABLE_LESS_THAN_32_GPIOS_REG_PKG_WORKAROUND|g' test/tb_gpio.sv +else + @sed -i -r 's|(//)?`define ENABLE_LESS_THAN_32_GPIOS_REG_PKG_WORKAROUND|//`define ENABLE_LESS_THAN_32_GPIOS_REG_PKG_WORKAROUND|g' test/tb_gpio.sv +endif + $(VENV)/python util/reggen/regtool.py gpio_regs.hjson -r -t src -p GPIOCount=${GPIOS} + $(VENV)/python util/reggen/regtool.py gpio_regs.hjson --cdefines -o hal/gpio_hal.h -p GPIOCount=${GPIOS}; + @echo "Done" + +.PHONY: help +help: Makefile + @printf "GPIO Reconfiguration\n" + @printf "Use this Makefile to regenerate the register file and HAL C-header for a different number GPIOs than the default one.\n\n" + @printf "Usage: \n" + @printf "make reconfigure GPIOS=\n\n" diff --git a/hw/vendored_ips/gpio/Makefile.venv b/hw/vendored_ips/gpio/Makefile.venv new file mode 100644 index 00000000..c79b9bbc --- /dev/null +++ b/hw/vendored_ips/gpio/Makefile.venv @@ -0,0 +1,274 @@ +# +# SEAMLESSLY MANAGE PYTHON VIRTUAL ENVIRONMENT WITH A MAKEFILE +# +# https://github.com/sio/Makefile.venv v2022.07.20 +# +# +# Insert `include Makefile.venv` at the bottom of your Makefile to enable these +# rules. +# +# When writing your Makefile use '$(VENV)/python' to refer to the Python +# interpreter within virtual environment and '$(VENV)/executablename' for any +# other executable in venv. +# +# This Makefile provides the following targets: +# venv +# Use this as a dependency for any target that requires virtual +# environment to be created and configured +# python, ipython +# Use these to launch interactive Python shell within virtual environment +# shell, bash, zsh +# Launch interactive command line shell. "shell" target launches the +# default shell Makefile executes its rules in (usually /bin/sh). +# "bash" and "zsh" can be used to refer to the specific desired shell. +# show-venv +# Show versions of Python and pip, and the path to the virtual environment +# clean-venv +# Remove virtual environment +# $(VENV)/executable_name +# Install `executable_name` with pip. Only packages with names matching +# the name of the corresponding executable are supported. +# Use this as a lightweight mechanism for development dependencies +# tracking. E.g. for one-off tools that are not required in every +# developer's environment, therefore are not included into +# requirements.txt or setup.py. +# Note: +# Rules using such target or dependency MUST be defined below +# `include` directive to make use of correct $(VENV) value. +# Example: +# codestyle: $(VENV)/pyflakes +# $(VENV)/pyflakes . +# See `ipython` target below for another example. +# +# This Makefile can be configured via following variables: +# PY +# Command name for system Python interpreter. It is used only initially to +# create the virtual environment +# Default: python3 +# REQUIREMENTS_TXT +# Space separated list of paths to requirements.txt files. +# Paths are resolved relative to current working directory. +# Default: requirements.txt +# +# Non-existent files are treated as hard dependencies, +# recipes for creating such files must be provided by the main Makefile. +# Providing empty value (REQUIREMENTS_TXT=) turns off processing of +# requirements.txt even when the file exists. +# SETUP_PY +# Space separated list of paths to setup.py files. +# Corresponding packages will be installed into venv in editable mode +# along with all their dependencies +# Default: setup.py +# +# Non-existent and empty values are treated in the same way as for REQUIREMENTS_TXT. +# WORKDIR +# Parent directory for the virtual environment. +# Default: current working directory. +# VENVDIR +# Python virtual environment directory. +# Default: $(WORKDIR)/.venv +# +# This Makefile was written for GNU Make and may not work with other make +# implementations. +# +# +# Copyright (c) 2019-2020 Vitaly Potyarkin +# +# Licensed under the Apache License, Version 2.0 +# +# + + +# +# Configuration variables +# + +WORKDIR?=. +VENVDIR?=$(WORKDIR)/.venv +REQUIREMENTS_TXT?=$(wildcard requirements.txt) # Multiple paths are supported (space separated) +SETUP_PY?=$(wildcard setup.py) # Multiple paths are supported (space separated) +SETUP_CFG?=$(foreach s,$(SETUP_PY),$(wildcard $(patsubst %setup.py,%setup.cfg,$(s)))) +MARKER=.initialized-with-Makefile.venv + + +# +# Python interpreter detection +# + +_PY_AUTODETECT_MSG=Detected Python interpreter: $(PY). Use PY environment variable to override + +ifeq (ok,$(shell test -e /dev/null 2>&1 && echo ok)) +NULL_STDERR=2>/dev/null +else +NULL_STDERR=2>NUL +endif + +ifndef PY +_PY_OPTION:=python3 +ifeq (ok,$(shell $(_PY_OPTION) -c "print('ok')" $(NULL_STDERR))) +PY=$(_PY_OPTION) +endif +endif + +ifndef PY +_PY_OPTION:=$(VENVDIR)/bin/python +ifeq (ok,$(shell $(_PY_OPTION) -c "print('ok')" $(NULL_STDERR))) +PY=$(_PY_OPTION) +$(info $(_PY_AUTODETECT_MSG)) +endif +endif + +ifndef PY +_PY_OPTION:=$(subst /,\,$(VENVDIR)/Scripts/python) +ifeq (ok,$(shell $(_PY_OPTION) -c "print('ok')" $(NULL_STDERR))) +PY=$(_PY_OPTION) +$(info $(_PY_AUTODETECT_MSG)) +endif +endif + +ifndef PY +_PY_OPTION:=py -3 +ifeq (ok,$(shell $(_PY_OPTION) -c "print('ok')" $(NULL_STDERR))) +PY=$(_PY_OPTION) +$(info $(_PY_AUTODETECT_MSG)) +endif +endif + +ifndef PY +_PY_OPTION:=python +ifeq (ok,$(shell $(_PY_OPTION) -c "print('ok')" $(NULL_STDERR))) +PY=$(_PY_OPTION) +$(info $(_PY_AUTODETECT_MSG)) +endif +endif + +ifndef PY +define _PY_AUTODETECT_ERR +Could not detect Python interpreter automatically. +Please specify path to interpreter via PY environment variable. +endef +$(error $(_PY_AUTODETECT_ERR)) +endif + + +# +# Internal variable resolution +# + +VENV=$(VENVDIR)/bin +EXE= +# Detect windows +ifeq (win32,$(shell $(PY) -c "import __future__, sys; print(sys.platform)")) +VENV=$(VENVDIR)/Scripts +EXE=.exe +endif + +touch=touch $(1) +ifeq (,$(shell command -v touch $(NULL_STDERR))) +# https://ss64.com/nt/touch.html +touch=type nul >> $(subst /,\,$(1)) && copy /y /b $(subst /,\,$(1))+,, $(subst /,\,$(1)) +endif + +RM?=rm -f +ifeq (,$(shell command -v $(firstword $(RM)) $(NULL_STDERR))) +RMDIR:=rd /s /q +else +RMDIR:=$(RM) -r +endif + + +# +# Virtual environment +# + +.PHONY: venv +venv: $(VENV)/$(MARKER) + +.PHONY: clean-venv +clean-venv: + -$(RMDIR) "$(VENVDIR)" + +.PHONY: show-venv +show-venv: venv + @$(VENV)/python -c "import sys; print('Python ' + sys.version.replace('\n',''))" + @$(VENV)/pip --version + @echo venv: $(VENVDIR) + +.PHONY: debug-venv +debug-venv: + @echo "PATH (Shell)=$$PATH" + @$(MAKE) --version + $(info PATH (GNU Make)="$(PATH)") + $(info SHELL="$(SHELL)") + $(info PY="$(PY)") + $(info REQUIREMENTS_TXT="$(REQUIREMENTS_TXT)") + $(info SETUP_PY="$(SETUP_PY)") + $(info SETUP_CFG="$(SETUP_CFG)") + $(info VENVDIR="$(VENVDIR)") + $(info VENVDEPENDS="$(VENVDEPENDS)") + $(info WORKDIR="$(WORKDIR)") + + +# +# Dependencies +# + +ifneq ($(strip $(REQUIREMENTS_TXT)),) +VENVDEPENDS+=$(REQUIREMENTS_TXT) +endif + +ifneq ($(strip $(SETUP_PY)),) +VENVDEPENDS+=$(SETUP_PY) +endif +ifneq ($(strip $(SETUP_CFG)),) +VENVDEPENDS+=$(SETUP_CFG) +endif + +$(VENV): + $(PY) -m venv $(VENVDIR) + $(VENV)/python -m pip install --upgrade pip setuptools wheel + +$(VENV)/$(MARKER): $(VENVDEPENDS) | $(VENV) +ifneq ($(strip $(REQUIREMENTS_TXT)),) + $(VENV)/pip install $(foreach path,$(REQUIREMENTS_TXT),-r $(path)) +endif +ifneq ($(strip $(SETUP_PY)),) + $(VENV)/pip install $(foreach path,$(SETUP_PY),-e $(dir $(path))) +endif + $(call touch,$(VENV)/$(MARKER)) + + +# +# Interactive shells +# + +.PHONY: python +python: venv + exec $(VENV)/python + +.PHONY: ipython +ipython: $(VENV)/ipython + exec $(VENV)/ipython + +.PHONY: shell +shell: venv + . $(VENV)/activate && exec $(notdir $(SHELL)) + +.PHONY: bash zsh +bash zsh: venv + . $(VENV)/activate && exec $@ + + +# +# Commandline tools (wildcard rule, executable name must match package name) +# + +ifneq ($(EXE),) +$(VENV)/%: $(VENV)/%$(EXE) ; +.PHONY: $(VENV)/% +.PRECIOUS: $(VENV)/%$(EXE) +endif + +$(VENV)/%$(EXE): $(VENV)/$(MARKER) + $(VENV)/pip install --upgrade $* + $(call touch,$@) diff --git a/hw/vendored_ips/gpio/README.md b/hw/vendored_ips/gpio/README.md new file mode 100644 index 00000000..40baff6d --- /dev/null +++ b/hw/vendored_ips/gpio/README.md @@ -0,0 +1,275 @@ +# GPIO Peripheral + +This repository provides an simple GPIO peripheral with integrated register file +to control 64 GPIOs (by default). The peripheral performs two stage +synchronization of the inputs to resolve potential metastability. The outputs +can be driven in push-pull or open-drain mode. Each GPIO supports any +combination of rising-edge, falling-edge, low-level and high-level interrupts +with individual status registers to query the type of pending interrupts. + +The interface to the peripheral is the lightweight [register_interface protocol](https://github.com/pulp-platform/register_interface ). +However, the repository contains convenience wrappers to attach AXI-lite or APB +buses for control. Each module in the repository contains an additional wrapper +at the bottom of the respective source files for the users that prefer +SystemVerilog interfaces over hierarchical structs. + +# Changing Number of GPIOs + Changing the number of GPIOs requires regeneration of the register file to + include the right number of config registers. The `gpio.sv` will automatically + adapt accordingly. + + The repo contains a Makefile that simplifies the process of invoking the reggen tool for this regeneration. + E.g. the following comand will reconfigure the project for 48 GPIOs. + + ``` + make reconfigure GPIOS=48 + ``` + +# Ports +| **Signal Name** | **Direction** | **Description** | +| ------------------------ | ------------- | --------------- | +| `clk_i` | *input* | Primary input clock. The control interface is suposed to be synchronous to this clock. | +| `rst_ni` | *input* | Asynchronous active-low reset | +| `gpio_in` | *input* | GPIO input signals from IO Pads (Pad -> SoC) signal. | +| `gpio_out` | *output* | GPIO output signals to IO Pads (SoC -> Pad) signal. | +| `gpio_tx_en_o` | *output* | GPIO TX Buffer enable signal. This signal is supposed to control the output buffer enable of the IO Pad. 0 -> TX disabled (High-Z or Pull-low/high), 1 -> TX. | +| `gpio_in_sync_o` | *input* | Synchronized GPIO input signals. This port provides the `gpio_in` signal synchronized to `clk_i`. | +| `global_interrupt_o` | *output* | Global interrupt line. The interrupt line is asserted for one `clk_i` if one or more unmasked interrupts occur, or asserted on any unmaksed interrupt and held until all interrupts are cleared depending on the `glbl_intrpt_mode` setting in the `CFG` register. | +| `pin_level_interrupts_o` | *output* | Per-pin interrupt lines. Each interrupt line is asserted for one `clk_i` if an interrupt occurs on the respective pin or asserted and held on an unamsked interrupt until the respective interrupt has been cleared depending on the `pin_lvl_intrpt_mode` setting in the `CFG` register. | +| `reg_req_i` | *input* | Control interface request side using register interface protocol. | +| `reg_rsp_o` | *output* | Control interface request side using register_interface protocol. | + +# Clock Gates +The GPIO IP manually instantiates a clock gate for each input to reduce power +consumption when the corresponding GPIO is disabled. However, some target +technologies (e.g. FPGA) don't behave that well when the clock path contains to +many clock gating resources. Therefore, the IP is available in two flavors, one +with the manual clock gates and one without them. You can (*and have to*) select +between the two by either supplying the /Bender Target/ `-t gpio_with_clk_gates` +or `-t gpio_no_clk_gates`. + +# Register Map +The registers of this module are all defined in the `gpio_regs.hjson` file which +is used to auto-generate the actual SV register file using [lowRISCs reggen tool](https://docs.opentitan.org/doc/rm/register_tool/ ). + +Here is a summary of the registers: +## `INFO` Register (offset 0x00, read-only) + Contains read-only registers with the number of GPIOs this instance of the + GPIO peripheral was parametrized for and an IP version number. + + | 31 - 20 | 19 - 10 | 9 - 0 | + |------------|------------|-----------------| + | *reserved* | IP_VERSION | Number of GPIOs | + + +## `CFG` Register (offset 0x04, rw) + Controls the operation of the global and pin-level interrupt outputs respectively. + + If `glbl_intrpt_mode` is 1, the global interrupt output is asserted until all interrupts are cleared. If 0, + a one-cycle pulse is generated every cycle were one or more interrupts occur. + + If `pin_lvl_intrpt_mode` is 1, a pin level interrupt outputs will are asserted until the respective interrupt has been + cleared. If 0, a one-cycle pulse is generated for interrupt that occurs on the respective pin. + + | 31 - 2 | 1 | 0 | + |------------|-----------------------|--------------------| + | *reserved* | `pin_lvl_intrpt_mode` | `glbl_intrpt_mode` | + +## `GPIO_MODE<0-XX>` Registers (offset 0x08+*4, rw) + The GPIO_MODE registers control the operating mode of the individual GPIOs. + Each register controls 16 GPIOs. + + | 31 - 30 | ... | 3 - 2 | 1 - 0 | + |----------|-----|---------|---------| + | `GPIO15` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + + The values for `GPIO0_MODE` are: + + | Value | Description | + |-------|-------------------------------------------------------------------------------| + | 0 | Configures GPIO as an input. | + | 1 | Configures GPIO as a push-pull output. | + | 2 | Configures the GPIO to be in open_drain0 (0 -> High-Z, 1 -> Drive High) mode. | + | 3 | Configures the GPIO to be in open_drain1 (0 -> Drive Low, 1 -> High-Z) mode. | + +## `GPIO_EN<0-XX>` Registers (offset 0x80+*4, rw) + Each bit of these registers control the sampling of one GPIO. This register + enables sampling of the inputs. If disables (0) the corresponding GPIO will + not sample the inputs (saves power) and will not generate any interrupts. + + | 31 | ... | 1 | 0 | + |----------|-----|---------|---------| + | `GPIO31` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + +## `GPIO_IN<0-XX>` Registers (offset 0x100+*4, read-only) + The bits of these registers contain the input values of the corresponding + gpios. + + | 31 | ... | 1 | 0 | + |----------|-----|---------|---------| + | `GPIO31` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + +## `GPIO_OUT<0-XX>` Registers (offset 0x180+*4, rw) + Change the value of the corresponding GPIO. In `GPIO_MODE 1` writing 1 drives + high, writing 0 drives low. In `GPIO_MODE 2` (drive 1) writing a 1 will drive + the gpio to high while writing a 0 will put the gpio in high-z. In `GPIO_MODE + 3` writing 0 drives low and writing 1 puts the gpio into high-z. + + | 31 | ... | 1 | 0 | + |----------|-----|---------|---------| + | `GPIO31` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + +## `GPIO_SET<0-XX>` Registers (offset 0x200+*4, rw) + For each asserted bit in the register, set the corresponding bit in the + GPIO_OUT register (masked set). This simplifys setting a single gpio without + altering the state of the other ones. + + | 31 | ... | 1 | 0 | + |----------|-----|---------|---------| + | `GPIO31` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + +## `GPIO_CLEAR<0-XX>` Registers (offset 0x280+*4, rw) + For each asserted bit in the register, clear the corresponding bit in the + GPIO_OUT register (masked clear). This simplifys clearing a single gpio without + altering the state of the other ones. + + | 31 | ... | 1 | 0 | + |----------|-----|---------|---------| + | `GPIO31` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + +## `GPIO_TOGGLE<0-XX>` Registers (offset 0x300+*4, rw) + For each asserted bit in the register, toggle the corresponding bit in the + GPIO_OUT register (masked toggle). This simplifys toggling a single gpio without + altering the state of the other ones. + + | 31 | ... | 1 | 0 | + |----------|-----|---------|---------| + | `GPIO31` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + +## `INTRPT_RISE_EN<0-xx>` Registers (offset 0x380+*4, rw) + Enable interrupts on rising edges for the corresponding GPIO. + + The corresponding gpio needs to be enabled `GPIO_EN`. Once an interrupt + condition is detected, the global interrupt line `interrupt_o` is asserted + (according to the interrupt mode in `CFG`) and the corresponding bit in the + interrupt status registers is set. To clear the interrupt, write a `1` to the + corresponding bit in the status register. + + | 31 | ... | 1 | 0 | + |----------|-----|---------|---------| + | `GPIO31` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + +## `INTRPT_FALL_EN<0-xx>` Registers (offset 0x400+*4, rw) + Enable interrupts on falling edges for the corresponding GPIO. + + The corresponding gpio needs to be enabled `GPIO_EN`. Once an interrupt + condition is detected, the global interrupt line `interrupt_o` is asserted + (according to the interrupt mode in `CFG`) and the corresponding bit in the + interrupt status registers is set. To clear the interrupt, write a `1` to the + corresponding bit in the status register. + + | 31 | ... | 1 | 0 | + |----------|-----|---------|---------| + | `GPIO31` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + +## `INTRPT_LVL_HIGH_EN<0-xx>` Registers (offset 0x480+*4, rw) + Enable logic-high level-sensitive interrupts for the corresponding GPIO + (interrupt keeps getting triggered while GPIO is high). + + The corresponding gpio needs to be enabled `GPIO_EN`. Once an interrupt + condition is detected, the global interrupt line `interrupt_o` is asserted + (according to the interrupt mode in `CFG`) and the corresponding bit in the + interrupt status registers is set. To clear the interrupt, write a `1` to the + corresponding bit in the status register. + + | 31 | ... | 1 | 0 | + |----------|-----|---------|---------| + | `GPIO31` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + +## `INTRPT_LVL_LOW_EN<0-xx>` Registers (offset 0x500+*4, rw) + Enable logic-low level-sensitive interrupts for the corresponding GPIO + (interrupt keeps getting triggered while GPIO is low). + + The corresponding gpio needs to be enabled `GPIO_EN`. Once an interrupt + condition is detected, the global interrupt line `interrupt_o` is asserted + (according to the interrupt mode in `CFG`) and the corresponding bit in the + interrupt status registers is set. To clear the interrupt, write a `1` to the + corresponding bit in the status register. + + | 31 | ... | 1 | 0 | + |----------|-----|---------|---------| + | `GPIO31` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + +## `INTRPT_STATUS<0-xx>` Registers (offset 0x580+*4, rw) + Each bit indicates if there are any pending interrupts on the corresponding + GPIO. Writing a 1 to a specific bit clears **all** pending interrupts (rise, + fall, low, high) for the corresponding GPIO. + + | 31 | ... | 1 | 0 | + |----------|-----|---------|---------| + | `GPIO31` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + +## `INTRPT_RISE_STATUS<0-xx>` Registers (offset 0x600+*4, rw) + Each bit indicates if there is a pending rising-edge interrupt on the corresponding + GPIO. Writing a 1 to a specific bit clears the interrupt for the corresponding GPIO. + + | 31 | ... | 1 | 0 | + |----------|-----|---------|---------| + | `GPIO31` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + +## `INTRPT_FALL_STATUS<0-xx>` Registers (offset 0x680+*4, rw) + Each bit indicates if there is a pending falling-edge interrupt on the corresponding + GPIO. Writing a 1 to a specific bit clears the interrupt for the corresponding GPIO. + + | 31 | ... | 1 | 0 | + |----------|-----|---------|---------| + | `GPIO31` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + +## `INTRPT_LVL_LOW_STATUS<0-xx>` Registers (offset 0x700+*4, rw) + Each bit indicates if there is a pending low-level sensitive interrupt on the corresponding + GPIO. Writing a 1 to a specific bit clears the interrupt for the corresponding GPIO. + + | 31 | ... | 1 | 0 | + |----------|-----|---------|---------| + | `GPIO31` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + +## `INTRPT_LVL_HIGH_STATUS<0-xx>` Registers (offset 0x780+*4, rw) + Each bit indicates if there is a pending low-level sensitive interrupt on the corresponding + GPIO. Writing a 1 to a specific bit clears the interrupt for the corresponding GPIO. + + | 31 | ... | 1 | 0 | + |----------|-----|---------|---------| + | `GPIO31` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + diff --git a/hw/vendored_ips/gpio/gpio_regs.hjson b/hw/vendored_ips/gpio/gpio_regs.hjson new file mode 100644 index 00000000..25c02891 --- /dev/null +++ b/hw/vendored_ips/gpio/gpio_regs.hjson @@ -0,0 +1,353 @@ +{ + name: "gpio" + clock_primary: "clk_i" + reset_primary: "rst_ni" + param_list: [ + { + name: GPIOCount + default: "32" + } + ] + bus_interfaces: [ + { protocol: "reg_iface", direction: "device"} + ] + regwidth: 32, + registers: [ + { + name: "INFO" + desc: "Info register that contains information about this peripheral." + swaccess: "ro", + hwaccess: "hwo", + hwext: true + fields: [ + { + name: "GPIO_CNT" + bits: "9:0" + desc: "Contains the number of GPIOs controlled by this peripheral." + } + { + name: "VERSION" + bits: "19:10" + desc: "The version number of the IPs." + resval: 2 + } + ] + } + { + name: "CFG" + desc: "Global configuration register for the peripheral" + swaccess: "rw" + hwaccess: "hro" + fields: [ + { + name: "GLBL_INTRPT_MODE" + bits: "0" + desc: ''' + If 1, keep the interrupt line asserted until all + interrupts are cleared. If 0, generate one cycle wide pulse for every interrupt. + ''' + resval: 0 + } + { + name: "PIN_LVL_INTRPT_MODE" + bits: "1" + desc: ''' + If 1, keep the interrupt line asserted until all + interrupts are cleared. If 0, generate one cycle wide pulse for every interrupt. + ''' + resval: 0 + } + ] + } + { multireg: + { name: "GPIO_MODE", + cname: "GPIO_MODE", + count: "GPIOCount", + desc: "Set the IO Mode of the GPIO." + swaccess: "rw", + hwaccess: "hro", + compact: true + fields: [ + { + bits: "1:0" + name: "MODE", + desc: "Change the IO mode of the GPIO." + resval: "0" + enum: [ + { value: 0, name: "INPUT_ONLY", desc: "The correspondin GPIO acts as an input only." } + { value: 1, name: "OUTPUT_ACTIVE", desc: "Actively drive output to 0 or 1" } + { value: 2, name: "OPEN_DRAIN0", desc: "Value 1 drives, value 0 enables tristate. "} + { value: 3, name: "OPEN_DRAIN1", desc: "Value 0 drives, value 1 enables tristate. "} + ] + } + ] + } + } + {skipto: "0x080"} + { multireg: + { name: "GPIO_EN", + cname: "GPIO_EN", + count: "GPIOCount", + compact: true, + desc: "Enable sampling on the corresponding GPIO", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { + bits: "0" + } + ] + } + } + {skipto: "0x100"} + { multireg: + { name: "GPIO_IN", + cname: "GPIO_IN", + count: "GPIOCount", + compact: true, + desc: "Read the current input values of all GPIOs." + swaccess: "ro", + hwaccess: "hwo", + hwext: true + fields: [ + { + bits: "0" + } + ] + } + } + {skipto: "0x180"} + { multireg: + { name: "GPIO_OUT", + cname: "GPIO_OUT", + count: "GPIOCount", + compact: true, + desc: "Set the output value of the corresponding GPIOs." + swaccess: "rw", + hwaccess: "hrw", + fields: [ + { + bits: "0" + } + ] + } + } + {skipto: "0x200"} + { multireg: + { name: "GPIO_SET", + cname: "GPIO_SET", + count: "GPIOCount", + compact: true, + desc: "For each asserted bit in this register, set the corresponding bit in the padout register." + swaccess: "wo", + hwaccess: "hro", + hwqe: true, + hwext: true, + fields: [ + { + bits: "0" + } + ] + } + } + {skipto: "0x280"} + { multireg: + { name: "GPIO_CLEAR", + cname: "GPIO_CLEAR", + count: "GPIOCount", + compact: true, + desc: "For each asserted bit in this register, clear the corresponding bit in the padout register." + swaccess: "wo", + hwaccess: "hro", + hwqe: true, + hwext: true, + fields: [ + { + bits: "0" + } + ] + } + } + {skipto: "0x300"} + { multireg: + { name: "GPIO_TOGGLE", + cname: "GPIO_TOGGLE", + count: "GPIOCount", + compact: true + desc: "For each asserted bit in this register, toggle the corresponding bit in the padout register." + swaccess: "wo", + hwaccess: "hro", + hwqe: true, + hwext: true, + fields: [ + { + bits: "0" + } + ] + } + } + {skipto: "0x380"} + { multireg: + { name: "INTRPT_RISE_EN", + cname: "INTRPT_RISE_EN", + count: "GPIOCount", + compact: true + desc: "Enable Interrupts on rising edges for the corresponding GPIO" + swaccess: "rw", + hwaccess: "hro", + fields: [ + { + bits: "0" + } + ] + } + } + {skipto: "0x400"} + { multireg: + { name: "INTRPT_FALL_EN", + cname: "INTRPT_FALL_EN", + count: "GPIOCount", + compact: true + desc: "Enable Interrupts on falling edges for the corresponding GPIO" + swaccess: "rw", + hwaccess: "hro", + fields: [ + { + bits: "0" + } + ] + } + } + {skipto: "0x480"} + { multireg: + { name: "INTRPT_LVL_HIGH_EN", + cname: "INTRPT_LVL_HIGH_EN", + count: "GPIOCount", + compact: true + desc: "Enable logic high level-sensitive Interrupts on the corresponding GPIO" + swaccess: "rw", + hwaccess: "hro", + fields: [ + { + bits: "0" + } + ] + } + } + {skipto: "0x500"} + { multireg: + { name: "INTRPT_LVL_LOW_EN", + cname: "INTRPT_LVL_LOW_EN", + count: "GPIOCount", + compact: true + desc: "Enable logic low level-sensitive Interrupts on the corresponding GPIO" + swaccess: "rw", + hwaccess: "hro", + fields: [ + { + bits: "0" + } + ] + } + } + {skipto: "0x580"} + { multireg: + { name: "INTRPT_STATUS", + cname: "INTRPT_STATUS", + count: "GPIOCount", + compact: true + desc: ''' + Asserted if there is any pending interrupts on corresponding GPIOs. + Writing 1 to a specific bit clears all pending interrupts (rise, fall, low, high) of the corresponding GPIO. + ''' + swaccess: "rw1c", + hwaccess: "hrw", + hwqe: true, + hwext: true, + fields: [ + { + bits: "0" + } + ] + } + } + {skipto: "0x600"} + { multireg: + { name: "INTRPT_RISE_STATUS", + cname: "INTRPT_RISE_STATUS", + count: "GPIOCount", + compact: true + desc: ''' + Asserted if there is a pending rise interrupts on corresponding GPIOs. + Writing 1 to a specific bit clears the pending interrupt of the corresponding GPIO. + ''' + fields: [ + { + bits: "0" + swaccess: "rw1c", + hwaccess: "hrw", + } + ] + } + } + {skipto: "0x680"} + { multireg: + { name: "INTRPT_FALL_STATUS", + cname: "INTRPT_FALL_STATUS", + count: "GPIOCount", + compact: true + desc: ''' + Asserted if there is any pending fall interrupts on corresponding GPIOs. + Writing 1 to a specific bit clears the pending interrupt of the corresponding GPIO. + ''' + fields: [ + { + bits: "0" + swaccess: "rw1c", + hwaccess: "hrw", + } + ] + } + } + {skipto: "0x700"} + { multireg: + { name: "INTRPT_LVL_HIGH_STATUS", + cname: "INTRPT_LVL_HIGH_STATUS", + count: "GPIOCount", + compact: true + desc: ''' + Asserted if there is any pending high-level interrupts on corresponding GPIOs. + Writing 1 to a specific bit clears the pending interrupt of the corresponding GPIO. + ''' + swaccess: "rw1c", + hwaccess: "hrw", + fields: [ + { + bits: "0" + swaccess: "rw1c", + hwaccess: "hrw", + } + ] + } + } + {skipto: "0x780"} + { multireg: + { name: "INTRPT_LVL_LOW_STATUS", + cname: "INTRPT_LVL_LOW_STATUS", + count: "GPIOCount", + compact: true + desc: ''' + Asserted if there is any pending low-level interrupts on corresponding GPIOs. + Writing 1 to a specific bit clears the pending interrupt of the corresponding GPIO. + ''' + fields: [ + { + bits: "0" + swaccess: "rw1c", + hwaccess: "hrw", + } + ] + } + } + ] +} diff --git a/hw/vendored_ips/gpio/hal/gpio_hal.h b/hw/vendored_ips/gpio/hal/gpio_hal.h new file mode 100644 index 00000000..d559f46f --- /dev/null +++ b/hw/vendored_ips/gpio/hal/gpio_hal.h @@ -0,0 +1,851 @@ +// Generated register defines for gpio + +#ifndef _GPIO_REG_DEFS_ +#define _GPIO_REG_DEFS_ + +#ifdef __cplusplus +extern "C" { +#endif +#define GPIO_PARAM_G_P_I_O_COUNT 32 + +// Register width +#define GPIO_PARAM_REG_WIDTH 32 + +// Info register that contains information about this peripheral. +#define GPIO_INFO_REG_OFFSET 0x0 +#define GPIO_INFO_GPIO_CNT_MASK 0x3ff +#define GPIO_INFO_GPIO_CNT_OFFSET 0 +#define GPIO_INFO_GPIO_CNT_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_INFO_GPIO_CNT_MASK, .index = GPIO_INFO_GPIO_CNT_OFFSET }) +#define GPIO_INFO_VERSION_MASK 0x3ff +#define GPIO_INFO_VERSION_OFFSET 10 +#define GPIO_INFO_VERSION_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_INFO_VERSION_MASK, .index = GPIO_INFO_VERSION_OFFSET }) + +// Global configuration register for the peripheral +#define GPIO_CFG_REG_OFFSET 0x4 +#define GPIO_CFG_GLBL_INTRPT_MODE_BIT 0 +#define GPIO_CFG_PIN_LVL_INTRPT_MODE_BIT 1 + +// Set the IO Mode of the GPIO. (common parameters) +#define GPIO_GPIO_MODE_MODE_FIELD_WIDTH 2 +#define GPIO_GPIO_MODE_MODE_FIELDS_PER_REG 16 +#define GPIO_GPIO_MODE_MULTIREG_COUNT 2 + +// Set the IO Mode of the GPIO. +#define GPIO_GPIO_MODE_0_REG_OFFSET 0x8 +#define GPIO_GPIO_MODE_0_MODE_0_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_0_OFFSET 0 +#define GPIO_GPIO_MODE_0_MODE_0_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_0_MASK, .index = GPIO_GPIO_MODE_0_MODE_0_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_0_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_0_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_0_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_0_VALUE_OPEN_DRAIN1 0x3 +#define GPIO_GPIO_MODE_0_MODE_1_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_1_OFFSET 2 +#define GPIO_GPIO_MODE_0_MODE_1_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_1_MASK, .index = GPIO_GPIO_MODE_0_MODE_1_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_1_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_1_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_1_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_1_VALUE_OPEN_DRAIN1 0x3 +#define GPIO_GPIO_MODE_0_MODE_2_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_2_OFFSET 4 +#define GPIO_GPIO_MODE_0_MODE_2_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_2_MASK, .index = GPIO_GPIO_MODE_0_MODE_2_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_2_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_2_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_2_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_2_VALUE_OPEN_DRAIN1 0x3 +#define GPIO_GPIO_MODE_0_MODE_3_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_3_OFFSET 6 +#define GPIO_GPIO_MODE_0_MODE_3_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_3_MASK, .index = GPIO_GPIO_MODE_0_MODE_3_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_3_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_3_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_3_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_3_VALUE_OPEN_DRAIN1 0x3 +#define GPIO_GPIO_MODE_0_MODE_4_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_4_OFFSET 8 +#define GPIO_GPIO_MODE_0_MODE_4_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_4_MASK, .index = GPIO_GPIO_MODE_0_MODE_4_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_4_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_4_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_4_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_4_VALUE_OPEN_DRAIN1 0x3 +#define GPIO_GPIO_MODE_0_MODE_5_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_5_OFFSET 10 +#define GPIO_GPIO_MODE_0_MODE_5_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_5_MASK, .index = GPIO_GPIO_MODE_0_MODE_5_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_5_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_5_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_5_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_5_VALUE_OPEN_DRAIN1 0x3 +#define GPIO_GPIO_MODE_0_MODE_6_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_6_OFFSET 12 +#define GPIO_GPIO_MODE_0_MODE_6_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_6_MASK, .index = GPIO_GPIO_MODE_0_MODE_6_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_6_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_6_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_6_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_6_VALUE_OPEN_DRAIN1 0x3 +#define GPIO_GPIO_MODE_0_MODE_7_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_7_OFFSET 14 +#define GPIO_GPIO_MODE_0_MODE_7_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_7_MASK, .index = GPIO_GPIO_MODE_0_MODE_7_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_7_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_7_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_7_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_7_VALUE_OPEN_DRAIN1 0x3 +#define GPIO_GPIO_MODE_0_MODE_8_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_8_OFFSET 16 +#define GPIO_GPIO_MODE_0_MODE_8_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_8_MASK, .index = GPIO_GPIO_MODE_0_MODE_8_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_8_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_8_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_8_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_8_VALUE_OPEN_DRAIN1 0x3 +#define GPIO_GPIO_MODE_0_MODE_9_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_9_OFFSET 18 +#define GPIO_GPIO_MODE_0_MODE_9_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_9_MASK, .index = GPIO_GPIO_MODE_0_MODE_9_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_9_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_9_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_9_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_9_VALUE_OPEN_DRAIN1 0x3 +#define GPIO_GPIO_MODE_0_MODE_10_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_10_OFFSET 20 +#define GPIO_GPIO_MODE_0_MODE_10_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_10_MASK, .index = GPIO_GPIO_MODE_0_MODE_10_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_10_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_10_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_10_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_10_VALUE_OPEN_DRAIN1 0x3 +#define GPIO_GPIO_MODE_0_MODE_11_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_11_OFFSET 22 +#define GPIO_GPIO_MODE_0_MODE_11_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_11_MASK, .index = GPIO_GPIO_MODE_0_MODE_11_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_11_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_11_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_11_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_11_VALUE_OPEN_DRAIN1 0x3 +#define GPIO_GPIO_MODE_0_MODE_12_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_12_OFFSET 24 +#define GPIO_GPIO_MODE_0_MODE_12_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_12_MASK, .index = GPIO_GPIO_MODE_0_MODE_12_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_12_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_12_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_12_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_12_VALUE_OPEN_DRAIN1 0x3 +#define GPIO_GPIO_MODE_0_MODE_13_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_13_OFFSET 26 +#define GPIO_GPIO_MODE_0_MODE_13_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_13_MASK, .index = GPIO_GPIO_MODE_0_MODE_13_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_13_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_13_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_13_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_13_VALUE_OPEN_DRAIN1 0x3 +#define GPIO_GPIO_MODE_0_MODE_14_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_14_OFFSET 28 +#define GPIO_GPIO_MODE_0_MODE_14_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_14_MASK, .index = GPIO_GPIO_MODE_0_MODE_14_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_14_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_14_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_14_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_14_VALUE_OPEN_DRAIN1 0x3 +#define GPIO_GPIO_MODE_0_MODE_15_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_15_OFFSET 30 +#define GPIO_GPIO_MODE_0_MODE_15_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_15_MASK, .index = GPIO_GPIO_MODE_0_MODE_15_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_15_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_15_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_15_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_15_VALUE_OPEN_DRAIN1 0x3 + +// Set the IO Mode of the GPIO. +#define GPIO_GPIO_MODE_1_REG_OFFSET 0xc +#define GPIO_GPIO_MODE_1_MODE_16_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_16_OFFSET 0 +#define GPIO_GPIO_MODE_1_MODE_16_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_16_MASK, .index = GPIO_GPIO_MODE_1_MODE_16_OFFSET }) +#define GPIO_GPIO_MODE_1_MODE_17_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_17_OFFSET 2 +#define GPIO_GPIO_MODE_1_MODE_17_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_17_MASK, .index = GPIO_GPIO_MODE_1_MODE_17_OFFSET }) +#define GPIO_GPIO_MODE_1_MODE_18_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_18_OFFSET 4 +#define GPIO_GPIO_MODE_1_MODE_18_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_18_MASK, .index = GPIO_GPIO_MODE_1_MODE_18_OFFSET }) +#define GPIO_GPIO_MODE_1_MODE_19_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_19_OFFSET 6 +#define GPIO_GPIO_MODE_1_MODE_19_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_19_MASK, .index = GPIO_GPIO_MODE_1_MODE_19_OFFSET }) +#define GPIO_GPIO_MODE_1_MODE_20_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_20_OFFSET 8 +#define GPIO_GPIO_MODE_1_MODE_20_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_20_MASK, .index = GPIO_GPIO_MODE_1_MODE_20_OFFSET }) +#define GPIO_GPIO_MODE_1_MODE_21_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_21_OFFSET 10 +#define GPIO_GPIO_MODE_1_MODE_21_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_21_MASK, .index = GPIO_GPIO_MODE_1_MODE_21_OFFSET }) +#define GPIO_GPIO_MODE_1_MODE_22_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_22_OFFSET 12 +#define GPIO_GPIO_MODE_1_MODE_22_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_22_MASK, .index = GPIO_GPIO_MODE_1_MODE_22_OFFSET }) +#define GPIO_GPIO_MODE_1_MODE_23_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_23_OFFSET 14 +#define GPIO_GPIO_MODE_1_MODE_23_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_23_MASK, .index = GPIO_GPIO_MODE_1_MODE_23_OFFSET }) +#define GPIO_GPIO_MODE_1_MODE_24_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_24_OFFSET 16 +#define GPIO_GPIO_MODE_1_MODE_24_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_24_MASK, .index = GPIO_GPIO_MODE_1_MODE_24_OFFSET }) +#define GPIO_GPIO_MODE_1_MODE_25_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_25_OFFSET 18 +#define GPIO_GPIO_MODE_1_MODE_25_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_25_MASK, .index = GPIO_GPIO_MODE_1_MODE_25_OFFSET }) +#define GPIO_GPIO_MODE_1_MODE_26_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_26_OFFSET 20 +#define GPIO_GPIO_MODE_1_MODE_26_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_26_MASK, .index = GPIO_GPIO_MODE_1_MODE_26_OFFSET }) +#define GPIO_GPIO_MODE_1_MODE_27_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_27_OFFSET 22 +#define GPIO_GPIO_MODE_1_MODE_27_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_27_MASK, .index = GPIO_GPIO_MODE_1_MODE_27_OFFSET }) +#define GPIO_GPIO_MODE_1_MODE_28_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_28_OFFSET 24 +#define GPIO_GPIO_MODE_1_MODE_28_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_28_MASK, .index = GPIO_GPIO_MODE_1_MODE_28_OFFSET }) +#define GPIO_GPIO_MODE_1_MODE_29_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_29_OFFSET 26 +#define GPIO_GPIO_MODE_1_MODE_29_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_29_MASK, .index = GPIO_GPIO_MODE_1_MODE_29_OFFSET }) +#define GPIO_GPIO_MODE_1_MODE_30_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_30_OFFSET 28 +#define GPIO_GPIO_MODE_1_MODE_30_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_30_MASK, .index = GPIO_GPIO_MODE_1_MODE_30_OFFSET }) +#define GPIO_GPIO_MODE_1_MODE_31_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_31_OFFSET 30 +#define GPIO_GPIO_MODE_1_MODE_31_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_31_MASK, .index = GPIO_GPIO_MODE_1_MODE_31_OFFSET }) + +// Enable sampling on the corresponding GPIO (common parameters) +#define GPIO_GPIO_EN_GPIO_EN_FIELD_WIDTH 1 +#define GPIO_GPIO_EN_GPIO_EN_FIELDS_PER_REG 32 +#define GPIO_GPIO_EN_MULTIREG_COUNT 1 + +// Enable sampling on the corresponding GPIO +#define GPIO_GPIO_EN_REG_OFFSET 0x80 +#define GPIO_GPIO_EN_GPIO_EN_0_BIT 0 +#define GPIO_GPIO_EN_GPIO_EN_1_BIT 1 +#define GPIO_GPIO_EN_GPIO_EN_2_BIT 2 +#define GPIO_GPIO_EN_GPIO_EN_3_BIT 3 +#define GPIO_GPIO_EN_GPIO_EN_4_BIT 4 +#define GPIO_GPIO_EN_GPIO_EN_5_BIT 5 +#define GPIO_GPIO_EN_GPIO_EN_6_BIT 6 +#define GPIO_GPIO_EN_GPIO_EN_7_BIT 7 +#define GPIO_GPIO_EN_GPIO_EN_8_BIT 8 +#define GPIO_GPIO_EN_GPIO_EN_9_BIT 9 +#define GPIO_GPIO_EN_GPIO_EN_10_BIT 10 +#define GPIO_GPIO_EN_GPIO_EN_11_BIT 11 +#define GPIO_GPIO_EN_GPIO_EN_12_BIT 12 +#define GPIO_GPIO_EN_GPIO_EN_13_BIT 13 +#define GPIO_GPIO_EN_GPIO_EN_14_BIT 14 +#define GPIO_GPIO_EN_GPIO_EN_15_BIT 15 +#define GPIO_GPIO_EN_GPIO_EN_16_BIT 16 +#define GPIO_GPIO_EN_GPIO_EN_17_BIT 17 +#define GPIO_GPIO_EN_GPIO_EN_18_BIT 18 +#define GPIO_GPIO_EN_GPIO_EN_19_BIT 19 +#define GPIO_GPIO_EN_GPIO_EN_20_BIT 20 +#define GPIO_GPIO_EN_GPIO_EN_21_BIT 21 +#define GPIO_GPIO_EN_GPIO_EN_22_BIT 22 +#define GPIO_GPIO_EN_GPIO_EN_23_BIT 23 +#define GPIO_GPIO_EN_GPIO_EN_24_BIT 24 +#define GPIO_GPIO_EN_GPIO_EN_25_BIT 25 +#define GPIO_GPIO_EN_GPIO_EN_26_BIT 26 +#define GPIO_GPIO_EN_GPIO_EN_27_BIT 27 +#define GPIO_GPIO_EN_GPIO_EN_28_BIT 28 +#define GPIO_GPIO_EN_GPIO_EN_29_BIT 29 +#define GPIO_GPIO_EN_GPIO_EN_30_BIT 30 +#define GPIO_GPIO_EN_GPIO_EN_31_BIT 31 + +// Read the current input values of all GPIOs. (common parameters) +#define GPIO_GPIO_IN_GPIO_IN_FIELD_WIDTH 1 +#define GPIO_GPIO_IN_GPIO_IN_FIELDS_PER_REG 32 +#define GPIO_GPIO_IN_MULTIREG_COUNT 1 + +// Read the current input values of all GPIOs. +#define GPIO_GPIO_IN_REG_OFFSET 0x100 +#define GPIO_GPIO_IN_GPIO_IN_0_BIT 0 +#define GPIO_GPIO_IN_GPIO_IN_1_BIT 1 +#define GPIO_GPIO_IN_GPIO_IN_2_BIT 2 +#define GPIO_GPIO_IN_GPIO_IN_3_BIT 3 +#define GPIO_GPIO_IN_GPIO_IN_4_BIT 4 +#define GPIO_GPIO_IN_GPIO_IN_5_BIT 5 +#define GPIO_GPIO_IN_GPIO_IN_6_BIT 6 +#define GPIO_GPIO_IN_GPIO_IN_7_BIT 7 +#define GPIO_GPIO_IN_GPIO_IN_8_BIT 8 +#define GPIO_GPIO_IN_GPIO_IN_9_BIT 9 +#define GPIO_GPIO_IN_GPIO_IN_10_BIT 10 +#define GPIO_GPIO_IN_GPIO_IN_11_BIT 11 +#define GPIO_GPIO_IN_GPIO_IN_12_BIT 12 +#define GPIO_GPIO_IN_GPIO_IN_13_BIT 13 +#define GPIO_GPIO_IN_GPIO_IN_14_BIT 14 +#define GPIO_GPIO_IN_GPIO_IN_15_BIT 15 +#define GPIO_GPIO_IN_GPIO_IN_16_BIT 16 +#define GPIO_GPIO_IN_GPIO_IN_17_BIT 17 +#define GPIO_GPIO_IN_GPIO_IN_18_BIT 18 +#define GPIO_GPIO_IN_GPIO_IN_19_BIT 19 +#define GPIO_GPIO_IN_GPIO_IN_20_BIT 20 +#define GPIO_GPIO_IN_GPIO_IN_21_BIT 21 +#define GPIO_GPIO_IN_GPIO_IN_22_BIT 22 +#define GPIO_GPIO_IN_GPIO_IN_23_BIT 23 +#define GPIO_GPIO_IN_GPIO_IN_24_BIT 24 +#define GPIO_GPIO_IN_GPIO_IN_25_BIT 25 +#define GPIO_GPIO_IN_GPIO_IN_26_BIT 26 +#define GPIO_GPIO_IN_GPIO_IN_27_BIT 27 +#define GPIO_GPIO_IN_GPIO_IN_28_BIT 28 +#define GPIO_GPIO_IN_GPIO_IN_29_BIT 29 +#define GPIO_GPIO_IN_GPIO_IN_30_BIT 30 +#define GPIO_GPIO_IN_GPIO_IN_31_BIT 31 + +// Set the output value of the corresponding GPIOs. (common parameters) +#define GPIO_GPIO_OUT_GPIO_OUT_FIELD_WIDTH 1 +#define GPIO_GPIO_OUT_GPIO_OUT_FIELDS_PER_REG 32 +#define GPIO_GPIO_OUT_MULTIREG_COUNT 1 + +// Set the output value of the corresponding GPIOs. +#define GPIO_GPIO_OUT_REG_OFFSET 0x180 +#define GPIO_GPIO_OUT_GPIO_OUT_0_BIT 0 +#define GPIO_GPIO_OUT_GPIO_OUT_1_BIT 1 +#define GPIO_GPIO_OUT_GPIO_OUT_2_BIT 2 +#define GPIO_GPIO_OUT_GPIO_OUT_3_BIT 3 +#define GPIO_GPIO_OUT_GPIO_OUT_4_BIT 4 +#define GPIO_GPIO_OUT_GPIO_OUT_5_BIT 5 +#define GPIO_GPIO_OUT_GPIO_OUT_6_BIT 6 +#define GPIO_GPIO_OUT_GPIO_OUT_7_BIT 7 +#define GPIO_GPIO_OUT_GPIO_OUT_8_BIT 8 +#define GPIO_GPIO_OUT_GPIO_OUT_9_BIT 9 +#define GPIO_GPIO_OUT_GPIO_OUT_10_BIT 10 +#define GPIO_GPIO_OUT_GPIO_OUT_11_BIT 11 +#define GPIO_GPIO_OUT_GPIO_OUT_12_BIT 12 +#define GPIO_GPIO_OUT_GPIO_OUT_13_BIT 13 +#define GPIO_GPIO_OUT_GPIO_OUT_14_BIT 14 +#define GPIO_GPIO_OUT_GPIO_OUT_15_BIT 15 +#define GPIO_GPIO_OUT_GPIO_OUT_16_BIT 16 +#define GPIO_GPIO_OUT_GPIO_OUT_17_BIT 17 +#define GPIO_GPIO_OUT_GPIO_OUT_18_BIT 18 +#define GPIO_GPIO_OUT_GPIO_OUT_19_BIT 19 +#define GPIO_GPIO_OUT_GPIO_OUT_20_BIT 20 +#define GPIO_GPIO_OUT_GPIO_OUT_21_BIT 21 +#define GPIO_GPIO_OUT_GPIO_OUT_22_BIT 22 +#define GPIO_GPIO_OUT_GPIO_OUT_23_BIT 23 +#define GPIO_GPIO_OUT_GPIO_OUT_24_BIT 24 +#define GPIO_GPIO_OUT_GPIO_OUT_25_BIT 25 +#define GPIO_GPIO_OUT_GPIO_OUT_26_BIT 26 +#define GPIO_GPIO_OUT_GPIO_OUT_27_BIT 27 +#define GPIO_GPIO_OUT_GPIO_OUT_28_BIT 28 +#define GPIO_GPIO_OUT_GPIO_OUT_29_BIT 29 +#define GPIO_GPIO_OUT_GPIO_OUT_30_BIT 30 +#define GPIO_GPIO_OUT_GPIO_OUT_31_BIT 31 + +// For each asserted bit in this register, set the corresponding bit in the +// padout register. (common parameters) +#define GPIO_GPIO_SET_GPIO_SET_FIELD_WIDTH 1 +#define GPIO_GPIO_SET_GPIO_SET_FIELDS_PER_REG 32 +#define GPIO_GPIO_SET_MULTIREG_COUNT 1 + +// For each asserted bit in this register, set the corresponding bit in the +// padout register. +#define GPIO_GPIO_SET_REG_OFFSET 0x200 +#define GPIO_GPIO_SET_GPIO_SET_0_BIT 0 +#define GPIO_GPIO_SET_GPIO_SET_1_BIT 1 +#define GPIO_GPIO_SET_GPIO_SET_2_BIT 2 +#define GPIO_GPIO_SET_GPIO_SET_3_BIT 3 +#define GPIO_GPIO_SET_GPIO_SET_4_BIT 4 +#define GPIO_GPIO_SET_GPIO_SET_5_BIT 5 +#define GPIO_GPIO_SET_GPIO_SET_6_BIT 6 +#define GPIO_GPIO_SET_GPIO_SET_7_BIT 7 +#define GPIO_GPIO_SET_GPIO_SET_8_BIT 8 +#define GPIO_GPIO_SET_GPIO_SET_9_BIT 9 +#define GPIO_GPIO_SET_GPIO_SET_10_BIT 10 +#define GPIO_GPIO_SET_GPIO_SET_11_BIT 11 +#define GPIO_GPIO_SET_GPIO_SET_12_BIT 12 +#define GPIO_GPIO_SET_GPIO_SET_13_BIT 13 +#define GPIO_GPIO_SET_GPIO_SET_14_BIT 14 +#define GPIO_GPIO_SET_GPIO_SET_15_BIT 15 +#define GPIO_GPIO_SET_GPIO_SET_16_BIT 16 +#define GPIO_GPIO_SET_GPIO_SET_17_BIT 17 +#define GPIO_GPIO_SET_GPIO_SET_18_BIT 18 +#define GPIO_GPIO_SET_GPIO_SET_19_BIT 19 +#define GPIO_GPIO_SET_GPIO_SET_20_BIT 20 +#define GPIO_GPIO_SET_GPIO_SET_21_BIT 21 +#define GPIO_GPIO_SET_GPIO_SET_22_BIT 22 +#define GPIO_GPIO_SET_GPIO_SET_23_BIT 23 +#define GPIO_GPIO_SET_GPIO_SET_24_BIT 24 +#define GPIO_GPIO_SET_GPIO_SET_25_BIT 25 +#define GPIO_GPIO_SET_GPIO_SET_26_BIT 26 +#define GPIO_GPIO_SET_GPIO_SET_27_BIT 27 +#define GPIO_GPIO_SET_GPIO_SET_28_BIT 28 +#define GPIO_GPIO_SET_GPIO_SET_29_BIT 29 +#define GPIO_GPIO_SET_GPIO_SET_30_BIT 30 +#define GPIO_GPIO_SET_GPIO_SET_31_BIT 31 + +// For each asserted bit in this register, clear the corresponding bit in the +// padout register. (common parameters) +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_FIELD_WIDTH 1 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_FIELDS_PER_REG 32 +#define GPIO_GPIO_CLEAR_MULTIREG_COUNT 1 + +// For each asserted bit in this register, clear the corresponding bit in the +// padout register. +#define GPIO_GPIO_CLEAR_REG_OFFSET 0x280 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_0_BIT 0 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_1_BIT 1 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_2_BIT 2 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_3_BIT 3 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_4_BIT 4 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_5_BIT 5 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_6_BIT 6 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_7_BIT 7 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_8_BIT 8 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_9_BIT 9 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_10_BIT 10 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_11_BIT 11 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_12_BIT 12 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_13_BIT 13 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_14_BIT 14 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_15_BIT 15 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_16_BIT 16 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_17_BIT 17 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_18_BIT 18 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_19_BIT 19 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_20_BIT 20 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_21_BIT 21 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_22_BIT 22 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_23_BIT 23 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_24_BIT 24 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_25_BIT 25 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_26_BIT 26 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_27_BIT 27 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_28_BIT 28 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_29_BIT 29 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_30_BIT 30 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_31_BIT 31 + +// For each asserted bit in this register, toggle the corresponding bit in +// the padout register. (common parameters) +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_FIELD_WIDTH 1 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_FIELDS_PER_REG 32 +#define GPIO_GPIO_TOGGLE_MULTIREG_COUNT 1 + +// For each asserted bit in this register, toggle the corresponding bit in +// the padout register. +#define GPIO_GPIO_TOGGLE_REG_OFFSET 0x300 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_0_BIT 0 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_1_BIT 1 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_2_BIT 2 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_3_BIT 3 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_4_BIT 4 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_5_BIT 5 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_6_BIT 6 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_7_BIT 7 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_8_BIT 8 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_9_BIT 9 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_10_BIT 10 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_11_BIT 11 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_12_BIT 12 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_13_BIT 13 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_14_BIT 14 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_15_BIT 15 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_16_BIT 16 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_17_BIT 17 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_18_BIT 18 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_19_BIT 19 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_20_BIT 20 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_21_BIT 21 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_22_BIT 22 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_23_BIT 23 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_24_BIT 24 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_25_BIT 25 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_26_BIT 26 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_27_BIT 27 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_28_BIT 28 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_29_BIT 29 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_30_BIT 30 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_31_BIT 31 + +// Enable Interrupts on rising edges for the corresponding GPIO (common +// parameters) +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_FIELD_WIDTH 1 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_FIELDS_PER_REG 32 +#define GPIO_INTRPT_RISE_EN_MULTIREG_COUNT 1 + +// Enable Interrupts on rising edges for the corresponding GPIO +#define GPIO_INTRPT_RISE_EN_REG_OFFSET 0x380 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_0_BIT 0 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_1_BIT 1 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_2_BIT 2 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_3_BIT 3 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_4_BIT 4 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_5_BIT 5 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_6_BIT 6 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_7_BIT 7 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_8_BIT 8 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_9_BIT 9 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_10_BIT 10 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_11_BIT 11 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_12_BIT 12 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_13_BIT 13 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_14_BIT 14 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_15_BIT 15 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_16_BIT 16 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_17_BIT 17 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_18_BIT 18 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_19_BIT 19 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_20_BIT 20 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_21_BIT 21 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_22_BIT 22 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_23_BIT 23 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_24_BIT 24 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_25_BIT 25 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_26_BIT 26 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_27_BIT 27 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_28_BIT 28 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_29_BIT 29 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_30_BIT 30 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_31_BIT 31 + +// Enable Interrupts on falling edges for the corresponding GPIO (common +// parameters) +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_FIELD_WIDTH 1 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_FIELDS_PER_REG 32 +#define GPIO_INTRPT_FALL_EN_MULTIREG_COUNT 1 + +// Enable Interrupts on falling edges for the corresponding GPIO +#define GPIO_INTRPT_FALL_EN_REG_OFFSET 0x400 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_0_BIT 0 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_1_BIT 1 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_2_BIT 2 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_3_BIT 3 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_4_BIT 4 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_5_BIT 5 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_6_BIT 6 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_7_BIT 7 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_8_BIT 8 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_9_BIT 9 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_10_BIT 10 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_11_BIT 11 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_12_BIT 12 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_13_BIT 13 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_14_BIT 14 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_15_BIT 15 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_16_BIT 16 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_17_BIT 17 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_18_BIT 18 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_19_BIT 19 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_20_BIT 20 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_21_BIT 21 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_22_BIT 22 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_23_BIT 23 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_24_BIT 24 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_25_BIT 25 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_26_BIT 26 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_27_BIT 27 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_28_BIT 28 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_29_BIT 29 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_30_BIT 30 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_31_BIT 31 + +// Enable logic high level-sensitive Interrupts on the corresponding GPIO +// (common parameters) +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_FIELD_WIDTH 1 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_FIELDS_PER_REG 32 +#define GPIO_INTRPT_LVL_HIGH_EN_MULTIREG_COUNT 1 + +// Enable logic high level-sensitive Interrupts on the corresponding GPIO +#define GPIO_INTRPT_LVL_HIGH_EN_REG_OFFSET 0x480 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_0_BIT 0 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_1_BIT 1 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_2_BIT 2 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_3_BIT 3 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_4_BIT 4 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_5_BIT 5 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_6_BIT 6 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_7_BIT 7 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_8_BIT 8 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_9_BIT 9 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_10_BIT 10 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_11_BIT 11 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_12_BIT 12 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_13_BIT 13 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_14_BIT 14 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_15_BIT 15 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_16_BIT 16 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_17_BIT 17 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_18_BIT 18 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_19_BIT 19 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_20_BIT 20 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_21_BIT 21 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_22_BIT 22 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_23_BIT 23 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_24_BIT 24 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_25_BIT 25 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_26_BIT 26 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_27_BIT 27 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_28_BIT 28 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_29_BIT 29 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_30_BIT 30 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_31_BIT 31 + +// Enable logic low level-sensitive Interrupts on the corresponding GPIO +// (common parameters) +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_FIELD_WIDTH 1 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_FIELDS_PER_REG 32 +#define GPIO_INTRPT_LVL_LOW_EN_MULTIREG_COUNT 1 + +// Enable logic low level-sensitive Interrupts on the corresponding GPIO +#define GPIO_INTRPT_LVL_LOW_EN_REG_OFFSET 0x500 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_0_BIT 0 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_1_BIT 1 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_2_BIT 2 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_3_BIT 3 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_4_BIT 4 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_5_BIT 5 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_6_BIT 6 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_7_BIT 7 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_8_BIT 8 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_9_BIT 9 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_10_BIT 10 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_11_BIT 11 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_12_BIT 12 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_13_BIT 13 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_14_BIT 14 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_15_BIT 15 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_16_BIT 16 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_17_BIT 17 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_18_BIT 18 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_19_BIT 19 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_20_BIT 20 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_21_BIT 21 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_22_BIT 22 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_23_BIT 23 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_24_BIT 24 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_25_BIT 25 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_26_BIT 26 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_27_BIT 27 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_28_BIT 28 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_29_BIT 29 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_30_BIT 30 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_31_BIT 31 + +// Asserted if there is any pending interrupts on corresponding GPIOs. +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_FIELD_WIDTH 1 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_FIELDS_PER_REG 32 +#define GPIO_INTRPT_STATUS_MULTIREG_COUNT 1 + +// Asserted if there is any pending interrupts on corresponding GPIOs. +#define GPIO_INTRPT_STATUS_REG_OFFSET 0x580 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_0_BIT 0 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_1_BIT 1 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_2_BIT 2 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_3_BIT 3 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_4_BIT 4 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_5_BIT 5 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_6_BIT 6 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_7_BIT 7 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_8_BIT 8 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_9_BIT 9 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_10_BIT 10 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_11_BIT 11 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_12_BIT 12 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_13_BIT 13 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_14_BIT 14 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_15_BIT 15 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_16_BIT 16 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_17_BIT 17 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_18_BIT 18 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_19_BIT 19 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_20_BIT 20 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_21_BIT 21 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_22_BIT 22 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_23_BIT 23 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_24_BIT 24 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_25_BIT 25 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_26_BIT 26 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_27_BIT 27 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_28_BIT 28 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_29_BIT 29 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_30_BIT 30 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_31_BIT 31 + +// Asserted if there is a pending rise interrupts on corresponding GPIOs. +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_FIELD_WIDTH 1 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_FIELDS_PER_REG 32 +#define GPIO_INTRPT_RISE_STATUS_MULTIREG_COUNT 1 + +// Asserted if there is a pending rise interrupts on corresponding GPIOs. +#define GPIO_INTRPT_RISE_STATUS_REG_OFFSET 0x600 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_0_BIT 0 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_1_BIT 1 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_2_BIT 2 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_3_BIT 3 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_4_BIT 4 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_5_BIT 5 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_6_BIT 6 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_7_BIT 7 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_8_BIT 8 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_9_BIT 9 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_10_BIT 10 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_11_BIT 11 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_12_BIT 12 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_13_BIT 13 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_14_BIT 14 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_15_BIT 15 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_16_BIT 16 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_17_BIT 17 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_18_BIT 18 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_19_BIT 19 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_20_BIT 20 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_21_BIT 21 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_22_BIT 22 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_23_BIT 23 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_24_BIT 24 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_25_BIT 25 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_26_BIT 26 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_27_BIT 27 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_28_BIT 28 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_29_BIT 29 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_30_BIT 30 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_31_BIT 31 + +// Asserted if there is any pending fall interrupts on corresponding GPIOs. +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_FIELD_WIDTH 1 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_FIELDS_PER_REG 32 +#define GPIO_INTRPT_FALL_STATUS_MULTIREG_COUNT 1 + +// Asserted if there is any pending fall interrupts on corresponding GPIOs. +#define GPIO_INTRPT_FALL_STATUS_REG_OFFSET 0x680 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_0_BIT 0 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_1_BIT 1 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_2_BIT 2 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_3_BIT 3 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_4_BIT 4 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_5_BIT 5 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_6_BIT 6 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_7_BIT 7 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_8_BIT 8 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_9_BIT 9 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_10_BIT 10 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_11_BIT 11 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_12_BIT 12 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_13_BIT 13 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_14_BIT 14 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_15_BIT 15 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_16_BIT 16 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_17_BIT 17 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_18_BIT 18 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_19_BIT 19 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_20_BIT 20 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_21_BIT 21 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_22_BIT 22 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_23_BIT 23 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_24_BIT 24 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_25_BIT 25 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_26_BIT 26 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_27_BIT 27 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_28_BIT 28 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_29_BIT 29 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_30_BIT 30 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_31_BIT 31 + +// Asserted if there is any pending high-level interrupts on corresponding +// GPIOs. +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_FIELD_WIDTH 1 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_FIELDS_PER_REG 32 +#define GPIO_INTRPT_LVL_HIGH_STATUS_MULTIREG_COUNT 1 + +// Asserted if there is any pending high-level interrupts on corresponding +// GPIOs. +#define GPIO_INTRPT_LVL_HIGH_STATUS_REG_OFFSET 0x700 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_0_BIT 0 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_1_BIT 1 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_2_BIT 2 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_3_BIT 3 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_4_BIT 4 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_5_BIT 5 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_6_BIT 6 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_7_BIT 7 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_8_BIT 8 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_9_BIT 9 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_10_BIT 10 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_11_BIT 11 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_12_BIT 12 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_13_BIT 13 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_14_BIT 14 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_15_BIT 15 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_16_BIT 16 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_17_BIT 17 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_18_BIT 18 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_19_BIT 19 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_20_BIT 20 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_21_BIT 21 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_22_BIT 22 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_23_BIT 23 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_24_BIT 24 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_25_BIT 25 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_26_BIT 26 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_27_BIT 27 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_28_BIT 28 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_29_BIT 29 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_30_BIT 30 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_31_BIT 31 + +// Asserted if there is any pending low-level interrupts on corresponding +// GPIOs. +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_FIELD_WIDTH 1 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_FIELDS_PER_REG 32 +#define GPIO_INTRPT_LVL_LOW_STATUS_MULTIREG_COUNT 1 + +// Asserted if there is any pending low-level interrupts on corresponding +// GPIOs. +#define GPIO_INTRPT_LVL_LOW_STATUS_REG_OFFSET 0x780 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_0_BIT 0 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_1_BIT 1 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_2_BIT 2 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_3_BIT 3 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_4_BIT 4 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_5_BIT 5 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_6_BIT 6 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_7_BIT 7 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_8_BIT 8 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_9_BIT 9 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_10_BIT 10 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_11_BIT 11 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_12_BIT 12 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_13_BIT 13 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_14_BIT 14 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_15_BIT 15 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_16_BIT 16 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_17_BIT 17 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_18_BIT 18 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_19_BIT 19 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_20_BIT 20 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_21_BIT 21 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_22_BIT 22 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_23_BIT 23 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_24_BIT 24 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_25_BIT 25 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_26_BIT 26 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_27_BIT 27 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_28_BIT 28 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_29_BIT 29 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_30_BIT 30 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_31_BIT 31 + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _GPIO_REG_DEFS_ +// End generated register defines for gpio \ No newline at end of file diff --git a/hw/vendored_ips/gpio/requirements.txt b/hw/vendored_ips/gpio/requirements.txt new file mode 100644 index 00000000..1f824cb0 --- /dev/null +++ b/hw/vendored_ips/gpio/requirements.txt @@ -0,0 +1,4 @@ +hjson==3.1.0 +Mako==1.2.4 +MarkupSafe==2.1.1 +PyYAML==6.0 diff --git a/hw/vendored_ips/gpio/src/gpio.sv b/hw/vendored_ips/gpio/src/gpio.sv new file mode 100644 index 00000000..a62d76aa --- /dev/null +++ b/hw/vendored_ips/gpio/src/gpio.sv @@ -0,0 +1,288 @@ +//----------------------------------------------------------------------------- +// Title : GPIO Peripheral +//----------------------------------------------------------------------------- +// File : gpio.sv +// Author : Manuel Eggimann +// Created : 06.05.2021 +//----------------------------------------------------------------------------- +// Description : +// This Module contains a very simple but clean implementation of a GPIO +// peripheral. The is controlled through a lightweight reg_bus interface. At the +// bottom of this file there is a SV interface wrapper for the module. +//----------------------------------------------------------------------------- +// Copyright (C) 2013-2021 ETH Zurich, University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +//----------------------------------------------------------------------------- + + +`include "register_interface/typedef.svh" +`include "register_interface/assign.svh" + +`define assert_condition(cond, rst_ni) \ +assert(^cond !== 1'bx | rst_ni !== 1'b1) \ + else $error("Condition: %s = X in instance %m.", `"cond`") + +module gpio #( + /// Data width of the reg_bus + parameter int unsigned DATA_WIDTH = 32, + /// Regbus request struct type. + parameter type reg_req_t = logic, + /// Regbus response struct type. + parameter type reg_rsp_t = logic, + /// The number of GPIOs in this module. This parameter can only be changed if + /// the corresponding register file is regenerated with the same number of + /// GPIOs. The module will error out during elaboration if the given parameter + /// does not match the number of defined GPIOs in the register file. + localparam int unsigned NrGPIOs = gpio_reg_pkg::GPIOCount +) ( + /// Primary input clock. The control interface is suposed to be synchronous to + /// this clock. + input logic clk_i, + /// Asynchronous active-low reset + input logic rst_ni, + /// GPIO input signals from IO Pads (Pad -> SoC) signal. + input logic [NrGPIOs-1:0] gpio_in, + /// GPIO output signals to IO Pads (SoC -> Pad) signal. + output logic [NrGPIOs-1:0] gpio_out, + /// GPIO tx enable signals. This signal is supposed to control the output + /// buffer enable of the corresponding IO Pad. 0 -> RX (input), 1 -> TX (output). + output logic [NrGPIOs-1:0] gpio_tx_en_o, // 0 -> input, 1 -> output + /// Synchronized GPIO input signals. This port provides the `gpio_in` signal + /// synchronized to `clk_i`. + output logic [NrGPIOs-1:0] gpio_in_sync_o, + /// Global interrupt line. The interrupt line is asserted for one `clk_i` + /// whenever an unmasked interrupt on one of the GPIOs arrives. + output logic global_interrupt_o, + output logic [NrGPIOs-1:0] pin_level_interrupts_o, + /// Control interface request side using register_interface protocol. + input reg_req_t reg_req_i, + /// Control interface request side using register_interface protocol. + output reg_rsp_t reg_rsp_o +); + // The version number exposed via the INFO register + localparam logic [9:0] HW_VERSION = 2; + + import gpio_reg_pkg::*; + + // Internal Signals + gpio_reg2hw_t s_reg2hw; + gpio_hw2reg_t s_hw2reg; + + // Synchronized inputs + logic [NrGPIOs-1:0] s_gpio_in_sync; + + + // Individual interrupt signals + logic [NrGPIOs-1:0] s_gpio_rise_edge; + logic [NrGPIOs-1:0] s_gpio_rise_intrpt_mask; + logic [NrGPIOs-1:0] s_gpio_fall_edge; + logic [NrGPIOs-1:0] s_gpio_fall_intrpt_mask; + // for the level sensitive interrupts we can use the synchronized signal + // directly, no need for an additional signal + logic [NrGPIOs-1:0] s_gpio_high_intrpt_mask; + logic [NrGPIOs-1:0] s_gpio_low_intrpt_mask; + + logic [NrGPIOs-1:0] s_gpio_rise_intrpt; + logic [NrGPIOs-1:0] s_gpio_fall_intrpt; + logic [NrGPIOs-1:0] s_gpio_high_intrpt; + logic [NrGPIOs-1:0] s_gpio_low_intrpt; + + // Aggregated interrupts per GPIO + logic [NrGPIOs-1:0] interrupts_edges; // Aggregates new interrupts + logic [NrGPIOs-1:0] interrupts_pending; // Aggregates pending interrupts + + // Instantiate auto-generated register file + gpio_reg_top #( + .reg_req_t(reg_req_t), + .reg_rsp_t(reg_rsp_t) + ) i_reg_file ( + .clk_i, + .rst_ni, + .reg_req_i, + .reg_rsp_o, + .reg2hw(s_reg2hw), + .hw2reg(s_hw2reg), + .devmode_i(1'b1) + ); + + // Asign value to info register + assign s_hw2reg.info.version.d = HW_VERSION; + assign s_hw2reg.info.gpio_cnt.d = NrGPIOs[9:0]; + + // Mask interrupts + assign s_gpio_rise_intrpt = s_gpio_rise_edge & s_gpio_rise_intrpt_mask; + assign s_gpio_fall_intrpt = s_gpio_fall_edge & s_gpio_fall_intrpt_mask; + assign s_gpio_high_intrpt = s_gpio_in_sync & s_gpio_high_intrpt_mask; + assign s_gpio_low_intrpt = ~s_gpio_in_sync & s_gpio_low_intrpt_mask; + + // Generate combined interrupt signal that combines all enabled interrupts for + // each GPIO + assign interrupts_edges = s_gpio_rise_intrpt | s_gpio_fall_intrpt | s_gpio_high_intrpt | s_gpio_low_intrpt; + + // Aggregate all pending interrupts. Aggregation of all sticky interrupts. + assign interrupts_pending = s_reg2hw.intrpt_rise_status | s_reg2hw.intrpt_fall_status | s_reg2hw.intrpt_lvl_high_status | s_reg2hw.intrpt_lvl_low_status; + + // Assign interrupt output signal depending on inerrupt mode + assign global_interrupt_o = (s_reg2hw.cfg.glbl_intrpt_mode.q)? |interrupts_pending : |interrupts_edges; + assign pin_level_interrupts_o = (s_reg2hw.cfg.pin_lvl_intrpt_mode.q)? interrupts_pending : interrupts_edges; + + // Assign synchronized gpio inputs to external port + assign gpio_in_sync_o = s_gpio_in_sync; + + // Instantiate logic for individual gpios in blocks of DATA_WIDTH + for (genvar gpio_idx = 0; gpio_idx < NrGPIOs; gpio_idx++) begin : gen_gpios + // Instantiate synchronizer to synchronize input to sampling clock + gpio_input_stage #( + .NrSyncStages(2) + ) i_sync_gpio_input( + .clk_i, + .rst_ni, + .en_i(s_reg2hw.gpio_en[gpio_idx].q && s_reg2hw.gpio_mode[gpio_idx].q == 0), + .serial_i(gpio_in[gpio_idx]), + .r_edge_o(s_gpio_rise_edge[gpio_idx]), + .f_edge_o(s_gpio_fall_edge[gpio_idx]), + .serial_o(s_gpio_in_sync[gpio_idx]) + ); + + // Assign GPIO_IN register + assign s_hw2reg.gpio_in[gpio_idx].d= s_gpio_in_sync[gpio_idx]; + + // Control output with GPIO_OUT register + assign gpio_out[gpio_idx] = s_reg2hw.gpio_out[gpio_idx].q; + // Control gpio_tx_en_o depending on GPIO_MODE register value + always_comb begin + `assert_condition(s_reg2hw.gpio_mode[gpio_idx], rst_ni); + case (s_reg2hw.gpio_mode[gpio_idx]) + 2'b00: begin //INPUT_ONLY + gpio_tx_en_o[gpio_idx] = 1'b0; + end + 2'b01: begin //OUTPUT_ACTIVE + gpio_tx_en_o[gpio_idx] = 1'b1; + end + 2'b10: begin // OPEN_DRAIN0 + gpio_tx_en_o[gpio_idx] = s_reg2hw.gpio_out[gpio_idx].q; + end + 2'b11: begin // OPEN_DRAIN1 + gpio_tx_en_o[gpio_idx] = ~s_reg2hw.gpio_out[gpio_idx].q; + end + default: begin + gpio_tx_en_o[gpio_idx] = 1'b0; + end + endcase + end + + // Wire individual masks + assign s_gpio_rise_intrpt_mask[gpio_idx] = s_reg2hw.intrpt_rise_en[gpio_idx].q; + assign s_gpio_fall_intrpt_mask[gpio_idx] = s_reg2hw.intrpt_fall_en[gpio_idx].q; + assign s_gpio_high_intrpt_mask[gpio_idx] = s_reg2hw.intrpt_lvl_high_en[gpio_idx].q; + assign s_gpio_low_intrpt_mask[gpio_idx] = s_reg2hw.intrpt_lvl_low_en[gpio_idx].q; + + // GPIO set, clear and toggle logic + always_comb begin + unique if (s_reg2hw.gpio_set[gpio_idx].qe && s_reg2hw.gpio_set[gpio_idx].q) begin + `assert_condition(s_reg2hw.gpio_set[gpio_idx].qe && s_reg2hw.gpio_set[gpio_idx].q, rst_ni); + s_hw2reg.gpio_out[gpio_idx].d = 1'b1; + s_hw2reg.gpio_out[gpio_idx].de = 1'b1; + end else if (s_reg2hw.gpio_clear[gpio_idx].qe && s_reg2hw.gpio_clear[gpio_idx].q) begin + `assert_condition(s_reg2hw.gpio_clear[gpio_idx].qe && s_reg2hw.gpio_clear[gpio_idx].q, rst_ni); + s_hw2reg.gpio_out[gpio_idx].d = 1'b0; + s_hw2reg.gpio_out[gpio_idx].de = 1'b1; + end else if (s_reg2hw.gpio_toggle[gpio_idx].qe && s_reg2hw.gpio_toggle[gpio_idx].q) begin + `assert_condition(s_reg2hw.gpio_toggle[gpio_idx].qe && s_reg2hw.gpio_toggle[gpio_idx].q, rst_ni); + s_hw2reg.gpio_out[gpio_idx].d = ~s_reg2hw.gpio_out[gpio_idx].q; + s_hw2reg.gpio_out[gpio_idx].de = 1'b1; + end else begin + s_hw2reg.gpio_out[gpio_idx].d = s_reg2hw.gpio_out[gpio_idx].q; + s_hw2reg.gpio_out[gpio_idx].de = 1'b0; + end + end + + //Wire interrupt status registers + always_comb begin + `assert_condition({s_reg2hw.intrpt_status[gpio_idx].qe && s_reg2hw.intrpt_status[gpio_idx].q}, rst_ni); + //If we clear the aggregated, clear all individual interrupt status registers for the corresponding block of + //GPIOs + if (s_reg2hw.intrpt_status[gpio_idx].qe & (s_reg2hw.intrpt_status[gpio_idx].q == 1)) begin + s_hw2reg.intrpt_rise_status[gpio_idx].d = '0; + s_hw2reg.intrpt_rise_status[gpio_idx].de = 1'b1; + s_hw2reg.intrpt_fall_status[gpio_idx].d = '0; + s_hw2reg.intrpt_fall_status[gpio_idx].de = 1'b1; + s_hw2reg.intrpt_lvl_high_status[gpio_idx].d = '0; + s_hw2reg.intrpt_lvl_high_status[gpio_idx].de = 1'b1; + s_hw2reg.intrpt_lvl_low_status[gpio_idx].d = '0; + s_hw2reg.intrpt_lvl_low_status[gpio_idx].de = 1'b1; + end else begin + // Set new bits of the the individual status registers when an interrupt + // arrives. Only update the registers (de) if there are any new + // interrupts of the given type. + s_hw2reg.intrpt_rise_status[gpio_idx].d = s_gpio_rise_intrpt[gpio_idx] | s_reg2hw.intrpt_rise_status[gpio_idx].q; + s_hw2reg.intrpt_rise_status[gpio_idx].de = |s_gpio_rise_intrpt[gpio_idx]; + s_hw2reg.intrpt_fall_status[gpio_idx].d = s_gpio_fall_intrpt[gpio_idx] | s_reg2hw.intrpt_fall_status[gpio_idx].q; + s_hw2reg.intrpt_fall_status[gpio_idx].de = |s_gpio_fall_intrpt[gpio_idx]; + s_hw2reg.intrpt_lvl_high_status[gpio_idx].d = s_gpio_high_intrpt[gpio_idx] | s_reg2hw.intrpt_lvl_high_status[gpio_idx].q; + s_hw2reg.intrpt_lvl_high_status[gpio_idx].de = |s_gpio_high_intrpt[gpio_idx]; + s_hw2reg.intrpt_lvl_low_status[gpio_idx].d = s_gpio_low_intrpt[gpio_idx] | s_reg2hw.intrpt_lvl_low_status[gpio_idx].q; + s_hw2reg.intrpt_lvl_low_status[gpio_idx].de = |s_gpio_low_intrpt[gpio_idx]; + end + end // always_comb + assign s_hw2reg.intrpt_status[gpio_idx].d = interrupts_pending[gpio_idx]; + end +endmodule : gpio + +module gpio_intf #( + /// ADDR_WIDTH of the reg_bus interface + parameter int unsigned ADDR_WIDTH = 32, + /// DATA_WIDTH of the reg_bus interface + parameter int unsigned DATA_WIDTH = 32, + localparam int unsigned NrGPIOs = gpio_reg_pkg::GPIOCount, + localparam int unsigned STRB_WIDTH = DATA_WIDTH/8 +) ( + input logic clk_i, + input logic rst_ni, + input logic [NrGPIOs-1:0] gpio_in, + output logic [NrGPIOs-1:0] gpio_out, + output logic [NrGPIOs-1:0] gpio_tx_en_o, // 0 -> input, 1 -> output + output logic [NrGPIOs-1:0] gpio_in_sync_o, // sampled and synchronized GPIO + // input. + output logic global_interrupt_o, + output logic [NrGPIOs-1:0] pin_level_interrupts_o, + REG_BUS.in reg_bus +); + + // Define structs for reg_bus + typedef logic [ADDR_WIDTH-1:0] addr_t; + typedef logic [DATA_WIDTH-1:0] data_t; + typedef logic [STRB_WIDTH-1:0] strb_t; + `REG_BUS_TYPEDEF_ALL(reg_bus, addr_t, data_t, strb_t) + + reg_bus_req_t s_reg_req; + reg_bus_rsp_t s_reg_rsp; + + // Assign SV interface to structs + `REG_BUS_ASSIGN_TO_REQ(s_reg_req, reg_bus) + `REG_BUS_ASSIGN_FROM_RSP(reg_bus, s_reg_rsp) + + gpio #( + .reg_req_t(reg_bus_req_t), + .reg_rsp_t(reg_bus_rsp_t) + ) i_gpio ( + .clk_i, + .rst_ni, + .gpio_in, + .gpio_out, + .gpio_tx_en_o, // 0 -> input, 1 -> output + .gpio_in_sync_o, // sampled and synchronized GPIO + .global_interrupt_o, + .pin_level_interrupts_o, + .reg_req_i(s_reg_req), + .reg_rsp_o(s_reg_rsp) + ); + +endmodule : gpio_intf diff --git a/hw/vendored_ips/gpio/src/gpio_apb_wrap.sv b/hw/vendored_ips/gpio/src/gpio_apb_wrap.sv new file mode 100644 index 00000000..3729e2a8 --- /dev/null +++ b/hw/vendored_ips/gpio/src/gpio_apb_wrap.sv @@ -0,0 +1,137 @@ +//----------------------------------------------------------------------------- +// Title : GPIO APB Wrapper +//----------------------------------------------------------------------------- +// File : gpio_apb_wrap.sv +// Author : Manuel Eggimann +// Created : 06.05.2021 +//----------------------------------------------------------------------------- +// Description : +// This file provides wrappers around the GPIO peripheral with an APB +// interface. The file contains two versions of the module, one structs for the +// APB interface and one using SystemVerilog Interfaces. +//----------------------------------------------------------------------------- +// Copyright (C) 2013-2021 ETH Zurich, University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +//----------------------------------------------------------------------------- +`include "apb/typedef.svh" +`include "apb/assign.svh" + +module gpio_apb_wrap # ( + /// ADDR_WIDTH of the APB interface + parameter int unsigned ADDR_WIDTH = 32, + /// DATA_WIDTH of the APB interface + parameter int unsigned DATA_WIDTH = 32, + /// APB request struct type. + parameter type apb_req_t = logic, + /// APB response struct type. + parameter type apb_rsp_t = logic, + localparam int unsigned NrGPIOs = gpio_reg_pkg::GPIOCount, + localparam int unsigned STRB_WIDTH = DATA_WIDTH/8 +)( + input logic clk_i, + input logic rst_ni, + input logic [NrGPIOs-1:0] gpio_in, + output logic [NrGPIOs-1:0] gpio_out, + output logic [NrGPIOs-1:0] gpio_tx_en_o, // 0 -> input, 1 -> output + output logic [NrGPIOs-1:0] gpio_in_sync_o, // sampled and synchronized GPIO + // input. + output logic global_interrupt_o, + output logic [NrGPIOs-1:0] pin_level_interrupts_o, + input apb_req_t apb_req_i, + output apb_rsp_t apb_rsp_o +); + + // Convert APB to reg_bus + REG_BUS #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(DATA_WIDTH)) s_reg_bus(.clk_i); + apb_to_reg i_abp_to_reg ( + .clk_i, + .rst_ni, + .penable_i ( apb_req_i.penable ), + .pwrite_i ( apb_req_i.pwrite ), + .paddr_i ( apb_req_i.paddr ), + .psel_i ( apb_req_i.psel ), + .pwdata_i ( apb_req_i.pwdata ), + .prdata_o ( apb_rsp_o.prdata ), + .pready_o ( apb_rsp_o.pready ), + .pslverr_o ( apb_rsp_o.pslverr ), + .reg_o ( s_reg_bus ) + ); + + gpio_intf #( + .ADDR_WIDTH ( ADDR_WIDTH ), + .DATA_WIDTH ( DATA_WIDTH ) + ) i_gpio ( + .clk_i, + .rst_ni, + .gpio_in, + .gpio_out, + .gpio_tx_en_o, + .gpio_in_sync_o, + .global_interrupt_o, + .pin_level_interrupts_o, + .reg_bus(s_reg_bus) + ); +endmodule // gpio_apb_wrap + + +module gpio_apb_wrap_intf # ( + /// ADDR_WIDTH of the APB interface + parameter int unsigned ADDR_WIDTH = 32, + /// DATA_WIDTH of the APB interface + parameter int unsigned DATA_WIDTH = 32, + localparam int unsigned NrGPIOs = gpio_reg_pkg::GPIOCount, + localparam int unsigned STRB_WIDTH = DATA_WIDTH/8 +)( + input logic clk_i, + input logic rst_ni, + input logic [NrGPIOs-1:0] gpio_in, + output logic [NrGPIOs-1:0] gpio_out, + output logic [NrGPIOs-1:0] gpio_tx_en_o, // 0 -> input, 1 -> output + output logic [NrGPIOs-1:0] gpio_in_sync_o, // sampled and synchronized GPIO + // input. + output logic global_interrupt_o, + output logic [NrGPIOs-1:0] pin_level_interrupts_o, + APB.Slave apb_slave +); + + // Convert SV Interface to structs + typedef logic [ADDR_WIDTH-1:0] addr_t; + typedef logic [DATA_WIDTH-1:0] data_t; + typedef logic [DATA_WIDTH/8-1:0] strb_t; // The APB bus interface only + // supports 8-bit strobe so we don't need to + // check the strobe width of the intput bus. + `APB_TYPEDEF_REQ_T(apb_req_t, addr_t, data_t, strb_t) + `APB_TYPEDEF_RESP_T(apb_rsp_t, data_t) + + apb_req_t s_apb_req; + apb_rsp_t s_apb_rsp; + + `APB_ASSIGN_TO_REQ(s_apb_req, apb_slave) + `APB_ASSIGN_FROM_RESP(apb_slave, s_apb_rsp) + + gpio_apb_wrap #( + .ADDR_WIDTH ( ADDR_WIDTH ), + .DATA_WIDTH ( DATA_WIDTH ), + .apb_req_t ( apb_req_t ), + .apb_rsp_t ( apb_rsp_t ) + ) i_gpio_apb_wrap ( + .clk_i, + .rst_ni, + .gpio_in, + .gpio_out, + .gpio_tx_en_o, + .gpio_in_sync_o, + .global_interrupt_o, + .pin_level_interrupts_o, + .apb_req_i ( s_apb_req ), + .apb_rsp_o ( s_apb_rsp ) + ); + +endmodule diff --git a/hw/vendored_ips/gpio/src/gpio_axi_lite_wrap.sv b/hw/vendored_ips/gpio/src/gpio_axi_lite_wrap.sv new file mode 100644 index 00000000..904e6530 --- /dev/null +++ b/hw/vendored_ips/gpio/src/gpio_axi_lite_wrap.sv @@ -0,0 +1,162 @@ +//----------------------------------------------------------------------------- +// Title : GPIO AXI Lite Wrapper +//----------------------------------------------------------------------------- +// File : gpio_axi_lite_wrap.sv +// Author : Manuel Eggimann +// Created : 06.05.2021 +//----------------------------------------------------------------------------- +// Description : +// This file provides a wrapper around the GPIO peripheral with an AXI4-lite +// interface. The file contains two versions of the module, one structs for the +// AXI-lite interface and one using SystemVerilog Interfaces. +//----------------------------------------------------------------------------- +// Copyright (C) 2013-2021 ETH Zurich, University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +//----------------------------------------------------------------------------- + + +`include "register_interface/typedef.svh" +`include "register_interface/assign.svh" +`include "axi/typedef.svh" +`include "axi/assign.svh" + +module gpio_axi_lite_wrap # ( + /// ADDR_WIDTH of the AXI lite interface + parameter int unsigned ADDR_WIDTH = 32, + /// DATA_WIDTH of the AXI lite interface + parameter int unsigned DATA_WIDTH = 32, + /// Whether the AXI-Lite W channel should be decoupled with a register. This + /// can help break long paths at the expense of registers. + parameter bit DECOUPLE_W = 1, + /// AXI-Lite request struct type. + parameter type axi_lite_req_t = logic, + /// AXI-Lite response struct type. + parameter type axi_lite_rsp_t = logic, + localparam int unsigned NrGPIOs = gpio_reg_pkg::GPIOCount, + localparam int unsigned STRB_WIDTH = DATA_WIDTH/8 +)( + input logic clk_i, + input logic rst_ni, + input logic [NrGPIOs-1:0] gpio_in, + output logic [NrGPIOs-1:0] gpio_out, + output logic [NrGPIOs-1:0] gpio_tx_en_o, // 0 -> input, 1 -> output + output logic [NrGPIOs-1:0] gpio_in_sync_o, // sampled and synchronized GPIO + // input. + output logic global_interrupt_o, + output logic [NrGPIOs-1:0] pin_level_interrupts_o, + input axi_lite_req_t axi_lite_req_i, + output axi_lite_rsp_t axi_lite_rsp_o +); + + if (STRB_WIDTH != DATA_WIDTH/8) + $error("Unsupported AXI strobe width (%d) The underlying register bus protocol does not support strobe widths other than 8-bit.", STRB_WIDTH); + + typedef logic [ADDR_WIDTH-1:0] addr_t; + typedef logic [DATA_WIDTH-1:0] data_t; + typedef logic [STRB_WIDTH-1:0] strb_t; + `REG_BUS_TYPEDEF_ALL(reg_bus, addr_t, data_t, strb_t) + + reg_bus_req_t s_reg_req; + reg_bus_rsp_t s_reg_rsp; + + axi_lite_to_reg #( + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .BUFFER_DEPTH(1), + .DECOUPLE_W(0), + .axi_lite_req_t(axi_lite_req_t), + .axi_lite_rsp_t(axi_lite_rsp_t), + .reg_req_t(reg_bus_req_t), + .reg_rsp_t(reg_bus_rsp_t) + ) i_axi_lite_to_reg ( + .clk_i, + .rst_ni, + .axi_lite_req_i, + .axi_lite_rsp_o, + .reg_req_o(s_reg_req), + .reg_rsp_i(s_reg_rsp) + ); + + + gpio #( + .DATA_WIDTH ( DATA_WIDTH ), + .reg_req_t ( reg_bus_req_t ), + .reg_rsp_t ( reg_bus_rsp_t ) + ) i_gpio ( + .clk_i, + .rst_ni, + .gpio_in, + .gpio_out, + .gpio_tx_en_o, + .gpio_in_sync_o, + .global_interrupt_o, + .pin_level_interrupts_o, + .reg_req_i ( s_reg_req ), + .reg_rsp_o ( s_reg_rsp ) + ); + +endmodule + +module gpio_axi_lite_wrap_intf # ( + /// ADDR_WIDTH of the AXI lite interface + parameter int unsigned ADDR_WIDTH = 32, + /// DATA_WIDTH of the AXI lite interface + parameter int unsigned DATA_WIDTH = 32, + /// Whether the AXI-Lite W channel should be decoupled with a register. This + /// can help break long paths at the expense of registers. + parameter bit DECOUPLE_W = 1, + localparam int unsigned NrGPIOs = gpio_reg_pkg::GPIOCount, + localparam int unsigned STRB_WIDTH = DATA_WIDTH/8 +)( + input logic clk_i, + input logic rst_ni, + input logic [NrGPIOs-1:0] gpio_in, + output logic [NrGPIOs-1:0] gpio_out, + output logic [NrGPIOs-1:0] gpio_tx_en_o, // 0 -> input, 1 -> output + output logic [NrGPIOs-1:0] gpio_in_sync_o, // sampled and synchronized GPIO + // input. + output logic global_interrupt_o, + output logic [NrGPIOs-1:0] pin_level_interrupts_o, + AXI_LITE.Slave axi_i +); + + // Convert SV interface to structs + // Declare axi_lite structs + typedef logic [ADDR_WIDTH-1:0] addr_t; + typedef logic [DATA_WIDTH-1:0] data_t; + typedef logic [STRB_WIDTH-1:0] strb_t; + `AXI_LITE_TYPEDEF_ALL(axi_lite, addr_t, data_t, strb_t) + // Declare axi_lit struct signals + axi_lite_req_t s_axi_lite_req; + axi_lite_resp_t s_axi_lite_rsp; + // Connect SV interface to structs + `AXI_LITE_ASSIGN_TO_REQ(s_axi_lite_req, axi_i) + `AXI_LITE_ASSIGN_FROM_RESP(axi_i, s_axi_lite_rsp) + + gpio_axi_lite_wrap #( + .ADDR_WIDTH ( ADDR_WIDTH ), + .DATA_WIDTH ( DATA_WIDTH ), + .DECOUPLE_W ( DECOUPLE_W ), + .axi_lite_req_t ( axi_lite_req_t ), + .axi_lite_rsp_t ( axi_lite_resp_t ) + ) i_gpio_axi_lite_wrap ( + .clk_i, + .rst_ni, + .gpio_in, + .gpio_out, + .gpio_tx_en_o, + .gpio_in_sync_o, + .global_interrupt_o, + .pin_level_interrupts_o, + .axi_lite_req_i ( s_axi_lite_req ), + .axi_lite_rsp_o ( s_axi_lite_rsp ) + ); + +endmodule diff --git a/hw/vendored_ips/gpio/src/gpio_input_stage.sv b/hw/vendored_ips/gpio/src/gpio_input_stage.sv new file mode 100644 index 00000000..e79143db --- /dev/null +++ b/hw/vendored_ips/gpio/src/gpio_input_stage.sv @@ -0,0 +1,81 @@ +//----------------------------------------------------------------------------- +// Title : GPIO Input Stage +//----------------------------------------------------------------------------- +// File : gpio_input_stage.sv +// Author : Manuel Eggimann +// Created : 14.04.2022 +//----------------------------------------------------------------------------- +// Description : +// +// This module implements the input synchronization stage for a single GPIO. It +// uses a two-stage synchronizer for meta-stability resolution. This version of +// the input stage instantiates a clock gate to disable input sampling when the +// corresponding GPIO is disabled. This clock gate instance (tc_clk_gating) is +// behavioraly implemented in the `pulp-plaform/common_cells` (on GitHub) +// repository. In case you want to tape-out this GPIO, you either have to map +// this behavioral clock gate cell to a dedicated ICG of your std cell library +// or use the alternative version (`gpio_input_stage_no_clk_gates.sv`) of the +// input stage that does not include any clock gates. +// +//----------------------------------------------------------------------------- +// Copyright (C) 2022 ETH Zurich, University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// SPDX-License-Identifier: SHL-0.51 +//----------------------------------------------------------------------------- + + +module gpio_input_stage #( + parameter NrSyncStages=2 +) ( + input logic clk_i, + input logic rst_ni, + input logic en_i, + input logic serial_i, + output logic r_edge_o, + output logic f_edge_o, + output logic serial_o +); + + logic clk; + logic serial, serial_q; + + assign serial_o = serial_q; + assign f_edge_o = (~serial) & serial_q; + assign r_edge_o = serial & (~serial_q); + + tc_clk_gating #( + .IS_FUNCTIONAL(0) // The clock gate is not required for proper + // functionality. Just for power saving. + ) i_clk_gate ( + .clk_i, + .en_i, + .test_en_i ( 1'b0 ), + .clk_o ( clk ) + ); + + sync #( + .STAGES (NrSyncStages) + ) i_sync ( + .clk_i(clk), + .rst_ni, + .serial_i, + .serial_o ( serial ) + ); + + always_ff @(posedge clk, negedge rst_ni) begin + if (!rst_ni) begin + serial_q <= 1'b0; + end else begin + serial_q <= serial; + end + end + + +endmodule : gpio_input_stage diff --git a/hw/vendored_ips/gpio/src/gpio_input_stage_no_clk_gates.sv b/hw/vendored_ips/gpio/src/gpio_input_stage_no_clk_gates.sv new file mode 100644 index 00000000..b73f5ab8 --- /dev/null +++ b/hw/vendored_ips/gpio/src/gpio_input_stage_no_clk_gates.sv @@ -0,0 +1,39 @@ +module gpio_input_stage #( + parameter NrSyncStages=2 +) ( + input logic clk_i, + input logic rst_ni, + input logic en_i, + input logic serial_i, + output logic r_edge_o, + output logic f_edge_o, + output logic serial_o +); + + logic serial, serial_q; + + assign serial_o = serial_q; + assign f_edge_o = (~serial) & serial_q; + assign r_edge_o = serial & (~serial_q); + + sync #( + .STAGES (NrSyncStages) + ) i_sync ( + .clk_i(clk_i), + .rst_ni, + .serial_i, + .serial_o ( serial ) + ); + + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin + serial_q <= 1'b0; + end else begin + if (en_i) begin + serial_q <= serial; + end + end + end + + +endmodule : gpio_input_stage diff --git a/hw/vendored_ips/gpio/src/gpio_reg_pkg.sv b/hw/vendored_ips/gpio/src/gpio_reg_pkg.sv new file mode 100644 index 00000000..310850d9 --- /dev/null +++ b/hw/vendored_ips/gpio/src/gpio_reg_pkg.sv @@ -0,0 +1,243 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package gpio_reg_pkg; + + // Param list + parameter int GPIOCount = 32; + + // Address widths within the block + parameter int BlockAw = 11; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + struct packed { + logic q; + } glbl_intrpt_mode; + struct packed { + logic q; + } pin_lvl_intrpt_mode; + } gpio_reg2hw_cfg_reg_t; + + typedef struct packed { + logic [1:0] q; + } gpio_reg2hw_gpio_mode_mreg_t; + + typedef struct packed { + logic q; + } gpio_reg2hw_gpio_en_mreg_t; + + typedef struct packed { + logic q; + } gpio_reg2hw_gpio_out_mreg_t; + + typedef struct packed { + logic q; + logic qe; + } gpio_reg2hw_gpio_set_mreg_t; + + typedef struct packed { + logic q; + logic qe; + } gpio_reg2hw_gpio_clear_mreg_t; + + typedef struct packed { + logic q; + logic qe; + } gpio_reg2hw_gpio_toggle_mreg_t; + + typedef struct packed { + logic q; + } gpio_reg2hw_intrpt_rise_en_mreg_t; + + typedef struct packed { + logic q; + } gpio_reg2hw_intrpt_fall_en_mreg_t; + + typedef struct packed { + logic q; + } gpio_reg2hw_intrpt_lvl_high_en_mreg_t; + + typedef struct packed { + logic q; + } gpio_reg2hw_intrpt_lvl_low_en_mreg_t; + + typedef struct packed { + logic q; + logic qe; + } gpio_reg2hw_intrpt_status_mreg_t; + + typedef struct packed { + logic q; + } gpio_reg2hw_intrpt_rise_status_mreg_t; + + typedef struct packed { + logic q; + } gpio_reg2hw_intrpt_fall_status_mreg_t; + + typedef struct packed { + logic q; + } gpio_reg2hw_intrpt_lvl_high_status_mreg_t; + + typedef struct packed { + logic q; + } gpio_reg2hw_intrpt_lvl_low_status_mreg_t; + + typedef struct packed { + struct packed { + logic [9:0] d; + } gpio_cnt; + struct packed { + logic [9:0] d; + } version; + } gpio_hw2reg_info_reg_t; + + typedef struct packed { + logic d; + } gpio_hw2reg_gpio_in_mreg_t; + + typedef struct packed { + logic d; + logic de; + } gpio_hw2reg_gpio_out_mreg_t; + + typedef struct packed { + logic d; + } gpio_hw2reg_intrpt_status_mreg_t; + + typedef struct packed { + logic d; + logic de; + } gpio_hw2reg_intrpt_rise_status_mreg_t; + + typedef struct packed { + logic d; + logic de; + } gpio_hw2reg_intrpt_fall_status_mreg_t; + + typedef struct packed { + logic d; + logic de; + } gpio_hw2reg_intrpt_lvl_high_status_mreg_t; + + typedef struct packed { + logic d; + logic de; + } gpio_hw2reg_intrpt_lvl_low_status_mreg_t; + + // Register -> HW type + typedef struct packed { + gpio_reg2hw_cfg_reg_t cfg; // [641:640] + gpio_reg2hw_gpio_mode_mreg_t [31:0] gpio_mode; // [639:576] + gpio_reg2hw_gpio_en_mreg_t [31:0] gpio_en; // [575:544] + gpio_reg2hw_gpio_out_mreg_t [31:0] gpio_out; // [543:512] + gpio_reg2hw_gpio_set_mreg_t [31:0] gpio_set; // [511:448] + gpio_reg2hw_gpio_clear_mreg_t [31:0] gpio_clear; // [447:384] + gpio_reg2hw_gpio_toggle_mreg_t [31:0] gpio_toggle; // [383:320] + gpio_reg2hw_intrpt_rise_en_mreg_t [31:0] intrpt_rise_en; // [319:288] + gpio_reg2hw_intrpt_fall_en_mreg_t [31:0] intrpt_fall_en; // [287:256] + gpio_reg2hw_intrpt_lvl_high_en_mreg_t [31:0] intrpt_lvl_high_en; // [255:224] + gpio_reg2hw_intrpt_lvl_low_en_mreg_t [31:0] intrpt_lvl_low_en; // [223:192] + gpio_reg2hw_intrpt_status_mreg_t [31:0] intrpt_status; // [191:128] + gpio_reg2hw_intrpt_rise_status_mreg_t [31:0] intrpt_rise_status; // [127:96] + gpio_reg2hw_intrpt_fall_status_mreg_t [31:0] intrpt_fall_status; // [95:64] + gpio_reg2hw_intrpt_lvl_high_status_mreg_t [31:0] intrpt_lvl_high_status; // [63:32] + gpio_reg2hw_intrpt_lvl_low_status_mreg_t [31:0] intrpt_lvl_low_status; // [31:0] + } gpio_reg2hw_t; + + // HW -> register type + typedef struct packed { + gpio_hw2reg_info_reg_t info; // [403:384] + gpio_hw2reg_gpio_in_mreg_t [31:0] gpio_in; // [383:352] + gpio_hw2reg_gpio_out_mreg_t [31:0] gpio_out; // [351:288] + gpio_hw2reg_intrpt_status_mreg_t [31:0] intrpt_status; // [287:256] + gpio_hw2reg_intrpt_rise_status_mreg_t [31:0] intrpt_rise_status; // [255:192] + gpio_hw2reg_intrpt_fall_status_mreg_t [31:0] intrpt_fall_status; // [191:128] + gpio_hw2reg_intrpt_lvl_high_status_mreg_t [31:0] intrpt_lvl_high_status; // [127:64] + gpio_hw2reg_intrpt_lvl_low_status_mreg_t [31:0] intrpt_lvl_low_status; // [63:0] + } gpio_hw2reg_t; + + // Register offsets + parameter logic [BlockAw-1:0] GPIO_INFO_OFFSET = 11'h 0; + parameter logic [BlockAw-1:0] GPIO_CFG_OFFSET = 11'h 4; + parameter logic [BlockAw-1:0] GPIO_GPIO_MODE_0_OFFSET = 11'h 8; + parameter logic [BlockAw-1:0] GPIO_GPIO_MODE_1_OFFSET = 11'h c; + parameter logic [BlockAw-1:0] GPIO_GPIO_EN_OFFSET = 11'h 80; + parameter logic [BlockAw-1:0] GPIO_GPIO_IN_OFFSET = 11'h 100; + parameter logic [BlockAw-1:0] GPIO_GPIO_OUT_OFFSET = 11'h 180; + parameter logic [BlockAw-1:0] GPIO_GPIO_SET_OFFSET = 11'h 200; + parameter logic [BlockAw-1:0] GPIO_GPIO_CLEAR_OFFSET = 11'h 280; + parameter logic [BlockAw-1:0] GPIO_GPIO_TOGGLE_OFFSET = 11'h 300; + parameter logic [BlockAw-1:0] GPIO_INTRPT_RISE_EN_OFFSET = 11'h 380; + parameter logic [BlockAw-1:0] GPIO_INTRPT_FALL_EN_OFFSET = 11'h 400; + parameter logic [BlockAw-1:0] GPIO_INTRPT_LVL_HIGH_EN_OFFSET = 11'h 480; + parameter logic [BlockAw-1:0] GPIO_INTRPT_LVL_LOW_EN_OFFSET = 11'h 500; + parameter logic [BlockAw-1:0] GPIO_INTRPT_STATUS_OFFSET = 11'h 580; + parameter logic [BlockAw-1:0] GPIO_INTRPT_RISE_STATUS_OFFSET = 11'h 600; + parameter logic [BlockAw-1:0] GPIO_INTRPT_FALL_STATUS_OFFSET = 11'h 680; + parameter logic [BlockAw-1:0] GPIO_INTRPT_LVL_HIGH_STATUS_OFFSET = 11'h 700; + parameter logic [BlockAw-1:0] GPIO_INTRPT_LVL_LOW_STATUS_OFFSET = 11'h 780; + + // Reset values for hwext registers and their fields + parameter logic [19:0] GPIO_INFO_RESVAL = 20'h 800; + parameter logic [9:0] GPIO_INFO_VERSION_RESVAL = 10'h 2; + parameter logic [31:0] GPIO_GPIO_IN_RESVAL = 32'h 0; + parameter logic [31:0] GPIO_GPIO_SET_RESVAL = 32'h 0; + parameter logic [31:0] GPIO_GPIO_CLEAR_RESVAL = 32'h 0; + parameter logic [31:0] GPIO_GPIO_TOGGLE_RESVAL = 32'h 0; + parameter logic [31:0] GPIO_INTRPT_STATUS_RESVAL = 32'h 0; + + // Register index + typedef enum int { + GPIO_INFO, + GPIO_CFG, + GPIO_GPIO_MODE_0, + GPIO_GPIO_MODE_1, + GPIO_GPIO_EN, + GPIO_GPIO_IN, + GPIO_GPIO_OUT, + GPIO_GPIO_SET, + GPIO_GPIO_CLEAR, + GPIO_GPIO_TOGGLE, + GPIO_INTRPT_RISE_EN, + GPIO_INTRPT_FALL_EN, + GPIO_INTRPT_LVL_HIGH_EN, + GPIO_INTRPT_LVL_LOW_EN, + GPIO_INTRPT_STATUS, + GPIO_INTRPT_RISE_STATUS, + GPIO_INTRPT_FALL_STATUS, + GPIO_INTRPT_LVL_HIGH_STATUS, + GPIO_INTRPT_LVL_LOW_STATUS + } gpio_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] GPIO_PERMIT [19] = '{ + 4'b 0111, // index[ 0] GPIO_INFO + 4'b 0001, // index[ 1] GPIO_CFG + 4'b 1111, // index[ 2] GPIO_GPIO_MODE_0 + 4'b 1111, // index[ 3] GPIO_GPIO_MODE_1 + 4'b 1111, // index[ 4] GPIO_GPIO_EN + 4'b 1111, // index[ 5] GPIO_GPIO_IN + 4'b 1111, // index[ 6] GPIO_GPIO_OUT + 4'b 1111, // index[ 7] GPIO_GPIO_SET + 4'b 1111, // index[ 8] GPIO_GPIO_CLEAR + 4'b 1111, // index[ 9] GPIO_GPIO_TOGGLE + 4'b 1111, // index[10] GPIO_INTRPT_RISE_EN + 4'b 1111, // index[11] GPIO_INTRPT_FALL_EN + 4'b 1111, // index[12] GPIO_INTRPT_LVL_HIGH_EN + 4'b 1111, // index[13] GPIO_INTRPT_LVL_LOW_EN + 4'b 1111, // index[14] GPIO_INTRPT_STATUS + 4'b 1111, // index[15] GPIO_INTRPT_RISE_STATUS + 4'b 1111, // index[16] GPIO_INTRPT_FALL_STATUS + 4'b 1111, // index[17] GPIO_INTRPT_LVL_HIGH_STATUS + 4'b 1111 // index[18] GPIO_INTRPT_LVL_LOW_STATUS + }; + +endpackage + diff --git a/hw/vendored_ips/gpio/src/gpio_reg_top.sv b/hw/vendored_ips/gpio/src/gpio_reg_top.sv new file mode 100644 index 00000000..c0ba07b0 --- /dev/null +++ b/hw/vendored_ips/gpio/src/gpio_reg_top.sv @@ -0,0 +1,15489 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + + +`include "common_cells/assertions.svh" + +module gpio_reg_top #( + parameter type reg_req_t = logic, + parameter type reg_rsp_t = logic, + parameter int AW = 11 +) ( + input logic clk_i, + input logic rst_ni, + input reg_req_t reg_req_i, + output reg_rsp_t reg_rsp_o, + // To HW + output gpio_reg_pkg::gpio_reg2hw_t reg2hw, // Write + input gpio_reg_pkg::gpio_hw2reg_t hw2reg, // Read + + + // Config + input devmode_i // If 1, explicit error return for unmapped register access +); + + import gpio_reg_pkg::* ; + + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + + // Below register interface can be changed + reg_req_t reg_intf_req; + reg_rsp_t reg_intf_rsp; + + + assign reg_intf_req = reg_req_i; + assign reg_rsp_o = reg_intf_rsp; + + + assign reg_we = reg_intf_req.valid & reg_intf_req.write; + assign reg_re = reg_intf_req.valid & ~reg_intf_req.write; + assign reg_addr = reg_intf_req.addr; + assign reg_wdata = reg_intf_req.wdata; + assign reg_be = reg_intf_req.wstrb; + assign reg_intf_rsp.rdata = reg_rdata; + assign reg_intf_rsp.error = reg_error; + assign reg_intf_rsp.ready = 1'b1; + + assign reg_rdata = reg_rdata_next ; + assign reg_error = (devmode_i & addrmiss) | wr_err; + + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic [9:0] info_gpio_cnt_qs; + logic info_gpio_cnt_re; + logic [9:0] info_version_qs; + logic info_version_re; + logic cfg_glbl_intrpt_mode_qs; + logic cfg_glbl_intrpt_mode_wd; + logic cfg_glbl_intrpt_mode_we; + logic cfg_pin_lvl_intrpt_mode_qs; + logic cfg_pin_lvl_intrpt_mode_wd; + logic cfg_pin_lvl_intrpt_mode_we; + logic [1:0] gpio_mode_0_mode_0_qs; + logic [1:0] gpio_mode_0_mode_0_wd; + logic gpio_mode_0_mode_0_we; + logic [1:0] gpio_mode_0_mode_1_qs; + logic [1:0] gpio_mode_0_mode_1_wd; + logic gpio_mode_0_mode_1_we; + logic [1:0] gpio_mode_0_mode_2_qs; + logic [1:0] gpio_mode_0_mode_2_wd; + logic gpio_mode_0_mode_2_we; + logic [1:0] gpio_mode_0_mode_3_qs; + logic [1:0] gpio_mode_0_mode_3_wd; + logic gpio_mode_0_mode_3_we; + logic [1:0] gpio_mode_0_mode_4_qs; + logic [1:0] gpio_mode_0_mode_4_wd; + logic gpio_mode_0_mode_4_we; + logic [1:0] gpio_mode_0_mode_5_qs; + logic [1:0] gpio_mode_0_mode_5_wd; + logic gpio_mode_0_mode_5_we; + logic [1:0] gpio_mode_0_mode_6_qs; + logic [1:0] gpio_mode_0_mode_6_wd; + logic gpio_mode_0_mode_6_we; + logic [1:0] gpio_mode_0_mode_7_qs; + logic [1:0] gpio_mode_0_mode_7_wd; + logic gpio_mode_0_mode_7_we; + logic [1:0] gpio_mode_0_mode_8_qs; + logic [1:0] gpio_mode_0_mode_8_wd; + logic gpio_mode_0_mode_8_we; + logic [1:0] gpio_mode_0_mode_9_qs; + logic [1:0] gpio_mode_0_mode_9_wd; + logic gpio_mode_0_mode_9_we; + logic [1:0] gpio_mode_0_mode_10_qs; + logic [1:0] gpio_mode_0_mode_10_wd; + logic gpio_mode_0_mode_10_we; + logic [1:0] gpio_mode_0_mode_11_qs; + logic [1:0] gpio_mode_0_mode_11_wd; + logic gpio_mode_0_mode_11_we; + logic [1:0] gpio_mode_0_mode_12_qs; + logic [1:0] gpio_mode_0_mode_12_wd; + logic gpio_mode_0_mode_12_we; + logic [1:0] gpio_mode_0_mode_13_qs; + logic [1:0] gpio_mode_0_mode_13_wd; + logic gpio_mode_0_mode_13_we; + logic [1:0] gpio_mode_0_mode_14_qs; + logic [1:0] gpio_mode_0_mode_14_wd; + logic gpio_mode_0_mode_14_we; + logic [1:0] gpio_mode_0_mode_15_qs; + logic [1:0] gpio_mode_0_mode_15_wd; + logic gpio_mode_0_mode_15_we; + logic [1:0] gpio_mode_1_mode_16_qs; + logic [1:0] gpio_mode_1_mode_16_wd; + logic gpio_mode_1_mode_16_we; + logic [1:0] gpio_mode_1_mode_17_qs; + logic [1:0] gpio_mode_1_mode_17_wd; + logic gpio_mode_1_mode_17_we; + logic [1:0] gpio_mode_1_mode_18_qs; + logic [1:0] gpio_mode_1_mode_18_wd; + logic gpio_mode_1_mode_18_we; + logic [1:0] gpio_mode_1_mode_19_qs; + logic [1:0] gpio_mode_1_mode_19_wd; + logic gpio_mode_1_mode_19_we; + logic [1:0] gpio_mode_1_mode_20_qs; + logic [1:0] gpio_mode_1_mode_20_wd; + logic gpio_mode_1_mode_20_we; + logic [1:0] gpio_mode_1_mode_21_qs; + logic [1:0] gpio_mode_1_mode_21_wd; + logic gpio_mode_1_mode_21_we; + logic [1:0] gpio_mode_1_mode_22_qs; + logic [1:0] gpio_mode_1_mode_22_wd; + logic gpio_mode_1_mode_22_we; + logic [1:0] gpio_mode_1_mode_23_qs; + logic [1:0] gpio_mode_1_mode_23_wd; + logic gpio_mode_1_mode_23_we; + logic [1:0] gpio_mode_1_mode_24_qs; + logic [1:0] gpio_mode_1_mode_24_wd; + logic gpio_mode_1_mode_24_we; + logic [1:0] gpio_mode_1_mode_25_qs; + logic [1:0] gpio_mode_1_mode_25_wd; + logic gpio_mode_1_mode_25_we; + logic [1:0] gpio_mode_1_mode_26_qs; + logic [1:0] gpio_mode_1_mode_26_wd; + logic gpio_mode_1_mode_26_we; + logic [1:0] gpio_mode_1_mode_27_qs; + logic [1:0] gpio_mode_1_mode_27_wd; + logic gpio_mode_1_mode_27_we; + logic [1:0] gpio_mode_1_mode_28_qs; + logic [1:0] gpio_mode_1_mode_28_wd; + logic gpio_mode_1_mode_28_we; + logic [1:0] gpio_mode_1_mode_29_qs; + logic [1:0] gpio_mode_1_mode_29_wd; + logic gpio_mode_1_mode_29_we; + logic [1:0] gpio_mode_1_mode_30_qs; + logic [1:0] gpio_mode_1_mode_30_wd; + logic gpio_mode_1_mode_30_we; + logic [1:0] gpio_mode_1_mode_31_qs; + logic [1:0] gpio_mode_1_mode_31_wd; + logic gpio_mode_1_mode_31_we; + logic gpio_en_gpio_en_0_qs; + logic gpio_en_gpio_en_0_wd; + logic gpio_en_gpio_en_0_we; + logic gpio_en_gpio_en_1_qs; + logic gpio_en_gpio_en_1_wd; + logic gpio_en_gpio_en_1_we; + logic gpio_en_gpio_en_2_qs; + logic gpio_en_gpio_en_2_wd; + logic gpio_en_gpio_en_2_we; + logic gpio_en_gpio_en_3_qs; + logic gpio_en_gpio_en_3_wd; + logic gpio_en_gpio_en_3_we; + logic gpio_en_gpio_en_4_qs; + logic gpio_en_gpio_en_4_wd; + logic gpio_en_gpio_en_4_we; + logic gpio_en_gpio_en_5_qs; + logic gpio_en_gpio_en_5_wd; + logic gpio_en_gpio_en_5_we; + logic gpio_en_gpio_en_6_qs; + logic gpio_en_gpio_en_6_wd; + logic gpio_en_gpio_en_6_we; + logic gpio_en_gpio_en_7_qs; + logic gpio_en_gpio_en_7_wd; + logic gpio_en_gpio_en_7_we; + logic gpio_en_gpio_en_8_qs; + logic gpio_en_gpio_en_8_wd; + logic gpio_en_gpio_en_8_we; + logic gpio_en_gpio_en_9_qs; + logic gpio_en_gpio_en_9_wd; + logic gpio_en_gpio_en_9_we; + logic gpio_en_gpio_en_10_qs; + logic gpio_en_gpio_en_10_wd; + logic gpio_en_gpio_en_10_we; + logic gpio_en_gpio_en_11_qs; + logic gpio_en_gpio_en_11_wd; + logic gpio_en_gpio_en_11_we; + logic gpio_en_gpio_en_12_qs; + logic gpio_en_gpio_en_12_wd; + logic gpio_en_gpio_en_12_we; + logic gpio_en_gpio_en_13_qs; + logic gpio_en_gpio_en_13_wd; + logic gpio_en_gpio_en_13_we; + logic gpio_en_gpio_en_14_qs; + logic gpio_en_gpio_en_14_wd; + logic gpio_en_gpio_en_14_we; + logic gpio_en_gpio_en_15_qs; + logic gpio_en_gpio_en_15_wd; + logic gpio_en_gpio_en_15_we; + logic gpio_en_gpio_en_16_qs; + logic gpio_en_gpio_en_16_wd; + logic gpio_en_gpio_en_16_we; + logic gpio_en_gpio_en_17_qs; + logic gpio_en_gpio_en_17_wd; + logic gpio_en_gpio_en_17_we; + logic gpio_en_gpio_en_18_qs; + logic gpio_en_gpio_en_18_wd; + logic gpio_en_gpio_en_18_we; + logic gpio_en_gpio_en_19_qs; + logic gpio_en_gpio_en_19_wd; + logic gpio_en_gpio_en_19_we; + logic gpio_en_gpio_en_20_qs; + logic gpio_en_gpio_en_20_wd; + logic gpio_en_gpio_en_20_we; + logic gpio_en_gpio_en_21_qs; + logic gpio_en_gpio_en_21_wd; + logic gpio_en_gpio_en_21_we; + logic gpio_en_gpio_en_22_qs; + logic gpio_en_gpio_en_22_wd; + logic gpio_en_gpio_en_22_we; + logic gpio_en_gpio_en_23_qs; + logic gpio_en_gpio_en_23_wd; + logic gpio_en_gpio_en_23_we; + logic gpio_en_gpio_en_24_qs; + logic gpio_en_gpio_en_24_wd; + logic gpio_en_gpio_en_24_we; + logic gpio_en_gpio_en_25_qs; + logic gpio_en_gpio_en_25_wd; + logic gpio_en_gpio_en_25_we; + logic gpio_en_gpio_en_26_qs; + logic gpio_en_gpio_en_26_wd; + logic gpio_en_gpio_en_26_we; + logic gpio_en_gpio_en_27_qs; + logic gpio_en_gpio_en_27_wd; + logic gpio_en_gpio_en_27_we; + logic gpio_en_gpio_en_28_qs; + logic gpio_en_gpio_en_28_wd; + logic gpio_en_gpio_en_28_we; + logic gpio_en_gpio_en_29_qs; + logic gpio_en_gpio_en_29_wd; + logic gpio_en_gpio_en_29_we; + logic gpio_en_gpio_en_30_qs; + logic gpio_en_gpio_en_30_wd; + logic gpio_en_gpio_en_30_we; + logic gpio_en_gpio_en_31_qs; + logic gpio_en_gpio_en_31_wd; + logic gpio_en_gpio_en_31_we; + logic gpio_in_gpio_in_0_qs; + logic gpio_in_gpio_in_0_re; + logic gpio_in_gpio_in_1_qs; + logic gpio_in_gpio_in_1_re; + logic gpio_in_gpio_in_2_qs; + logic gpio_in_gpio_in_2_re; + logic gpio_in_gpio_in_3_qs; + logic gpio_in_gpio_in_3_re; + logic gpio_in_gpio_in_4_qs; + logic gpio_in_gpio_in_4_re; + logic gpio_in_gpio_in_5_qs; + logic gpio_in_gpio_in_5_re; + logic gpio_in_gpio_in_6_qs; + logic gpio_in_gpio_in_6_re; + logic gpio_in_gpio_in_7_qs; + logic gpio_in_gpio_in_7_re; + logic gpio_in_gpio_in_8_qs; + logic gpio_in_gpio_in_8_re; + logic gpio_in_gpio_in_9_qs; + logic gpio_in_gpio_in_9_re; + logic gpio_in_gpio_in_10_qs; + logic gpio_in_gpio_in_10_re; + logic gpio_in_gpio_in_11_qs; + logic gpio_in_gpio_in_11_re; + logic gpio_in_gpio_in_12_qs; + logic gpio_in_gpio_in_12_re; + logic gpio_in_gpio_in_13_qs; + logic gpio_in_gpio_in_13_re; + logic gpio_in_gpio_in_14_qs; + logic gpio_in_gpio_in_14_re; + logic gpio_in_gpio_in_15_qs; + logic gpio_in_gpio_in_15_re; + logic gpio_in_gpio_in_16_qs; + logic gpio_in_gpio_in_16_re; + logic gpio_in_gpio_in_17_qs; + logic gpio_in_gpio_in_17_re; + logic gpio_in_gpio_in_18_qs; + logic gpio_in_gpio_in_18_re; + logic gpio_in_gpio_in_19_qs; + logic gpio_in_gpio_in_19_re; + logic gpio_in_gpio_in_20_qs; + logic gpio_in_gpio_in_20_re; + logic gpio_in_gpio_in_21_qs; + logic gpio_in_gpio_in_21_re; + logic gpio_in_gpio_in_22_qs; + logic gpio_in_gpio_in_22_re; + logic gpio_in_gpio_in_23_qs; + logic gpio_in_gpio_in_23_re; + logic gpio_in_gpio_in_24_qs; + logic gpio_in_gpio_in_24_re; + logic gpio_in_gpio_in_25_qs; + logic gpio_in_gpio_in_25_re; + logic gpio_in_gpio_in_26_qs; + logic gpio_in_gpio_in_26_re; + logic gpio_in_gpio_in_27_qs; + logic gpio_in_gpio_in_27_re; + logic gpio_in_gpio_in_28_qs; + logic gpio_in_gpio_in_28_re; + logic gpio_in_gpio_in_29_qs; + logic gpio_in_gpio_in_29_re; + logic gpio_in_gpio_in_30_qs; + logic gpio_in_gpio_in_30_re; + logic gpio_in_gpio_in_31_qs; + logic gpio_in_gpio_in_31_re; + logic gpio_out_gpio_out_0_qs; + logic gpio_out_gpio_out_0_wd; + logic gpio_out_gpio_out_0_we; + logic gpio_out_gpio_out_1_qs; + logic gpio_out_gpio_out_1_wd; + logic gpio_out_gpio_out_1_we; + logic gpio_out_gpio_out_2_qs; + logic gpio_out_gpio_out_2_wd; + logic gpio_out_gpio_out_2_we; + logic gpio_out_gpio_out_3_qs; + logic gpio_out_gpio_out_3_wd; + logic gpio_out_gpio_out_3_we; + logic gpio_out_gpio_out_4_qs; + logic gpio_out_gpio_out_4_wd; + logic gpio_out_gpio_out_4_we; + logic gpio_out_gpio_out_5_qs; + logic gpio_out_gpio_out_5_wd; + logic gpio_out_gpio_out_5_we; + logic gpio_out_gpio_out_6_qs; + logic gpio_out_gpio_out_6_wd; + logic gpio_out_gpio_out_6_we; + logic gpio_out_gpio_out_7_qs; + logic gpio_out_gpio_out_7_wd; + logic gpio_out_gpio_out_7_we; + logic gpio_out_gpio_out_8_qs; + logic gpio_out_gpio_out_8_wd; + logic gpio_out_gpio_out_8_we; + logic gpio_out_gpio_out_9_qs; + logic gpio_out_gpio_out_9_wd; + logic gpio_out_gpio_out_9_we; + logic gpio_out_gpio_out_10_qs; + logic gpio_out_gpio_out_10_wd; + logic gpio_out_gpio_out_10_we; + logic gpio_out_gpio_out_11_qs; + logic gpio_out_gpio_out_11_wd; + logic gpio_out_gpio_out_11_we; + logic gpio_out_gpio_out_12_qs; + logic gpio_out_gpio_out_12_wd; + logic gpio_out_gpio_out_12_we; + logic gpio_out_gpio_out_13_qs; + logic gpio_out_gpio_out_13_wd; + logic gpio_out_gpio_out_13_we; + logic gpio_out_gpio_out_14_qs; + logic gpio_out_gpio_out_14_wd; + logic gpio_out_gpio_out_14_we; + logic gpio_out_gpio_out_15_qs; + logic gpio_out_gpio_out_15_wd; + logic gpio_out_gpio_out_15_we; + logic gpio_out_gpio_out_16_qs; + logic gpio_out_gpio_out_16_wd; + logic gpio_out_gpio_out_16_we; + logic gpio_out_gpio_out_17_qs; + logic gpio_out_gpio_out_17_wd; + logic gpio_out_gpio_out_17_we; + logic gpio_out_gpio_out_18_qs; + logic gpio_out_gpio_out_18_wd; + logic gpio_out_gpio_out_18_we; + logic gpio_out_gpio_out_19_qs; + logic gpio_out_gpio_out_19_wd; + logic gpio_out_gpio_out_19_we; + logic gpio_out_gpio_out_20_qs; + logic gpio_out_gpio_out_20_wd; + logic gpio_out_gpio_out_20_we; + logic gpio_out_gpio_out_21_qs; + logic gpio_out_gpio_out_21_wd; + logic gpio_out_gpio_out_21_we; + logic gpio_out_gpio_out_22_qs; + logic gpio_out_gpio_out_22_wd; + logic gpio_out_gpio_out_22_we; + logic gpio_out_gpio_out_23_qs; + logic gpio_out_gpio_out_23_wd; + logic gpio_out_gpio_out_23_we; + logic gpio_out_gpio_out_24_qs; + logic gpio_out_gpio_out_24_wd; + logic gpio_out_gpio_out_24_we; + logic gpio_out_gpio_out_25_qs; + logic gpio_out_gpio_out_25_wd; + logic gpio_out_gpio_out_25_we; + logic gpio_out_gpio_out_26_qs; + logic gpio_out_gpio_out_26_wd; + logic gpio_out_gpio_out_26_we; + logic gpio_out_gpio_out_27_qs; + logic gpio_out_gpio_out_27_wd; + logic gpio_out_gpio_out_27_we; + logic gpio_out_gpio_out_28_qs; + logic gpio_out_gpio_out_28_wd; + logic gpio_out_gpio_out_28_we; + logic gpio_out_gpio_out_29_qs; + logic gpio_out_gpio_out_29_wd; + logic gpio_out_gpio_out_29_we; + logic gpio_out_gpio_out_30_qs; + logic gpio_out_gpio_out_30_wd; + logic gpio_out_gpio_out_30_we; + logic gpio_out_gpio_out_31_qs; + logic gpio_out_gpio_out_31_wd; + logic gpio_out_gpio_out_31_we; + logic gpio_set_gpio_set_0_wd; + logic gpio_set_gpio_set_0_we; + logic gpio_set_gpio_set_1_wd; + logic gpio_set_gpio_set_1_we; + logic gpio_set_gpio_set_2_wd; + logic gpio_set_gpio_set_2_we; + logic gpio_set_gpio_set_3_wd; + logic gpio_set_gpio_set_3_we; + logic gpio_set_gpio_set_4_wd; + logic gpio_set_gpio_set_4_we; + logic gpio_set_gpio_set_5_wd; + logic gpio_set_gpio_set_5_we; + logic gpio_set_gpio_set_6_wd; + logic gpio_set_gpio_set_6_we; + logic gpio_set_gpio_set_7_wd; + logic gpio_set_gpio_set_7_we; + logic gpio_set_gpio_set_8_wd; + logic gpio_set_gpio_set_8_we; + logic gpio_set_gpio_set_9_wd; + logic gpio_set_gpio_set_9_we; + logic gpio_set_gpio_set_10_wd; + logic gpio_set_gpio_set_10_we; + logic gpio_set_gpio_set_11_wd; + logic gpio_set_gpio_set_11_we; + logic gpio_set_gpio_set_12_wd; + logic gpio_set_gpio_set_12_we; + logic gpio_set_gpio_set_13_wd; + logic gpio_set_gpio_set_13_we; + logic gpio_set_gpio_set_14_wd; + logic gpio_set_gpio_set_14_we; + logic gpio_set_gpio_set_15_wd; + logic gpio_set_gpio_set_15_we; + logic gpio_set_gpio_set_16_wd; + logic gpio_set_gpio_set_16_we; + logic gpio_set_gpio_set_17_wd; + logic gpio_set_gpio_set_17_we; + logic gpio_set_gpio_set_18_wd; + logic gpio_set_gpio_set_18_we; + logic gpio_set_gpio_set_19_wd; + logic gpio_set_gpio_set_19_we; + logic gpio_set_gpio_set_20_wd; + logic gpio_set_gpio_set_20_we; + logic gpio_set_gpio_set_21_wd; + logic gpio_set_gpio_set_21_we; + logic gpio_set_gpio_set_22_wd; + logic gpio_set_gpio_set_22_we; + logic gpio_set_gpio_set_23_wd; + logic gpio_set_gpio_set_23_we; + logic gpio_set_gpio_set_24_wd; + logic gpio_set_gpio_set_24_we; + logic gpio_set_gpio_set_25_wd; + logic gpio_set_gpio_set_25_we; + logic gpio_set_gpio_set_26_wd; + logic gpio_set_gpio_set_26_we; + logic gpio_set_gpio_set_27_wd; + logic gpio_set_gpio_set_27_we; + logic gpio_set_gpio_set_28_wd; + logic gpio_set_gpio_set_28_we; + logic gpio_set_gpio_set_29_wd; + logic gpio_set_gpio_set_29_we; + logic gpio_set_gpio_set_30_wd; + logic gpio_set_gpio_set_30_we; + logic gpio_set_gpio_set_31_wd; + logic gpio_set_gpio_set_31_we; + logic gpio_clear_gpio_clear_0_wd; + logic gpio_clear_gpio_clear_0_we; + logic gpio_clear_gpio_clear_1_wd; + logic gpio_clear_gpio_clear_1_we; + logic gpio_clear_gpio_clear_2_wd; + logic gpio_clear_gpio_clear_2_we; + logic gpio_clear_gpio_clear_3_wd; + logic gpio_clear_gpio_clear_3_we; + logic gpio_clear_gpio_clear_4_wd; + logic gpio_clear_gpio_clear_4_we; + logic gpio_clear_gpio_clear_5_wd; + logic gpio_clear_gpio_clear_5_we; + logic gpio_clear_gpio_clear_6_wd; + logic gpio_clear_gpio_clear_6_we; + logic gpio_clear_gpio_clear_7_wd; + logic gpio_clear_gpio_clear_7_we; + logic gpio_clear_gpio_clear_8_wd; + logic gpio_clear_gpio_clear_8_we; + logic gpio_clear_gpio_clear_9_wd; + logic gpio_clear_gpio_clear_9_we; + logic gpio_clear_gpio_clear_10_wd; + logic gpio_clear_gpio_clear_10_we; + logic gpio_clear_gpio_clear_11_wd; + logic gpio_clear_gpio_clear_11_we; + logic gpio_clear_gpio_clear_12_wd; + logic gpio_clear_gpio_clear_12_we; + logic gpio_clear_gpio_clear_13_wd; + logic gpio_clear_gpio_clear_13_we; + logic gpio_clear_gpio_clear_14_wd; + logic gpio_clear_gpio_clear_14_we; + logic gpio_clear_gpio_clear_15_wd; + logic gpio_clear_gpio_clear_15_we; + logic gpio_clear_gpio_clear_16_wd; + logic gpio_clear_gpio_clear_16_we; + logic gpio_clear_gpio_clear_17_wd; + logic gpio_clear_gpio_clear_17_we; + logic gpio_clear_gpio_clear_18_wd; + logic gpio_clear_gpio_clear_18_we; + logic gpio_clear_gpio_clear_19_wd; + logic gpio_clear_gpio_clear_19_we; + logic gpio_clear_gpio_clear_20_wd; + logic gpio_clear_gpio_clear_20_we; + logic gpio_clear_gpio_clear_21_wd; + logic gpio_clear_gpio_clear_21_we; + logic gpio_clear_gpio_clear_22_wd; + logic gpio_clear_gpio_clear_22_we; + logic gpio_clear_gpio_clear_23_wd; + logic gpio_clear_gpio_clear_23_we; + logic gpio_clear_gpio_clear_24_wd; + logic gpio_clear_gpio_clear_24_we; + logic gpio_clear_gpio_clear_25_wd; + logic gpio_clear_gpio_clear_25_we; + logic gpio_clear_gpio_clear_26_wd; + logic gpio_clear_gpio_clear_26_we; + logic gpio_clear_gpio_clear_27_wd; + logic gpio_clear_gpio_clear_27_we; + logic gpio_clear_gpio_clear_28_wd; + logic gpio_clear_gpio_clear_28_we; + logic gpio_clear_gpio_clear_29_wd; + logic gpio_clear_gpio_clear_29_we; + logic gpio_clear_gpio_clear_30_wd; + logic gpio_clear_gpio_clear_30_we; + logic gpio_clear_gpio_clear_31_wd; + logic gpio_clear_gpio_clear_31_we; + logic gpio_toggle_gpio_toggle_0_wd; + logic gpio_toggle_gpio_toggle_0_we; + logic gpio_toggle_gpio_toggle_1_wd; + logic gpio_toggle_gpio_toggle_1_we; + logic gpio_toggle_gpio_toggle_2_wd; + logic gpio_toggle_gpio_toggle_2_we; + logic gpio_toggle_gpio_toggle_3_wd; + logic gpio_toggle_gpio_toggle_3_we; + logic gpio_toggle_gpio_toggle_4_wd; + logic gpio_toggle_gpio_toggle_4_we; + logic gpio_toggle_gpio_toggle_5_wd; + logic gpio_toggle_gpio_toggle_5_we; + logic gpio_toggle_gpio_toggle_6_wd; + logic gpio_toggle_gpio_toggle_6_we; + logic gpio_toggle_gpio_toggle_7_wd; + logic gpio_toggle_gpio_toggle_7_we; + logic gpio_toggle_gpio_toggle_8_wd; + logic gpio_toggle_gpio_toggle_8_we; + logic gpio_toggle_gpio_toggle_9_wd; + logic gpio_toggle_gpio_toggle_9_we; + logic gpio_toggle_gpio_toggle_10_wd; + logic gpio_toggle_gpio_toggle_10_we; + logic gpio_toggle_gpio_toggle_11_wd; + logic gpio_toggle_gpio_toggle_11_we; + logic gpio_toggle_gpio_toggle_12_wd; + logic gpio_toggle_gpio_toggle_12_we; + logic gpio_toggle_gpio_toggle_13_wd; + logic gpio_toggle_gpio_toggle_13_we; + logic gpio_toggle_gpio_toggle_14_wd; + logic gpio_toggle_gpio_toggle_14_we; + logic gpio_toggle_gpio_toggle_15_wd; + logic gpio_toggle_gpio_toggle_15_we; + logic gpio_toggle_gpio_toggle_16_wd; + logic gpio_toggle_gpio_toggle_16_we; + logic gpio_toggle_gpio_toggle_17_wd; + logic gpio_toggle_gpio_toggle_17_we; + logic gpio_toggle_gpio_toggle_18_wd; + logic gpio_toggle_gpio_toggle_18_we; + logic gpio_toggle_gpio_toggle_19_wd; + logic gpio_toggle_gpio_toggle_19_we; + logic gpio_toggle_gpio_toggle_20_wd; + logic gpio_toggle_gpio_toggle_20_we; + logic gpio_toggle_gpio_toggle_21_wd; + logic gpio_toggle_gpio_toggle_21_we; + logic gpio_toggle_gpio_toggle_22_wd; + logic gpio_toggle_gpio_toggle_22_we; + logic gpio_toggle_gpio_toggle_23_wd; + logic gpio_toggle_gpio_toggle_23_we; + logic gpio_toggle_gpio_toggle_24_wd; + logic gpio_toggle_gpio_toggle_24_we; + logic gpio_toggle_gpio_toggle_25_wd; + logic gpio_toggle_gpio_toggle_25_we; + logic gpio_toggle_gpio_toggle_26_wd; + logic gpio_toggle_gpio_toggle_26_we; + logic gpio_toggle_gpio_toggle_27_wd; + logic gpio_toggle_gpio_toggle_27_we; + logic gpio_toggle_gpio_toggle_28_wd; + logic gpio_toggle_gpio_toggle_28_we; + logic gpio_toggle_gpio_toggle_29_wd; + logic gpio_toggle_gpio_toggle_29_we; + logic gpio_toggle_gpio_toggle_30_wd; + logic gpio_toggle_gpio_toggle_30_we; + logic gpio_toggle_gpio_toggle_31_wd; + logic gpio_toggle_gpio_toggle_31_we; + logic intrpt_rise_en_intrpt_rise_en_0_qs; + logic intrpt_rise_en_intrpt_rise_en_0_wd; + logic intrpt_rise_en_intrpt_rise_en_0_we; + logic intrpt_rise_en_intrpt_rise_en_1_qs; + logic intrpt_rise_en_intrpt_rise_en_1_wd; + logic intrpt_rise_en_intrpt_rise_en_1_we; + logic intrpt_rise_en_intrpt_rise_en_2_qs; + logic intrpt_rise_en_intrpt_rise_en_2_wd; + logic intrpt_rise_en_intrpt_rise_en_2_we; + logic intrpt_rise_en_intrpt_rise_en_3_qs; + logic intrpt_rise_en_intrpt_rise_en_3_wd; + logic intrpt_rise_en_intrpt_rise_en_3_we; + logic intrpt_rise_en_intrpt_rise_en_4_qs; + logic intrpt_rise_en_intrpt_rise_en_4_wd; + logic intrpt_rise_en_intrpt_rise_en_4_we; + logic intrpt_rise_en_intrpt_rise_en_5_qs; + logic intrpt_rise_en_intrpt_rise_en_5_wd; + logic intrpt_rise_en_intrpt_rise_en_5_we; + logic intrpt_rise_en_intrpt_rise_en_6_qs; + logic intrpt_rise_en_intrpt_rise_en_6_wd; + logic intrpt_rise_en_intrpt_rise_en_6_we; + logic intrpt_rise_en_intrpt_rise_en_7_qs; + logic intrpt_rise_en_intrpt_rise_en_7_wd; + logic intrpt_rise_en_intrpt_rise_en_7_we; + logic intrpt_rise_en_intrpt_rise_en_8_qs; + logic intrpt_rise_en_intrpt_rise_en_8_wd; + logic intrpt_rise_en_intrpt_rise_en_8_we; + logic intrpt_rise_en_intrpt_rise_en_9_qs; + logic intrpt_rise_en_intrpt_rise_en_9_wd; + logic intrpt_rise_en_intrpt_rise_en_9_we; + logic intrpt_rise_en_intrpt_rise_en_10_qs; + logic intrpt_rise_en_intrpt_rise_en_10_wd; + logic intrpt_rise_en_intrpt_rise_en_10_we; + logic intrpt_rise_en_intrpt_rise_en_11_qs; + logic intrpt_rise_en_intrpt_rise_en_11_wd; + logic intrpt_rise_en_intrpt_rise_en_11_we; + logic intrpt_rise_en_intrpt_rise_en_12_qs; + logic intrpt_rise_en_intrpt_rise_en_12_wd; + logic intrpt_rise_en_intrpt_rise_en_12_we; + logic intrpt_rise_en_intrpt_rise_en_13_qs; + logic intrpt_rise_en_intrpt_rise_en_13_wd; + logic intrpt_rise_en_intrpt_rise_en_13_we; + logic intrpt_rise_en_intrpt_rise_en_14_qs; + logic intrpt_rise_en_intrpt_rise_en_14_wd; + logic intrpt_rise_en_intrpt_rise_en_14_we; + logic intrpt_rise_en_intrpt_rise_en_15_qs; + logic intrpt_rise_en_intrpt_rise_en_15_wd; + logic intrpt_rise_en_intrpt_rise_en_15_we; + logic intrpt_rise_en_intrpt_rise_en_16_qs; + logic intrpt_rise_en_intrpt_rise_en_16_wd; + logic intrpt_rise_en_intrpt_rise_en_16_we; + logic intrpt_rise_en_intrpt_rise_en_17_qs; + logic intrpt_rise_en_intrpt_rise_en_17_wd; + logic intrpt_rise_en_intrpt_rise_en_17_we; + logic intrpt_rise_en_intrpt_rise_en_18_qs; + logic intrpt_rise_en_intrpt_rise_en_18_wd; + logic intrpt_rise_en_intrpt_rise_en_18_we; + logic intrpt_rise_en_intrpt_rise_en_19_qs; + logic intrpt_rise_en_intrpt_rise_en_19_wd; + logic intrpt_rise_en_intrpt_rise_en_19_we; + logic intrpt_rise_en_intrpt_rise_en_20_qs; + logic intrpt_rise_en_intrpt_rise_en_20_wd; + logic intrpt_rise_en_intrpt_rise_en_20_we; + logic intrpt_rise_en_intrpt_rise_en_21_qs; + logic intrpt_rise_en_intrpt_rise_en_21_wd; + logic intrpt_rise_en_intrpt_rise_en_21_we; + logic intrpt_rise_en_intrpt_rise_en_22_qs; + logic intrpt_rise_en_intrpt_rise_en_22_wd; + logic intrpt_rise_en_intrpt_rise_en_22_we; + logic intrpt_rise_en_intrpt_rise_en_23_qs; + logic intrpt_rise_en_intrpt_rise_en_23_wd; + logic intrpt_rise_en_intrpt_rise_en_23_we; + logic intrpt_rise_en_intrpt_rise_en_24_qs; + logic intrpt_rise_en_intrpt_rise_en_24_wd; + logic intrpt_rise_en_intrpt_rise_en_24_we; + logic intrpt_rise_en_intrpt_rise_en_25_qs; + logic intrpt_rise_en_intrpt_rise_en_25_wd; + logic intrpt_rise_en_intrpt_rise_en_25_we; + logic intrpt_rise_en_intrpt_rise_en_26_qs; + logic intrpt_rise_en_intrpt_rise_en_26_wd; + logic intrpt_rise_en_intrpt_rise_en_26_we; + logic intrpt_rise_en_intrpt_rise_en_27_qs; + logic intrpt_rise_en_intrpt_rise_en_27_wd; + logic intrpt_rise_en_intrpt_rise_en_27_we; + logic intrpt_rise_en_intrpt_rise_en_28_qs; + logic intrpt_rise_en_intrpt_rise_en_28_wd; + logic intrpt_rise_en_intrpt_rise_en_28_we; + logic intrpt_rise_en_intrpt_rise_en_29_qs; + logic intrpt_rise_en_intrpt_rise_en_29_wd; + logic intrpt_rise_en_intrpt_rise_en_29_we; + logic intrpt_rise_en_intrpt_rise_en_30_qs; + logic intrpt_rise_en_intrpt_rise_en_30_wd; + logic intrpt_rise_en_intrpt_rise_en_30_we; + logic intrpt_rise_en_intrpt_rise_en_31_qs; + logic intrpt_rise_en_intrpt_rise_en_31_wd; + logic intrpt_rise_en_intrpt_rise_en_31_we; + logic intrpt_fall_en_intrpt_fall_en_0_qs; + logic intrpt_fall_en_intrpt_fall_en_0_wd; + logic intrpt_fall_en_intrpt_fall_en_0_we; + logic intrpt_fall_en_intrpt_fall_en_1_qs; + logic intrpt_fall_en_intrpt_fall_en_1_wd; + logic intrpt_fall_en_intrpt_fall_en_1_we; + logic intrpt_fall_en_intrpt_fall_en_2_qs; + logic intrpt_fall_en_intrpt_fall_en_2_wd; + logic intrpt_fall_en_intrpt_fall_en_2_we; + logic intrpt_fall_en_intrpt_fall_en_3_qs; + logic intrpt_fall_en_intrpt_fall_en_3_wd; + logic intrpt_fall_en_intrpt_fall_en_3_we; + logic intrpt_fall_en_intrpt_fall_en_4_qs; + logic intrpt_fall_en_intrpt_fall_en_4_wd; + logic intrpt_fall_en_intrpt_fall_en_4_we; + logic intrpt_fall_en_intrpt_fall_en_5_qs; + logic intrpt_fall_en_intrpt_fall_en_5_wd; + logic intrpt_fall_en_intrpt_fall_en_5_we; + logic intrpt_fall_en_intrpt_fall_en_6_qs; + logic intrpt_fall_en_intrpt_fall_en_6_wd; + logic intrpt_fall_en_intrpt_fall_en_6_we; + logic intrpt_fall_en_intrpt_fall_en_7_qs; + logic intrpt_fall_en_intrpt_fall_en_7_wd; + logic intrpt_fall_en_intrpt_fall_en_7_we; + logic intrpt_fall_en_intrpt_fall_en_8_qs; + logic intrpt_fall_en_intrpt_fall_en_8_wd; + logic intrpt_fall_en_intrpt_fall_en_8_we; + logic intrpt_fall_en_intrpt_fall_en_9_qs; + logic intrpt_fall_en_intrpt_fall_en_9_wd; + logic intrpt_fall_en_intrpt_fall_en_9_we; + logic intrpt_fall_en_intrpt_fall_en_10_qs; + logic intrpt_fall_en_intrpt_fall_en_10_wd; + logic intrpt_fall_en_intrpt_fall_en_10_we; + logic intrpt_fall_en_intrpt_fall_en_11_qs; + logic intrpt_fall_en_intrpt_fall_en_11_wd; + logic intrpt_fall_en_intrpt_fall_en_11_we; + logic intrpt_fall_en_intrpt_fall_en_12_qs; + logic intrpt_fall_en_intrpt_fall_en_12_wd; + logic intrpt_fall_en_intrpt_fall_en_12_we; + logic intrpt_fall_en_intrpt_fall_en_13_qs; + logic intrpt_fall_en_intrpt_fall_en_13_wd; + logic intrpt_fall_en_intrpt_fall_en_13_we; + logic intrpt_fall_en_intrpt_fall_en_14_qs; + logic intrpt_fall_en_intrpt_fall_en_14_wd; + logic intrpt_fall_en_intrpt_fall_en_14_we; + logic intrpt_fall_en_intrpt_fall_en_15_qs; + logic intrpt_fall_en_intrpt_fall_en_15_wd; + logic intrpt_fall_en_intrpt_fall_en_15_we; + logic intrpt_fall_en_intrpt_fall_en_16_qs; + logic intrpt_fall_en_intrpt_fall_en_16_wd; + logic intrpt_fall_en_intrpt_fall_en_16_we; + logic intrpt_fall_en_intrpt_fall_en_17_qs; + logic intrpt_fall_en_intrpt_fall_en_17_wd; + logic intrpt_fall_en_intrpt_fall_en_17_we; + logic intrpt_fall_en_intrpt_fall_en_18_qs; + logic intrpt_fall_en_intrpt_fall_en_18_wd; + logic intrpt_fall_en_intrpt_fall_en_18_we; + logic intrpt_fall_en_intrpt_fall_en_19_qs; + logic intrpt_fall_en_intrpt_fall_en_19_wd; + logic intrpt_fall_en_intrpt_fall_en_19_we; + logic intrpt_fall_en_intrpt_fall_en_20_qs; + logic intrpt_fall_en_intrpt_fall_en_20_wd; + logic intrpt_fall_en_intrpt_fall_en_20_we; + logic intrpt_fall_en_intrpt_fall_en_21_qs; + logic intrpt_fall_en_intrpt_fall_en_21_wd; + logic intrpt_fall_en_intrpt_fall_en_21_we; + logic intrpt_fall_en_intrpt_fall_en_22_qs; + logic intrpt_fall_en_intrpt_fall_en_22_wd; + logic intrpt_fall_en_intrpt_fall_en_22_we; + logic intrpt_fall_en_intrpt_fall_en_23_qs; + logic intrpt_fall_en_intrpt_fall_en_23_wd; + logic intrpt_fall_en_intrpt_fall_en_23_we; + logic intrpt_fall_en_intrpt_fall_en_24_qs; + logic intrpt_fall_en_intrpt_fall_en_24_wd; + logic intrpt_fall_en_intrpt_fall_en_24_we; + logic intrpt_fall_en_intrpt_fall_en_25_qs; + logic intrpt_fall_en_intrpt_fall_en_25_wd; + logic intrpt_fall_en_intrpt_fall_en_25_we; + logic intrpt_fall_en_intrpt_fall_en_26_qs; + logic intrpt_fall_en_intrpt_fall_en_26_wd; + logic intrpt_fall_en_intrpt_fall_en_26_we; + logic intrpt_fall_en_intrpt_fall_en_27_qs; + logic intrpt_fall_en_intrpt_fall_en_27_wd; + logic intrpt_fall_en_intrpt_fall_en_27_we; + logic intrpt_fall_en_intrpt_fall_en_28_qs; + logic intrpt_fall_en_intrpt_fall_en_28_wd; + logic intrpt_fall_en_intrpt_fall_en_28_we; + logic intrpt_fall_en_intrpt_fall_en_29_qs; + logic intrpt_fall_en_intrpt_fall_en_29_wd; + logic intrpt_fall_en_intrpt_fall_en_29_we; + logic intrpt_fall_en_intrpt_fall_en_30_qs; + logic intrpt_fall_en_intrpt_fall_en_30_wd; + logic intrpt_fall_en_intrpt_fall_en_30_we; + logic intrpt_fall_en_intrpt_fall_en_31_qs; + logic intrpt_fall_en_intrpt_fall_en_31_wd; + logic intrpt_fall_en_intrpt_fall_en_31_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_0_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_0_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_0_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_1_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_1_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_1_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_2_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_2_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_2_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_3_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_3_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_3_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_4_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_4_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_4_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_5_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_5_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_5_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_6_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_6_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_6_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_7_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_7_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_7_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_8_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_8_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_8_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_9_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_9_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_9_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_10_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_10_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_10_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_11_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_11_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_11_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_12_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_12_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_12_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_13_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_13_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_13_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_14_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_14_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_14_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_15_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_15_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_15_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_16_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_16_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_16_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_17_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_17_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_17_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_18_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_18_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_18_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_19_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_19_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_19_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_20_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_20_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_20_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_21_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_21_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_21_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_22_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_22_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_22_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_23_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_23_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_23_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_24_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_24_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_24_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_25_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_25_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_25_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_26_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_26_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_26_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_27_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_27_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_27_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_28_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_28_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_28_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_29_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_29_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_29_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_30_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_30_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_30_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_31_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_31_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_31_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_0_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_0_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_0_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_1_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_1_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_1_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_2_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_2_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_2_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_3_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_3_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_3_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_4_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_4_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_4_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_5_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_5_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_5_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_6_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_6_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_6_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_7_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_7_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_7_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_8_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_8_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_8_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_9_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_9_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_9_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_10_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_10_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_10_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_11_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_11_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_11_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_12_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_12_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_12_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_13_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_13_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_13_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_14_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_14_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_14_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_15_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_15_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_15_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_16_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_16_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_16_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_17_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_17_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_17_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_18_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_18_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_18_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_19_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_19_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_19_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_20_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_20_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_20_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_21_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_21_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_21_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_22_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_22_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_22_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_23_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_23_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_23_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_24_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_24_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_24_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_25_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_25_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_25_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_26_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_26_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_26_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_27_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_27_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_27_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_28_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_28_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_28_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_29_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_29_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_29_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_30_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_30_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_30_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_31_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_31_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_31_we; + logic intrpt_status_intrpt_status_0_qs; + logic intrpt_status_intrpt_status_0_wd; + logic intrpt_status_intrpt_status_0_we; + logic intrpt_status_intrpt_status_0_re; + logic intrpt_status_intrpt_status_1_qs; + logic intrpt_status_intrpt_status_1_wd; + logic intrpt_status_intrpt_status_1_we; + logic intrpt_status_intrpt_status_1_re; + logic intrpt_status_intrpt_status_2_qs; + logic intrpt_status_intrpt_status_2_wd; + logic intrpt_status_intrpt_status_2_we; + logic intrpt_status_intrpt_status_2_re; + logic intrpt_status_intrpt_status_3_qs; + logic intrpt_status_intrpt_status_3_wd; + logic intrpt_status_intrpt_status_3_we; + logic intrpt_status_intrpt_status_3_re; + logic intrpt_status_intrpt_status_4_qs; + logic intrpt_status_intrpt_status_4_wd; + logic intrpt_status_intrpt_status_4_we; + logic intrpt_status_intrpt_status_4_re; + logic intrpt_status_intrpt_status_5_qs; + logic intrpt_status_intrpt_status_5_wd; + logic intrpt_status_intrpt_status_5_we; + logic intrpt_status_intrpt_status_5_re; + logic intrpt_status_intrpt_status_6_qs; + logic intrpt_status_intrpt_status_6_wd; + logic intrpt_status_intrpt_status_6_we; + logic intrpt_status_intrpt_status_6_re; + logic intrpt_status_intrpt_status_7_qs; + logic intrpt_status_intrpt_status_7_wd; + logic intrpt_status_intrpt_status_7_we; + logic intrpt_status_intrpt_status_7_re; + logic intrpt_status_intrpt_status_8_qs; + logic intrpt_status_intrpt_status_8_wd; + logic intrpt_status_intrpt_status_8_we; + logic intrpt_status_intrpt_status_8_re; + logic intrpt_status_intrpt_status_9_qs; + logic intrpt_status_intrpt_status_9_wd; + logic intrpt_status_intrpt_status_9_we; + logic intrpt_status_intrpt_status_9_re; + logic intrpt_status_intrpt_status_10_qs; + logic intrpt_status_intrpt_status_10_wd; + logic intrpt_status_intrpt_status_10_we; + logic intrpt_status_intrpt_status_10_re; + logic intrpt_status_intrpt_status_11_qs; + logic intrpt_status_intrpt_status_11_wd; + logic intrpt_status_intrpt_status_11_we; + logic intrpt_status_intrpt_status_11_re; + logic intrpt_status_intrpt_status_12_qs; + logic intrpt_status_intrpt_status_12_wd; + logic intrpt_status_intrpt_status_12_we; + logic intrpt_status_intrpt_status_12_re; + logic intrpt_status_intrpt_status_13_qs; + logic intrpt_status_intrpt_status_13_wd; + logic intrpt_status_intrpt_status_13_we; + logic intrpt_status_intrpt_status_13_re; + logic intrpt_status_intrpt_status_14_qs; + logic intrpt_status_intrpt_status_14_wd; + logic intrpt_status_intrpt_status_14_we; + logic intrpt_status_intrpt_status_14_re; + logic intrpt_status_intrpt_status_15_qs; + logic intrpt_status_intrpt_status_15_wd; + logic intrpt_status_intrpt_status_15_we; + logic intrpt_status_intrpt_status_15_re; + logic intrpt_status_intrpt_status_16_qs; + logic intrpt_status_intrpt_status_16_wd; + logic intrpt_status_intrpt_status_16_we; + logic intrpt_status_intrpt_status_16_re; + logic intrpt_status_intrpt_status_17_qs; + logic intrpt_status_intrpt_status_17_wd; + logic intrpt_status_intrpt_status_17_we; + logic intrpt_status_intrpt_status_17_re; + logic intrpt_status_intrpt_status_18_qs; + logic intrpt_status_intrpt_status_18_wd; + logic intrpt_status_intrpt_status_18_we; + logic intrpt_status_intrpt_status_18_re; + logic intrpt_status_intrpt_status_19_qs; + logic intrpt_status_intrpt_status_19_wd; + logic intrpt_status_intrpt_status_19_we; + logic intrpt_status_intrpt_status_19_re; + logic intrpt_status_intrpt_status_20_qs; + logic intrpt_status_intrpt_status_20_wd; + logic intrpt_status_intrpt_status_20_we; + logic intrpt_status_intrpt_status_20_re; + logic intrpt_status_intrpt_status_21_qs; + logic intrpt_status_intrpt_status_21_wd; + logic intrpt_status_intrpt_status_21_we; + logic intrpt_status_intrpt_status_21_re; + logic intrpt_status_intrpt_status_22_qs; + logic intrpt_status_intrpt_status_22_wd; + logic intrpt_status_intrpt_status_22_we; + logic intrpt_status_intrpt_status_22_re; + logic intrpt_status_intrpt_status_23_qs; + logic intrpt_status_intrpt_status_23_wd; + logic intrpt_status_intrpt_status_23_we; + logic intrpt_status_intrpt_status_23_re; + logic intrpt_status_intrpt_status_24_qs; + logic intrpt_status_intrpt_status_24_wd; + logic intrpt_status_intrpt_status_24_we; + logic intrpt_status_intrpt_status_24_re; + logic intrpt_status_intrpt_status_25_qs; + logic intrpt_status_intrpt_status_25_wd; + logic intrpt_status_intrpt_status_25_we; + logic intrpt_status_intrpt_status_25_re; + logic intrpt_status_intrpt_status_26_qs; + logic intrpt_status_intrpt_status_26_wd; + logic intrpt_status_intrpt_status_26_we; + logic intrpt_status_intrpt_status_26_re; + logic intrpt_status_intrpt_status_27_qs; + logic intrpt_status_intrpt_status_27_wd; + logic intrpt_status_intrpt_status_27_we; + logic intrpt_status_intrpt_status_27_re; + logic intrpt_status_intrpt_status_28_qs; + logic intrpt_status_intrpt_status_28_wd; + logic intrpt_status_intrpt_status_28_we; + logic intrpt_status_intrpt_status_28_re; + logic intrpt_status_intrpt_status_29_qs; + logic intrpt_status_intrpt_status_29_wd; + logic intrpt_status_intrpt_status_29_we; + logic intrpt_status_intrpt_status_29_re; + logic intrpt_status_intrpt_status_30_qs; + logic intrpt_status_intrpt_status_30_wd; + logic intrpt_status_intrpt_status_30_we; + logic intrpt_status_intrpt_status_30_re; + logic intrpt_status_intrpt_status_31_qs; + logic intrpt_status_intrpt_status_31_wd; + logic intrpt_status_intrpt_status_31_we; + logic intrpt_status_intrpt_status_31_re; + logic intrpt_rise_status_intrpt_rise_status_0_qs; + logic intrpt_rise_status_intrpt_rise_status_0_wd; + logic intrpt_rise_status_intrpt_rise_status_0_we; + logic intrpt_rise_status_intrpt_rise_status_1_qs; + logic intrpt_rise_status_intrpt_rise_status_1_wd; + logic intrpt_rise_status_intrpt_rise_status_1_we; + logic intrpt_rise_status_intrpt_rise_status_2_qs; + logic intrpt_rise_status_intrpt_rise_status_2_wd; + logic intrpt_rise_status_intrpt_rise_status_2_we; + logic intrpt_rise_status_intrpt_rise_status_3_qs; + logic intrpt_rise_status_intrpt_rise_status_3_wd; + logic intrpt_rise_status_intrpt_rise_status_3_we; + logic intrpt_rise_status_intrpt_rise_status_4_qs; + logic intrpt_rise_status_intrpt_rise_status_4_wd; + logic intrpt_rise_status_intrpt_rise_status_4_we; + logic intrpt_rise_status_intrpt_rise_status_5_qs; + logic intrpt_rise_status_intrpt_rise_status_5_wd; + logic intrpt_rise_status_intrpt_rise_status_5_we; + logic intrpt_rise_status_intrpt_rise_status_6_qs; + logic intrpt_rise_status_intrpt_rise_status_6_wd; + logic intrpt_rise_status_intrpt_rise_status_6_we; + logic intrpt_rise_status_intrpt_rise_status_7_qs; + logic intrpt_rise_status_intrpt_rise_status_7_wd; + logic intrpt_rise_status_intrpt_rise_status_7_we; + logic intrpt_rise_status_intrpt_rise_status_8_qs; + logic intrpt_rise_status_intrpt_rise_status_8_wd; + logic intrpt_rise_status_intrpt_rise_status_8_we; + logic intrpt_rise_status_intrpt_rise_status_9_qs; + logic intrpt_rise_status_intrpt_rise_status_9_wd; + logic intrpt_rise_status_intrpt_rise_status_9_we; + logic intrpt_rise_status_intrpt_rise_status_10_qs; + logic intrpt_rise_status_intrpt_rise_status_10_wd; + logic intrpt_rise_status_intrpt_rise_status_10_we; + logic intrpt_rise_status_intrpt_rise_status_11_qs; + logic intrpt_rise_status_intrpt_rise_status_11_wd; + logic intrpt_rise_status_intrpt_rise_status_11_we; + logic intrpt_rise_status_intrpt_rise_status_12_qs; + logic intrpt_rise_status_intrpt_rise_status_12_wd; + logic intrpt_rise_status_intrpt_rise_status_12_we; + logic intrpt_rise_status_intrpt_rise_status_13_qs; + logic intrpt_rise_status_intrpt_rise_status_13_wd; + logic intrpt_rise_status_intrpt_rise_status_13_we; + logic intrpt_rise_status_intrpt_rise_status_14_qs; + logic intrpt_rise_status_intrpt_rise_status_14_wd; + logic intrpt_rise_status_intrpt_rise_status_14_we; + logic intrpt_rise_status_intrpt_rise_status_15_qs; + logic intrpt_rise_status_intrpt_rise_status_15_wd; + logic intrpt_rise_status_intrpt_rise_status_15_we; + logic intrpt_rise_status_intrpt_rise_status_16_qs; + logic intrpt_rise_status_intrpt_rise_status_16_wd; + logic intrpt_rise_status_intrpt_rise_status_16_we; + logic intrpt_rise_status_intrpt_rise_status_17_qs; + logic intrpt_rise_status_intrpt_rise_status_17_wd; + logic intrpt_rise_status_intrpt_rise_status_17_we; + logic intrpt_rise_status_intrpt_rise_status_18_qs; + logic intrpt_rise_status_intrpt_rise_status_18_wd; + logic intrpt_rise_status_intrpt_rise_status_18_we; + logic intrpt_rise_status_intrpt_rise_status_19_qs; + logic intrpt_rise_status_intrpt_rise_status_19_wd; + logic intrpt_rise_status_intrpt_rise_status_19_we; + logic intrpt_rise_status_intrpt_rise_status_20_qs; + logic intrpt_rise_status_intrpt_rise_status_20_wd; + logic intrpt_rise_status_intrpt_rise_status_20_we; + logic intrpt_rise_status_intrpt_rise_status_21_qs; + logic intrpt_rise_status_intrpt_rise_status_21_wd; + logic intrpt_rise_status_intrpt_rise_status_21_we; + logic intrpt_rise_status_intrpt_rise_status_22_qs; + logic intrpt_rise_status_intrpt_rise_status_22_wd; + logic intrpt_rise_status_intrpt_rise_status_22_we; + logic intrpt_rise_status_intrpt_rise_status_23_qs; + logic intrpt_rise_status_intrpt_rise_status_23_wd; + logic intrpt_rise_status_intrpt_rise_status_23_we; + logic intrpt_rise_status_intrpt_rise_status_24_qs; + logic intrpt_rise_status_intrpt_rise_status_24_wd; + logic intrpt_rise_status_intrpt_rise_status_24_we; + logic intrpt_rise_status_intrpt_rise_status_25_qs; + logic intrpt_rise_status_intrpt_rise_status_25_wd; + logic intrpt_rise_status_intrpt_rise_status_25_we; + logic intrpt_rise_status_intrpt_rise_status_26_qs; + logic intrpt_rise_status_intrpt_rise_status_26_wd; + logic intrpt_rise_status_intrpt_rise_status_26_we; + logic intrpt_rise_status_intrpt_rise_status_27_qs; + logic intrpt_rise_status_intrpt_rise_status_27_wd; + logic intrpt_rise_status_intrpt_rise_status_27_we; + logic intrpt_rise_status_intrpt_rise_status_28_qs; + logic intrpt_rise_status_intrpt_rise_status_28_wd; + logic intrpt_rise_status_intrpt_rise_status_28_we; + logic intrpt_rise_status_intrpt_rise_status_29_qs; + logic intrpt_rise_status_intrpt_rise_status_29_wd; + logic intrpt_rise_status_intrpt_rise_status_29_we; + logic intrpt_rise_status_intrpt_rise_status_30_qs; + logic intrpt_rise_status_intrpt_rise_status_30_wd; + logic intrpt_rise_status_intrpt_rise_status_30_we; + logic intrpt_rise_status_intrpt_rise_status_31_qs; + logic intrpt_rise_status_intrpt_rise_status_31_wd; + logic intrpt_rise_status_intrpt_rise_status_31_we; + logic intrpt_fall_status_intrpt_fall_status_0_qs; + logic intrpt_fall_status_intrpt_fall_status_0_wd; + logic intrpt_fall_status_intrpt_fall_status_0_we; + logic intrpt_fall_status_intrpt_fall_status_1_qs; + logic intrpt_fall_status_intrpt_fall_status_1_wd; + logic intrpt_fall_status_intrpt_fall_status_1_we; + logic intrpt_fall_status_intrpt_fall_status_2_qs; + logic intrpt_fall_status_intrpt_fall_status_2_wd; + logic intrpt_fall_status_intrpt_fall_status_2_we; + logic intrpt_fall_status_intrpt_fall_status_3_qs; + logic intrpt_fall_status_intrpt_fall_status_3_wd; + logic intrpt_fall_status_intrpt_fall_status_3_we; + logic intrpt_fall_status_intrpt_fall_status_4_qs; + logic intrpt_fall_status_intrpt_fall_status_4_wd; + logic intrpt_fall_status_intrpt_fall_status_4_we; + logic intrpt_fall_status_intrpt_fall_status_5_qs; + logic intrpt_fall_status_intrpt_fall_status_5_wd; + logic intrpt_fall_status_intrpt_fall_status_5_we; + logic intrpt_fall_status_intrpt_fall_status_6_qs; + logic intrpt_fall_status_intrpt_fall_status_6_wd; + logic intrpt_fall_status_intrpt_fall_status_6_we; + logic intrpt_fall_status_intrpt_fall_status_7_qs; + logic intrpt_fall_status_intrpt_fall_status_7_wd; + logic intrpt_fall_status_intrpt_fall_status_7_we; + logic intrpt_fall_status_intrpt_fall_status_8_qs; + logic intrpt_fall_status_intrpt_fall_status_8_wd; + logic intrpt_fall_status_intrpt_fall_status_8_we; + logic intrpt_fall_status_intrpt_fall_status_9_qs; + logic intrpt_fall_status_intrpt_fall_status_9_wd; + logic intrpt_fall_status_intrpt_fall_status_9_we; + logic intrpt_fall_status_intrpt_fall_status_10_qs; + logic intrpt_fall_status_intrpt_fall_status_10_wd; + logic intrpt_fall_status_intrpt_fall_status_10_we; + logic intrpt_fall_status_intrpt_fall_status_11_qs; + logic intrpt_fall_status_intrpt_fall_status_11_wd; + logic intrpt_fall_status_intrpt_fall_status_11_we; + logic intrpt_fall_status_intrpt_fall_status_12_qs; + logic intrpt_fall_status_intrpt_fall_status_12_wd; + logic intrpt_fall_status_intrpt_fall_status_12_we; + logic intrpt_fall_status_intrpt_fall_status_13_qs; + logic intrpt_fall_status_intrpt_fall_status_13_wd; + logic intrpt_fall_status_intrpt_fall_status_13_we; + logic intrpt_fall_status_intrpt_fall_status_14_qs; + logic intrpt_fall_status_intrpt_fall_status_14_wd; + logic intrpt_fall_status_intrpt_fall_status_14_we; + logic intrpt_fall_status_intrpt_fall_status_15_qs; + logic intrpt_fall_status_intrpt_fall_status_15_wd; + logic intrpt_fall_status_intrpt_fall_status_15_we; + logic intrpt_fall_status_intrpt_fall_status_16_qs; + logic intrpt_fall_status_intrpt_fall_status_16_wd; + logic intrpt_fall_status_intrpt_fall_status_16_we; + logic intrpt_fall_status_intrpt_fall_status_17_qs; + logic intrpt_fall_status_intrpt_fall_status_17_wd; + logic intrpt_fall_status_intrpt_fall_status_17_we; + logic intrpt_fall_status_intrpt_fall_status_18_qs; + logic intrpt_fall_status_intrpt_fall_status_18_wd; + logic intrpt_fall_status_intrpt_fall_status_18_we; + logic intrpt_fall_status_intrpt_fall_status_19_qs; + logic intrpt_fall_status_intrpt_fall_status_19_wd; + logic intrpt_fall_status_intrpt_fall_status_19_we; + logic intrpt_fall_status_intrpt_fall_status_20_qs; + logic intrpt_fall_status_intrpt_fall_status_20_wd; + logic intrpt_fall_status_intrpt_fall_status_20_we; + logic intrpt_fall_status_intrpt_fall_status_21_qs; + logic intrpt_fall_status_intrpt_fall_status_21_wd; + logic intrpt_fall_status_intrpt_fall_status_21_we; + logic intrpt_fall_status_intrpt_fall_status_22_qs; + logic intrpt_fall_status_intrpt_fall_status_22_wd; + logic intrpt_fall_status_intrpt_fall_status_22_we; + logic intrpt_fall_status_intrpt_fall_status_23_qs; + logic intrpt_fall_status_intrpt_fall_status_23_wd; + logic intrpt_fall_status_intrpt_fall_status_23_we; + logic intrpt_fall_status_intrpt_fall_status_24_qs; + logic intrpt_fall_status_intrpt_fall_status_24_wd; + logic intrpt_fall_status_intrpt_fall_status_24_we; + logic intrpt_fall_status_intrpt_fall_status_25_qs; + logic intrpt_fall_status_intrpt_fall_status_25_wd; + logic intrpt_fall_status_intrpt_fall_status_25_we; + logic intrpt_fall_status_intrpt_fall_status_26_qs; + logic intrpt_fall_status_intrpt_fall_status_26_wd; + logic intrpt_fall_status_intrpt_fall_status_26_we; + logic intrpt_fall_status_intrpt_fall_status_27_qs; + logic intrpt_fall_status_intrpt_fall_status_27_wd; + logic intrpt_fall_status_intrpt_fall_status_27_we; + logic intrpt_fall_status_intrpt_fall_status_28_qs; + logic intrpt_fall_status_intrpt_fall_status_28_wd; + logic intrpt_fall_status_intrpt_fall_status_28_we; + logic intrpt_fall_status_intrpt_fall_status_29_qs; + logic intrpt_fall_status_intrpt_fall_status_29_wd; + logic intrpt_fall_status_intrpt_fall_status_29_we; + logic intrpt_fall_status_intrpt_fall_status_30_qs; + logic intrpt_fall_status_intrpt_fall_status_30_wd; + logic intrpt_fall_status_intrpt_fall_status_30_we; + logic intrpt_fall_status_intrpt_fall_status_31_qs; + logic intrpt_fall_status_intrpt_fall_status_31_wd; + logic intrpt_fall_status_intrpt_fall_status_31_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_0_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_0_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_0_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_1_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_1_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_1_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_2_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_2_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_2_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_3_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_3_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_3_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_4_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_4_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_4_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_5_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_5_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_5_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_6_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_6_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_6_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_7_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_7_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_7_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_8_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_8_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_8_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_9_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_9_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_9_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_10_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_10_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_10_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_11_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_11_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_11_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_12_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_12_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_12_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_13_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_13_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_13_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_14_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_14_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_14_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_15_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_15_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_15_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_16_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_16_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_16_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_17_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_17_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_17_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_18_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_18_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_18_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_19_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_19_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_19_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_20_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_20_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_20_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_21_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_21_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_21_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_22_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_22_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_22_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_23_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_23_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_23_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_24_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_24_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_24_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_25_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_25_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_25_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_26_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_26_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_26_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_27_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_27_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_27_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_28_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_28_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_28_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_29_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_29_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_29_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_30_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_30_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_30_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_31_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_31_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_31_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_0_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_0_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_0_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_1_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_1_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_1_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_2_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_2_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_2_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_3_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_3_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_3_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_4_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_4_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_4_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_5_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_5_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_5_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_6_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_6_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_6_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_7_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_7_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_7_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_8_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_8_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_8_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_9_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_9_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_9_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_10_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_10_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_10_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_11_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_11_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_11_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_12_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_12_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_12_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_13_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_13_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_13_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_14_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_14_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_14_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_15_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_15_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_15_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_16_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_16_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_16_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_17_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_17_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_17_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_18_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_18_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_18_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_19_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_19_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_19_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_20_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_20_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_20_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_21_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_21_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_21_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_22_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_22_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_22_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_23_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_23_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_23_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_24_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_24_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_24_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_25_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_25_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_25_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_26_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_26_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_26_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_27_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_27_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_27_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_28_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_28_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_28_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_29_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_29_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_29_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_30_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_30_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_30_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_31_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_31_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_31_we; + + // Register instances + // R[info]: V(True) + + // F[gpio_cnt]: 9:0 + prim_subreg_ext #( + .DW (10) + ) u_info_gpio_cnt ( + .re (info_gpio_cnt_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.info.gpio_cnt.d), + .qre (), + .qe (), + .q (), + .qs (info_gpio_cnt_qs) + ); + + + // F[version]: 19:10 + prim_subreg_ext #( + .DW (10) + ) u_info_version ( + .re (info_version_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.info.version.d), + .qre (), + .qe (), + .q (), + .qs (info_version_qs) + ); + + + // R[cfg]: V(False) + + // F[glbl_intrpt_mode]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_cfg_glbl_intrpt_mode ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_glbl_intrpt_mode_we), + .wd (cfg_glbl_intrpt_mode_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg.glbl_intrpt_mode.q ), + + // to register interface (read) + .qs (cfg_glbl_intrpt_mode_qs) + ); + + + // F[pin_lvl_intrpt_mode]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_cfg_pin_lvl_intrpt_mode ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_pin_lvl_intrpt_mode_we), + .wd (cfg_pin_lvl_intrpt_mode_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg.pin_lvl_intrpt_mode.q ), + + // to register interface (read) + .qs (cfg_pin_lvl_intrpt_mode_qs) + ); + + + + // Subregister 0 of Multireg gpio_mode + // R[gpio_mode_0]: V(False) + + // F[mode_0]: 1:0 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_0_we), + .wd (gpio_mode_0_mode_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[0].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_0_qs) + ); + + + // F[mode_1]: 3:2 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_1_we), + .wd (gpio_mode_0_mode_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[1].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_1_qs) + ); + + + // F[mode_2]: 5:4 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_2_we), + .wd (gpio_mode_0_mode_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[2].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_2_qs) + ); + + + // F[mode_3]: 7:6 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_3_we), + .wd (gpio_mode_0_mode_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[3].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_3_qs) + ); + + + // F[mode_4]: 9:8 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_4_we), + .wd (gpio_mode_0_mode_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[4].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_4_qs) + ); + + + // F[mode_5]: 11:10 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_5_we), + .wd (gpio_mode_0_mode_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[5].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_5_qs) + ); + + + // F[mode_6]: 13:12 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_6_we), + .wd (gpio_mode_0_mode_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[6].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_6_qs) + ); + + + // F[mode_7]: 15:14 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_7_we), + .wd (gpio_mode_0_mode_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[7].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_7_qs) + ); + + + // F[mode_8]: 17:16 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_8_we), + .wd (gpio_mode_0_mode_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[8].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_8_qs) + ); + + + // F[mode_9]: 19:18 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_9_we), + .wd (gpio_mode_0_mode_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[9].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_9_qs) + ); + + + // F[mode_10]: 21:20 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_10_we), + .wd (gpio_mode_0_mode_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[10].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_10_qs) + ); + + + // F[mode_11]: 23:22 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_11_we), + .wd (gpio_mode_0_mode_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[11].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_11_qs) + ); + + + // F[mode_12]: 25:24 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_12_we), + .wd (gpio_mode_0_mode_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[12].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_12_qs) + ); + + + // F[mode_13]: 27:26 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_13_we), + .wd (gpio_mode_0_mode_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[13].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_13_qs) + ); + + + // F[mode_14]: 29:28 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_14_we), + .wd (gpio_mode_0_mode_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[14].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_14_qs) + ); + + + // F[mode_15]: 31:30 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_15_we), + .wd (gpio_mode_0_mode_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[15].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_15_qs) + ); + + + // Subregister 16 of Multireg gpio_mode + // R[gpio_mode_1]: V(False) + + // F[mode_16]: 1:0 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_16_we), + .wd (gpio_mode_1_mode_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[16].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_16_qs) + ); + + + // F[mode_17]: 3:2 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_17_we), + .wd (gpio_mode_1_mode_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[17].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_17_qs) + ); + + + // F[mode_18]: 5:4 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_18_we), + .wd (gpio_mode_1_mode_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[18].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_18_qs) + ); + + + // F[mode_19]: 7:6 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_19_we), + .wd (gpio_mode_1_mode_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[19].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_19_qs) + ); + + + // F[mode_20]: 9:8 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_20_we), + .wd (gpio_mode_1_mode_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[20].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_20_qs) + ); + + + // F[mode_21]: 11:10 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_21_we), + .wd (gpio_mode_1_mode_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[21].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_21_qs) + ); + + + // F[mode_22]: 13:12 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_22_we), + .wd (gpio_mode_1_mode_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[22].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_22_qs) + ); + + + // F[mode_23]: 15:14 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_23_we), + .wd (gpio_mode_1_mode_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[23].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_23_qs) + ); + + + // F[mode_24]: 17:16 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_24_we), + .wd (gpio_mode_1_mode_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[24].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_24_qs) + ); + + + // F[mode_25]: 19:18 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_25_we), + .wd (gpio_mode_1_mode_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[25].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_25_qs) + ); + + + // F[mode_26]: 21:20 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_26_we), + .wd (gpio_mode_1_mode_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[26].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_26_qs) + ); + + + // F[mode_27]: 23:22 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_27_we), + .wd (gpio_mode_1_mode_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[27].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_27_qs) + ); + + + // F[mode_28]: 25:24 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_28_we), + .wd (gpio_mode_1_mode_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[28].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_28_qs) + ); + + + // F[mode_29]: 27:26 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_29_we), + .wd (gpio_mode_1_mode_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[29].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_29_qs) + ); + + + // F[mode_30]: 29:28 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_30_we), + .wd (gpio_mode_1_mode_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[30].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_30_qs) + ); + + + // F[mode_31]: 31:30 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_31_we), + .wd (gpio_mode_1_mode_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[31].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_31_qs) + ); + + + + + // Subregister 0 of Multireg gpio_en + // R[gpio_en]: V(False) + + // F[gpio_en_0]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_0_we), + .wd (gpio_en_gpio_en_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[0].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_0_qs) + ); + + + // F[gpio_en_1]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_1_we), + .wd (gpio_en_gpio_en_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[1].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_1_qs) + ); + + + // F[gpio_en_2]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_2_we), + .wd (gpio_en_gpio_en_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[2].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_2_qs) + ); + + + // F[gpio_en_3]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_3_we), + .wd (gpio_en_gpio_en_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[3].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_3_qs) + ); + + + // F[gpio_en_4]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_4_we), + .wd (gpio_en_gpio_en_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[4].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_4_qs) + ); + + + // F[gpio_en_5]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_5_we), + .wd (gpio_en_gpio_en_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[5].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_5_qs) + ); + + + // F[gpio_en_6]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_6_we), + .wd (gpio_en_gpio_en_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[6].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_6_qs) + ); + + + // F[gpio_en_7]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_7_we), + .wd (gpio_en_gpio_en_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[7].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_7_qs) + ); + + + // F[gpio_en_8]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_8_we), + .wd (gpio_en_gpio_en_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[8].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_8_qs) + ); + + + // F[gpio_en_9]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_9_we), + .wd (gpio_en_gpio_en_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[9].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_9_qs) + ); + + + // F[gpio_en_10]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_10_we), + .wd (gpio_en_gpio_en_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[10].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_10_qs) + ); + + + // F[gpio_en_11]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_11_we), + .wd (gpio_en_gpio_en_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[11].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_11_qs) + ); + + + // F[gpio_en_12]: 12:12 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_12_we), + .wd (gpio_en_gpio_en_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[12].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_12_qs) + ); + + + // F[gpio_en_13]: 13:13 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_13_we), + .wd (gpio_en_gpio_en_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[13].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_13_qs) + ); + + + // F[gpio_en_14]: 14:14 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_14_we), + .wd (gpio_en_gpio_en_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[14].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_14_qs) + ); + + + // F[gpio_en_15]: 15:15 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_15_we), + .wd (gpio_en_gpio_en_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[15].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_15_qs) + ); + + + // F[gpio_en_16]: 16:16 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_16_we), + .wd (gpio_en_gpio_en_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[16].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_16_qs) + ); + + + // F[gpio_en_17]: 17:17 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_17_we), + .wd (gpio_en_gpio_en_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[17].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_17_qs) + ); + + + // F[gpio_en_18]: 18:18 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_18_we), + .wd (gpio_en_gpio_en_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[18].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_18_qs) + ); + + + // F[gpio_en_19]: 19:19 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_19_we), + .wd (gpio_en_gpio_en_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[19].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_19_qs) + ); + + + // F[gpio_en_20]: 20:20 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_20_we), + .wd (gpio_en_gpio_en_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[20].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_20_qs) + ); + + + // F[gpio_en_21]: 21:21 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_21_we), + .wd (gpio_en_gpio_en_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[21].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_21_qs) + ); + + + // F[gpio_en_22]: 22:22 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_22_we), + .wd (gpio_en_gpio_en_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[22].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_22_qs) + ); + + + // F[gpio_en_23]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_23_we), + .wd (gpio_en_gpio_en_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[23].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_23_qs) + ); + + + // F[gpio_en_24]: 24:24 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_24_we), + .wd (gpio_en_gpio_en_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[24].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_24_qs) + ); + + + // F[gpio_en_25]: 25:25 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_25_we), + .wd (gpio_en_gpio_en_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[25].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_25_qs) + ); + + + // F[gpio_en_26]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_26_we), + .wd (gpio_en_gpio_en_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[26].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_26_qs) + ); + + + // F[gpio_en_27]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_27_we), + .wd (gpio_en_gpio_en_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[27].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_27_qs) + ); + + + // F[gpio_en_28]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_28_we), + .wd (gpio_en_gpio_en_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[28].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_28_qs) + ); + + + // F[gpio_en_29]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_29_we), + .wd (gpio_en_gpio_en_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[29].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_29_qs) + ); + + + // F[gpio_en_30]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_30_we), + .wd (gpio_en_gpio_en_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[30].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_30_qs) + ); + + + // F[gpio_en_31]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_31_we), + .wd (gpio_en_gpio_en_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[31].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_31_qs) + ); + + + + + // Subregister 0 of Multireg gpio_in + // R[gpio_in]: V(True) + + // F[gpio_in_0]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_0 ( + .re (gpio_in_gpio_in_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[0].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_0_qs) + ); + + + // F[gpio_in_1]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_1 ( + .re (gpio_in_gpio_in_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[1].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_1_qs) + ); + + + // F[gpio_in_2]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_2 ( + .re (gpio_in_gpio_in_2_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[2].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_2_qs) + ); + + + // F[gpio_in_3]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_3 ( + .re (gpio_in_gpio_in_3_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[3].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_3_qs) + ); + + + // F[gpio_in_4]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_4 ( + .re (gpio_in_gpio_in_4_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[4].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_4_qs) + ); + + + // F[gpio_in_5]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_5 ( + .re (gpio_in_gpio_in_5_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[5].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_5_qs) + ); + + + // F[gpio_in_6]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_6 ( + .re (gpio_in_gpio_in_6_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[6].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_6_qs) + ); + + + // F[gpio_in_7]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_7 ( + .re (gpio_in_gpio_in_7_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[7].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_7_qs) + ); + + + // F[gpio_in_8]: 8:8 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_8 ( + .re (gpio_in_gpio_in_8_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[8].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_8_qs) + ); + + + // F[gpio_in_9]: 9:9 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_9 ( + .re (gpio_in_gpio_in_9_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[9].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_9_qs) + ); + + + // F[gpio_in_10]: 10:10 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_10 ( + .re (gpio_in_gpio_in_10_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[10].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_10_qs) + ); + + + // F[gpio_in_11]: 11:11 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_11 ( + .re (gpio_in_gpio_in_11_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[11].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_11_qs) + ); + + + // F[gpio_in_12]: 12:12 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_12 ( + .re (gpio_in_gpio_in_12_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[12].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_12_qs) + ); + + + // F[gpio_in_13]: 13:13 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_13 ( + .re (gpio_in_gpio_in_13_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[13].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_13_qs) + ); + + + // F[gpio_in_14]: 14:14 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_14 ( + .re (gpio_in_gpio_in_14_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[14].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_14_qs) + ); + + + // F[gpio_in_15]: 15:15 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_15 ( + .re (gpio_in_gpio_in_15_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[15].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_15_qs) + ); + + + // F[gpio_in_16]: 16:16 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_16 ( + .re (gpio_in_gpio_in_16_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[16].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_16_qs) + ); + + + // F[gpio_in_17]: 17:17 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_17 ( + .re (gpio_in_gpio_in_17_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[17].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_17_qs) + ); + + + // F[gpio_in_18]: 18:18 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_18 ( + .re (gpio_in_gpio_in_18_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[18].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_18_qs) + ); + + + // F[gpio_in_19]: 19:19 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_19 ( + .re (gpio_in_gpio_in_19_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[19].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_19_qs) + ); + + + // F[gpio_in_20]: 20:20 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_20 ( + .re (gpio_in_gpio_in_20_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[20].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_20_qs) + ); + + + // F[gpio_in_21]: 21:21 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_21 ( + .re (gpio_in_gpio_in_21_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[21].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_21_qs) + ); + + + // F[gpio_in_22]: 22:22 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_22 ( + .re (gpio_in_gpio_in_22_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[22].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_22_qs) + ); + + + // F[gpio_in_23]: 23:23 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_23 ( + .re (gpio_in_gpio_in_23_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[23].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_23_qs) + ); + + + // F[gpio_in_24]: 24:24 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_24 ( + .re (gpio_in_gpio_in_24_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[24].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_24_qs) + ); + + + // F[gpio_in_25]: 25:25 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_25 ( + .re (gpio_in_gpio_in_25_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[25].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_25_qs) + ); + + + // F[gpio_in_26]: 26:26 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_26 ( + .re (gpio_in_gpio_in_26_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[26].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_26_qs) + ); + + + // F[gpio_in_27]: 27:27 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_27 ( + .re (gpio_in_gpio_in_27_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[27].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_27_qs) + ); + + + // F[gpio_in_28]: 28:28 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_28 ( + .re (gpio_in_gpio_in_28_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[28].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_28_qs) + ); + + + // F[gpio_in_29]: 29:29 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_29 ( + .re (gpio_in_gpio_in_29_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[29].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_29_qs) + ); + + + // F[gpio_in_30]: 30:30 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_30 ( + .re (gpio_in_gpio_in_30_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[30].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_30_qs) + ); + + + // F[gpio_in_31]: 31:31 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_31 ( + .re (gpio_in_gpio_in_31_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[31].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_31_qs) + ); + + + + + // Subregister 0 of Multireg gpio_out + // R[gpio_out]: V(False) + + // F[gpio_out_0]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_0_we), + .wd (gpio_out_gpio_out_0_wd), + + // from internal hardware + .de (hw2reg.gpio_out[0].de), + .d (hw2reg.gpio_out[0].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[0].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_0_qs) + ); + + + // F[gpio_out_1]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_1_we), + .wd (gpio_out_gpio_out_1_wd), + + // from internal hardware + .de (hw2reg.gpio_out[1].de), + .d (hw2reg.gpio_out[1].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[1].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_1_qs) + ); + + + // F[gpio_out_2]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_2_we), + .wd (gpio_out_gpio_out_2_wd), + + // from internal hardware + .de (hw2reg.gpio_out[2].de), + .d (hw2reg.gpio_out[2].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[2].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_2_qs) + ); + + + // F[gpio_out_3]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_3_we), + .wd (gpio_out_gpio_out_3_wd), + + // from internal hardware + .de (hw2reg.gpio_out[3].de), + .d (hw2reg.gpio_out[3].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[3].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_3_qs) + ); + + + // F[gpio_out_4]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_4_we), + .wd (gpio_out_gpio_out_4_wd), + + // from internal hardware + .de (hw2reg.gpio_out[4].de), + .d (hw2reg.gpio_out[4].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[4].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_4_qs) + ); + + + // F[gpio_out_5]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_5_we), + .wd (gpio_out_gpio_out_5_wd), + + // from internal hardware + .de (hw2reg.gpio_out[5].de), + .d (hw2reg.gpio_out[5].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[5].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_5_qs) + ); + + + // F[gpio_out_6]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_6_we), + .wd (gpio_out_gpio_out_6_wd), + + // from internal hardware + .de (hw2reg.gpio_out[6].de), + .d (hw2reg.gpio_out[6].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[6].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_6_qs) + ); + + + // F[gpio_out_7]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_7_we), + .wd (gpio_out_gpio_out_7_wd), + + // from internal hardware + .de (hw2reg.gpio_out[7].de), + .d (hw2reg.gpio_out[7].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[7].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_7_qs) + ); + + + // F[gpio_out_8]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_8_we), + .wd (gpio_out_gpio_out_8_wd), + + // from internal hardware + .de (hw2reg.gpio_out[8].de), + .d (hw2reg.gpio_out[8].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[8].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_8_qs) + ); + + + // F[gpio_out_9]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_9_we), + .wd (gpio_out_gpio_out_9_wd), + + // from internal hardware + .de (hw2reg.gpio_out[9].de), + .d (hw2reg.gpio_out[9].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[9].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_9_qs) + ); + + + // F[gpio_out_10]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_10_we), + .wd (gpio_out_gpio_out_10_wd), + + // from internal hardware + .de (hw2reg.gpio_out[10].de), + .d (hw2reg.gpio_out[10].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[10].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_10_qs) + ); + + + // F[gpio_out_11]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_11_we), + .wd (gpio_out_gpio_out_11_wd), + + // from internal hardware + .de (hw2reg.gpio_out[11].de), + .d (hw2reg.gpio_out[11].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[11].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_11_qs) + ); + + + // F[gpio_out_12]: 12:12 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_12_we), + .wd (gpio_out_gpio_out_12_wd), + + // from internal hardware + .de (hw2reg.gpio_out[12].de), + .d (hw2reg.gpio_out[12].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[12].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_12_qs) + ); + + + // F[gpio_out_13]: 13:13 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_13_we), + .wd (gpio_out_gpio_out_13_wd), + + // from internal hardware + .de (hw2reg.gpio_out[13].de), + .d (hw2reg.gpio_out[13].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[13].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_13_qs) + ); + + + // F[gpio_out_14]: 14:14 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_14_we), + .wd (gpio_out_gpio_out_14_wd), + + // from internal hardware + .de (hw2reg.gpio_out[14].de), + .d (hw2reg.gpio_out[14].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[14].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_14_qs) + ); + + + // F[gpio_out_15]: 15:15 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_15_we), + .wd (gpio_out_gpio_out_15_wd), + + // from internal hardware + .de (hw2reg.gpio_out[15].de), + .d (hw2reg.gpio_out[15].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[15].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_15_qs) + ); + + + // F[gpio_out_16]: 16:16 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_16_we), + .wd (gpio_out_gpio_out_16_wd), + + // from internal hardware + .de (hw2reg.gpio_out[16].de), + .d (hw2reg.gpio_out[16].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[16].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_16_qs) + ); + + + // F[gpio_out_17]: 17:17 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_17_we), + .wd (gpio_out_gpio_out_17_wd), + + // from internal hardware + .de (hw2reg.gpio_out[17].de), + .d (hw2reg.gpio_out[17].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[17].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_17_qs) + ); + + + // F[gpio_out_18]: 18:18 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_18_we), + .wd (gpio_out_gpio_out_18_wd), + + // from internal hardware + .de (hw2reg.gpio_out[18].de), + .d (hw2reg.gpio_out[18].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[18].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_18_qs) + ); + + + // F[gpio_out_19]: 19:19 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_19_we), + .wd (gpio_out_gpio_out_19_wd), + + // from internal hardware + .de (hw2reg.gpio_out[19].de), + .d (hw2reg.gpio_out[19].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[19].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_19_qs) + ); + + + // F[gpio_out_20]: 20:20 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_20_we), + .wd (gpio_out_gpio_out_20_wd), + + // from internal hardware + .de (hw2reg.gpio_out[20].de), + .d (hw2reg.gpio_out[20].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[20].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_20_qs) + ); + + + // F[gpio_out_21]: 21:21 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_21_we), + .wd (gpio_out_gpio_out_21_wd), + + // from internal hardware + .de (hw2reg.gpio_out[21].de), + .d (hw2reg.gpio_out[21].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[21].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_21_qs) + ); + + + // F[gpio_out_22]: 22:22 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_22_we), + .wd (gpio_out_gpio_out_22_wd), + + // from internal hardware + .de (hw2reg.gpio_out[22].de), + .d (hw2reg.gpio_out[22].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[22].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_22_qs) + ); + + + // F[gpio_out_23]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_23_we), + .wd (gpio_out_gpio_out_23_wd), + + // from internal hardware + .de (hw2reg.gpio_out[23].de), + .d (hw2reg.gpio_out[23].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[23].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_23_qs) + ); + + + // F[gpio_out_24]: 24:24 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_24_we), + .wd (gpio_out_gpio_out_24_wd), + + // from internal hardware + .de (hw2reg.gpio_out[24].de), + .d (hw2reg.gpio_out[24].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[24].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_24_qs) + ); + + + // F[gpio_out_25]: 25:25 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_25_we), + .wd (gpio_out_gpio_out_25_wd), + + // from internal hardware + .de (hw2reg.gpio_out[25].de), + .d (hw2reg.gpio_out[25].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[25].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_25_qs) + ); + + + // F[gpio_out_26]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_26_we), + .wd (gpio_out_gpio_out_26_wd), + + // from internal hardware + .de (hw2reg.gpio_out[26].de), + .d (hw2reg.gpio_out[26].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[26].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_26_qs) + ); + + + // F[gpio_out_27]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_27_we), + .wd (gpio_out_gpio_out_27_wd), + + // from internal hardware + .de (hw2reg.gpio_out[27].de), + .d (hw2reg.gpio_out[27].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[27].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_27_qs) + ); + + + // F[gpio_out_28]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_28_we), + .wd (gpio_out_gpio_out_28_wd), + + // from internal hardware + .de (hw2reg.gpio_out[28].de), + .d (hw2reg.gpio_out[28].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[28].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_28_qs) + ); + + + // F[gpio_out_29]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_29_we), + .wd (gpio_out_gpio_out_29_wd), + + // from internal hardware + .de (hw2reg.gpio_out[29].de), + .d (hw2reg.gpio_out[29].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[29].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_29_qs) + ); + + + // F[gpio_out_30]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_30_we), + .wd (gpio_out_gpio_out_30_wd), + + // from internal hardware + .de (hw2reg.gpio_out[30].de), + .d (hw2reg.gpio_out[30].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[30].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_30_qs) + ); + + + // F[gpio_out_31]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_31_we), + .wd (gpio_out_gpio_out_31_wd), + + // from internal hardware + .de (hw2reg.gpio_out[31].de), + .d (hw2reg.gpio_out[31].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[31].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_31_qs) + ); + + + + + // Subregister 0 of Multireg gpio_set + // R[gpio_set]: V(True) + + // F[gpio_set_0]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_0 ( + .re (1'b0), + .we (gpio_set_gpio_set_0_we), + .wd (gpio_set_gpio_set_0_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[0].qe), + .q (reg2hw.gpio_set[0].q ), + .qs () + ); + + + // F[gpio_set_1]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_1 ( + .re (1'b0), + .we (gpio_set_gpio_set_1_we), + .wd (gpio_set_gpio_set_1_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[1].qe), + .q (reg2hw.gpio_set[1].q ), + .qs () + ); + + + // F[gpio_set_2]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_2 ( + .re (1'b0), + .we (gpio_set_gpio_set_2_we), + .wd (gpio_set_gpio_set_2_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[2].qe), + .q (reg2hw.gpio_set[2].q ), + .qs () + ); + + + // F[gpio_set_3]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_3 ( + .re (1'b0), + .we (gpio_set_gpio_set_3_we), + .wd (gpio_set_gpio_set_3_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[3].qe), + .q (reg2hw.gpio_set[3].q ), + .qs () + ); + + + // F[gpio_set_4]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_4 ( + .re (1'b0), + .we (gpio_set_gpio_set_4_we), + .wd (gpio_set_gpio_set_4_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[4].qe), + .q (reg2hw.gpio_set[4].q ), + .qs () + ); + + + // F[gpio_set_5]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_5 ( + .re (1'b0), + .we (gpio_set_gpio_set_5_we), + .wd (gpio_set_gpio_set_5_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[5].qe), + .q (reg2hw.gpio_set[5].q ), + .qs () + ); + + + // F[gpio_set_6]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_6 ( + .re (1'b0), + .we (gpio_set_gpio_set_6_we), + .wd (gpio_set_gpio_set_6_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[6].qe), + .q (reg2hw.gpio_set[6].q ), + .qs () + ); + + + // F[gpio_set_7]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_7 ( + .re (1'b0), + .we (gpio_set_gpio_set_7_we), + .wd (gpio_set_gpio_set_7_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[7].qe), + .q (reg2hw.gpio_set[7].q ), + .qs () + ); + + + // F[gpio_set_8]: 8:8 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_8 ( + .re (1'b0), + .we (gpio_set_gpio_set_8_we), + .wd (gpio_set_gpio_set_8_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[8].qe), + .q (reg2hw.gpio_set[8].q ), + .qs () + ); + + + // F[gpio_set_9]: 9:9 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_9 ( + .re (1'b0), + .we (gpio_set_gpio_set_9_we), + .wd (gpio_set_gpio_set_9_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[9].qe), + .q (reg2hw.gpio_set[9].q ), + .qs () + ); + + + // F[gpio_set_10]: 10:10 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_10 ( + .re (1'b0), + .we (gpio_set_gpio_set_10_we), + .wd (gpio_set_gpio_set_10_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[10].qe), + .q (reg2hw.gpio_set[10].q ), + .qs () + ); + + + // F[gpio_set_11]: 11:11 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_11 ( + .re (1'b0), + .we (gpio_set_gpio_set_11_we), + .wd (gpio_set_gpio_set_11_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[11].qe), + .q (reg2hw.gpio_set[11].q ), + .qs () + ); + + + // F[gpio_set_12]: 12:12 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_12 ( + .re (1'b0), + .we (gpio_set_gpio_set_12_we), + .wd (gpio_set_gpio_set_12_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[12].qe), + .q (reg2hw.gpio_set[12].q ), + .qs () + ); + + + // F[gpio_set_13]: 13:13 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_13 ( + .re (1'b0), + .we (gpio_set_gpio_set_13_we), + .wd (gpio_set_gpio_set_13_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[13].qe), + .q (reg2hw.gpio_set[13].q ), + .qs () + ); + + + // F[gpio_set_14]: 14:14 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_14 ( + .re (1'b0), + .we (gpio_set_gpio_set_14_we), + .wd (gpio_set_gpio_set_14_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[14].qe), + .q (reg2hw.gpio_set[14].q ), + .qs () + ); + + + // F[gpio_set_15]: 15:15 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_15 ( + .re (1'b0), + .we (gpio_set_gpio_set_15_we), + .wd (gpio_set_gpio_set_15_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[15].qe), + .q (reg2hw.gpio_set[15].q ), + .qs () + ); + + + // F[gpio_set_16]: 16:16 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_16 ( + .re (1'b0), + .we (gpio_set_gpio_set_16_we), + .wd (gpio_set_gpio_set_16_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[16].qe), + .q (reg2hw.gpio_set[16].q ), + .qs () + ); + + + // F[gpio_set_17]: 17:17 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_17 ( + .re (1'b0), + .we (gpio_set_gpio_set_17_we), + .wd (gpio_set_gpio_set_17_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[17].qe), + .q (reg2hw.gpio_set[17].q ), + .qs () + ); + + + // F[gpio_set_18]: 18:18 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_18 ( + .re (1'b0), + .we (gpio_set_gpio_set_18_we), + .wd (gpio_set_gpio_set_18_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[18].qe), + .q (reg2hw.gpio_set[18].q ), + .qs () + ); + + + // F[gpio_set_19]: 19:19 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_19 ( + .re (1'b0), + .we (gpio_set_gpio_set_19_we), + .wd (gpio_set_gpio_set_19_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[19].qe), + .q (reg2hw.gpio_set[19].q ), + .qs () + ); + + + // F[gpio_set_20]: 20:20 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_20 ( + .re (1'b0), + .we (gpio_set_gpio_set_20_we), + .wd (gpio_set_gpio_set_20_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[20].qe), + .q (reg2hw.gpio_set[20].q ), + .qs () + ); + + + // F[gpio_set_21]: 21:21 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_21 ( + .re (1'b0), + .we (gpio_set_gpio_set_21_we), + .wd (gpio_set_gpio_set_21_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[21].qe), + .q (reg2hw.gpio_set[21].q ), + .qs () + ); + + + // F[gpio_set_22]: 22:22 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_22 ( + .re (1'b0), + .we (gpio_set_gpio_set_22_we), + .wd (gpio_set_gpio_set_22_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[22].qe), + .q (reg2hw.gpio_set[22].q ), + .qs () + ); + + + // F[gpio_set_23]: 23:23 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_23 ( + .re (1'b0), + .we (gpio_set_gpio_set_23_we), + .wd (gpio_set_gpio_set_23_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[23].qe), + .q (reg2hw.gpio_set[23].q ), + .qs () + ); + + + // F[gpio_set_24]: 24:24 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_24 ( + .re (1'b0), + .we (gpio_set_gpio_set_24_we), + .wd (gpio_set_gpio_set_24_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[24].qe), + .q (reg2hw.gpio_set[24].q ), + .qs () + ); + + + // F[gpio_set_25]: 25:25 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_25 ( + .re (1'b0), + .we (gpio_set_gpio_set_25_we), + .wd (gpio_set_gpio_set_25_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[25].qe), + .q (reg2hw.gpio_set[25].q ), + .qs () + ); + + + // F[gpio_set_26]: 26:26 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_26 ( + .re (1'b0), + .we (gpio_set_gpio_set_26_we), + .wd (gpio_set_gpio_set_26_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[26].qe), + .q (reg2hw.gpio_set[26].q ), + .qs () + ); + + + // F[gpio_set_27]: 27:27 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_27 ( + .re (1'b0), + .we (gpio_set_gpio_set_27_we), + .wd (gpio_set_gpio_set_27_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[27].qe), + .q (reg2hw.gpio_set[27].q ), + .qs () + ); + + + // F[gpio_set_28]: 28:28 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_28 ( + .re (1'b0), + .we (gpio_set_gpio_set_28_we), + .wd (gpio_set_gpio_set_28_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[28].qe), + .q (reg2hw.gpio_set[28].q ), + .qs () + ); + + + // F[gpio_set_29]: 29:29 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_29 ( + .re (1'b0), + .we (gpio_set_gpio_set_29_we), + .wd (gpio_set_gpio_set_29_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[29].qe), + .q (reg2hw.gpio_set[29].q ), + .qs () + ); + + + // F[gpio_set_30]: 30:30 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_30 ( + .re (1'b0), + .we (gpio_set_gpio_set_30_we), + .wd (gpio_set_gpio_set_30_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[30].qe), + .q (reg2hw.gpio_set[30].q ), + .qs () + ); + + + // F[gpio_set_31]: 31:31 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_31 ( + .re (1'b0), + .we (gpio_set_gpio_set_31_we), + .wd (gpio_set_gpio_set_31_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[31].qe), + .q (reg2hw.gpio_set[31].q ), + .qs () + ); + + + + + // Subregister 0 of Multireg gpio_clear + // R[gpio_clear]: V(True) + + // F[gpio_clear_0]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_0 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_0_we), + .wd (gpio_clear_gpio_clear_0_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[0].qe), + .q (reg2hw.gpio_clear[0].q ), + .qs () + ); + + + // F[gpio_clear_1]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_1 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_1_we), + .wd (gpio_clear_gpio_clear_1_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[1].qe), + .q (reg2hw.gpio_clear[1].q ), + .qs () + ); + + + // F[gpio_clear_2]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_2 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_2_we), + .wd (gpio_clear_gpio_clear_2_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[2].qe), + .q (reg2hw.gpio_clear[2].q ), + .qs () + ); + + + // F[gpio_clear_3]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_3 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_3_we), + .wd (gpio_clear_gpio_clear_3_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[3].qe), + .q (reg2hw.gpio_clear[3].q ), + .qs () + ); + + + // F[gpio_clear_4]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_4 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_4_we), + .wd (gpio_clear_gpio_clear_4_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[4].qe), + .q (reg2hw.gpio_clear[4].q ), + .qs () + ); + + + // F[gpio_clear_5]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_5 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_5_we), + .wd (gpio_clear_gpio_clear_5_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[5].qe), + .q (reg2hw.gpio_clear[5].q ), + .qs () + ); + + + // F[gpio_clear_6]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_6 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_6_we), + .wd (gpio_clear_gpio_clear_6_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[6].qe), + .q (reg2hw.gpio_clear[6].q ), + .qs () + ); + + + // F[gpio_clear_7]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_7 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_7_we), + .wd (gpio_clear_gpio_clear_7_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[7].qe), + .q (reg2hw.gpio_clear[7].q ), + .qs () + ); + + + // F[gpio_clear_8]: 8:8 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_8 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_8_we), + .wd (gpio_clear_gpio_clear_8_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[8].qe), + .q (reg2hw.gpio_clear[8].q ), + .qs () + ); + + + // F[gpio_clear_9]: 9:9 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_9 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_9_we), + .wd (gpio_clear_gpio_clear_9_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[9].qe), + .q (reg2hw.gpio_clear[9].q ), + .qs () + ); + + + // F[gpio_clear_10]: 10:10 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_10 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_10_we), + .wd (gpio_clear_gpio_clear_10_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[10].qe), + .q (reg2hw.gpio_clear[10].q ), + .qs () + ); + + + // F[gpio_clear_11]: 11:11 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_11 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_11_we), + .wd (gpio_clear_gpio_clear_11_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[11].qe), + .q (reg2hw.gpio_clear[11].q ), + .qs () + ); + + + // F[gpio_clear_12]: 12:12 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_12 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_12_we), + .wd (gpio_clear_gpio_clear_12_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[12].qe), + .q (reg2hw.gpio_clear[12].q ), + .qs () + ); + + + // F[gpio_clear_13]: 13:13 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_13 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_13_we), + .wd (gpio_clear_gpio_clear_13_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[13].qe), + .q (reg2hw.gpio_clear[13].q ), + .qs () + ); + + + // F[gpio_clear_14]: 14:14 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_14 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_14_we), + .wd (gpio_clear_gpio_clear_14_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[14].qe), + .q (reg2hw.gpio_clear[14].q ), + .qs () + ); + + + // F[gpio_clear_15]: 15:15 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_15 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_15_we), + .wd (gpio_clear_gpio_clear_15_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[15].qe), + .q (reg2hw.gpio_clear[15].q ), + .qs () + ); + + + // F[gpio_clear_16]: 16:16 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_16 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_16_we), + .wd (gpio_clear_gpio_clear_16_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[16].qe), + .q (reg2hw.gpio_clear[16].q ), + .qs () + ); + + + // F[gpio_clear_17]: 17:17 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_17 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_17_we), + .wd (gpio_clear_gpio_clear_17_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[17].qe), + .q (reg2hw.gpio_clear[17].q ), + .qs () + ); + + + // F[gpio_clear_18]: 18:18 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_18 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_18_we), + .wd (gpio_clear_gpio_clear_18_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[18].qe), + .q (reg2hw.gpio_clear[18].q ), + .qs () + ); + + + // F[gpio_clear_19]: 19:19 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_19 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_19_we), + .wd (gpio_clear_gpio_clear_19_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[19].qe), + .q (reg2hw.gpio_clear[19].q ), + .qs () + ); + + + // F[gpio_clear_20]: 20:20 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_20 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_20_we), + .wd (gpio_clear_gpio_clear_20_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[20].qe), + .q (reg2hw.gpio_clear[20].q ), + .qs () + ); + + + // F[gpio_clear_21]: 21:21 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_21 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_21_we), + .wd (gpio_clear_gpio_clear_21_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[21].qe), + .q (reg2hw.gpio_clear[21].q ), + .qs () + ); + + + // F[gpio_clear_22]: 22:22 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_22 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_22_we), + .wd (gpio_clear_gpio_clear_22_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[22].qe), + .q (reg2hw.gpio_clear[22].q ), + .qs () + ); + + + // F[gpio_clear_23]: 23:23 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_23 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_23_we), + .wd (gpio_clear_gpio_clear_23_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[23].qe), + .q (reg2hw.gpio_clear[23].q ), + .qs () + ); + + + // F[gpio_clear_24]: 24:24 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_24 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_24_we), + .wd (gpio_clear_gpio_clear_24_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[24].qe), + .q (reg2hw.gpio_clear[24].q ), + .qs () + ); + + + // F[gpio_clear_25]: 25:25 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_25 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_25_we), + .wd (gpio_clear_gpio_clear_25_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[25].qe), + .q (reg2hw.gpio_clear[25].q ), + .qs () + ); + + + // F[gpio_clear_26]: 26:26 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_26 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_26_we), + .wd (gpio_clear_gpio_clear_26_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[26].qe), + .q (reg2hw.gpio_clear[26].q ), + .qs () + ); + + + // F[gpio_clear_27]: 27:27 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_27 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_27_we), + .wd (gpio_clear_gpio_clear_27_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[27].qe), + .q (reg2hw.gpio_clear[27].q ), + .qs () + ); + + + // F[gpio_clear_28]: 28:28 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_28 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_28_we), + .wd (gpio_clear_gpio_clear_28_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[28].qe), + .q (reg2hw.gpio_clear[28].q ), + .qs () + ); + + + // F[gpio_clear_29]: 29:29 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_29 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_29_we), + .wd (gpio_clear_gpio_clear_29_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[29].qe), + .q (reg2hw.gpio_clear[29].q ), + .qs () + ); + + + // F[gpio_clear_30]: 30:30 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_30 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_30_we), + .wd (gpio_clear_gpio_clear_30_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[30].qe), + .q (reg2hw.gpio_clear[30].q ), + .qs () + ); + + + // F[gpio_clear_31]: 31:31 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_31 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_31_we), + .wd (gpio_clear_gpio_clear_31_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[31].qe), + .q (reg2hw.gpio_clear[31].q ), + .qs () + ); + + + + + // Subregister 0 of Multireg gpio_toggle + // R[gpio_toggle]: V(True) + + // F[gpio_toggle_0]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_0 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_0_we), + .wd (gpio_toggle_gpio_toggle_0_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[0].qe), + .q (reg2hw.gpio_toggle[0].q ), + .qs () + ); + + + // F[gpio_toggle_1]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_1 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_1_we), + .wd (gpio_toggle_gpio_toggle_1_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[1].qe), + .q (reg2hw.gpio_toggle[1].q ), + .qs () + ); + + + // F[gpio_toggle_2]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_2 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_2_we), + .wd (gpio_toggle_gpio_toggle_2_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[2].qe), + .q (reg2hw.gpio_toggle[2].q ), + .qs () + ); + + + // F[gpio_toggle_3]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_3 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_3_we), + .wd (gpio_toggle_gpio_toggle_3_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[3].qe), + .q (reg2hw.gpio_toggle[3].q ), + .qs () + ); + + + // F[gpio_toggle_4]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_4 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_4_we), + .wd (gpio_toggle_gpio_toggle_4_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[4].qe), + .q (reg2hw.gpio_toggle[4].q ), + .qs () + ); + + + // F[gpio_toggle_5]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_5 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_5_we), + .wd (gpio_toggle_gpio_toggle_5_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[5].qe), + .q (reg2hw.gpio_toggle[5].q ), + .qs () + ); + + + // F[gpio_toggle_6]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_6 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_6_we), + .wd (gpio_toggle_gpio_toggle_6_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[6].qe), + .q (reg2hw.gpio_toggle[6].q ), + .qs () + ); + + + // F[gpio_toggle_7]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_7 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_7_we), + .wd (gpio_toggle_gpio_toggle_7_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[7].qe), + .q (reg2hw.gpio_toggle[7].q ), + .qs () + ); + + + // F[gpio_toggle_8]: 8:8 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_8 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_8_we), + .wd (gpio_toggle_gpio_toggle_8_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[8].qe), + .q (reg2hw.gpio_toggle[8].q ), + .qs () + ); + + + // F[gpio_toggle_9]: 9:9 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_9 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_9_we), + .wd (gpio_toggle_gpio_toggle_9_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[9].qe), + .q (reg2hw.gpio_toggle[9].q ), + .qs () + ); + + + // F[gpio_toggle_10]: 10:10 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_10 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_10_we), + .wd (gpio_toggle_gpio_toggle_10_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[10].qe), + .q (reg2hw.gpio_toggle[10].q ), + .qs () + ); + + + // F[gpio_toggle_11]: 11:11 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_11 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_11_we), + .wd (gpio_toggle_gpio_toggle_11_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[11].qe), + .q (reg2hw.gpio_toggle[11].q ), + .qs () + ); + + + // F[gpio_toggle_12]: 12:12 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_12 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_12_we), + .wd (gpio_toggle_gpio_toggle_12_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[12].qe), + .q (reg2hw.gpio_toggle[12].q ), + .qs () + ); + + + // F[gpio_toggle_13]: 13:13 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_13 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_13_we), + .wd (gpio_toggle_gpio_toggle_13_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[13].qe), + .q (reg2hw.gpio_toggle[13].q ), + .qs () + ); + + + // F[gpio_toggle_14]: 14:14 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_14 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_14_we), + .wd (gpio_toggle_gpio_toggle_14_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[14].qe), + .q (reg2hw.gpio_toggle[14].q ), + .qs () + ); + + + // F[gpio_toggle_15]: 15:15 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_15 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_15_we), + .wd (gpio_toggle_gpio_toggle_15_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[15].qe), + .q (reg2hw.gpio_toggle[15].q ), + .qs () + ); + + + // F[gpio_toggle_16]: 16:16 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_16 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_16_we), + .wd (gpio_toggle_gpio_toggle_16_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[16].qe), + .q (reg2hw.gpio_toggle[16].q ), + .qs () + ); + + + // F[gpio_toggle_17]: 17:17 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_17 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_17_we), + .wd (gpio_toggle_gpio_toggle_17_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[17].qe), + .q (reg2hw.gpio_toggle[17].q ), + .qs () + ); + + + // F[gpio_toggle_18]: 18:18 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_18 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_18_we), + .wd (gpio_toggle_gpio_toggle_18_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[18].qe), + .q (reg2hw.gpio_toggle[18].q ), + .qs () + ); + + + // F[gpio_toggle_19]: 19:19 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_19 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_19_we), + .wd (gpio_toggle_gpio_toggle_19_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[19].qe), + .q (reg2hw.gpio_toggle[19].q ), + .qs () + ); + + + // F[gpio_toggle_20]: 20:20 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_20 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_20_we), + .wd (gpio_toggle_gpio_toggle_20_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[20].qe), + .q (reg2hw.gpio_toggle[20].q ), + .qs () + ); + + + // F[gpio_toggle_21]: 21:21 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_21 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_21_we), + .wd (gpio_toggle_gpio_toggle_21_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[21].qe), + .q (reg2hw.gpio_toggle[21].q ), + .qs () + ); + + + // F[gpio_toggle_22]: 22:22 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_22 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_22_we), + .wd (gpio_toggle_gpio_toggle_22_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[22].qe), + .q (reg2hw.gpio_toggle[22].q ), + .qs () + ); + + + // F[gpio_toggle_23]: 23:23 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_23 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_23_we), + .wd (gpio_toggle_gpio_toggle_23_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[23].qe), + .q (reg2hw.gpio_toggle[23].q ), + .qs () + ); + + + // F[gpio_toggle_24]: 24:24 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_24 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_24_we), + .wd (gpio_toggle_gpio_toggle_24_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[24].qe), + .q (reg2hw.gpio_toggle[24].q ), + .qs () + ); + + + // F[gpio_toggle_25]: 25:25 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_25 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_25_we), + .wd (gpio_toggle_gpio_toggle_25_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[25].qe), + .q (reg2hw.gpio_toggle[25].q ), + .qs () + ); + + + // F[gpio_toggle_26]: 26:26 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_26 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_26_we), + .wd (gpio_toggle_gpio_toggle_26_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[26].qe), + .q (reg2hw.gpio_toggle[26].q ), + .qs () + ); + + + // F[gpio_toggle_27]: 27:27 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_27 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_27_we), + .wd (gpio_toggle_gpio_toggle_27_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[27].qe), + .q (reg2hw.gpio_toggle[27].q ), + .qs () + ); + + + // F[gpio_toggle_28]: 28:28 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_28 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_28_we), + .wd (gpio_toggle_gpio_toggle_28_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[28].qe), + .q (reg2hw.gpio_toggle[28].q ), + .qs () + ); + + + // F[gpio_toggle_29]: 29:29 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_29 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_29_we), + .wd (gpio_toggle_gpio_toggle_29_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[29].qe), + .q (reg2hw.gpio_toggle[29].q ), + .qs () + ); + + + // F[gpio_toggle_30]: 30:30 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_30 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_30_we), + .wd (gpio_toggle_gpio_toggle_30_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[30].qe), + .q (reg2hw.gpio_toggle[30].q ), + .qs () + ); + + + // F[gpio_toggle_31]: 31:31 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_31 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_31_we), + .wd (gpio_toggle_gpio_toggle_31_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[31].qe), + .q (reg2hw.gpio_toggle[31].q ), + .qs () + ); + + + + + // Subregister 0 of Multireg intrpt_rise_en + // R[intrpt_rise_en]: V(False) + + // F[intrpt_rise_en_0]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_0_we), + .wd (intrpt_rise_en_intrpt_rise_en_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[0].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_0_qs) + ); + + + // F[intrpt_rise_en_1]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_1_we), + .wd (intrpt_rise_en_intrpt_rise_en_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[1].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_1_qs) + ); + + + // F[intrpt_rise_en_2]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_2_we), + .wd (intrpt_rise_en_intrpt_rise_en_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[2].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_2_qs) + ); + + + // F[intrpt_rise_en_3]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_3_we), + .wd (intrpt_rise_en_intrpt_rise_en_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[3].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_3_qs) + ); + + + // F[intrpt_rise_en_4]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_4_we), + .wd (intrpt_rise_en_intrpt_rise_en_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[4].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_4_qs) + ); + + + // F[intrpt_rise_en_5]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_5_we), + .wd (intrpt_rise_en_intrpt_rise_en_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[5].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_5_qs) + ); + + + // F[intrpt_rise_en_6]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_6_we), + .wd (intrpt_rise_en_intrpt_rise_en_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[6].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_6_qs) + ); + + + // F[intrpt_rise_en_7]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_7_we), + .wd (intrpt_rise_en_intrpt_rise_en_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[7].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_7_qs) + ); + + + // F[intrpt_rise_en_8]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_8_we), + .wd (intrpt_rise_en_intrpt_rise_en_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[8].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_8_qs) + ); + + + // F[intrpt_rise_en_9]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_9_we), + .wd (intrpt_rise_en_intrpt_rise_en_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[9].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_9_qs) + ); + + + // F[intrpt_rise_en_10]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_10_we), + .wd (intrpt_rise_en_intrpt_rise_en_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[10].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_10_qs) + ); + + + // F[intrpt_rise_en_11]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_11_we), + .wd (intrpt_rise_en_intrpt_rise_en_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[11].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_11_qs) + ); + + + // F[intrpt_rise_en_12]: 12:12 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_12_we), + .wd (intrpt_rise_en_intrpt_rise_en_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[12].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_12_qs) + ); + + + // F[intrpt_rise_en_13]: 13:13 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_13_we), + .wd (intrpt_rise_en_intrpt_rise_en_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[13].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_13_qs) + ); + + + // F[intrpt_rise_en_14]: 14:14 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_14_we), + .wd (intrpt_rise_en_intrpt_rise_en_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[14].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_14_qs) + ); + + + // F[intrpt_rise_en_15]: 15:15 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_15_we), + .wd (intrpt_rise_en_intrpt_rise_en_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[15].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_15_qs) + ); + + + // F[intrpt_rise_en_16]: 16:16 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_16_we), + .wd (intrpt_rise_en_intrpt_rise_en_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[16].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_16_qs) + ); + + + // F[intrpt_rise_en_17]: 17:17 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_17_we), + .wd (intrpt_rise_en_intrpt_rise_en_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[17].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_17_qs) + ); + + + // F[intrpt_rise_en_18]: 18:18 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_18_we), + .wd (intrpt_rise_en_intrpt_rise_en_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[18].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_18_qs) + ); + + + // F[intrpt_rise_en_19]: 19:19 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_19_we), + .wd (intrpt_rise_en_intrpt_rise_en_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[19].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_19_qs) + ); + + + // F[intrpt_rise_en_20]: 20:20 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_20_we), + .wd (intrpt_rise_en_intrpt_rise_en_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[20].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_20_qs) + ); + + + // F[intrpt_rise_en_21]: 21:21 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_21_we), + .wd (intrpt_rise_en_intrpt_rise_en_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[21].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_21_qs) + ); + + + // F[intrpt_rise_en_22]: 22:22 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_22_we), + .wd (intrpt_rise_en_intrpt_rise_en_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[22].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_22_qs) + ); + + + // F[intrpt_rise_en_23]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_23_we), + .wd (intrpt_rise_en_intrpt_rise_en_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[23].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_23_qs) + ); + + + // F[intrpt_rise_en_24]: 24:24 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_24_we), + .wd (intrpt_rise_en_intrpt_rise_en_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[24].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_24_qs) + ); + + + // F[intrpt_rise_en_25]: 25:25 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_25_we), + .wd (intrpt_rise_en_intrpt_rise_en_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[25].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_25_qs) + ); + + + // F[intrpt_rise_en_26]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_26_we), + .wd (intrpt_rise_en_intrpt_rise_en_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[26].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_26_qs) + ); + + + // F[intrpt_rise_en_27]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_27_we), + .wd (intrpt_rise_en_intrpt_rise_en_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[27].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_27_qs) + ); + + + // F[intrpt_rise_en_28]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_28_we), + .wd (intrpt_rise_en_intrpt_rise_en_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[28].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_28_qs) + ); + + + // F[intrpt_rise_en_29]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_29_we), + .wd (intrpt_rise_en_intrpt_rise_en_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[29].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_29_qs) + ); + + + // F[intrpt_rise_en_30]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_30_we), + .wd (intrpt_rise_en_intrpt_rise_en_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[30].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_30_qs) + ); + + + // F[intrpt_rise_en_31]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_31_we), + .wd (intrpt_rise_en_intrpt_rise_en_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[31].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_31_qs) + ); + + + + + // Subregister 0 of Multireg intrpt_fall_en + // R[intrpt_fall_en]: V(False) + + // F[intrpt_fall_en_0]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_0_we), + .wd (intrpt_fall_en_intrpt_fall_en_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[0].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_0_qs) + ); + + + // F[intrpt_fall_en_1]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_1_we), + .wd (intrpt_fall_en_intrpt_fall_en_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[1].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_1_qs) + ); + + + // F[intrpt_fall_en_2]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_2_we), + .wd (intrpt_fall_en_intrpt_fall_en_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[2].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_2_qs) + ); + + + // F[intrpt_fall_en_3]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_3_we), + .wd (intrpt_fall_en_intrpt_fall_en_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[3].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_3_qs) + ); + + + // F[intrpt_fall_en_4]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_4_we), + .wd (intrpt_fall_en_intrpt_fall_en_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[4].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_4_qs) + ); + + + // F[intrpt_fall_en_5]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_5_we), + .wd (intrpt_fall_en_intrpt_fall_en_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[5].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_5_qs) + ); + + + // F[intrpt_fall_en_6]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_6_we), + .wd (intrpt_fall_en_intrpt_fall_en_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[6].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_6_qs) + ); + + + // F[intrpt_fall_en_7]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_7_we), + .wd (intrpt_fall_en_intrpt_fall_en_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[7].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_7_qs) + ); + + + // F[intrpt_fall_en_8]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_8_we), + .wd (intrpt_fall_en_intrpt_fall_en_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[8].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_8_qs) + ); + + + // F[intrpt_fall_en_9]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_9_we), + .wd (intrpt_fall_en_intrpt_fall_en_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[9].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_9_qs) + ); + + + // F[intrpt_fall_en_10]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_10_we), + .wd (intrpt_fall_en_intrpt_fall_en_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[10].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_10_qs) + ); + + + // F[intrpt_fall_en_11]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_11_we), + .wd (intrpt_fall_en_intrpt_fall_en_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[11].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_11_qs) + ); + + + // F[intrpt_fall_en_12]: 12:12 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_12_we), + .wd (intrpt_fall_en_intrpt_fall_en_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[12].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_12_qs) + ); + + + // F[intrpt_fall_en_13]: 13:13 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_13_we), + .wd (intrpt_fall_en_intrpt_fall_en_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[13].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_13_qs) + ); + + + // F[intrpt_fall_en_14]: 14:14 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_14_we), + .wd (intrpt_fall_en_intrpt_fall_en_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[14].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_14_qs) + ); + + + // F[intrpt_fall_en_15]: 15:15 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_15_we), + .wd (intrpt_fall_en_intrpt_fall_en_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[15].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_15_qs) + ); + + + // F[intrpt_fall_en_16]: 16:16 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_16_we), + .wd (intrpt_fall_en_intrpt_fall_en_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[16].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_16_qs) + ); + + + // F[intrpt_fall_en_17]: 17:17 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_17_we), + .wd (intrpt_fall_en_intrpt_fall_en_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[17].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_17_qs) + ); + + + // F[intrpt_fall_en_18]: 18:18 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_18_we), + .wd (intrpt_fall_en_intrpt_fall_en_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[18].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_18_qs) + ); + + + // F[intrpt_fall_en_19]: 19:19 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_19_we), + .wd (intrpt_fall_en_intrpt_fall_en_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[19].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_19_qs) + ); + + + // F[intrpt_fall_en_20]: 20:20 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_20_we), + .wd (intrpt_fall_en_intrpt_fall_en_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[20].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_20_qs) + ); + + + // F[intrpt_fall_en_21]: 21:21 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_21_we), + .wd (intrpt_fall_en_intrpt_fall_en_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[21].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_21_qs) + ); + + + // F[intrpt_fall_en_22]: 22:22 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_22_we), + .wd (intrpt_fall_en_intrpt_fall_en_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[22].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_22_qs) + ); + + + // F[intrpt_fall_en_23]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_23_we), + .wd (intrpt_fall_en_intrpt_fall_en_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[23].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_23_qs) + ); + + + // F[intrpt_fall_en_24]: 24:24 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_24_we), + .wd (intrpt_fall_en_intrpt_fall_en_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[24].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_24_qs) + ); + + + // F[intrpt_fall_en_25]: 25:25 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_25_we), + .wd (intrpt_fall_en_intrpt_fall_en_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[25].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_25_qs) + ); + + + // F[intrpt_fall_en_26]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_26_we), + .wd (intrpt_fall_en_intrpt_fall_en_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[26].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_26_qs) + ); + + + // F[intrpt_fall_en_27]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_27_we), + .wd (intrpt_fall_en_intrpt_fall_en_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[27].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_27_qs) + ); + + + // F[intrpt_fall_en_28]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_28_we), + .wd (intrpt_fall_en_intrpt_fall_en_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[28].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_28_qs) + ); + + + // F[intrpt_fall_en_29]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_29_we), + .wd (intrpt_fall_en_intrpt_fall_en_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[29].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_29_qs) + ); + + + // F[intrpt_fall_en_30]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_30_we), + .wd (intrpt_fall_en_intrpt_fall_en_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[30].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_30_qs) + ); + + + // F[intrpt_fall_en_31]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_31_we), + .wd (intrpt_fall_en_intrpt_fall_en_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[31].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_31_qs) + ); + + + + + // Subregister 0 of Multireg intrpt_lvl_high_en + // R[intrpt_lvl_high_en]: V(False) + + // F[intrpt_lvl_high_en_0]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_0_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[0].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_0_qs) + ); + + + // F[intrpt_lvl_high_en_1]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_1_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[1].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_1_qs) + ); + + + // F[intrpt_lvl_high_en_2]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_2_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[2].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_2_qs) + ); + + + // F[intrpt_lvl_high_en_3]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_3_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[3].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_3_qs) + ); + + + // F[intrpt_lvl_high_en_4]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_4_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[4].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_4_qs) + ); + + + // F[intrpt_lvl_high_en_5]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_5_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[5].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_5_qs) + ); + + + // F[intrpt_lvl_high_en_6]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_6_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[6].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_6_qs) + ); + + + // F[intrpt_lvl_high_en_7]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_7_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[7].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_7_qs) + ); + + + // F[intrpt_lvl_high_en_8]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_8_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[8].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_8_qs) + ); + + + // F[intrpt_lvl_high_en_9]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_9_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[9].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_9_qs) + ); + + + // F[intrpt_lvl_high_en_10]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_10_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[10].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_10_qs) + ); + + + // F[intrpt_lvl_high_en_11]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_11_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[11].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_11_qs) + ); + + + // F[intrpt_lvl_high_en_12]: 12:12 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_12_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[12].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_12_qs) + ); + + + // F[intrpt_lvl_high_en_13]: 13:13 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_13_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[13].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_13_qs) + ); + + + // F[intrpt_lvl_high_en_14]: 14:14 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_14_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[14].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_14_qs) + ); + + + // F[intrpt_lvl_high_en_15]: 15:15 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_15_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[15].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_15_qs) + ); + + + // F[intrpt_lvl_high_en_16]: 16:16 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_16_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[16].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_16_qs) + ); + + + // F[intrpt_lvl_high_en_17]: 17:17 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_17_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[17].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_17_qs) + ); + + + // F[intrpt_lvl_high_en_18]: 18:18 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_18_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[18].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_18_qs) + ); + + + // F[intrpt_lvl_high_en_19]: 19:19 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_19_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[19].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_19_qs) + ); + + + // F[intrpt_lvl_high_en_20]: 20:20 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_20_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[20].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_20_qs) + ); + + + // F[intrpt_lvl_high_en_21]: 21:21 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_21_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[21].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_21_qs) + ); + + + // F[intrpt_lvl_high_en_22]: 22:22 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_22_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[22].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_22_qs) + ); + + + // F[intrpt_lvl_high_en_23]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_23_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[23].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_23_qs) + ); + + + // F[intrpt_lvl_high_en_24]: 24:24 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_24_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[24].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_24_qs) + ); + + + // F[intrpt_lvl_high_en_25]: 25:25 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_25_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[25].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_25_qs) + ); + + + // F[intrpt_lvl_high_en_26]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_26_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[26].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_26_qs) + ); + + + // F[intrpt_lvl_high_en_27]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_27_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[27].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_27_qs) + ); + + + // F[intrpt_lvl_high_en_28]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_28_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[28].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_28_qs) + ); + + + // F[intrpt_lvl_high_en_29]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_29_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[29].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_29_qs) + ); + + + // F[intrpt_lvl_high_en_30]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_30_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[30].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_30_qs) + ); + + + // F[intrpt_lvl_high_en_31]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_31_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[31].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_31_qs) + ); + + + + + // Subregister 0 of Multireg intrpt_lvl_low_en + // R[intrpt_lvl_low_en]: V(False) + + // F[intrpt_lvl_low_en_0]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_0_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[0].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_0_qs) + ); + + + // F[intrpt_lvl_low_en_1]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_1_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[1].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_1_qs) + ); + + + // F[intrpt_lvl_low_en_2]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_2_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[2].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_2_qs) + ); + + + // F[intrpt_lvl_low_en_3]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_3_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[3].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_3_qs) + ); + + + // F[intrpt_lvl_low_en_4]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_4_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[4].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_4_qs) + ); + + + // F[intrpt_lvl_low_en_5]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_5_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[5].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_5_qs) + ); + + + // F[intrpt_lvl_low_en_6]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_6_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[6].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_6_qs) + ); + + + // F[intrpt_lvl_low_en_7]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_7_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[7].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_7_qs) + ); + + + // F[intrpt_lvl_low_en_8]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_8_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[8].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_8_qs) + ); + + + // F[intrpt_lvl_low_en_9]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_9_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[9].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_9_qs) + ); + + + // F[intrpt_lvl_low_en_10]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_10_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[10].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_10_qs) + ); + + + // F[intrpt_lvl_low_en_11]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_11_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[11].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_11_qs) + ); + + + // F[intrpt_lvl_low_en_12]: 12:12 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_12_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[12].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_12_qs) + ); + + + // F[intrpt_lvl_low_en_13]: 13:13 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_13_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[13].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_13_qs) + ); + + + // F[intrpt_lvl_low_en_14]: 14:14 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_14_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[14].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_14_qs) + ); + + + // F[intrpt_lvl_low_en_15]: 15:15 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_15_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[15].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_15_qs) + ); + + + // F[intrpt_lvl_low_en_16]: 16:16 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_16_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[16].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_16_qs) + ); + + + // F[intrpt_lvl_low_en_17]: 17:17 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_17_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[17].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_17_qs) + ); + + + // F[intrpt_lvl_low_en_18]: 18:18 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_18_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[18].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_18_qs) + ); + + + // F[intrpt_lvl_low_en_19]: 19:19 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_19_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[19].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_19_qs) + ); + + + // F[intrpt_lvl_low_en_20]: 20:20 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_20_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[20].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_20_qs) + ); + + + // F[intrpt_lvl_low_en_21]: 21:21 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_21_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[21].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_21_qs) + ); + + + // F[intrpt_lvl_low_en_22]: 22:22 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_22_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[22].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_22_qs) + ); + + + // F[intrpt_lvl_low_en_23]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_23_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[23].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_23_qs) + ); + + + // F[intrpt_lvl_low_en_24]: 24:24 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_24_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[24].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_24_qs) + ); + + + // F[intrpt_lvl_low_en_25]: 25:25 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_25_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[25].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_25_qs) + ); + + + // F[intrpt_lvl_low_en_26]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_26_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[26].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_26_qs) + ); + + + // F[intrpt_lvl_low_en_27]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_27_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[27].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_27_qs) + ); + + + // F[intrpt_lvl_low_en_28]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_28_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[28].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_28_qs) + ); + + + // F[intrpt_lvl_low_en_29]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_29_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[29].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_29_qs) + ); + + + // F[intrpt_lvl_low_en_30]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_30_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[30].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_30_qs) + ); + + + // F[intrpt_lvl_low_en_31]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_31_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[31].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_31_qs) + ); + + + + + // Subregister 0 of Multireg intrpt_status + // R[intrpt_status]: V(True) + + // F[intrpt_status_0]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_0 ( + .re (intrpt_status_intrpt_status_0_re), + .we (intrpt_status_intrpt_status_0_we), + .wd (intrpt_status_intrpt_status_0_wd), + .d (hw2reg.intrpt_status[0].d), + .qre (), + .qe (reg2hw.intrpt_status[0].qe), + .q (reg2hw.intrpt_status[0].q ), + .qs (intrpt_status_intrpt_status_0_qs) + ); + + + // F[intrpt_status_1]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_1 ( + .re (intrpt_status_intrpt_status_1_re), + .we (intrpt_status_intrpt_status_1_we), + .wd (intrpt_status_intrpt_status_1_wd), + .d (hw2reg.intrpt_status[1].d), + .qre (), + .qe (reg2hw.intrpt_status[1].qe), + .q (reg2hw.intrpt_status[1].q ), + .qs (intrpt_status_intrpt_status_1_qs) + ); + + + // F[intrpt_status_2]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_2 ( + .re (intrpt_status_intrpt_status_2_re), + .we (intrpt_status_intrpt_status_2_we), + .wd (intrpt_status_intrpt_status_2_wd), + .d (hw2reg.intrpt_status[2].d), + .qre (), + .qe (reg2hw.intrpt_status[2].qe), + .q (reg2hw.intrpt_status[2].q ), + .qs (intrpt_status_intrpt_status_2_qs) + ); + + + // F[intrpt_status_3]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_3 ( + .re (intrpt_status_intrpt_status_3_re), + .we (intrpt_status_intrpt_status_3_we), + .wd (intrpt_status_intrpt_status_3_wd), + .d (hw2reg.intrpt_status[3].d), + .qre (), + .qe (reg2hw.intrpt_status[3].qe), + .q (reg2hw.intrpt_status[3].q ), + .qs (intrpt_status_intrpt_status_3_qs) + ); + + + // F[intrpt_status_4]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_4 ( + .re (intrpt_status_intrpt_status_4_re), + .we (intrpt_status_intrpt_status_4_we), + .wd (intrpt_status_intrpt_status_4_wd), + .d (hw2reg.intrpt_status[4].d), + .qre (), + .qe (reg2hw.intrpt_status[4].qe), + .q (reg2hw.intrpt_status[4].q ), + .qs (intrpt_status_intrpt_status_4_qs) + ); + + + // F[intrpt_status_5]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_5 ( + .re (intrpt_status_intrpt_status_5_re), + .we (intrpt_status_intrpt_status_5_we), + .wd (intrpt_status_intrpt_status_5_wd), + .d (hw2reg.intrpt_status[5].d), + .qre (), + .qe (reg2hw.intrpt_status[5].qe), + .q (reg2hw.intrpt_status[5].q ), + .qs (intrpt_status_intrpt_status_5_qs) + ); + + + // F[intrpt_status_6]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_6 ( + .re (intrpt_status_intrpt_status_6_re), + .we (intrpt_status_intrpt_status_6_we), + .wd (intrpt_status_intrpt_status_6_wd), + .d (hw2reg.intrpt_status[6].d), + .qre (), + .qe (reg2hw.intrpt_status[6].qe), + .q (reg2hw.intrpt_status[6].q ), + .qs (intrpt_status_intrpt_status_6_qs) + ); + + + // F[intrpt_status_7]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_7 ( + .re (intrpt_status_intrpt_status_7_re), + .we (intrpt_status_intrpt_status_7_we), + .wd (intrpt_status_intrpt_status_7_wd), + .d (hw2reg.intrpt_status[7].d), + .qre (), + .qe (reg2hw.intrpt_status[7].qe), + .q (reg2hw.intrpt_status[7].q ), + .qs (intrpt_status_intrpt_status_7_qs) + ); + + + // F[intrpt_status_8]: 8:8 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_8 ( + .re (intrpt_status_intrpt_status_8_re), + .we (intrpt_status_intrpt_status_8_we), + .wd (intrpt_status_intrpt_status_8_wd), + .d (hw2reg.intrpt_status[8].d), + .qre (), + .qe (reg2hw.intrpt_status[8].qe), + .q (reg2hw.intrpt_status[8].q ), + .qs (intrpt_status_intrpt_status_8_qs) + ); + + + // F[intrpt_status_9]: 9:9 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_9 ( + .re (intrpt_status_intrpt_status_9_re), + .we (intrpt_status_intrpt_status_9_we), + .wd (intrpt_status_intrpt_status_9_wd), + .d (hw2reg.intrpt_status[9].d), + .qre (), + .qe (reg2hw.intrpt_status[9].qe), + .q (reg2hw.intrpt_status[9].q ), + .qs (intrpt_status_intrpt_status_9_qs) + ); + + + // F[intrpt_status_10]: 10:10 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_10 ( + .re (intrpt_status_intrpt_status_10_re), + .we (intrpt_status_intrpt_status_10_we), + .wd (intrpt_status_intrpt_status_10_wd), + .d (hw2reg.intrpt_status[10].d), + .qre (), + .qe (reg2hw.intrpt_status[10].qe), + .q (reg2hw.intrpt_status[10].q ), + .qs (intrpt_status_intrpt_status_10_qs) + ); + + + // F[intrpt_status_11]: 11:11 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_11 ( + .re (intrpt_status_intrpt_status_11_re), + .we (intrpt_status_intrpt_status_11_we), + .wd (intrpt_status_intrpt_status_11_wd), + .d (hw2reg.intrpt_status[11].d), + .qre (), + .qe (reg2hw.intrpt_status[11].qe), + .q (reg2hw.intrpt_status[11].q ), + .qs (intrpt_status_intrpt_status_11_qs) + ); + + + // F[intrpt_status_12]: 12:12 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_12 ( + .re (intrpt_status_intrpt_status_12_re), + .we (intrpt_status_intrpt_status_12_we), + .wd (intrpt_status_intrpt_status_12_wd), + .d (hw2reg.intrpt_status[12].d), + .qre (), + .qe (reg2hw.intrpt_status[12].qe), + .q (reg2hw.intrpt_status[12].q ), + .qs (intrpt_status_intrpt_status_12_qs) + ); + + + // F[intrpt_status_13]: 13:13 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_13 ( + .re (intrpt_status_intrpt_status_13_re), + .we (intrpt_status_intrpt_status_13_we), + .wd (intrpt_status_intrpt_status_13_wd), + .d (hw2reg.intrpt_status[13].d), + .qre (), + .qe (reg2hw.intrpt_status[13].qe), + .q (reg2hw.intrpt_status[13].q ), + .qs (intrpt_status_intrpt_status_13_qs) + ); + + + // F[intrpt_status_14]: 14:14 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_14 ( + .re (intrpt_status_intrpt_status_14_re), + .we (intrpt_status_intrpt_status_14_we), + .wd (intrpt_status_intrpt_status_14_wd), + .d (hw2reg.intrpt_status[14].d), + .qre (), + .qe (reg2hw.intrpt_status[14].qe), + .q (reg2hw.intrpt_status[14].q ), + .qs (intrpt_status_intrpt_status_14_qs) + ); + + + // F[intrpt_status_15]: 15:15 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_15 ( + .re (intrpt_status_intrpt_status_15_re), + .we (intrpt_status_intrpt_status_15_we), + .wd (intrpt_status_intrpt_status_15_wd), + .d (hw2reg.intrpt_status[15].d), + .qre (), + .qe (reg2hw.intrpt_status[15].qe), + .q (reg2hw.intrpt_status[15].q ), + .qs (intrpt_status_intrpt_status_15_qs) + ); + + + // F[intrpt_status_16]: 16:16 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_16 ( + .re (intrpt_status_intrpt_status_16_re), + .we (intrpt_status_intrpt_status_16_we), + .wd (intrpt_status_intrpt_status_16_wd), + .d (hw2reg.intrpt_status[16].d), + .qre (), + .qe (reg2hw.intrpt_status[16].qe), + .q (reg2hw.intrpt_status[16].q ), + .qs (intrpt_status_intrpt_status_16_qs) + ); + + + // F[intrpt_status_17]: 17:17 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_17 ( + .re (intrpt_status_intrpt_status_17_re), + .we (intrpt_status_intrpt_status_17_we), + .wd (intrpt_status_intrpt_status_17_wd), + .d (hw2reg.intrpt_status[17].d), + .qre (), + .qe (reg2hw.intrpt_status[17].qe), + .q (reg2hw.intrpt_status[17].q ), + .qs (intrpt_status_intrpt_status_17_qs) + ); + + + // F[intrpt_status_18]: 18:18 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_18 ( + .re (intrpt_status_intrpt_status_18_re), + .we (intrpt_status_intrpt_status_18_we), + .wd (intrpt_status_intrpt_status_18_wd), + .d (hw2reg.intrpt_status[18].d), + .qre (), + .qe (reg2hw.intrpt_status[18].qe), + .q (reg2hw.intrpt_status[18].q ), + .qs (intrpt_status_intrpt_status_18_qs) + ); + + + // F[intrpt_status_19]: 19:19 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_19 ( + .re (intrpt_status_intrpt_status_19_re), + .we (intrpt_status_intrpt_status_19_we), + .wd (intrpt_status_intrpt_status_19_wd), + .d (hw2reg.intrpt_status[19].d), + .qre (), + .qe (reg2hw.intrpt_status[19].qe), + .q (reg2hw.intrpt_status[19].q ), + .qs (intrpt_status_intrpt_status_19_qs) + ); + + + // F[intrpt_status_20]: 20:20 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_20 ( + .re (intrpt_status_intrpt_status_20_re), + .we (intrpt_status_intrpt_status_20_we), + .wd (intrpt_status_intrpt_status_20_wd), + .d (hw2reg.intrpt_status[20].d), + .qre (), + .qe (reg2hw.intrpt_status[20].qe), + .q (reg2hw.intrpt_status[20].q ), + .qs (intrpt_status_intrpt_status_20_qs) + ); + + + // F[intrpt_status_21]: 21:21 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_21 ( + .re (intrpt_status_intrpt_status_21_re), + .we (intrpt_status_intrpt_status_21_we), + .wd (intrpt_status_intrpt_status_21_wd), + .d (hw2reg.intrpt_status[21].d), + .qre (), + .qe (reg2hw.intrpt_status[21].qe), + .q (reg2hw.intrpt_status[21].q ), + .qs (intrpt_status_intrpt_status_21_qs) + ); + + + // F[intrpt_status_22]: 22:22 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_22 ( + .re (intrpt_status_intrpt_status_22_re), + .we (intrpt_status_intrpt_status_22_we), + .wd (intrpt_status_intrpt_status_22_wd), + .d (hw2reg.intrpt_status[22].d), + .qre (), + .qe (reg2hw.intrpt_status[22].qe), + .q (reg2hw.intrpt_status[22].q ), + .qs (intrpt_status_intrpt_status_22_qs) + ); + + + // F[intrpt_status_23]: 23:23 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_23 ( + .re (intrpt_status_intrpt_status_23_re), + .we (intrpt_status_intrpt_status_23_we), + .wd (intrpt_status_intrpt_status_23_wd), + .d (hw2reg.intrpt_status[23].d), + .qre (), + .qe (reg2hw.intrpt_status[23].qe), + .q (reg2hw.intrpt_status[23].q ), + .qs (intrpt_status_intrpt_status_23_qs) + ); + + + // F[intrpt_status_24]: 24:24 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_24 ( + .re (intrpt_status_intrpt_status_24_re), + .we (intrpt_status_intrpt_status_24_we), + .wd (intrpt_status_intrpt_status_24_wd), + .d (hw2reg.intrpt_status[24].d), + .qre (), + .qe (reg2hw.intrpt_status[24].qe), + .q (reg2hw.intrpt_status[24].q ), + .qs (intrpt_status_intrpt_status_24_qs) + ); + + + // F[intrpt_status_25]: 25:25 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_25 ( + .re (intrpt_status_intrpt_status_25_re), + .we (intrpt_status_intrpt_status_25_we), + .wd (intrpt_status_intrpt_status_25_wd), + .d (hw2reg.intrpt_status[25].d), + .qre (), + .qe (reg2hw.intrpt_status[25].qe), + .q (reg2hw.intrpt_status[25].q ), + .qs (intrpt_status_intrpt_status_25_qs) + ); + + + // F[intrpt_status_26]: 26:26 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_26 ( + .re (intrpt_status_intrpt_status_26_re), + .we (intrpt_status_intrpt_status_26_we), + .wd (intrpt_status_intrpt_status_26_wd), + .d (hw2reg.intrpt_status[26].d), + .qre (), + .qe (reg2hw.intrpt_status[26].qe), + .q (reg2hw.intrpt_status[26].q ), + .qs (intrpt_status_intrpt_status_26_qs) + ); + + + // F[intrpt_status_27]: 27:27 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_27 ( + .re (intrpt_status_intrpt_status_27_re), + .we (intrpt_status_intrpt_status_27_we), + .wd (intrpt_status_intrpt_status_27_wd), + .d (hw2reg.intrpt_status[27].d), + .qre (), + .qe (reg2hw.intrpt_status[27].qe), + .q (reg2hw.intrpt_status[27].q ), + .qs (intrpt_status_intrpt_status_27_qs) + ); + + + // F[intrpt_status_28]: 28:28 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_28 ( + .re (intrpt_status_intrpt_status_28_re), + .we (intrpt_status_intrpt_status_28_we), + .wd (intrpt_status_intrpt_status_28_wd), + .d (hw2reg.intrpt_status[28].d), + .qre (), + .qe (reg2hw.intrpt_status[28].qe), + .q (reg2hw.intrpt_status[28].q ), + .qs (intrpt_status_intrpt_status_28_qs) + ); + + + // F[intrpt_status_29]: 29:29 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_29 ( + .re (intrpt_status_intrpt_status_29_re), + .we (intrpt_status_intrpt_status_29_we), + .wd (intrpt_status_intrpt_status_29_wd), + .d (hw2reg.intrpt_status[29].d), + .qre (), + .qe (reg2hw.intrpt_status[29].qe), + .q (reg2hw.intrpt_status[29].q ), + .qs (intrpt_status_intrpt_status_29_qs) + ); + + + // F[intrpt_status_30]: 30:30 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_30 ( + .re (intrpt_status_intrpt_status_30_re), + .we (intrpt_status_intrpt_status_30_we), + .wd (intrpt_status_intrpt_status_30_wd), + .d (hw2reg.intrpt_status[30].d), + .qre (), + .qe (reg2hw.intrpt_status[30].qe), + .q (reg2hw.intrpt_status[30].q ), + .qs (intrpt_status_intrpt_status_30_qs) + ); + + + // F[intrpt_status_31]: 31:31 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_31 ( + .re (intrpt_status_intrpt_status_31_re), + .we (intrpt_status_intrpt_status_31_we), + .wd (intrpt_status_intrpt_status_31_wd), + .d (hw2reg.intrpt_status[31].d), + .qre (), + .qe (reg2hw.intrpt_status[31].qe), + .q (reg2hw.intrpt_status[31].q ), + .qs (intrpt_status_intrpt_status_31_qs) + ); + + + + + // Subregister 0 of Multireg intrpt_rise_status + // R[intrpt_rise_status]: V(False) + + // F[intrpt_rise_status_0]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_0_we), + .wd (intrpt_rise_status_intrpt_rise_status_0_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[0].de), + .d (hw2reg.intrpt_rise_status[0].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[0].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_0_qs) + ); + + + // F[intrpt_rise_status_1]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_1_we), + .wd (intrpt_rise_status_intrpt_rise_status_1_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[1].de), + .d (hw2reg.intrpt_rise_status[1].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[1].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_1_qs) + ); + + + // F[intrpt_rise_status_2]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_2_we), + .wd (intrpt_rise_status_intrpt_rise_status_2_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[2].de), + .d (hw2reg.intrpt_rise_status[2].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[2].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_2_qs) + ); + + + // F[intrpt_rise_status_3]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_3_we), + .wd (intrpt_rise_status_intrpt_rise_status_3_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[3].de), + .d (hw2reg.intrpt_rise_status[3].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[3].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_3_qs) + ); + + + // F[intrpt_rise_status_4]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_4_we), + .wd (intrpt_rise_status_intrpt_rise_status_4_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[4].de), + .d (hw2reg.intrpt_rise_status[4].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[4].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_4_qs) + ); + + + // F[intrpt_rise_status_5]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_5_we), + .wd (intrpt_rise_status_intrpt_rise_status_5_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[5].de), + .d (hw2reg.intrpt_rise_status[5].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[5].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_5_qs) + ); + + + // F[intrpt_rise_status_6]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_6_we), + .wd (intrpt_rise_status_intrpt_rise_status_6_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[6].de), + .d (hw2reg.intrpt_rise_status[6].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[6].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_6_qs) + ); + + + // F[intrpt_rise_status_7]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_7_we), + .wd (intrpt_rise_status_intrpt_rise_status_7_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[7].de), + .d (hw2reg.intrpt_rise_status[7].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[7].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_7_qs) + ); + + + // F[intrpt_rise_status_8]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_8_we), + .wd (intrpt_rise_status_intrpt_rise_status_8_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[8].de), + .d (hw2reg.intrpt_rise_status[8].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[8].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_8_qs) + ); + + + // F[intrpt_rise_status_9]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_9_we), + .wd (intrpt_rise_status_intrpt_rise_status_9_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[9].de), + .d (hw2reg.intrpt_rise_status[9].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[9].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_9_qs) + ); + + + // F[intrpt_rise_status_10]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_10_we), + .wd (intrpt_rise_status_intrpt_rise_status_10_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[10].de), + .d (hw2reg.intrpt_rise_status[10].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[10].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_10_qs) + ); + + + // F[intrpt_rise_status_11]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_11_we), + .wd (intrpt_rise_status_intrpt_rise_status_11_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[11].de), + .d (hw2reg.intrpt_rise_status[11].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[11].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_11_qs) + ); + + + // F[intrpt_rise_status_12]: 12:12 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_12_we), + .wd (intrpt_rise_status_intrpt_rise_status_12_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[12].de), + .d (hw2reg.intrpt_rise_status[12].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[12].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_12_qs) + ); + + + // F[intrpt_rise_status_13]: 13:13 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_13_we), + .wd (intrpt_rise_status_intrpt_rise_status_13_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[13].de), + .d (hw2reg.intrpt_rise_status[13].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[13].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_13_qs) + ); + + + // F[intrpt_rise_status_14]: 14:14 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_14_we), + .wd (intrpt_rise_status_intrpt_rise_status_14_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[14].de), + .d (hw2reg.intrpt_rise_status[14].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[14].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_14_qs) + ); + + + // F[intrpt_rise_status_15]: 15:15 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_15_we), + .wd (intrpt_rise_status_intrpt_rise_status_15_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[15].de), + .d (hw2reg.intrpt_rise_status[15].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[15].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_15_qs) + ); + + + // F[intrpt_rise_status_16]: 16:16 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_16_we), + .wd (intrpt_rise_status_intrpt_rise_status_16_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[16].de), + .d (hw2reg.intrpt_rise_status[16].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[16].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_16_qs) + ); + + + // F[intrpt_rise_status_17]: 17:17 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_17_we), + .wd (intrpt_rise_status_intrpt_rise_status_17_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[17].de), + .d (hw2reg.intrpt_rise_status[17].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[17].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_17_qs) + ); + + + // F[intrpt_rise_status_18]: 18:18 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_18_we), + .wd (intrpt_rise_status_intrpt_rise_status_18_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[18].de), + .d (hw2reg.intrpt_rise_status[18].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[18].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_18_qs) + ); + + + // F[intrpt_rise_status_19]: 19:19 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_19_we), + .wd (intrpt_rise_status_intrpt_rise_status_19_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[19].de), + .d (hw2reg.intrpt_rise_status[19].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[19].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_19_qs) + ); + + + // F[intrpt_rise_status_20]: 20:20 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_20_we), + .wd (intrpt_rise_status_intrpt_rise_status_20_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[20].de), + .d (hw2reg.intrpt_rise_status[20].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[20].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_20_qs) + ); + + + // F[intrpt_rise_status_21]: 21:21 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_21_we), + .wd (intrpt_rise_status_intrpt_rise_status_21_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[21].de), + .d (hw2reg.intrpt_rise_status[21].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[21].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_21_qs) + ); + + + // F[intrpt_rise_status_22]: 22:22 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_22_we), + .wd (intrpt_rise_status_intrpt_rise_status_22_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[22].de), + .d (hw2reg.intrpt_rise_status[22].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[22].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_22_qs) + ); + + + // F[intrpt_rise_status_23]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_23_we), + .wd (intrpt_rise_status_intrpt_rise_status_23_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[23].de), + .d (hw2reg.intrpt_rise_status[23].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[23].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_23_qs) + ); + + + // F[intrpt_rise_status_24]: 24:24 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_24_we), + .wd (intrpt_rise_status_intrpt_rise_status_24_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[24].de), + .d (hw2reg.intrpt_rise_status[24].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[24].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_24_qs) + ); + + + // F[intrpt_rise_status_25]: 25:25 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_25_we), + .wd (intrpt_rise_status_intrpt_rise_status_25_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[25].de), + .d (hw2reg.intrpt_rise_status[25].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[25].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_25_qs) + ); + + + // F[intrpt_rise_status_26]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_26_we), + .wd (intrpt_rise_status_intrpt_rise_status_26_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[26].de), + .d (hw2reg.intrpt_rise_status[26].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[26].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_26_qs) + ); + + + // F[intrpt_rise_status_27]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_27_we), + .wd (intrpt_rise_status_intrpt_rise_status_27_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[27].de), + .d (hw2reg.intrpt_rise_status[27].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[27].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_27_qs) + ); + + + // F[intrpt_rise_status_28]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_28_we), + .wd (intrpt_rise_status_intrpt_rise_status_28_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[28].de), + .d (hw2reg.intrpt_rise_status[28].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[28].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_28_qs) + ); + + + // F[intrpt_rise_status_29]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_29_we), + .wd (intrpt_rise_status_intrpt_rise_status_29_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[29].de), + .d (hw2reg.intrpt_rise_status[29].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[29].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_29_qs) + ); + + + // F[intrpt_rise_status_30]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_30_we), + .wd (intrpt_rise_status_intrpt_rise_status_30_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[30].de), + .d (hw2reg.intrpt_rise_status[30].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[30].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_30_qs) + ); + + + // F[intrpt_rise_status_31]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_31_we), + .wd (intrpt_rise_status_intrpt_rise_status_31_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[31].de), + .d (hw2reg.intrpt_rise_status[31].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[31].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_31_qs) + ); + + + + + // Subregister 0 of Multireg intrpt_fall_status + // R[intrpt_fall_status]: V(False) + + // F[intrpt_fall_status_0]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_0_we), + .wd (intrpt_fall_status_intrpt_fall_status_0_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[0].de), + .d (hw2reg.intrpt_fall_status[0].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[0].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_0_qs) + ); + + + // F[intrpt_fall_status_1]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_1_we), + .wd (intrpt_fall_status_intrpt_fall_status_1_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[1].de), + .d (hw2reg.intrpt_fall_status[1].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[1].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_1_qs) + ); + + + // F[intrpt_fall_status_2]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_2_we), + .wd (intrpt_fall_status_intrpt_fall_status_2_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[2].de), + .d (hw2reg.intrpt_fall_status[2].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[2].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_2_qs) + ); + + + // F[intrpt_fall_status_3]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_3_we), + .wd (intrpt_fall_status_intrpt_fall_status_3_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[3].de), + .d (hw2reg.intrpt_fall_status[3].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[3].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_3_qs) + ); + + + // F[intrpt_fall_status_4]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_4_we), + .wd (intrpt_fall_status_intrpt_fall_status_4_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[4].de), + .d (hw2reg.intrpt_fall_status[4].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[4].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_4_qs) + ); + + + // F[intrpt_fall_status_5]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_5_we), + .wd (intrpt_fall_status_intrpt_fall_status_5_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[5].de), + .d (hw2reg.intrpt_fall_status[5].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[5].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_5_qs) + ); + + + // F[intrpt_fall_status_6]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_6_we), + .wd (intrpt_fall_status_intrpt_fall_status_6_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[6].de), + .d (hw2reg.intrpt_fall_status[6].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[6].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_6_qs) + ); + + + // F[intrpt_fall_status_7]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_7_we), + .wd (intrpt_fall_status_intrpt_fall_status_7_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[7].de), + .d (hw2reg.intrpt_fall_status[7].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[7].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_7_qs) + ); + + + // F[intrpt_fall_status_8]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_8_we), + .wd (intrpt_fall_status_intrpt_fall_status_8_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[8].de), + .d (hw2reg.intrpt_fall_status[8].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[8].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_8_qs) + ); + + + // F[intrpt_fall_status_9]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_9_we), + .wd (intrpt_fall_status_intrpt_fall_status_9_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[9].de), + .d (hw2reg.intrpt_fall_status[9].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[9].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_9_qs) + ); + + + // F[intrpt_fall_status_10]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_10_we), + .wd (intrpt_fall_status_intrpt_fall_status_10_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[10].de), + .d (hw2reg.intrpt_fall_status[10].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[10].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_10_qs) + ); + + + // F[intrpt_fall_status_11]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_11_we), + .wd (intrpt_fall_status_intrpt_fall_status_11_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[11].de), + .d (hw2reg.intrpt_fall_status[11].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[11].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_11_qs) + ); + + + // F[intrpt_fall_status_12]: 12:12 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_12_we), + .wd (intrpt_fall_status_intrpt_fall_status_12_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[12].de), + .d (hw2reg.intrpt_fall_status[12].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[12].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_12_qs) + ); + + + // F[intrpt_fall_status_13]: 13:13 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_13_we), + .wd (intrpt_fall_status_intrpt_fall_status_13_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[13].de), + .d (hw2reg.intrpt_fall_status[13].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[13].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_13_qs) + ); + + + // F[intrpt_fall_status_14]: 14:14 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_14_we), + .wd (intrpt_fall_status_intrpt_fall_status_14_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[14].de), + .d (hw2reg.intrpt_fall_status[14].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[14].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_14_qs) + ); + + + // F[intrpt_fall_status_15]: 15:15 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_15_we), + .wd (intrpt_fall_status_intrpt_fall_status_15_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[15].de), + .d (hw2reg.intrpt_fall_status[15].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[15].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_15_qs) + ); + + + // F[intrpt_fall_status_16]: 16:16 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_16_we), + .wd (intrpt_fall_status_intrpt_fall_status_16_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[16].de), + .d (hw2reg.intrpt_fall_status[16].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[16].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_16_qs) + ); + + + // F[intrpt_fall_status_17]: 17:17 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_17_we), + .wd (intrpt_fall_status_intrpt_fall_status_17_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[17].de), + .d (hw2reg.intrpt_fall_status[17].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[17].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_17_qs) + ); + + + // F[intrpt_fall_status_18]: 18:18 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_18_we), + .wd (intrpt_fall_status_intrpt_fall_status_18_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[18].de), + .d (hw2reg.intrpt_fall_status[18].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[18].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_18_qs) + ); + + + // F[intrpt_fall_status_19]: 19:19 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_19_we), + .wd (intrpt_fall_status_intrpt_fall_status_19_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[19].de), + .d (hw2reg.intrpt_fall_status[19].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[19].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_19_qs) + ); + + + // F[intrpt_fall_status_20]: 20:20 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_20_we), + .wd (intrpt_fall_status_intrpt_fall_status_20_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[20].de), + .d (hw2reg.intrpt_fall_status[20].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[20].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_20_qs) + ); + + + // F[intrpt_fall_status_21]: 21:21 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_21_we), + .wd (intrpt_fall_status_intrpt_fall_status_21_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[21].de), + .d (hw2reg.intrpt_fall_status[21].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[21].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_21_qs) + ); + + + // F[intrpt_fall_status_22]: 22:22 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_22_we), + .wd (intrpt_fall_status_intrpt_fall_status_22_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[22].de), + .d (hw2reg.intrpt_fall_status[22].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[22].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_22_qs) + ); + + + // F[intrpt_fall_status_23]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_23_we), + .wd (intrpt_fall_status_intrpt_fall_status_23_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[23].de), + .d (hw2reg.intrpt_fall_status[23].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[23].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_23_qs) + ); + + + // F[intrpt_fall_status_24]: 24:24 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_24_we), + .wd (intrpt_fall_status_intrpt_fall_status_24_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[24].de), + .d (hw2reg.intrpt_fall_status[24].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[24].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_24_qs) + ); + + + // F[intrpt_fall_status_25]: 25:25 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_25_we), + .wd (intrpt_fall_status_intrpt_fall_status_25_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[25].de), + .d (hw2reg.intrpt_fall_status[25].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[25].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_25_qs) + ); + + + // F[intrpt_fall_status_26]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_26_we), + .wd (intrpt_fall_status_intrpt_fall_status_26_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[26].de), + .d (hw2reg.intrpt_fall_status[26].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[26].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_26_qs) + ); + + + // F[intrpt_fall_status_27]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_27_we), + .wd (intrpt_fall_status_intrpt_fall_status_27_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[27].de), + .d (hw2reg.intrpt_fall_status[27].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[27].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_27_qs) + ); + + + // F[intrpt_fall_status_28]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_28_we), + .wd (intrpt_fall_status_intrpt_fall_status_28_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[28].de), + .d (hw2reg.intrpt_fall_status[28].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[28].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_28_qs) + ); + + + // F[intrpt_fall_status_29]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_29_we), + .wd (intrpt_fall_status_intrpt_fall_status_29_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[29].de), + .d (hw2reg.intrpt_fall_status[29].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[29].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_29_qs) + ); + + + // F[intrpt_fall_status_30]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_30_we), + .wd (intrpt_fall_status_intrpt_fall_status_30_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[30].de), + .d (hw2reg.intrpt_fall_status[30].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[30].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_30_qs) + ); + + + // F[intrpt_fall_status_31]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_31_we), + .wd (intrpt_fall_status_intrpt_fall_status_31_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[31].de), + .d (hw2reg.intrpt_fall_status[31].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[31].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_31_qs) + ); + + + + + // Subregister 0 of Multireg intrpt_lvl_high_status + // R[intrpt_lvl_high_status]: V(False) + + // F[intrpt_lvl_high_status_0]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_0_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_0_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[0].de), + .d (hw2reg.intrpt_lvl_high_status[0].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[0].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_0_qs) + ); + + + // F[intrpt_lvl_high_status_1]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_1_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_1_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[1].de), + .d (hw2reg.intrpt_lvl_high_status[1].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[1].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_1_qs) + ); + + + // F[intrpt_lvl_high_status_2]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_2_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_2_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[2].de), + .d (hw2reg.intrpt_lvl_high_status[2].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[2].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_2_qs) + ); + + + // F[intrpt_lvl_high_status_3]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_3_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_3_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[3].de), + .d (hw2reg.intrpt_lvl_high_status[3].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[3].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_3_qs) + ); + + + // F[intrpt_lvl_high_status_4]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_4_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_4_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[4].de), + .d (hw2reg.intrpt_lvl_high_status[4].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[4].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_4_qs) + ); + + + // F[intrpt_lvl_high_status_5]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_5_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_5_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[5].de), + .d (hw2reg.intrpt_lvl_high_status[5].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[5].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_5_qs) + ); + + + // F[intrpt_lvl_high_status_6]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_6_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_6_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[6].de), + .d (hw2reg.intrpt_lvl_high_status[6].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[6].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_6_qs) + ); + + + // F[intrpt_lvl_high_status_7]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_7_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_7_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[7].de), + .d (hw2reg.intrpt_lvl_high_status[7].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[7].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_7_qs) + ); + + + // F[intrpt_lvl_high_status_8]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_8_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_8_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[8].de), + .d (hw2reg.intrpt_lvl_high_status[8].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[8].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_8_qs) + ); + + + // F[intrpt_lvl_high_status_9]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_9_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_9_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[9].de), + .d (hw2reg.intrpt_lvl_high_status[9].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[9].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_9_qs) + ); + + + // F[intrpt_lvl_high_status_10]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_10_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_10_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[10].de), + .d (hw2reg.intrpt_lvl_high_status[10].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[10].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_10_qs) + ); + + + // F[intrpt_lvl_high_status_11]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_11_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_11_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[11].de), + .d (hw2reg.intrpt_lvl_high_status[11].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[11].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_11_qs) + ); + + + // F[intrpt_lvl_high_status_12]: 12:12 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_12_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_12_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[12].de), + .d (hw2reg.intrpt_lvl_high_status[12].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[12].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_12_qs) + ); + + + // F[intrpt_lvl_high_status_13]: 13:13 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_13_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_13_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[13].de), + .d (hw2reg.intrpt_lvl_high_status[13].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[13].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_13_qs) + ); + + + // F[intrpt_lvl_high_status_14]: 14:14 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_14_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_14_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[14].de), + .d (hw2reg.intrpt_lvl_high_status[14].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[14].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_14_qs) + ); + + + // F[intrpt_lvl_high_status_15]: 15:15 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_15_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_15_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[15].de), + .d (hw2reg.intrpt_lvl_high_status[15].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[15].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_15_qs) + ); + + + // F[intrpt_lvl_high_status_16]: 16:16 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_16_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_16_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[16].de), + .d (hw2reg.intrpt_lvl_high_status[16].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[16].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_16_qs) + ); + + + // F[intrpt_lvl_high_status_17]: 17:17 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_17_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_17_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[17].de), + .d (hw2reg.intrpt_lvl_high_status[17].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[17].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_17_qs) + ); + + + // F[intrpt_lvl_high_status_18]: 18:18 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_18_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_18_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[18].de), + .d (hw2reg.intrpt_lvl_high_status[18].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[18].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_18_qs) + ); + + + // F[intrpt_lvl_high_status_19]: 19:19 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_19_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_19_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[19].de), + .d (hw2reg.intrpt_lvl_high_status[19].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[19].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_19_qs) + ); + + + // F[intrpt_lvl_high_status_20]: 20:20 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_20_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_20_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[20].de), + .d (hw2reg.intrpt_lvl_high_status[20].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[20].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_20_qs) + ); + + + // F[intrpt_lvl_high_status_21]: 21:21 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_21_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_21_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[21].de), + .d (hw2reg.intrpt_lvl_high_status[21].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[21].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_21_qs) + ); + + + // F[intrpt_lvl_high_status_22]: 22:22 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_22_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_22_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[22].de), + .d (hw2reg.intrpt_lvl_high_status[22].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[22].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_22_qs) + ); + + + // F[intrpt_lvl_high_status_23]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_23_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_23_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[23].de), + .d (hw2reg.intrpt_lvl_high_status[23].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[23].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_23_qs) + ); + + + // F[intrpt_lvl_high_status_24]: 24:24 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_24_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_24_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[24].de), + .d (hw2reg.intrpt_lvl_high_status[24].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[24].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_24_qs) + ); + + + // F[intrpt_lvl_high_status_25]: 25:25 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_25_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_25_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[25].de), + .d (hw2reg.intrpt_lvl_high_status[25].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[25].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_25_qs) + ); + + + // F[intrpt_lvl_high_status_26]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_26_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_26_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[26].de), + .d (hw2reg.intrpt_lvl_high_status[26].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[26].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_26_qs) + ); + + + // F[intrpt_lvl_high_status_27]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_27_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_27_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[27].de), + .d (hw2reg.intrpt_lvl_high_status[27].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[27].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_27_qs) + ); + + + // F[intrpt_lvl_high_status_28]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_28_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_28_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[28].de), + .d (hw2reg.intrpt_lvl_high_status[28].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[28].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_28_qs) + ); + + + // F[intrpt_lvl_high_status_29]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_29_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_29_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[29].de), + .d (hw2reg.intrpt_lvl_high_status[29].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[29].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_29_qs) + ); + + + // F[intrpt_lvl_high_status_30]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_30_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_30_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[30].de), + .d (hw2reg.intrpt_lvl_high_status[30].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[30].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_30_qs) + ); + + + // F[intrpt_lvl_high_status_31]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_31_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_31_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[31].de), + .d (hw2reg.intrpt_lvl_high_status[31].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[31].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_31_qs) + ); + + + + + // Subregister 0 of Multireg intrpt_lvl_low_status + // R[intrpt_lvl_low_status]: V(False) + + // F[intrpt_lvl_low_status_0]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_0_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_0_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[0].de), + .d (hw2reg.intrpt_lvl_low_status[0].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[0].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_0_qs) + ); + + + // F[intrpt_lvl_low_status_1]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_1_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_1_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[1].de), + .d (hw2reg.intrpt_lvl_low_status[1].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[1].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_1_qs) + ); + + + // F[intrpt_lvl_low_status_2]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_2_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_2_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[2].de), + .d (hw2reg.intrpt_lvl_low_status[2].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[2].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_2_qs) + ); + + + // F[intrpt_lvl_low_status_3]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_3_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_3_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[3].de), + .d (hw2reg.intrpt_lvl_low_status[3].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[3].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_3_qs) + ); + + + // F[intrpt_lvl_low_status_4]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_4_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_4_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[4].de), + .d (hw2reg.intrpt_lvl_low_status[4].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[4].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_4_qs) + ); + + + // F[intrpt_lvl_low_status_5]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_5_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_5_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[5].de), + .d (hw2reg.intrpt_lvl_low_status[5].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[5].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_5_qs) + ); + + + // F[intrpt_lvl_low_status_6]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_6_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_6_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[6].de), + .d (hw2reg.intrpt_lvl_low_status[6].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[6].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_6_qs) + ); + + + // F[intrpt_lvl_low_status_7]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_7_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_7_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[7].de), + .d (hw2reg.intrpt_lvl_low_status[7].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[7].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_7_qs) + ); + + + // F[intrpt_lvl_low_status_8]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_8_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_8_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[8].de), + .d (hw2reg.intrpt_lvl_low_status[8].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[8].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_8_qs) + ); + + + // F[intrpt_lvl_low_status_9]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_9_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_9_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[9].de), + .d (hw2reg.intrpt_lvl_low_status[9].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[9].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_9_qs) + ); + + + // F[intrpt_lvl_low_status_10]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_10_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_10_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[10].de), + .d (hw2reg.intrpt_lvl_low_status[10].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[10].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_10_qs) + ); + + + // F[intrpt_lvl_low_status_11]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_11_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_11_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[11].de), + .d (hw2reg.intrpt_lvl_low_status[11].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[11].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_11_qs) + ); + + + // F[intrpt_lvl_low_status_12]: 12:12 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_12_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_12_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[12].de), + .d (hw2reg.intrpt_lvl_low_status[12].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[12].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_12_qs) + ); + + + // F[intrpt_lvl_low_status_13]: 13:13 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_13_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_13_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[13].de), + .d (hw2reg.intrpt_lvl_low_status[13].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[13].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_13_qs) + ); + + + // F[intrpt_lvl_low_status_14]: 14:14 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_14_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_14_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[14].de), + .d (hw2reg.intrpt_lvl_low_status[14].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[14].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_14_qs) + ); + + + // F[intrpt_lvl_low_status_15]: 15:15 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_15_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_15_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[15].de), + .d (hw2reg.intrpt_lvl_low_status[15].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[15].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_15_qs) + ); + + + // F[intrpt_lvl_low_status_16]: 16:16 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_16_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_16_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[16].de), + .d (hw2reg.intrpt_lvl_low_status[16].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[16].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_16_qs) + ); + + + // F[intrpt_lvl_low_status_17]: 17:17 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_17_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_17_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[17].de), + .d (hw2reg.intrpt_lvl_low_status[17].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[17].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_17_qs) + ); + + + // F[intrpt_lvl_low_status_18]: 18:18 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_18_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_18_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[18].de), + .d (hw2reg.intrpt_lvl_low_status[18].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[18].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_18_qs) + ); + + + // F[intrpt_lvl_low_status_19]: 19:19 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_19_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_19_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[19].de), + .d (hw2reg.intrpt_lvl_low_status[19].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[19].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_19_qs) + ); + + + // F[intrpt_lvl_low_status_20]: 20:20 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_20_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_20_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[20].de), + .d (hw2reg.intrpt_lvl_low_status[20].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[20].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_20_qs) + ); + + + // F[intrpt_lvl_low_status_21]: 21:21 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_21_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_21_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[21].de), + .d (hw2reg.intrpt_lvl_low_status[21].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[21].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_21_qs) + ); + + + // F[intrpt_lvl_low_status_22]: 22:22 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_22_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_22_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[22].de), + .d (hw2reg.intrpt_lvl_low_status[22].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[22].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_22_qs) + ); + + + // F[intrpt_lvl_low_status_23]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_23_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_23_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[23].de), + .d (hw2reg.intrpt_lvl_low_status[23].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[23].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_23_qs) + ); + + + // F[intrpt_lvl_low_status_24]: 24:24 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_24_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_24_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[24].de), + .d (hw2reg.intrpt_lvl_low_status[24].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[24].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_24_qs) + ); + + + // F[intrpt_lvl_low_status_25]: 25:25 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_25_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_25_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[25].de), + .d (hw2reg.intrpt_lvl_low_status[25].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[25].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_25_qs) + ); + + + // F[intrpt_lvl_low_status_26]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_26_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_26_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[26].de), + .d (hw2reg.intrpt_lvl_low_status[26].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[26].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_26_qs) + ); + + + // F[intrpt_lvl_low_status_27]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_27_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_27_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[27].de), + .d (hw2reg.intrpt_lvl_low_status[27].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[27].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_27_qs) + ); + + + // F[intrpt_lvl_low_status_28]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_28_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_28_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[28].de), + .d (hw2reg.intrpt_lvl_low_status[28].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[28].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_28_qs) + ); + + + // F[intrpt_lvl_low_status_29]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_29_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_29_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[29].de), + .d (hw2reg.intrpt_lvl_low_status[29].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[29].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_29_qs) + ); + + + // F[intrpt_lvl_low_status_30]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_30_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_30_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[30].de), + .d (hw2reg.intrpt_lvl_low_status[30].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[30].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_30_qs) + ); + + + // F[intrpt_lvl_low_status_31]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_31_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_31_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[31].de), + .d (hw2reg.intrpt_lvl_low_status[31].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[31].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_31_qs) + ); + + + + + + logic [18:0] addr_hit; + always_comb begin + addr_hit = '0; + addr_hit[ 0] = (reg_addr == GPIO_INFO_OFFSET); + addr_hit[ 1] = (reg_addr == GPIO_CFG_OFFSET); + addr_hit[ 2] = (reg_addr == GPIO_GPIO_MODE_0_OFFSET); + addr_hit[ 3] = (reg_addr == GPIO_GPIO_MODE_1_OFFSET); + addr_hit[ 4] = (reg_addr == GPIO_GPIO_EN_OFFSET); + addr_hit[ 5] = (reg_addr == GPIO_GPIO_IN_OFFSET); + addr_hit[ 6] = (reg_addr == GPIO_GPIO_OUT_OFFSET); + addr_hit[ 7] = (reg_addr == GPIO_GPIO_SET_OFFSET); + addr_hit[ 8] = (reg_addr == GPIO_GPIO_CLEAR_OFFSET); + addr_hit[ 9] = (reg_addr == GPIO_GPIO_TOGGLE_OFFSET); + addr_hit[10] = (reg_addr == GPIO_INTRPT_RISE_EN_OFFSET); + addr_hit[11] = (reg_addr == GPIO_INTRPT_FALL_EN_OFFSET); + addr_hit[12] = (reg_addr == GPIO_INTRPT_LVL_HIGH_EN_OFFSET); + addr_hit[13] = (reg_addr == GPIO_INTRPT_LVL_LOW_EN_OFFSET); + addr_hit[14] = (reg_addr == GPIO_INTRPT_STATUS_OFFSET); + addr_hit[15] = (reg_addr == GPIO_INTRPT_RISE_STATUS_OFFSET); + addr_hit[16] = (reg_addr == GPIO_INTRPT_FALL_STATUS_OFFSET); + addr_hit[17] = (reg_addr == GPIO_INTRPT_LVL_HIGH_STATUS_OFFSET); + addr_hit[18] = (reg_addr == GPIO_INTRPT_LVL_LOW_STATUS_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(GPIO_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(GPIO_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(GPIO_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(GPIO_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(GPIO_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(GPIO_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(GPIO_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(GPIO_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(GPIO_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(GPIO_PERMIT[ 9] & ~reg_be))) | + (addr_hit[10] & (|(GPIO_PERMIT[10] & ~reg_be))) | + (addr_hit[11] & (|(GPIO_PERMIT[11] & ~reg_be))) | + (addr_hit[12] & (|(GPIO_PERMIT[12] & ~reg_be))) | + (addr_hit[13] & (|(GPIO_PERMIT[13] & ~reg_be))) | + (addr_hit[14] & (|(GPIO_PERMIT[14] & ~reg_be))) | + (addr_hit[15] & (|(GPIO_PERMIT[15] & ~reg_be))) | + (addr_hit[16] & (|(GPIO_PERMIT[16] & ~reg_be))) | + (addr_hit[17] & (|(GPIO_PERMIT[17] & ~reg_be))) | + (addr_hit[18] & (|(GPIO_PERMIT[18] & ~reg_be))))); + end + + assign info_gpio_cnt_re = addr_hit[0] & reg_re & !reg_error; + + assign info_version_re = addr_hit[0] & reg_re & !reg_error; + + assign cfg_glbl_intrpt_mode_we = addr_hit[1] & reg_we & !reg_error; + assign cfg_glbl_intrpt_mode_wd = reg_wdata[0]; + + assign cfg_pin_lvl_intrpt_mode_we = addr_hit[1] & reg_we & !reg_error; + assign cfg_pin_lvl_intrpt_mode_wd = reg_wdata[1]; + + assign gpio_mode_0_mode_0_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_0_wd = reg_wdata[1:0]; + + assign gpio_mode_0_mode_1_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_1_wd = reg_wdata[3:2]; + + assign gpio_mode_0_mode_2_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_2_wd = reg_wdata[5:4]; + + assign gpio_mode_0_mode_3_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_3_wd = reg_wdata[7:6]; + + assign gpio_mode_0_mode_4_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_4_wd = reg_wdata[9:8]; + + assign gpio_mode_0_mode_5_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_5_wd = reg_wdata[11:10]; + + assign gpio_mode_0_mode_6_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_6_wd = reg_wdata[13:12]; + + assign gpio_mode_0_mode_7_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_7_wd = reg_wdata[15:14]; + + assign gpio_mode_0_mode_8_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_8_wd = reg_wdata[17:16]; + + assign gpio_mode_0_mode_9_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_9_wd = reg_wdata[19:18]; + + assign gpio_mode_0_mode_10_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_10_wd = reg_wdata[21:20]; + + assign gpio_mode_0_mode_11_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_11_wd = reg_wdata[23:22]; + + assign gpio_mode_0_mode_12_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_12_wd = reg_wdata[25:24]; + + assign gpio_mode_0_mode_13_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_13_wd = reg_wdata[27:26]; + + assign gpio_mode_0_mode_14_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_14_wd = reg_wdata[29:28]; + + assign gpio_mode_0_mode_15_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_15_wd = reg_wdata[31:30]; + + assign gpio_mode_1_mode_16_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_16_wd = reg_wdata[1:0]; + + assign gpio_mode_1_mode_17_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_17_wd = reg_wdata[3:2]; + + assign gpio_mode_1_mode_18_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_18_wd = reg_wdata[5:4]; + + assign gpio_mode_1_mode_19_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_19_wd = reg_wdata[7:6]; + + assign gpio_mode_1_mode_20_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_20_wd = reg_wdata[9:8]; + + assign gpio_mode_1_mode_21_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_21_wd = reg_wdata[11:10]; + + assign gpio_mode_1_mode_22_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_22_wd = reg_wdata[13:12]; + + assign gpio_mode_1_mode_23_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_23_wd = reg_wdata[15:14]; + + assign gpio_mode_1_mode_24_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_24_wd = reg_wdata[17:16]; + + assign gpio_mode_1_mode_25_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_25_wd = reg_wdata[19:18]; + + assign gpio_mode_1_mode_26_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_26_wd = reg_wdata[21:20]; + + assign gpio_mode_1_mode_27_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_27_wd = reg_wdata[23:22]; + + assign gpio_mode_1_mode_28_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_28_wd = reg_wdata[25:24]; + + assign gpio_mode_1_mode_29_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_29_wd = reg_wdata[27:26]; + + assign gpio_mode_1_mode_30_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_30_wd = reg_wdata[29:28]; + + assign gpio_mode_1_mode_31_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_31_wd = reg_wdata[31:30]; + + assign gpio_en_gpio_en_0_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_0_wd = reg_wdata[0]; + + assign gpio_en_gpio_en_1_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_1_wd = reg_wdata[1]; + + assign gpio_en_gpio_en_2_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_2_wd = reg_wdata[2]; + + assign gpio_en_gpio_en_3_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_3_wd = reg_wdata[3]; + + assign gpio_en_gpio_en_4_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_4_wd = reg_wdata[4]; + + assign gpio_en_gpio_en_5_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_5_wd = reg_wdata[5]; + + assign gpio_en_gpio_en_6_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_6_wd = reg_wdata[6]; + + assign gpio_en_gpio_en_7_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_7_wd = reg_wdata[7]; + + assign gpio_en_gpio_en_8_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_8_wd = reg_wdata[8]; + + assign gpio_en_gpio_en_9_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_9_wd = reg_wdata[9]; + + assign gpio_en_gpio_en_10_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_10_wd = reg_wdata[10]; + + assign gpio_en_gpio_en_11_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_11_wd = reg_wdata[11]; + + assign gpio_en_gpio_en_12_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_12_wd = reg_wdata[12]; + + assign gpio_en_gpio_en_13_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_13_wd = reg_wdata[13]; + + assign gpio_en_gpio_en_14_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_14_wd = reg_wdata[14]; + + assign gpio_en_gpio_en_15_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_15_wd = reg_wdata[15]; + + assign gpio_en_gpio_en_16_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_16_wd = reg_wdata[16]; + + assign gpio_en_gpio_en_17_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_17_wd = reg_wdata[17]; + + assign gpio_en_gpio_en_18_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_18_wd = reg_wdata[18]; + + assign gpio_en_gpio_en_19_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_19_wd = reg_wdata[19]; + + assign gpio_en_gpio_en_20_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_20_wd = reg_wdata[20]; + + assign gpio_en_gpio_en_21_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_21_wd = reg_wdata[21]; + + assign gpio_en_gpio_en_22_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_22_wd = reg_wdata[22]; + + assign gpio_en_gpio_en_23_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_23_wd = reg_wdata[23]; + + assign gpio_en_gpio_en_24_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_24_wd = reg_wdata[24]; + + assign gpio_en_gpio_en_25_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_25_wd = reg_wdata[25]; + + assign gpio_en_gpio_en_26_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_26_wd = reg_wdata[26]; + + assign gpio_en_gpio_en_27_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_27_wd = reg_wdata[27]; + + assign gpio_en_gpio_en_28_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_28_wd = reg_wdata[28]; + + assign gpio_en_gpio_en_29_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_29_wd = reg_wdata[29]; + + assign gpio_en_gpio_en_30_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_30_wd = reg_wdata[30]; + + assign gpio_en_gpio_en_31_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_31_wd = reg_wdata[31]; + + assign gpio_in_gpio_in_0_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_1_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_2_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_3_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_4_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_5_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_6_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_7_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_8_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_9_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_10_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_11_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_12_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_13_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_14_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_15_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_16_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_17_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_18_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_19_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_20_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_21_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_22_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_23_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_24_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_25_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_26_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_27_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_28_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_29_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_30_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_31_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_out_gpio_out_0_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_0_wd = reg_wdata[0]; + + assign gpio_out_gpio_out_1_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_1_wd = reg_wdata[1]; + + assign gpio_out_gpio_out_2_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_2_wd = reg_wdata[2]; + + assign gpio_out_gpio_out_3_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_3_wd = reg_wdata[3]; + + assign gpio_out_gpio_out_4_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_4_wd = reg_wdata[4]; + + assign gpio_out_gpio_out_5_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_5_wd = reg_wdata[5]; + + assign gpio_out_gpio_out_6_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_6_wd = reg_wdata[6]; + + assign gpio_out_gpio_out_7_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_7_wd = reg_wdata[7]; + + assign gpio_out_gpio_out_8_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_8_wd = reg_wdata[8]; + + assign gpio_out_gpio_out_9_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_9_wd = reg_wdata[9]; + + assign gpio_out_gpio_out_10_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_10_wd = reg_wdata[10]; + + assign gpio_out_gpio_out_11_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_11_wd = reg_wdata[11]; + + assign gpio_out_gpio_out_12_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_12_wd = reg_wdata[12]; + + assign gpio_out_gpio_out_13_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_13_wd = reg_wdata[13]; + + assign gpio_out_gpio_out_14_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_14_wd = reg_wdata[14]; + + assign gpio_out_gpio_out_15_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_15_wd = reg_wdata[15]; + + assign gpio_out_gpio_out_16_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_16_wd = reg_wdata[16]; + + assign gpio_out_gpio_out_17_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_17_wd = reg_wdata[17]; + + assign gpio_out_gpio_out_18_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_18_wd = reg_wdata[18]; + + assign gpio_out_gpio_out_19_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_19_wd = reg_wdata[19]; + + assign gpio_out_gpio_out_20_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_20_wd = reg_wdata[20]; + + assign gpio_out_gpio_out_21_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_21_wd = reg_wdata[21]; + + assign gpio_out_gpio_out_22_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_22_wd = reg_wdata[22]; + + assign gpio_out_gpio_out_23_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_23_wd = reg_wdata[23]; + + assign gpio_out_gpio_out_24_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_24_wd = reg_wdata[24]; + + assign gpio_out_gpio_out_25_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_25_wd = reg_wdata[25]; + + assign gpio_out_gpio_out_26_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_26_wd = reg_wdata[26]; + + assign gpio_out_gpio_out_27_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_27_wd = reg_wdata[27]; + + assign gpio_out_gpio_out_28_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_28_wd = reg_wdata[28]; + + assign gpio_out_gpio_out_29_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_29_wd = reg_wdata[29]; + + assign gpio_out_gpio_out_30_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_30_wd = reg_wdata[30]; + + assign gpio_out_gpio_out_31_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_31_wd = reg_wdata[31]; + + assign gpio_set_gpio_set_0_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_0_wd = reg_wdata[0]; + + assign gpio_set_gpio_set_1_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_1_wd = reg_wdata[1]; + + assign gpio_set_gpio_set_2_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_2_wd = reg_wdata[2]; + + assign gpio_set_gpio_set_3_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_3_wd = reg_wdata[3]; + + assign gpio_set_gpio_set_4_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_4_wd = reg_wdata[4]; + + assign gpio_set_gpio_set_5_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_5_wd = reg_wdata[5]; + + assign gpio_set_gpio_set_6_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_6_wd = reg_wdata[6]; + + assign gpio_set_gpio_set_7_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_7_wd = reg_wdata[7]; + + assign gpio_set_gpio_set_8_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_8_wd = reg_wdata[8]; + + assign gpio_set_gpio_set_9_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_9_wd = reg_wdata[9]; + + assign gpio_set_gpio_set_10_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_10_wd = reg_wdata[10]; + + assign gpio_set_gpio_set_11_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_11_wd = reg_wdata[11]; + + assign gpio_set_gpio_set_12_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_12_wd = reg_wdata[12]; + + assign gpio_set_gpio_set_13_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_13_wd = reg_wdata[13]; + + assign gpio_set_gpio_set_14_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_14_wd = reg_wdata[14]; + + assign gpio_set_gpio_set_15_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_15_wd = reg_wdata[15]; + + assign gpio_set_gpio_set_16_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_16_wd = reg_wdata[16]; + + assign gpio_set_gpio_set_17_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_17_wd = reg_wdata[17]; + + assign gpio_set_gpio_set_18_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_18_wd = reg_wdata[18]; + + assign gpio_set_gpio_set_19_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_19_wd = reg_wdata[19]; + + assign gpio_set_gpio_set_20_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_20_wd = reg_wdata[20]; + + assign gpio_set_gpio_set_21_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_21_wd = reg_wdata[21]; + + assign gpio_set_gpio_set_22_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_22_wd = reg_wdata[22]; + + assign gpio_set_gpio_set_23_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_23_wd = reg_wdata[23]; + + assign gpio_set_gpio_set_24_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_24_wd = reg_wdata[24]; + + assign gpio_set_gpio_set_25_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_25_wd = reg_wdata[25]; + + assign gpio_set_gpio_set_26_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_26_wd = reg_wdata[26]; + + assign gpio_set_gpio_set_27_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_27_wd = reg_wdata[27]; + + assign gpio_set_gpio_set_28_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_28_wd = reg_wdata[28]; + + assign gpio_set_gpio_set_29_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_29_wd = reg_wdata[29]; + + assign gpio_set_gpio_set_30_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_30_wd = reg_wdata[30]; + + assign gpio_set_gpio_set_31_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_31_wd = reg_wdata[31]; + + assign gpio_clear_gpio_clear_0_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_0_wd = reg_wdata[0]; + + assign gpio_clear_gpio_clear_1_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_1_wd = reg_wdata[1]; + + assign gpio_clear_gpio_clear_2_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_2_wd = reg_wdata[2]; + + assign gpio_clear_gpio_clear_3_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_3_wd = reg_wdata[3]; + + assign gpio_clear_gpio_clear_4_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_4_wd = reg_wdata[4]; + + assign gpio_clear_gpio_clear_5_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_5_wd = reg_wdata[5]; + + assign gpio_clear_gpio_clear_6_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_6_wd = reg_wdata[6]; + + assign gpio_clear_gpio_clear_7_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_7_wd = reg_wdata[7]; + + assign gpio_clear_gpio_clear_8_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_8_wd = reg_wdata[8]; + + assign gpio_clear_gpio_clear_9_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_9_wd = reg_wdata[9]; + + assign gpio_clear_gpio_clear_10_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_10_wd = reg_wdata[10]; + + assign gpio_clear_gpio_clear_11_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_11_wd = reg_wdata[11]; + + assign gpio_clear_gpio_clear_12_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_12_wd = reg_wdata[12]; + + assign gpio_clear_gpio_clear_13_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_13_wd = reg_wdata[13]; + + assign gpio_clear_gpio_clear_14_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_14_wd = reg_wdata[14]; + + assign gpio_clear_gpio_clear_15_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_15_wd = reg_wdata[15]; + + assign gpio_clear_gpio_clear_16_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_16_wd = reg_wdata[16]; + + assign gpio_clear_gpio_clear_17_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_17_wd = reg_wdata[17]; + + assign gpio_clear_gpio_clear_18_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_18_wd = reg_wdata[18]; + + assign gpio_clear_gpio_clear_19_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_19_wd = reg_wdata[19]; + + assign gpio_clear_gpio_clear_20_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_20_wd = reg_wdata[20]; + + assign gpio_clear_gpio_clear_21_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_21_wd = reg_wdata[21]; + + assign gpio_clear_gpio_clear_22_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_22_wd = reg_wdata[22]; + + assign gpio_clear_gpio_clear_23_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_23_wd = reg_wdata[23]; + + assign gpio_clear_gpio_clear_24_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_24_wd = reg_wdata[24]; + + assign gpio_clear_gpio_clear_25_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_25_wd = reg_wdata[25]; + + assign gpio_clear_gpio_clear_26_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_26_wd = reg_wdata[26]; + + assign gpio_clear_gpio_clear_27_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_27_wd = reg_wdata[27]; + + assign gpio_clear_gpio_clear_28_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_28_wd = reg_wdata[28]; + + assign gpio_clear_gpio_clear_29_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_29_wd = reg_wdata[29]; + + assign gpio_clear_gpio_clear_30_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_30_wd = reg_wdata[30]; + + assign gpio_clear_gpio_clear_31_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_31_wd = reg_wdata[31]; + + assign gpio_toggle_gpio_toggle_0_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_0_wd = reg_wdata[0]; + + assign gpio_toggle_gpio_toggle_1_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_1_wd = reg_wdata[1]; + + assign gpio_toggle_gpio_toggle_2_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_2_wd = reg_wdata[2]; + + assign gpio_toggle_gpio_toggle_3_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_3_wd = reg_wdata[3]; + + assign gpio_toggle_gpio_toggle_4_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_4_wd = reg_wdata[4]; + + assign gpio_toggle_gpio_toggle_5_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_5_wd = reg_wdata[5]; + + assign gpio_toggle_gpio_toggle_6_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_6_wd = reg_wdata[6]; + + assign gpio_toggle_gpio_toggle_7_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_7_wd = reg_wdata[7]; + + assign gpio_toggle_gpio_toggle_8_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_8_wd = reg_wdata[8]; + + assign gpio_toggle_gpio_toggle_9_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_9_wd = reg_wdata[9]; + + assign gpio_toggle_gpio_toggle_10_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_10_wd = reg_wdata[10]; + + assign gpio_toggle_gpio_toggle_11_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_11_wd = reg_wdata[11]; + + assign gpio_toggle_gpio_toggle_12_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_12_wd = reg_wdata[12]; + + assign gpio_toggle_gpio_toggle_13_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_13_wd = reg_wdata[13]; + + assign gpio_toggle_gpio_toggle_14_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_14_wd = reg_wdata[14]; + + assign gpio_toggle_gpio_toggle_15_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_15_wd = reg_wdata[15]; + + assign gpio_toggle_gpio_toggle_16_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_16_wd = reg_wdata[16]; + + assign gpio_toggle_gpio_toggle_17_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_17_wd = reg_wdata[17]; + + assign gpio_toggle_gpio_toggle_18_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_18_wd = reg_wdata[18]; + + assign gpio_toggle_gpio_toggle_19_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_19_wd = reg_wdata[19]; + + assign gpio_toggle_gpio_toggle_20_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_20_wd = reg_wdata[20]; + + assign gpio_toggle_gpio_toggle_21_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_21_wd = reg_wdata[21]; + + assign gpio_toggle_gpio_toggle_22_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_22_wd = reg_wdata[22]; + + assign gpio_toggle_gpio_toggle_23_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_23_wd = reg_wdata[23]; + + assign gpio_toggle_gpio_toggle_24_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_24_wd = reg_wdata[24]; + + assign gpio_toggle_gpio_toggle_25_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_25_wd = reg_wdata[25]; + + assign gpio_toggle_gpio_toggle_26_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_26_wd = reg_wdata[26]; + + assign gpio_toggle_gpio_toggle_27_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_27_wd = reg_wdata[27]; + + assign gpio_toggle_gpio_toggle_28_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_28_wd = reg_wdata[28]; + + assign gpio_toggle_gpio_toggle_29_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_29_wd = reg_wdata[29]; + + assign gpio_toggle_gpio_toggle_30_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_30_wd = reg_wdata[30]; + + assign gpio_toggle_gpio_toggle_31_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_31_wd = reg_wdata[31]; + + assign intrpt_rise_en_intrpt_rise_en_0_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_0_wd = reg_wdata[0]; + + assign intrpt_rise_en_intrpt_rise_en_1_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_1_wd = reg_wdata[1]; + + assign intrpt_rise_en_intrpt_rise_en_2_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_2_wd = reg_wdata[2]; + + assign intrpt_rise_en_intrpt_rise_en_3_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_3_wd = reg_wdata[3]; + + assign intrpt_rise_en_intrpt_rise_en_4_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_4_wd = reg_wdata[4]; + + assign intrpt_rise_en_intrpt_rise_en_5_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_5_wd = reg_wdata[5]; + + assign intrpt_rise_en_intrpt_rise_en_6_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_6_wd = reg_wdata[6]; + + assign intrpt_rise_en_intrpt_rise_en_7_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_7_wd = reg_wdata[7]; + + assign intrpt_rise_en_intrpt_rise_en_8_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_8_wd = reg_wdata[8]; + + assign intrpt_rise_en_intrpt_rise_en_9_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_9_wd = reg_wdata[9]; + + assign intrpt_rise_en_intrpt_rise_en_10_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_10_wd = reg_wdata[10]; + + assign intrpt_rise_en_intrpt_rise_en_11_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_11_wd = reg_wdata[11]; + + assign intrpt_rise_en_intrpt_rise_en_12_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_12_wd = reg_wdata[12]; + + assign intrpt_rise_en_intrpt_rise_en_13_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_13_wd = reg_wdata[13]; + + assign intrpt_rise_en_intrpt_rise_en_14_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_14_wd = reg_wdata[14]; + + assign intrpt_rise_en_intrpt_rise_en_15_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_15_wd = reg_wdata[15]; + + assign intrpt_rise_en_intrpt_rise_en_16_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_16_wd = reg_wdata[16]; + + assign intrpt_rise_en_intrpt_rise_en_17_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_17_wd = reg_wdata[17]; + + assign intrpt_rise_en_intrpt_rise_en_18_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_18_wd = reg_wdata[18]; + + assign intrpt_rise_en_intrpt_rise_en_19_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_19_wd = reg_wdata[19]; + + assign intrpt_rise_en_intrpt_rise_en_20_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_20_wd = reg_wdata[20]; + + assign intrpt_rise_en_intrpt_rise_en_21_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_21_wd = reg_wdata[21]; + + assign intrpt_rise_en_intrpt_rise_en_22_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_22_wd = reg_wdata[22]; + + assign intrpt_rise_en_intrpt_rise_en_23_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_23_wd = reg_wdata[23]; + + assign intrpt_rise_en_intrpt_rise_en_24_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_24_wd = reg_wdata[24]; + + assign intrpt_rise_en_intrpt_rise_en_25_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_25_wd = reg_wdata[25]; + + assign intrpt_rise_en_intrpt_rise_en_26_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_26_wd = reg_wdata[26]; + + assign intrpt_rise_en_intrpt_rise_en_27_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_27_wd = reg_wdata[27]; + + assign intrpt_rise_en_intrpt_rise_en_28_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_28_wd = reg_wdata[28]; + + assign intrpt_rise_en_intrpt_rise_en_29_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_29_wd = reg_wdata[29]; + + assign intrpt_rise_en_intrpt_rise_en_30_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_30_wd = reg_wdata[30]; + + assign intrpt_rise_en_intrpt_rise_en_31_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_31_wd = reg_wdata[31]; + + assign intrpt_fall_en_intrpt_fall_en_0_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_0_wd = reg_wdata[0]; + + assign intrpt_fall_en_intrpt_fall_en_1_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_1_wd = reg_wdata[1]; + + assign intrpt_fall_en_intrpt_fall_en_2_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_2_wd = reg_wdata[2]; + + assign intrpt_fall_en_intrpt_fall_en_3_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_3_wd = reg_wdata[3]; + + assign intrpt_fall_en_intrpt_fall_en_4_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_4_wd = reg_wdata[4]; + + assign intrpt_fall_en_intrpt_fall_en_5_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_5_wd = reg_wdata[5]; + + assign intrpt_fall_en_intrpt_fall_en_6_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_6_wd = reg_wdata[6]; + + assign intrpt_fall_en_intrpt_fall_en_7_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_7_wd = reg_wdata[7]; + + assign intrpt_fall_en_intrpt_fall_en_8_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_8_wd = reg_wdata[8]; + + assign intrpt_fall_en_intrpt_fall_en_9_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_9_wd = reg_wdata[9]; + + assign intrpt_fall_en_intrpt_fall_en_10_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_10_wd = reg_wdata[10]; + + assign intrpt_fall_en_intrpt_fall_en_11_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_11_wd = reg_wdata[11]; + + assign intrpt_fall_en_intrpt_fall_en_12_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_12_wd = reg_wdata[12]; + + assign intrpt_fall_en_intrpt_fall_en_13_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_13_wd = reg_wdata[13]; + + assign intrpt_fall_en_intrpt_fall_en_14_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_14_wd = reg_wdata[14]; + + assign intrpt_fall_en_intrpt_fall_en_15_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_15_wd = reg_wdata[15]; + + assign intrpt_fall_en_intrpt_fall_en_16_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_16_wd = reg_wdata[16]; + + assign intrpt_fall_en_intrpt_fall_en_17_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_17_wd = reg_wdata[17]; + + assign intrpt_fall_en_intrpt_fall_en_18_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_18_wd = reg_wdata[18]; + + assign intrpt_fall_en_intrpt_fall_en_19_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_19_wd = reg_wdata[19]; + + assign intrpt_fall_en_intrpt_fall_en_20_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_20_wd = reg_wdata[20]; + + assign intrpt_fall_en_intrpt_fall_en_21_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_21_wd = reg_wdata[21]; + + assign intrpt_fall_en_intrpt_fall_en_22_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_22_wd = reg_wdata[22]; + + assign intrpt_fall_en_intrpt_fall_en_23_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_23_wd = reg_wdata[23]; + + assign intrpt_fall_en_intrpt_fall_en_24_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_24_wd = reg_wdata[24]; + + assign intrpt_fall_en_intrpt_fall_en_25_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_25_wd = reg_wdata[25]; + + assign intrpt_fall_en_intrpt_fall_en_26_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_26_wd = reg_wdata[26]; + + assign intrpt_fall_en_intrpt_fall_en_27_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_27_wd = reg_wdata[27]; + + assign intrpt_fall_en_intrpt_fall_en_28_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_28_wd = reg_wdata[28]; + + assign intrpt_fall_en_intrpt_fall_en_29_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_29_wd = reg_wdata[29]; + + assign intrpt_fall_en_intrpt_fall_en_30_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_30_wd = reg_wdata[30]; + + assign intrpt_fall_en_intrpt_fall_en_31_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_31_wd = reg_wdata[31]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_0_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_0_wd = reg_wdata[0]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_1_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_1_wd = reg_wdata[1]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_2_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_2_wd = reg_wdata[2]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_3_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_3_wd = reg_wdata[3]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_4_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_4_wd = reg_wdata[4]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_5_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_5_wd = reg_wdata[5]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_6_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_6_wd = reg_wdata[6]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_7_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_7_wd = reg_wdata[7]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_8_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_8_wd = reg_wdata[8]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_9_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_9_wd = reg_wdata[9]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_10_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_10_wd = reg_wdata[10]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_11_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_11_wd = reg_wdata[11]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_12_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_12_wd = reg_wdata[12]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_13_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_13_wd = reg_wdata[13]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_14_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_14_wd = reg_wdata[14]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_15_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_15_wd = reg_wdata[15]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_16_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_16_wd = reg_wdata[16]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_17_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_17_wd = reg_wdata[17]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_18_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_18_wd = reg_wdata[18]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_19_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_19_wd = reg_wdata[19]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_20_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_20_wd = reg_wdata[20]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_21_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_21_wd = reg_wdata[21]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_22_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_22_wd = reg_wdata[22]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_23_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_23_wd = reg_wdata[23]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_24_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_24_wd = reg_wdata[24]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_25_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_25_wd = reg_wdata[25]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_26_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_26_wd = reg_wdata[26]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_27_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_27_wd = reg_wdata[27]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_28_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_28_wd = reg_wdata[28]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_29_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_29_wd = reg_wdata[29]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_30_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_30_wd = reg_wdata[30]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_31_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_31_wd = reg_wdata[31]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_0_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_0_wd = reg_wdata[0]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_1_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_1_wd = reg_wdata[1]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_2_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_2_wd = reg_wdata[2]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_3_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_3_wd = reg_wdata[3]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_4_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_4_wd = reg_wdata[4]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_5_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_5_wd = reg_wdata[5]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_6_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_6_wd = reg_wdata[6]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_7_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_7_wd = reg_wdata[7]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_8_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_8_wd = reg_wdata[8]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_9_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_9_wd = reg_wdata[9]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_10_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_10_wd = reg_wdata[10]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_11_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_11_wd = reg_wdata[11]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_12_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_12_wd = reg_wdata[12]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_13_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_13_wd = reg_wdata[13]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_14_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_14_wd = reg_wdata[14]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_15_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_15_wd = reg_wdata[15]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_16_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_16_wd = reg_wdata[16]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_17_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_17_wd = reg_wdata[17]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_18_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_18_wd = reg_wdata[18]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_19_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_19_wd = reg_wdata[19]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_20_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_20_wd = reg_wdata[20]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_21_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_21_wd = reg_wdata[21]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_22_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_22_wd = reg_wdata[22]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_23_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_23_wd = reg_wdata[23]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_24_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_24_wd = reg_wdata[24]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_25_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_25_wd = reg_wdata[25]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_26_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_26_wd = reg_wdata[26]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_27_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_27_wd = reg_wdata[27]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_28_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_28_wd = reg_wdata[28]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_29_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_29_wd = reg_wdata[29]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_30_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_30_wd = reg_wdata[30]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_31_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_31_wd = reg_wdata[31]; + + assign intrpt_status_intrpt_status_0_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_0_wd = reg_wdata[0]; + assign intrpt_status_intrpt_status_0_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_1_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_1_wd = reg_wdata[1]; + assign intrpt_status_intrpt_status_1_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_2_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_2_wd = reg_wdata[2]; + assign intrpt_status_intrpt_status_2_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_3_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_3_wd = reg_wdata[3]; + assign intrpt_status_intrpt_status_3_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_4_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_4_wd = reg_wdata[4]; + assign intrpt_status_intrpt_status_4_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_5_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_5_wd = reg_wdata[5]; + assign intrpt_status_intrpt_status_5_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_6_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_6_wd = reg_wdata[6]; + assign intrpt_status_intrpt_status_6_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_7_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_7_wd = reg_wdata[7]; + assign intrpt_status_intrpt_status_7_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_8_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_8_wd = reg_wdata[8]; + assign intrpt_status_intrpt_status_8_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_9_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_9_wd = reg_wdata[9]; + assign intrpt_status_intrpt_status_9_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_10_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_10_wd = reg_wdata[10]; + assign intrpt_status_intrpt_status_10_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_11_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_11_wd = reg_wdata[11]; + assign intrpt_status_intrpt_status_11_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_12_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_12_wd = reg_wdata[12]; + assign intrpt_status_intrpt_status_12_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_13_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_13_wd = reg_wdata[13]; + assign intrpt_status_intrpt_status_13_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_14_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_14_wd = reg_wdata[14]; + assign intrpt_status_intrpt_status_14_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_15_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_15_wd = reg_wdata[15]; + assign intrpt_status_intrpt_status_15_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_16_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_16_wd = reg_wdata[16]; + assign intrpt_status_intrpt_status_16_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_17_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_17_wd = reg_wdata[17]; + assign intrpt_status_intrpt_status_17_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_18_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_18_wd = reg_wdata[18]; + assign intrpt_status_intrpt_status_18_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_19_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_19_wd = reg_wdata[19]; + assign intrpt_status_intrpt_status_19_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_20_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_20_wd = reg_wdata[20]; + assign intrpt_status_intrpt_status_20_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_21_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_21_wd = reg_wdata[21]; + assign intrpt_status_intrpt_status_21_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_22_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_22_wd = reg_wdata[22]; + assign intrpt_status_intrpt_status_22_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_23_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_23_wd = reg_wdata[23]; + assign intrpt_status_intrpt_status_23_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_24_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_24_wd = reg_wdata[24]; + assign intrpt_status_intrpt_status_24_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_25_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_25_wd = reg_wdata[25]; + assign intrpt_status_intrpt_status_25_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_26_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_26_wd = reg_wdata[26]; + assign intrpt_status_intrpt_status_26_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_27_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_27_wd = reg_wdata[27]; + assign intrpt_status_intrpt_status_27_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_28_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_28_wd = reg_wdata[28]; + assign intrpt_status_intrpt_status_28_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_29_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_29_wd = reg_wdata[29]; + assign intrpt_status_intrpt_status_29_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_30_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_30_wd = reg_wdata[30]; + assign intrpt_status_intrpt_status_30_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_31_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_31_wd = reg_wdata[31]; + assign intrpt_status_intrpt_status_31_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_rise_status_intrpt_rise_status_0_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_0_wd = reg_wdata[0]; + + assign intrpt_rise_status_intrpt_rise_status_1_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_1_wd = reg_wdata[1]; + + assign intrpt_rise_status_intrpt_rise_status_2_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_2_wd = reg_wdata[2]; + + assign intrpt_rise_status_intrpt_rise_status_3_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_3_wd = reg_wdata[3]; + + assign intrpt_rise_status_intrpt_rise_status_4_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_4_wd = reg_wdata[4]; + + assign intrpt_rise_status_intrpt_rise_status_5_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_5_wd = reg_wdata[5]; + + assign intrpt_rise_status_intrpt_rise_status_6_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_6_wd = reg_wdata[6]; + + assign intrpt_rise_status_intrpt_rise_status_7_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_7_wd = reg_wdata[7]; + + assign intrpt_rise_status_intrpt_rise_status_8_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_8_wd = reg_wdata[8]; + + assign intrpt_rise_status_intrpt_rise_status_9_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_9_wd = reg_wdata[9]; + + assign intrpt_rise_status_intrpt_rise_status_10_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_10_wd = reg_wdata[10]; + + assign intrpt_rise_status_intrpt_rise_status_11_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_11_wd = reg_wdata[11]; + + assign intrpt_rise_status_intrpt_rise_status_12_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_12_wd = reg_wdata[12]; + + assign intrpt_rise_status_intrpt_rise_status_13_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_13_wd = reg_wdata[13]; + + assign intrpt_rise_status_intrpt_rise_status_14_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_14_wd = reg_wdata[14]; + + assign intrpt_rise_status_intrpt_rise_status_15_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_15_wd = reg_wdata[15]; + + assign intrpt_rise_status_intrpt_rise_status_16_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_16_wd = reg_wdata[16]; + + assign intrpt_rise_status_intrpt_rise_status_17_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_17_wd = reg_wdata[17]; + + assign intrpt_rise_status_intrpt_rise_status_18_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_18_wd = reg_wdata[18]; + + assign intrpt_rise_status_intrpt_rise_status_19_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_19_wd = reg_wdata[19]; + + assign intrpt_rise_status_intrpt_rise_status_20_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_20_wd = reg_wdata[20]; + + assign intrpt_rise_status_intrpt_rise_status_21_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_21_wd = reg_wdata[21]; + + assign intrpt_rise_status_intrpt_rise_status_22_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_22_wd = reg_wdata[22]; + + assign intrpt_rise_status_intrpt_rise_status_23_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_23_wd = reg_wdata[23]; + + assign intrpt_rise_status_intrpt_rise_status_24_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_24_wd = reg_wdata[24]; + + assign intrpt_rise_status_intrpt_rise_status_25_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_25_wd = reg_wdata[25]; + + assign intrpt_rise_status_intrpt_rise_status_26_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_26_wd = reg_wdata[26]; + + assign intrpt_rise_status_intrpt_rise_status_27_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_27_wd = reg_wdata[27]; + + assign intrpt_rise_status_intrpt_rise_status_28_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_28_wd = reg_wdata[28]; + + assign intrpt_rise_status_intrpt_rise_status_29_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_29_wd = reg_wdata[29]; + + assign intrpt_rise_status_intrpt_rise_status_30_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_30_wd = reg_wdata[30]; + + assign intrpt_rise_status_intrpt_rise_status_31_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_31_wd = reg_wdata[31]; + + assign intrpt_fall_status_intrpt_fall_status_0_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_0_wd = reg_wdata[0]; + + assign intrpt_fall_status_intrpt_fall_status_1_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_1_wd = reg_wdata[1]; + + assign intrpt_fall_status_intrpt_fall_status_2_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_2_wd = reg_wdata[2]; + + assign intrpt_fall_status_intrpt_fall_status_3_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_3_wd = reg_wdata[3]; + + assign intrpt_fall_status_intrpt_fall_status_4_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_4_wd = reg_wdata[4]; + + assign intrpt_fall_status_intrpt_fall_status_5_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_5_wd = reg_wdata[5]; + + assign intrpt_fall_status_intrpt_fall_status_6_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_6_wd = reg_wdata[6]; + + assign intrpt_fall_status_intrpt_fall_status_7_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_7_wd = reg_wdata[7]; + + assign intrpt_fall_status_intrpt_fall_status_8_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_8_wd = reg_wdata[8]; + + assign intrpt_fall_status_intrpt_fall_status_9_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_9_wd = reg_wdata[9]; + + assign intrpt_fall_status_intrpt_fall_status_10_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_10_wd = reg_wdata[10]; + + assign intrpt_fall_status_intrpt_fall_status_11_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_11_wd = reg_wdata[11]; + + assign intrpt_fall_status_intrpt_fall_status_12_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_12_wd = reg_wdata[12]; + + assign intrpt_fall_status_intrpt_fall_status_13_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_13_wd = reg_wdata[13]; + + assign intrpt_fall_status_intrpt_fall_status_14_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_14_wd = reg_wdata[14]; + + assign intrpt_fall_status_intrpt_fall_status_15_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_15_wd = reg_wdata[15]; + + assign intrpt_fall_status_intrpt_fall_status_16_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_16_wd = reg_wdata[16]; + + assign intrpt_fall_status_intrpt_fall_status_17_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_17_wd = reg_wdata[17]; + + assign intrpt_fall_status_intrpt_fall_status_18_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_18_wd = reg_wdata[18]; + + assign intrpt_fall_status_intrpt_fall_status_19_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_19_wd = reg_wdata[19]; + + assign intrpt_fall_status_intrpt_fall_status_20_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_20_wd = reg_wdata[20]; + + assign intrpt_fall_status_intrpt_fall_status_21_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_21_wd = reg_wdata[21]; + + assign intrpt_fall_status_intrpt_fall_status_22_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_22_wd = reg_wdata[22]; + + assign intrpt_fall_status_intrpt_fall_status_23_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_23_wd = reg_wdata[23]; + + assign intrpt_fall_status_intrpt_fall_status_24_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_24_wd = reg_wdata[24]; + + assign intrpt_fall_status_intrpt_fall_status_25_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_25_wd = reg_wdata[25]; + + assign intrpt_fall_status_intrpt_fall_status_26_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_26_wd = reg_wdata[26]; + + assign intrpt_fall_status_intrpt_fall_status_27_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_27_wd = reg_wdata[27]; + + assign intrpt_fall_status_intrpt_fall_status_28_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_28_wd = reg_wdata[28]; + + assign intrpt_fall_status_intrpt_fall_status_29_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_29_wd = reg_wdata[29]; + + assign intrpt_fall_status_intrpt_fall_status_30_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_30_wd = reg_wdata[30]; + + assign intrpt_fall_status_intrpt_fall_status_31_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_31_wd = reg_wdata[31]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_0_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_0_wd = reg_wdata[0]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_1_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_1_wd = reg_wdata[1]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_2_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_2_wd = reg_wdata[2]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_3_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_3_wd = reg_wdata[3]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_4_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_4_wd = reg_wdata[4]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_5_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_5_wd = reg_wdata[5]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_6_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_6_wd = reg_wdata[6]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_7_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_7_wd = reg_wdata[7]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_8_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_8_wd = reg_wdata[8]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_9_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_9_wd = reg_wdata[9]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_10_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_10_wd = reg_wdata[10]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_11_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_11_wd = reg_wdata[11]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_12_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_12_wd = reg_wdata[12]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_13_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_13_wd = reg_wdata[13]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_14_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_14_wd = reg_wdata[14]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_15_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_15_wd = reg_wdata[15]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_16_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_16_wd = reg_wdata[16]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_17_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_17_wd = reg_wdata[17]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_18_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_18_wd = reg_wdata[18]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_19_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_19_wd = reg_wdata[19]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_20_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_20_wd = reg_wdata[20]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_21_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_21_wd = reg_wdata[21]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_22_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_22_wd = reg_wdata[22]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_23_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_23_wd = reg_wdata[23]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_24_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_24_wd = reg_wdata[24]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_25_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_25_wd = reg_wdata[25]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_26_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_26_wd = reg_wdata[26]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_27_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_27_wd = reg_wdata[27]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_28_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_28_wd = reg_wdata[28]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_29_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_29_wd = reg_wdata[29]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_30_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_30_wd = reg_wdata[30]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_31_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_31_wd = reg_wdata[31]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_0_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_0_wd = reg_wdata[0]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_1_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_1_wd = reg_wdata[1]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_2_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_2_wd = reg_wdata[2]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_3_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_3_wd = reg_wdata[3]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_4_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_4_wd = reg_wdata[4]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_5_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_5_wd = reg_wdata[5]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_6_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_6_wd = reg_wdata[6]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_7_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_7_wd = reg_wdata[7]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_8_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_8_wd = reg_wdata[8]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_9_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_9_wd = reg_wdata[9]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_10_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_10_wd = reg_wdata[10]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_11_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_11_wd = reg_wdata[11]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_12_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_12_wd = reg_wdata[12]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_13_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_13_wd = reg_wdata[13]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_14_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_14_wd = reg_wdata[14]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_15_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_15_wd = reg_wdata[15]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_16_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_16_wd = reg_wdata[16]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_17_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_17_wd = reg_wdata[17]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_18_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_18_wd = reg_wdata[18]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_19_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_19_wd = reg_wdata[19]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_20_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_20_wd = reg_wdata[20]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_21_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_21_wd = reg_wdata[21]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_22_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_22_wd = reg_wdata[22]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_23_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_23_wd = reg_wdata[23]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_24_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_24_wd = reg_wdata[24]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_25_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_25_wd = reg_wdata[25]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_26_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_26_wd = reg_wdata[26]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_27_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_27_wd = reg_wdata[27]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_28_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_28_wd = reg_wdata[28]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_29_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_29_wd = reg_wdata[29]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_30_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_30_wd = reg_wdata[30]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_31_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_31_wd = reg_wdata[31]; + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[9:0] = info_gpio_cnt_qs; + reg_rdata_next[19:10] = info_version_qs; + end + + addr_hit[1]: begin + reg_rdata_next[0] = cfg_glbl_intrpt_mode_qs; + reg_rdata_next[1] = cfg_pin_lvl_intrpt_mode_qs; + end + + addr_hit[2]: begin + reg_rdata_next[1:0] = gpio_mode_0_mode_0_qs; + reg_rdata_next[3:2] = gpio_mode_0_mode_1_qs; + reg_rdata_next[5:4] = gpio_mode_0_mode_2_qs; + reg_rdata_next[7:6] = gpio_mode_0_mode_3_qs; + reg_rdata_next[9:8] = gpio_mode_0_mode_4_qs; + reg_rdata_next[11:10] = gpio_mode_0_mode_5_qs; + reg_rdata_next[13:12] = gpio_mode_0_mode_6_qs; + reg_rdata_next[15:14] = gpio_mode_0_mode_7_qs; + reg_rdata_next[17:16] = gpio_mode_0_mode_8_qs; + reg_rdata_next[19:18] = gpio_mode_0_mode_9_qs; + reg_rdata_next[21:20] = gpio_mode_0_mode_10_qs; + reg_rdata_next[23:22] = gpio_mode_0_mode_11_qs; + reg_rdata_next[25:24] = gpio_mode_0_mode_12_qs; + reg_rdata_next[27:26] = gpio_mode_0_mode_13_qs; + reg_rdata_next[29:28] = gpio_mode_0_mode_14_qs; + reg_rdata_next[31:30] = gpio_mode_0_mode_15_qs; + end + + addr_hit[3]: begin + reg_rdata_next[1:0] = gpio_mode_1_mode_16_qs; + reg_rdata_next[3:2] = gpio_mode_1_mode_17_qs; + reg_rdata_next[5:4] = gpio_mode_1_mode_18_qs; + reg_rdata_next[7:6] = gpio_mode_1_mode_19_qs; + reg_rdata_next[9:8] = gpio_mode_1_mode_20_qs; + reg_rdata_next[11:10] = gpio_mode_1_mode_21_qs; + reg_rdata_next[13:12] = gpio_mode_1_mode_22_qs; + reg_rdata_next[15:14] = gpio_mode_1_mode_23_qs; + reg_rdata_next[17:16] = gpio_mode_1_mode_24_qs; + reg_rdata_next[19:18] = gpio_mode_1_mode_25_qs; + reg_rdata_next[21:20] = gpio_mode_1_mode_26_qs; + reg_rdata_next[23:22] = gpio_mode_1_mode_27_qs; + reg_rdata_next[25:24] = gpio_mode_1_mode_28_qs; + reg_rdata_next[27:26] = gpio_mode_1_mode_29_qs; + reg_rdata_next[29:28] = gpio_mode_1_mode_30_qs; + reg_rdata_next[31:30] = gpio_mode_1_mode_31_qs; + end + + addr_hit[4]: begin + reg_rdata_next[0] = gpio_en_gpio_en_0_qs; + reg_rdata_next[1] = gpio_en_gpio_en_1_qs; + reg_rdata_next[2] = gpio_en_gpio_en_2_qs; + reg_rdata_next[3] = gpio_en_gpio_en_3_qs; + reg_rdata_next[4] = gpio_en_gpio_en_4_qs; + reg_rdata_next[5] = gpio_en_gpio_en_5_qs; + reg_rdata_next[6] = gpio_en_gpio_en_6_qs; + reg_rdata_next[7] = gpio_en_gpio_en_7_qs; + reg_rdata_next[8] = gpio_en_gpio_en_8_qs; + reg_rdata_next[9] = gpio_en_gpio_en_9_qs; + reg_rdata_next[10] = gpio_en_gpio_en_10_qs; + reg_rdata_next[11] = gpio_en_gpio_en_11_qs; + reg_rdata_next[12] = gpio_en_gpio_en_12_qs; + reg_rdata_next[13] = gpio_en_gpio_en_13_qs; + reg_rdata_next[14] = gpio_en_gpio_en_14_qs; + reg_rdata_next[15] = gpio_en_gpio_en_15_qs; + reg_rdata_next[16] = gpio_en_gpio_en_16_qs; + reg_rdata_next[17] = gpio_en_gpio_en_17_qs; + reg_rdata_next[18] = gpio_en_gpio_en_18_qs; + reg_rdata_next[19] = gpio_en_gpio_en_19_qs; + reg_rdata_next[20] = gpio_en_gpio_en_20_qs; + reg_rdata_next[21] = gpio_en_gpio_en_21_qs; + reg_rdata_next[22] = gpio_en_gpio_en_22_qs; + reg_rdata_next[23] = gpio_en_gpio_en_23_qs; + reg_rdata_next[24] = gpio_en_gpio_en_24_qs; + reg_rdata_next[25] = gpio_en_gpio_en_25_qs; + reg_rdata_next[26] = gpio_en_gpio_en_26_qs; + reg_rdata_next[27] = gpio_en_gpio_en_27_qs; + reg_rdata_next[28] = gpio_en_gpio_en_28_qs; + reg_rdata_next[29] = gpio_en_gpio_en_29_qs; + reg_rdata_next[30] = gpio_en_gpio_en_30_qs; + reg_rdata_next[31] = gpio_en_gpio_en_31_qs; + end + + addr_hit[5]: begin + reg_rdata_next[0] = gpio_in_gpio_in_0_qs; + reg_rdata_next[1] = gpio_in_gpio_in_1_qs; + reg_rdata_next[2] = gpio_in_gpio_in_2_qs; + reg_rdata_next[3] = gpio_in_gpio_in_3_qs; + reg_rdata_next[4] = gpio_in_gpio_in_4_qs; + reg_rdata_next[5] = gpio_in_gpio_in_5_qs; + reg_rdata_next[6] = gpio_in_gpio_in_6_qs; + reg_rdata_next[7] = gpio_in_gpio_in_7_qs; + reg_rdata_next[8] = gpio_in_gpio_in_8_qs; + reg_rdata_next[9] = gpio_in_gpio_in_9_qs; + reg_rdata_next[10] = gpio_in_gpio_in_10_qs; + reg_rdata_next[11] = gpio_in_gpio_in_11_qs; + reg_rdata_next[12] = gpio_in_gpio_in_12_qs; + reg_rdata_next[13] = gpio_in_gpio_in_13_qs; + reg_rdata_next[14] = gpio_in_gpio_in_14_qs; + reg_rdata_next[15] = gpio_in_gpio_in_15_qs; + reg_rdata_next[16] = gpio_in_gpio_in_16_qs; + reg_rdata_next[17] = gpio_in_gpio_in_17_qs; + reg_rdata_next[18] = gpio_in_gpio_in_18_qs; + reg_rdata_next[19] = gpio_in_gpio_in_19_qs; + reg_rdata_next[20] = gpio_in_gpio_in_20_qs; + reg_rdata_next[21] = gpio_in_gpio_in_21_qs; + reg_rdata_next[22] = gpio_in_gpio_in_22_qs; + reg_rdata_next[23] = gpio_in_gpio_in_23_qs; + reg_rdata_next[24] = gpio_in_gpio_in_24_qs; + reg_rdata_next[25] = gpio_in_gpio_in_25_qs; + reg_rdata_next[26] = gpio_in_gpio_in_26_qs; + reg_rdata_next[27] = gpio_in_gpio_in_27_qs; + reg_rdata_next[28] = gpio_in_gpio_in_28_qs; + reg_rdata_next[29] = gpio_in_gpio_in_29_qs; + reg_rdata_next[30] = gpio_in_gpio_in_30_qs; + reg_rdata_next[31] = gpio_in_gpio_in_31_qs; + end + + addr_hit[6]: begin + reg_rdata_next[0] = gpio_out_gpio_out_0_qs; + reg_rdata_next[1] = gpio_out_gpio_out_1_qs; + reg_rdata_next[2] = gpio_out_gpio_out_2_qs; + reg_rdata_next[3] = gpio_out_gpio_out_3_qs; + reg_rdata_next[4] = gpio_out_gpio_out_4_qs; + reg_rdata_next[5] = gpio_out_gpio_out_5_qs; + reg_rdata_next[6] = gpio_out_gpio_out_6_qs; + reg_rdata_next[7] = gpio_out_gpio_out_7_qs; + reg_rdata_next[8] = gpio_out_gpio_out_8_qs; + reg_rdata_next[9] = gpio_out_gpio_out_9_qs; + reg_rdata_next[10] = gpio_out_gpio_out_10_qs; + reg_rdata_next[11] = gpio_out_gpio_out_11_qs; + reg_rdata_next[12] = gpio_out_gpio_out_12_qs; + reg_rdata_next[13] = gpio_out_gpio_out_13_qs; + reg_rdata_next[14] = gpio_out_gpio_out_14_qs; + reg_rdata_next[15] = gpio_out_gpio_out_15_qs; + reg_rdata_next[16] = gpio_out_gpio_out_16_qs; + reg_rdata_next[17] = gpio_out_gpio_out_17_qs; + reg_rdata_next[18] = gpio_out_gpio_out_18_qs; + reg_rdata_next[19] = gpio_out_gpio_out_19_qs; + reg_rdata_next[20] = gpio_out_gpio_out_20_qs; + reg_rdata_next[21] = gpio_out_gpio_out_21_qs; + reg_rdata_next[22] = gpio_out_gpio_out_22_qs; + reg_rdata_next[23] = gpio_out_gpio_out_23_qs; + reg_rdata_next[24] = gpio_out_gpio_out_24_qs; + reg_rdata_next[25] = gpio_out_gpio_out_25_qs; + reg_rdata_next[26] = gpio_out_gpio_out_26_qs; + reg_rdata_next[27] = gpio_out_gpio_out_27_qs; + reg_rdata_next[28] = gpio_out_gpio_out_28_qs; + reg_rdata_next[29] = gpio_out_gpio_out_29_qs; + reg_rdata_next[30] = gpio_out_gpio_out_30_qs; + reg_rdata_next[31] = gpio_out_gpio_out_31_qs; + end + + addr_hit[7]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + reg_rdata_next[2] = '0; + reg_rdata_next[3] = '0; + reg_rdata_next[4] = '0; + reg_rdata_next[5] = '0; + reg_rdata_next[6] = '0; + reg_rdata_next[7] = '0; + reg_rdata_next[8] = '0; + reg_rdata_next[9] = '0; + reg_rdata_next[10] = '0; + reg_rdata_next[11] = '0; + reg_rdata_next[12] = '0; + reg_rdata_next[13] = '0; + reg_rdata_next[14] = '0; + reg_rdata_next[15] = '0; + reg_rdata_next[16] = '0; + reg_rdata_next[17] = '0; + reg_rdata_next[18] = '0; + reg_rdata_next[19] = '0; + reg_rdata_next[20] = '0; + reg_rdata_next[21] = '0; + reg_rdata_next[22] = '0; + reg_rdata_next[23] = '0; + reg_rdata_next[24] = '0; + reg_rdata_next[25] = '0; + reg_rdata_next[26] = '0; + reg_rdata_next[27] = '0; + reg_rdata_next[28] = '0; + reg_rdata_next[29] = '0; + reg_rdata_next[30] = '0; + reg_rdata_next[31] = '0; + end + + addr_hit[8]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + reg_rdata_next[2] = '0; + reg_rdata_next[3] = '0; + reg_rdata_next[4] = '0; + reg_rdata_next[5] = '0; + reg_rdata_next[6] = '0; + reg_rdata_next[7] = '0; + reg_rdata_next[8] = '0; + reg_rdata_next[9] = '0; + reg_rdata_next[10] = '0; + reg_rdata_next[11] = '0; + reg_rdata_next[12] = '0; + reg_rdata_next[13] = '0; + reg_rdata_next[14] = '0; + reg_rdata_next[15] = '0; + reg_rdata_next[16] = '0; + reg_rdata_next[17] = '0; + reg_rdata_next[18] = '0; + reg_rdata_next[19] = '0; + reg_rdata_next[20] = '0; + reg_rdata_next[21] = '0; + reg_rdata_next[22] = '0; + reg_rdata_next[23] = '0; + reg_rdata_next[24] = '0; + reg_rdata_next[25] = '0; + reg_rdata_next[26] = '0; + reg_rdata_next[27] = '0; + reg_rdata_next[28] = '0; + reg_rdata_next[29] = '0; + reg_rdata_next[30] = '0; + reg_rdata_next[31] = '0; + end + + addr_hit[9]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + reg_rdata_next[2] = '0; + reg_rdata_next[3] = '0; + reg_rdata_next[4] = '0; + reg_rdata_next[5] = '0; + reg_rdata_next[6] = '0; + reg_rdata_next[7] = '0; + reg_rdata_next[8] = '0; + reg_rdata_next[9] = '0; + reg_rdata_next[10] = '0; + reg_rdata_next[11] = '0; + reg_rdata_next[12] = '0; + reg_rdata_next[13] = '0; + reg_rdata_next[14] = '0; + reg_rdata_next[15] = '0; + reg_rdata_next[16] = '0; + reg_rdata_next[17] = '0; + reg_rdata_next[18] = '0; + reg_rdata_next[19] = '0; + reg_rdata_next[20] = '0; + reg_rdata_next[21] = '0; + reg_rdata_next[22] = '0; + reg_rdata_next[23] = '0; + reg_rdata_next[24] = '0; + reg_rdata_next[25] = '0; + reg_rdata_next[26] = '0; + reg_rdata_next[27] = '0; + reg_rdata_next[28] = '0; + reg_rdata_next[29] = '0; + reg_rdata_next[30] = '0; + reg_rdata_next[31] = '0; + end + + addr_hit[10]: begin + reg_rdata_next[0] = intrpt_rise_en_intrpt_rise_en_0_qs; + reg_rdata_next[1] = intrpt_rise_en_intrpt_rise_en_1_qs; + reg_rdata_next[2] = intrpt_rise_en_intrpt_rise_en_2_qs; + reg_rdata_next[3] = intrpt_rise_en_intrpt_rise_en_3_qs; + reg_rdata_next[4] = intrpt_rise_en_intrpt_rise_en_4_qs; + reg_rdata_next[5] = intrpt_rise_en_intrpt_rise_en_5_qs; + reg_rdata_next[6] = intrpt_rise_en_intrpt_rise_en_6_qs; + reg_rdata_next[7] = intrpt_rise_en_intrpt_rise_en_7_qs; + reg_rdata_next[8] = intrpt_rise_en_intrpt_rise_en_8_qs; + reg_rdata_next[9] = intrpt_rise_en_intrpt_rise_en_9_qs; + reg_rdata_next[10] = intrpt_rise_en_intrpt_rise_en_10_qs; + reg_rdata_next[11] = intrpt_rise_en_intrpt_rise_en_11_qs; + reg_rdata_next[12] = intrpt_rise_en_intrpt_rise_en_12_qs; + reg_rdata_next[13] = intrpt_rise_en_intrpt_rise_en_13_qs; + reg_rdata_next[14] = intrpt_rise_en_intrpt_rise_en_14_qs; + reg_rdata_next[15] = intrpt_rise_en_intrpt_rise_en_15_qs; + reg_rdata_next[16] = intrpt_rise_en_intrpt_rise_en_16_qs; + reg_rdata_next[17] = intrpt_rise_en_intrpt_rise_en_17_qs; + reg_rdata_next[18] = intrpt_rise_en_intrpt_rise_en_18_qs; + reg_rdata_next[19] = intrpt_rise_en_intrpt_rise_en_19_qs; + reg_rdata_next[20] = intrpt_rise_en_intrpt_rise_en_20_qs; + reg_rdata_next[21] = intrpt_rise_en_intrpt_rise_en_21_qs; + reg_rdata_next[22] = intrpt_rise_en_intrpt_rise_en_22_qs; + reg_rdata_next[23] = intrpt_rise_en_intrpt_rise_en_23_qs; + reg_rdata_next[24] = intrpt_rise_en_intrpt_rise_en_24_qs; + reg_rdata_next[25] = intrpt_rise_en_intrpt_rise_en_25_qs; + reg_rdata_next[26] = intrpt_rise_en_intrpt_rise_en_26_qs; + reg_rdata_next[27] = intrpt_rise_en_intrpt_rise_en_27_qs; + reg_rdata_next[28] = intrpt_rise_en_intrpt_rise_en_28_qs; + reg_rdata_next[29] = intrpt_rise_en_intrpt_rise_en_29_qs; + reg_rdata_next[30] = intrpt_rise_en_intrpt_rise_en_30_qs; + reg_rdata_next[31] = intrpt_rise_en_intrpt_rise_en_31_qs; + end + + addr_hit[11]: begin + reg_rdata_next[0] = intrpt_fall_en_intrpt_fall_en_0_qs; + reg_rdata_next[1] = intrpt_fall_en_intrpt_fall_en_1_qs; + reg_rdata_next[2] = intrpt_fall_en_intrpt_fall_en_2_qs; + reg_rdata_next[3] = intrpt_fall_en_intrpt_fall_en_3_qs; + reg_rdata_next[4] = intrpt_fall_en_intrpt_fall_en_4_qs; + reg_rdata_next[5] = intrpt_fall_en_intrpt_fall_en_5_qs; + reg_rdata_next[6] = intrpt_fall_en_intrpt_fall_en_6_qs; + reg_rdata_next[7] = intrpt_fall_en_intrpt_fall_en_7_qs; + reg_rdata_next[8] = intrpt_fall_en_intrpt_fall_en_8_qs; + reg_rdata_next[9] = intrpt_fall_en_intrpt_fall_en_9_qs; + reg_rdata_next[10] = intrpt_fall_en_intrpt_fall_en_10_qs; + reg_rdata_next[11] = intrpt_fall_en_intrpt_fall_en_11_qs; + reg_rdata_next[12] = intrpt_fall_en_intrpt_fall_en_12_qs; + reg_rdata_next[13] = intrpt_fall_en_intrpt_fall_en_13_qs; + reg_rdata_next[14] = intrpt_fall_en_intrpt_fall_en_14_qs; + reg_rdata_next[15] = intrpt_fall_en_intrpt_fall_en_15_qs; + reg_rdata_next[16] = intrpt_fall_en_intrpt_fall_en_16_qs; + reg_rdata_next[17] = intrpt_fall_en_intrpt_fall_en_17_qs; + reg_rdata_next[18] = intrpt_fall_en_intrpt_fall_en_18_qs; + reg_rdata_next[19] = intrpt_fall_en_intrpt_fall_en_19_qs; + reg_rdata_next[20] = intrpt_fall_en_intrpt_fall_en_20_qs; + reg_rdata_next[21] = intrpt_fall_en_intrpt_fall_en_21_qs; + reg_rdata_next[22] = intrpt_fall_en_intrpt_fall_en_22_qs; + reg_rdata_next[23] = intrpt_fall_en_intrpt_fall_en_23_qs; + reg_rdata_next[24] = intrpt_fall_en_intrpt_fall_en_24_qs; + reg_rdata_next[25] = intrpt_fall_en_intrpt_fall_en_25_qs; + reg_rdata_next[26] = intrpt_fall_en_intrpt_fall_en_26_qs; + reg_rdata_next[27] = intrpt_fall_en_intrpt_fall_en_27_qs; + reg_rdata_next[28] = intrpt_fall_en_intrpt_fall_en_28_qs; + reg_rdata_next[29] = intrpt_fall_en_intrpt_fall_en_29_qs; + reg_rdata_next[30] = intrpt_fall_en_intrpt_fall_en_30_qs; + reg_rdata_next[31] = intrpt_fall_en_intrpt_fall_en_31_qs; + end + + addr_hit[12]: begin + reg_rdata_next[0] = intrpt_lvl_high_en_intrpt_lvl_high_en_0_qs; + reg_rdata_next[1] = intrpt_lvl_high_en_intrpt_lvl_high_en_1_qs; + reg_rdata_next[2] = intrpt_lvl_high_en_intrpt_lvl_high_en_2_qs; + reg_rdata_next[3] = intrpt_lvl_high_en_intrpt_lvl_high_en_3_qs; + reg_rdata_next[4] = intrpt_lvl_high_en_intrpt_lvl_high_en_4_qs; + reg_rdata_next[5] = intrpt_lvl_high_en_intrpt_lvl_high_en_5_qs; + reg_rdata_next[6] = intrpt_lvl_high_en_intrpt_lvl_high_en_6_qs; + reg_rdata_next[7] = intrpt_lvl_high_en_intrpt_lvl_high_en_7_qs; + reg_rdata_next[8] = intrpt_lvl_high_en_intrpt_lvl_high_en_8_qs; + reg_rdata_next[9] = intrpt_lvl_high_en_intrpt_lvl_high_en_9_qs; + reg_rdata_next[10] = intrpt_lvl_high_en_intrpt_lvl_high_en_10_qs; + reg_rdata_next[11] = intrpt_lvl_high_en_intrpt_lvl_high_en_11_qs; + reg_rdata_next[12] = intrpt_lvl_high_en_intrpt_lvl_high_en_12_qs; + reg_rdata_next[13] = intrpt_lvl_high_en_intrpt_lvl_high_en_13_qs; + reg_rdata_next[14] = intrpt_lvl_high_en_intrpt_lvl_high_en_14_qs; + reg_rdata_next[15] = intrpt_lvl_high_en_intrpt_lvl_high_en_15_qs; + reg_rdata_next[16] = intrpt_lvl_high_en_intrpt_lvl_high_en_16_qs; + reg_rdata_next[17] = intrpt_lvl_high_en_intrpt_lvl_high_en_17_qs; + reg_rdata_next[18] = intrpt_lvl_high_en_intrpt_lvl_high_en_18_qs; + reg_rdata_next[19] = intrpt_lvl_high_en_intrpt_lvl_high_en_19_qs; + reg_rdata_next[20] = intrpt_lvl_high_en_intrpt_lvl_high_en_20_qs; + reg_rdata_next[21] = intrpt_lvl_high_en_intrpt_lvl_high_en_21_qs; + reg_rdata_next[22] = intrpt_lvl_high_en_intrpt_lvl_high_en_22_qs; + reg_rdata_next[23] = intrpt_lvl_high_en_intrpt_lvl_high_en_23_qs; + reg_rdata_next[24] = intrpt_lvl_high_en_intrpt_lvl_high_en_24_qs; + reg_rdata_next[25] = intrpt_lvl_high_en_intrpt_lvl_high_en_25_qs; + reg_rdata_next[26] = intrpt_lvl_high_en_intrpt_lvl_high_en_26_qs; + reg_rdata_next[27] = intrpt_lvl_high_en_intrpt_lvl_high_en_27_qs; + reg_rdata_next[28] = intrpt_lvl_high_en_intrpt_lvl_high_en_28_qs; + reg_rdata_next[29] = intrpt_lvl_high_en_intrpt_lvl_high_en_29_qs; + reg_rdata_next[30] = intrpt_lvl_high_en_intrpt_lvl_high_en_30_qs; + reg_rdata_next[31] = intrpt_lvl_high_en_intrpt_lvl_high_en_31_qs; + end + + addr_hit[13]: begin + reg_rdata_next[0] = intrpt_lvl_low_en_intrpt_lvl_low_en_0_qs; + reg_rdata_next[1] = intrpt_lvl_low_en_intrpt_lvl_low_en_1_qs; + reg_rdata_next[2] = intrpt_lvl_low_en_intrpt_lvl_low_en_2_qs; + reg_rdata_next[3] = intrpt_lvl_low_en_intrpt_lvl_low_en_3_qs; + reg_rdata_next[4] = intrpt_lvl_low_en_intrpt_lvl_low_en_4_qs; + reg_rdata_next[5] = intrpt_lvl_low_en_intrpt_lvl_low_en_5_qs; + reg_rdata_next[6] = intrpt_lvl_low_en_intrpt_lvl_low_en_6_qs; + reg_rdata_next[7] = intrpt_lvl_low_en_intrpt_lvl_low_en_7_qs; + reg_rdata_next[8] = intrpt_lvl_low_en_intrpt_lvl_low_en_8_qs; + reg_rdata_next[9] = intrpt_lvl_low_en_intrpt_lvl_low_en_9_qs; + reg_rdata_next[10] = intrpt_lvl_low_en_intrpt_lvl_low_en_10_qs; + reg_rdata_next[11] = intrpt_lvl_low_en_intrpt_lvl_low_en_11_qs; + reg_rdata_next[12] = intrpt_lvl_low_en_intrpt_lvl_low_en_12_qs; + reg_rdata_next[13] = intrpt_lvl_low_en_intrpt_lvl_low_en_13_qs; + reg_rdata_next[14] = intrpt_lvl_low_en_intrpt_lvl_low_en_14_qs; + reg_rdata_next[15] = intrpt_lvl_low_en_intrpt_lvl_low_en_15_qs; + reg_rdata_next[16] = intrpt_lvl_low_en_intrpt_lvl_low_en_16_qs; + reg_rdata_next[17] = intrpt_lvl_low_en_intrpt_lvl_low_en_17_qs; + reg_rdata_next[18] = intrpt_lvl_low_en_intrpt_lvl_low_en_18_qs; + reg_rdata_next[19] = intrpt_lvl_low_en_intrpt_lvl_low_en_19_qs; + reg_rdata_next[20] = intrpt_lvl_low_en_intrpt_lvl_low_en_20_qs; + reg_rdata_next[21] = intrpt_lvl_low_en_intrpt_lvl_low_en_21_qs; + reg_rdata_next[22] = intrpt_lvl_low_en_intrpt_lvl_low_en_22_qs; + reg_rdata_next[23] = intrpt_lvl_low_en_intrpt_lvl_low_en_23_qs; + reg_rdata_next[24] = intrpt_lvl_low_en_intrpt_lvl_low_en_24_qs; + reg_rdata_next[25] = intrpt_lvl_low_en_intrpt_lvl_low_en_25_qs; + reg_rdata_next[26] = intrpt_lvl_low_en_intrpt_lvl_low_en_26_qs; + reg_rdata_next[27] = intrpt_lvl_low_en_intrpt_lvl_low_en_27_qs; + reg_rdata_next[28] = intrpt_lvl_low_en_intrpt_lvl_low_en_28_qs; + reg_rdata_next[29] = intrpt_lvl_low_en_intrpt_lvl_low_en_29_qs; + reg_rdata_next[30] = intrpt_lvl_low_en_intrpt_lvl_low_en_30_qs; + reg_rdata_next[31] = intrpt_lvl_low_en_intrpt_lvl_low_en_31_qs; + end + + addr_hit[14]: begin + reg_rdata_next[0] = intrpt_status_intrpt_status_0_qs; + reg_rdata_next[1] = intrpt_status_intrpt_status_1_qs; + reg_rdata_next[2] = intrpt_status_intrpt_status_2_qs; + reg_rdata_next[3] = intrpt_status_intrpt_status_3_qs; + reg_rdata_next[4] = intrpt_status_intrpt_status_4_qs; + reg_rdata_next[5] = intrpt_status_intrpt_status_5_qs; + reg_rdata_next[6] = intrpt_status_intrpt_status_6_qs; + reg_rdata_next[7] = intrpt_status_intrpt_status_7_qs; + reg_rdata_next[8] = intrpt_status_intrpt_status_8_qs; + reg_rdata_next[9] = intrpt_status_intrpt_status_9_qs; + reg_rdata_next[10] = intrpt_status_intrpt_status_10_qs; + reg_rdata_next[11] = intrpt_status_intrpt_status_11_qs; + reg_rdata_next[12] = intrpt_status_intrpt_status_12_qs; + reg_rdata_next[13] = intrpt_status_intrpt_status_13_qs; + reg_rdata_next[14] = intrpt_status_intrpt_status_14_qs; + reg_rdata_next[15] = intrpt_status_intrpt_status_15_qs; + reg_rdata_next[16] = intrpt_status_intrpt_status_16_qs; + reg_rdata_next[17] = intrpt_status_intrpt_status_17_qs; + reg_rdata_next[18] = intrpt_status_intrpt_status_18_qs; + reg_rdata_next[19] = intrpt_status_intrpt_status_19_qs; + reg_rdata_next[20] = intrpt_status_intrpt_status_20_qs; + reg_rdata_next[21] = intrpt_status_intrpt_status_21_qs; + reg_rdata_next[22] = intrpt_status_intrpt_status_22_qs; + reg_rdata_next[23] = intrpt_status_intrpt_status_23_qs; + reg_rdata_next[24] = intrpt_status_intrpt_status_24_qs; + reg_rdata_next[25] = intrpt_status_intrpt_status_25_qs; + reg_rdata_next[26] = intrpt_status_intrpt_status_26_qs; + reg_rdata_next[27] = intrpt_status_intrpt_status_27_qs; + reg_rdata_next[28] = intrpt_status_intrpt_status_28_qs; + reg_rdata_next[29] = intrpt_status_intrpt_status_29_qs; + reg_rdata_next[30] = intrpt_status_intrpt_status_30_qs; + reg_rdata_next[31] = intrpt_status_intrpt_status_31_qs; + end + + addr_hit[15]: begin + reg_rdata_next[0] = intrpt_rise_status_intrpt_rise_status_0_qs; + reg_rdata_next[1] = intrpt_rise_status_intrpt_rise_status_1_qs; + reg_rdata_next[2] = intrpt_rise_status_intrpt_rise_status_2_qs; + reg_rdata_next[3] = intrpt_rise_status_intrpt_rise_status_3_qs; + reg_rdata_next[4] = intrpt_rise_status_intrpt_rise_status_4_qs; + reg_rdata_next[5] = intrpt_rise_status_intrpt_rise_status_5_qs; + reg_rdata_next[6] = intrpt_rise_status_intrpt_rise_status_6_qs; + reg_rdata_next[7] = intrpt_rise_status_intrpt_rise_status_7_qs; + reg_rdata_next[8] = intrpt_rise_status_intrpt_rise_status_8_qs; + reg_rdata_next[9] = intrpt_rise_status_intrpt_rise_status_9_qs; + reg_rdata_next[10] = intrpt_rise_status_intrpt_rise_status_10_qs; + reg_rdata_next[11] = intrpt_rise_status_intrpt_rise_status_11_qs; + reg_rdata_next[12] = intrpt_rise_status_intrpt_rise_status_12_qs; + reg_rdata_next[13] = intrpt_rise_status_intrpt_rise_status_13_qs; + reg_rdata_next[14] = intrpt_rise_status_intrpt_rise_status_14_qs; + reg_rdata_next[15] = intrpt_rise_status_intrpt_rise_status_15_qs; + reg_rdata_next[16] = intrpt_rise_status_intrpt_rise_status_16_qs; + reg_rdata_next[17] = intrpt_rise_status_intrpt_rise_status_17_qs; + reg_rdata_next[18] = intrpt_rise_status_intrpt_rise_status_18_qs; + reg_rdata_next[19] = intrpt_rise_status_intrpt_rise_status_19_qs; + reg_rdata_next[20] = intrpt_rise_status_intrpt_rise_status_20_qs; + reg_rdata_next[21] = intrpt_rise_status_intrpt_rise_status_21_qs; + reg_rdata_next[22] = intrpt_rise_status_intrpt_rise_status_22_qs; + reg_rdata_next[23] = intrpt_rise_status_intrpt_rise_status_23_qs; + reg_rdata_next[24] = intrpt_rise_status_intrpt_rise_status_24_qs; + reg_rdata_next[25] = intrpt_rise_status_intrpt_rise_status_25_qs; + reg_rdata_next[26] = intrpt_rise_status_intrpt_rise_status_26_qs; + reg_rdata_next[27] = intrpt_rise_status_intrpt_rise_status_27_qs; + reg_rdata_next[28] = intrpt_rise_status_intrpt_rise_status_28_qs; + reg_rdata_next[29] = intrpt_rise_status_intrpt_rise_status_29_qs; + reg_rdata_next[30] = intrpt_rise_status_intrpt_rise_status_30_qs; + reg_rdata_next[31] = intrpt_rise_status_intrpt_rise_status_31_qs; + end + + addr_hit[16]: begin + reg_rdata_next[0] = intrpt_fall_status_intrpt_fall_status_0_qs; + reg_rdata_next[1] = intrpt_fall_status_intrpt_fall_status_1_qs; + reg_rdata_next[2] = intrpt_fall_status_intrpt_fall_status_2_qs; + reg_rdata_next[3] = intrpt_fall_status_intrpt_fall_status_3_qs; + reg_rdata_next[4] = intrpt_fall_status_intrpt_fall_status_4_qs; + reg_rdata_next[5] = intrpt_fall_status_intrpt_fall_status_5_qs; + reg_rdata_next[6] = intrpt_fall_status_intrpt_fall_status_6_qs; + reg_rdata_next[7] = intrpt_fall_status_intrpt_fall_status_7_qs; + reg_rdata_next[8] = intrpt_fall_status_intrpt_fall_status_8_qs; + reg_rdata_next[9] = intrpt_fall_status_intrpt_fall_status_9_qs; + reg_rdata_next[10] = intrpt_fall_status_intrpt_fall_status_10_qs; + reg_rdata_next[11] = intrpt_fall_status_intrpt_fall_status_11_qs; + reg_rdata_next[12] = intrpt_fall_status_intrpt_fall_status_12_qs; + reg_rdata_next[13] = intrpt_fall_status_intrpt_fall_status_13_qs; + reg_rdata_next[14] = intrpt_fall_status_intrpt_fall_status_14_qs; + reg_rdata_next[15] = intrpt_fall_status_intrpt_fall_status_15_qs; + reg_rdata_next[16] = intrpt_fall_status_intrpt_fall_status_16_qs; + reg_rdata_next[17] = intrpt_fall_status_intrpt_fall_status_17_qs; + reg_rdata_next[18] = intrpt_fall_status_intrpt_fall_status_18_qs; + reg_rdata_next[19] = intrpt_fall_status_intrpt_fall_status_19_qs; + reg_rdata_next[20] = intrpt_fall_status_intrpt_fall_status_20_qs; + reg_rdata_next[21] = intrpt_fall_status_intrpt_fall_status_21_qs; + reg_rdata_next[22] = intrpt_fall_status_intrpt_fall_status_22_qs; + reg_rdata_next[23] = intrpt_fall_status_intrpt_fall_status_23_qs; + reg_rdata_next[24] = intrpt_fall_status_intrpt_fall_status_24_qs; + reg_rdata_next[25] = intrpt_fall_status_intrpt_fall_status_25_qs; + reg_rdata_next[26] = intrpt_fall_status_intrpt_fall_status_26_qs; + reg_rdata_next[27] = intrpt_fall_status_intrpt_fall_status_27_qs; + reg_rdata_next[28] = intrpt_fall_status_intrpt_fall_status_28_qs; + reg_rdata_next[29] = intrpt_fall_status_intrpt_fall_status_29_qs; + reg_rdata_next[30] = intrpt_fall_status_intrpt_fall_status_30_qs; + reg_rdata_next[31] = intrpt_fall_status_intrpt_fall_status_31_qs; + end + + addr_hit[17]: begin + reg_rdata_next[0] = intrpt_lvl_high_status_intrpt_lvl_high_status_0_qs; + reg_rdata_next[1] = intrpt_lvl_high_status_intrpt_lvl_high_status_1_qs; + reg_rdata_next[2] = intrpt_lvl_high_status_intrpt_lvl_high_status_2_qs; + reg_rdata_next[3] = intrpt_lvl_high_status_intrpt_lvl_high_status_3_qs; + reg_rdata_next[4] = intrpt_lvl_high_status_intrpt_lvl_high_status_4_qs; + reg_rdata_next[5] = intrpt_lvl_high_status_intrpt_lvl_high_status_5_qs; + reg_rdata_next[6] = intrpt_lvl_high_status_intrpt_lvl_high_status_6_qs; + reg_rdata_next[7] = intrpt_lvl_high_status_intrpt_lvl_high_status_7_qs; + reg_rdata_next[8] = intrpt_lvl_high_status_intrpt_lvl_high_status_8_qs; + reg_rdata_next[9] = intrpt_lvl_high_status_intrpt_lvl_high_status_9_qs; + reg_rdata_next[10] = intrpt_lvl_high_status_intrpt_lvl_high_status_10_qs; + reg_rdata_next[11] = intrpt_lvl_high_status_intrpt_lvl_high_status_11_qs; + reg_rdata_next[12] = intrpt_lvl_high_status_intrpt_lvl_high_status_12_qs; + reg_rdata_next[13] = intrpt_lvl_high_status_intrpt_lvl_high_status_13_qs; + reg_rdata_next[14] = intrpt_lvl_high_status_intrpt_lvl_high_status_14_qs; + reg_rdata_next[15] = intrpt_lvl_high_status_intrpt_lvl_high_status_15_qs; + reg_rdata_next[16] = intrpt_lvl_high_status_intrpt_lvl_high_status_16_qs; + reg_rdata_next[17] = intrpt_lvl_high_status_intrpt_lvl_high_status_17_qs; + reg_rdata_next[18] = intrpt_lvl_high_status_intrpt_lvl_high_status_18_qs; + reg_rdata_next[19] = intrpt_lvl_high_status_intrpt_lvl_high_status_19_qs; + reg_rdata_next[20] = intrpt_lvl_high_status_intrpt_lvl_high_status_20_qs; + reg_rdata_next[21] = intrpt_lvl_high_status_intrpt_lvl_high_status_21_qs; + reg_rdata_next[22] = intrpt_lvl_high_status_intrpt_lvl_high_status_22_qs; + reg_rdata_next[23] = intrpt_lvl_high_status_intrpt_lvl_high_status_23_qs; + reg_rdata_next[24] = intrpt_lvl_high_status_intrpt_lvl_high_status_24_qs; + reg_rdata_next[25] = intrpt_lvl_high_status_intrpt_lvl_high_status_25_qs; + reg_rdata_next[26] = intrpt_lvl_high_status_intrpt_lvl_high_status_26_qs; + reg_rdata_next[27] = intrpt_lvl_high_status_intrpt_lvl_high_status_27_qs; + reg_rdata_next[28] = intrpt_lvl_high_status_intrpt_lvl_high_status_28_qs; + reg_rdata_next[29] = intrpt_lvl_high_status_intrpt_lvl_high_status_29_qs; + reg_rdata_next[30] = intrpt_lvl_high_status_intrpt_lvl_high_status_30_qs; + reg_rdata_next[31] = intrpt_lvl_high_status_intrpt_lvl_high_status_31_qs; + end + + addr_hit[18]: begin + reg_rdata_next[0] = intrpt_lvl_low_status_intrpt_lvl_low_status_0_qs; + reg_rdata_next[1] = intrpt_lvl_low_status_intrpt_lvl_low_status_1_qs; + reg_rdata_next[2] = intrpt_lvl_low_status_intrpt_lvl_low_status_2_qs; + reg_rdata_next[3] = intrpt_lvl_low_status_intrpt_lvl_low_status_3_qs; + reg_rdata_next[4] = intrpt_lvl_low_status_intrpt_lvl_low_status_4_qs; + reg_rdata_next[5] = intrpt_lvl_low_status_intrpt_lvl_low_status_5_qs; + reg_rdata_next[6] = intrpt_lvl_low_status_intrpt_lvl_low_status_6_qs; + reg_rdata_next[7] = intrpt_lvl_low_status_intrpt_lvl_low_status_7_qs; + reg_rdata_next[8] = intrpt_lvl_low_status_intrpt_lvl_low_status_8_qs; + reg_rdata_next[9] = intrpt_lvl_low_status_intrpt_lvl_low_status_9_qs; + reg_rdata_next[10] = intrpt_lvl_low_status_intrpt_lvl_low_status_10_qs; + reg_rdata_next[11] = intrpt_lvl_low_status_intrpt_lvl_low_status_11_qs; + reg_rdata_next[12] = intrpt_lvl_low_status_intrpt_lvl_low_status_12_qs; + reg_rdata_next[13] = intrpt_lvl_low_status_intrpt_lvl_low_status_13_qs; + reg_rdata_next[14] = intrpt_lvl_low_status_intrpt_lvl_low_status_14_qs; + reg_rdata_next[15] = intrpt_lvl_low_status_intrpt_lvl_low_status_15_qs; + reg_rdata_next[16] = intrpt_lvl_low_status_intrpt_lvl_low_status_16_qs; + reg_rdata_next[17] = intrpt_lvl_low_status_intrpt_lvl_low_status_17_qs; + reg_rdata_next[18] = intrpt_lvl_low_status_intrpt_lvl_low_status_18_qs; + reg_rdata_next[19] = intrpt_lvl_low_status_intrpt_lvl_low_status_19_qs; + reg_rdata_next[20] = intrpt_lvl_low_status_intrpt_lvl_low_status_20_qs; + reg_rdata_next[21] = intrpt_lvl_low_status_intrpt_lvl_low_status_21_qs; + reg_rdata_next[22] = intrpt_lvl_low_status_intrpt_lvl_low_status_22_qs; + reg_rdata_next[23] = intrpt_lvl_low_status_intrpt_lvl_low_status_23_qs; + reg_rdata_next[24] = intrpt_lvl_low_status_intrpt_lvl_low_status_24_qs; + reg_rdata_next[25] = intrpt_lvl_low_status_intrpt_lvl_low_status_25_qs; + reg_rdata_next[26] = intrpt_lvl_low_status_intrpt_lvl_low_status_26_qs; + reg_rdata_next[27] = intrpt_lvl_low_status_intrpt_lvl_low_status_27_qs; + reg_rdata_next[28] = intrpt_lvl_low_status_intrpt_lvl_low_status_28_qs; + reg_rdata_next[29] = intrpt_lvl_low_status_intrpt_lvl_low_status_29_qs; + reg_rdata_next[30] = intrpt_lvl_low_status_intrpt_lvl_low_status_30_qs; + reg_rdata_next[31] = intrpt_lvl_low_status_intrpt_lvl_low_status_31_qs; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit)) + +endmodule + +module gpio_reg_top_intf +#( + parameter int AW = 11, + localparam int DW = 32 +) ( + input logic clk_i, + input logic rst_ni, + REG_BUS.in regbus_slave, + // To HW + output gpio_reg_pkg::gpio_reg2hw_t reg2hw, // Write + input gpio_reg_pkg::gpio_hw2reg_t hw2reg, // Read + // Config + input devmode_i // If 1, explicit error return for unmapped register access +); + localparam int unsigned STRB_WIDTH = DW/8; + +`include "register_interface/typedef.svh" +`include "register_interface/assign.svh" + + // Define structs for reg_bus + typedef logic [AW-1:0] addr_t; + typedef logic [DW-1:0] data_t; + typedef logic [STRB_WIDTH-1:0] strb_t; + `REG_BUS_TYPEDEF_ALL(reg_bus, addr_t, data_t, strb_t) + + reg_bus_req_t s_reg_req; + reg_bus_rsp_t s_reg_rsp; + + // Assign SV interface to structs + `REG_BUS_ASSIGN_TO_REQ(s_reg_req, regbus_slave) + `REG_BUS_ASSIGN_FROM_RSP(regbus_slave, s_reg_rsp) + + + + gpio_reg_top #( + .reg_req_t(reg_bus_req_t), + .reg_rsp_t(reg_bus_rsp_t), + .AW(AW) + ) i_regs ( + .clk_i, + .rst_ni, + .reg_req_i(s_reg_req), + .reg_rsp_o(s_reg_rsp), + .reg2hw, // Write + .hw2reg, // Read + .devmode_i + ); + +endmodule + + diff --git a/hw/vendored_ips/gpio/test/tb_gpio.sv b/hw/vendored_ips/gpio/test/tb_gpio.sv new file mode 100644 index 00000000..4ae7b5b6 --- /dev/null +++ b/hw/vendored_ips/gpio/test/tb_gpio.sv @@ -0,0 +1,952 @@ +//----------------------------------------------------------------------------- +// Title : GPIO Testbench +//----------------------------------------------------------------------------- +// File : tb_gpio.sv +// Author : Manuel Eggimann +// Created : 07.05.2021 +//----------------------------------------------------------------------------- +// Description : +// Test the functionality of the GPIO Peripheral +//----------------------------------------------------------------------------- +// Copyright (C) 2013-2021 ETH Zurich, University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +//----------------------------------------------------------------------------- + + +`define SV_RAND_CHECK(r) \ +do begin \ + if (!(r)) begin \ + $display("%s:%0d: Randomization failed \"%s\"", `__FILE__, `__LINE__, `"r`"); \ + $stop;\ + end\ +end while (0) + +// Unfortunately, the reggen tool has very inconsistent naming rules for multi +// regs. The generated parameters use a suffixed index for multireg iff there +// are at least two registers. If we generate less then 32 GPIOs the multiregs +// will only contain a single reg instance. In that case, the current version of +// reggen will ommit the suffix which causes issues in this TB we thus use this +// preproc macro workaround to alias to the right regs in this case. The +// 'reconfigure' target in the makefile will take care of enabling/disabling the +// workaround as needed. Thus DO NOT TOUCH THE FOLLOWING TWO LINES MANUALLY. + +//`define ENABLE_LESS_THAN_16_GPIOS_REG_PKG_WORKAROUND +`define ENABLE_LESS_THAN_32_GPIOS_REG_PKG_WORKAROUND + +module tb_gpio; + localparam ClkPeriod = 10ns; + localparam RstCycles = 6; + localparam ApplTime = 1ns; + localparam TestTime = 8ns; + localparam DataWidth = 32; + localparam AddrWidth = 32; + parameter NumRepetitions = 20; + localparam SimTimeoutCycles = 5000*NumRepetitions; // Timeout the simulation after 5000 cycles + localparam NrGPIOs = gpio_reg_pkg::GPIOCount; + + // Testbench control signals + logic clk; + logic rst_n; + logic end_of_sim; + + // Generate clock and reset + clk_rst_gen #( + .ClkPeriod ( ClkPeriod ), + .RstClkCycles ( RstCycles ) + ) i_clk_rst_gen ( + .clk_o ( clk ), + .rst_no( rst_n ) + ); + + // Test Timeout Module + sim_timeout #( + .Cycles(SimTimeoutCycles) + ) i_sim_timeout( + .clk_i ( clk ), + .rst_ni ( rst_n ) + ); + + // End of test procedure + initial begin : proc_end_of_test + wait (end_of_sim); + repeat (100) @(posedge clk); + $info("Simulation ended."); + $stop(); + end + + // Interface Signals + REG_BUS #( + .ADDR_WIDTH (AddrWidth), + .DATA_WIDTH (DataWidth)) s_reg_bus (.clk_i(clk)); + + logic [NrGPIOs-1:0] gpio_in; + logic [NrGPIOs-1:0] gpio_in_sync; + logic [NrGPIOs-1:0] gpio_out; + logic [NrGPIOs-1:0] gpio_tx_en; + logic global_interrupt; + + + // Instantiate DUT + gpio_intf #( + .ADDR_WIDTH ( AddrWidth ), + .DATA_WIDTH ( DataWidth ) + ) i_dut ( + .reg_bus ( s_reg_bus.in ), + // Outputs + .gpio_out ( gpio_out[NrGPIOs-1:0] ), + .gpio_tx_en_o ( gpio_tx_en[NrGPIOs-1:0] ), + .gpio_in_sync_o ( gpio_in_sync[NrGPIOs-1:0] ), + .global_interrupt_o ( global_interrupt ), + .pin_level_interrupts_o ( ), + // Inputs + .clk_i ( clk ), + .rst_ni ( rst_n ), + .gpio_in ( gpio_in[NrGPIOs-1:0] ) + ); + + // Connect test programm + test #( + .NrGPIOs ( NrGPIOs ), + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .ApplTime ( ApplTime ), + .TestTime ( TestTime ), + .NumRepetitions ( NumRepetitions ) + ) i_test ( + .end_of_sim_o ( end_of_sim ), + .clk_i ( clk ), + .rst_ni ( rst_n ), + .gpio_in_o ( gpio_in ), + .gpio_out_i ( gpio_out ), + .gpio_tx_en_i ( gpio_tx_en ), + .gpio_in_sync_i ( gpio_in_sync ), + .global_interrupt_i ( global_interrupt ), + .reg_bus ( s_reg_bus ) + ); +endmodule + + +program automatic test #( + parameter int unsigned NrGPIOs = 64, + localparam int unsigned NrGPIOs_rounded = ((NrGPIOs+32-1)/32)*32, + parameter DataWidth = 32, + parameter AddrWidth = 32, + parameter ApplTime, + parameter TestTime, + parameter int unsigned NumRepetitions +) ( + output logic end_of_sim_o, + input logic clk_i, + input logic rst_ni, + output logic [NrGPIOs-1:0] gpio_in_o, + input logic [NrGPIOs-1:0] gpio_out_i, + input logic [NrGPIOs-1:0] gpio_tx_en_i, // 0 -> input, 1 -> output + input logic [NrGPIOs-1:0] gpio_in_sync_i, // sampled and synchronized GPIO + // input. + input logic global_interrupt_i, + REG_BUS.out reg_bus +); + default clocking cb @(posedge clk_i); + endclocking + + import reg_test::reg_driver; + import gpio_reg_pkg::*; + + localparam type gpio_reg_driver_t = reg_driver #(.AW(AddrWidth), .DW(DataWidth), .TA(ApplTime), .TT(TestTime)); + gpio_reg_driver_t gpio_reg_driver; + // reg_driver #(.AW(AddrWidth), .DW(DataWidth), .TA(ApplTime), .TT(TestTime)) gpio_reg_driver; + + // Debug Signals + logic [NrGPIOs_rounded-1:0][1:0] gpio_modes; + logic [NrGPIOs_rounded-1:0] gpio_values; + int error_count = 0; + + task automatic test_toggle_set_clear(gpio_reg_driver_t gpio_reg_driver, int unsigned NumRepetitions); + logic [DataWidth-1:0] data = 0; + logic [AddrWidth-1:0] addr; + logic [DataWidth/8-1:0] strb = '1; + logic error = 0; + + $info("Verifying toggle, set and clear functionality of the outputs"); + for (int i = 0; i < (NrGPIOs+DataWidth-1)/DataWidth*2; i++) begin : cfg_gpio_modes +`ifdef ENABLE_LESS_THAN_16_GPIOS_REG_PKG_WORKAROUND + addr = GPIO_GPIO_MODE_OFFSET + i*4; +`else + addr = GPIO_GPIO_MODE_0_OFFSET + i*4; +`endif + data = {16{2'b01}}; // Put all gpios in push-pull mode + gpio_reg_driver.send_write(addr, data, strb, error); + assert(error == 0) else begin + $error("Interface write error while writing GPIO mode."); + error_count++; + end + end + + // Set random gpio out values + `SV_RAND_CHECK(randomize(gpio_values)); + for (int i = 0; i < (NrGPIOs+DataWidth-1)/DataWidth; i++) begin +`ifdef ENABLE_LESS_THAN_32_GPIOS_REG_PKG_WORKAROUND + addr = GPIO_GPIO_OUT_OFFSET + i*4; +`else + addr = GPIO_GPIO_OUT_0_OFFSET + i*4; +`endif + data = gpio_values[i*DataWidth+:DataWidth]; + gpio_reg_driver.send_write(addr, data, strb, error); + assert(error == 0) else begin + $error("Interface write error while writing GPIO out values."); + error_count++; + end + end + + assert (gpio_tx_en_i == '1) else begin + $error("GPIO TX driver not enabled although all GPIOs should be configured as outputs in push-pull mode."); + error_count++; + end + assert (gpio_out_i == gpio_values[NrGPIOs-1:0]) else begin + $error("Missmatch in GPIO outputs. Expected output pattern %0b but was %0b.", gpio_values, gpio_out_i); + error_count++; + end + + // Sequentially toggle, set and clear all GPIOs and verify only the ones set are modified + for (int i= 0; i < NrGPIOs; i++) begin + data = 1<<(i%32); + // Toggle the GPIO +`ifdef ENABLE_LESS_THAN_32_GPIOS_REG_PKG_WORKAROUND + addr = GPIO_GPIO_TOGGLE_OFFSET + i/32*4; +`else + addr = GPIO_GPIO_TOGGLE_0_OFFSET + i/32*4; +`endif + gpio_reg_driver.send_write(addr, data, strb, error); + for (int j = 0; j < NrGPIOs; j++) begin + if (i == j) begin + assert(gpio_out_i[j] == ~gpio_values[j]) else begin + $error("GPIO %0d has not toggled.", j); + error_count++; + end + end else begin + assert(gpio_out_i[j] == gpio_values[j]) else begin + $error("GPIO %0d was %0b instead of %0b although it should not have beend altered during modification of GPIO %0d.", j, gpio_out_i[j], gpio_values[j], i); + error_count++; + end + end + end + + + //Set the GPIO +`ifdef ENABLE_LESS_THAN_32_GPIOS_REG_PKG_WORKAROUND + addr = GPIO_GPIO_SET_OFFSET + i/32*4; +`else + addr = GPIO_GPIO_SET_0_OFFSET + i/32*4; +`endif + gpio_reg_driver.send_write(addr, data, strb, error); + for (int j = 0; j < NrGPIOs; j++) begin + if (i == j) begin + assert(gpio_out_i[j] == 1'b1) else begin + $error("GPIO %0d is not set.", j); + error_count++; + end + end else begin + assert(gpio_out_i[j] == gpio_values[j]) else begin + $error("GPIO %0d was %0b instead of %0b although it should not have beend altered during modification of GPIO %0d.", j, gpio_out_i[j], gpio_values[j], i); + error_count++; + end + end + end + + // Now clear the GPIO +`ifdef ENABLE_LESS_THAN_32_GPIOS_REG_PKG_WORKAROUND + addr = GPIO_GPIO_CLEAR_OFFSET + i/32*4; +`else + addr = GPIO_GPIO_CLEAR_0_OFFSET + i/32*4; +`endif + gpio_reg_driver.send_write(addr, data, strb, error); + for (int j = 0; j < NrGPIOs; j++) begin + if (i == j) begin + assert(gpio_out_i[j] == 1'b0) else begin + $error("GPIO %0d is not cleared.", j); + error_count++; + end + end else begin + assert(gpio_out_i[j] == gpio_values[j]) else begin + $error("GPIO %0d was %0b instead of %0b although it should not have beend altered during modification of GPIO %0d.", j, gpio_out_i[j], gpio_values[j], i); + error_count++; + end + end + end + gpio_values[i] = 1'b0; + end + + endtask + + task automatic test_inputs(gpio_reg_driver_t reg_driver, int unsigned NumRepetitions); + logic [DataWidth-1:0] data = 0; + logic [AddrWidth-1:0] addr; + logic [DataWidth/8-1:0] strb = '1; + logic error = 0; + logic [NrGPIOs_rounded-1:0] enabled_gpios; + logic [NrGPIOs-1:0] gpio_values; + logic [NrGPIOs-1:0] data_queue[$]; + + gpio_in_o = '0; + + $info("Test GPIOs in input mode with random data."); + for (int i = 0; i < (NrGPIOs+DataWidth-1)/DataWidth*2; i++) begin : cfg_gpio_modes +`ifdef ENABLE_LESS_THAN_16_GPIOS_REG_PKG_WORKAROUND + addr = GPIO_GPIO_MODE_OFFSET + i*4; +`else + addr = GPIO_GPIO_MODE_0_OFFSET + i*4; +`endif + data = {16{2'b00}}; // Put all gpios in input mode + gpio_reg_driver.send_write(addr, data, strb, error); + assert(error == 0) else begin + $error("Interface write error while writing GPIO mode."); + error_count++; + end + end + $info("Enabling input sampling on random GPIOs"); + `SV_RAND_CHECK(randomize(enabled_gpios)); + for (int i = 0; i < (NrGPIOs+DataWidth-1)/DataWidth; i++) begin : cfg_gpio_enable +`ifdef ENABLE_LESS_THAN_32_GPIOS_REG_PKG_WORKAROUND + addr = GPIO_GPIO_EN_OFFSET + i*4; +`else + addr = GPIO_GPIO_EN_0_OFFSET + i*4; +`endif + data = enabled_gpios[i*32+:32]; + gpio_reg_driver.send_write(addr, data, strb, error); + assert(error == 0) else begin + $error("Interface write error while writing GPIO mode."); + error_count++; + end + end + + $info("Apply and verify random inputs"); + for (int i = 0; i < NumRepetitions; i++) begin + `SV_RAND_CHECK(randomize(gpio_in_o)); + ##3; //Wait three cycles + #TestTime; + for (int i = 0; i < (NrGPIOs+DataWidth-1)/DataWidth; i++) begin +`ifdef ENABLE_LESS_THAN_32_GPIOS_REG_PKG_WORKAROUND + addr = GPIO_GPIO_IN_OFFSET + i*4; +`else + addr = GPIO_GPIO_IN_0_OFFSET + i*4; +`endif + gpio_reg_driver.send_read(addr, data, error); + assert(error == 0) else begin + $error("Interface write error while writing GPIO mode."); + error_count++; + end + for (int j = i*32; j < (i+1)*32; j++) begin + if (j < NrGPIOs && enabled_gpios[j]) begin + assert(gpio_in_o[j] == data[j%32]) else begin + $error("Got wrong gpio value for GPIO%0d. Was %0b instead of %0b", j, gpio_in_o[j], data[j%32]); + error_count++; + end + end + end + end + end + + $info("Test fast data sampling"); + for (int k = 0; k < NumRepetitions; k++) begin + `SV_RAND_CHECK(randomize(gpio_values)); + data_queue.push_back(gpio_values); + end + fork + begin + $info("Aplying inputs..."); + foreach(data_queue[i]) begin + #ApplTime; + gpio_in_o = data_queue[i]; + ##1; + end + end + begin + ##3; // Delay sampling by 3 cycles for + $info("Start reading sampled values on GPIO0..."); +`ifdef ENABLE_LESS_THAN_32_GPIOS_REG_PKG_WORKAROUND + addr = GPIO_GPIO_IN_OFFSET; +`else + addr = GPIO_GPIO_IN_0_OFFSET; +`endif + foreach(data_queue[i]) begin + gpio_reg_driver.send_read(addr, data, error); + for (int j = 0; j < NrGPIOs && j < 32; j++) begin + if (enabled_gpios[j]) + assert(data[j] == data_queue[i][j]) else begin + $error("On GPIO %0d. Was %0b instead of %0b.", j, data[j], data_queue[i][j]); + error_count++; + end + end + end + end + join + endtask + + typedef enum logic[2:0] {None, Rising, Falling, EitherEdge, Low, High} interrupt_mode_e; + interrupt_mode_e [NrGPIOs_rounded-1:0] interrupt_modes; + + task automatic test_interrupts(gpio_reg_driver_t gpio_reg_driver, int unsigned NumRepetitions); + logic [DataWidth-1:0] data = 0; + logic [AddrWidth-1:0] addr; + logic [DataWidth/8-1:0] strb = '1; + logic error = 0; + logic [NrGPIOs_rounded-1:0] enabled_gpios; + logic [NrGPIOs-1:0] gpio_values; + logic [NrGPIOs-1:0] toggle_mask; + logic [NrGPIOs_rounded-1:0] pending_intrpt, pending_rise_intrpt, pending_fall_intrpt, pending_low_intrpt, pending_high_intrpt; + logic clear_interrupt; + + + int unsigned delay; + + $info("Test GPIO interrupts."); + for (int i = 0; i < (NrGPIOs+DataWidth-1)/DataWidth*2; i++) begin : cfg_gpio_modes +`ifdef ENABLE_LESS_THAN_16_GPIOS_REG_PKG_WORKAROUND + addr = GPIO_GPIO_MODE_OFFSET + i*4; +`else + addr = GPIO_GPIO_MODE_0_OFFSET + i*4; +`endif + data = {16{2'b00}}; // Put all gpios in input mode + gpio_reg_driver.send_write(addr, data, strb, error); + assert(error == 0) else begin + $error("Interface write error while writing GPIO mode."); + error_count++; + end + end + $info("Enabling input sampling on all GPIOs"); + `SV_RAND_CHECK(randomize(enabled_gpios)); + for (int i = 0; i < (NrGPIOs+DataWidth-1)/DataWidth; i++) begin : cfg_gpio_enable +`ifdef ENABLE_LESS_THAN_32_GPIOS_REG_PKG_WORKAROUND + addr = GPIO_GPIO_EN_OFFSET + i*4; +`else + addr = GPIO_GPIO_EN_0_OFFSET + i*4; +`endif + data = '1; + gpio_reg_driver.send_write(addr, data, strb, error); + assert(error == 0) else begin + $error("Interface write error while writing GPIO mode."); + error_count++; + end + end + + $info("Put GPIOs into random interrupt modes..."); + // We randomize the modes such that there are not to many enabled + // interrupts. Otherwise the global_interrupt line will probably stay high all the + // time due to the level sensitive interrupts. + std::randomize(interrupt_modes) with { + foreach (interrupt_modes[i]) { + interrupt_modes[i] dist { + None := 20, + Rising := 2, + Falling := 2, + EitherEdge := 1, + Low := 1, + High := 1 + }; + } + }; + // Before enabling level low sensitive interrupts, put gpio inputs in a state + // that doesn't immediately trigger them. + foreach(gpio_in_o[i]) begin + gpio_in_o[i] = interrupt_modes[i] == Low; + end + ##3; + + for (int i = 0; i < (NrGPIOs+DataWidth-1)/DataWidth; i++) begin : cfg_gpio_enable + // Enable rising edge interrupts +`ifdef ENABLE_LESS_THAN_32_GPIOS_REG_PKG_WORKAROUND + addr = GPIO_INTRPT_RISE_EN_OFFSET + i*4; +`else + addr = GPIO_INTRPT_RISE_EN_0_OFFSET + i*4; +`endif + foreach(data[j]) begin + data[j] = interrupt_modes[i*32+j] == Rising || interrupt_modes[i*32+j] == EitherEdge; + end + gpio_reg_driver.send_write(addr, data, strb, error); + // Enable falling edge interrupts +`ifdef ENABLE_LESS_THAN_32_GPIOS_REG_PKG_WORKAROUND + addr = GPIO_INTRPT_FALL_EN_OFFSET + i*4; +`else + addr = GPIO_INTRPT_FALL_EN_0_OFFSET + i*4; +`endif + foreach(data[j]) begin + data[j] = interrupt_modes[i*32+j] == Falling || interrupt_modes[i*32+j] == EitherEdge; + end + gpio_reg_driver.send_write(addr, data, strb, error); + + // Enable low level-sensitive interrupts + foreach(data[j]) begin + data[j] = interrupt_modes[i*32+j] == Low; + end +`ifdef ENABLE_LESS_THAN_32_GPIOS_REG_PKG_WORKAROUND + addr = GPIO_INTRPT_LVL_LOW_EN_OFFSET + i*4; +`else + addr = GPIO_INTRPT_LVL_LOW_EN_0_OFFSET + i*4; +`endif + gpio_reg_driver.send_write(addr, data, strb, error); + // Enable high level-sensitive interrupts +`ifdef ENABLE_LESS_THAN_32_GPIOS_REG_PKG_WORKAROUND + addr = GPIO_INTRPT_LVL_HIGH_EN_OFFSET + i*4; +`else + addr = GPIO_INTRPT_LVL_HIGH_EN_0_OFFSET + i*4; +`endif + foreach(data[j]) begin + data[j] = interrupt_modes[i*32+j] == High; + end + gpio_reg_driver.send_write(addr, data, strb, error); + assert(error == 0) else begin + $error("Interface write error while writing GPIO mode."); + error_count++; + end + end + ##10; + + $info("Inserting random interrupts..."); + pending_rise_intrpt = '0; + pending_fall_intrpt = '0; + pending_high_intrpt = '0; + pending_low_intrpt = '0; + for (int i = 0; i < NumRepetitions; i++) begin + ## 1; + // Toggle some random GPIOs + `SV_RAND_CHECK(randomize(toggle_mask) with { + $countones(toggle_mask) < 3; + }); + $info("Toggling GPIOs..."); + gpio_in_o ^= toggle_mask; + #ApplTime; + //Check which interrups this change should trigger... + foreach(toggle_mask[j]) begin + case (interrupt_modes[j]) + Falling: begin + if (gpio_in_o[j] == 1'b0 && toggle_mask[j]) + pending_fall_intrpt[j] = 1'b1; + end + + Rising: begin + if (gpio_in_o[j] == 1'b1 && toggle_mask[j]) + pending_rise_intrpt[j] = 1'b1; + end + + EitherEdge: begin + if (toggle_mask[j]) begin + if (gpio_in_o[j] == 1'b1) + pending_rise_intrpt[j] = 1'b1; + else + pending_fall_intrpt[j] = 1'b1; + end + end + + Low: begin + if (gpio_in_o[j] == 1'b0) + pending_low_intrpt[j] = 1'b1; + end + + High: begin + if (gpio_in_o[j] == 1'b1) + pending_high_intrpt[j] = 1'b1; + end + endcase + end + $info("Checking global_interrupt status regs..."); + pending_intrpt = pending_high_intrpt | pending_low_intrpt | pending_rise_intrpt | pending_fall_intrpt; + if (pending_intrpt) begin + if (pending_rise_intrpt | pending_fall_intrpt) begin + // Wait 2 cycles (rising and falling edge interrupts arrive 1 cycle + // earlier than level sensitive interrupts) + ##2; + end else begin + ##3; + end + + #TestTime; + assert(global_interrupt_i == 1'b1) else begin + $error("Interrupt was not asserted."); + error_count++; + end + ##2; // Wait another 2 cycles for the global_interrupt status register to be + // updated + //Read global_interrupt status registers + for (int i = 0; i < (NrGPIOs+DataWidth-1)/DataWidth; i++) begin +`ifdef ENABLE_LESS_THAN_32_GPIOS_REG_PKG_WORKAROUND + addr = GPIO_INTRPT_STATUS_OFFSET + i*4; +`else + addr = GPIO_INTRPT_STATUS_0_OFFSET + i*4; +`endif + gpio_reg_driver.send_read(addr, data, error); + assert(data == pending_intrpt[i*32+:32]) else begin + $error("Interrupt status missmatch. Was %0x instead of %0x", data, pending_intrpt[i*32+:32]); + error_count++; + end +`ifdef ENABLE_LESS_THAN_32_GPIOS_REG_PKG_WORKAROUND + addr = GPIO_INTRPT_RISE_STATUS_OFFSET + i*4; +`else + addr = GPIO_INTRPT_RISE_STATUS_0_OFFSET + i*4; +`endif + gpio_reg_driver.send_read(addr, data, error); + assert(data == pending_rise_intrpt[i*32+:32]) else begin + $error("Interrupt rise status missmatch. Was %0x instead of %0x", data, pending_rise_intrpt[i*32+:32]); + error_count++; + end +`ifdef ENABLE_LESS_THAN_32_GPIOS_REG_PKG_WORKAROUND + addr = GPIO_INTRPT_FALL_STATUS_OFFSET + i*4; +`else + addr = GPIO_INTRPT_FALL_STATUS_0_OFFSET + i*4; +`endif + gpio_reg_driver.send_read(addr, data, error); + assert(data == pending_fall_intrpt[i*32+:32]) else begin + $error("Interrupt fall status missmatch. Was %0x instead of %0x", data, pending_fall_intrpt[i*32+:32]); + error_count++; + end +`ifdef ENABLE_LESS_THAN_32_GPIOS_REG_PKG_WORKAROUND + addr = GPIO_INTRPT_LVL_LOW_STATUS_OFFSET + i*4; +`else + addr = GPIO_INTRPT_LVL_LOW_STATUS_0_OFFSET + i*4; +`endif + gpio_reg_driver.send_read(addr, data, error); + assert(data == pending_low_intrpt[i*32+:32]) else begin + $error("Interrupt low status missmatch. Was %0x instead of %0x", data, pending_low_intrpt[i*32+:32]); + error_count++; + end +`ifdef ENABLE_LESS_THAN_32_GPIOS_REG_PKG_WORKAROUND + addr = GPIO_INTRPT_LVL_HIGH_STATUS_OFFSET + i*4; +`else + addr = GPIO_INTRPT_LVL_HIGH_STATUS_0_OFFSET + i*4; +`endif + gpio_reg_driver.send_read(addr, data, error); + assert(data == pending_high_intrpt[i*32+:32]) else begin + $error("Interrupt high status missmatch. Was %0x instead of %0x", data, pending_high_intrpt[i*32+:32]); + error_count++; + end + end + + //Now clear some of the pending interrupts + $info("Start global_interrupt clearing..."); + foreach(pending_intrpt[j]) begin + if (pending_intrpt[j]) begin + randcase + 2: begin + $info("Clearing all interrupts on GPIO %0d.", j); +`ifdef ENABLE_LESS_THAN_32_GPIOS_REG_PKG_WORKAROUND + addr = GPIO_INTRPT_STATUS_OFFSET + j/32*4; +`else + addr = GPIO_INTRPT_STATUS_0_OFFSET + j/32*4; +`endif + data = 1<}}). +To ensure things stay up to date, the register JSON format information +is documented by the tool itself. +The documentation can be generated by running the following commands: + +```console +$ cd $REPO_TOP/util +$ ./build_docs.py +``` +Under the hood, the `build_docs.py` tool will automatically use the `reggen` +tool to produce Markdown and processing that into HTML. + +### Examples using standalone regtool + +Normally for documentation the `build_docs.py` tool will automatically +use `reggen`. The script `regtool.py` provides a standalone way to run +`reggen`. See the +[register tool documentation]({{< relref "doc/rm/register_tool/index.md" >}}) +for details about how to invoke the tool. + +The following shows an example of how to generate RTL from a register +description: + +```console +$ cd $REPO_TOP/util +$ mkdir /tmp/rtl +$ ./regtool.py -r -t /tmp/rtl ../hw/ip/uart/data/uart.hjson +$ ls /tmp/rtl + uart_reg_pkg.sv uart_reg_top.sv +``` + +The following shows an example of how to generate a DV UVM class from +a register description: + +```console +$ cd $REPO_TOP/util +$ mkdir /tmp/dv +$ ./regtool.py -s -t /tmp/dv ../hw/ip/uart/data/uart.hjson +$ ls /tmp/dv + uart_ral_pkg.sv +``` + +By default, the generated block, register and field models are derived from +`dv_base_reg` classes provided at `hw/dv/sv/dv_base_reg`. If required, the user +can supply the `--dv-base-prefix my_base` switch to have the models derive from +a custom, user-defined RAL classes instead: + +```console +$ cd $REPO_TOP/util +$ mkdir /tmp/dv +$ ./regtool.py -s -t /tmp/dv ../hw/ip/uart/data/uart.hjson \ + --dv-base-prefix my_base +$ ls /tmp/dv + uart_ral_pkg.sv +``` + +This makes the following assumptions: +- A FuseSoC core file aggregating the `my_base` RAL classes with the VLNV + name `lowrisc:dv:my_base_reg` is provided in the cores search path. +- These custom classes are derived from the corresponding `dv_base_reg` classes + and have the following names: + - `my_base_reg_pkg.sv`: The RAL package that includes the below sources + - `my_base_reg_block.sv`: The register block abstraction + - `my_base_reg.sv`: The register abstraction + - `my_base_reg_field.sv`: The register field abstraction + - `my_base_mem.sv`: The memory abstraction +- If any of the above class specializations is not needed, it can be + `typedef`'ed in `my_base_reg_pkg`: + ```systemverilog + package my_base_reg_pkg; + import dv_base_reg_pkg::*; + typedef dv_base_reg_field my_base_reg_field; + typedef dv_base_mem my_base_mem; + `include "my_base_reg.sv" + `include "my_base_reg_block.sv" + endpackage + ``` + +The following shows an example of how to generate a FPV csr read write assertion +module from a register description: + +```console +$ cd $REPO_TOP/util +$ mkdir /tmp/fpv/vip +$ ./regtool.py -f -t /tmp/fpv/vip ../hw/ip/uart/data/uart.hjson +$ ls /tmp/fpv + uart_csr_assert_fpv.sv +``` + +If the target directory is not specified, the tool creates the DV file +under the `hw/ip/{module}/dv/` directory. diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/__init__.py b/hw/vendored_ips/gpio/util/reggen/reggen/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/access.py b/hw/vendored_ips/gpio/util/reggen/reggen/access.py new file mode 100644 index 00000000..286fc87b --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/access.py @@ -0,0 +1,121 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +"""Enumerated types for fields +Generated by validation, used by backends +""" + +from enum import Enum + +from .lib import check_str + + +class JsonEnum(Enum): + def for_json(x) -> str: + return str(x) + + +class SwWrAccess(JsonEnum): + WR = 1 + NONE = 2 + + +class SwRdAccess(JsonEnum): + RD = 1 + RC = 2 # Special handling for port + NONE = 3 + + +class SwAccess(JsonEnum): + RO = 1 + RW = 2 + WO = 3 + W1C = 4 + W1S = 5 + W0C = 6 + RC = 7 + R0W1C = 8 + NONE = 9 + + +class HwAccess(JsonEnum): + HRO = 1 + HRW = 2 + HWO = 3 + NONE = 4 # No access allowed + + +# swaccess permitted values +# text description, access enum, wr access enum, rd access enum, ok in window +SWACCESS_PERMITTED = { + 'none': ("No access", # noqa: E241 + SwAccess.NONE, SwWrAccess.NONE, SwRdAccess.NONE, False), # noqa: E241 + 'ro': ("Read Only", # noqa: E241 + SwAccess.RO, SwWrAccess.NONE, SwRdAccess.RD, True), # noqa: E241 + 'rc': ("Read Only, reading clears", # noqa: E241 + SwAccess.RC, SwWrAccess.WR, SwRdAccess.RC, False), # noqa: E241 + 'rw': ("Read/Write", # noqa: E241 + SwAccess.RW, SwWrAccess.WR, SwRdAccess.RD, True), # noqa: E241 + 'r0w1c': ("Read zero, Write with 1 clears", # noqa: E241 + SwAccess.W1C, SwWrAccess.WR, SwRdAccess.NONE, False), # noqa: E241 + 'rw1s': ("Read, Write with 1 sets", # noqa: E241 + SwAccess.W1S, SwWrAccess.WR, SwRdAccess.RD, False), # noqa: E241 + 'rw1c': ("Read, Write with 1 clears", # noqa: E241 + SwAccess.W1C, SwWrAccess.WR, SwRdAccess.RD, False), # noqa: E241 + 'rw0c': ("Read, Write with 0 clears", # noqa: E241 + SwAccess.W0C, SwWrAccess.WR, SwRdAccess.RD, False), # noqa: E241 + 'wo': ("Write Only", # noqa: E241 + SwAccess.WO, SwWrAccess.WR, SwRdAccess.NONE, True) # noqa: E241 +} + +# hwaccess permitted values +HWACCESS_PERMITTED = { + 'hro': ("Read Only", HwAccess.HRO), + 'hrw': ("Read/Write", HwAccess.HRW), + 'hwo': ("Write Only", HwAccess.HWO), + 'none': ("No Access Needed", HwAccess.NONE) +} + + +class SWAccess: + def __init__(self, where: str, raw: object): + self.key = check_str(raw, 'swaccess for {}'.format(where)) + try: + self.value = SWACCESS_PERMITTED[self.key] + except KeyError: + raise ValueError('Unknown swaccess key, {}, for {}.' + .format(self.key, where)) from None + + def dv_rights(self) -> str: + if self.key in ['none', 'ro', 'rc']: + return "RO" + elif self.key in ['rw', 'r0w1c', 'rw1s', 'rw1c', 'rw0c']: + return "RW" + else: + assert self.key == 'wo' + return "WO" + + def swrd(self) -> SwRdAccess: + return self.value[3] + + def allows_read(self) -> bool: + return self.value[3] != SwRdAccess.NONE + + def allows_write(self) -> bool: + return self.value[2] == SwWrAccess.WR + + +class HWAccess: + def __init__(self, where: str, raw: object): + self.key = check_str(raw, 'hwaccess for {}'.format(where)) + try: + self.value = HWACCESS_PERMITTED[self.key] + except KeyError: + raise ValueError('Unknown hwaccess key, {}, for {}.' + .format(self.key, where)) from None + + def allows_read(self) -> bool: + return self.key in ['hro', 'hrw'] + + def allows_write(self) -> bool: + return self.key in ['hrw', 'hwo'] diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/alert.py b/hw/vendored_ips/gpio/util/reggen/reggen/alert.py new file mode 100644 index 00000000..a23ff491 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/alert.py @@ -0,0 +1,54 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +from typing import Dict, List + +from .bits import Bits +from .signal import Signal +from .lib import check_keys, check_name, check_str, check_list + + +class Alert(Signal): + def __init__(self, name: str, desc: str, bit: int, fatal: bool): + super().__init__(name, desc, Bits(bit, bit)) + self.bit = bit + self.fatal = fatal + + @staticmethod + def from_raw(what: str, + lsb: int, + raw: object) -> 'Alert': + rd = check_keys(raw, what, ['name', 'desc'], []) + + name = check_name(rd['name'], 'name field of ' + what) + desc = check_str(rd['desc'], 'desc field of ' + what) + + # Make sense of the alert name, which should be prefixed with recov_ or + # fatal_. + pfx = name.split('_')[0] + if pfx == 'recov': + fatal = False + elif pfx == 'fatal': + fatal = True + else: + raise ValueError('Invalid name field of {}: alert names must be ' + 'prefixed with "recov_" or "fatal_". Saw {!r}.' + .format(what, name)) + + return Alert(name, desc, lsb, fatal) + + @staticmethod + def from_raw_list(what: str, raw: object) -> List['Alert']: + ret = [] + for idx, entry in enumerate(check_list(raw, what)): + entry_what = 'entry {} of {}'.format(idx, what) + alert = Alert.from_raw(entry_what, idx, entry) + ret.append(alert) + return ret + + def _asdict(self) -> Dict[str, object]: + return { + 'name': self.name, + 'desc': self.desc, + } diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/bits.py b/hw/vendored_ips/gpio/util/reggen/reggen/bits.py new file mode 100644 index 00000000..c8d48f70 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/bits.py @@ -0,0 +1,87 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +'''Support code for bit ranges in reggen''' + +from typing import Tuple + +from .lib import check_str +from .params import ReggenParams + + +class Bits: + def __init__(self, msb: int, lsb: int): + assert 0 <= lsb <= msb + self.msb = msb + self.lsb = lsb + + def bitmask(self) -> int: + return (1 << (self.msb + 1)) - (1 << self.lsb) + + def width(self) -> int: + return 1 + self.msb - self.lsb + + def max_value(self) -> int: + return (1 << self.width()) - 1 + + def extract_field(self, reg_val: int) -> int: + return (reg_val & self.bitmask()) >> self.lsb + + @staticmethod + def from_raw(where: str, + reg_width: int, + params: ReggenParams, + raw: object) -> 'Bits': + # Bits should be specified as msb:lsb or as just a single bit index. + if isinstance(raw, int): + msb = raw + lsb = raw + else: + str_val = check_str(raw, 'bits field for {}'.format(where)) + msb, lsb = Bits._parse_str(where, params, str_val) + + # Check that the bit indices look sensible + if msb < lsb: + raise ValueError('msb for {} is {}: less than {}, the msb.' + .format(where, msb, lsb)) + if lsb < 0: + raise ValueError('lsb for {} is {}, which is negative.' + .format(where, lsb)) + if msb >= reg_width: + raise ValueError("msb for {} is {}, which doesn't fit in {} bits." + .format(where, msb, reg_width)) + + return Bits(msb, lsb) + + @staticmethod + def _parse_str(where: str, + params: ReggenParams, + str_val: str) -> Tuple[int, int]: + try: + idx = int(str_val) + return (idx, idx) + except ValueError: + # Doesn't look like an integer. Never mind: try msb:lsb + pass + + parts = str_val.split(':') + if len(parts) != 2: + raise ValueError('bits field for {} is not an ' + 'integer or of the form msb:lsb. Saw {!r}.' + .format(where, str_val)) + return (params.expand(parts[0], + 'msb of bits field for {}'.format(where)), + params.expand(parts[1], + 'lsb of bits field for {}'.format(where))) + + def make_translated(self, bit_offset: int) -> 'Bits': + assert 0 <= bit_offset + return Bits(self.msb + bit_offset, self.lsb + bit_offset) + + def as_str(self) -> str: + if self.lsb == self.msb: + return str(self.lsb) + else: + assert self.lsb < self.msb + return '{}:{}'.format(self.msb, self.lsb) diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/bus_interfaces.py b/hw/vendored_ips/gpio/util/reggen/reggen/bus_interfaces.py new file mode 100644 index 00000000..37c5818e --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/bus_interfaces.py @@ -0,0 +1,187 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +'''Code representing a list of bus interfaces for a block''' +from enum import Enum +from typing import Dict, List, Optional, Tuple + +from .inter_signal import InterSignal +from .lib import check_list, check_keys, check_str, check_optional_str + +class BusProtocol(Enum): + TLUL = "tlul" + REG_IFACE = "reg_iface" + + @classmethod + def has_value(cls, v): + return v in cls._value2member_map_ + + +class BusInterfaces: + def __init__(self, + has_unnamed_host: bool, + named_hosts: List[str], + has_unnamed_device: bool, + named_devices: List[str], + interface_list: List[Dict]): + assert has_unnamed_device or named_devices + assert len(named_hosts) == len(set(named_hosts)) + assert len(named_devices) == len(set(named_devices)) + + self.has_unnamed_host = has_unnamed_host + self.named_hosts = named_hosts + self.has_unnamed_device = has_unnamed_device + self.named_devices = named_devices + self.interface_list = interface_list + + @staticmethod + def from_raw(raw: object, where: str) -> 'BusInterfaces': + has_unnamed_host = False + named_hosts = [] + interface_list = [] + + has_unnamed_device = False + named_devices = [] + + for idx, raw_entry in enumerate(check_list(raw, where)): + entry_what = 'entry {} of {}'.format(idx + 1, where) + ed = check_keys(raw_entry, entry_what, + ['protocol', 'direction'], + ['name']) + + protocol = check_str(ed['protocol'], + 'protocol field of ' + entry_what) + if not BusProtocol.has_value(protocol): + raise ValueError('Unknown protocol {!r} at {}' + .format(protocol, entry_what)) + + direction = check_str(ed['direction'], + 'direction field of ' + entry_what) + if direction not in ['device', 'host']: + raise ValueError('Unknown interface direction {!r} at {}' + .format(direction, entry_what)) + + name = check_optional_str(ed.get('name'), + 'name field of ' + entry_what) + + if direction == 'host': + if name is None: + if has_unnamed_host: + raise ValueError('Multiple un-named host ' + 'interfaces at {}' + .format(where)) + has_unnamed_host = True + else: + if name in named_hosts: + raise ValueError('Duplicate host interface ' + 'with name {!r} at {}' + .format(name, where)) + named_hosts.append(name) + else: + if name is None: + if has_unnamed_device: + raise ValueError('Multiple un-named device ' + 'interfaces at {}' + .format(where)) + has_unnamed_device = True + else: + if name in named_devices: + raise ValueError('Duplicate device interface ' + 'with name {!r} at {}' + .format(name, where)) + named_devices.append(name) + interface_list.append({'name': name, 'protocol': BusProtocol(protocol), 'is_host': direction=='host'}) + + if not (has_unnamed_device or named_devices): + raise ValueError('No device interface at ' + where) + + return BusInterfaces(has_unnamed_host, named_hosts, + has_unnamed_device, named_devices, interface_list) + + def has_host(self) -> bool: + return bool(self.has_unnamed_host or self.named_hosts) + + def _interfaces(self) -> List[Tuple[bool, Optional[str]]]: + ret = [] # type: List[Tuple[bool, Optional[str]]] + if self.has_unnamed_host: + ret.append((True, None)) + for name in self.named_hosts: + ret.append((True, name)) + + if self.has_unnamed_device: + ret.append((False, None)) + for name in self.named_devices: + ret.append((False, name)) + + return ret + + @staticmethod + def _if_dict(is_host: bool, name: Optional[str]) -> Dict[str, object]: + ret = { + 'protocol': 'tlul', + 'direction': 'host' if is_host else 'device' + } # type: Dict[str, object] + + if name is not None: + ret['name'] = name + + return ret + + def as_dicts(self) -> List[Dict[str, object]]: + return [BusInterfaces._if_dict(is_host, name) + for is_host, name in self._interfaces()] + + def get_port_name(self, is_host: bool, name: Optional[str]) -> str: + if is_host: + tl_suffix = 'tl_h' + else: + tl_suffix = 'tl_d' if self.has_host() else 'tl' + + return (tl_suffix if name is None + else '{}_{}'.format(name, tl_suffix)) + + def get_port_names(self, inc_hosts: bool, inc_devices: bool) -> List[str]: + ret = [] + for is_host, name in self._interfaces(): + if not (inc_hosts if is_host else inc_devices): + continue + ret.append(self.get_port_name(is_host, name)) + return ret + + def _if_inter_signal(self, + is_host: bool, + name: Optional[str]) -> InterSignal: + return InterSignal(self.get_port_name(is_host, name), + None, 'tl', 'tlul_pkg', 'req_rsp', 'rsp', 1, None) + + def inter_signals(self) -> List[InterSignal]: + return [self._if_inter_signal(is_host, name) + for is_host, name in self._interfaces()] + + def has_interface(self, is_host: bool, name: Optional[str]) -> bool: + if is_host: + if name is None: + return self.has_unnamed_host + else: + return name in self.named_hosts + else: + if name is None: + return self.has_unnamed_device + else: + return name in self.named_devices + + def find_port_name(self, is_host: bool, name: Optional[str]) -> str: + '''Look up the given host/name pair and return its port name. + + Raises a KeyError if there is no match. + + ''' + if not self.has_interface(is_host, name): + called = ('with no name' + if name is None else 'called {!r}'.format(name)) + raise KeyError('There is no {} bus interface {}.' + .format('host' if is_host else 'device', + called)) + + return self.get_port_name(is_host, name) diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/enum_entry.py b/hw/vendored_ips/gpio/util/reggen/reggen/enum_entry.py new file mode 100644 index 00000000..fe1e9ecd --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/enum_entry.py @@ -0,0 +1,35 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +from typing import Dict + +from .lib import check_keys, check_str, check_int + +REQUIRED_FIELDS = { + 'name': ['s', "name of the member of the enum"], + 'desc': ['t', "description when field has this value"], + 'value': ['d', "value of this member of the enum"] +} + + +class EnumEntry: + def __init__(self, where: str, max_val: int, raw: object): + rd = check_keys(raw, where, + list(REQUIRED_FIELDS.keys()), + []) + + self.name = check_str(rd['name'], 'name field of {}'.format(where)) + self.desc = check_str(rd['desc'], 'desc field of {}'.format(where)) + self.value = check_int(rd['value'], 'value field of {}'.format(where)) + if not (0 <= self.value <= max_val): + raise ValueError("value for {} is {}, which isn't representable " + "in the field (representable range: 0 .. {})." + .format(where, self.value, max_val)) + + def _asdict(self) -> Dict[str, object]: + return { + 'name': self.name, + 'desc': self.desc, + 'value': str(self.value) + } diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/field.py b/hw/vendored_ips/gpio/util/reggen/reggen/field.py new file mode 100644 index 00000000..a2beb735 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/field.py @@ -0,0 +1,291 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +from typing import Dict, List, Optional + +from .access import SWAccess, HWAccess +from .bits import Bits +from .enum_entry import EnumEntry +from .lib import (check_keys, check_str, check_name, + check_list, check_str_list, check_xint) +from .params import ReggenParams + +REQUIRED_FIELDS = { + 'bits': ['b', "bit or bit range (msb:lsb)"] +} + +OPTIONAL_FIELDS = { + 'name': ['s', "name of the field"], + 'desc': ['t', "description of field (required if the field has a name)"], + 'swaccess': [ + 's', "software access permission, copied from " + "register if not provided in field. " + "(Tool adds if not provided.)" + ], + 'hwaccess': [ + 's', "hardware access permission, copied from " + "register if not prvided in field. " + "(Tool adds if not provided.)" + ], + 'resval': [ + 'x', "reset value, comes from register resval " + "if not provided in field. Zero if neither " + "are provided and the field is readable, " + "x if neither are provided and the field " + "is wo. Must match if both are provided." + ], + 'enum': ['l', "list of permitted enumeration groups"], + 'tags': [ + 's', + "tags for the field, followed by the format 'tag_name:item1:item2...'" + ] +} + + +class Field: + def __init__(self, + name: str, + desc: Optional[str], + tags: List[str], + swaccess: SWAccess, + hwaccess: HWAccess, + hwqe: bool, + hwre: bool, + bits: Bits, + resval: Optional[int], + enum: Optional[List[EnumEntry]]): + self.name = name + self.desc = desc + self.tags = tags + self.swaccess = swaccess + self.hwaccess = hwaccess + self.hwqe = hwqe + self.hwre = hwre + self.bits = bits + self.resval = resval + self.enum = enum + + @staticmethod + def from_raw(reg_name: str, + field_idx: int, + num_fields: int, + default_swaccess: SWAccess, + default_hwaccess: HWAccess, + reg_resval: Optional[int], + reg_width: int, + reg_hwqe: bool, + reg_hwre: bool, + params: ReggenParams, + raw: object) -> 'Field': + where = 'field {} of {} register'.format(field_idx, reg_name) + rd = check_keys(raw, where, + list(REQUIRED_FIELDS.keys()), + list(OPTIONAL_FIELDS.keys())) + + raw_name = rd.get('name') + if raw_name is None: + name = ('field{}'.format(field_idx + 1) + if num_fields > 1 else reg_name) + else: + name = check_name(raw_name, 'name of {}'.format(where)) + + raw_desc = rd.get('desc') + if raw_desc is None and raw_name is not None: + raise ValueError('Missing desc field for {}' + .format(where)) + if raw_desc is None: + desc = None + else: + desc = check_str(raw_desc, 'desc field for {}'.format(where)) + + tags = check_str_list(rd.get('tags', []), + 'tags for {}'.format(where)) + + raw_swaccess = rd.get('swaccess') + if raw_swaccess is not None: + swaccess = SWAccess(where, raw_swaccess) + else: + swaccess = default_swaccess + + raw_hwaccess = rd.get('hwaccess') + if raw_hwaccess is not None: + hwaccess = HWAccess(where, raw_hwaccess) + else: + hwaccess = default_hwaccess + + bits = Bits.from_raw(where, reg_width, params, rd['bits']) + + raw_resval = rd.get('resval') + if raw_resval is None: + # The field doesn't define a reset value. Use bits from reg_resval + # if it's defined, otherwise None (which means "x"). + if reg_resval is None: + resval = None + else: + resval = bits.extract_field(reg_resval) + else: + # The field does define a reset value. It should be an integer or + # 'x'. In the latter case, we set resval to None (as above). + resval = check_xint(raw_resval, 'resval field for {}'.format(where)) + if resval is None: + # We don't allow a field to be explicitly 'x' on reset but for + # the containing register to have a reset value. + if reg_resval is not None: + raise ValueError('resval field for {} is "x", but the ' + 'register defines a resval as well.' + .format(where)) + else: + # Check that the reset value is representable with bits + if not (0 <= resval <= bits.max_value()): + raise ValueError("resval field for {} is {}, which " + "isn't representable as an unsigned " + "{}-bit integer." + .format(where, resval, bits.width())) + + # If the register had a resval, check this value matches it. + if reg_resval is not None: + resval_from_reg = bits.extract_field(reg_resval) + if resval != resval_from_reg: + raise ValueError('resval field for {} is {}, but the ' + 'register defines a resval as well, ' + 'where bits {}:{} would give {}.' + .format(where, resval, + bits.msb, bits.lsb, + resval_from_reg)) + + raw_enum = rd.get('enum') + if raw_enum is None: + enum = None + else: + enum = [] + raw_entries = check_list(raw_enum, + 'enum field for {}'.format(where)) + enum_val_to_name = {} # type: Dict[int, str] + for idx, raw_entry in enumerate(raw_entries): + entry = EnumEntry('entry {} in enum list for {}' + .format(idx + 1, where), + bits.max_value(), + raw_entry) + if entry.value in enum_val_to_name: + raise ValueError('In {}, duplicate enum entries for ' + 'value {} ({} and {}).' + .format(where, + entry.value, + enum_val_to_name[entry.value], + entry.name)) + enum.append(entry) + enum_val_to_name[entry.value] = entry.name + + return Field(name, desc, tags, + swaccess, hwaccess, + reg_hwqe, reg_hwre, bits, resval, enum) + + def has_incomplete_enum(self) -> bool: + return (self.enum is not None and + len(self.enum) != 1 + self.bits.max_value()) + + def get_n_bits(self, hwext: bool, bittype: List[str]) -> int: + '''Get the size of this field in bits + + bittype should be a list of the types of signals to count. The elements + should come from the following list: + + - 'q': A signal for the value of the field. Only needed if HW can read + its contents. + + - 'd': A signal for the next value of the field. Only needed if HW can + write its contents. + + - 'qe': A write enable signal for bus accesses. Only needed if HW can + read the field's contents and the field has the hwqe flag. + + - 're': A read enable signal for bus accesses. Only needed if HW can + read the field's contents and the field has the hwre flag. + + - 'de': A write enable signal for hardware accesses. Only needed if HW + can write the field's contents and the register data is stored in the + register block (true if the hwext flag is false). + + ''' + n_bits = 0 + if "q" in bittype and self.hwaccess.allows_read(): + n_bits += self.bits.width() + if "d" in bittype and self.hwaccess.allows_write(): + n_bits += self.bits.width() + if "qe" in bittype and self.hwaccess.allows_read(): + n_bits += int(self.hwqe) + if "re" in bittype and self.hwaccess.allows_read(): + n_bits += int(self.hwre) + if "de" in bittype and self.hwaccess.allows_write(): + n_bits += int(not hwext) + return n_bits + + def make_multi(self, + reg_width: int, + min_reg_idx: int, + max_reg_idx: int, + cname: str, + creg_idx: int, + stripped: bool) -> List['Field']: + assert 0 <= min_reg_idx <= max_reg_idx + + # Check that we won't overflow reg_width. We assume that the LSB should + # be preserved: if msb=5, lsb=2 then the replicated copies will be + # [5:2], [11:8] etc. + num_copies = 1 + max_reg_idx - min_reg_idx + field_width = self.bits.msb + 1 + + if field_width * num_copies > reg_width: + raise ValueError('Cannot replicate field {} {} times: the ' + 'resulting width would be {}, but the register ' + 'width is just {}.' + .format(self.name, num_copies, + field_width * num_copies, reg_width)) + + desc = ('For {}{}'.format(cname, creg_idx) + if stripped else self.desc) + enum = None if stripped else self.enum + + ret = [] + for reg_idx in range(min_reg_idx, max_reg_idx + 1): + name = '{}_{}'.format(self.name, reg_idx) + + bit_offset = field_width * (reg_idx - min_reg_idx) + bits = (self.bits + if bit_offset == 0 + else self.bits.make_translated(bit_offset)) + + ret.append(Field(name, desc, + self.tags, self.swaccess, self.hwaccess, + self.hwqe, self.hwre, bits, self.resval, enum)) + + return ret + + def make_suffixed(self, suffix: str, + cname: str, + creg_idx: int, + stripped: bool) -> 'Field': + desc = ('For {}{}'.format(cname, creg_idx) + if stripped else self.desc) + enum = None if stripped else self.enum + + return Field(self.name + suffix, + desc, self.tags, self.swaccess, self.hwaccess, + self.hwqe, self.hwre, self.bits, self.resval, enum) + + def _asdict(self) -> Dict[str, object]: + rd = { + 'bits': self.bits.as_str(), + 'name': self.name, + 'swaccess': self.swaccess.key, + 'hwaccess': self.hwaccess.key, + 'resval': 'x' if self.resval is None else str(self.resval), + 'tags': self.tags + } # type: Dict[str, object] + + if self.desc is not None: + rd['desc'] = self.desc + if self.enum is not None: + rd['enum'] = self.enum + return rd diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/fpv_csr.sv.tpl b/hw/vendored_ips/gpio/util/reggen/reggen/fpv_csr.sv.tpl new file mode 100644 index 00000000..01f20c73 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/fpv_csr.sv.tpl @@ -0,0 +1,177 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// FPV CSR read and write assertions auto-generated by `reggen` containing data structure +// Do Not Edit directly +// TODO: This automation currently only support register without HW write access +<% + from reggen import (gen_fpv) + from reggen.register import Register + + from topgen import lib + + lblock = block.name.lower() + use_reg_iface = any([interface['protocol'] == BusProtocol.REG_IFACE and not interace['is_host'] for interface in block.bus_interfaces.interface_list]) + + # This template shouldn't be instantiated if the device interface + # doesn't actually have any registers. + assert rb.flat_regs + +%>\ +<%def name="construct_classes(block)">\ + +% if use_reg_iface: +`include "common_cells/assertions.svh" +% else: +`include "prim_assert.sv" +% endif +`ifdef UVM + import uvm_pkg::*; +`endif + +// Block: ${lblock} +module ${mod_base}_csr_assert_fpv import tlul_pkg::*; + import top_pkg::*;( + input clk_i, + input rst_ni, + + // tile link ports + input tl_h2d_t h2d, + input tl_d2h_t d2h +); +<% + addr_width = rb.get_addr_width() + addr_msb = addr_width - 1 + hro_regs_list = [r for r in rb.flat_regs if not r.hwaccess.allows_write()] + num_hro_regs = len(hro_regs_list) + hro_map = {r.offset: (idx, r) for idx, r in enumerate(hro_regs_list)} +%>\ + +// Currently FPV csr assertion only support HRO registers. +% if num_hro_regs > 0: +`ifndef VERILATOR +`ifndef SYNTHESIS + + parameter bit[3:0] MAX_A_SOURCE = 10; // used for FPV only to reduce runtime + + typedef struct packed { + logic [TL_DW-1:0] wr_data; + logic [TL_AW-1:0] addr; + logic wr_pending; + logic rd_pending; + } pend_item_t; + + bit disable_sva; + + // mask register to convert byte to bit + logic [TL_DW-1:0] a_mask_bit; + + assign a_mask_bit[7:0] = h2d.a_mask[0] ? '1 : '0; + assign a_mask_bit[15:8] = h2d.a_mask[1] ? '1 : '0; + assign a_mask_bit[23:16] = h2d.a_mask[2] ? '1 : '0; + assign a_mask_bit[31:24] = h2d.a_mask[3] ? '1 : '0; + + bit [${addr_msb}-2:0] hro_idx; // index for exp_vals + bit [${addr_msb}:0] normalized_addr; + + // Map register address with hro_idx in exp_vals array. + always_comb begin: decode_hro_addr_to_idx + unique case (pend_trans[d2h.d_source].addr) +% for idx, r in hro_map.values(): + ${r.offset}: hro_idx <= ${idx}; +% endfor + // If the register is not a HRO register, the write data will all update to this default idx. + default: hro_idx <= ${num_hro_regs + 1}; + endcase + end + + // store internal expected values for HW ReadOnly registers + logic [TL_DW-1:0] exp_vals[${num_hro_regs + 1}]; + + `ifdef FPV_ON + pend_item_t [MAX_A_SOURCE:0] pend_trans; + `else + pend_item_t [2**TL_AIW-1:0] pend_trans; + `endif + + // normalized address only take the [${addr_msb}:2] address from the TLUL a_address + assign normalized_addr = {h2d.a_address[${addr_msb}:2], 2'b0}; + +% if num_hro_regs > 0: + // for write HRO registers, store the write data into exp_vals + always_ff @(negedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + pend_trans <= '0; + % for hro_reg in hro_regs_list: + exp_vals[${hro_map.get(hro_reg.offset)[0]}] <= ${hro_reg.resval}; + % endfor + end else begin + if (h2d.a_valid && d2h.a_ready) begin + pend_trans[h2d.a_source].addr <= normalized_addr; + if (h2d.a_opcode inside {PutFullData, PutPartialData}) begin + pend_trans[h2d.a_source].wr_data <= h2d.a_data & a_mask_bit; + pend_trans[h2d.a_source].wr_pending <= 1'b1; + end else if (h2d.a_opcode == Get) begin + pend_trans[h2d.a_source].rd_pending <= 1'b1; + end + end + if (d2h.d_valid) begin + if (pend_trans[d2h.d_source].wr_pending == 1) begin + if (!d2h.d_error) begin + exp_vals[hro_idx] <= pend_trans[d2h.d_source].wr_data; + end + pend_trans[d2h.d_source].wr_pending <= 1'b0; + end + if (h2d.d_ready && pend_trans[d2h.d_source].rd_pending == 1) begin + pend_trans[d2h.d_source].rd_pending <= 1'b0; + end + end + end + end + + // for read HRO registers, assert read out values by access policy and exp_vals + % for hro_reg in hro_regs_list: +<% + r_name = hro_reg.name.lower() + reg_addr = hro_reg.offset + reg_addr_hex = format(reg_addr, 'x') + regwen = hro_reg.regwen + reg_mask = 0 + + for f in hro_reg.get_field_list(): + f_access = f.swaccess.key.lower() + if f_access == "rw" and regwen == None: + reg_mask = reg_mask | f.bits.bitmask() +%>\ + % if reg_mask != 0: +<% reg_mask_hex = format(reg_mask, 'x') %>\ + `ASSERT(${r_name}_rd_A, d2h.d_valid && pend_trans[d2h.d_source].rd_pending && + pend_trans[d2h.d_source].addr == ${addr_width}'h${reg_addr_hex} |-> + d2h.d_error || + (d2h.d_data & 'h${reg_mask_hex}) == (exp_vals[${hro_map.get(reg_addr)[0]}] & 'h${reg_mask_hex})) + + % endif + % endfor +% endif + + // This FPV only assumption is to reduce the FPV runtime. + `ASSUME_FPV(TlulSource_M, h2d.a_source >= 0 && h2d.a_source <= MAX_A_SOURCE, clk_i, !rst_ni) + + `ifdef UVM + initial forever begin + bit csr_assert_en; + uvm_config_db#(bit)::wait_modified(null, "%m", "csr_assert_en"); + if (!uvm_config_db#(bit)::get(null, "%m", "csr_assert_en", csr_assert_en)) begin + `uvm_fatal("csr_assert", "Can't find csr_assert_en") + end + disable_sva = !csr_assert_en; + end + `endif + +`endif +`endif +% endif +endmodule +\ +${construct_classes(block)} diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/gen_cfg_html.py b/hw/vendored_ips/gpio/util/reggen/reggen/gen_cfg_html.py new file mode 100644 index 00000000..0bb44d3d --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/gen_cfg_html.py @@ -0,0 +1,113 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +""" +Generate HTML documentation from Block +""" + +from typing import TextIO + +from .ip_block import IpBlock +from .html_helpers import render_td +from .signal import Signal + + +def genout(outfile: TextIO, msg: str) -> None: + outfile.write(msg) + + +def name_width(x: Signal) -> str: + if x.bits.width() == 1: + return x.name + + return '{}[{}:0]'.format(x.name, x.bits.msb) + + +def gen_kv(outfile: TextIO, key: str, value: str) -> None: + genout(outfile, + '

{}: {}

\n'.format(key, value)) + + +def gen_cfg_html(cfgs: IpBlock, outfile: TextIO) -> None: + rnames = cfgs.get_rnames() + + ot_server = 'https://docs.opentitan.org' + comport_url = ot_server + '/doc/rm/comportability_specification' + genout(outfile, + '

Referring to the Comportable guideline for ' + 'peripheral device functionality, the module ' + '{mod_name} has the following hardware ' + 'interfaces defined.

\n' + .format(url=comport_url, mod_name=cfgs.name)) + + # clocks + gen_kv(outfile, + 'Primary Clock', + '{}'.format(cfgs.clock_signals[0])) + if len(cfgs.clock_signals) > 1: + other_clocks = ['{}'.format(clk) + for clk in cfgs.clock_signals[1:]] + gen_kv(outfile, 'Other Clocks', ', '.join(other_clocks)) + else: + gen_kv(outfile, 'Other Clocks', 'none') + + # bus interfaces + dev_ports = ['{}'.format(port) + for port in cfgs.bus_interfaces.get_port_names(False, True)] + assert dev_ports + gen_kv(outfile, 'Bus Device Interfaces (TL-UL)', ', '.join(dev_ports)) + + host_ports = ['{}'.format(port) + for port in cfgs.bus_interfaces.get_port_names(True, False)] + if host_ports: + gen_kv(outfile, 'Bus Host Interfaces (TL-UL)', ', '.join(host_ports)) + else: + gen_kv(outfile, 'Bus Host Interfaces (TL-UL)', 'none') + + # IO + ios = ([('input', x) for x in cfgs.xputs[1]] + + [('output', x) for x in cfgs.xputs[2]] + + [('inout', x) for x in cfgs.xputs[0]]) + if ios: + genout(outfile, "

Peripheral Pins for Chip IO:

\n") + genout( + outfile, "" + + "" + + "\n") + for direction, x in ios: + genout(outfile, + '{}' + .format(name_width(x), + direction, + render_td(x.desc, rnames, None))) + genout(outfile, "
Pin namedirectionDescription
{}{}
\n") + else: + genout(outfile, "

Peripheral Pins for Chip IO: none

\n") + + if not cfgs.interrupts: + genout(outfile, "

Interrupts: none

\n") + else: + genout(outfile, "

Interrupts:

\n") + genout( + outfile, "" + + "\n") + for x in cfgs.interrupts: + genout(outfile, + '{}' + .format(name_width(x), + render_td(x.desc, rnames, None))) + genout(outfile, "
Interrupt NameDescription
{}
\n") + + if not cfgs.alerts: + genout(outfile, "

Security Alerts: none

\n") + else: + genout(outfile, "

Security Alerts:

\n") + genout( + outfile, "" + + "\n") + for x in cfgs.alerts: + genout(outfile, + '{}' + .format(x.name, + render_td(x.desc, rnames, None))) + genout(outfile, "
Alert NameDescription
{}
\n") diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/gen_cheader.py b/hw/vendored_ips/gpio/util/reggen/reggen/gen_cheader.py new file mode 100644 index 00000000..f68bd396 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/gen_cheader.py @@ -0,0 +1,439 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +""" +Generate C header from validated register JSON tree +""" + +import io +import logging as log +import sys +import textwrap +import warnings +from typing import List, Optional, Set, TextIO + + +from .field import Field +from .ip_block import IpBlock +from .params import LocalParam +from .register import Register +from .multi_register import MultiRegister +from .signal import Signal +from .window import Window + + +def genout(outfile: TextIO, msg: str) -> None: + outfile.write(msg) + +def to_snake_case(s: str) -> str: + val = [] + for i, ch in enumerate(s): + if i > 0 and ch.isupper(): + val.append('_') + val.append(ch) + return ''.join(val) + +def as_define(s: str) -> str: + s = s.upper() + r = '' + for i in range(0, len(s)): + r += s[i] if s[i].isalnum() else '_' + return r + + +def first_line(s: str) -> str: + """Returns the first line of a multi-line string""" + return s.splitlines()[0] + + +def format_comment(s: str) -> str: + """Formats a string to comment wrapped to an 80 character line width + + Returns wrapped string including newline and // comment characters. + """ + return '\n'.join( + textwrap.wrap( + s, width=77, initial_indent='// ', subsequent_indent='// ')) + '\n' + + +def gen_define(name: str, + args: List[str], + body: str, + existing_defines: Set[str], + indent: str = ' ') -> str: + r"""Produces a #define string, will split into two lines if a single line + has a width greater than 80 characters. Result includes newline. + + Arguments: + name - Name of the #define + args - List of arguments for the define, provide an empty list if there are + none + body - Body of the #define + existing_defines - set of already generated define names. + Error if `name` is in `existing_defines`. + indent - Gives string to prepend on any new lines produced by + wrapping (default ' ') + + Example result: + name = 'A_MACRO' + args = ['arg1', 'arg2'], + body = 'arg1 + arg2 + 10' + + #define A_MACRO(arg1, arg2) arg1 + arg2 + 10 + + When the macro is wrapped the break happens after the argument list (or + macro name if there is no argument list + + #define A_MACRO(arg1, arg2) \ + arg1 + arg2 + 10 + + """ + + if name in existing_defines: + log.error("Duplicate #define for " + name) + sys.exit(1) + + if len(args) != 0: + define_declare = '#define ' + name + '(' + ', '.join(args) + ')' + else: + define_declare = '#define ' + name + + oneline_define = define_declare + ' ' + body + + existing_defines.add(name) + + if len(oneline_define) <= 80: + return oneline_define + '\n' + + return define_declare + ' \\\n' + indent + body + '\n' + + +def gen_cdefine_register(outstr: TextIO, + reg: Register, + comp: str, + width: int, + rnames: Set[str], + existing_defines: Set[str]) -> None: + rname = reg.name + offset = reg.offset + + genout(outstr, format_comment(first_line(reg.desc))) + defname = as_define(comp + '_' + rname) + genout( + outstr, + gen_define(defname + '_REG_OFFSET', [], hex(offset), existing_defines)) + + for field in reg.fields: + dname = defname + '_' + as_define(field.name) + field_width = field.bits.width() + + if field_width == 1: + # single bit + genout( + outstr, + gen_define(dname + '_BIT', [], str(field.bits.lsb), + existing_defines)) + else: + # multiple bits (unless it is the whole register) + if field_width != width: + mask = field.bits.bitmask() >> field.bits.lsb + genout( + outstr, + gen_define(dname + '_MASK', [], hex(mask), + existing_defines)) + genout( + outstr, + gen_define(dname + '_OFFSET', [], str(field.bits.lsb), + existing_defines)) + genout( + outstr, + gen_define( + dname + '_FIELD', [], + '((bitfield_field32_t) {{ .mask = {dname}_MASK, .index = {dname}_OFFSET }})' + .format(dname=dname), existing_defines)) + if field.enum is not None: + for enum in field.enum: + ename = as_define(enum.name) + value = hex(enum.value) + genout( + outstr, + gen_define( + defname + '_' + as_define(field.name) + + '_VALUE_' + ename, [], value, existing_defines)) + genout(outstr, '\n') + return + + +def gen_cdefine_window(outstr: TextIO, + win: Window, + comp: str, + regwidth: int, + rnames: Set[str], + existing_defines: Set[str]) -> None: + offset = win.offset + + genout(outstr, format_comment('Memory area: ' + first_line(win.desc))) + defname = as_define(comp + '_' + win.name) + genout( + outstr, + gen_define(defname + '_REG_OFFSET', [], hex(offset), existing_defines)) + items = win.items + genout( + outstr, + gen_define(defname + '_SIZE_WORDS', [], str(items), existing_defines)) + items = items * (regwidth // 8) + genout( + outstr, + gen_define(defname + '_SIZE_BYTES', [], str(items), existing_defines)) + + wid = win.validbits + if (wid != regwidth): + mask = (1 << wid) - 1 + genout(outstr, + gen_define(defname + '_MASK ', [], hex(mask), existing_defines)) + + +def gen_cdefines_module_param(outstr: TextIO, + param: LocalParam, + module_name: str, + existing_defines: Set[str]) -> None: + # Presently there is only one type (int), however if the new types are + # added, they potentially need to be handled differently. + known_types = ["int"] + if param.param_type not in known_types: + warnings.warn("Cannot generate a module define of type {}" + .format(param.param_type)) + return + + if param.desc is not None: + genout(outstr, format_comment(first_line(param.desc))) + # Heuristic: if the name already has underscores, it's already snake_case, + # otherwise, assume StudlyCaps and covert it to snake_case. + param_name = param.name if '_' in param.name else to_snake_case(param.name) + define_name = as_define(module_name + '_PARAM_' + param_name) + if param.param_type == "int": + define = gen_define(define_name, [], param.value, + existing_defines) + + genout(outstr, define) + genout(outstr, '\n') + + +def gen_cdefines_module_params(outstr: TextIO, + module_data: IpBlock, + module_name: str, + register_width: int, + existing_defines: Set[str]) -> None: + module_params = module_data.params + + for param in module_params.get_localparams(): + gen_cdefines_module_param(outstr, param, module_name, existing_defines) + + genout(outstr, format_comment(first_line("Register width"))) + define_name = as_define(module_name + '_PARAM_REG_WIDTH') + define = gen_define(define_name, [], str(register_width), existing_defines) + genout(outstr, define) + genout(outstr, '\n') + + +def gen_multireg_field_defines(outstr: TextIO, + regname: str, + field: Field, + subreg_num: int, + regwidth: int, + existing_defines: Set[str]) -> None: + field_width = field.bits.width() + fields_per_reg = regwidth // field_width + + define_name = regname + '_' + as_define(field.name + "_FIELD_WIDTH") + define = gen_define(define_name, [], str(field_width), existing_defines) + genout(outstr, define) + + define_name = regname + '_' + as_define(field.name + "_FIELDS_PER_REG") + define = gen_define(define_name, [], str(fields_per_reg), existing_defines) + genout(outstr, define) + + define_name = regname + "_MULTIREG_COUNT" + define = gen_define(define_name, [], str(subreg_num), existing_defines) + genout(outstr, define) + + genout(outstr, '\n') + + +def gen_cdefine_multireg(outstr: TextIO, + multireg: MultiRegister, + component: str, + regwidth: int, + rnames: Set[str], + existing_defines: Set[str]) -> None: + comment = multireg.reg.desc + " (common parameters)" + genout(outstr, format_comment(first_line(comment))) + if len(multireg.reg.fields) == 1: + regname = as_define(component + '_' + multireg.reg.name) + gen_multireg_field_defines(outstr, regname, multireg.reg.fields[0], + len(multireg.regs), regwidth, existing_defines) + else: + log.warn("Non-homogeneous multireg " + multireg.reg.name + + " skip multireg specific data generation.") + + for subreg in multireg.regs: + gen_cdefine_register(outstr, subreg, component, regwidth, rnames, + existing_defines) + + +def gen_cdefines_interrupt_field(outstr: TextIO, + interrupt: Signal, + component: str, + regwidth: int, + existing_defines: Set[str]) -> None: + fieldlsb = interrupt.bits.lsb + iname = interrupt.name + defname = as_define(component + '_INTR_COMMON_' + iname) + + if interrupt.bits.width() == 1: + # single bit + genout( + outstr, + gen_define(defname + '_BIT', [], str(fieldlsb), existing_defines)) + else: + # multiple bits (unless it is the whole register) + if interrupt.bits.width() != regwidth: + mask = interrupt.bits.msb >> fieldlsb + genout( + outstr, + gen_define(defname + '_MASK', [], hex(mask), existing_defines)) + genout( + outstr, + gen_define(defname + '_OFFSET', [], str(fieldlsb), + existing_defines)) + genout( + outstr, + gen_define( + defname + '_FIELD', [], + '((bitfield_field32_t) {{ .mask = {dname}_MASK, .index = {dname}_OFFSET }})' + .format(dname=defname), existing_defines)) + + +def gen_cdefines_interrupts(outstr: TextIO, + block: IpBlock, + component: str, + regwidth: int, + existing_defines: Set[str]) -> None: + # If no_auto_intr_regs is true, then we do not generate common defines, + # because the bit offsets for a particular interrupt may differ between + # the interrupt enable/state/test registers. + if block.no_auto_intr: + return + + genout(outstr, format_comment(first_line("Common Interrupt Offsets"))) + for intr in block.interrupts: + gen_cdefines_interrupt_field(outstr, intr, component, regwidth, + existing_defines) + genout(outstr, '\n') + + +def gen_cdefines(block: IpBlock, + outfile: TextIO, + src_lic: Optional[str], + src_copy: str) -> int: + rnames = block.get_rnames() + + outstr = io.StringIO() + + # This tracks the defines that have been generated so far, so we + # can error if we attempt to duplicate a definition + existing_defines = set() # type: Set[str] + + gen_cdefines_module_params(outstr, block, block.name, block.regwidth, + existing_defines) + + gen_cdefines_interrupts(outstr, block, block.name, block.regwidth, + existing_defines) + + for rb in block.reg_blocks.values(): + for x in rb.entries: + if isinstance(x, Register): + gen_cdefine_register(outstr, x, block.name, block.regwidth, rnames, + existing_defines) + continue + + if isinstance(x, MultiRegister): + gen_cdefine_multireg(outstr, x, block.name, block.regwidth, rnames, + existing_defines) + continue + + if isinstance(x, Window): + gen_cdefine_window(outstr, x, block.name, block.regwidth, + rnames, existing_defines) + continue + + generated = outstr.getvalue() + outstr.close() + + genout(outfile, '// Generated register defines for ' + block.name + '\n\n') + if src_copy != '': + genout(outfile, '// Copyright information found in source file:\n') + genout(outfile, '// ' + src_copy + '\n\n') + if src_lic is not None: + genout(outfile, '// Licensing information found in source file:\n') + for line in src_lic.splitlines(): + genout(outfile, '// ' + line + '\n') + genout(outfile, '\n') + + # Header Include Guard + genout(outfile, '#ifndef _' + as_define(block.name) + '_REG_DEFS_\n') + genout(outfile, '#define _' + as_define(block.name) + '_REG_DEFS_\n\n') + + # Header Extern Guard (so header can be used from C and C++) + genout(outfile, '#ifdef __cplusplus\n') + genout(outfile, 'extern "C" {\n') + genout(outfile, '#endif\n') + + genout(outfile, generated) + + # Header Extern Guard + genout(outfile, '#ifdef __cplusplus\n') + genout(outfile, '} // extern "C"\n') + genout(outfile, '#endif\n') + + # Header Include Guard + genout(outfile, '#endif // _' + as_define(block.name) + '_REG_DEFS_\n') + + genout(outfile, '// End generated register defines for ' + block.name) + + return 0 + + +def test_gen_define() -> None: + basic_oneline = '#define MACRO_NAME body\n' + assert gen_define('MACRO_NAME', [], 'body', set()) == basic_oneline + + basic_oneline_with_args = '#define MACRO_NAME(arg1, arg2) arg1 + arg2\n' + assert (gen_define('MACRO_NAME', ['arg1', 'arg2'], 'arg1 + arg2', + set()) == basic_oneline_with_args) + + long_macro_name = 'A_VERY_VERY_VERY_VERY_VERY_VERY_VERY_VERY_VERY_VERY_VERY_LONG_MACRO_NAME' + + multiline = ('#define ' + long_macro_name + ' \\\n' + + ' a_fairly_long_body + something_else + 10\n') + + assert (gen_define(long_macro_name, [], + 'a_fairly_long_body + something_else + 10', + set()) == multiline) + + multiline_with_args = ('#define ' + long_macro_name + + '(arg1, arg2, arg3) \\\n' + + ' a_fairly_long_body + arg1 + arg2 + arg3\n') + + assert (gen_define(long_macro_name, ['arg1', 'arg2', 'arg3'], + 'a_fairly_long_body + arg1 + arg2 + arg3', + set()) == multiline_with_args) + + multiline_with_args_big_indent = ( + '#define ' + long_macro_name + '(arg1, arg2, arg3) \\\n' + + ' a_fairly_long_body + arg1 + arg2 + arg3\n') + + assert (gen_define(long_macro_name, ['arg1', 'arg2', 'arg3'], + 'a_fairly_long_body + arg1 + arg2 + arg3', + set(), + indent=' ') == multiline_with_args_big_indent) diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/gen_dv.py b/hw/vendored_ips/gpio/util/reggen/reggen/gen_dv.py new file mode 100644 index 00000000..d2d054ad --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/gen_dv.py @@ -0,0 +1,108 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +'''Generate DV code for an IP block''' + +import logging as log +import os +from typing import List + +import yaml + +from mako import exceptions # type: ignore +from mako.lookup import TemplateLookup # type: ignore +from pkg_resources import resource_filename + +from .ip_block import IpBlock +from .register import Register +from .window import Window + + +def bcname(esc_if_name: str) -> str: + '''Get the name of the dv_base_reg_block subclass for this device interface''' + return esc_if_name + "_reg_block" + + +def rcname(esc_if_name: str, r: Register) -> str: + '''Get the name of the dv_base_reg subclass for this register''' + return '{}_reg_{}'.format(esc_if_name, r.name.lower()) + + +def mcname(esc_if_name: str, m: Window) -> str: + '''Get the name of the dv_base_mem subclass for this memory''' + return '{}_mem_{}'.format(esc_if_name, m.name.lower()) + + +def miname(m: Window) -> str: + '''Get the lower-case name of a memory block''' + return m.name.lower() + + +def gen_core_file(outdir: str, + lblock: str, + dv_base_prefix: str, + paths: List[str]) -> None: + depends = ["lowrisc:dv:dv_base_reg"] + if dv_base_prefix and dv_base_prefix != "dv_base": + depends.append("lowrisc:dv:{}_reg".format(dv_base_prefix)) + + # Generate a fusesoc core file that points at the files we've just + # generated. + core_data = { + 'name': "lowrisc:dv:{}_ral_pkg".format(lblock), + 'filesets': { + 'files_dv': { + 'depend': depends, + 'files': paths, + 'file_type': 'systemVerilogSource' + }, + }, + 'targets': { + 'default': { + 'filesets': [ + 'files_dv', + ], + }, + }, + } + core_file_path = os.path.join(outdir, lblock + '_ral_pkg.core') + with open(core_file_path, 'w') as core_file: + core_file.write('CAPI=2:\n') + yaml.dump(core_data, core_file, encoding='utf-8') + + +def gen_dv(block: IpBlock, dv_base_prefix: str, outdir: str) -> int: + '''Generate DV files for an IpBlock''' + + lookup = TemplateLookup(directories=[resource_filename('reggen', '.')]) + uvm_reg_tpl = lookup.get_template('uvm_reg.sv.tpl') + + # Generate the RAL package(s). For a device interface with no name we + # generate the package "_ral_pkg" (writing to _ral_pkg.sv). + # In any other case, we also need the interface name, giving + # __ral_pkg. + generated = [] + + lblock = block.name.lower() + for if_name, rb in block.reg_blocks.items(): + hier_path = '' if block.hier_path is None else block.hier_path + '.' + if_suffix = '' if if_name is None else '_' + if_name.lower() + mod_base = lblock + if_suffix + reg_block_path = hier_path + 'u_reg' + if_suffix + + file_name = mod_base + '_ral_pkg.sv' + generated.append(file_name) + reg_top_path = os.path.join(outdir, file_name) + with open(reg_top_path, 'w', encoding='UTF-8') as fout: + try: + fout.write(uvm_reg_tpl.render(rb=rb, + block=block, + esc_if_name=mod_base, + reg_block_path=reg_block_path, + dv_base_prefix=dv_base_prefix)) + except: # noqa F722 for template Exception handling + log.error(exceptions.text_error_template().render()) + return 1 + + gen_core_file(outdir, lblock, dv_base_prefix, generated) + return 0 diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/gen_fpv.py b/hw/vendored_ips/gpio/util/reggen/reggen/gen_fpv.py new file mode 100644 index 00000000..e6e6d7d3 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/gen_fpv.py @@ -0,0 +1,81 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# # Lint as: python3 +# +"""Generate FPV CSR read and write assertions from IpBlock +""" + +import logging as log +import os.path + +import yaml +from mako import exceptions +from mako.template import Template +from pkg_resources import resource_filename + +from .ip_block import IpBlock + + +def gen_fpv(block: IpBlock, outdir): + # Read Register templates + fpv_csr_tpl = Template( + filename=resource_filename('reggen', 'fpv_csr.sv.tpl')) + + # Generate a module with CSR assertions for each device interface. For a + # device interface with no name, we generate _csr_assert_fpv. For a + # named interface, we generate __csr_assert_fpv. + lblock = block.name.lower() + generated = [] + for if_name, rb in block.reg_blocks.items(): + if not rb.flat_regs: + # No registers to check! + continue + + if if_name is None: + mod_base = lblock + else: + mod_base = lblock + '_' + if_name.lower() + + mod_name = mod_base + '_csr_assert_fpv' + filename = mod_name + '.sv' + generated.append(filename) + reg_top_path = os.path.join(outdir, filename) + with open(reg_top_path, 'w', encoding='UTF-8') as fout: + try: + fout.write(fpv_csr_tpl.render(block=block, + mod_base=mod_base, + if_name=if_name, + rb=rb)) + except: # noqa F722 for template Exception handling + log.error(exceptions.text_error_template().render()) + return 1 + + # Generate a fusesoc core file that points at the files we've just + # generated. + core_data = { + 'name': "lowrisc:fpv:{}_csr_assert".format(lblock), + 'filesets': { + 'files_dv': { + 'depend': [ + "lowrisc:tlul:headers", + "lowrisc:prim:assert", + ], + 'files': generated, + 'file_type': 'systemVerilogSource' + }, + }, + 'targets': { + 'default': { + 'filesets': [ + 'files_dv', + ], + }, + }, + } + core_file_path = os.path.join(outdir, lblock + '_csr_assert_fpv.core') + with open(core_file_path, 'w') as core_file: + core_file.write('CAPI=2:\n') + yaml.dump(core_data, core_file, encoding='utf-8') + + return 0 diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/gen_html.py b/hw/vendored_ips/gpio/util/reggen/reggen/gen_html.py new file mode 100644 index 00000000..e8c427b1 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/gen_html.py @@ -0,0 +1,325 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +""" +Generate HTML documentation from IpBlock +""" + +from typing import Set, TextIO + +from .ip_block import IpBlock +from .html_helpers import expand_paras, render_td +from .multi_register import MultiRegister +from .reg_block import RegBlock +from .register import Register +from .window import Window + + +def genout(outfile: TextIO, msg: str) -> None: + outfile.write(msg) + + +# Generation of HTML table with register bit-field summary picture +# Max 16-bit wide on one line + + +def gen_tbl_row(outfile: TextIO, msb: int, width: int, close: bool) -> None: + if (close): + genout(outfile, "\n") + genout(outfile, "") + for x in range(msb, msb - width, -1): + genout(outfile, "" + str(x) + "") + + genout(outfile, "") + + +def gen_html_reg_pic(outfile: TextIO, reg: Register, width: int) -> None: + + if (width > 32): + bsize = 3 + nextbit = 63 + hdrbits = 16 + nextline = 48 + elif (width > 16): + bsize = 3 + nextbit = 31 + hdrbits = 16 + nextline = 16 + elif (width > 8): + bsize = 3 + nextbit = 15 + nextline = 0 + hdrbits = 16 + else: + bsize = 12 + nextbit = 7 + nextline = 0 + hdrbits = 8 + + genout(outfile, "") + gen_tbl_row(outfile, nextbit, hdrbits, False) + + for field in reversed(reg.fields): + fieldlsb = field.bits.lsb + fieldwidth = field.bits.width() + fieldmsb = field.bits.msb + fname = field.name + + while nextbit > fieldmsb: + if (nextbit >= nextline) and (fieldmsb < nextline): + spans = nextbit - (nextline - 1) + else: + spans = nextbit - fieldmsb + genout( + outfile, "\n") + if (nextbit >= nextline) and (fieldmsb < nextline): + nextbit = nextline - 1 + gen_tbl_row(outfile, nextbit, hdrbits, True) + nextline = nextline - 16 + else: + nextbit = fieldmsb + + while (fieldmsb >= nextline) and (fieldlsb < nextline): + spans = fieldmsb - (nextline - 1) + genout( + outfile, "\n") + fname = "..." + field.name + fieldwidth = fieldwidth - spans + fieldmsb = nextline - 1 + nextline = nextline - 16 + gen_tbl_row(outfile, fieldmsb, hdrbits, True) + + namelen = len(fname) + if namelen == 0 or fname == ' ': + fname = " " + if (namelen > bsize * fieldwidth): + usestyle = (" style=\"font-size:" + str( + (bsize * 100 * fieldwidth) / namelen) + "%\"") + else: + usestyle = "" + + genout( + outfile, "\n") + + if (fieldlsb == nextline) and nextline > 0: + gen_tbl_row(outfile, nextline - 1, hdrbits, True) + nextline = nextline - 16 + + nextbit = fieldlsb - 1 + while (nextbit > 0): + spans = nextbit - (nextline - 1) + genout(outfile, + "\n") + nextbit = nextline - 1 + if (nextline > 0): + gen_tbl_row(outfile, nextline - 1, hdrbits, True) + nextline = nextline - 16 + + genout(outfile, "
 " + + fname + "..." + fname + " 
") + + +# Generation of HTML table with header, register picture and details + + +def gen_html_register(outfile: TextIO, + reg: Register, + comp: str, + width: int, + rnames: Set[str]) -> None: + rname = reg.name + offset = reg.offset + regwen_div = '' + if reg.regwen is not None: + regwen_div = ('
Register enable = {}
\n' + .format(reg.regwen)) + + desc_paras = expand_paras(reg.desc, rnames) + desc_head = desc_paras[0] + desc_body = desc_paras[1:] + + genout(outfile, + '\n' + ' \n' + ' \n' + ' \n' + .format(lrname=rname.lower(), + comp=comp, + rname=rname, + off=offset, + desc=desc_head, + resval=reg.resval, + mask=reg.resmask, + wen=regwen_div)) + if desc_body: + genout(outfile, + '' + .format(''.join(desc_body))) + + genout(outfile, "\n") + + genout(outfile, "") + genout(outfile, "") + genout(outfile, "") + genout(outfile, "") + genout(outfile, "") + nextbit = 0 + fcount = 0 + + for field in reg.fields: + fcount += 1 + fname = field.name + + fieldlsb = field.bits.lsb + if fieldlsb > nextbit: + genout(outfile, "") + genout(outfile, "") + genout(outfile, "") + genout( + outfile, "") + genout(outfile, "") + + # Collect up any description and enum table + desc_parts = [] + + if field.desc is not None: + desc_parts += expand_paras(field.desc, rnames) + + if field.enum is not None: + desc_parts.append('
\n' + '
{comp}.{rname} @ {off:#x}
\n' + '
{desc}
\n' + '
Reset default = {resval:#x}, mask {mask:#x}
\n' + '{wen}' + '
{}
") + gen_html_reg_pic(outfile, reg, width) + genout(outfile, "
BitsTypeResetNameDescription
") + if (nextbit == (fieldlsb - 1)): + genout(outfile, str(nextbit)) + else: + genout(outfile, str(fieldlsb - 1) + ":" + str(nextbit)) + genout(outfile, + "Reserved
" + field.bits.as_str() + "" + field.swaccess.key + "" + + ('x' if field.resval is None else hex(field.resval)) + + "" + fname + "
') + for enum in field.enum: + enum_desc_paras = expand_paras(enum.desc, rnames) + desc_parts.append('' + '' + '' + '' + '\n' + .format(val=enum.value, + name=enum.name, + desc=''.join(enum_desc_paras))) + desc_parts.append('
{val}{name}{desc}
') + if field.has_incomplete_enum(): + desc_parts.append("

Other values are reserved.

") + + genout(outfile, + '{}'.format(''.join(desc_parts))) + nextbit = fieldlsb + field.bits.width() + + genout(outfile, "\n
\n") + + +def gen_html_window(outfile: TextIO, + win: Window, + comp: str, + regwidth: int, + rnames: Set[str]) -> None: + wname = win.name or '(unnamed window)' + offset = win.offset + genout(outfile, + '\n' + ' \n' + ' \n' + ' \n' + .format(comp=comp, + wname=wname, + lwname=wname.lower(), + off=offset, + items=win.items, + swaccess=win.swaccess.key, + byte_writes=('' if win.byte_write else 'not '))) + genout(outfile, '{}'.format(render_td(win.desc, rnames, 'regde'))) + genout(outfile, "
\n' + '
{comp}.{wname} @ + {off:#x}
\n' + '
{items} item {swaccess} window
\n' + '
Byte writes are {byte_writes}supported
\n' + '
') + genout(outfile, '') + wid = win.validbits + + for x in range(regwidth - 1, -1, -1): + if x == regwidth - 1 or x == wid - 1 or x == 0: + genout(outfile, '') + else: + genout(outfile, '') + genout(outfile, '') + tblmax = win.items - 1 + for x in [0, 1, 2, tblmax - 1, tblmax]: + if x == 2: + genout( + outfile, '') + else: + genout( + outfile, '') + if wid < regwidth: + genout( + outfile, '\n') + genout( + outfile, + '\n') + else: + genout( + outfile, '\n') + genout(outfile, '') + genout(outfile, '
' + str(x) + '
 ...
+' + + hex(offset + x * (regwidth // 8)) + '   
') + genout(outfile, + '
\n
\n") + + +def gen_html_reg_block(outfile: TextIO, + rb: RegBlock, + comp: str, + width: int, + rnames: Set[str]) -> None: + for x in rb.entries: + if isinstance(x, Register): + gen_html_register(outfile, x, comp, width, rnames) + elif isinstance(x, MultiRegister): + for reg in x.regs: + gen_html_register(outfile, reg, comp, width, rnames) + else: + assert isinstance(x, Window) + gen_html_window(outfile, x, comp, width, rnames) + + +def gen_html(block: IpBlock, outfile: TextIO) -> int: + rnames = block.get_rnames() + + assert block.reg_blocks + # Handle the case where there's just one interface + if len(block.reg_blocks) == 1: + rb = list(block.reg_blocks.values())[0] + gen_html_reg_block(outfile, rb, block.name, block.regwidth, rnames) + return 0 + + # Handle the case where there is more than one device interface and, + # correspondingly, more than one reg block. + for iface_name, rb in block.reg_blocks.items(): + iface_desc = ('device interface {}'.format(iface_name) + if iface_name is not None + else 'the unnamed device interface') + genout(outfile, + '

Registers visible under {}

'.format(iface_desc)) + gen_html_reg_block(outfile, rb, block.name, block.regwidth, rnames) + + return 0 diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/gen_json.py b/hw/vendored_ips/gpio/util/reggen/reggen/gen_json.py new file mode 100644 index 00000000..c593cc1c --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/gen_json.py @@ -0,0 +1,34 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +"""Generate JSON/compact JSON/Hjson from register JSON tree +""" + +import hjson + + +def gen_json(obj, outfile, format): + if format == 'json': + hjson.dumpJSON(obj, + outfile, + ensure_ascii=False, + use_decimal=True, + indent=' ', + for_json=True) + elif format == 'compact': + hjson.dumpJSON(obj, + outfile, + ensure_ascii=False, + for_json=True, + use_decimal=True, + separators=(',', ':')) + elif format == 'hjson': + hjson.dump(obj, + outfile, + ensure_ascii=False, + for_json=True, + use_decimal=True) + else: + raise ValueError('Invalid JSON format ' + format) + + return 0 diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/gen_rtl.py b/hw/vendored_ips/gpio/util/reggen/reggen/gen_rtl.py new file mode 100644 index 00000000..14c9b4ba --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/gen_rtl.py @@ -0,0 +1,136 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +"""Generate SystemVerilog designs from IpBlock object""" + +import logging as log +import os +from typing import Dict, Optional, Tuple + +from mako import exceptions # type: ignore +from mako.template import Template # type: ignore +from pkg_resources import resource_filename + +from .ip_block import IpBlock +from .multi_register import MultiRegister +from .reg_base import RegBase +from .register import Register + + +def escape_name(name: str) -> str: + return name.lower().replace(' ', '_') + + +def make_box_quote(msg: str, indent: str = ' ') -> str: + hr = indent + ('/' * (len(msg) + 6)) + middle = indent + '// ' + msg + ' //' + return '\n'.join([hr, middle, hr]) + + +def _get_awparam_name(iface_name: Optional[str]) -> str: + return (iface_name or 'Iface').capitalize() + 'Aw' + + +def get_addr_widths(block: IpBlock) -> Dict[Optional[str], Tuple[str, int]]: + '''Return the address widths for the device interfaces + + Returns a dictionary keyed by interface name whose values are pairs: + (paramname, width) where paramname is IfaceAw for an unnamed interface and + FooAw for an interface called foo. This is constructed in the same order as + block.reg_blocks. + + If there is a single device interface and that interface is unnamed, use + the more general parameter name "BlockAw". + + ''' + assert block.reg_blocks + if len(block.reg_blocks) == 1 and None in block.reg_blocks: + return {None: ('BlockAw', block.reg_blocks[None].get_addr_width())} + + return {name: (_get_awparam_name(name), rb.get_addr_width()) + for name, rb in block.reg_blocks.items()} + + +def get_type_name_pfx(block: IpBlock, iface_name: Optional[str]) -> str: + return block.name.lower() + ('' if iface_name is None + else '_{}'.format(iface_name.lower())) + + +def get_r0(reg: RegBase) -> Register: + '''Get a Register representing an entry in the RegBase''' + if isinstance(reg, Register): + return reg + else: + assert isinstance(reg, MultiRegister) + return reg.reg + + +def get_iface_tx_type(block: IpBlock, + iface_name: Optional[str], + hw2reg: bool) -> str: + x2x = 'hw2reg' if hw2reg else 'reg2hw' + pfx = get_type_name_pfx(block, iface_name) + return '_'.join([pfx, x2x, 't']) + + +def get_reg_tx_type(block: IpBlock, reg: RegBase, hw2reg: bool) -> str: + '''Get the name of the hw2reg or reg2hw type for reg''' + if isinstance(reg, Register): + r0 = reg + type_suff = 'reg_t' + else: + assert isinstance(reg, MultiRegister) + r0 = reg.reg + type_suff = 'mreg_t' + + x2x = 'hw2reg' if hw2reg else 'reg2hw' + return '_'.join([block.name.lower(), + x2x, + r0.name.lower(), + type_suff]) + + +def gen_rtl(block: IpBlock, outdir: str) -> int: + # Read Register templates + reg_top_tpl = Template( + filename=resource_filename('reggen', 'reg_top.sv.tpl')) + reg_pkg_tpl = Template( + filename=resource_filename('reggen', 'reg_pkg.sv.tpl')) + + # Generate _reg_pkg.sv + # + # This defines the various types used to interface between the *_reg_top + # module(s) and the block itself. + reg_pkg_path = os.path.join(outdir, block.name.lower() + "_reg_pkg.sv") + with open(reg_pkg_path, 'w', encoding='UTF-8') as fout: + try: + fout.write(reg_pkg_tpl.render(block=block)) + except: # noqa F722 for template Exception handling + log.error(exceptions.text_error_template().render()) + return 1 + + # Generate the register block implementation(s). For a device interface + # with no name we generate the register module "_reg_top" (writing + # to _reg_top.sv). In any other case, we also need the interface + # name, giving __reg_top. + lblock = block.name.lower() + for if_name, rb in block.reg_blocks.items(): + if if_name is None: + mod_base = lblock + else: + mod_base = lblock + '_' + if_name.lower() + + mod_name = mod_base + '_reg_top' + reg_top_path = os.path.join(outdir, mod_name + '.sv') + with open(reg_top_path, 'w', encoding='UTF-8') as fout: + try: + fout.write(reg_top_tpl.render(block=block, + mod_base=mod_base, + mod_name=mod_name, + if_name=if_name, + rb=rb)) + except: # noqa F722 for template Exception handling + log.error(exceptions.text_error_template().render()) + return 1 + + return 0 diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/gen_selfdoc.py b/hw/vendored_ips/gpio/util/reggen/reggen/gen_selfdoc.py new file mode 100644 index 00000000..5f38404a --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/gen_selfdoc.py @@ -0,0 +1,306 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +""" +Generates the documentation for the register tool + +""" +from .access import SWACCESS_PERMITTED, HWACCESS_PERMITTED +from reggen import (validate, + ip_block, enum_entry, field, + register, multi_register, window) + + +def genout(outfile, msg): + outfile.write(msg) + + +doc_intro = """ + + + +The tables describe each key and the type of the value. The following +types are used: + +Type | Description +---- | ----------- +""" + +swaccess_intro = """ + +Register fields are tagged using the swaccess key to describe the +permitted access and side-effects. This key must have one of these +values: + +""" + +hwaccess_intro = """ + +Register fields are tagged using the hwaccess key to describe the +permitted access from hardware logic and side-effects. This key must +have one of these values: + +""" + +top_example = """ +The basic structure of a register definition file is thus: + +```hjson +{ + name: "GP", + regwidth: "32", + registers: [ + // register definitions... + ] +} + +``` + +""" + +register_example = """ + +The basic register definition group will follow this pattern: + +```hjson + { name: "REGA", + desc: "Description of register", + swaccess: "rw", + resval: "42", + fields: [ + // bit field definitions... + ] + } +``` + +The name and brief description are required. If the swaccess key is +provided it describes the access pattern that will be used by all +bitfields in the register that do not override with their own swaccess +key. This is a useful shortcut because in most cases a register will +have the same access restrictions for all fields. The reset value of +the register may also be provided here or in the individual fields. If +it is provided in both places then they must match, if it is provided +in neither place then the reset value defaults to zero for all except +write-only fields when it defaults to x. + +""" + +field_example = """ + +Field names should be relatively short because they will be used +frequently (and need to fit in the register layout picture!) The field +description is expected to be longer and will most likely make use of +the Hjson ability to include multi-line strings. An example with three +fields: + +```hjson + fields: [ + { bits: "15:0", + name: "RXS", + desc: ''' + Last 16 oversampled values of RX. These are captured at 16x the baud + rate clock. This is a shift register with the most recent bit in + bit 0 and the oldest in bit 15. Only valid when ENRXS is set. + ''' + } + { bits: "16", + name: "ENRXS", + desc: ''' + If this bit is set the receive oversampled data is collected + in the RXS field. + ''' + } + {bits: "20:19", name: "TXILVL", + desc: "Trigger level for TX interrupts", + resval: "2", + enum: [ + { value: "0", name: "txlvl1", desc: "1 character" }, + { value: "1", name: "txlvl4", desc: "4 characters" }, + { value: "2", name: "txlvl8", desc: "8 characters" }, + { value: "3", name: "txlvl16", desc: "16 characters" } + ] + } + ] +``` + +In all of these the swaccess parameter is inherited from the register +level, and will be added so this key is always available to the +backend. The RXS and ENRXS will default to zero reset value (unless +something different is provided for the register) and will have the +key added, but TXILVL expicitly sets its reset value as 2. + +The missing bits 17 and 18 will be treated as reserved by the tool, as +will any bits between 21 and the maximum in the register. + +The TXILVL is an example using an enumeration to specify all valid +values for the field. In this case all possible values are described, +if the list is incomplete then the field is marked with the rsvdenum +key so the backend can take appropriate action. (If the enum field is +more than 7 bits then the checking is not done.) + +""" + +offset_intro = """ + +""" + +multi_intro = """ + +The multireg expands on the register required fields and will generate +a list of the generated registers (that contain all required and +generated keys for an actual register). + +""" + +window_intro = """ + +A window defines an open region of the register space that can be used +for things that are not registers (for example access to a buffer ram). + +""" + +regwen_intro = """ + +Registers can protect themselves from software writes by using the +register attribute regwen. When not an emptry string (the default +value), regwen indicates that another register must be true in order +to allow writes to this register. This is useful for the prevention +of software modification. The register-enable register (call it +REGWEN) must be one bit in width, and should default to 1 and be rw1c +for preferred security control. This allows all writes to proceed +until at some point software disables future modifications by clearing +REGWEN. An error is reported if REGWEN does not exist, contains more +than one bit, is not `rw1c` or does not default to 1. One REGWEN can +protect multiple registers. The REGWEN register must precede those +registers that refer to it in the .hjson register list. An example: + +```hjson + { name: "REGWEN", + desc: "Register write enable for a bank of registers", + swaccess: "rw1c", + fields: [ { bits: "0", resval: "1" } ] + } + { name: "REGA", + swaccess: "rw", + regwen: "REGWEN", + ... + } + { name: "REGB", + swaccess: "rw", + regwen: "REGWEN", + ... + } +``` +""" + +doc_tail = """ + +(end of output generated by `regtool.py --doc`) + +""" + + +def doc_tbl_head(outfile, use): + if use is not None: + genout(outfile, "\nKey | Kind | Type | Description of Value\n") + genout(outfile, "--- | ---- | ---- | --------------------\n") + else: + genout(outfile, "\nKey | Description\n") + genout(outfile, "--- | -----------\n") + + +def doc_tbl_line(outfile, key, use, desc): + if use is not None: + desc_key, desc_txt = desc + val_type = (validate.val_types[desc_key][0] + if desc_key is not None else None) + else: + assert isinstance(desc, str) + val_type = None + desc_txt = desc + + if val_type is not None: + genout( + outfile, '{} | {} | {} | {}\n'.format(key, validate.key_use[use], + val_type, desc_txt)) + else: + genout(outfile, key + " | " + desc_txt + "\n") + + +def document(outfile): + genout(outfile, doc_intro) + for x in validate.val_types: + genout( + outfile, + validate.val_types[x][0] + " | " + validate.val_types[x][1] + "\n") + + genout(outfile, swaccess_intro) + doc_tbl_head(outfile, None) + for key, value in SWACCESS_PERMITTED.items(): + doc_tbl_line(outfile, key, None, value[0]) + + genout(outfile, hwaccess_intro) + doc_tbl_head(outfile, None) + for key, value in HWACCESS_PERMITTED.items(): + doc_tbl_line(outfile, key, None, value[0]) + + genout( + outfile, "\n\nThe top level of the JSON is a group containing " + "the following keys:\n") + doc_tbl_head(outfile, 1) + for k, v in ip_block.REQUIRED_FIELDS.items(): + doc_tbl_line(outfile, k, 'r', v) + for k, v in ip_block.OPTIONAL_FIELDS.items(): + doc_tbl_line(outfile, k, 'o', v) + genout(outfile, top_example) + + genout( + outfile, "\n\nThe list of registers includes register definition " + "groups containing the following keys:\n") + doc_tbl_head(outfile, 1) + for k, v in register.REQUIRED_FIELDS.items(): + doc_tbl_line(outfile, k, 'r', v) + for k, v in register.OPTIONAL_FIELDS.items(): + doc_tbl_line(outfile, k, 'o', v) + genout(outfile, register_example) + + genout( + outfile, "\n\nIn the fields list each field definition is a group " + "itself containing the following keys:\n") + doc_tbl_head(outfile, 1) + for k, v in field.REQUIRED_FIELDS.items(): + doc_tbl_line(outfile, k, 'r', v) + for k, v in field.OPTIONAL_FIELDS.items(): + doc_tbl_line(outfile, k, 'o', v) + genout(outfile, field_example) + + genout(outfile, "\n\nDefinitions in an enumeration group contain:\n") + doc_tbl_head(outfile, 1) + for k, v in enum_entry.REQUIRED_FIELDS.items(): + doc_tbl_line(outfile, k, 'r', v) + + genout( + outfile, "\n\nThe list of registers may include single entry groups " + "to control the offset, open a window or generate registers:\n") + doc_tbl_head(outfile, 1) + for x in validate.list_optone: + doc_tbl_line(outfile, x, 'o', validate.list_optone[x]) + + genout(outfile, offset_intro) + genout(outfile, regwen_intro) + + genout(outfile, window_intro) + doc_tbl_head(outfile, 1) + for k, v in window.REQUIRED_FIELDS.items(): + doc_tbl_line(outfile, k, 'r', v) + for k, v in window.OPTIONAL_FIELDS.items(): + doc_tbl_line(outfile, k, 'o', v) + + genout(outfile, multi_intro) + doc_tbl_head(outfile, 1) + for k, v in multi_register.REQUIRED_FIELDS.items(): + doc_tbl_line(outfile, k, 'r', v) + for k, v in multi_register.OPTIONAL_FIELDS.items(): + doc_tbl_line(outfile, k, 'o', v) + + genout(outfile, doc_tail) diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/html_helpers.py b/hw/vendored_ips/gpio/util/reggen/reggen/html_helpers.py new file mode 100644 index 00000000..8c828ee2 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/html_helpers.py @@ -0,0 +1,83 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +import logging as log +import re +from typing import List, Match, Optional, Set + + +def expand_paras(s: str, rnames: Set[str]) -> List[str]: + '''Expand a description field to HTML. + + This supports a sort of simple pseudo-markdown. Supported Markdown + features: + + - Separate paragraphs on a blank line + - **bold** and *italicised* text + - Back-ticks for pre-formatted text + + We also generate links to registers when a name is prefixed with a double + exclamation mark. For example, if there is a register FOO then !!FOO or + !!FOO.field will generate a link to that register. + + Returns a list of rendered paragraphs + + ''' + # Start by splitting into paragraphs. The regex matches a newline followed + # by one or more lines that just contain whitespace. Then render each + # paragraph with the _expand_paragraph worker function. + paras = [_expand_paragraph(paragraph.strip(), rnames) + for paragraph in re.split(r'\n(?:\s*\n)+', s)] + + # There will always be at least one paragraph (splitting an empty string + # gives ['']) + assert paras + return paras + + +def _expand_paragraph(s: str, rnames: Set[str]) -> str: + '''Expand a single paragraph, as described in _get_desc_paras''' + def fieldsub(match: Match[str]) -> str: + base = match.group(1).partition('.')[0].lower() + if base in rnames: + if match.group(1)[-1] == ".": + return ('' + + match.group(1)[:-1] + '.') + else: + return ('' + + match.group(1) + '') + log.warn('!!' + match.group(1).partition('.')[0] + + ' not found in register list.') + return match.group(0) + + # Split out pre-formatted text. Because the call to re.split has a capture + # group in the regex, we get an odd number of results. Elements with even + # indices are "normal text". Those with odd indices are the captured text + # between the back-ticks. + code_split = re.split(r'`([^`]+)`', s) + expanded_parts = [] + + for idx, part in enumerate(code_split): + if idx & 1: + # Text contained in back ticks + expanded_parts.append('{}'.format(part)) + continue + + part = re.sub(r"!!([A-Za-z0-9_.]+)", fieldsub, part) + part = re.sub(r"(?s)\*\*(.+?)\*\*", r'\1', part) + part = re.sub(r"\*([^*]+?)\*", r'\1', part) + expanded_parts.append(part) + + return '

{}

'.format(''.join(expanded_parts)) + + +def render_td(s: str, rnames: Set[str], td_class: Optional[str]) -> str: + '''Expand a description field and put it in a . + + Returns a string. See _get_desc_paras for the format that gets expanded. + + ''' + desc_paras = expand_paras(s, rnames) + class_attr = '' if td_class is None else ' class="{}"'.format(td_class) + return '{}'.format(class_attr, ''.join(desc_paras)) diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/inter_signal.py b/hw/vendored_ips/gpio/util/reggen/reggen/inter_signal.py new file mode 100644 index 00000000..cf27d511 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/inter_signal.py @@ -0,0 +1,81 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +from typing import Dict, Optional + +from .lib import (check_keys, check_name, + check_str, check_optional_str, check_int) + + +class InterSignal: + def __init__(self, + name: str, + desc: Optional[str], + struct: str, + package: Optional[str], + signal_type: str, + act: str, + width: int, + default: Optional[str]): + assert 0 < width + self.name = name + self.desc = desc + self.struct = struct + self.package = package + self.signal_type = signal_type + self.act = act + self.width = width + self.default = default + + @staticmethod + def from_raw(what: str, raw: object) -> 'InterSignal': + rd = check_keys(raw, what, + ['name', 'struct', 'type', 'act'], + ['desc', 'package', 'width', 'default']) + + name = check_name(rd['name'], 'name field of ' + what) + + r_desc = rd.get('desc') + if r_desc is None: + desc = None + else: + desc = check_str(r_desc, 'desc field of ' + what) + + struct = check_str(rd['struct'], 'struct field of ' + what) + + r_package = rd.get('package') + if r_package is None or r_package == '': + package = None + else: + package = check_name(r_package, 'package field of ' + what) + + signal_type = check_name(rd['type'], 'type field of ' + what) + act = check_name(rd['act'], 'act field of ' + what) + width = check_int(rd.get('width', 1), 'width field of ' + what) + if width <= 0: + raise ValueError('width field of {} is not positive.'.format(what)) + + default = check_optional_str(rd.get('default'), + 'default field of ' + what) + + return InterSignal(name, desc, struct, package, + signal_type, act, width, default) + + def _asdict(self) -> Dict[str, object]: + ret = {'name': self.name} # type: Dict[str, object] + if self.desc is not None: + ret['desc'] = self.desc + ret['struct'] = self.struct + if self.package is not None: + ret['package'] = self.package + ret['type'] = self.signal_type + ret['act'] = self.act + ret['width'] = self.width + if self.default is not None: + ret['default'] = self.default + + return ret + + def as_dict(self) -> Dict[str, object]: + return self._asdict() diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/ip_block.py b/hw/vendored_ips/gpio/util/reggen/reggen/ip_block.py new file mode 100644 index 00000000..5865d04a --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/ip_block.py @@ -0,0 +1,365 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +'''Code representing an IP block for reggen''' + +from typing import Dict, List, Optional, Sequence, Set, Tuple + +import hjson # type: ignore + +from .alert import Alert +from .bus_interfaces import BusInterfaces +from .inter_signal import InterSignal +from .lib import (check_keys, check_name, check_int, check_bool, + check_list, check_optional_str, check_name_list) +from .params import ReggenParams, LocalParam +from .reg_block import RegBlock +from .signal import Signal + + +REQUIRED_FIELDS = { + 'name': ['s', "name of the component"], + 'clock_primary': ['s', "name of the primary clock"], + 'bus_interfaces': ['l', "bus interfaces for the device"], + 'registers': [ + 'l', + "list of register definition groups and " + "offset control groups" + ] +} + +OPTIONAL_FIELDS = { + 'alert_list': ['lnw', "list of peripheral alerts"], + 'available_inout_list': ['lnw', "list of available peripheral inouts"], + 'available_input_list': ['lnw', "list of available peripheral inputs"], + 'available_output_list': ['lnw', "list of available peripheral outputs"], + 'hier_path': [ + None, + 'additional hierarchy path before the reg block instance' + ], + 'interrupt_list': ['lnw', "list of peripheral interrupts"], + 'inter_signal_list': ['l', "list of inter-module signals"], + 'no_auto_alert_regs': [ + 's', "Set to true to suppress automatic " + "generation of alert test registers. " + "Defaults to true if no alert_list is present. " + "Otherwise this defaults to false. " + ], + 'no_auto_intr_regs': [ + 's', "Set to true to suppress automatic " + "generation of interrupt registers. " + "Defaults to true if no interrupt_list is present. " + "Otherwise this defaults to false. " + ], + 'other_clock_list': ['l', "list of other chip clocks needed"], + 'other_reset_list': ['l', "list of other resets"], + 'param_list': ['lp', "list of parameters of the IP"], + 'regwidth': ['d', "width of registers in bits (default 32)"], + 'reset_primary': ['s', "primary reset used by the module"], + 'reset_request_list': ['l', 'list of signals requesting reset'], + 'scan': ['pb', 'Indicates the module have `scanmode_i`'], + 'scan_reset': ['pb', 'Indicates the module have `scan_rst_ni`'], + 'scan_en': ['pb', 'Indicates the module has `scan_en_i`'], + 'SPDX-License-Identifier': [ + 's', "License ientifier (if using pure json) " + "Only use this if unable to put this " + "information in a comment at the top of the " + "file." + ], + 'wakeup_list': ['lnw', "list of peripheral wakeups"] +} + + +class IpBlock: + def __init__(self, + name: str, + regwidth: int, + params: ReggenParams, + reg_blocks: Dict[Optional[str], RegBlock], + interrupts: Sequence[Signal], + no_auto_intr: bool, + alerts: List[Alert], + no_auto_alert: bool, + scan: bool, + inter_signals: List[InterSignal], + bus_interfaces: BusInterfaces, + hier_path: Optional[str], + clock_signals: List[str], + reset_signals: List[str], + xputs: Tuple[Sequence[Signal], + Sequence[Signal], + Sequence[Signal]], + wakeups: Sequence[Signal], + reset_requests: Sequence[Signal], + scan_reset: bool, + scan_en: bool): + assert reg_blocks + assert clock_signals + assert reset_signals + + # Check that register blocks are in bijection with device interfaces + reg_block_names = reg_blocks.keys() + dev_if_names = [] # type: List[Optional[str]] + dev_if_names += bus_interfaces.named_devices + if bus_interfaces.has_unnamed_device: + dev_if_names.append(None) + assert set(reg_block_names) == set(dev_if_names) + + self.name = name + self.regwidth = regwidth + self.reg_blocks = reg_blocks + self.params = params + self.interrupts = interrupts + self.no_auto_intr = no_auto_intr + self.alerts = alerts + self.no_auto_alert = no_auto_alert + self.scan = scan + self.inter_signals = inter_signals + self.bus_interfaces = bus_interfaces + self.hier_path = hier_path + self.clock_signals = clock_signals + self.reset_signals = reset_signals + self.xputs = xputs + self.wakeups = wakeups + self.reset_requests = reset_requests + self.scan_reset = scan_reset + self.scan_en = scan_en + + @staticmethod + def from_raw(param_defaults: List[Tuple[str, str]], + raw: object, + where: str) -> 'IpBlock': + + rd = check_keys(raw, 'block at ' + where, + list(REQUIRED_FIELDS.keys()), + list(OPTIONAL_FIELDS.keys())) + + name = check_name(rd['name'], 'name of block at ' + where) + + what = '{} block at {}'.format(name, where) + + r_regwidth = rd.get('regwidth') + if r_regwidth is None: + regwidth = 32 + else: + regwidth = check_int(r_regwidth, 'regwidth field of ' + what) + if regwidth <= 0: + raise ValueError('Invalid regwidth field for {}: ' + '{} is not positive.' + .format(what, regwidth)) + + params = ReggenParams.from_raw('parameter list for ' + what, + rd.get('param_list', [])) + try: + params.apply_defaults(param_defaults) + except (ValueError, KeyError) as err: + raise ValueError('Failed to apply defaults to params: {}' + .format(err)) from None + + init_block = RegBlock(regwidth, params) + + interrupts = Signal.from_raw_list('interrupt_list for block {}' + .format(name), + rd.get('interrupt_list', [])) + alerts = Alert.from_raw_list('alert_list for block {}' + .format(name), + rd.get('alert_list', [])) + + no_auto_intr = check_bool(rd.get('no_auto_intr_regs', not interrupts), + 'no_auto_intr_regs field of ' + what) + + no_auto_alert = check_bool(rd.get('no_auto_alert_regs', not alerts), + 'no_auto_alert_regs field of ' + what) + + if interrupts and not no_auto_intr: + if interrupts[-1].bits.msb >= regwidth: + raise ValueError("Interrupt list for {} is too wide: " + "msb is {}, which doesn't fit with a " + "regwidth of {}." + .format(what, + interrupts[-1].bits.msb, regwidth)) + init_block.make_intr_regs(interrupts) + + if alerts: + if not no_auto_alert: + if len(alerts) > regwidth: + raise ValueError("Interrupt list for {} is too wide: " + "{} alerts don't fit with a regwidth of {}." + .format(what, len(alerts), regwidth)) + init_block.make_alert_regs(alerts) + + # Generate a NumAlerts parameter + existing_param = params.get('NumAlerts') + if existing_param is not None: + if ((not isinstance(existing_param, LocalParam) or + existing_param.param_type != 'int' or + existing_param.value != str(len(alerts)))): + raise ValueError('Conflicting definition of NumAlerts ' + 'parameter.') + else: + params.add(LocalParam(name='NumAlerts', + desc='Number of alerts', + param_type='int', + value=str(len(alerts)))) + + scan = check_bool(rd.get('scan', False), 'scan field of ' + what) + + reg_blocks = RegBlock.build_blocks(init_block, rd['registers']) + + r_inter_signals = check_list(rd.get('inter_signal_list', []), + 'inter_signal_list field') + inter_signals = [ + InterSignal.from_raw('entry {} of the inter_signal_list field' + .format(idx + 1), + entry) + for idx, entry in enumerate(r_inter_signals) + ] + + bus_interfaces = (BusInterfaces. + from_raw(rd['bus_interfaces'], + 'bus_interfaces field of ' + where)) + inter_signals += bus_interfaces.inter_signals() + + hier_path = check_optional_str(rd.get('hier_path', None), + 'hier_path field of ' + what) + + clock_primary = check_name(rd['clock_primary'], + 'clock_primary field of ' + what) + other_clock_list = check_name_list(rd.get('other_clock_list', []), + 'other_clock_list field of ' + what) + clock_signals = [clock_primary] + other_clock_list + + reset_primary = check_name(rd.get('reset_primary', 'rst_ni'), + 'reset_primary field of ' + what) + other_reset_list = check_name_list(rd.get('other_reset_list', []), + 'other_reset_list field of ' + what) + reset_signals = [reset_primary] + other_reset_list + + xputs = ( + Signal.from_raw_list('available_inout_list for block ' + name, + rd.get('available_inout_list', [])), + Signal.from_raw_list('available_input_list for block ' + name, + rd.get('available_input_list', [])), + Signal.from_raw_list('available_output_list for block ' + name, + rd.get('available_output_list', [])) + ) + wakeups = Signal.from_raw_list('wakeup_list for block ' + name, + rd.get('wakeup_list', [])) + rst_reqs = Signal.from_raw_list('reset_request_list for block ' + name, + rd.get('reset_request_list', [])) + + scan_reset = check_bool(rd.get('scan_reset', False), + 'scan_reset field of ' + what) + + scan_en = check_bool(rd.get('scan_en', False), + 'scan_en field of ' + what) + + # Check that register blocks are in bijection with device interfaces + reg_block_names = reg_blocks.keys() + dev_if_names = [] # type: List[Optional[str]] + dev_if_names += bus_interfaces.named_devices + if bus_interfaces.has_unnamed_device: + dev_if_names.append(None) + if set(reg_block_names) != set(dev_if_names): + raise ValueError("IP block {} defines device interfaces, named {} " + "but its registers don't match (they are keyed " + "by {})." + .format(name, dev_if_names, + list(reg_block_names))) + + return IpBlock(name, regwidth, params, reg_blocks, + interrupts, no_auto_intr, alerts, no_auto_alert, + scan, inter_signals, bus_interfaces, + hier_path, clock_signals, reset_signals, xputs, + wakeups, rst_reqs, scan_reset, scan_en) + + @staticmethod + def from_text(txt: str, + param_defaults: List[Tuple[str, str]], + where: str) -> 'IpBlock': + '''Load an IpBlock from an hjson description in txt''' + return IpBlock.from_raw(param_defaults, + hjson.loads(txt, use_decimal=True), + where) + + @staticmethod + def from_path(path: str, + param_defaults: List[Tuple[str, str]]) -> 'IpBlock': + '''Load an IpBlock from an hjson description in a file at path''' + with open(path, 'r', encoding='utf-8') as handle: + return IpBlock.from_text(handle.read(), param_defaults, + 'file at {!r}'.format(path)) + + def _asdict(self) -> Dict[str, object]: + ret = { + 'name': self.name, + 'regwidth': self.regwidth + } + if len(self.reg_blocks) == 1 and None in self.reg_blocks: + ret['registers'] = self.reg_blocks[None].as_dicts() + else: + ret['registers'] = {k: v.as_dicts() + for k, v in self.reg_blocks.items()} + + ret['param_list'] = self.params.as_dicts() + ret['interrupt_list'] = self.interrupts + ret['no_auto_intr_regs'] = self.no_auto_intr + ret['alert_list'] = self.alerts + ret['no_auto_alert_regs'] = self.no_auto_alert + ret['scan'] = self.scan + ret['inter_signal_list'] = self.inter_signals + ret['bus_interfaces'] = self.bus_interfaces.as_dicts() + + if self.hier_path is not None: + ret['hier_path'] = self.hier_path + + ret['clock_primary'] = self.clock_signals[0] + if len(self.clock_signals) > 1: + ret['other_clock_list'] = self.clock_signals[1:] + + ret['reset_primary'] = self.reset_signals[0] + if len(self.reset_signals) > 1: + ret['other_reset_list'] = self.reset_signals[1:] + + inouts, inputs, outputs = self.xputs + if inouts: + ret['available_inout_list'] = inouts + if inputs: + ret['available_input_list'] = inputs + if outputs: + ret['available_output_list'] = outputs + + if self.wakeups: + ret['wakeup_list'] = self.wakeups + if self.reset_requests: + ret['reset_request_list'] = self.reset_requests + + ret['scan_reset'] = self.scan_reset + ret['scan_en'] = self.scan_en + + return ret + + def get_rnames(self) -> Set[str]: + ret = set() # type: Set[str] + for rb in self.reg_blocks.values(): + ret = ret.union(set(rb.name_to_offset.keys())) + return ret + + def get_signals_as_list_of_dicts(self) -> List[Dict]: + '''Look up and return signal by name''' + result = [] + for iodir, xput in zip(('inout', 'input', 'output'), self.xputs): + for sig in xput: + result.append(sig.as_nwt_dict(iodir)) + return result + + def get_signal_by_name_as_dict(self, name: str) -> Dict: + '''Look up and return signal by name''' + sig_list = self.get_signals_as_list_of_dicts() + for sig in sig_list: + if sig['name'] == name: + return sig + else: + raise ValueError("Signal {} does not exist in IP block {}" + .format(name, self.name)) diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/lib.py b/hw/vendored_ips/gpio/util/reggen/reggen/lib.py new file mode 100644 index 00000000..d72ef3d3 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/lib.py @@ -0,0 +1,262 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +'''Parsing support code for reggen''' + +import re +from typing import Dict, List, Optional, cast + + +# Names that are prohibited (used as reserved keywords in systemverilog) +_VERILOG_KEYWORDS = { + 'alias', 'always', 'always_comb', 'always_ff', 'always_latch', 'and', + 'assert', 'assign', 'assume', 'automatic', 'before', 'begin', 'bind', + 'bins', 'binsof', 'bit', 'break', 'buf', 'bufif0', 'bufif1', 'byte', + 'case', 'casex', 'casez', 'cell', 'chandle', 'class', 'clocking', 'cmos', + 'config', 'const', 'constraint', 'context', 'continue', 'cover', + 'covergroup', 'coverpoint', 'cross', 'deassign', 'default', 'defparam', + 'design', 'disable', 'dist', 'do', 'edge', 'else', 'end', 'endcase', + 'endclass', 'endclocking', 'endconfig', 'endfunction', 'endgenerate', + 'endgroup', 'endinterface', 'endmodule', 'endpackage', 'endprimitive', + 'endprogram', 'endproperty', 'endspecify', 'endsequence', 'endtable', + 'endtask', 'enum', 'event', 'expect', 'export', 'extends', 'extern', + 'final', 'first_match', 'for', 'force', 'foreach', 'forever', 'fork', + 'forkjoin', 'function', 'generate', 'genvar', 'highz0', 'highz1', 'if', + 'iff', 'ifnone', 'ignore_bins', 'illegal_bins', 'import', 'incdir', + 'include', 'initial', 'inout', 'input', 'inside', 'instance', 'int', + 'integer', 'interface', 'intersect', 'join', 'join_any', 'join_none', + 'large', 'liblist', 'library', 'local', 'localparam', 'logic', 'longint', + 'macromodule', 'matches', 'medium', 'modport', 'module', 'nand', 'negedge', + 'new', 'nmos', 'nor', 'noshowcancelled', 'not', 'notif0', 'notif1', 'null', + 'or', 'output', 'package', 'packed', 'parameter', 'pmos', 'posedge', + 'primitive', 'priority', 'program', 'property', 'protected', 'pull0', + 'pull1', 'pulldown', 'pullup', 'pulsestyle_onevent', 'pulsestyle_ondetect', + 'pure', 'rand', 'randc', 'randcase', 'randsequence', 'rcmos', 'real', + 'realtime', 'ref', 'reg', 'release', 'repeat', 'return', 'rnmos', 'rpmos', + 'rtran', 'rtranif0', 'rtranif1', 'scalared', 'sequence', 'shortint', + 'shortreal', 'showcancelled', 'signed', 'small', 'solve', 'specify', + 'specparam', 'static', 'string', 'strong0', 'strong1', 'struct', 'super', + 'supply0', 'supply1', 'table', 'tagged', 'task', 'this', 'throughout', + 'time', 'timeprecision', 'timeunit', 'tran', 'tranif0', 'tranif1', 'tri', + 'tri0', 'tri1', 'triand', 'trior', 'trireg', 'type', 'typedef', 'union', + 'unique', 'unsigned', 'use', 'uwire', 'var', 'vectored', 'virtual', 'void', + 'wait', 'wait_order', 'wand', 'weak0', 'weak1', 'while', 'wildcard', + 'wire', 'with', 'within', 'wor', 'xnor', 'xor' +} + + +def check_str_dict(obj: object, what: str) -> Dict[str, object]: + if not isinstance(obj, dict): + raise ValueError("{} is expected to be a dict, but was actually a {}." + .format(what, type(obj).__name__)) + + for key in obj: + if not isinstance(key, str): + raise ValueError('{} has a key {!r}, which is not a string.' + .format(what, key)) + + return cast(Dict[str, object], obj) + + +def check_keys(obj: object, + what: str, + required_keys: List[str], + optional_keys: List[str]) -> Dict[str, object]: + '''Check that obj is a dict object with the expected keys + + If not, raise a ValueError; the what argument names the object. + + ''' + od = check_str_dict(obj, what) + + allowed = set() + missing = [] + for key in required_keys: + assert key not in allowed + allowed.add(key) + if key not in od: + missing.append(key) + + for key in optional_keys: + assert key not in allowed + allowed.add(key) + + unexpected = [] + for key in od: + if key not in allowed: + unexpected.append(key) + + if missing or unexpected: + mstr = ('The following required fields were missing: {}.' + .format(', '.join(missing)) if missing else '') + ustr = ('The following unexpected fields were found: {}.' + .format(', '.join(unexpected)) if unexpected else '') + raise ValueError("{} doesn't have the right keys. {}{}{}" + .format(what, + mstr, + ' ' if mstr and ustr else '', + ustr)) + + return od + + +def check_str(obj: object, what: str) -> str: + '''Check that the given object is a string + + If not, raise a ValueError; the what argument names the object. + + ''' + if not isinstance(obj, str): + raise ValueError('{} is of type {}, not a string.' + .format(what, type(obj).__name__)) + return obj + + +def check_name(obj: object, what: str) -> str: + '''Check that obj is a string that's a valid name. + + If not, raise a ValueError; the what argument names the object. + + ''' + as_str = check_str(obj, what) + + # Allow the usual symbol constituents (alphanumeric plus underscore; no + # leading numbers) + if not re.match(r'[a-zA-Z_][a-zA-Z_0-9]*$', as_str): + raise ValueError("{} is {!r}, which isn't a valid symbol in " + "C / Verilog, so isn't allowed as a name." + .format(what, as_str)) + + # Also check that this isn't a reserved word. + if as_str in _VERILOG_KEYWORDS: + raise ValueError("{} is {!r}, which is a reserved word in " + "SystemVerilog, so isn't allowed as a name." + .format(what, as_str)) + + return as_str + + +def check_bool(obj: object, what: str) -> bool: + '''Check that obj is a bool or a string that parses to a bool. + + If not, raise a ValueError; the what argument names the object. + + ''' + if isinstance(obj, str): + as_bool = { + 'true': True, + 'false': False, + '1': True, + '0': False + }.get(obj.lower()) + if as_bool is None: + raise ValueError('{} is {!r}, which cannot be parsed as a bool.' + .format(what, obj)) + return as_bool + + if obj is True or obj is False: + return obj + + raise ValueError('{} is of type {}, not a bool.' + .format(what, type(obj).__name__)) + + +def check_list(obj: object, what: str) -> List[object]: + '''Check that the given object is a list + + If not, raise a ValueError; the what argument names the object. + + ''' + if not isinstance(obj, list): + raise ValueError('{} is of type {}, not a list.' + .format(what, type(obj).__name__)) + return obj + + +def check_str_list(obj: object, what: str) -> List[str]: + '''Check that the given object is a list of strings + + If not, raise a ValueError; the what argument names the object. + + ''' + lst = check_list(obj, what) + for idx, elt in enumerate(lst): + if not isinstance(elt, str): + raise ValueError('Element {} of {} is of type {}, ' + 'not a string.' + .format(idx, what, type(elt).__name__)) + return cast(List[str], lst) + + +def check_name_list(obj: object, what: str) -> List[str]: + '''Check that the given object is a list of valid names + + If not, raise a ValueError; the what argument names the object. + + ''' + lst = check_list(obj, what) + for idx, elt in enumerate(lst): + check_name(elt, 'Element {} of {}'.format(idx + 1, what)) + + return cast(List[str], lst) + + +def check_int(obj: object, what: str) -> int: + '''Check that obj is an integer or a string that parses to an integer. + + If not, raise a ValueError; the what argument names the object. + + ''' + if isinstance(obj, int): + return obj + + if isinstance(obj, str): + try: + return int(obj, 0) + except ValueError: + raise ValueError('{} is {!r}, which cannot be parsed as an int.' + .format(what, obj)) from None + + raise ValueError('{} is of type {}, not an integer.' + .format(what, type(obj).__name__)) + + +def check_xint(obj: object, what: str) -> Optional[int]: + '''Check that obj is an integer, a string that parses to an integer or "x". + + On success, return an integer value if there is one or None if the value + was 'x'. On failure, raise a ValueError; the what argument names the + object. + + ''' + if isinstance(obj, int): + return obj + + if isinstance(obj, str): + if obj == 'x': + return None + try: + return int(obj, 0) + except ValueError: + raise ValueError('{} is {!r}, which is not "x", ' + 'nor can it be parsed as an int.' + .format(what, obj)) from None + + raise ValueError('{} is of type {}, not an integer.' + .format(what, type(obj).__name__)) + + +def check_optional_str(obj: object, what: str) -> Optional[str]: + '''Check that obj is a string or None''' + return None if obj is None else check_str(obj, what) + + +def get_basename(name: str) -> str: + '''Strip trailing _number (used as multireg suffix) from name''' + # TODO: This is a workaround, should solve this as part of parsing a + # multi-reg. + match = re.search(r'_[0-9]+$', name) + assert match + assert match.start() > 0 + return name[0:match.start()] diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/multi_register.py b/hw/vendored_ips/gpio/util/reggen/reggen/multi_register.py new file mode 100644 index 00000000..82c86677 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/multi_register.py @@ -0,0 +1,142 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +from typing import Dict, List + +from reggen import register +from .field import Field +from .lib import check_keys, check_str, check_name, check_bool +from .params import ReggenParams +from .reg_base import RegBase +from .register import Register + +REQUIRED_FIELDS = { + 'name': ['s', "base name of the registers"], + 'desc': ['t', "description of the registers"], + 'count': [ + 's', "number of instances to generate." + " This field can be integer or string matching" + " from param_list." + ], + 'cname': [ + 's', "base name for each instance, mostly" + " useful for referring to instance in messages." + ], + 'fields': [ + 'l', "list of register field description" + " groups. Describes bit positions used for" + " base instance." + ] +} +OPTIONAL_FIELDS = register.OPTIONAL_FIELDS.copy() +OPTIONAL_FIELDS.update({ + 'regwen_multi': [ + 'pb', "If true, regwen term increments" + " along with current multireg count." + ], + 'compact': [ + 'pb', "If true, allow multireg compacting." + "If false, do not compact." + ] +}) + + +class MultiRegister(RegBase): + def __init__(self, + offset: int, + addrsep: int, + reg_width: int, + params: ReggenParams, + raw: object): + super().__init__(offset) + + rd = check_keys(raw, 'multireg', + list(REQUIRED_FIELDS.keys()), + list(OPTIONAL_FIELDS.keys())) + + # Now that we've checked the schema of rd, we make a "reg" version of + # it that removes any fields that are allowed by MultiRegister but + # aren't allowed by Register. We'll pass that to the register factory + # method. + reg_allowed_keys = (set(register.REQUIRED_FIELDS.keys()) | + set(register.OPTIONAL_FIELDS.keys())) + reg_rd = {key: value + for key, value in rd.items() + if key in reg_allowed_keys} + self.reg = Register.from_raw(reg_width, offset, params, reg_rd) + + self.cname = check_name(rd['cname'], + 'cname field of multireg {}' + .format(self.reg.name)) + + self.regwen_multi = check_bool(rd.get('regwen_multi', False), + 'regwen_multi field of multireg {}' + .format(self.reg.name)) + + default_compact = True if len(self.reg.fields) == 1 else False + self.compact = check_bool(rd.get('compact', default_compact), + 'compact field of multireg {}' + .format(self.reg.name)) + if self.compact and len(self.reg.fields) > 1: + raise ValueError('Multireg {} sets the compact flag ' + 'but has multiple fields.' + .format(self.reg.name)) + + count_str = check_str(rd['count'], + 'count field of multireg {}' + .format(self.reg.name)) + self.count = params.expand(count_str, + 'count field of multireg ' + self.reg.name) + if self.count <= 0: + raise ValueError("Multireg {} has a count of {}, " + "which isn't positive." + .format(self.reg.name, self.count)) + + # Generate the registers that this multireg expands into. Here, a + # "creg" is a "compacted register", which might contain multiple actual + # registers. + if self.compact: + assert len(self.reg.fields) == 1 + width_per_reg = self.reg.fields[0].bits.msb + 1 + assert width_per_reg <= reg_width + regs_per_creg = reg_width // width_per_reg + else: + regs_per_creg = 1 + + self.regs = [] + creg_count = (self.count + regs_per_creg - 1) // regs_per_creg + for creg_idx in range(creg_count): + min_reg_idx = regs_per_creg * creg_idx + max_reg_idx = min(min_reg_idx + regs_per_creg, self.count) - 1 + creg_offset = offset + creg_idx * addrsep + + reg = self.reg.make_multi(reg_width, + creg_offset, creg_idx, creg_count, + self.regwen_multi, self.compact, + min_reg_idx, max_reg_idx, self.cname) + self.regs.append(reg) + + def next_offset(self, addrsep: int) -> int: + return self.offset + len(self.regs) * addrsep + + def get_n_bits(self, bittype: List[str] = ["q"]) -> int: + return sum(reg.get_n_bits(bittype) for reg in self.regs) + + def get_field_list(self) -> List[Field]: + ret = [] + for reg in self.regs: + ret += reg.get_field_list() + return ret + + def is_homogeneous(self) -> bool: + return self.reg.is_homogeneous() + + def _asdict(self) -> Dict[str, object]: + rd = self.reg._asdict() + rd['count'] = str(self.count) + rd['cname'] = self.cname + rd['regwen_multi'] = str(self.regwen_multi) + rd['compact'] = str(self.compact) + + return {'multireg': rd} diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/params.py b/hw/vendored_ips/gpio/util/reggen/reggen/params.py new file mode 100644 index 00000000..b7a6adcb --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/params.py @@ -0,0 +1,341 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +import re +from collections.abc import MutableMapping +from typing import Dict, List, Optional, Tuple + +from .lib import check_keys, check_str, check_int, check_bool, check_list + +REQUIRED_FIELDS = { + 'name': ['s', "name of the item"], +} + +OPTIONAL_FIELDS = { + 'desc': ['s', "description of the item"], + 'type': ['s', "item type. int by default"], + 'default': ['s', "item default value"], + 'local': ['pb', "to be localparam"], + 'expose': ['pb', "to be exposed to top"], + 'randcount': [ + 's', "number of bits to randomize in the parameter. 0 by default." + ], + 'randtype': ['s', "type of randomization to perform. none by default"], +} + + +class BaseParam: + def __init__(self, name: str, desc: Optional[str], param_type: str): + self.name = name + self.desc = desc + self.param_type = param_type + + def apply_default(self, value: str) -> None: + if self.param_type[:3] == 'int': + check_int(value, + 'default value for parameter {} ' + '(which has type {})' + .format(self.name, self.param_type)) + self.default = value + + def as_dict(self) -> Dict[str, object]: + rd = {} # type: Dict[str, object] + rd['name'] = self.name + if self.desc is not None: + rd['desc'] = self.desc + rd['type'] = self.param_type + return rd + + +class LocalParam(BaseParam): + def __init__(self, + name: str, + desc: Optional[str], + param_type: str, + value: str): + super().__init__(name, desc, param_type) + self.value = value + + def expand_value(self, when: str) -> int: + try: + return int(self.value, 0) + except ValueError: + raise ValueError("When {}, the {} value expanded as " + "{}, which doesn't parse as an integer." + .format(when, self.name, self.value)) from None + + def as_dict(self) -> Dict[str, object]: + rd = super().as_dict() + rd['local'] = True + rd['default'] = self.value + return rd + + +class Parameter(BaseParam): + def __init__(self, + name: str, + desc: Optional[str], + param_type: str, + default: str, + expose: bool): + super().__init__(name, desc, param_type) + self.default = default + self.expose = expose + + def as_dict(self) -> Dict[str, object]: + rd = super().as_dict() + rd['default'] = self.default + rd['expose'] = 'true' if self.expose else 'false' + return rd + + +class RandParameter(BaseParam): + def __init__(self, + name: str, + desc: Optional[str], + param_type: str, + randcount: int, + randtype: str): + assert randcount > 0 + assert randtype in ['perm', 'data'] + super().__init__(name, desc, param_type) + self.randcount = randcount + self.randtype = randtype + + def apply_default(self, value: str) -> None: + raise ValueError('Cannot apply a default value of {!r} to ' + 'parameter {}: it is a random netlist constant.' + .format(self.name, value)) + + def as_dict(self) -> Dict[str, object]: + rd = super().as_dict() + rd['randcount'] = self.randcount + rd['randtype'] = self.randtype + return rd + + +def _parse_parameter(where: str, raw: object) -> BaseParam: + rd = check_keys(raw, where, + list(REQUIRED_FIELDS.keys()), + list(OPTIONAL_FIELDS.keys())) + + # TODO: Check if PascalCase or ALL_CAPS + name = check_str(rd['name'], 'name field of ' + where) + + r_desc = rd.get('desc') + if r_desc is None: + desc = None + else: + desc = check_str(r_desc, 'desc field of ' + where) + + # TODO: We should probably check that any register called RndCnstFoo has + # randtype and randcount. + if name.lower().startswith('rndcnst') and 'randtype' in rd: + # This is a random netlist constant and should be parsed as a + # RandParameter. + randtype = check_str(rd.get('randtype', 'none'), + 'randtype field of ' + where) + if randtype not in ['perm', 'data']: + raise ValueError('At {}, parameter {} has a name that implies it ' + 'is a random netlist constant, which means it ' + 'must specify a randtype of "perm" or "data", ' + 'rather than {!r}.' + .format(where, name, randtype)) + + r_randcount = rd.get('randcount') + if r_randcount is None: + raise ValueError('At {}, the random netlist constant {} has no ' + 'randcount field.' + .format(where, name)) + randcount = check_int(r_randcount, 'randcount field of ' + where) + if randcount <= 0: + raise ValueError('At {}, the random netlist constant {} has a ' + 'randcount of {}, which is not positive.' + .format(where, name, randcount)) + + r_type = rd.get('type') + if r_type is None: + raise ValueError('At {}, parameter {} has no type field (which is ' + 'required for random netlist constants).' + .format(where, name)) + param_type = check_str(r_type, 'type field of ' + where) + + local = check_bool(rd.get('local', 'false'), 'local field of ' + where) + if local: + raise ValueError('At {}, the parameter {} specifies local = true, ' + 'meaning that it is a localparam. This is ' + 'incompatible with being a random netlist ' + 'constant (how would it be set?)' + .format(where, name)) + + r_default = rd.get('default') + if r_default is not None: + raise ValueError('At {}, the parameter {} specifies a value for ' + 'the "default" field. This is incompatible with ' + 'being a random netlist constant: the value will ' + 'be set by the random generator.' + .format(where, name)) + + expose = check_bool(rd.get('expose', 'false'), + 'expose field of ' + where) + if expose: + raise ValueError('At {}, the parameter {} specifies expose = ' + 'true, meaning that the parameter is exposed to ' + 'the top-level. This is incompatible with being ' + 'a random netlist constant.' + .format(where, name)) + + return RandParameter(name, desc, param_type, randcount, randtype) + + # This doesn't have a name like a random netlist constant. Check that it + # doesn't define randcount or randtype. + for fld in ['randcount', 'randtype']: + if fld in rd: + raise ValueError("At {where}, the parameter {name} specifies " + "{fld} but the name doesn't look like a random " + "netlist constant. To use {fld}, prefix the name " + "with RndCnst." + .format(where=where, name=name, fld=fld)) + + r_type = rd.get('type') + if r_type is None: + param_type = 'int' + else: + param_type = check_str(r_type, 'type field of ' + where) + + local = check_bool(rd.get('local', 'true'), 'local field of ' + where) + expose = check_bool(rd.get('expose', 'false'), 'expose field of ' + where) + + r_default = rd.get('default') + if r_default is None: + raise ValueError('At {}, the {} param has no default field.' + .format(where, name)) + else: + default = check_str(r_default, 'default field of ' + where) + if param_type[:3] == 'int': + check_int(default, + 'default field of {}, (an integer parameter)' + .format(name)) + + if local: + if expose: + raise ValueError('At {}, the localparam {} cannot be exposed to ' + 'the top-level.' + .format(where, name)) + return LocalParam(name, desc, param_type, value=default) + else: + return Parameter(name, desc, param_type, default, expose) + + +class Params(MutableMapping): + def __init__(self) -> None: + self.by_name = {} # type: Dict[str, BaseParam] + + def __getitem__(self, key): + return self.by_name[key] + + def __delitem__(self, key): + del self.by_name[key] + + def __setitem__(self, key, value): + self.by_name[key] = value + + def __iter__(self): + return iter(self.by_name) + + def __len__(self): + return len(self.by_name) + + def __repr__(self): + return f"{type(self).__name__}({self.by_name})" + + def add(self, param: BaseParam) -> None: + assert param.name not in self.by_name + self.by_name[param.name] = param + + def apply_defaults(self, defaults: List[Tuple[str, str]]) -> None: + for idx, (key, value) in enumerate(defaults): + param = self.by_name[key] + if param is None: + raise KeyError('Cannot find parameter ' + '{} to set default value.' + .format(key)) + + param.apply_default(value) + + def _expand_one(self, value: str, when: str) -> int: + # Check whether value is already an integer: if so, return that. + try: + return int(value, 0) + except ValueError: + pass + + param = self.by_name.get(value) + if param is None: + raise ValueError('Cannot find a parameter called {} when {}. ' + 'Known parameters: {}.' + .format(value, + when, + ', '.join(self.by_name.keys()))) + + # Only allow localparams in the expansion (because otherwise we're at + # the mercy of whatever instantiates the block). + if not isinstance(param, LocalParam): + raise ValueError("When {}, {} is a not a local parameter." + .format(when, value)) + + return param.expand_value(when) + + def expand(self, value: str, where: str) -> int: + # Here, we want to support arithmetic expressions with + and -. We + # don't support other operators, or parentheses (so can parse with just + # a regex). + # + # Use re.split, capturing the operators. This turns e.g. "a + b-c" into + # ['a ', '+', ' b', '-', 'c']. If there's a leading operator ("+a"), + # the first element of the results is an empty string. This means + # elements with odd positions are always operators and elements with + # even positions are values. + acc = 0 + is_neg = False + + for idx, tok in enumerate(re.split(r'([+-])', value)): + if idx == 0 and not tok: + continue + if idx % 2: + is_neg = (tok == '-') + continue + + term = self._expand_one(tok.strip(), + 'expanding term {} of {}' + .format(idx // 2, where)) + acc += -term if is_neg else term + + return acc + + def as_dicts(self) -> List[Dict[str, object]]: + return [p.as_dict() for p in self.by_name.values()] + + +class ReggenParams(Params): + @staticmethod + def from_raw(where: str, raw: object) -> 'ReggenParams': + ret = ReggenParams() + rl = check_list(raw, where) + for idx, r_param in enumerate(rl): + entry_where = 'entry {} in {}'.format(idx + 1, where) + param = _parse_parameter(entry_where, r_param) + if param.name in ret: + raise ValueError('At {}, found a duplicate parameter with ' + 'name {}.' + .format(entry_where, param.name)) + ret.add(param) + return ret + + def get_localparams(self) -> List[LocalParam]: + ret = [] + for param in self.by_name.values(): + if isinstance(param, LocalParam): + ret.append(param) + return ret diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/reg_base.py b/hw/vendored_ips/gpio/util/reggen/reggen/reg_base.py new file mode 100644 index 00000000..eb88b463 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/reg_base.py @@ -0,0 +1,45 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +from typing import List + +from .field import Field + + +class RegBase: + '''An abstract class inherited by Register and MultiRegister + + This represents a block of one or more registers with a base address. + + ''' + def __init__(self, offset: int): + self.offset = offset + + def get_n_bits(self, bittype: List[str]) -> int: + '''Get the size of this register / these registers in bits + + See Field.get_n_bits() for the precise meaning of bittype. + + ''' + raise NotImplementedError() + + def get_field_list(self) -> List[Field]: + '''Get an ordered list of the fields in the register(s) + + Registers are ordered from low to high address. Within a register, + fields are ordered as Register.fields: from LSB to MSB. + + ''' + raise NotImplementedError() + + def is_homogeneous(self) -> bool: + '''True if every field in the block is identical + + For a single register, this is true if it only has one field. For a + multireg, it is true if the generating register has just one field. + Note that if the compact flag is set, the generated registers might + have multiple (replicated) fields. + + ''' + raise NotImplementedError() diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/reg_block.py b/hw/vendored_ips/gpio/util/reggen/reggen/reg_block.py new file mode 100644 index 00000000..30a4f747 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/reg_block.py @@ -0,0 +1,431 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +'''Code representing the registers, windows etc. for a block''' + +import re +from typing import Callable, Dict, List, Optional, Sequence, Union + +from .alert import Alert +from .access import SWAccess, HWAccess +from .field import Field +from .signal import Signal +from .lib import check_int, check_list, check_str_dict, check_str +from .multi_register import MultiRegister +from .params import ReggenParams +from .register import Register +from .window import Window + + +class RegBlock: + def __init__(self, reg_width: int, params: ReggenParams): + + self._addrsep = (reg_width + 7) // 8 + self._reg_width = reg_width + self._params = params + + self.offset = 0 + self.multiregs = [] # type: List[MultiRegister] + self.registers = [] # type: List[Register] + self.windows = [] # type: List[Window] + + # Boolean indication whether ANY window in regblock has data integrity passthrough + self.has_data_intg_passthru = False + + # A list of all registers, expanding multiregs, ordered by offset + self.flat_regs = [] # type: List[Register] + + # A list of registers and multiregisters (unexpanded) + self.all_regs = [] # type: List[Union[Register, MultiRegister]] + + # A list with everything in order + self.entries = [] # type: List[object] + + # A dict of named entries, mapping name to offset + self.name_to_offset = {} # type: Dict[str, int] + + # A dict of all registers (expanding multiregs), mapping name to the + # register object + self.name_to_flat_reg = {} # type: Dict[str, Register] + + # A list of all write enable names + self.wennames = [] # type: List[str] + + @staticmethod + def build_blocks(block: 'RegBlock', + raw: object) -> Dict[Optional[str], 'RegBlock']: + '''Build a dictionary of blocks for a 'registers' field in the hjson + + There are two different syntaxes we might see here. The simple syntax + just consists of a list of entries (register, multireg, window, + skipto). If we see that, each entry gets added to init_block and then + we return {None: init_block}. + + The more complicated syntax is a dictionary. This parses from hjson as + an OrderedDict which we walk in document order. Entries from the first + key/value pair in the dictionary will be added to init_block. Later + key/value pairs start empty RegBlocks. The return value is a dictionary + mapping the keys we saw to their respective RegBlocks. + + ''' + if isinstance(raw, list): + # This is the simple syntax + block.add_raw_registers(raw, 'registers field at top-level') + return {None: block} + + # This is the more complicated syntax + if not isinstance(raw, dict): + raise ValueError('registers field at top-level is ' + 'neither a list or a dictionary.') + + ret = {} # type: Dict[Optional[str], RegBlock] + for idx, (r_key, r_val) in enumerate(raw.items()): + if idx > 0: + block = RegBlock(block._reg_width, block._params) + + rb_key = check_str(r_key, + 'the key for item {} of ' + 'the registers dictionary at top-level' + .format(idx + 1)) + rb_val = check_list(r_val, + 'the value for item {} of ' + 'the registers dictionary at top-level' + .format(idx + 1)) + + block.add_raw_registers(rb_val, + 'item {} of the registers ' + 'dictionary at top-level' + .format(idx + 1)) + block.validate() + + assert rb_key not in ret + ret[rb_key] = block + + return ret + + def add_raw_registers(self, raw: object, what: str) -> None: + rl = check_list(raw, 'registers field at top-level') + for entry_idx, entry_raw in enumerate(rl): + where = ('entry {} of the top-level registers field' + .format(entry_idx + 1)) + self.add_raw(where, entry_raw) + + def add_raw(self, where: str, raw: object) -> None: + entry = check_str_dict(raw, where) + + handlers = { + 'register': self._handle_register, + 'reserved': self._handle_reserved, + 'skipto': self._handle_skipto, + 'window': self._handle_window, + 'multireg': self._handle_multireg + } + + entry_type = 'register' + entry_body = entry # type: object + + for t in ['reserved', 'skipto', 'window', 'multireg']: + t_body = entry.get(t) + if t_body is not None: + # Special entries look like { window: { ... } }, so if we + # get a hit, this should be the only key in entry. Note + # that this also checks that nothing has more than one + # entry type. + if len(entry) != 1: + other_keys = [k for k in entry if k != t] + assert other_keys + raise ValueError('At offset {:#x}, {} has key {}, which ' + 'should give its type. But it also has ' + 'other keys too: {}.' + .format(self.offset, + where, t, ', '.join(other_keys))) + entry_type = t + entry_body = t_body + + entry_where = ('At offset {:#x}, {}, type {!r}' + .format(self.offset, where, entry_type)) + + handlers[entry_type](entry_where, entry_body) + + def _handle_register(self, where: str, body: object) -> None: + reg = Register.from_raw(self._reg_width, + self.offset, self._params, body) + self.add_register(reg) + + def _handle_reserved(self, where: str, body: object) -> None: + nreserved = check_int(body, 'body of ' + where) + if nreserved <= 0: + raise ValueError('Reserved count in {} is {}, ' + 'which is not positive.' + .format(where, nreserved)) + + self.offset += self._addrsep * nreserved + + def _handle_skipto(self, where: str, body: object) -> None: + skipto = check_int(body, 'body of ' + where) + if skipto < self.offset: + raise ValueError('Destination of skipto in {} is {:#x}, ' + 'is less than the current offset, {:#x}.' + .format(where, skipto, self.offset)) + if skipto % self._addrsep: + raise ValueError('Destination of skipto in {} is {:#x}, ' + 'not a multiple of addrsep, {:#x}.' + .format(where, skipto, self._addrsep)) + self.offset = skipto + + def _handle_window(self, where: str, body: object) -> None: + window = Window.from_raw(self.offset, + self._reg_width, self._params, body) + if window.name is not None: + lname = window.name.lower() + if lname in self.name_to_offset: + raise ValueError('Window {} (at offset {:#x}) has the ' + 'same name as something at offset {:#x}.' + .format(window.name, window.offset, + self.name_to_offset[lname])) + self.add_window(window) + + def _handle_multireg(self, where: str, body: object) -> None: + mr = MultiRegister(self.offset, + self._addrsep, self._reg_width, self._params, body) + for reg in mr.regs: + lname = reg.name.lower() + if lname in self.name_to_offset: + raise ValueError('Multiregister {} (at offset {:#x}) expands ' + 'to a register with name {} (at offset ' + '{:#x}), but this already names something at ' + 'offset {:#x}.' + .format(mr.reg.name, mr.reg.offset, + reg.name, reg.offset, + self.name_to_offset[lname])) + self._add_flat_reg(reg) + self.name_to_offset[lname] = reg.offset + + self.multiregs.append(mr) + self.all_regs.append(mr) + self.entries.append(mr) + self.offset = mr.next_offset(self._addrsep) + + def add_register(self, reg: Register) -> None: + assert reg.offset == self.offset + + lname = reg.name.lower() + if lname in self.name_to_offset: + raise ValueError('Register {} (at offset {:#x}) has the same ' + 'name as something at offset {:#x}.' + .format(reg.name, reg.offset, + self.name_to_offset[lname])) + self._add_flat_reg(reg) + self.name_to_offset[lname] = reg.offset + + self.registers.append(reg) + self.all_regs.append(reg) + self.entries.append(reg) + self.offset = reg.next_offset(self._addrsep) + + if reg.regwen is not None and reg.regwen not in self.wennames: + self.wennames.append(reg.regwen) + + def _add_flat_reg(self, reg: Register) -> None: + # The first assertion is checked at the call site (where we can print + # out a nicer message for multiregs). The second assertion should be + # implied by the first. + assert reg.name not in self.name_to_offset + assert reg.name not in self.name_to_flat_reg + + self.flat_regs.append(reg) + self.name_to_flat_reg[reg.name.lower()] = reg + + def add_window(self, window: Window) -> None: + if window.name is not None: + lname = window.name.lower() + assert lname not in self.name_to_offset + self.name_to_offset[lname] = window.offset + + self.windows.append(window) + self.entries.append(window) + assert self.offset <= window.offset + self.offset = window.next_offset(self._addrsep) + + self.has_data_intg_passthru |= window.data_intg_passthru + + def validate(self) -> None: + '''Run this to check consistency after all registers have been added''' + + # Check that every write-enable register has a good name, a valid reset + # value, and valid access permissions. + for wenname in self.wennames: + # check the REGWEN naming convention + if re.fullmatch(r'(.+_)*REGWEN(_[0-9]+)?', wenname) is None: + raise ValueError("Regwen name {} must have the suffix '_REGWEN'" + .format(wenname)) + + wen_reg = self.name_to_flat_reg.get(wenname.lower()) + if wen_reg is None: + raise ValueError('One or more registers use {} as a ' + 'write-enable, but there is no such register.' + .format(wenname)) + + # If the REGWEN bit is SW controlled, check that the register + # defaults to enabled. If this bit is read-only by SW and hence + # hardware controlled, we do not enforce this requirement. + if wen_reg.swaccess.key != "ro" and not wen_reg.resval: + raise ValueError('One or more registers use {} as a ' + 'write-enable. Since it is SW-controlled ' + 'it should have a nonzero reset value.' + .format(wenname)) + + if wen_reg.swaccess.key == "rw0c": + # The register is software managed: all good! + continue + + if wen_reg.swaccess.key == "ro" and wen_reg.hwaccess.key == "hwo": + # The register is hardware managed: that's fine too. + continue + + raise ValueError('One or more registers use {} as a write-enable. ' + 'However, it has invalid access permissions ' + '({} / {}). It should either have swaccess=RW0C ' + 'or have swaccess=RO and hwaccess=HWO.' + .format(wenname, + wen_reg.swaccess.key, + wen_reg.hwaccess.key)) + + def get_n_bits(self, bittype: List[str] = ["q"]) -> int: + '''Returns number of bits in registers in this block. + + This includes those expanded from multiregs. See Field.get_n_bits for a + description of the bittype argument. + + ''' + return sum(reg.get_n_bits(bittype) for reg in self.flat_regs) + + def as_dicts(self) -> List[object]: + entries = [] # type: List[object] + offset = 0 + for entry in self.entries: + assert (isinstance(entry, Register) or + isinstance(entry, MultiRegister) or + isinstance(entry, Window)) + + next_off = entry.offset + assert offset <= next_off + res_bytes = next_off - offset + if res_bytes: + assert res_bytes % self._addrsep == 0 + entries.append({'reserved': res_bytes // self._addrsep}) + + entries.append(entry) + offset = entry.next_offset(self._addrsep) + + return entries + + _FieldFormatter = Callable[[bool, str], str] + + def _add_intr_alert_reg(self, + signals: Sequence[Signal], + reg_name: str, + reg_desc: str, + field_desc_fmt: Optional[Union[str, _FieldFormatter]], + swaccess: str, + hwaccess: str, + is_testreg: bool, + reg_tags: List[str]) -> None: + swaccess_obj = SWAccess('RegBlock._make_intr_alert_reg()', swaccess) + hwaccess_obj = HWAccess('RegBlock._make_intr_alert_reg()', hwaccess) + + fields = [] + for signal in signals: + if field_desc_fmt is None: + field_desc = signal.desc + elif isinstance(field_desc_fmt, str): + field_desc = field_desc_fmt + else: + width = signal.bits.width() + field_desc = field_desc_fmt(width > 1, signal.name) + + fields.append(Field(signal.name, + field_desc or signal.desc, + tags=[], + swaccess=swaccess_obj, + hwaccess=hwaccess_obj, + hwqe=is_testreg, + hwre=False, + bits=signal.bits, + resval=0, + enum=None)) + + reg = Register(self.offset, + reg_name, + reg_desc, + swaccess_obj, + hwaccess_obj, + hwext=is_testreg, + hwqe=is_testreg, + hwre=False, + regwen=None, + tags=reg_tags, + resval=None, + shadowed=False, + fields=fields, + update_err_alert=None, + storage_err_alert=None) + self.add_register(reg) + + def make_intr_regs(self, interrupts: Sequence[Signal]) -> None: + assert interrupts + assert interrupts[-1].bits.msb < self._reg_width + + self._add_intr_alert_reg(interrupts, + 'INTR_STATE', + 'Interrupt State Register', + None, + 'rw1c', + 'hrw', + False, + # intr_state csr is affected by writes to + # other csrs - skip write-check + ["excl:CsrNonInitTests:CsrExclWriteCheck"]) + self._add_intr_alert_reg(interrupts, + 'INTR_ENABLE', + 'Interrupt Enable Register', + lambda w, n: ('Enable interrupt when ' + '{}!!INTR_STATE.{} is set.' + .format('corresponding bit in ' + if w else '', + n)), + 'rw', + 'hro', + False, + []) + self._add_intr_alert_reg(interrupts, + 'INTR_TEST', + 'Interrupt Test Register', + lambda w, n: ('Write 1 to force ' + '{}!!INTR_STATE.{} to 1.' + .format('corresponding bit in ' + if w else '', + n)), + 'wo', + 'hro', + True, + # intr_test csr is WO so reads back 0s + ["excl:CsrNonInitTests:CsrExclWrite"]) + + def make_alert_regs(self, alerts: List[Alert]) -> None: + assert alerts + assert len(alerts) < self._reg_width + self._add_intr_alert_reg(alerts, + 'ALERT_TEST', + 'Alert Test Register', + ('Write 1 to trigger ' + 'one alert event of this kind.'), + 'wo', + 'hro', + True, + []) + + def get_addr_width(self) -> int: + '''Calculate the number of bits to address every byte of the block''' + return (self.offset - 1).bit_length() diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/reg_html.css b/hw/vendored_ips/gpio/util/reggen/reggen/reg_html.css new file mode 100644 index 00000000..4cb48edb --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/reg_html.css @@ -0,0 +1,74 @@ +/* Stylesheet for reggen HTML register output */ +/* Copyright lowRISC contributors. */ +/* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ +/* SPDX-License-Identifier: Apache-2.0 */ + +table.regpic { + width: 95%; + border-collapse: collapse; + margin-left:auto; + margin-right:auto; + table-layout:fixed; +} + +table.regdef { + border: 1px solid black; + width: 80%; + border-collapse: collapse; + margin-left:auto; + margin-right:auto; + table-layout:auto; +} + +table.regdef th { + border: 1px solid black; + font-family: sans-serif; + +} + +td.bitnum { + font-size: 60%; + text-align: center; +} + +td.unused { + border: 1px solid black; + background-color: gray; +} + +td.fname { + border: 1px solid black; + text-align: center; + font-family: sans-serif; +} + + +td.regbits, td.regperm, td.regrv { + border: 1px solid black; + text-align: center; + font-family: sans-serif; +} + +td.regde, td.regfn { + border: 1px solid black; +} + +table.cfgtable { + border: 1px solid black; + width: 80%; + border-collapse: collapse; + margin-left:auto; + margin-right:auto; + table-layout:auto; +} + +table.cfgtable th { + border: 1px solid black; + font-family: sans-serif; + font-weight: bold; +} + +table.cfgtable td { + border: 1px solid black; + font-family: sans-serif; +} diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/reg_pkg.sv.tpl b/hw/vendored_ips/gpio/util/reggen/reggen/reg_pkg.sv.tpl new file mode 100644 index 00000000..1c5520a5 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/reg_pkg.sv.tpl @@ -0,0 +1,347 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure +<% + from topgen import lib # TODO: Split lib to common lib module + + from reggen.access import HwAccess, SwRdAccess, SwWrAccess + from reggen.register import Register + from reggen.multi_register import MultiRegister + + from reggen import gen_rtl + + localparams = block.params.get_localparams() + + addr_widths = gen_rtl.get_addr_widths(block) + + lblock = block.name.lower() + ublock = lblock.upper() + + def reg_pfx(reg): + return '{}_{}'.format(ublock, reg.name.upper()) + + def reg_resname(reg): + return '{}_RESVAL'.format(reg_pfx(reg)) + + def field_resname(reg, field): + return '{}_{}_RESVAL'.format(reg_pfx(reg), field.name.upper()) + +%>\ +<%def name="typedefs_for_iface(iface_name, iface_desc, for_iface, rb)">\ +<% + hdr = gen_rtl.make_box_quote('Typedefs for registers' + for_iface) +%>\ +% for r in rb.all_regs: + % if r.get_n_bits(["q"]): + % if hdr: + +${hdr} + % endif +<% + r0 = gen_rtl.get_r0(r) + hdr = None +%>\ + + typedef struct packed { + % if r.is_homogeneous(): + ## If we have a homogeneous register or multireg, there is just one field + ## (possibly replicated many times). The typedef is for one copy of that + ## field. +<% + field = r.get_field_list()[0] + field_q_width = field.get_n_bits(r0.hwext, ['q']) + field_q_bits = lib.bitarray(field_q_width, 2) +%>\ + logic ${field_q_bits} q; + % if field.hwqe: + logic qe; + % endif + % if field.hwre or (r0.shadowed and r0.hwext): + logic re; + % endif + % if r0.shadowed and not r0.hwext: + logic err_update; + logic err_storage; + % endif + % else: + ## We are inhomogeneous, which means there is more than one different + ## field. Generate a reg2hw typedef that packs together all the fields of + ## the register. + % for f in r0.fields: + % if f.get_n_bits(r0.hwext, ["q"]) >= 1: +<% + field_q_width = f.get_n_bits(r0.hwext, ['q']) + field_q_bits = lib.bitarray(field_q_width, 2) + + struct_name = f.name.lower() +%>\ + struct packed { + logic ${field_q_bits} q; + % if f.hwqe: + logic qe; + % endif + % if f.hwre or (r0.shadowed and r0.hwext): + logic re; + % endif + % if r0.shadowed and not r0.hwext: + logic err_update; + logic err_storage; + % endif + } ${struct_name}; + %endif + %endfor + %endif + } ${gen_rtl.get_reg_tx_type(block, r, False)}; + %endif +% endfor +% for r in rb.all_regs: + % if r.get_n_bits(["d"]): + % if hdr: + +${hdr} + % endif +<% + r0 = gen_rtl.get_r0(r) + hdr = None +%>\ + + typedef struct packed { + % if r.is_homogeneous(): + ## If we have a homogeneous register or multireg, there is just one field + ## (possibly replicated many times). The typedef is for one copy of that + ## field. +<% + field = r.get_field_list()[0] + field_d_width = field.get_n_bits(r0.hwext, ['d']) + field_d_bits = lib.bitarray(field_d_width, 2) +%>\ + logic ${field_d_bits} d; + % if not r0.hwext: + logic de; + % endif + % else: + ## We are inhomogeneous, which means there is more than one different + ## field. Generate a hw2reg typedef that packs together all the fields of + ## the register. + % for f in r0.fields: + % if f.get_n_bits(r0.hwext, ["d"]) >= 1: +<% + field_d_width = f.get_n_bits(r0.hwext, ['d']) + field_d_bits = lib.bitarray(field_d_width, 2) + + struct_name = f.name.lower() +%>\ + struct packed { + logic ${field_d_bits} d; + % if not r0.hwext: + logic de; + % endif + } ${struct_name}; + %endif + %endfor + %endif + } ${gen_rtl.get_reg_tx_type(block, r, True)}; + % endif +% endfor +\ +<%def name="reg2hw_for_iface(iface_name, iface_desc, for_iface, rb)">\ +<% +nbits = rb.get_n_bits(["q", "qe", "re"]) +packbit = 0 +%>\ +% if nbits > 0: + + // Register -> HW type${for_iface} + typedef struct packed { +% for r in rb.all_regs: + % if r.get_n_bits(["q"]): +<% + r0 = gen_rtl.get_r0(r) + struct_type = gen_rtl.get_reg_tx_type(block, r, False) + struct_width = r0.get_n_bits(['q', 'qe', 're']) + + if isinstance(r, MultiRegister): + struct_type += " [{}:0]".format(r.count - 1) + struct_width *= r.count + + msb = nbits - packbit - 1 + lsb = msb - struct_width + 1 + packbit += struct_width +%>\ + ${struct_type} ${r0.name.lower()}; // [${msb}:${lsb}] + % endif +% endfor + } ${gen_rtl.get_iface_tx_type(block, iface_name, False)}; +% endif +\ +<%def name="hw2reg_for_iface(iface_name, iface_desc, for_iface, rb)">\ +<% +nbits = rb.get_n_bits(["d", "de"]) +packbit = 0 +%>\ +% if nbits > 0: + + // HW -> register type${for_iface} + typedef struct packed { +% for r in rb.all_regs: + % if r.get_n_bits(["d"]): +<% + r0 = gen_rtl.get_r0(r) + struct_type = gen_rtl.get_reg_tx_type(block, r, True) + struct_width = r0.get_n_bits(['d', 'de']) + + if isinstance(r, MultiRegister): + struct_type += " [{}:0]".format(r.count - 1) + struct_width *= r.count + + msb = nbits - packbit - 1 + lsb = msb - struct_width + 1 + packbit += struct_width +%>\ + ${struct_type} ${r0.name.lower()}; // [${msb}:${lsb}] + % endif +% endfor + } ${gen_rtl.get_iface_tx_type(block, iface_name, True)}; +% endif +\ +<%def name="offsets_for_iface(iface_name, iface_desc, for_iface, rb)">\ +% if not rb.flat_regs: +<% return STOP_RENDERING %> +% endif + + // Register offsets${for_iface} +<% +aw_name, aw = addr_widths[iface_name] +%>\ +% for r in rb.flat_regs: +<% +value = "{}'h {:x}".format(aw, r.offset) +%>\ + parameter logic [${aw_name}-1:0] ${reg_pfx(r)}_OFFSET = ${value}; +% endfor +\ +<%def name="hwext_resvals_for_iface(iface_name, iface_desc, for_iface, rb)">\ +<% + hwext_regs = [r for r in rb.flat_regs if r.hwext] +%>\ +% if hwext_regs: + + // Reset values for hwext registers and their fields${for_iface} + % for reg in hwext_regs: +<% + reg_width = reg.get_width() + reg_msb = reg_width - 1 + reg_resval = "{}'h {:x}".format(reg_width, reg.resval) +%>\ + parameter logic [${reg_msb}:0] ${reg_resname(reg)} = ${reg_resval}; + % for field in reg.fields: + % if field.resval is not None: +<% + field_width = field.bits.width() + field_msb = field_width - 1 + field_resval = "{}'h {:x}".format(field_width, field.resval) +%>\ + parameter logic [${field_msb}:0] ${field_resname(reg, field)} = ${field_resval}; + % endif + % endfor + % endfor +% endif +\ +<%def name="windows_for_iface(iface_name, iface_desc, for_iface, rb)">\ +% if rb.windows: +<% + aw_name, aw = addr_widths[iface_name] +%>\ + + // Window parameters${for_iface} +% for i,w in enumerate(rb.windows): +<% + win_pfx = '{}_{}'.format(ublock, w.name.upper()) + base_txt_val = "{}'h {:x}".format(aw, w.offset) + size_txt_val = "'h {:x}".format(w.size_in_bytes) + + offset_type = 'logic [{}-1:0]'.format(aw_name) + size_type = 'int unsigned' + max_type_len = max(len(offset_type), len(size_type)) + + offset_type += ' ' * (max_type_len - len(offset_type)) + size_type += ' ' * (max_type_len - len(size_type)) + +%>\ + parameter ${offset_type} ${win_pfx}_OFFSET = ${base_txt_val}; + parameter ${size_type} ${win_pfx}_SIZE = ${size_txt_val}; +% endfor +% endif +\ +<%def name="reg_data_for_iface(iface_name, iface_desc, for_iface, rb)">\ +% if rb.flat_regs: +<% + lpfx = gen_rtl.get_type_name_pfx(block, iface_name) + upfx = lpfx.upper() + idx_len = len("{}".format(len(rb.flat_regs) - 1)) +%>\ + + // Register index${for_iface} + typedef enum int { +% for r in rb.flat_regs: + ${ublock}_${r.name.upper()}${"" if loop.last else ","} +% endfor + } ${lpfx}_id_e; + + // Register width information to check illegal writes${for_iface} + parameter logic [3:0] ${upfx}_PERMIT [${len(rb.flat_regs)}] = '{ + % for i, r in enumerate(rb.flat_regs): +<% + index_str = "{}".format(i).rjust(idx_len) + width = r.get_width() + if width > 24: + mask = '1111' + elif width > 16: + mask = '0111' + elif width > 8: + mask = '0011' + else: + mask = '0001' + + comma = ',' if i < len(rb.flat_regs) - 1 else ' ' +%>\ + 4'b ${mask}${comma} // index[${index_str}] ${ublock}_${r.name.upper()} + % endfor + }; +% endif +\ + +package ${lblock}_reg_pkg; +% if localparams: + + // Param list +% for param in localparams: + parameter ${param.param_type} ${param.name} = ${param.value}; +% endfor +% endif + + // Address widths within the block +% for param_name, width in addr_widths.values(): + parameter int ${param_name} = ${width}; +% endfor +<% + just_default = len(block.reg_blocks) == 1 and None in block.reg_blocks +%>\ +% for iface_name, rb in block.reg_blocks.items(): +<% + iface_desc = iface_name or 'default' + for_iface = '' if just_default else ' for {} interface'.format(iface_desc) +%>\ +${typedefs_for_iface(iface_name, iface_desc, for_iface, rb)}\ +${reg2hw_for_iface(iface_name, iface_desc, for_iface, rb)}\ +${hw2reg_for_iface(iface_name, iface_desc, for_iface, rb)}\ +${offsets_for_iface(iface_name, iface_desc, for_iface, rb)}\ +${hwext_resvals_for_iface(iface_name, iface_desc, for_iface, rb)}\ +${windows_for_iface(iface_name, iface_desc, for_iface, rb)}\ +${reg_data_for_iface(iface_name, iface_desc, for_iface, rb)}\ +% endfor + +endpackage + diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/reg_top.sv.tpl b/hw/vendored_ips/gpio/util/reggen/reggen/reg_top.sv.tpl new file mode 100644 index 00000000..3e14b553 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/reg_top.sv.tpl @@ -0,0 +1,795 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` +<% + from reggen import gen_rtl + from reggen.access import HwAccess, SwRdAccess, SwWrAccess + from reggen.lib import get_basename + from reggen.register import Register + from reggen.multi_register import MultiRegister + from reggen.ip_block import IpBlock + from reggen.bus_interfaces import BusProtocol + + num_wins = len(rb.windows) + num_wins_width = ((num_wins+1).bit_length()) - 1 + num_reg_dsp = 1 if rb.all_regs else 0 + num_dsp = num_wins + num_reg_dsp + regs_flat = rb.flat_regs + max_regs_char = len("{}".format(len(regs_flat) - 1)) + addr_width = rb.get_addr_width() + + # Used for the dev_select_i signal on a tlul_socket_1n with N = + # num_wins + 1. This needs to be able to represent any value up to + # N-1. + steer_msb = ((num_wins).bit_length()) - 1 + + lblock = block.name.lower() + ublock = lblock.upper() + + u_mod_base = mod_base.upper() + + reg2hw_t = gen_rtl.get_iface_tx_type(block, if_name, False) + hw2reg_t = gen_rtl.get_iface_tx_type(block, if_name, True) + + # Calculate whether we're going to need an AW parameter. We use it if there + # are any registers (obviously). We also use it if there are any windows that + # don't start at zero and end at 1 << addr_width (see the "addr_checks" + # calculation below for where that comes from). + needs_aw = (bool(regs_flat) or + num_wins > 1 or + rb.windows and ( + rb.windows[0].offset != 0 or + rb.windows[0].size_in_bytes != (1 << addr_width))) + + # Check if the interface protocol is reg_interface + use_reg_iface = any([interface['protocol'] == BusProtocol.REG_IFACE and not interface['is_host'] for interface in block.bus_interfaces.interface_list]) + reg_intf_req = "reg_req_t" + reg_intf_rsp = "reg_rsp_t" + + common_data_intg_gen = 0 if rb.has_data_intg_passthru else 1 + adapt_data_intg_gen = 1 if rb.has_data_intg_passthru else 0 + assert common_data_intg_gen != adapt_data_intg_gen +%> + +% if use_reg_iface: +`include "common_cells/assertions.svh" +% else: +`include "prim_assert.sv" +% endif + +module ${mod_name} \ +% if use_reg_iface: +#( + parameter type reg_req_t = logic, + parameter type reg_rsp_t = logic, + parameter int AW = ${addr_width} +) \ +% else: + % if needs_aw: +#( + parameter int AW = ${addr_width} +) \ + % endif +% endif +( + input logic clk_i, + input logic rst_ni, +% if use_reg_iface: + input ${reg_intf_req} reg_req_i, + output ${reg_intf_rsp} reg_rsp_o, +% else: + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, +% endif +% if num_wins != 0: + + // Output port for window +% if use_reg_iface: + output ${reg_intf_req} [${num_wins}-1:0] reg_req_win_o, + input ${reg_intf_rsp} [${num_wins}-1:0] reg_rsp_win_i, +% else: + output tlul_pkg::tl_h2d_t tl_win_o [${num_wins}], + input tlul_pkg::tl_d2h_t tl_win_i [${num_wins}], +% endif + +% endif + // To HW +% if rb.get_n_bits(["q","qe","re"]): + output ${lblock}_reg_pkg::${reg2hw_t} reg2hw, // Write +% endif +% if rb.get_n_bits(["d","de"]): + input ${lblock}_reg_pkg::${hw2reg_t} hw2reg, // Read +% endif + +% if not use_reg_iface: + // Integrity check errors + output logic intg_err_o, +% endif + + // Config + input devmode_i // If 1, explicit error return for unmapped register access +); + + import ${lblock}_reg_pkg::* ; + +% if rb.all_regs: + localparam int DW = ${block.regwidth}; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + +% if use_reg_iface: + // Below register interface can be changed + reg_req_t reg_intf_req; + reg_rsp_t reg_intf_rsp; +% else: + tlul_pkg::tl_h2d_t tl_reg_h2d; + tlul_pkg::tl_d2h_t tl_reg_d2h; +% endif +% endif + +% if not use_reg_iface: + // incoming payload check + logic intg_err; + tlul_cmd_intg_chk u_chk ( + .tl_i, + .err_o(intg_err) + ); + + logic intg_err_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + intg_err_q <= '0; + end else if (intg_err) begin + intg_err_q <= 1'b1; + end + end + + // integrity error output is permanent and should be used for alert generation + // register errors are transactional + assign intg_err_o = intg_err_q | intg_err; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(${common_data_intg_gen}) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o + ); +% endif + +% if num_dsp == 1: + ## Either no windows (and just registers) or no registers and only + ## one window. + % if num_wins == 0: + % if use_reg_iface: + assign reg_intf_req = reg_req_i; + assign reg_rsp_o = reg_intf_rsp; + % else: + assign tl_reg_h2d = tl_i; + assign tl_o_pre = tl_reg_d2h; + % endif + % else: + % if use_reg_iface: + assign reg_req_win_o = reg_req_i; + assign reg_rsp_o = reg_rsp_win_i + % else: + assign tl_win_o[0] = tl_i; + assign tl_o_pre = tl_win_i[0]; + % endif + % endif +% else: + logic [${steer_msb}:0] reg_steer; + + % if use_reg_iface: + ${reg_intf_req} [${num_dsp}-1:0] reg_intf_demux_req; + ${reg_intf_rsp} [${num_dsp}-1:0] reg_intf_demux_rsp; + + // demux connection + assign reg_intf_req = reg_intf_demux_req[${num_wins}]; + assign reg_intf_demux_rsp[${num_wins}] = reg_intf_rsp; + + % for i in range(num_wins): + assign reg_req_win_o[${i}] = reg_intf_demux_req[${i}]; + assign reg_intf_demux_rsp[${i}] = reg_rsp_win_i[${i}]; + % endfor + + // Create Socket_1n + reg_demux #( + .NoPorts (${num_dsp}), + .req_t (${reg_intf_req}), + .rsp_t (${reg_intf_rsp}) + ) i_reg_demux ( + .clk_i, + .rst_ni, + .in_req_i (reg_req_i), + .in_rsp_o (reg_rsp_o), + .out_req_o (reg_intf_demux_req), + .out_rsp_i (reg_intf_demux_rsp), + .in_select_i (reg_steer) + ); + + % else: + tlul_pkg::tl_h2d_t tl_socket_h2d [${num_dsp}]; + tlul_pkg::tl_d2h_t tl_socket_d2h [${num_dsp}]; + + // socket_1n connection + % if rb.all_regs: + assign tl_reg_h2d = tl_socket_h2d[${num_wins}]; + assign tl_socket_d2h[${num_wins}] = tl_reg_d2h; + + % endif + % for i,t in enumerate(rb.windows): + assign tl_win_o[${i}] = tl_socket_h2d[${i}]; + % if common_data_intg_gen == 0 and rb.windows[i].data_intg_passthru == False: + ## If there are multiple windows, and not every window has data integrity + ## passthrough, we must generate data integrity for it here. + tlul_rsp_intg_gen #( + .EnableRspIntgGen(0), + .EnableDataIntgGen(1) + ) u_win${i}_data_intg_gen ( + .tl_i(tl_win_i[${i}]), + .tl_o(tl_socket_d2h[${i}]) + ); + % else: + assign tl_socket_d2h[${i}] = tl_win_i[${i}]; + % endif + % endfor + + // Create Socket_1n + tlul_socket_1n #( + .N (${num_dsp}), + .HReqPass (1'b1), + .HRspPass (1'b1), + .DReqPass ({${num_dsp}{1'b1}}), + .DRspPass ({${num_dsp}{1'b1}}), + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth ({${num_dsp}{4'h0}}), + .DRspDepth ({${num_dsp}{4'h0}}) + ) u_socket ( + .clk_i, + .rst_ni, + .tl_h_i (tl_i), + .tl_h_o (tl_o_pre), + .tl_d_o (tl_socket_h2d), + .tl_d_i (tl_socket_d2h), + .dev_select_i (reg_steer) + ); + % endif + + // Create steering logic + always_comb begin + reg_steer = ${num_dsp-1}; // Default set to register + + // TODO: Can below codes be unique case () inside ? + % for i,w in enumerate(rb.windows): +<% + base_addr = w.offset + limit_addr = w.offset + w.size_in_bytes + if use_reg_iface: + hi_check = 'reg_req_i.addr[AW-1:0] < {}'.format(limit_addr) + else: + hi_check = 'tl_i.a_address[AW-1:0] < {}'.format(limit_addr) + addr_checks = [] + if base_addr > 0: + if use_reg_iface: + addr_checks.append('reg_req_i.addr[AW-1:0] >= {}'.format(base_addr)) + else: + addr_checks.append('tl_i.a_address[AW-1:0] >= {}'.format(base_addr)) + if limit_addr < 2**addr_width: + if use_reg_iface: + addr_checks.append('reg_req_i.addr[AW-1:0] < {}'.format(limit_addr)) + else: + addr_checks.append('tl_i.a_address[AW-1:0] < {}'.format(limit_addr)) + + addr_test = ' && '.join(addr_checks) +%>\ + % if addr_test: + if (${addr_test}) begin + % endif + reg_steer = ${i}; + % if addr_test: + end + % endif + % endfor + % if not use_reg_iface: + if (intg_err) begin + reg_steer = ${num_dsp-1}; + end + % endif + end +% endif +% if rb.all_regs: + + +% if use_reg_iface: + assign reg_we = reg_intf_req.valid & reg_intf_req.write; + assign reg_re = reg_intf_req.valid & ~reg_intf_req.write; + assign reg_addr = reg_intf_req.addr; + assign reg_wdata = reg_intf_req.wdata; + assign reg_be = reg_intf_req.wstrb; + assign reg_intf_rsp.rdata = reg_rdata; + assign reg_intf_rsp.error = reg_error; + assign reg_intf_rsp.ready = 1'b1; +% else: + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW), + .EnableDataIntgGen(${adapt_data_intg_gen}) + ) u_reg_if ( + .clk_i, + .rst_ni, + + .tl_i (tl_reg_h2d), + .tl_o (tl_reg_d2h), + + .we_o (reg_we), + .re_o (reg_re), + .addr_o (reg_addr), + .wdata_o (reg_wdata), + .be_o (reg_be), + .rdata_i (reg_rdata), + .error_i (reg_error) + ); +% endif + + assign reg_rdata = reg_rdata_next ; +% if use_reg_iface: + assign reg_error = (devmode_i & addrmiss) | wr_err; +% else: + assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err; +% endif + + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + % for r in regs_flat: + % if len(r.fields) == 1: +${sig_gen(r.fields[0], r.name.lower(), r.hwext, r.shadowed)}\ + % else: + % for f in r.fields: +${sig_gen(f, r.name.lower() + "_" + f.name.lower(), r.hwext, r.shadowed)}\ + % endfor + % endif + % endfor + + // Register instances + % for r in rb.all_regs: + ######################## multiregister ########################### + % if isinstance(r, MultiRegister): +<% + k = 0 +%> + % for sr in r.regs: + // Subregister ${k} of Multireg ${r.reg.name.lower()} + // R[${sr.name.lower()}]: V(${str(sr.hwext)}) + % if len(sr.fields) == 1: +<% + f = sr.fields[0] + finst_name = sr.name.lower() + fsig_name = r.reg.name.lower() + "[%d]" % k + k = k + 1 +%> +${finst_gen(f, finst_name, fsig_name, sr.hwext, sr.regwen, sr.shadowed)} + % else: + % for f in sr.fields: +<% + finst_name = sr.name.lower() + "_" + f.name.lower() + if r.is_homogeneous(): + fsig_name = r.reg.name.lower() + "[%d]" % k + k = k + 1 + else: + fsig_name = r.reg.name.lower() + "[%d]" % k + "." + get_basename(f.name.lower()) +%> + // F[${f.name.lower()}]: ${f.bits.msb}:${f.bits.lsb} +${finst_gen(f, finst_name, fsig_name, sr.hwext, sr.regwen, sr.shadowed)} + % endfor +<% + if not r.is_homogeneous(): + k += 1 +%> + % endif + ## for: mreg_flat + % endfor +######################## register with single field ########################### + % elif len(r.fields) == 1: + // R[${r.name.lower()}]: V(${str(r.hwext)}) +<% + f = r.fields[0] + finst_name = r.name.lower() + fsig_name = r.name.lower() +%> +${finst_gen(f, finst_name, fsig_name, r.hwext, r.regwen, r.shadowed)} +######################## register with multiple fields ########################### + % else: + // R[${r.name.lower()}]: V(${str(r.hwext)}) + % for f in r.fields: +<% + finst_name = r.name.lower() + "_" + f.name.lower() + fsig_name = r.name.lower() + "." + f.name.lower() +%> + // F[${f.name.lower()}]: ${f.bits.msb}:${f.bits.lsb} +${finst_gen(f, finst_name, fsig_name, r.hwext, r.regwen, r.shadowed)} + % endfor + % endif + + ## for: rb.all_regs + % endfor + + + logic [${len(regs_flat)-1}:0] addr_hit; + always_comb begin + addr_hit = '0; + % for i,r in enumerate(regs_flat): + addr_hit[${"{}".format(i).rjust(max_regs_char)}] = (reg_addr == ${ublock}_${r.name.upper()}_OFFSET); + % endfor + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + +% if regs_flat: +<% + # We want to signal wr_err if reg_be (the byte enable signal) is true for + # any bytes that aren't supported by a register. That's true if a + # addr_hit[i] and a bit is set in reg_be but not in *_PERMIT[i]. + + wr_err_terms = ['(addr_hit[{idx}] & (|({mod}_PERMIT[{idx}] & ~reg_be)))' + .format(idx=str(i).rjust(max_regs_char), + mod=u_mod_base) + for i in range(len(regs_flat))] + wr_err_expr = (' |\n' + (' ' * 15)).join(wr_err_terms) +%>\ + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + (${wr_err_expr})); + end +% else: + assign wr_error = 1'b0; +% endif\ + + % for i, r in enumerate(regs_flat): + % if len(r.fields) == 1: +${we_gen(r.fields[0], r.name.lower(), r.hwext, r.shadowed, i)}\ + % else: + % for f in r.fields: +${we_gen(f, r.name.lower() + "_" + f.name.lower(), r.hwext, r.shadowed, i)}\ + % endfor + % endif + % endfor + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + % for i, r in enumerate(regs_flat): + % if len(r.fields) == 1: + addr_hit[${i}]: begin +${rdata_gen(r.fields[0], r.name.lower())}\ + end + + % else: + addr_hit[${i}]: begin + % for f in r.fields: +${rdata_gen(f, r.name.lower() + "_" + f.name.lower())}\ + % endfor + end + + % endif + % endfor + default: begin + reg_rdata_next = '1; + end + endcase + end +% endif + + // Unused signal tieoff +% if rb.all_regs: + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; +% else: + // devmode_i is not used if there are no registers + logic unused_devmode; + assign unused_devmode = ^devmode_i; +% endif +% if rb.all_regs: + + // Assertions for Register Interface +% if not use_reg_iface: + `ASSERT_PULSE(wePulse, reg_we) + `ASSERT_PULSE(rePulse, reg_re) + + `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid) + + // this is formulated as an assumption such that the FPV testbenches do disprove this + // property by mistake + //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) +% endif + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit)) + +% endif +endmodule + +% if use_reg_iface: +module ${mod_name}_intf +#( + parameter int AW = ${addr_width}, + localparam int DW = ${block.regwidth} +) ( + input logic clk_i, + input logic rst_ni, + REG_BUS.in regbus_slave, +% if num_wins != 0: + REG_BUS.out regbus_win_mst[${num_wins}-1:0], +% endif + // To HW +% if rb.get_n_bits(["q","qe","re"]): + output ${lblock}_reg_pkg::${reg2hw_t} reg2hw, // Write +% endif +% if rb.get_n_bits(["d","de"]): + input ${lblock}_reg_pkg::${hw2reg_t} hw2reg, // Read +% endif + // Config + input devmode_i // If 1, explicit error return for unmapped register access +); + localparam int unsigned STRB_WIDTH = DW/8; + +`include "register_interface/typedef.svh" +`include "register_interface/assign.svh" + + // Define structs for reg_bus + typedef logic [AW-1:0] addr_t; + typedef logic [DW-1:0] data_t; + typedef logic [STRB_WIDTH-1:0] strb_t; + `REG_BUS_TYPEDEF_ALL(reg_bus, addr_t, data_t, strb_t) + + reg_bus_req_t s_reg_req; + reg_bus_rsp_t s_reg_rsp; + + // Assign SV interface to structs + `REG_BUS_ASSIGN_TO_REQ(s_reg_req, regbus_slave) + `REG_BUS_ASSIGN_FROM_RSP(regbus_slave, s_reg_rsp) + +% if num_wins != 0: + reg_bus_req_t s_reg_win_req[${num_wins}-1:0]; + reg_bus_rsp_t s_reg_win_rsp[${num_wins}-1:0]; + for (genvar i = 0; i < ${num_wins}; i++) begin : gen_assign_window_structs + `REG_BUS_ASSIGN_TO_REQ(s_reg_win_req[i], regbus_win_mst[i]) + `REG_BUS_ASSIGN_FROM_RSP(regbus_win_mst[i], s_reg_win_rsp[i]) + end + +% endif + + + ${mod_name} #( + .reg_req_t(reg_bus_req_t), + .reg_rsp_t(reg_bus_rsp_t), + .AW(AW) + ) i_regs ( + .clk_i, + .rst_ni, + .reg_req_i(s_reg_req), + .reg_rsp_o(s_reg_rsp), +% if num_wins != 0: + .reg_req_win_o(s_reg_win_req), + .reg_rsp_win_i(s_reg_win_rsp), +% endif +% if rb.get_n_bits(["q","qe","re"]): + .reg2hw, // Write +% endif +% if rb.get_n_bits(["d","de"]): + .hw2reg, // Read +% endif + .devmode_i + ); + +endmodule + +% endif + +<%def name="str_bits_sv(bits)">\ +% if bits.msb != bits.lsb: +${bits.msb}:${bits.lsb}\ +% else: +${bits.msb}\ +% endif +\ +<%def name="str_arr_sv(bits)">\ +% if bits.msb != bits.lsb: +[${bits.msb-bits.lsb}:0] \ +% endif +\ +<%def name="sig_gen(field, sig_name, hwext, shadowed)">\ + % if field.swaccess.allows_read(): + logic ${str_arr_sv(field.bits)}${sig_name}_qs; + % endif + % if field.swaccess.allows_write(): + logic ${str_arr_sv(field.bits)}${sig_name}_wd; + logic ${sig_name}_we; + % endif + % if (field.swaccess.allows_read() and hwext) or shadowed: + logic ${sig_name}_re; + % endif +\ +<%def name="finst_gen(field, finst_name, fsig_name, hwext, regwen, shadowed)">\ + % if hwext: ## if hwext, instantiate prim_subreg_ext + prim_subreg_ext #( + .DW (${field.bits.width()}) + ) u_${finst_name} ( + % if field.swaccess.allows_read(): + .re (${finst_name}_re), + % else: + .re (1'b0), + % endif + % if field.swaccess.allows_write(): + % if regwen: + // qualified with register enable + .we (${finst_name}_we & ${regwen.lower()}_qs), + % else: + .we (${finst_name}_we), + % endif + .wd (${finst_name}_wd), + % else: + .we (1'b0), + .wd ('0), + % endif + % if field.hwaccess.allows_write(): + .d (hw2reg.${fsig_name}.d), + % else: + .d ('0), + % endif + % if field.hwre or shadowed: + .qre (reg2hw.${fsig_name}.re), + % else: + .qre (), + % endif + % if not field.hwaccess.allows_read(): + .qe (), + .q (), + % else: + % if field.hwqe: + .qe (reg2hw.${fsig_name}.qe), + % else: + .qe (), + % endif + .q (reg2hw.${fsig_name}.q ), + % endif + % if field.swaccess.allows_read(): + .qs (${finst_name}_qs) + % else: + .qs () + % endif + ); + % else: ## if not hwext, instantiate prim_subreg, prim_subreg_shadow or constant assign + % if ((not field.hwaccess.allows_read() and\ + not field.hwaccess.allows_write() and\ + field.swaccess.swrd() == SwRdAccess.RD and\ + not field.swaccess.allows_write())): + // constant-only read + assign ${finst_name}_qs = ${field.bits.width()}'h${"%x" % (field.resval or 0)}; + % else: ## not hwext not constant + % if not shadowed: + prim_subreg #( + % else: + prim_subreg_shadow #( + % endif + .DW (${field.bits.width()}), + .SWACCESS("${field.swaccess.value[1].name.upper()}"), + .RESVAL (${field.bits.width()}'h${"%x" % (field.resval or 0)}) + ) u_${finst_name} ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + % if shadowed: + .re (${finst_name}_re), + % endif + % if field.swaccess.allows_write(): ## non-RO types + % if regwen: + // from register interface (qualified with register enable) + .we (${finst_name}_we & ${regwen.lower()}_qs), + % else: + // from register interface + .we (${finst_name}_we), + % endif + .wd (${finst_name}_wd), + % else: ## RO types + .we (1'b0), + .wd ('0 ), + % endif + + // from internal hardware + % if field.hwaccess.allows_write(): + .de (hw2reg.${fsig_name}.de), + .d (hw2reg.${fsig_name}.d ), + % else: + .de (1'b0), + .d ('0 ), + % endif + + // to internal hardware + % if not field.hwaccess.allows_read(): + .qe (), + .q (), + % else: + % if field.hwqe: + .qe (reg2hw.${fsig_name}.qe), + % else: + .qe (), + % endif + .q (reg2hw.${fsig_name}.q ), + % endif + + % if not shadowed: + % if field.swaccess.allows_read(): + // to register interface (read) + .qs (${finst_name}_qs) + % else: + .qs () + % endif + % else: + % if field.swaccess.allows_read(): + // to register interface (read) + .qs (${finst_name}_qs), + % else: + .qs (), + % endif + + // Shadow register error conditions + .err_update (reg2hw.${fsig_name}.err_update ), + .err_storage (reg2hw.${fsig_name}.err_storage) + % endif + ); + % endif ## end non-constant prim_subreg + % endif +\ +<%def name="we_gen(field, sig_name, hwext, shadowed, idx)">\ +<% + needs_we = field.swaccess.allows_write() + needs_re = (field.swaccess.allows_read() and hwext) or shadowed + space = '\n' if needs_we or needs_re else '' +%>\ +${space}\ +% if needs_we: + % if field.swaccess.swrd() != SwRdAccess.RC: + assign ${sig_name}_we = addr_hit[${idx}] & reg_we & !reg_error; + assign ${sig_name}_wd = reg_wdata[${str_bits_sv(field.bits)}]; + % else: + ## Generate WE based on read request, read should clear + assign ${sig_name}_we = addr_hit[${idx}] & reg_re & !reg_error; + assign ${sig_name}_wd = '1; + % endif +% endif +% if needs_re: + assign ${sig_name}_re = addr_hit[${idx}] & reg_re & !reg_error; +% endif +\ +<%def name="rdata_gen(field, sig_name)">\ +% if field.swaccess.allows_read(): + reg_rdata_next[${str_bits_sv(field.bits)}] = ${sig_name}_qs; +% else: + reg_rdata_next[${str_bits_sv(field.bits)}] = '0; +% endif +\ diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/register.py b/hw/vendored_ips/gpio/util/reggen/reggen/register.py new file mode 100644 index 00000000..24f73d02 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/register.py @@ -0,0 +1,375 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +from typing import Dict, List, Optional + +from .access import SWAccess, HWAccess +from .field import Field +from .lib import (check_keys, check_str, check_name, check_bool, + check_list, check_str_list, check_int) +from .params import ReggenParams +from .reg_base import RegBase + +REQUIRED_FIELDS = { + 'name': ['s', "name of the register"], + 'desc': ['t', "description of the register"], + 'fields': ['l', "list of register field description groups"] +} + +OPTIONAL_FIELDS = { + 'swaccess': [ + 's', + "software access permission to use for " + "fields that don't specify swaccess" + ], + 'hwaccess': [ + 's', + "hardware access permission to use for " + "fields that don't specify hwaccess" + ], + 'hwext': [ + 's', + "'true' if the register is stored outside " + "of the register module" + ], + 'hwqe': [ + 's', + "'true' if hardware uses 'q' enable signal, " + "which is latched signal of software write pulse." + ], + 'hwre': [ + 's', + "'true' if hardware uses 're' signal, " + "which is latched signal of software read pulse." + ], + 'regwen': [ + 's', + "if register is write-protected by another register, that " + "register name should be given here. empty-string for no register " + "write protection" + ], + 'resval': [ + 'd', + "reset value of full register (default 0)" + ], + 'tags': [ + 's', + "tags for the register, following the format 'tag_name:item1:item2...'" + ], + 'shadowed': [ + 's', + "'true' if the register is shadowed" + ], + 'update_err_alert': [ + 's', + "alert that will be triggered if " + "this shadowed register has update error" + ], + 'storage_err_alert': [ + 's', + "alert that will be triggered if " + "this shadowed register has storage error" + ] +} + + +class Register(RegBase): + '''Code representing a register for reggen''' + def __init__(self, + offset: int, + name: str, + desc: str, + swaccess: SWAccess, + hwaccess: HWAccess, + hwext: bool, + hwqe: bool, + hwre: bool, + regwen: Optional[str], + tags: List[str], + resval: Optional[int], + shadowed: bool, + fields: List[Field], + update_err_alert: Optional[str], + storage_err_alert: Optional[str]): + super().__init__(offset) + self.name = name + self.desc = desc + + self.swaccess = swaccess + self.hwaccess = hwaccess + + self.hwext = hwext + if self.hwext and self.hwaccess.key == 'hro' and self.sw_readable(): + raise ValueError('hwext flag for {} register is set, but ' + 'hwaccess is hro and the register value ' + 'is readable by software mode ({}).' + .format(self.name, self.swaccess.key)) + + self.hwqe = hwqe + if self.hwext and not self.hwqe and self.sw_writable(): + raise ValueError('The {} register has hwext set and is writable ' + 'by software (mode {}), so must also have hwqe ' + 'enabled.' + .format(self.name, self.swaccess.key)) + + self.hwre = hwre + if self.hwre and not self.hwext: + raise ValueError('The {} register specifies hwre but not hwext.' + .format(self.name)) + + self.regwen = regwen + self.tags = tags + + self.shadowed = shadowed + sounds_shadowy = self.name.lower().endswith('_shadowed') + if self.shadowed and not sounds_shadowy: + raise ValueError("Register {} has the shadowed flag but its name " + "doesn't end with the _shadowed suffix." + .format(self.name)) + elif sounds_shadowy and not self.shadowed: + raise ValueError("Register {} has a name ending in _shadowed, but " + "the shadowed flag is not set." + .format(self.name)) + + # Take a copy of fields and then sort by bit index + assert fields + self.fields = fields.copy() + self.fields.sort(key=lambda field: field.bits.lsb) + + # Index fields by name and check for duplicates + self.name_to_field = {} # type: Dict[str, Field] + for field in self.fields: + if field.name in self.name_to_field: + raise ValueError('Register {} has duplicate fields called {}.' + .format(self.name, field.name)) + self.name_to_field[field.name] = field + + # Check that field bits are disjoint + bits_used = 0 + for field in self.fields: + field_mask = field.bits.bitmask() + if bits_used & field_mask: + raise ValueError('Register {} has non-disjoint fields: ' + '{} uses bits {:#x} used by other fields.' + .format(self.name, field.name, + bits_used & field_mask)) + + # Compute a reset value and mask from our constituent fields. + self.resval = 0 + self.resmask = 0 + for field in self.fields: + self.resval |= (field.resval or 0) << field.bits.lsb + self.resmask |= field.bits.bitmask() + + # If the register defined a reset value, make sure it matches. We've + # already checked that each field matches, but we still need to make + # sure there weren't any bits unaccounted for. + if resval is not None and self.resval != resval: + raise ValueError('Register {} specifies a reset value of {:#x} but ' + 'collecting reset values across its fields yields ' + '{:#x}.' + .format(self.name, resval, self.resval)) + + self.update_err_alert = update_err_alert + self.storage_err_alert = storage_err_alert + + @staticmethod + def from_raw(reg_width: int, + offset: int, + params: ReggenParams, + raw: object) -> 'Register': + rd = check_keys(raw, 'register', + list(REQUIRED_FIELDS.keys()), + list(OPTIONAL_FIELDS.keys())) + + name = check_name(rd['name'], 'name of register') + desc = check_str(rd['desc'], 'desc for {} register'.format(name)) + + swaccess = SWAccess('{} register'.format(name), + rd.get('swaccess', 'none')) + hwaccess = HWAccess('{} register'.format(name), + rd.get('hwaccess', 'hro')) + + hwext = check_bool(rd.get('hwext', False), + 'hwext flag for {} register'.format(name)) + + hwqe = check_bool(rd.get('hwqe', False), + 'hwqe flag for {} register'.format(name)) + + hwre = check_bool(rd.get('hwre', False), + 'hwre flag for {} register'.format(name)) + + raw_regwen = rd.get('regwen', '') + if not raw_regwen: + regwen = None + else: + regwen = check_name(raw_regwen, + 'regwen for {} register'.format(name)) + + tags = check_str_list(rd.get('tags', []), + 'tags for {} register'.format(name)) + + raw_resval = rd.get('resval') + if raw_resval is None: + resval = None + else: + resval = check_int(raw_resval, + 'resval for {} register'.format(name)) + if not 0 <= resval < (1 << reg_width): + raise ValueError('resval for {} register is {}, ' + 'not an unsigned {}-bit number.' + .format(name, resval, reg_width)) + + shadowed = check_bool(rd.get('shadowed', False), + 'shadowed flag for {} register' + .format(name)) + + raw_fields = check_list(rd['fields'], + 'fields for {} register'.format(name)) + if not raw_fields: + raise ValueError('Register {} has no fields.'.format(name)) + fields = [Field.from_raw(name, + idx, + len(raw_fields), + swaccess, + hwaccess, + resval, + reg_width, + hwqe, + hwre, + params, + rf) + for idx, rf in enumerate(raw_fields)] + + raw_uea = rd.get('update_err_alert') + if raw_uea is None: + update_err_alert = None + else: + update_err_alert = check_name(raw_uea, + 'update_err_alert for {} register' + .format(name)) + + raw_sea = rd.get('storage_err_alert') + if raw_sea is None: + storage_err_alert = None + else: + storage_err_alert = check_name(raw_sea, + 'storage_err_alert for {} register' + .format(name)) + + return Register(offset, name, desc, swaccess, hwaccess, + hwext, hwqe, hwre, regwen, + tags, resval, shadowed, fields, + update_err_alert, storage_err_alert) + + def next_offset(self, addrsep: int) -> int: + return self.offset + addrsep + + def sw_readable(self) -> bool: + return self.swaccess.key not in ['wo', 'r0w1c'] + + def sw_writable(self) -> bool: + return self.swaccess.key != 'ro' + + def dv_rights(self) -> str: + return self.swaccess.dv_rights() + + def get_n_bits(self, bittype: List[str]) -> int: + return sum(field.get_n_bits(self.hwext, bittype) + for field in self.fields) + + def get_field_list(self) -> List[Field]: + return self.fields + + def is_homogeneous(self) -> bool: + return len(self.fields) == 1 + + def get_width(self) -> int: + '''Get the width of the fields in the register in bits + + This counts dead space between and below fields, so it's calculated as + one more than the highest msb. + + ''' + # self.fields is ordered by (increasing) LSB, so we can find the MSB of + # the register by taking the MSB of the last field. + return 1 + self.fields[-1].bits.msb + + def make_multi(self, + reg_width: int, + offset: int, + creg_idx: int, + creg_count: int, + regwen_multi: bool, + compact: bool, + min_reg_idx: int, + max_reg_idx: int, + cname: str) -> 'Register': + '''Generate a numbered, packed version of the register''' + assert 0 <= creg_idx < creg_count + assert 0 <= min_reg_idx <= max_reg_idx + assert compact or (min_reg_idx == max_reg_idx) + + new_name = ('{}_{}'.format(self.name, creg_idx) + if creg_count > 1 + else self.name) + + if self.regwen is None or not regwen_multi or creg_count == 1: + new_regwen = self.regwen + else: + new_regwen = '{}_{}'.format(self.regwen, creg_idx) + + strip_field = creg_idx > 0 + + if compact: + # Compacting multiple registers into a single "compacted" register. + # This is only supported if we have exactly one field (checked at + # the call-site) + assert len(self.fields) == 1 + new_fields = self.fields[0].make_multi(reg_width, + min_reg_idx, max_reg_idx, + cname, creg_idx, + strip_field) + else: + # No compacting going on, but we still choose to rename the fields + # to match the registers + assert creg_idx == min_reg_idx + new_fields = [field.make_suffixed('_{}'.format(creg_idx), + cname, creg_idx, strip_field) + for field in self.fields] + + # Don't specify a reset value for the new register. Any reset value + # defined for the original register will have propagated to its fields, + # so when we combine them here, the Register constructor can compute a + # reset value for us (which might well be different from self.resval if + # we've replicated fields). + new_resval = None + + return Register(offset, new_name, self.desc, + self.swaccess, self.hwaccess, + self.hwext, self.hwqe, self.hwre, new_regwen, + self.tags, new_resval, self.shadowed, new_fields, + self.update_err_alert, self.storage_err_alert) + + def _asdict(self) -> Dict[str, object]: + rd = { + 'name': self.name, + 'desc': self.desc, + 'fields': self.fields, + 'swaccess': self.swaccess.key, + 'hwaccess': self.hwaccess.key, + 'hwext': str(self.hwext), + 'hwqe': str(self.hwqe), + 'hwre': str(self.hwre), + 'tags': self.tags, + 'shadowed': str(self.shadowed), + } + if self.regwen is not None: + rd['regwen'] = self.regwen + if self.update_err_alert is not None: + rd['update_err_alert'] = self.update_err_alert + if self.storage_err_alert is not None: + rd['storage_err_alert'] = self.storage_err_alert + + return rd diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/signal.py b/hw/vendored_ips/gpio/util/reggen/reggen/signal.py new file mode 100644 index 00000000..bd4d6a33 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/signal.py @@ -0,0 +1,63 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +from typing import Dict, Sequence + +from .bits import Bits +from .lib import check_keys, check_name, check_str, check_int, check_list + + +class Signal: + def __init__(self, name: str, desc: str, bits: Bits): + self.name = name + self.desc = desc + self.bits = bits + + @staticmethod + def from_raw(what: str, lsb: int, raw: object) -> 'Signal': + rd = check_keys(raw, what, + ['name', 'desc'], + ['width']) + + name = check_name(rd['name'], 'name field of ' + what) + desc = check_str(rd['desc'], 'desc field of ' + what) + width = check_int(rd.get('width', 1), 'width field of ' + what) + if width <= 0: + raise ValueError('The width field of signal {} ({}) ' + 'has value {}, but should be positive.' + .format(name, what, width)) + + bits = Bits(lsb + width - 1, lsb) + + return Signal(name, desc, bits) + + @staticmethod + def from_raw_list(what: str, raw: object) -> Sequence['Signal']: + lsb = 0 + ret = [] + for idx, entry in enumerate(check_list(raw, what)): + entry_what = 'entry {} of {}'.format(idx, what) + interrupt = Signal.from_raw(entry_what, lsb, entry) + ret.append(interrupt) + lsb += interrupt.bits.width() + return ret + + def _asdict(self) -> Dict[str, object]: + return { + 'name': self.name, + 'desc': self.desc, + 'width': str(self.bits.width()) + } + + def as_nwt_dict(self, type_field: str) -> Dict[str, object]: + '''Return a view of the signal as a dictionary + + The dictionary has fields "name", "width" and "type", the last + of which comes from the type_field argument. Used for topgen + integration. + + ''' + return {'name': self.name, + 'width': self.bits.width(), + 'type': type_field} diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/uvm_reg.sv.tpl b/hw/vendored_ips/gpio/util/reggen/reggen/uvm_reg.sv.tpl new file mode 100644 index 00000000..9d8d9dc7 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/uvm_reg.sv.tpl @@ -0,0 +1,14 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// UVM Registers auto-generated by `reggen` containing data structure +## +## +## We use functions from uvm_reg_base.sv.tpl to define +## per-device-interface code. +## +<%namespace file="uvm_reg_base.sv.tpl" import="*"/>\ +## +## +${make_ral_pkg(dv_base_prefix, block.regwidth, reg_block_path, rb, esc_if_name)} diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/uvm_reg_base.sv.tpl b/hw/vendored_ips/gpio/util/reggen/reggen/uvm_reg_base.sv.tpl new file mode 100644 index 00000000..d1da4f4f --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/uvm_reg_base.sv.tpl @@ -0,0 +1,431 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +<%! + from reggen import gen_dv + from reggen.access import HwAccess, SwRdAccess, SwWrAccess +%> +## +## +## make_ral_pkg +## ============ +## +## Generate the RAL package for a device interface. +## +## dv_base_prefix a string naming the base register type. If it is FOO, +## then we will inherit from FOO_reg (assumed to +## be a subclass of uvm_reg). +## +## reg_width an integer giving the width of registers in bits +## +## reg_block_path the hierarchical path to the relevant register block in the +## design +## +## rb a RegBlock object +## +## esc_if_name a string giving the full, escaped, interface name. For +## a device interface called FOO on block BAR, +## this will be bar__foo. For an unnamed interface +## on block BAR, this will be just bar. +## +<%def name="make_ral_pkg(dv_base_prefix, reg_width, reg_block_path, rb, esc_if_name)">\ +package ${esc_if_name}_ral_pkg; +${make_ral_pkg_hdr(dv_base_prefix, [])} + +${make_ral_pkg_fwd_decls(esc_if_name, rb.flat_regs, rb.windows)} +% for reg in rb.flat_regs: + +${make_ral_pkg_reg_class(dv_base_prefix, reg_width, esc_if_name, reg_block_path, reg)} +% endfor +% for window in rb.windows: + +${make_ral_pkg_window_class(dv_base_prefix, esc_if_name, window)} +% endfor + +<% + reg_block_name = gen_dv.bcname(esc_if_name) +%>\ + class ${reg_block_name} extends ${dv_base_prefix}_reg_block; +% if rb.flat_regs: + // registers +% for r in rb.flat_regs: + rand ${gen_dv.rcname(esc_if_name, r)} ${r.name.lower()}; +% endfor +% endif +% if rb.windows: + // memories +% for window in rb.windows: + rand ${gen_dv.mcname(esc_if_name, window)} ${gen_dv.miname(window)}; +% endfor +% endif + + `uvm_object_utils(${reg_block_name}) + + function new(string name = "${reg_block_name}", + int has_coverage = UVM_NO_COVERAGE); + super.new(name, has_coverage); + endfunction : new + + virtual function void build(uvm_reg_addr_t base_addr, + csr_excl_item csr_excl = null); + // create default map + this.default_map = create_map(.name("default_map"), + .base_addr(base_addr), + .n_bytes(${reg_width//8}), + .endian(UVM_LITTLE_ENDIAN)); + if (csr_excl == null) begin + csr_excl = csr_excl_item::type_id::create("csr_excl"); + this.csr_excl = csr_excl; + end +% if rb.flat_regs: + set_hdl_path_root("tb.dut", "BkdrRegPathRtl"); + set_hdl_path_root("tb.dut", "BkdrRegPathRtlCommitted"); + set_hdl_path_root("tb.dut", "BkdrRegPathRtlShadow"); + // create registers +% for r in rb.flat_regs: +<% + reg_name = r.name.lower() + reg_right = r.dv_rights() + reg_offset = "{}'h{:x}".format(reg_width, r.offset) + reg_tags = r.tags + reg_shadowed = r.shadowed + + type_id_indent = ' ' * (len(reg_name) + 4) +%>\ + ${reg_name} = (${gen_dv.rcname(esc_if_name, r)}:: + ${type_id_indent}type_id::create("${reg_name}")); + ${reg_name}.configure(.blk_parent(this)); + ${reg_name}.build(csr_excl); + default_map.add_reg(.rg(${reg_name}), + .offset(${reg_offset}), + .rights("${reg_right}")); +% if reg_shadowed: + ${reg_name}.set_is_shadowed(); +% endif +% if reg_tags: + // create register tags +% for reg_tag in reg_tags: +<% + tag = reg_tag.split(":") +%>\ +% if tag[0] == "excl": + csr_excl.add_excl(${reg_name}.get_full_name(), ${tag[2]}, ${tag[1]}); +% endif +% endfor +% endif +% endfor +<% + any_regwen = False + for r in rb.flat_regs: + if r.regwen: + any_regwen = True + break +%>\ +% if any_regwen: + // assign locked reg to its regwen reg +% for r in rb.flat_regs: +% if r.regwen: +% for reg in rb.flat_regs: +% if r.regwen.lower() == reg.name.lower(): + ${r.regwen.lower()}.add_lockable_reg_or_fld(${r.name.lower()}); +<% break %>\ +% elif reg.name.lower() in r.regwen.lower(): +% for field in reg.get_field_list(): +% if r.regwen.lower() == (reg.name.lower() + "_" + field.name.lower()): + ${r.regwen.lower()}.${field.name.lower()}.add_lockable_reg_or_fld(${r.name.lower()}); +<% break %>\ +% endif +% endfor +% endif +% endfor +% endif +% endfor +% endif +% endif +${make_ral_pkg_window_instances(reg_width, esc_if_name, rb)} + endfunction : build + endclass : ${reg_block_name} + +endpackage +\ +## +## +## make_ral_pkg_hdr +## ================ +## +## Generate the header for a RAL package +## +## dv_base_prefix as for make_ral_pkg +## +## deps a list of names for packages that should be explicitly +## imported +## +<%def name="make_ral_pkg_hdr(dv_base_prefix, deps)">\ + // dep packages + import uvm_pkg::*; + import dv_base_reg_pkg::*; +% if dv_base_prefix != "dv_base": + import ${dv_base_prefix}_reg_pkg::*; +% endif +% for dep in deps: + import ${dep}::*; +% endfor + + // macro includes + `include "uvm_macros.svh"\ +\ +## +## +## make_ral_pkg_fwd_decls +## ====================== +## +## Generate the forward declarations for a RAL package +## +## esc_if_name as for make_ral_pkg +## +## flat_regs a list of Register objects (expanding multiregs) +## +## windows a list of Window objects +## +<%def name="make_ral_pkg_fwd_decls(esc_if_name, flat_regs, windows)">\ + // Forward declare all register/memory/block classes +% for r in flat_regs: + typedef class ${gen_dv.rcname(esc_if_name, r)}; +% endfor +% for w in windows: + typedef class ${gen_dv.mcname(esc_if_name, w)}; +% endfor + typedef class ${gen_dv.bcname(esc_if_name)};\ +\ +## +## +## make_ral_pkg_reg_class +## ====================== +## +## Generate the classes for a register inside a RAL package +## +## dv_base_prefix as for make_ral_pkg +## +## reg_width as for make_ral_pkg +## +## esc_if_name as for make_ral_pkg +## +## reg_block_path as for make_ral_pkg +## +## reg a Register object +<%def name="make_ral_pkg_reg_class(dv_base_prefix, reg_width, esc_if_name, reg_block_path, reg)">\ +<% + reg_name = reg.name.lower() + + is_ext = reg.hwext + for field in reg.fields: + if (field.hwaccess.value[1] == HwAccess.NONE and + field.swaccess.swrd() == SwRdAccess.RD and + not field.swaccess.allows_write()): + is_ext = 1 + + class_name = gen_dv.rcname(esc_if_name, reg) +%>\ + class ${class_name} extends ${dv_base_prefix}_reg; + // fields +% for f in reg.fields: + rand ${dv_base_prefix}_reg_field ${f.name.lower()}; +% endfor + + `uvm_object_utils(${class_name}) + + function new(string name = "${class_name}", + int unsigned n_bits = ${reg_width}, + int has_coverage = UVM_NO_COVERAGE); + super.new(name, n_bits, has_coverage); + endfunction : new + + virtual function void build(csr_excl_item csr_excl = null); + // create fields +% for field in reg.fields: +<% + if len(reg.fields) == 1: + reg_field_name = reg_name + else: + reg_field_name = reg_name + "_" + field.name.lower() +%>\ +${_create_reg_field(dv_base_prefix, reg_width, reg_block_path, reg.shadowed, reg.hwext, reg_field_name, field)} +% endfor +% if reg.shadowed and reg.hwext: +<% + shadowed_reg_path = '' + for tag in reg.tags: + parts = tag.split(':') + if parts[0] == 'shadowed_reg_path': + shadowed_reg_path = parts[1] + + if not shadowed_reg_path: + print("ERROR: ext shadow_reg does not have tags for shadowed_reg_path!") + assert 0 + + bit_idx = reg.fields[-1].bits.msb + 1 + +%>\ + add_update_err_alert("${reg.update_err_alert}"); + add_storage_err_alert("${reg.storage_err_alert}"); + add_hdl_path_slice("${shadowed_reg_path}.committed_reg.q", + 0, ${bit_idx}, 0, "BkdrRegPathRtlCommitted"); + add_hdl_path_slice("${shadowed_reg_path}.shadow_reg.q", + 0, ${bit_idx}, 0, "BkdrRegPathRtlShadow"); +% endif +% if is_ext: + set_is_ext_reg(1); +% endif + endfunction : build + endclass : ${class_name}\ +\ +## +## +## _create_reg_field +## ================= +## +## Generate the code that creates a uvm_reg_field object for a field +## in a register. +## +## dv_base_prefix as for make_ral_pkg +## +## reg_width as for make_ral_pkg +## +## reg_block_path as for make_ral_pkg +## +## shadowed true if the field's register is shadowed +## +## hwext true if the field's register is hwext +## +## reg_field_name a string with the name to give the field in the HDL +## +## field a Field object +<%def name="_create_reg_field(dv_base_prefix, reg_width, reg_block_path, shadowed, hwext, reg_field_name, field)">\ +<% + field_size = field.bits.width() + if field.swaccess.key == "r0w1c": + field_access = "W1C" + else: + field_access = field.swaccess.value[1].name + + if not field.hwaccess.allows_write(): + field_volatile = 0 + else: + field_volatile = 1 + field_tags = field.tags + + fname = field.name.lower() + type_id_indent = ' ' * (len(fname) + 4) +%>\ + ${fname} = (${dv_base_prefix}_reg_field:: + ${type_id_indent}type_id::create("${fname}")); + ${fname}.configure( + .parent(this), + .size(${field_size}), + .lsb_pos(${field.bits.lsb}), + .access("${field_access}"), + .volatile(${field_volatile}), + .reset(${reg_width}'h${format(field.resval or 0, 'x')}), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + ${fname}.set_original_access("${field_access}"); +% if ((field.hwaccess.value[1] == HwAccess.NONE and\ + field.swaccess.swrd() == SwRdAccess.RD and\ + not field.swaccess.allows_write())): + // constant reg + add_hdl_path_slice("${reg_block_path}.${reg_field_name}_qs", + ${field.bits.lsb}, ${field_size}, 0, "BkdrRegPathRtl"); +% else: + add_hdl_path_slice("${reg_block_path}.u_${reg_field_name}.q${"s" if hwext else ""}", + ${field.bits.lsb}, ${field_size}, 0, "BkdrRegPathRtl"); +% endif +% if shadowed and not hwext: + add_hdl_path_slice("${reg_block_path}.u_${reg_field_name}.committed_reg.q", + ${field.bits.lsb}, ${field_size}, 0, "BkdrRegPathRtlCommitted"); + add_hdl_path_slice("${reg_block_path}.u_${reg_field_name}.shadow_reg.q", + ${field.bits.lsb}, ${field_size}, 0, "BkdrRegPathRtlShadow"); +% endif +% if field_tags: + // create field tags +% for field_tag in field_tags: +<% + tag = field_tag.split(":") +%>\ +% if tag[0] == "excl": + csr_excl.add_excl(${field.name.lower()}.get_full_name(), ${tag[2]}, ${tag[1]}); +% endif +% endfor +% endif +\ +## +## +## make_ral_pkg_window_class +## ========================= +## +## Generate the classes for a window inside a RAL package +## +## dv_base_prefix as for make_ral_pkg +## +## esc_if_name as for make_ral_pkg +## +## window a Window object +<%def name="make_ral_pkg_window_class(dv_base_prefix, esc_if_name, window)">\ +<% + mem_name = window.name.lower() + mem_right = window.swaccess.dv_rights() + mem_n_bits = window.validbits + mem_size = window.items + + class_name = gen_dv.mcname(esc_if_name, window) +%>\ + class ${class_name} extends ${dv_base_prefix}_mem; + + `uvm_object_utils(${class_name}) + + function new(string name = "${class_name}", + longint unsigned size = ${mem_size}, + int unsigned n_bits = ${mem_n_bits}, + string access = "${mem_right}", + int has_coverage = UVM_NO_COVERAGE); + super.new(name, size, n_bits, access, has_coverage); +% if window.byte_write: + set_mem_partial_write_support(1); +% endif + endfunction : new + + endclass : ${class_name} +\ +## +## +## make_ral_pkg_window_instances +## ============================= +## +## Generate the classes for a window inside a RAL package +## +## reg_width as for make_ral_pkg +## +## esc_if_name as for make_ral_pkg +## +## rb a RegBlock object +## +<%def name="make_ral_pkg_window_instances(reg_width, esc_if_name, rb)">\ +% if rb.windows: + + // create memories +% for w in rb.windows: +<% + mem_name = w.name.lower() + mem_right = w.swaccess.dv_rights() + mem_offset = "{}'h{:x}".format(reg_width, w.offset) + mem_n_bits = w.validbits + mem_size = w.items +%>\ + ${mem_name} = ${gen_dv.mcname(esc_if_name, w)}::type_id::create("${mem_name}"); + ${mem_name}.configure(.parent(this)); + default_map.add_mem(.mem(${mem_name}), + .offset(${mem_offset}), + .rights("${mem_right}")); +% endfor +% endif +\ diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/validate.py b/hw/vendored_ips/gpio/util/reggen/reggen/validate.py new file mode 100644 index 00000000..e1cea7fa --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/validate.py @@ -0,0 +1,155 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +""" +Register JSON validation +""" + +import logging as log + + +# validating version of int(x, 0) +# returns int value, error flag +# if error flag is True value will be zero +def check_int(x, err_prefix, suppress_err_msg=False): + if isinstance(x, int): + return x, False + if x[0] == '0' and len(x) > 2: + if x[1] in 'bB': + validch = '01' + elif x[1] in 'oO': + validch = '01234567' + elif x[1] in 'xX': + validch = '0123456789abcdefABCDEF' + else: + if not suppress_err_msg: + log.error(err_prefix + + ": int must start digit, 0b, 0B, 0o, 0O, 0x or 0X") + return 0, True + for c in x[2:]: + if c not in validch: + if not suppress_err_msg: + log.error(err_prefix + ": Bad character " + c + " in " + x) + return 0, True + else: + if not x.isdecimal(): + if not suppress_err_msg: + log.error(err_prefix + ": Number not valid int " + x) + return 0, True + return int(x, 0), False + + +def check_bool(x, err_prefix): + """check_bool checks if input 'x' is one of the list: + "true", "false" + + It returns value as Bool type and Error condition. + """ + if isinstance(x, bool): + # if Bool returns as it is + return x, False + if not x.lower() in ["true", "false"]: + log.error(err_prefix + ": Bad field value " + x) + return False, True + else: + return (x.lower() == "true"), False + + +def check_ln(obj, x, withwidth, err_prefix): + error = 0 + if not isinstance(obj[x], list): + log.error(err_prefix + ' element ' + x + ' not a list') + return 1 + for y in obj[x]: + error += check_keys(y, ln_required, ln_optional if withwidth else {}, + {}, err_prefix + ' element ' + x) + if withwidth: + if 'width' in y: + w, err = check_int(y['width'], err_prefix + ' width in ' + x) + if err: + error += 1 + w = 1 + else: + w = 1 + y['width'] = str(w) + + return error + + +def check_keys(obj, required_keys, optional_keys, added_keys, err_prefix): + error = 0 + for x in required_keys: + if x not in obj: + error += 1 + log.error(err_prefix + " missing required key " + x) + for x in obj: + type = None + if x in required_keys: + type = required_keys[x][0] + elif x in optional_keys: + type = optional_keys[x][0] + elif x not in added_keys: + log.warning(err_prefix + " contains extra key " + x) + if type is not None: + if type[:2] == 'ln': + error += check_ln(obj, x, type == 'lnw', err_prefix) + + return error + + +val_types = { + 'd': ["int", "integer (binary 0b, octal 0o, decimal, hex 0x)"], + 'x': ["xint", "x for undefined otherwise int"], + 'b': [ + "bitrange", "bit number as decimal integer, " + "or bit-range as decimal integers msb:lsb" + ], + 'l': ["list", "comma separated list enclosed in `[]`"], + 'ln': [ + "name list", 'comma separated list enclosed in `[]` of ' + 'one or more groups that have just name and dscr keys.' + ' e.g. `{ name: "name", desc: "description"}`' + ], + 'lnw': ["name list+", 'name list that optionally contains a width'], + 'lp': ["parameter list", 'parameter list having default value optionally'], + 'g': ["group", "comma separated group of key:value enclosed in `{}`"], + 'lg': [ + "list of group", "comma separated group of key:value enclosed in `{}`" + " the second entry of the list is the sub group format" + ], + 's': ["string", "string, typically short"], + 't': [ + "text", "string, may be multi-line enclosed in `'''` " + "may use `**bold**`, `*italic*` or `!!Reg` markup" + ], + 'T': ["tuple", "tuple enclosed in ()"], + 'pi': ["python int", "Native Python type int (generated)"], + 'pb': ["python Bool", "Native Python type Bool (generated)"], + 'pl': ["python list", "Native Python type list (generated)"], + 'pe': ["python enum", "Native Python type enum (generated)"] +} + +# ln type has list of groups with only name and description +# (was called "subunit" in cfg_validate) +ln_required = { + 'name': ['s', "name of the item"], + 'desc': ['s', "description of the item"], +} +ln_optional = { + 'width': ['d', "bit width of the item (if not 1)"], +} + +# Registers list may have embedded keys +list_optone = { + 'reserved': ['d', "number of registers to reserve space for"], + 'skipto': ['d', "set next register offset to value"], + 'window': [ + 'g', "group defining an address range " + "for something other than standard registers" + ], + 'multireg': + ['g', "group defining registers generated " + "from a base instance."] +} + +key_use = {'r': "required", 'o': "optional", 'a': "added by tool"} diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/version.py b/hw/vendored_ips/gpio/util/reggen/reggen/version.py new file mode 100644 index 00000000..3539c460 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/version.py @@ -0,0 +1,24 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +r"""Standard version printing +""" +import os +import subprocess +import sys + +import pkg_resources # part of setuptools + + +def show_and_exit(clitool, packages): + util_path = os.path.dirname(os.path.realpath(clitool)) + os.chdir(util_path) + ver = subprocess.run( + ["git", "describe", "--always", "--dirty", "--broken"], + stdout=subprocess.PIPE).stdout.strip().decode('ascii') + if (ver == ''): + ver = 'not found (not in Git repository?)' + sys.stderr.write(clitool + " Git version " + ver + '\n') + for p in packages: + sys.stderr.write(p + ' ' + pkg_resources.require(p)[0].version + '\n') + exit(0) diff --git a/hw/vendored_ips/gpio/util/reggen/reggen/window.py b/hw/vendored_ips/gpio/util/reggen/reggen/window.py new file mode 100644 index 00000000..d4355c88 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/reggen/window.py @@ -0,0 +1,169 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +from typing import Dict + +from .access import SWAccess +from .lib import check_keys, check_str, check_bool, check_int +from .params import ReggenParams + + +REQUIRED_FIELDS = { + 'name': ['s', "name of the window"], + 'desc': ['t', "description of the window"], + 'items': ['d', "size in fieldaccess width words of the window"], + 'swaccess': ['s', "software access permitted"], +} + +# TODO potential for additional optional to give more type info? +# eg sram-hw-port: "none", "sync", "async" +OPTIONAL_FIELDS = { + 'data-intg-passthru': [ + 's', "True if the window has data integrity pass through. " + "Defaults to false if not present." + ], + 'byte-write': [ + 's', "True if byte writes are supported. " + "Defaults to false if not present." + ], + 'validbits': [ + 'd', "Number of valid data bits within " + "regwidth sized word. " + "Defaults to regwidth. If " + "smaller than the regwidth then in each " + "word of the window bits " + "[regwidth-1:validbits] are unused and " + "bits [validbits-1:0] are valid." + ], + 'unusual': [ + 's', "True if window has unusual parameters " + "(set to prevent Unusual: errors)." + "Defaults to false if not present." + ] +} + + +class Window: + '''A class representing a memory window''' + def __init__(self, + name: str, + desc: str, + unusual: bool, + byte_write: bool, + data_intg_passthru: bool, + validbits: int, + items: int, + size_in_bytes: int, + offset: int, + swaccess: SWAccess): + assert 0 < validbits + assert 0 < items <= size_in_bytes + + self.name = name + self.desc = desc + self.unusual = unusual + self.byte_write = byte_write + self.data_intg_passthru = data_intg_passthru + self.validbits = validbits + self.items = items + self.size_in_bytes = size_in_bytes + self.offset = offset + self.swaccess = swaccess + + # Check that offset has been adjusted so that the first item in the + # window has all zeros in the low bits. + po2_size = 1 << (self.size_in_bytes - 1).bit_length() + assert not (offset & (po2_size - 1)) + + @staticmethod + def from_raw(offset: int, + reg_width: int, + params: ReggenParams, + raw: object) -> 'Window': + rd = check_keys(raw, 'window', + list(REQUIRED_FIELDS.keys()), + list(OPTIONAL_FIELDS.keys())) + + wind_desc = 'window at offset {:#x}'.format(offset) + name = check_str(rd['name'], wind_desc) + wind_desc = '{!r} {}'.format(name, wind_desc) + + desc = check_str(rd['desc'], 'desc field for ' + wind_desc) + + unusual = check_bool(rd.get('unusual', False), + 'unusual field for ' + wind_desc) + byte_write = check_bool(rd.get('byte-write', False), + 'byte-write field for ' + wind_desc) + data_intg_passthru = check_bool(rd.get('data-intg-passthru', False), + 'data-intg-passthru field for ' + wind_desc) + + validbits = check_int(rd.get('validbits', reg_width), + 'validbits field for ' + wind_desc) + if validbits <= 0: + raise ValueError('validbits field for {} is not positive.' + .format(wind_desc)) + if validbits > reg_width: + raise ValueError('validbits field for {} is {}, ' + 'which is greater than {}, the register width.' + .format(wind_desc, validbits, reg_width)) + + r_items = check_str(rd['items'], 'items field for ' + wind_desc) + items = params.expand(r_items, 'items field for ' + wind_desc) + if items <= 0: + raise ValueError("Items field for {} is {}, " + "which isn't positive." + .format(wind_desc, items)) + + assert reg_width % 8 == 0 + size_in_bytes = items * (reg_width // 8) + + # Round size_in_bytes up to the next power of 2. The calculation is + # like clog2 calculations in SystemVerilog, where we start with the + # last index, rather than the number of elements. + assert size_in_bytes > 0 + po2_size = 1 << (size_in_bytes - 1).bit_length() + + # A size that isn't a power of 2 is not allowed unless the unusual flag + # is set. + if po2_size != size_in_bytes and not unusual: + raise ValueError('Items field for {} is {}, which gives a size of ' + '{} bytes. This is not a power of 2 (next power ' + 'of 2 is {}). If you want to do this even so, ' + 'set the "unusual" flag.' + .format(wind_desc, items, + size_in_bytes, po2_size)) + + # Adjust offset if necessary to make sure the base address of the first + # item in the window has all zeros in the low bits. + addr_mask = po2_size - 1 + if offset & addr_mask: + offset = (offset | addr_mask) + 1 + offset = offset + + swaccess = SWAccess(wind_desc, rd['swaccess']) + if not (swaccess.value[4] or unusual): + raise ValueError('swaccess field for {} is {}, which is an ' + 'unusual access type for a window. If you want ' + 'to do this, set the "unusual" flag.' + .format(wind_desc, swaccess.key)) + + return Window(name, desc, unusual, byte_write, data_intg_passthru, + validbits, items, size_in_bytes, offset, swaccess) + + def next_offset(self, addrsep: int) -> int: + return self.offset + self.size_in_bytes + + def _asdict(self) -> Dict[str, object]: + rd = { + 'desc': self.desc, + 'items': self.items, + 'swaccess': self.swaccess.key, + 'byte-write': self.byte_write, + 'validbits': self.validbits, + 'unusual': self.unusual + } + if self.name is not None: + rd['name'] = self.name + + return {'window': rd} diff --git a/hw/vendored_ips/gpio/util/reggen/regtool.py b/hw/vendored_ips/gpio/util/reggen/regtool.py new file mode 100755 index 00000000..76268c9c --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/regtool.py @@ -0,0 +1,238 @@ +#!/usr/bin/env python3 +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +r"""Command-line tool to validate and convert register hjson + +""" +import argparse +import logging as log +import re +import sys +from pathlib import PurePath + +from reggen import (gen_cheader, gen_dv, gen_fpv, gen_html, + gen_json, gen_rtl, gen_selfdoc, version) +from reggen.ip_block import IpBlock + +DESC = """regtool, generate register info from Hjson source""" + +USAGE = ''' + regtool [options] + regtool [options] + regtool (-h | --help) + regtool (-V | --version) +''' + + +def main(): + verbose = 0 + + parser = argparse.ArgumentParser( + prog="regtool", + formatter_class=argparse.RawDescriptionHelpFormatter, + usage=USAGE, + description=DESC) + parser.add_argument('input', + nargs='?', + metavar='file', + type=argparse.FileType('r'), + default=sys.stdin, + help='input file in Hjson type') + parser.add_argument('-d', + action='store_true', + help='Output register documentation (html)') + parser.add_argument('--cdefines', + '-D', + action='store_true', + help='Output C defines header') + parser.add_argument('--doc', + action='store_true', + help='Output source file documentation (gfm)') + parser.add_argument('-j', + action='store_true', + help='Output as formatted JSON') + parser.add_argument('-c', action='store_true', help='Output as JSON') + parser.add_argument('-r', + action='store_true', + help='Output as SystemVerilog RTL') + parser.add_argument('-s', + action='store_true', + help='Output as UVM Register class') + parser.add_argument('-f', + action='store_true', + help='Output as FPV CSR rw assertion module') + parser.add_argument('--outdir', + '-t', + help='Target directory for generated RTL; ' + 'tool uses ../rtl if blank.') + parser.add_argument('--dv-base-prefix', + default='dv_base', + help='Prefix for the DV register classes from which ' + 'the register models are derived.') + parser.add_argument('--outfile', + '-o', + type=argparse.FileType('w'), + default=sys.stdout, + help='Target filename for json, html, gfm.') + parser.add_argument('--verbose', + '-v', + action='store_true', + help='Verbose and run validate twice') + parser.add_argument('--param', + '-p', + type=str, + default="", + help='''Change the Parameter values. + Only integer value is supported. + You can add multiple param arguments. + + Format: ParamA=ValA;ParamB=ValB + ''') + parser.add_argument('--version', + '-V', + action='store_true', + help='Show version') + parser.add_argument('--novalidate', + action='store_true', + help='Skip validate, just output json') + + args = parser.parse_args() + + if args.version: + version.show_and_exit(__file__, ["Hjson", "Mako"]) + + verbose = args.verbose + if (verbose): + log.basicConfig(format="%(levelname)s: %(message)s", level=log.DEBUG) + else: + log.basicConfig(format="%(levelname)s: %(message)s") + + # Entries are triples of the form (arg, (format, dirspec)). + # + # arg is the name of the argument that selects the format. format is the + # name of the format. dirspec is None if the output is a single file; if + # the output needs a directory, it is a default path relative to the source + # file (used when --outdir is not given). + arg_to_format = [('j', ('json', None)), ('c', ('compact', None)), + ('d', ('html', None)), ('doc', ('doc', None)), + ('r', ('rtl', 'rtl')), ('s', ('dv', 'dv')), + ('f', ('fpv', 'fpv/vip')), ('cdefines', ('cdh', None))] + format = None + dirspec = None + for arg_name, spec in arg_to_format: + if getattr(args, arg_name): + if format is not None: + log.error('Multiple output formats specified on ' + 'command line ({} and {}).'.format(format, spec[0])) + sys.exit(1) + format, dirspec = spec + if format is None: + format = 'hjson' + + infile = args.input + + # Split parameters into key=value pairs. + raw_params = args.param.split(';') if args.param else [] + params = [] + for idx, raw_param in enumerate(raw_params): + tokens = raw_param.split('=') + if len(tokens) != 2: + raise ValueError('Entry {} in list of parameter defaults to ' + 'apply is {!r}, which is not of the form ' + 'param=value.' + .format(idx, raw_param)) + params.append((tokens[0], tokens[1])) + + # Define either outfile or outdir (but not both), depending on the output + # format. + outfile = None + outdir = None + if dirspec is None: + if args.outdir is not None: + log.error('The {} format expects an output file, ' + 'not an output directory.'.format(format)) + sys.exit(1) + + outfile = args.outfile + else: + if args.outfile is not sys.stdout: + log.error('The {} format expects an output directory, ' + 'not an output file.'.format(format)) + sys.exit(1) + + if args.outdir is not None: + outdir = args.outdir + elif infile is not sys.stdin: + outdir = str(PurePath(infile.name).parents[1].joinpath(dirspec)) + else: + # We're using sys.stdin, so can't infer an output directory name + log.error( + 'The {} format writes to an output directory, which ' + 'cannot be inferred automatically if the input comes ' + 'from stdin. Use --outdir to specify it manually.'.format( + format)) + sys.exit(1) + + if format == 'doc': + with outfile: + gen_selfdoc.document(outfile) + exit(0) + + srcfull = infile.read() + + try: + obj = IpBlock.from_text(srcfull, params, infile.name) + except ValueError as err: + log.error(str(err)) + exit(1) + + if args.novalidate: + with outfile: + gen_json.gen_json(obj, outfile, format) + outfile.write('\n') + else: + if format == 'rtl': + return gen_rtl.gen_rtl(obj, outdir) + if format == 'dv': + return gen_dv.gen_dv(obj, args.dv_base_prefix, outdir) + if format == 'fpv': + return gen_fpv.gen_fpv(obj, outdir) + src_lic = None + src_copy = '' + found_spdx = None + found_lunder = None + copy = re.compile(r'.*(copyright.*)|(.*\(c\).*)', re.IGNORECASE) + spdx = re.compile(r'.*(SPDX-License-Identifier:.+)') + lunder = re.compile(r'.*(Licensed under.+)', re.IGNORECASE) + for line in srcfull.splitlines(): + mat = copy.match(line) + if mat is not None: + src_copy += mat.group(1) + mat = spdx.match(line) + if mat is not None: + found_spdx = mat.group(1) + mat = lunder.match(line) + if mat is not None: + found_lunder = mat.group(1) + if found_lunder: + src_lic = found_lunder + if found_spdx: + if src_lic is None: + src_lic = '\n' + found_spdx + else: + src_lic += '\n' + found_spdx + + with outfile: + if format == 'html': + return gen_html.gen_html(obj, outfile) + elif format == 'cdh': + return gen_cheader.gen_cdefines(obj, outfile, src_lic, src_copy) + else: + return gen_json.gen_json(obj, outfile, format) + + outfile.write('\n') + + +if __name__ == '__main__': + sys.exit(main()) diff --git a/hw/vendored_ips/gpio/util/reggen/topgen/__init__.py b/hw/vendored_ips/gpio/util/reggen/topgen/__init__.py new file mode 100644 index 00000000..d8a34008 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/topgen/__init__.py @@ -0,0 +1,8 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +from .lib import get_hjsonobj_xbars, search_ips # noqa: F401 +# noqa: F401 These functions are used in topgen.py +from .merge import amend_clocks, merge_top # noqa: F401 +from .validate import validate_top, check_flash # noqa: F401 diff --git a/hw/vendored_ips/gpio/util/reggen/topgen/c.py b/hw/vendored_ips/gpio/util/reggen/topgen/c.py new file mode 100644 index 00000000..58760a37 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/topgen/c.py @@ -0,0 +1,444 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +"""This contains a class which is used to help generate `top_{name}.h` and +`top_{name}.h`. +""" +from collections import OrderedDict +from typing import Dict, List, Optional, Tuple + +from mako.template import Template + +from .lib import get_base_and_size, Name + +from reggen.ip_block import IpBlock + + +class MemoryRegion(object): + def __init__(self, name: Name, base_addr: int, size_bytes: int): + assert isinstance(base_addr, int) + self.name = name + self.base_addr = base_addr + self.size_bytes = size_bytes + self.size_words = (size_bytes + 3) // 4 + + def base_addr_name(self): + return self.name + Name(["base", "addr"]) + + def offset_name(self): + return self.name + Name(["offset"]) + + def size_bytes_name(self): + return self.name + Name(["size", "bytes"]) + + def size_words_name(self): + return self.name + Name(["size", "words"]) + + +class CEnum(object): + def __init__(self, name): + self.name = name + self.enum_counter = 0 + self.finalized = False + + self.constants = [] + + def add_constant(self, constant_name, docstring=""): + assert not self.finalized + + full_name = self.name + constant_name + + value = self.enum_counter + self.enum_counter += 1 + + self.constants.append((full_name, value, docstring)) + + return full_name + + def add_last_constant(self, docstring=""): + assert not self.finalized + + full_name = self.name + Name(["last"]) + + _, last_val, _ = self.constants[-1] + + self.constants.append((full_name, last_val, r"\internal " + docstring)) + self.finalized = True + + def render(self): + template = ("typedef enum ${enum.name.as_snake_case()} {\n" + "% for name, value, docstring in enum.constants:\n" + " ${name.as_c_enum()} = ${value}, /**< ${docstring} */\n" + "% endfor\n" + "} ${enum.name.as_c_type()};") + return Template(template).render(enum=self) + + +class CArrayMapping(object): + def __init__(self, name, output_type_name): + self.name = name + self.output_type_name = output_type_name + + self.mapping = OrderedDict() + + def add_entry(self, in_name, out_name): + self.mapping[in_name] = out_name + + def render_declaration(self): + template = ( + "extern const ${mapping.output_type_name.as_c_type()}\n" + " ${mapping.name.as_snake_case()}[${len(mapping.mapping)}];") + return Template(template).render(mapping=self) + + def render_definition(self): + template = ( + "const ${mapping.output_type_name.as_c_type()}\n" + " ${mapping.name.as_snake_case()}[${len(mapping.mapping)}] = {\n" + "% for in_name, out_name in mapping.mapping.items():\n" + " [${in_name.as_c_enum()}] = ${out_name.as_c_enum()},\n" + "% endfor\n" + "};\n") + return Template(template).render(mapping=self) + + +class TopGenC: + def __init__(self, top_info, name_to_block: Dict[str, IpBlock]): + self.top = top_info + self._top_name = Name(["top"]) + Name.from_snake_case(top_info["name"]) + self._name_to_block = name_to_block + + # The .c file needs the .h file's relative path, store it here + self.header_path = None + + self._init_plic_targets() + self._init_plic_mapping() + self._init_alert_mapping() + self._init_pinmux_mapping() + self._init_pwrmgr_wakeups() + self._init_rstmgr_sw_rsts() + self._init_pwrmgr_reset_requests() + self._init_clkmgr_clocks() + + def devices(self) -> List[Tuple[Tuple[str, Optional[str]], MemoryRegion]]: + '''Return a list of MemoryRegion objects for devices on the bus + + The list returned is pairs (full_if, region) where full_if is itself a + pair (inst_name, if_name). inst_name is the name of some IP block + instantiation. if_name is the name of the interface (may be None). + region is a MemoryRegion object representing the device. + + ''' + ret = [] # type: List[Tuple[Tuple[str, Optional[str]], MemoryRegion]] + for inst in self.top['module']: + block = self._name_to_block[inst['type']] + for if_name, rb in block.reg_blocks.items(): + full_if = (inst['name'], if_name) + full_if_name = Name.from_snake_case(full_if[0]) + if if_name is not None: + full_if_name += Name.from_snake_case(if_name) + + name = self._top_name + full_if_name + base, size = get_base_and_size(self._name_to_block, + inst, if_name) + + region = MemoryRegion(name, base, size) + ret.append((full_if, region)) + + return ret + + def memories(self): + return [(m["name"], + MemoryRegion(self._top_name + Name.from_snake_case(m["name"]), + int(m["base_addr"], 0), + int(m["size"], 0))) + for m in self.top["memory"]] + + def _init_plic_targets(self): + enum = CEnum(self._top_name + Name(["plic", "target"])) + + for core_id in range(int(self.top["num_cores"])): + enum.add_constant(Name(["ibex", str(core_id)]), + docstring="Ibex Core {}".format(core_id)) + + enum.add_last_constant("Final PLIC target") + + self.plic_targets = enum + + def _init_plic_mapping(self): + """We eventually want to generate a mapping from interrupt id to the + source peripheral. + + In order to do so, we generate two enums (one for interrupts, one for + sources), and store the generated names in a dictionary that represents + the mapping. + + PLIC Interrupt ID 0 corresponds to no interrupt, and so no peripheral, + so we encode that in the enum as "unknown". + + The interrupts have to be added in order, with "none" first, to ensure + that they get the correct mapping to their PLIC id, which is used for + addressing the right registers and bits. + """ + sources = CEnum(self._top_name + Name(["plic", "peripheral"])) + interrupts = CEnum(self._top_name + Name(["plic", "irq", "id"])) + plic_mapping = CArrayMapping( + self._top_name + Name(["plic", "interrupt", "for", "peripheral"]), + sources.name) + + unknown_source = sources.add_constant(Name(["unknown"]), + docstring="Unknown Peripheral") + none_irq_id = interrupts.add_constant(Name(["none"]), + docstring="No Interrupt") + plic_mapping.add_entry(none_irq_id, unknown_source) + + # When we generate the `interrupts` enum, the only info we have about + # the source is the module name. We'll use `source_name_map` to map a + # short module name to the full name object used for the enum constant. + source_name_map = {} + + for name in self.top["interrupt_module"]: + source_name = sources.add_constant(Name.from_snake_case(name), + docstring=name) + source_name_map[name] = source_name + + sources.add_last_constant("Final PLIC peripheral") + + for intr in self.top["interrupt"]: + # Some interrupts are multiple bits wide. Here we deal with that by + # adding a bit-index suffix + if "width" in intr and int(intr["width"]) != 1: + for i in range(int(intr["width"])): + name = Name.from_snake_case(intr["name"]) + Name([str(i)]) + irq_id = interrupts.add_constant(name, + docstring="{} {}".format( + intr["name"], i)) + source_name = source_name_map[intr["module_name"]] + plic_mapping.add_entry(irq_id, source_name) + else: + name = Name.from_snake_case(intr["name"]) + irq_id = interrupts.add_constant(name, docstring=intr["name"]) + source_name = source_name_map[intr["module_name"]] + plic_mapping.add_entry(irq_id, source_name) + + interrupts.add_last_constant("The Last Valid Interrupt ID.") + + self.plic_sources = sources + self.plic_interrupts = interrupts + self.plic_mapping = plic_mapping + + def _init_alert_mapping(self): + """We eventually want to generate a mapping from alert id to the source + peripheral. + + In order to do so, we generate two enums (one for alerts, one for + sources), and store the generated names in a dictionary that represents + the mapping. + + Alert Handler has no concept of "no alert", unlike the PLIC. + + The alerts have to be added in order, to ensure that they get the + correct mapping to their alert id, which is used for addressing the + right registers and bits. + """ + sources = CEnum(self._top_name + Name(["alert", "peripheral"])) + alerts = CEnum(self._top_name + Name(["alert", "id"])) + alert_mapping = CArrayMapping( + self._top_name + Name(["alert", "for", "peripheral"]), + sources.name) + + # When we generate the `alerts` enum, the only info we have about the + # source is the module name. We'll use `source_name_map` to map a short + # module name to the full name object used for the enum constant. + source_name_map = {} + + for name in self.top["alert_module"]: + source_name = sources.add_constant(Name.from_snake_case(name), + docstring=name) + source_name_map[name] = source_name + + sources.add_last_constant("Final Alert peripheral") + + for alert in self.top["alert"]: + if "width" in alert and int(alert["width"]) != 1: + for i in range(int(alert["width"])): + name = Name.from_snake_case(alert["name"]) + Name([str(i)]) + irq_id = alerts.add_constant(name, + docstring="{} {}".format( + alert["name"], i)) + source_name = source_name_map[alert["module_name"]] + alert_mapping.add_entry(irq_id, source_name) + else: + name = Name.from_snake_case(alert["name"]) + alert_id = alerts.add_constant(name, docstring=alert["name"]) + source_name = source_name_map[alert["module_name"]] + alert_mapping.add_entry(alert_id, source_name) + + alerts.add_last_constant("The Last Valid Alert ID.") + + self.alert_sources = sources + self.alert_alerts = alerts + self.alert_mapping = alert_mapping + + def _init_pinmux_mapping(self): + """Generate C enums for addressing pinmux registers and in/out selects. + + Inputs/outputs are connected in the order the modules are listed in + the hjson under the "mio_modules" key. For each module, the corresponding + inouts are connected first, followed by either the inputs or the outputs. + + Inputs: + - Peripheral chooses register field (pinmux_peripheral_in) + - Insel chooses MIO input (pinmux_insel) + + Outputs: + - MIO chooses register field (pinmux_mio_out) + - Outsel chooses peripheral output (pinmux_outsel) + + Insel and outsel have some special values which are captured here too. + """ + pinmux_info = self.top['pinmux'] + pinout_info = self.top['pinout'] + + # Peripheral Inputs + peripheral_in = CEnum(self._top_name + + Name(['pinmux', 'peripheral', 'in'])) + i = 0 + for sig in pinmux_info['ios']: + if sig['connection'] == 'muxed' and sig['type'] in ['inout', 'input']: + index = Name([str(sig['idx'])]) if sig['idx'] != -1 else Name([]) + name = Name.from_snake_case(sig['name']) + index + peripheral_in.add_constant(name, docstring='Peripheral Input {}'.format(i)) + i += 1 + + peripheral_in.add_last_constant('Last valid peripheral input') + + # Pinmux Input Selects + insel = CEnum(self._top_name + Name(['pinmux', 'insel'])) + insel.add_constant(Name(['constant', 'zero']), + docstring='Tie constantly to zero') + insel.add_constant(Name(['constant', 'one']), + docstring='Tie constantly to one') + i = 0 + for pad in pinout_info['pads']: + if pad['connection'] == 'muxed': + insel.add_constant(Name([pad['name']]), + docstring='MIO Pad {}'.format(i)) + i += 1 + insel.add_last_constant('Last valid insel value') + + # MIO Outputs + mio_out = CEnum(self._top_name + Name(['pinmux', 'mio', 'out'])) + i = 0 + for pad in pinout_info['pads']: + if pad['connection'] == 'muxed': + mio_out.add_constant(Name.from_snake_case(pad['name']), + docstring='MIO Pad {}'.format(i)) + i += 1 + mio_out.add_last_constant('Last valid mio output') + + # Pinmux Output Selects + outsel = CEnum(self._top_name + Name(['pinmux', 'outsel'])) + outsel.add_constant(Name(['constant', 'zero']), + docstring='Tie constantly to zero') + outsel.add_constant(Name(['constant', 'one']), + docstring='Tie constantly to one') + outsel.add_constant(Name(['constant', 'high', 'z']), + docstring='Tie constantly to high-Z') + i = 0 + for sig in pinmux_info['ios']: + if sig['connection'] == 'muxed' and sig['type'] in ['inout', 'output']: + index = Name([str(sig['idx'])]) if sig['idx'] != -1 else Name([]) + name = Name.from_snake_case(sig['name']) + index + outsel.add_constant(name, docstring='Peripheral Output {}'.format(i)) + i += 1 + + outsel.add_last_constant('Last valid outsel value') + + self.pinmux_peripheral_in = peripheral_in + self.pinmux_insel = insel + self.pinmux_mio_out = mio_out + self.pinmux_outsel = outsel + + def _init_pwrmgr_wakeups(self): + enum = CEnum(self._top_name + + Name(["power", "manager", "wake", "ups"])) + + for signal in self.top["wakeups"]: + enum.add_constant( + Name.from_snake_case(signal["module"]) + + Name.from_snake_case(signal["name"])) + + enum.add_last_constant("Last valid pwrmgr wakeup signal") + + self.pwrmgr_wakeups = enum + + # Enumerates the positions of all software controllable resets + def _init_rstmgr_sw_rsts(self): + sw_rsts = [ + rst for rst in self.top["resets"]["nodes"] + if 'sw' in rst and rst['sw'] == 1 + ] + + enum = CEnum(self._top_name + + Name(["reset", "manager", "sw", "resets"])) + + for rst in sw_rsts: + enum.add_constant(Name.from_snake_case(rst["name"])) + + enum.add_last_constant("Last valid rstmgr software reset request") + + self.rstmgr_sw_rsts = enum + + def _init_pwrmgr_reset_requests(self): + enum = CEnum(self._top_name + + Name(["power", "manager", "reset", "requests"])) + + for signal in self.top["reset_requests"]: + enum.add_constant( + Name.from_snake_case(signal["module"]) + + Name.from_snake_case(signal["name"])) + + enum.add_last_constant("Last valid pwrmgr reset_request signal") + + self.pwrmgr_reset_requests = enum + + def _init_clkmgr_clocks(self): + """ + Creates CEnums for accessing the software-controlled clocks in the + design. + + The logic here matches the logic in topgen.py in how it instantiates the + clock manager with the described clocks. + + We differentiate "gateable" clocks and "hintable" clocks because the + clock manager has separate register interfaces for each group. + """ + + aon_clocks = set() + for src in self.top['clocks']['srcs'] + self.top['clocks'][ + 'derived_srcs']: + if src['aon'] == 'yes': + aon_clocks.add(src['name']) + + gateable_clocks = CEnum(self._top_name + Name(["gateable", "clocks"])) + hintable_clocks = CEnum(self._top_name + Name(["hintable", "clocks"])) + + # This replicates the behaviour in `topgen.py` in deriving `hints` and + # `sw_clocks`. + for group in self.top['clocks']['groups']: + for (name, source) in group['clocks'].items(): + if source not in aon_clocks: + # All these clocks start with `clk_` which is redundant. + clock_name = Name.from_snake_case(name).remove_part("clk") + docstring = "Clock {} in group {}".format( + name, group['name']) + if group["sw_cg"] == "yes": + gateable_clocks.add_constant(clock_name, docstring) + elif group["sw_cg"] == "hint": + hintable_clocks.add_constant(clock_name, docstring) + + gateable_clocks.add_last_constant("Last Valid Gateable Clock") + hintable_clocks.add_last_constant("Last Valid Hintable Clock") + + self.clkmgr_gateable_clocks = gateable_clocks + self.clkmgr_hintable_clocks = hintable_clocks diff --git a/hw/vendored_ips/gpio/util/reggen/topgen/gen_dv.py b/hw/vendored_ips/gpio/util/reggen/topgen/gen_dv.py new file mode 100644 index 00000000..5e2beaa1 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/topgen/gen_dv.py @@ -0,0 +1,46 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +import logging as log +from typing import Optional, Tuple + +from mako import exceptions # type: ignore +from mako.lookup import TemplateLookup # type: ignore +from pkg_resources import resource_filename + +from reggen.gen_dv import gen_core_file + +from .top import Top + + +def sv_base_addr(top: Top, if_name: Tuple[str, Optional[str]]) -> str: + '''Get the base address of a device interface in SV syntax''' + return "{}'h{:x}".format(top.regwidth, top.if_addrs[if_name]) + + +def gen_dv(top: Top, + dv_base_prefix: str, + outdir: str) -> int: + '''Generate DV RAL model for a Top''' + # Read template + lookup = TemplateLookup(directories=[resource_filename('topgen', '.'), + resource_filename('reggen', '.')]) + uvm_reg_tpl = lookup.get_template('top_uvm_reg.sv.tpl') + + # Expand template + try: + to_write = uvm_reg_tpl.render(top=top, + dv_base_prefix=dv_base_prefix) + except: # noqa: E722 + log.error(exceptions.text_error_template().render()) + return 1 + + # Dump to output file + dest_path = '{}/chip_ral_pkg.sv'.format(outdir) + with open(dest_path, 'w') as fout: + fout.write(to_write) + + gen_core_file(outdir, 'chip', dv_base_prefix, ['chip_ral_pkg.sv']) + + return 0 diff --git a/hw/vendored_ips/gpio/util/reggen/topgen/intermodule.py b/hw/vendored_ips/gpio/util/reggen/topgen/intermodule.py new file mode 100644 index 00000000..d1048c12 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/topgen/intermodule.py @@ -0,0 +1,1005 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +import logging as log +import re +from collections import OrderedDict +from enum import Enum +from typing import Dict, List, Tuple + +from reggen.ip_block import IpBlock +from reggen.inter_signal import InterSignal +from reggen.validate import check_int +from topgen import lib + +IM_TYPES = ['uni', 'req_rsp'] +IM_ACTS = ['req', 'rsp', 'rcv'] +IM_VALID_TYPEACT = {'uni': ['req', 'rcv'], 'req_rsp': ['req', 'rsp']} +IM_CONN_TYPE = ['1-to-1', '1-to-N', 'broadcast'] + + +class ImType(Enum): + Uni = 1 + ReqRsp = 2 + + +class ImAct(Enum): + Req = 1 + Rsp = 2 + Rcv = 3 + + +class ImConn(Enum): + OneToOne = 1 # req <-> {rsp,rcv} with same width + OneToN = 2 # req width N <-> N x {rsp,rcv}s width 1 + Broadcast = 3 # req width 1 <-> N x rcvs width 1 + + +def intersignal_format(req: Dict) -> str: + """Determine the signal format of the inter-module connections + + @param[req] Request struct. It has instance name, package format + and etc. + """ + + # TODO: Handle array signal + result = "{req}_{struct}".format(req=req["inst_name"], struct=req["name"]) + + # check signal length if exceeds 100 + + # 7 : space + . + # 3 : _{i|o}( + # 6 : _{req|rsp}), + req_length = 7 + len(req["name"]) + 3 + len(result) + 6 + + if req_length > 100: + logmsg = "signal {0} length cannot be greater than 100" + log.warning(logmsg.format(result)) + log.warning("Please consider shorten the instance name") + return result + + +def get_suffixes(ims: OrderedDict) -> Tuple[str, str]: + """Get suffixes of the struct. + + TL-UL struct uses `h2d`, `d2h` suffixes for req, rsp pair. + """ + if ims["package"] == "tlul_pkg" and ims["struct"] == "tl": + return ("_h2d", "_d2h") + + return ("_req", "_rsp") + + +def add_intermodule_connection(obj: OrderedDict, req_m: str, req_s: str, + rsp_m: str, rsp_s: str): + """Add if doesn't exist the connection + + Add a connection into obj['inter_module']['connect'] dictionary if doesn't exist. + + Parameters: + obj: Top dictionary object + req_m: Requester module name + req_s: Requester signal name + rsp_m: Responder module name + rsp_s: Responder signal name + + Returns: + No return type for this function + """ + req_key = "{}.{}".format(req_m, req_s) + rsp_key = "{}.{}".format(rsp_m, rsp_s) + + connect = obj["inter_module"]["connect"] + if req_key in connect: + # check if rsp has data + if rsp_key in connect[req_key]: + return + req_key.append(rsp_key) + return + + # req_key is not in connect: + # check if rsp_key + if rsp_key in connect: + # check if rsp has data + if req_key in connect[rsp_key]: + return + rsp_key.append(req_key) + return + + # Add new key and connect + connect[req_key] = [rsp_key] + + +def autoconnect_xbar(topcfg: OrderedDict, + name_to_block: Dict[str, IpBlock], + xbar: OrderedDict) -> None: + # The crossbar is connecting to modules and memories in topcfg, plus + # possible external connections. Make indices for the modules and memories + # for quick lookup and add some assertions to make sure no name appears in + # multiple places. + name_to_module = {} + for mod in topcfg['module']: + assert mod['name'] not in name_to_module + if lib.is_inst(mod): + name_to_module[mod['name']] = mod + + name_to_memory = {} + for mem in topcfg['memory']: + assert mem['name'] not in name_to_memory + if lib.is_inst(mem): + name_to_memory[mem['name']] = mem + + # The names of modules and memories should be disjoint + assert not (set(name_to_module.keys()) & set(name_to_memory.keys())) + + external_names = (set(topcfg['inter_module']['top']) | + set(topcfg["inter_module"]["external"].keys())) + + ports = [x for x in xbar["nodes"] if x["type"] in ["host", "device"]] + for port in ports: + # Here, we expect port_name to either be a single identifier (in which + # case, it's taken as the name of some module or memory) to be a dotted + # pair MOD.INAME where MOD is the name of some module and INAME is the + # associated interface name. + name_parts = port['name'].split('.', 1) + port_base = name_parts[0] + port_iname = name_parts[1] if len(name_parts) > 1 else None + esc_name = port['name'].replace('.', '__') + + if port["xbar"]: + if port_iname is not None: + log.error('A crossbar connection may not ' + 'have a target of the form MOD.INAME (saw {!r})' + .format(port['name'])) + continue + + if port["type"] == "host": + # Skip as device will add connection + continue + + # Device port adds signal + add_intermodule_connection(obj=topcfg, + req_m=xbar["name"], + req_s="tl_" + esc_name, + rsp_m=esc_name, + rsp_s="tl_" + xbar["name"]) + continue # xbar port case + + port_mod = name_to_module.get(port_base) + port_mem = name_to_memory.get(port_base) + assert port_mod is None or port_mem is None + + if not (port_mod or port_mem): + # if not in module, memory, should be existed in top or ext field + module_key = "{}.tl_{}".format(xbar["name"], esc_name) + if module_key not in external_names: + log.error("Inter-module key {} cannot be found in module, " + "memory, top, or external lists.".format(module_key)) + + continue + + if port_iname is not None and port_mem is not None: + log.error('Cannot make connection for {!r}: the base of the name ' + 'points to a memory but memories do not support ' + 'interface names.' + .format(port['name'])) + + is_host = port['type'] == 'host' + + # If the hit is a module, it originally came from reggen (via + # merge.py's amend_ip() function). In this case, we should have a + # BusInterfaces object as well as a list of InterSignal objects. + # + # If not, this is a memory that will just have a dictionary of inter + # signals. + if port_mod is not None: + block = name_to_block[port_mod['type']] + try: + sig_name = block.bus_interfaces.find_port_name(is_host, + port_iname) + except KeyError: + log.error('Cannot make {} connection for {!r}: the base of ' + 'the target module has no matching bus interface.' + .format('host' if is_host else 'device', + port['name'])) + continue + else: + inter_signal_list = port_mem['inter_signal_list'] + act = 'req' if is_host else 'rsp' + matches = [ + x for x in inter_signal_list + if (x.get('package') == 'tlul_pkg' and + x['struct'] == 'tl' and + x['act'] == act) + ] + if not matches: + log.error('Cannot make {} connection for {!r}: the memory ' + 'has no signal with an action of {}.' + .format('host' if is_host else 'device', + port['name'], + act)) + continue + + assert len(matches) == 1 + sig_name = matches[0]['name'] + + add_intermodule_connection(obj=topcfg, + req_m=port_base, + req_s=sig_name, + rsp_m=xbar["name"], + rsp_s="tl_" + esc_name) + + +def autoconnect(topcfg: OrderedDict, name_to_block: Dict[str, IpBlock]): + """Matching the connection based on the naming rule + between {memory, module} <-> Xbar. + """ + + # Add xbar connection to the modules, memories + for xbar in topcfg["xbar"]: + autoconnect_xbar(topcfg, name_to_block, xbar) + + +def _get_default_name(sig, suffix): + """Generate default for a net if one does not already exist. + """ + + # The else case covers the scenario where neither package nor default is provided. + # Specifically, the interface is 'logic' and has no default value. + # In this situation, just return 0's + if sig['default']: + return sig['default'] + elif sig['package']: + return "{}::{}_DEFAULT".format(sig['package'], (sig["struct"] + suffix).upper()) + else: + return "'0" + + +def elab_intermodule(topcfg: OrderedDict): + """Check the connection of inter-module and categorize them + + In the top template, it uses updated inter_module fields to create + connections between the modules (incl. memories). This function is to + create and check the validity of the connections `inter_module` using IPs' + `inter_signal_list`. + """ + + list_of_intersignals = [] + + if "inter_signal" not in topcfg: + topcfg["inter_signal"] = OrderedDict() + + # Gather the inter_signal_list + instances = topcfg["module"] + topcfg["memory"] + topcfg["xbar"] + \ + topcfg["host"] + topcfg["port"] + + for x in instances: + old_isl = x.get('inter_signal_list') + if old_isl is None: + continue + + new_isl = [] + for entry in old_isl: + # Convert any InterSignal objects to the expected dictionary format. + sig = (entry.as_dict() + if isinstance(entry, InterSignal) + else entry.copy()) + + # Add instance name to the entry and add to list_of_intersignals + sig["inst_name"] = x["name"] + list_of_intersignals.append(sig) + new_isl.append(sig) + + x['inter_signal_list'] = new_isl + + # Add field to the topcfg + topcfg["inter_signal"]["signals"] = list_of_intersignals + + # TODO: Cross check Can be done here not in validate as ipobj is not + # available in validate + error = check_intermodule(topcfg, "Inter-module Check") + assert error == 0, "Inter-module validation is failed cannot move forward." + + # intermodule + definitions = [] + + # Check the originator + # As inter-module connection allow only 1:1, 1:N, or N:1, pick the most + # common signals. If a requester connects to multiple responders/receivers, + # the requester is main connector so that the definition becomes array. + # + # For example: + # inter_module: { + # 'connect': { + # 'pwr_mgr.pwrup': ['lc.pwrup', 'otp.pwrup'] + # } + # } + # The tool adds `struct [1:0] pwr_mgr_pwrup` + # It doesn't matter whether `pwr_mgr.pwrup` is requester or responder. + # If the key is responder type, then the connection is made in reverse, + # such that `lc.pwrup --> pwr_mgr.pwrup[0]` and + # `otp.pwrup --> pwr_mgr.pwrup[1]` + + uid = 0 # Unique connection ID across the top + + for req, rsps in topcfg["inter_module"]["connect"].items(): + log.info("{req} --> {rsps}".format(req=req, rsps=rsps)) + + # Split index + req_module, req_signal, req_index = filter_index(req) + + # get the module signal + req_struct = find_intermodule_signal(list_of_intersignals, req_module, + req_signal) + + # decide signal format based on the `key` + sig_name = intersignal_format(req_struct) + req_struct["top_signame"] = sig_name + + # Find package in req, rsps + if "package" in req_struct: + package = req_struct["package"] + else: + for rsp in rsps: + rsp_module, rsp_signal, rsp_index = filter_index(rsp) + rsp_struct = find_intermodule_signal(list_of_intersignals, + rsp_module, rsp_signal) + if "package" in rsp_struct: + package = rsp_struct["package"] + break + if not package: + package = "" + + # Add to definition + if req_struct["type"] == "req_rsp": + req_suffix, rsp_suffix = get_suffixes(req_struct) + req_default = _get_default_name(req_struct, req_suffix) + rsp_default = _get_default_name(req_struct, rsp_suffix) + + # based on the active direction of the req_struct, one of the directions does not + # need a default since it will be an output + if (req_struct["act"] == 'req'): + req_default = '' + else: + rsp_default = '' + + # Add two definitions + definitions.append( + OrderedDict([('package', package), + ('struct', req_struct["struct"] + req_suffix), + ('signame', sig_name + "_req"), + ('width', req_struct["width"]), + ('type', req_struct["type"]), + ('end_idx', req_struct["end_idx"]), + ('act', req_struct["act"]), + ('suffix', "req"), + ('default', req_default)])) + definitions.append( + OrderedDict([('package', package), + ('struct', req_struct["struct"] + rsp_suffix), + ('signame', sig_name + "_rsp"), + ('width', req_struct["width"]), + ('type', req_struct["type"]), + ('end_idx', req_struct["end_idx"]), + ('act', req_struct["act"]), + ('suffix', "rsp"), + ('default', rsp_default)])) + else: + # unidirection + default = _get_default_name(req_struct, "") + definitions.append( + OrderedDict([('package', package), + ('struct', req_struct["struct"]), + ('signame', sig_name), + ('width', req_struct["width"]), + ('type', req_struct["type"]), + ('end_idx', req_struct["end_idx"]), + ('act', req_struct["act"]), + ('suffix', ""), + ('default', default)])) + + req_struct["index"] = -1 + + for i, rsp in enumerate(rsps): + # Split index + rsp_module, rsp_signal, rsp_index = filter_index(rsp) + + rsp_struct = find_intermodule_signal(list_of_intersignals, + rsp_module, rsp_signal) + + # determine the signal name + + rsp_struct["top_signame"] = sig_name + if req_struct["type"] == "uni" and req_struct[ + "top_type"] == "broadcast": + rsp_struct["index"] = -1 + elif rsp_struct["width"] == req_struct["width"] and len(rsps) == 1: + rsp_struct["index"] = -1 + else: + rsp_struct["index"] = -1 if req_struct["width"] == 1 else i + + # Assume it is logic + # req_rsp doesn't allow logic + if req_struct["struct"] == "logic": + assert req_struct[ + "type"] != "req_rsp", "logic signal cannot have req_rsp type" + + # increase Unique ID + uid += 1 + + # TODO: Check unconnected port + if "top" not in topcfg["inter_module"]: + topcfg["inter_module"]["top"] = [] + + for s in topcfg["inter_module"]["top"]: + sig_m, sig_s, sig_i = filter_index(s) + assert sig_i == -1, 'top net connection should not use bit index' + sig = find_intermodule_signal(list_of_intersignals, sig_m, sig_s) + sig_name = intersignal_format(sig) + sig["top_signame"] = sig_name + if "index" not in sig: + sig["index"] = -1 + + if sig["type"] == "req_rsp": + req_suffix, rsp_suffix = get_suffixes(sig) + # Add two definitions + definitions.append( + OrderedDict([('package', sig["package"]), + ('struct', sig["struct"] + req_suffix), + ('signame', sig_name + "_req"), + ('width', sig["width"]), ('type', sig["type"]), + ('end_idx', -1), + ('default', sig["default"])])) + definitions.append( + OrderedDict([('package', sig["package"]), + ('struct', sig["struct"] + rsp_suffix), + ('signame', sig_name + "_rsp"), + ('width', sig["width"]), ('type', sig["type"]), + ('end_idx', -1), + ('default', sig["default"])])) + else: # if sig["type"] == "uni": + definitions.append( + OrderedDict([('package', sig["package"]), + ('struct', sig["struct"]), ('signame', sig_name), + ('width', sig["width"]), ('type', sig["type"]), + ('end_idx', -1), + ('default', sig["default"])])) + + topcfg["inter_module"].setdefault('external', []) + topcfg["inter_signal"].setdefault('external', []) + + for s, port in topcfg["inter_module"]["external"].items(): + sig_m, sig_s, sig_i = filter_index(s) + assert sig_i == -1, 'top net connection should not use bit index' + sig = find_intermodule_signal(list_of_intersignals, sig_m, sig_s) + + # To make netname `_o` or `_i` + sig['external'] = True + + sig_name = port if port != "" else intersignal_format(sig) + + # if top signame already defined, then a previous connection category + # is already connected to external pin. Sig name is only used for + # port definition + conn_type = False + if "top_signame" not in sig: + sig["top_signame"] = sig_name + else: + conn_type = True + + if "index" not in sig: + sig["index"] = -1 + + # Add the port definition to top external ports + index = sig["index"] + netname = sig["top_signame"] + if sig["type"] == "req_rsp": + req_suffix, rsp_suffix = get_suffixes(sig) + if sig["act"] == "req": + req_sigsuffix, rsp_sigsuffix = ("_o", "_i") + + else: + req_sigsuffix, rsp_sigsuffix = ("_i", "_o") + + topcfg["inter_signal"]["external"].append( + OrderedDict([('package', sig["package"]), + ('struct', sig["struct"] + req_suffix), + ('signame', sig_name + "_req" + req_sigsuffix), + ('width', sig["width"]), ('type', sig["type"]), + ('default', sig["default"]), + ('direction', + 'out' if sig['act'] == "req" else 'in'), + ('conn_type', conn_type), + ('index', index), + ('netname', netname + req_suffix)])) + topcfg["inter_signal"]["external"].append( + OrderedDict([('package', sig["package"]), + ('struct', sig["struct"] + rsp_suffix), + ('signame', sig_name + "_rsp" + rsp_sigsuffix), + ('width', sig["width"]), ('type', sig["type"]), + ('default', sig["default"]), + ('direction', + 'in' if sig['act'] == "req" else 'out'), + ('conn_type', conn_type), + ('index', index), + ('netname', netname + rsp_suffix)])) + else: # uni + if sig["act"] == "req": + sigsuffix = "_o" + else: + sigsuffix = "_i" + topcfg["inter_signal"]["external"].append( + OrderedDict([('package', sig.get("package", "")), + ('struct', sig["struct"]), + ('signame', sig_name + sigsuffix), + ('width', sig["width"]), ('type', sig["type"]), + ('default', sig["default"]), + ('direction', + 'out' if sig['act'] == "req" else 'in'), + ('conn_type', conn_type), + ('index', index), + ('netname', netname)])) + + for sig in topcfg["inter_signal"]["signals"]: + # Check if it exist in definitions + if "top_signame" in sig: + continue + + # Set index to -1 + sig["index"] = -1 + + # TODO: Handle the unconnected port rule + + if "definitions" not in topcfg["inter_signal"]: + topcfg["inter_signal"]["definitions"] = definitions + + +def filter_index(signame: str) -> Tuple[str, str, int]: + """If the signal has array indicator `[N]` then split and return name and + array index. If not, array index is -1. + + param signame module.sig{[N]} + + result (module_name, signal_name, array_index) + """ + m = re.match(r'(\w+)\.(\w+)(\[(\d+)\])*', signame) + + if not m: + # Cannot match the pattern + return "", "", -1 + + if m.group(3): + # array index is not None + return m.group(1), m.group(2), m.group(4) + + return m.group(1), m.group(2), -1 + + +def find_intermodule_signal(sig_list, m_name, s_name) -> Dict: + """Return the intermodule signal structure + """ + + filtered = [ + x for x in sig_list if x["name"] == s_name and x["inst_name"] == m_name + ] + + if len(filtered) == 1: + return filtered[0] + + log.error("Found {num} entry/entries for {m_name}.{s_name}:".format( + num=len(filtered), m_name=m_name, s_name=s_name)) + return None + + +# Validation +def check_intermodule_field(sig: OrderedDict, + prefix: str = "") -> Tuple[int, OrderedDict]: + error = 0 + + # type check + if sig["type"] not in IM_TYPES: + log.error("{prefix} Inter_signal {name} " + "type {type} is incorrect.".format(prefix=prefix, + name=sig["name"], + type=sig["type"])) + error += 1 + + if sig["act"] not in IM_ACTS: + log.error("{prefix} Inter_signal {name} " + "act {act} is incorrect.".format(prefix=prefix, + name=sig["name"], + act=sig["act"])) + error += 1 + + # Check if type and act are matched + if error == 0: + if sig["act"] not in IM_VALID_TYPEACT[sig['type']]: + log.error("{type} and {act} of {name} are not a valid pair." + "".format(type=sig['type'], + act=sig['act'], + name=sig['name'])) + error += 1 + # Check 'width' field + width = 1 + if "width" not in sig: + sig["width"] = 1 + elif not isinstance(sig["width"], int): + width, err = check_int(sig["width"], sig["name"]) + if err: + log.error("{prefix} Inter-module {inst}.{sig} 'width' " + "should be int type.".format(prefix=prefix, + inst=sig["inst_name"], + sig=sig["name"])) + error += 1 + else: + # convert to int value + sig["width"] = width + + # Add empty string if no explicit default for dangling pins is given. + # In that case, dangling pins of type struct will be tied to the default + # parameter in the corresponding package, and dangling pins of type logic + # will be tied off to '0. + if "default" not in sig: + sig["default"] = "" + + if "package" not in sig: + sig["package"] = "" + + return error, sig + + +def find_otherside_modules(topcfg: OrderedDict, m, + s) -> List[Tuple[str, str, str]]: + """Find far-end port based on given module and signal name + """ + # TODO: handle special cases + special_inst_names = { + ('main', 'tl_rom'): ('tl_adapter_rom', 'tl'), + ('main', 'tl_ram_main'): ('tl_adapter_ram_main', 'tl'), + ('main', 'tl_eflash'): ('tl_adapter_eflash', 'tl'), + ('peri', 'tl_ram_ret_aon'): ('tl_adapter_ram_ret_aon', 'tl'), + ('main', 'tl_corei'): ('rv_core_ibex', 'tl_i'), + ('main', 'tl_cored'): ('rv_core_ibex', 'tl_d'), + ('main', 'tl_dm_sba'): ('dm_top', 'tl_h'), + ('main', 'tl_debug_mem'): ('dm_top', 'tl_d'), + ('peri', 'tl_ast'): ('ast', 'tl') + } + special_result = special_inst_names.get((m, s)) + if special_result is not None: + return [('top', special_result[0], special_result[1])] + + signame = "{}.{}".format(m, s) + for req, rsps in topcfg["inter_module"]["connect"].items(): + if req.startswith(signame): + # return rsps after splitting module instance name and the port + result = [] + for rsp in rsps: + rsp_m, rsp_s, rsp_i = filter_index(rsp) + result.append(('connect', rsp_m, rsp_s)) + return result + + for rsp in rsps: + if signame == rsp: + req_m, req_s, req_i = filter_index(req) + return [('connect', req_m, req_s)] + + # if reaches here, it means either the format is wrong, or floating port. + log.error("`find_otherside_modules()`: " + "No such signal {}.{} exists.".format(m, s)) + return [] + + +def check_intermodule(topcfg: Dict, prefix: str) -> int: + if "inter_module" not in topcfg: + return 0 + + total_error = 0 + + for req, rsps in topcfg["inter_module"]["connect"].items(): + error = 0 + # checking the key, value are in correct format + # Allowed format + # 1. module.signal + # 2. module.signal[index] // Remember array is not yet supported + # // But allow in format checker + # + # Example: + # inter_module: { + # 'connect': { + # 'flash_ctrl.flash': ['eflash.flash_ctrl'], + # 'life_cycle.provision': ['debug_tap.dbg_en', 'dft_ctrl.en'], + # 'otp.pwr_hold': ['pwrmgr.peri[0]'], + # 'flash_ctrl.pwr_hold': ['pwrmgr.peri[1]'], + # } + # } + # + # If length of value list is > 1, then key should be array (width need to match) + # If key is format #2, then length of value list shall be 1 + # If one of the value is format #2, then the key should be 1 bit width and + # entries of value list should be 1 + req_m, req_s, req_i = filter_index(req) + + if req_s == "": + log.error( + "Cannot parse the inter-module signal key '{req}'".format( + req=req)) + error += 1 + + # Check rsps signal format is list + if not isinstance(rsps, list): + log.error("Value of key '{req}' should be a list".format(req=req)) + error += 1 + continue + + req_struct = find_intermodule_signal(topcfg["inter_signal"]["signals"], + req_m, req_s) + + err, req_struct = check_intermodule_field(req_struct) + error += err + + if req_i != -1 and len(rsps) != 1: + # Array format should have one entry + log.error( + "If key {req} has index, only one entry is allowed.".format( + req=req)) + error += 1 + + total_width = 0 + widths = [] + + # Check rsp format + for i, rsp in enumerate(rsps): + rsp_m, rsp_s, rsp_i = filter_index(rsp) + if rsp_s == "": + log.error( + "Cannot parse the inter-module signal key '{req}->{rsp}'". + format(req=req, rsp=rsp)) + error += 1 + + rsp_struct = find_intermodule_signal( + topcfg["inter_signal"]["signals"], rsp_m, rsp_s) + + err, rsp_struct = check_intermodule_field(rsp_struct) + error += err + + total_width += rsp_struct["width"] + widths.append(rsp_struct["width"]) + + # Type check + # If no package was declared, it is declared with an empty string + if not rsp_struct["package"]: + rsp_struct["package"] = req_struct.get("package", "") + elif req_struct["package"] != rsp_struct["package"]: + log.error( + "Inter-module package should be matched: " + "{req}->{rsp} exp({expected}), actual({actual})".format( + req=req_struct["name"], + rsp=rsp_struct["name"], + expected=req_struct["package"], + actual=rsp_struct["package"])) + error += 1 + if req_struct["type"] != rsp_struct["type"]: + log.error( + "Inter-module type should be matched: " + "{req}->{rsp} exp({expected}), actual({actual})".format( + req=req_struct["name"], + rsp=rsp_struct["name"], + expected=req_struct["type"], + actual=rsp_struct["type"])) + error += 1 + + # If len(rsps) is 1, then the width should be matched to req + if req_struct["width"] != 1: + if rsp_struct["width"] not in [1, req_struct["width"]]: + log.error( + "If req {req} is an array, " + "rsp {rsp} shall be non-array or array with same width" + .format(req=req, rsp=rsp)) + error += 1 + + elif rsp_i != -1: + # If rsp has index, req should be width 1 + log.error( + "If rsp {rsp} has an array index, only one-to-one map is allowed." + .format(rsp=rsp)) + error += 1 + + # Determine if broadcast or one-to-N + log.debug("Handling inter-sig {} {}".format(req_struct['name'], total_width)) + req_struct["end_idx"] = -1 + if req_struct["width"] > 1 or len(rsps) != 1: + # If req width is same to the every width of rsps ==> broadcast + if len(rsps) * [req_struct["width"]] == widths: + log.debug("broadcast type") + req_struct["top_type"] = "broadcast" + + # If req width is same as total width of rsps ==> one-to-N + elif req_struct["width"] == total_width: + log.debug("one-to-N type") + req_struct["top_type"] = "one-to-N" + + # one-to-N connection is not fully populated + elif req_struct["width"] > total_width: + log.debug("partial one-to-N type") + req_struct["top_type"] = "partial-one-to-N" + req_struct["end_idx"] = len(rsps) + + # If not, error + else: + log.error("'uni' type connection {req} should be either " + "OneToN or Broadcast".format(req=req)) + error += 1 + + elif req_struct["type"] == "uni": + # one-to-one connection + req_struct["top_type"] = "broadcast" + + # If req is array, it is not allowed to have partial connections. + # Doing for loop again here: Make code separate from other checker + # for easier maintenance + total_error += error + + if error != 0: + # Skip the check + continue + + for item in topcfg["inter_module"]["top"] + list( + topcfg["inter_module"]["external"].keys()): + sig_m, sig_s, sig_i = filter_index(item) + if sig_i != -1: + log.error("{item} cannot have index".format(item=item)) + total_error += 1 + + sig_struct = find_intermodule_signal(topcfg["inter_signal"]["signals"], + sig_m, sig_s) + err, sig_struct = check_intermodule_field(sig_struct) + total_error += err + + return total_error + + +# Template functions +def im_defname(obj: OrderedDict) -> str: + """return definition struct name + + e.g. flash_ctrl::flash_req_t + """ + if obj["package"] == "": + # should be logic + return "logic" + + return "{package}::{struct}_t".format(package=obj["package"], + struct=obj["struct"]) + + +def im_netname(sig: OrderedDict, + suffix: str = "", default_name=False) -> str: + """return top signal name with index + + It also adds suffix for external signal. + + The default name input forces function to return default name, even if object + has a connection. + """ + + # Basic check and add missing fields + err, obj = check_intermodule_field(sig) + assert not err + + # Floating signals + # TODO: Find smarter way to assign default? + if "top_signame" not in obj or default_name: + if obj["act"] == "req" and suffix == "req": + return "" + if obj["act"] == "rsp" and suffix == "rsp": + return "" + if obj["act"] == "req" and suffix == "rsp": + # custom default has been specified + if obj["default"]: + return obj["default"] + if obj["package"] == "tlul_pkg" and obj["struct"] == "tl": + return "{package}::{struct}_D2H_DEFAULT".format( + package=obj["package"], struct=obj["struct"].upper()) + return "{package}::{struct}_RSP_DEFAULT".format( + package=obj["package"], struct=obj["struct"].upper()) + if obj["act"] == "rsp" and suffix == "req": + # custom default has been specified + if obj["default"]: + return obj["default"] + if obj.get("package") == "tlul_pkg" and obj["struct"] == "tl": + return "{package}::{struct}_H2D_DEFAULT".format( + package=obj["package"], struct=obj["struct"].upper()) + # default is used for dangling ports in definitions. + # the struct name already has `_req` suffix + return "{package}::{struct}_REQ_DEFAULT".format( + package=obj.get("package", ''), struct=obj["struct"].upper()) + if obj["act"] == "rcv" and suffix == "" and obj["struct"] == "logic": + # custom default has been specified + if obj["default"]: + return obj["default"] + return "'0" + if obj["act"] == "rcv" and suffix == "": + # custom default has been specified + if obj["default"]: + return obj["default"] + return "{package}::{struct}_DEFAULT".format( + package=obj["package"], struct=obj["struct"].upper()) + + return "" + + # Connected signals + assert suffix in ["", "req", "rsp"] + + suffix_s = "_{suffix}".format(suffix=suffix) if suffix != "" else suffix + + # External signal handling + if "external" in obj and obj["external"]: + pairs = { + # act , suffix: additional suffix + ("req", "req"): "_o", + ("req", "rsp"): "_i", + ("rsp", "req"): "_i", + ("rsp", "rsp"): "_o", + ("req", ""): "_o", + ("rcv", ""): "_i" + } + suffix_s += pairs[(obj['act'], suffix)] + + return "{top_signame}{suffix}{index}".format( + top_signame=obj["top_signame"], + suffix=suffix_s, + index=lib.index(obj["index"])) + + +def im_portname(obj: OrderedDict, suffix: str = "") -> str: + """return IP's port name + + e.g signame_o for requester req signal + """ + act = obj['act'] + name = obj['name'] + + if suffix == "": + suffix_s = "_o" if act == "req" else "_i" + elif suffix == "req": + suffix_s = "_o" if act == "req" else "_i" + else: + suffix_s = "_o" if act == "rsp" else "_i" + + return name + suffix_s + + +def get_dangling_im_def(objs: OrderedDict) -> str: + """return partial inter-module definitions + + Dangling intermodule connections happen when a one-to-N assignment + is not fully populated. + + This can result in two types of dangling: + - outgoing requests not used + - incoming responses not driven + + The determination of which category we fall into follows similar rules + as those used by im_netname. + + When the direction of the net is the same as the active direction of the + the connecting module, it is "unused". + + When the direction of the net is opposite of the active direction of the + the connecting module, it is "undriven". + + As an example, edn is defined as "rsp" of a "req_rsp" pair. It is also used + as the "active" module in inter-module connection. If there are not enough + connecting modules, the 'req' line is undriven, while the 'rsp' line is + unused. + + """ + unused_def = [obj for obj in objs if obj['end_idx'] > 0 and + obj['act'] == obj['suffix']] + + undriven_def = [obj for obj in objs if obj['end_idx'] > 0 and + (obj['act'] == 'req' and obj['suffix'] == 'rsp' or + obj['act'] == 'rsp' and obj['suffix'] == 'req')] + + return unused_def, undriven_def diff --git a/hw/vendored_ips/gpio/util/reggen/topgen/lib.py b/hw/vendored_ips/gpio/util/reggen/topgen/lib.py new file mode 100644 index 00000000..a1354fdf --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/topgen/lib.py @@ -0,0 +1,497 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +import logging as log +import re +import sys +from collections import OrderedDict +from copy import deepcopy +from pathlib import Path +from typing import Dict, List, Optional, Tuple + +import hjson + +from reggen.ip_block import IpBlock + +# Ignore flake8 warning as the function is used in the template +# disable isort formating, as conflicting with flake8 +from .intermodule import find_otherside_modules # noqa : F401 # isort:skip +from .intermodule import im_portname, im_defname, im_netname # noqa : F401 # isort:skip +from .intermodule import get_dangling_im_def # noqa : F401 # isort:skip + + +class Name: + """ + We often need to format names in specific ways; this class does so. + + To simplify parsing and reassembling of name strings, this class + stores the name parts as a canonical list of strings internally + (in self.parts). + + The "from_*" functions parse and split a name string into the canonical + list, whereas the "as_*" functions reassemble the canonical list in the + format specified. + + For example, ex = Name.from_snake_case("example_name") gets split into + ["example", "name"] internally, and ex.as_camel_case() reassembles this + internal representation into "ExampleName". + """ + def __add__(self, other): + return Name(self.parts + other.parts) + + @staticmethod + def from_snake_case(input: str) -> 'Name': + return Name(input.split("_")) + + def __init__(self, parts: List[str]): + self.parts = parts + for p in parts: + assert len(p) > 0, "cannot add zero-length name piece" + + def as_snake_case(self) -> str: + return "_".join([p.lower() for p in self.parts]) + + def as_camel_case(self) -> str: + out = "" + for p in self.parts: + # If we're about to join two parts which would introduce adjacent + # numbers, put an underscore between them. + if out[-1:].isnumeric() and p[:1].isnumeric(): + out += "_" + p + else: + out += p.capitalize() + return out + + def as_c_define(self) -> str: + return "_".join([p.upper() for p in self.parts]) + + def as_c_enum(self) -> str: + return "k" + self.as_camel_case() + + def as_c_type(self) -> str: + return self.as_snake_case() + "_t" + + def remove_part(self, part_to_remove: str) -> "Name": + return Name([p for p in self.parts if p != part_to_remove]) + + +def is_ipcfg(ip: Path) -> bool: # return bool + log.info("IP Path: %s" % repr(ip)) + ip_name = ip.parents[1].name + hjson_name = ip.name + + log.info("IP Name(%s) and HJSON name (%s)" % (ip_name, hjson_name)) + + if ip_name + ".hjson" == hjson_name or ip_name + "_reg.hjson" == hjson_name: + return True + return False + + +def search_ips(ip_path): # return list of config files + # list the every Hjson file + p = ip_path.glob('*/data/*.hjson') + + # filter only ip_name/data/ip_name{_reg|''}.hjson + ips = [x for x in p if is_ipcfg(x)] + + log.info("Filtered-in IP files: %s" % repr(ips)) + return ips + + +def is_xbarcfg(xbar_obj): + if "type" in xbar_obj and xbar_obj["type"] == "xbar": + return True + + return False + + +def get_hjsonobj_xbars(xbar_path): + """ Search crossbars Hjson files from given path. + + Search every Hjson in the directory and check Hjson type. + It could be type: "top" or type: "xbar" + returns [(name, obj), ... ] + """ + p = xbar_path.glob('*.hjson') + try: + xbar_objs = [ + hjson.load(x.open('r'), + use_decimal=True, + object_pairs_hook=OrderedDict) for x in p + ] + except ValueError: + raise SystemExit(sys.exc_info()[1]) + + xbar_objs = [x for x in xbar_objs if is_xbarcfg(x)] + + return xbar_objs + + +def get_module_by_name(top, name): + """Search in top["module"] by name + """ + module = None + for m in top["module"]: + if m["name"] == name: + module = m + break + + return module + + +def intersignal_to_signalname(top, m_name, s_name) -> str: + + # TODO: Find the signal in the `inter_module_list` and get the correct signal name + + return "{m_name}_{s_name}".format(m_name=m_name, s_name=s_name) + + +def get_package_name_by_intermodule_signal(top, struct) -> str: + """Search inter-module signal package with the struct name + + For instance, if `flash_ctrl` has inter-module signal package, + this function returns the package name + """ + instances = top["module"] + top["memory"] + + intermodule_instances = [ + x["inter_signal_list"] for x in instances if "inter_signal_list" in x + ] + + for m in intermodule_instances: + if m["name"] == struct and "package" in m: + return m["package"] + return "" + + +def get_signal_by_name(module, name): + """Return the signal struct with the type input/output/inout + """ + result = None + for s in module["available_input_list"] + module[ + "available_output_list"] + module["available_inout_list"]: + if s["name"] == name: + result = s + break + + return result + + +def add_module_prefix_to_signal(signal, module): + """Add module prefix to module signal format { name: "sig_name", width: NN } + """ + result = deepcopy(signal) + + if "name" not in signal: + raise SystemExit("signal {} doesn't have name field".format(signal)) + + result["name"] = module + "_" + signal["name"] + result["module_name"] = module + + return result + + +def get_ms_name(name): + """Split module_name.signal_name to module_name , signal_name + """ + + tokens = name.split('.') + + if len(tokens) == 0: + raise SystemExit("This to be catched in validate.py") + + module = tokens[0] + signal = None + if len(tokens) == 2: + signal = tokens[1] + + return module, signal + + +def parse_pad_field(padstr): + """Parse PadName[NN...NN] or PadName[NN] or just PadName + """ + match = re.match(r'^([A-Za-z0-9_]+)(\[([0-9]+)(\.\.([0-9]+))?\]|)', padstr) + return match.group(1), match.group(3), match.group(5) + + +def get_pad_list(padstr): + pads = [] + + pad, first, last = parse_pad_field(padstr) + if first is None: + first = 0 + last = 0 + elif last is None: + last = first + first = int(first, 0) + last = int(last, 0) + # width = first - last + 1 + + for p in range(first, last + 1): + pads.append(OrderedDict([("name", pad), ("index", p)])) + + return pads + + +# Template functions +def ljust(x, width): + return "{:<{width}}".format(x, width=width) + + +def bitarray(d, width): + """Print Systemverilog bit array + + @param d the bit width of the signal + @param width max character width of the signal group + + For instance, if width is 4, the max d value in the signal group could be + 9999. If d is 2, then this function pads 3 spaces at the end of the bit + slice. + + "[1:0] " <- d:=2, width=4 + "[9999:0]" <- max d-1 value + + If d is 1, it means array slice isn't necessary. So it returns empty spaces + """ + + if d <= 0: + log.error("lib.bitarray: Given value {} is smaller than 1".format(d)) + raise ValueError + if d == 1: + return " " * (width + 4) # [x:0] needs 4 more space than char_width + + out = "[{}:0]".format(d - 1) + return out + (" " * (width - len(str(d)))) + + +def parameterize(text): + """Return the value wrapping with quote if not integer nor bits + """ + if re.match(r'(\d+\'[hdb]\s*[0-9a-f_A-F]+|[0-9]+)', text) is None: + return "\"{}\"".format(text) + + return text + + +def index(i: int) -> str: + """Return index if it is not -1 + """ + return "[{}]".format(i) if i != -1 else "" + + +def get_clk_name(clk): + """Return the appropriate clk name + """ + if clk == 'main': + return 'clk_i' + else: + return "clk_{}_i".format(clk) + + +def get_reset_path(reset, domain, reset_cfg): + """Return the appropriate reset path given name + """ + # find matching node for reset + node_match = [node for node in reset_cfg['nodes'] if node['name'] == reset] + assert len(node_match) == 1 + reset_type = node_match[0]['type'] + + # find matching path + hier_path = "" + if reset_type == "int": + log.debug("{} used as internal reset".format(reset["name"])) + else: + hier_path = reset_cfg['hier_paths'][reset_type] + + # find domain selection + domain_sel = '' + if reset_type not in ["ext", "int"]: + domain_sel = "[rstmgr_pkg::Domain{}Sel]".format(domain) + + reset_path = "" + if reset_type == "ext": + reset_path = reset + else: + reset_path = "{}rst_{}_n{}".format(hier_path, reset, domain_sel) + + return reset_path + + +def get_unused_resets(top): + """Return dict of unused resets and associated domain + """ + unused_resets = OrderedDict() + unused_resets = { + reset['name']: domain + for reset in top['resets']['nodes'] + for domain in top['power']['domains'] + if reset['type'] == 'top' and domain not in reset['domains'] + } + + log.debug("Unused resets are {}".format(unused_resets)) + return unused_resets + + +def is_templated(module): + """Returns an indication where a particular module is templated + """ + if "attr" not in module: + return False + elif module["attr"] in ["templated"]: + return True + else: + return False + + +def is_top_reggen(module): + """Returns an indication where a particular module is NOT templated + and requires top level specific reggen + """ + if "attr" not in module: + return False + elif module["attr"] in ["reggen_top", "reggen_only"]: + return True + else: + return False + + +def is_inst(module): + """Returns an indication where a particular module should be instantiated + in the top level + """ + top_level_module = False + top_level_mem = False + + if "attr" not in module: + top_level_module = True + elif module["attr"] in ["normal", "templated", "reggen_top"]: + top_level_module = True + elif module["attr"] in ["reggen_only"]: + top_level_module = False + else: + raise ValueError('Attribute {} in {} is not valid' + .format(module['attr'], module['name'])) + + if module['type'] in ['rom', 'ram_1p_scr', 'eflash']: + top_level_mem = True + + return top_level_mem or top_level_module + + +def get_base_and_size(name_to_block: Dict[str, IpBlock], + inst: Dict[str, object], + ifname: Optional[str]) -> Tuple[int, int]: + min_device_spacing = 0x1000 + + block = name_to_block.get(inst['type']) + if block is None: + # If inst isn't the instantiation of a block, it came from some memory. + # Memories have their sizes defined, so we can just look it up there. + bytes_used = int(inst['size'], 0) + + # Memories don't have multiple or named interfaces, so this will only + # work if ifname is None. + assert ifname is None + base_addr = inst['base_addr'] + + else: + # If inst is the instantiation of some block, find the register block + # that corresponds to ifname + rb = block.reg_blocks.get(ifname) + if rb is None: + log.error('Cannot connect to non-existent {} device interface ' + 'on {!r} (an instance of the {!r} block)' + .format('default' if ifname is None else repr(ifname), + inst['name'], block.name)) + bytes_used = 0 + else: + bytes_used = 1 << rb.get_addr_width() + + base_addr = inst['base_addrs'][ifname] + + # Round up to min_device_spacing if necessary + size_byte = max(bytes_used, min_device_spacing) + + if isinstance(base_addr, str): + base_addr = int(base_addr, 0) + else: + assert isinstance(base_addr, int) + + return (base_addr, size_byte) + + +def get_io_enum_literal(sig: Dict, prefix: str) -> str: + """Returns the DIO pin enum literal with value assignment""" + name = Name.from_snake_case(prefix) + Name.from_snake_case(sig["name"]) + # In this case, the signal is a multibit signal, and hence + # we have to make the signal index part of the parameter + # name to uniquify it. + if sig['width'] > 1: + name += Name([str(sig['idx'])]) + return name.as_camel_case() + + +def make_bit_concatenation(sig_name: str, + indices: List[int], + end_indent: int) -> str: + '''Return SV code for concatenating certain indices from a signal + + sig_name is the name of the signal and indices is a non-empty list of the + indices to use, MSB first. So + + make_bit_concatenation("foo", [0, 100, 20]) + + should give + + {foo[0], foo[100], foo[20]} + + Adjacent bits turn into a range select. For example: + + make_bit_concatenation("foo", [0, 1, 2]) + + should give + + foo[0:2] + + If there are multiple ranges, they are printed one to a line. end_indent + gives the indentation of the closing brace and the range selects in between + get indented to end_indent + 2. + + ''' + assert 0 <= end_indent + + ranges = [] + cur_range_start = indices[0] + cur_range_end = indices[0] + for idx in indices[1:]: + if idx == cur_range_end + 1 and cur_range_start <= cur_range_end: + cur_range_end += 1 + continue + if idx == cur_range_end - 1 and cur_range_start >= cur_range_end: + cur_range_end -= 1 + continue + ranges.append((cur_range_start, cur_range_end)) + cur_range_start = idx + cur_range_end = idx + ranges.append((cur_range_start, cur_range_end)) + + items = [] + for range_start, range_end in ranges: + if range_start == range_end: + select = str(range_start) + else: + select = '{}:{}'.format(range_start, range_end) + items.append('{}[{}]'.format(sig_name, select)) + + if len(items) == 1: + return items[0] + + item_indent = '\n' + (' ' * (end_indent + 2)) + + acc = ['{', item_indent, items[0]] + for item in items[1:]: + acc += [',', item_indent, item] + acc += ['\n', ' ' * end_indent, '}'] + return ''.join(acc) diff --git a/hw/vendored_ips/gpio/util/reggen/topgen/merge.py b/hw/vendored_ips/gpio/util/reggen/topgen/merge.py new file mode 100644 index 00000000..6c0a9cd4 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/topgen/merge.py @@ -0,0 +1,1081 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +import logging as log +import random +from collections import OrderedDict +from copy import deepcopy +from math import ceil, log2 +from typing import Dict, List + +from topgen import c, lib +from reggen.ip_block import IpBlock +from reggen.params import LocalParam, Parameter, RandParameter + + +def _get_random_data_hex_literal(width): + """ Fetch 'width' random bits and return them as hex literal""" + width = int(width) + literal_str = hex(random.getrandbits(width)) + return literal_str + + +def _get_random_perm_hex_literal(numel): + """ Compute a random permutation of 'numel' elements and + return as packed hex literal""" + num_elements = int(numel) + width = int(ceil(log2(num_elements))) + idx = [x for x in range(num_elements)] + random.shuffle(idx) + literal_str = "" + for k in idx: + literal_str += format(k, '0' + str(width) + 'b') + # convert to hex for space efficiency + literal_str = hex(int(literal_str, 2)) + return literal_str + + +def elaborate_instances(top, name_to_block: Dict[str, IpBlock]): + '''Add additional fields to the elements of top['module'] + + These elements represent instantiations of IP blocks. This function adds + extra fields to them to carry across information from the IpBlock objects + that represent the blocks being instantiated. See elaborate_instance for + more details of what gets added. + + ''' + # Initialize RNG for compile-time netlist constants. + random.seed(int(top['rnd_cnst_seed'])) + + for instance in top['module']: + block = name_to_block[instance['type']] + elaborate_instance(instance, block) + + +def elaborate_instance(instance, block: IpBlock): + """Add additional fields to a single instance of a module. + + instance is the instance to be filled in. block is the block that it's + instantiating. + + Altered fields: + - param_list (list of parameters for the instance) + - inter_signal_list (list of inter-module signals) + - base_addrs (a map from interface name to its base address) + + Removed fields: + - base_addr (this is reflected in base_addrs) + + """ + mod_name = instance["name"] + + # param_list + new_params = [] + for param in block.params.by_name.values(): + if isinstance(param, LocalParam): + # Remove local parameters. + continue + + new_param = param.as_dict() + + param_expose = param.expose if isinstance(param, Parameter) else False + + # Check for security-relevant parameters that are not exposed, + # adding a top-level name. + if param.name.lower().startswith("sec") and not param_expose: + log.warning("{} has security-critical parameter {} " + "not exposed to top".format( + mod_name, param.name)) + + # Move special prefixes to the beginnining of the parameter name. + param_prefixes = ["Sec", "RndCnst"] + cc_mod_name = c.Name.from_snake_case(mod_name).as_camel_case() + name_top = cc_mod_name + param.name + for prefix in param_prefixes: + if param.name.lower().startswith(prefix.lower()): + name_top = (prefix + cc_mod_name + + param.name[len(prefix):]) + break + + new_param['name_top'] = name_top + + # Generate random bits or permutation, if needed + if isinstance(param, RandParameter): + if param.randtype == 'data': + new_default = _get_random_data_hex_literal(param.randcount) + # Effective width of the random vector + randwidth = param.randcount + else: + assert param.randtype == 'perm' + new_default = _get_random_perm_hex_literal(param.randcount) + # Effective width of the random vector + randwidth = param.randcount * ceil(log2(param.randcount)) + + new_param['default'] = new_default + new_param['randwidth'] = randwidth + + new_params.append(new_param) + + instance["param_list"] = new_params + + # These objects get added-to in place by code in intermodule.py, so we have + # to convert and copy them here. + instance["inter_signal_list"] = [s.as_dict() for s in block.inter_signals] + + # An instance must either have a 'base_addr' address or a 'base_addrs' + # address, but can't have both. + base_addrs = instance.get('base_addrs') + if base_addrs is None: + if 'base_addr' not in instance: + log.error('Instance {!r} has neither a base_addr ' + 'nor a base_addrs field.' + .format(instance['name'])) + else: + # If the instance has a base_addr field, make sure that the block + # has just one device interface. + if len(block.reg_blocks) != 1: + log.error('Instance {!r} has a base_addr field but it ' + 'instantiates the block {!r}, which has {} ' + 'device interfaces.' + .format(instance['name'], + block.name, len(block.reg_blocks))) + else: + if_name = next(iter(block.reg_blocks)) + base_addrs = {if_name: instance['base_addr']} + + # Fill in a bogus base address (we don't have proper error handling, so + # have to do *something*) + if base_addrs is None: + base_addrs = {None: 0} + + instance['base_addrs'] = base_addrs + else: + if 'base_addr' in instance: + log.error('Instance {!r} has both a base_addr ' + 'and a base_addrs field.' + .format(instance['name'])) + + # Since the instance already has a base_addrs field, make sure that + # it's got the same set of keys as the name of the interfaces in the + # block. + inst_if_names = set(base_addrs.keys()) + block_if_names = set(block.reg_blocks.keys()) + if block_if_names != inst_if_names: + log.error('Instance {!r} has a base_addrs field with keys {} ' + 'but the block it instantiates ({!r}) has device ' + 'interfaces {}.' + .format(instance['name'], inst_if_names, + block.name, block_if_names)) + + if 'base_addr' in instance: + del instance['base_addr'] + + +# TODO: Replace this part to be configurable from Hjson or template +predefined_modules = { + "corei": "rv_core_ibex", + "cored": "rv_core_ibex", + "dm_sba": "rv_dm", + "debug_mem": "rv_dm" +} + + +def is_xbar(top, name): + """Check if the given name is crossbar + """ + xbars = list(filter(lambda node: node["name"] == name, top["xbar"])) + if len(xbars) == 0: + return False, None + + if len(xbars) > 1: + log.error("Matching crossbar {} is more than one.".format(name)) + raise SystemExit() + + return True, xbars[0] + + +def xbar_addhost(top, xbar, host): + """Add host nodes information + + - xbar: bool, true if the host port is from another Xbar + """ + # Check and fetch host if exists in nodes + obj = list(filter(lambda node: node["name"] == host, xbar["nodes"])) + if len(obj) == 0: + log.warning( + "host %s doesn't exist in the node list. Using default values" % + host) + obj = OrderedDict([ + ("name", host), + ("clock", xbar['clock']), + ("reset", xbar['reset']), + ("type", "host"), + ("inst_type", ""), + ("stub", False), + # The default matches RTL default + # pipeline_byp is don't care if pipeline is false + ("pipeline", "true"), + ("pipeline_byp", "true") + ]) + xbar["nodes"].append(obj) + return + + xbar_bool, xbar_h = is_xbar(top, host) + if xbar_bool: + log.info("host {} is a crossbar. Nothing to deal with.".format(host)) + + obj[0]["xbar"] = xbar_bool + + if 'clock' not in obj[0]: + obj[0]["clock"] = xbar['clock'] + + if 'reset' not in obj[0]: + obj[0]["reset"] = xbar["reset"] + + obj[0]["stub"] = False + obj[0]["inst_type"] = predefined_modules[ + host] if host in predefined_modules else "" + obj[0]["pipeline"] = obj[0]["pipeline"] if "pipeline" in obj[0] else "true" + obj[0]["pipeline_byp"] = obj[0]["pipeline_byp"] if obj[0][ + "pipeline"] == "true" and "pipeline_byp" in obj[0] else "true" + + +def process_pipeline_var(node): + """Add device nodes pipeline / pipeline_byp information + + - Supply a default of true / true if not defined by xbar + """ + node["pipeline"] = node["pipeline"] if "pipeline" in node else "true" + node["pipeline_byp"] = node[ + "pipeline_byp"] if "pipeline_byp" in node else "true" + + +def xbar_adddevice(top: Dict[str, object], + name_to_block: Dict[str, IpBlock], + xbar: Dict[str, object], + other_xbars: List[str], + device: str) -> None: + """Add or amend an entry in xbar['nodes'] to represent the device interface + + - clock: comes from module if exist, use xbar default otherwise + - reset: comes from module if exist, use xbar default otherwise + - inst_type: comes from module or memory if exist. + - base_addr: comes from module or memory, or assume rv_plic? + - size_byte: comes from module or memory + - xbar: bool, true if the device port is another xbar + - stub: There is no backing module / memory, instead a tlul port + is created and forwarded above the current hierarchy + """ + device_parts = device.split('.', 1) + device_base = device_parts[0] + device_ifname = device_parts[1] if len(device_parts) > 1 else None + + # Try to find a block or memory instance with name device_base. Object + # names should be unique, so there should never be more than one hit. + instances = [ + node for node in top["module"] + top["memory"] + if node['name'] == device_base + ] + assert len(instances) <= 1 + inst = instances[0] if instances else None + + # Try to find a node in the crossbar called device. Node names should be + # unique, so there should never be more than one hit. + nodes = [ + node for node in xbar['nodes'] + if node['name'] == device + ] + assert len(nodes) <= 1 + node = nodes[0] if nodes else None + + log.info("Handling xbar device {} (matches instance? {}; matches node? {})" + .format(device, inst is not None, node is not None)) + + # case 1: another xbar --> check in xbar list + if node is None and device in other_xbars: + log.error( + "Another crossbar %s needs to be specified in the 'nodes' list" % + device) + return + + # If there is no module or memory with the right name, this might still be + # ok: we might be connecting to another crossbar or to a predefined module. + if inst is None: + # case 1: Crossbar handling + if device in other_xbars: + log.info( + "device {} in Xbar {} is connected to another Xbar".format( + device, xbar["name"])) + assert node is not None + node["xbar"] = True + node["stub"] = False + process_pipeline_var(node) + return + + # case 2: predefined_modules (debug_mem, rv_plic) + # TODO: Find configurable solution not from predefined but from object? + if device in predefined_modules: + if device == "debug_mem": + if node is None: + # Add new debug_mem + xbar["nodes"].append({ + "name": "debug_mem", + "type": "device", + "clock": xbar['clock'], + "reset": xbar['reset'], + "inst_type": predefined_modules["debug_mem"], + "addr_range": [OrderedDict([ + ("base_addr", top["debug_mem_base_addr"]), + ("size_byte", "0x1000"), + ])], + "xbar": False, + "stub": False, + "pipeline": "true", + "pipeline_byp": "true" + }) # yapf: disable + else: + # Update if exists + node["inst_type"] = predefined_modules["debug_mem"] + node["addr_range"] = [ + OrderedDict([("base_addr", top["debug_mem_base_addr"]), + ("size_byte", "0x1000")]) + ] + node["xbar"] = False + node["stub"] = False + process_pipeline_var(node) + else: + log.error("device %s shouldn't be host type" % device) + + return + + # case 3: not defined + # Crossbar check + log.error("Device %s doesn't exist in 'module', 'memory', predefined, " + "or as a node object" % device) + return + + # If we get here, inst points an instance of some block or memory. It + # shouldn't point at a crossbar (because that would imply a naming clash) + assert device_base not in other_xbars + base_addr, size_byte = lib.get_base_and_size(name_to_block, + inst, device_ifname) + addr_range = {"base_addr": hex(base_addr), "size_byte": hex(size_byte)} + + stub = not lib.is_inst(inst) + + if node is None: + log.error('Cannot connect to {!r} because ' + 'the crossbar defines no node for {!r}.' + .format(device, device_base)) + return + + node["inst_type"] = inst["type"] + node["addr_range"] = [addr_range] + node["xbar"] = False + node["stub"] = stub + process_pipeline_var(node) + + +def amend_xbar(top: Dict[str, object], + name_to_block: Dict[str, IpBlock], + xbar: Dict[str, object]): + """Amend crossbar informations to the top list + + Amended fields + - clock: Adopt from module clock if exists + - inst_type: Module instance some module will be hard-coded + the tool searches module list and memory list then put here + - base_addr: from top["module"] + - size: from top["module"] + """ + xbar_list = [x["name"] for x in top["xbar"]] + if not xbar["name"] in xbar_list: + log.info( + "Xbar %s doesn't belong to the top %s. Check if the xbar doesn't need" + % (xbar["name"], top["name"])) + return + + topxbar = list( + filter(lambda node: node["name"] == xbar["name"], top["xbar"]))[0] + + topxbar["connections"] = deepcopy(xbar["connections"]) + if "nodes" in xbar: + topxbar["nodes"] = deepcopy(xbar["nodes"]) + else: + topxbar["nodes"] = [] + + # xbar primary clock and reset + topxbar["clock"] = xbar["clock_primary"] + topxbar["reset"] = xbar["reset_primary"] + + # Build nodes from 'connections' + device_nodes = set() + for host, devices in xbar["connections"].items(): + # add host first + xbar_addhost(top, topxbar, host) + + # add device if doesn't exist + device_nodes.update(devices) + + other_xbars = [x["name"] + for x in top["xbar"] + if x["name"] != xbar["name"]] + + log.info(device_nodes) + for device in device_nodes: + xbar_adddevice(top, name_to_block, topxbar, other_xbars, device) + + +def xbar_cross(xbar, xbars): + """Check if cyclic dependency among xbars + + And gather the address range for device port (to another Xbar) + + @param node_name if not "", the function only search downstream + devices starting from the node_name + @param visited The nodes it visited to reach this port. If any + downstream port from node_name in visited, it means + circular path exists. It should be fatal error. + """ + # Step 1: Visit devices (gather the address range) + log.info("Processing circular path check for {}".format(xbar["name"])) + addr = [] + for node in [ + x for x in xbar["nodes"] + if x["type"] == "device" and "xbar" in x and x["xbar"] is False + ]: + addr.extend(node["addr_range"]) + + # Step 2: visit xbar device ports + xbar_nodes = [ + x for x in xbar["nodes"] + if x["type"] == "device" and "xbar" in x and x["xbar"] is True + ] + + # Now call function to get the device range + # the node["name"] is used to find the host_xbar and its connection. The + # assumption here is that there's only one connection from crossbar A to + # crossbar B. + # + # device_xbar is the crossbar has a device port with name as node["name"]. + # host_xbar is the crossbar has a host port with name as node["name"]. + for node in xbar_nodes: + xbar_addr = xbar_cross_node(node["name"], xbar, xbars, visited=[]) + node["addr_range"] = xbar_addr + + +def xbar_cross_node(node_name, device_xbar, xbars, visited=[]): + # 1. Get the connected xbar + host_xbars = [x for x in xbars if x["name"] == node_name] + assert len(host_xbars) == 1 + host_xbar = host_xbars[0] + + log.info("Processing node {} in Xbar {}.".format(node_name, + device_xbar["name"])) + result = [] # [(base_addr, size), .. ] + # Sweep the devices using connections and gather the address. + # If the device is another xbar, call recursive + visited.append(host_xbar["name"]) + devices = host_xbar["connections"][device_xbar["name"]] + + for node in host_xbar["nodes"]: + if not node["name"] in devices: + continue + if "xbar" in node and node["xbar"] is True: + if "addr_range" not in node: + # Deeper dive into another crossbar + xbar_addr = xbar_cross_node(node["name"], host_xbar, xbars, + visited) + node["addr_range"] = xbar_addr + + result.extend(deepcopy(node["addr_range"])) + + visited.pop() + + return result + + +# find the first instance name of a given type +def _find_module_name(modules, module_type): + for m in modules: + if m['type'] == module_type: + return m['name'] + + return None + + +def amend_clocks(top: OrderedDict): + """Add a list of clocks to each clock group + Amend the clock connections of each entry to reflect the actual gated clock + """ + clks_attr = top['clocks'] + clk_paths = clks_attr['hier_paths'] + clkmgr_name = _find_module_name(top['module'], 'clkmgr') + groups_in_top = [x["name"].lower() for x in clks_attr['groups']] + exported_clks = OrderedDict() + trans_eps = [] + + # Assign default parameters to source clocks + for src in clks_attr['srcs']: + if 'derived' not in src: + src['derived'] = "no" + src['params'] = OrderedDict() + + # Default assignments + for group in clks_attr['groups']: + + # if unique not defined, it defaults to 'no' + if 'unique' not in group: + group['unique'] = "no" + + # if no hardwired clocks, define an empty set + group['clocks'] = OrderedDict( + ) if 'clocks' not in group else group['clocks'] + + for ep in top['module'] + top['memory'] + top['xbar']: + + clock_connections = OrderedDict() + + # Ensure each module has a default case + export_if = ep.get('clock_reset_export', []) + + # if no clock group assigned, default is unique + ep['clock_group'] = 'secure' if 'clock_group' not in ep else ep[ + 'clock_group'] + ep_grp = ep['clock_group'] + + # if ep is in the transactional group, collect into list below + if ep['clock_group'] == 'trans': + trans_eps.append(ep['name']) + + # end point names and clocks + ep_name = ep['name'] + ep_clks = [] + + # clock group index + cg_idx = groups_in_top.index(ep_grp) + + # unique property of each group + unique = clks_attr['groups'][cg_idx]['unique'] + + # src property of each group + src = clks_attr['groups'][cg_idx]['src'] + + for port, clk in ep['clock_srcs'].items(): + ep_clks.append(clk) + + name = '' + hier_name = clk_paths[src] + + if src == 'ext': + # clock comes from top ports + if clk == 'main': + name = "i" + else: + name = "{}_i".format(clk) + + elif unique == "yes": + # new unqiue clock name + name = "{}_{}".format(clk, ep_name) + + else: + # new group clock name + name = "{}_{}".format(clk, ep_grp) + + clk_name = "clk_" + name + + # add clock to a particular group + clks_attr['groups'][cg_idx]['clocks'][clk_name] = clk + + # add clock connections + clock_connections[port] = hier_name + clk_name + + # clocks for this module are exported + for intf in export_if: + log.info("{} export clock name is {}".format(ep_name, name)) + + # create dict entry if it does not exit + if intf not in exported_clks: + exported_clks[intf] = OrderedDict() + + # if first time encounter end point, declare + if ep_name not in exported_clks[intf]: + exported_clks[intf][ep_name] = [] + + # append clocks + exported_clks[intf][ep_name].append(name) + + # Add to endpoint structure + ep['clock_connections'] = clock_connections + + # add entry to top level json + top['exported_clks'] = exported_clks + + # add entry to inter_module automatically + for intf in top['exported_clks']: + top['inter_module']['external']['{}.clocks_{}'.format( + clkmgr_name, intf)] = "clks_{}".format(intf) + + # add to intermodule connections + for ep in trans_eps: + entry = ep + ".idle" + top['inter_module']['connect']['{}.idle'.format(clkmgr_name)].append(entry) + + +def amend_resets(top): + """Generate exported reset structure and automatically connect to + intermodule. + """ + + rstmgr_name = _find_module_name(top['module'], 'rstmgr') + + # Generate exported reset list + exported_rsts = OrderedDict() + for module in top["module"]: + + # This code is here to ensure if amend_clocks/resets switched order + # everything would still work + export_if = module.get('clock_reset_export', []) + + # There may be multiple export interfaces + for intf in export_if: + # create dict entry if it does not exit + if intf not in exported_rsts: + exported_rsts[intf] = OrderedDict() + + # grab directly from reset_connections definition + rsts = [rst for rst in module['reset_connections'].values()] + exported_rsts[intf][module['name']] = rsts + + # add entry to top level json + top['exported_rsts'] = exported_rsts + + # add entry to inter_module automatically + for intf in top['exported_rsts']: + top['inter_module']['external']['{}.resets_{}'.format( + rstmgr_name, intf)] = "rsts_{}".format(intf) + """Discover the full path and selection to each reset connection. + This is done by modifying the reset connection of each end point. + """ + for end_point in top['module'] + top['memory'] + top['xbar']: + for port, net in end_point['reset_connections'].items(): + reset_path = lib.get_reset_path(net, end_point['domain'], + top['resets']) + end_point['reset_connections'][port] = reset_path + + # reset paths are still needed temporarily until host only modules are properly automated + reset_paths = OrderedDict() + reset_hiers = top["resets"]['hier_paths'] + + for reset in top["resets"]["nodes"]: + if "type" not in reset: + log.error("{} missing type field".format(reset["name"])) + return + + if reset["type"] == "top": + reset_paths[reset["name"]] = "{}rst_{}_n".format( + reset_hiers["top"], reset["name"]) + + elif reset["type"] == "ext": + reset_paths[reset["name"]] = reset_hiers["ext"] + reset['name'] + elif reset["type"] == "int": + log.info("{} used as internal reset".format(reset["name"])) + else: + log.error("{} type is invalid".format(reset["type"])) + + top["reset_paths"] = reset_paths + + return + + +def ensure_interrupt_modules(top: OrderedDict, name_to_block: Dict[str, IpBlock]): + '''Populate top['interrupt_module'] if necessary + + Do this by adding each module in top['modules'] that defines at least one + interrupt. + + ''' + if 'interrupt_module' in top: + return + + modules = [] + for module in top['module']: + block = name_to_block[module['type']] + if block.interrupts: + modules.append(module['name']) + + top['interrupt_module'] = modules + + +def amend_interrupt(top: OrderedDict, name_to_block: Dict[str, IpBlock]): + """Check interrupt_module if exists, or just use all modules + """ + ensure_interrupt_modules(top, name_to_block) + + if "interrupt" not in top or top["interrupt"] == "": + top["interrupt"] = [] + + for m in top["interrupt_module"]: + ips = list(filter(lambda module: module["name"] == m, top["module"])) + if len(ips) == 0: + log.warning( + "Cannot find IP %s which is used in the interrupt_module" % m) + continue + + ip = ips[0] + block = name_to_block[ip['type']] + + log.info("Adding interrupts from module %s" % ip["name"]) + for signal in block.interrupts: + sig_dict = signal.as_nwt_dict('interrupt') + qual = lib.add_module_prefix_to_signal(sig_dict, + module=m.lower()) + top["interrupt"].append(qual) + + +def ensure_alert_modules(top: OrderedDict, name_to_block: Dict[str, IpBlock]): + '''Populate top['alert_module'] if necessary + + Do this by adding each module in top['modules'] that defines at least one + alert. + + ''' + if 'alert_module' in top: + return + + modules = [] + for module in top['module']: + block = name_to_block[module['type']] + if block.alerts: + modules.append(module['name']) + + top['alert_module'] = modules + + +def amend_alert(top: OrderedDict, name_to_block: Dict[str, IpBlock]): + """Check interrupt_module if exists, or just use all modules + """ + ensure_alert_modules(top, name_to_block) + + if "alert" not in top or top["alert"] == "": + top["alert"] = [] + + # Find the alert handler and extract the name of its clock + alert_clock = None + for instance in top['module']: + if instance['type'].lower() == 'alert_handler': + alert_clock = instance['clock_srcs']['clk_i'] + break + assert alert_clock is not None + + for m in top["alert_module"]: + ips = list(filter(lambda module: module["name"] == m, top["module"])) + if len(ips) == 0: + log.warning("Cannot find IP %s which is used in the alert_module" % + m) + continue + + ip = ips[0] + block = name_to_block[ip['type']] + + log.info("Adding alert from module %s" % ip["name"]) + has_async_alerts = ip['clock_srcs']['clk_i'] != alert_clock + for alert in block.alerts: + alert_dict = alert.as_nwt_dict('alert') + alert_dict['async'] = '1' if has_async_alerts else '0' + qual_sig = lib.add_module_prefix_to_signal(alert_dict, + module=m.lower()) + top["alert"].append(qual_sig) + + +def amend_wkup(topcfg: OrderedDict, name_to_block: Dict[str, IpBlock]): + + pwrmgr_name = _find_module_name(topcfg['module'], 'pwrmgr') + + if "wakeups" not in topcfg or topcfg["wakeups"] == "": + topcfg["wakeups"] = [] + + # create list of wakeup signals + for m in topcfg["module"]: + log.info("Adding wakeup from module %s" % m["name"]) + block = name_to_block[m['type']] + for signal in block.wakeups: + log.info("Adding signal %s" % signal.name) + topcfg["wakeups"].append({ + 'name': signal.name, + 'width': str(signal.bits.width()), + 'module': m["name"] + }) + + # add wakeup signals to pwrmgr connections + signal_names = [ + "{}.{}".format(s["module"].lower(), s["name"].lower()) + for s in topcfg["wakeups"] + ] + + topcfg["inter_module"]["connect"]["{}.wakeups".format(pwrmgr_name)] = signal_names + log.info("Intermodule signals: {}".format( + topcfg["inter_module"]["connect"])) + + +# Handle reset requests from modules +def amend_reset_request(topcfg: OrderedDict, + name_to_block: Dict[str, IpBlock]): + + pwrmgr_name = _find_module_name(topcfg['module'], 'pwrmgr') + + if "reset_requests" not in topcfg or topcfg["reset_requests"] == "": + topcfg["reset_requests"] = [] + + # create list of reset signals + for m in topcfg["module"]: + log.info("Adding reset requests from module %s" % m["name"]) + block = name_to_block[m['type']] + for signal in block.reset_requests: + log.info("Adding signal %s" % signal.name) + topcfg["reset_requests"].append({ + 'name': signal.name, + 'width': str(signal.bits.width()), + 'module': m["name"] + }) + + # add reset requests to pwrmgr connections + signal_names = [ + "{}.{}".format(s["module"].lower(), s["name"].lower()) + for s in topcfg["reset_requests"] + ] + + topcfg["inter_module"]["connect"]["{}.rstreqs".format(pwrmgr_name)] = signal_names + log.info("Intermodule signals: {}".format( + topcfg["inter_module"]["connect"])) + + +def append_io_signal(temp: Dict, sig_inst: Dict) -> None: + '''Appends the signal to the correct list''' + if sig_inst['type'] == 'inout': + temp['inouts'].append(sig_inst) + if sig_inst['type'] == 'input': + temp['inputs'].append(sig_inst) + if sig_inst['type'] == 'output': + temp['outputs'].append(sig_inst) + + +def get_index_and_incr(ctrs: Dict, connection: str, io_dir: str) -> Dict: + '''Get correct index counter and increment''' + + if connection != 'muxed': + connection = 'dedicated' + + if io_dir in 'inout': + result = ctrs[connection]['inouts'] + ctrs[connection]['inouts'] += 1 + elif connection == 'muxed': + # For MIOs, the input/output arrays differ in RTL + # I.e., the input array contains {inputs, inouts}, whereas + # the output array contains {outputs, inouts}. + if io_dir == 'input': + result = ctrs[connection]['inputs'] + ctrs[connection]['inouts'] + ctrs[connection]['inputs'] += 1 + elif io_dir == 'output': + result = ctrs[connection]['outputs'] + ctrs[connection]['inouts'] + ctrs[connection]['outputs'] += 1 + else: + assert(0) # should not happen + else: + # For DIOs, the input/output arrays are identical in terms of index layout. + # Unused inputs are left unconnected and unused outputs are tied off. + if io_dir == 'input': + result = ctrs[connection]['inputs'] + ctrs[connection]['inouts'] + ctrs[connection]['inputs'] += 1 + elif io_dir == 'output': + result = (ctrs[connection]['outputs'] + + ctrs[connection]['inouts'] + + ctrs[connection]['inputs']) + ctrs[connection]['outputs'] += 1 + else: + assert(0) # should not happen + + return result + + +def amend_pinmux_io(top: Dict, name_to_block: Dict[str, IpBlock]): + """ Process pinmux/pinout configuration and assign available IOs + """ + pinmux = top['pinmux'] + pinout = top['pinout'] + targets = top['targets'] + + temp = {} + temp['inouts'] = [] + temp['inputs'] = [] + temp['outputs'] = [] + + for sig in pinmux['signals']: + # Get the signal information from the IP block type of this instance/ + mod_name = sig['instance'] + m = lib.get_module_by_name(top, mod_name) + + if m is None: + raise SystemExit("Module {} is not searchable.".format(mod_name)) + + block = name_to_block[m['type']] + + # If the signal is explicitly named. + if sig['port'] != '': + + # If this is a bus signal with explicit indexes. + if '[' in sig['port']: + name_split = sig['port'].split('[') + sig_name = name_split[0] + idx = int(name_split[1][:-1]) + else: + idx = -1 + sig_name = sig['port'] + + sig_inst = deepcopy(block.get_signal_by_name_as_dict(sig_name)) + + if idx >= 0 and idx >= sig_inst['width']: + raise SystemExit("Index {} is out of bounds for signal {}" + " with width {}.".format(idx, sig_name, sig_inst['width'])) + if idx == -1 and sig_inst['width'] != 1: + raise SystemExit("Bus signal {} requires an index.".format(sig_name)) + + # If we got this far we know that the signal is valid and exists. + # Augment this signal instance with additional information. + sig_inst.update({'idx': idx, + 'pad': sig['pad'], + 'attr': sig['attr'], + 'connection': sig['connection']}) + sig_inst['name'] = mod_name + '_' + sig_inst['name'] + append_io_signal(temp, sig_inst) + + # Otherwise the name is a wildcard for selecting all available IO signals + # of this block and we need to extract them here one by one signals here. + else: + sig_list = deepcopy(block.get_signals_as_list_of_dicts()) + + for sig_inst in sig_list: + # If this is a multibit signal, unroll the bus and + # generate a single bit IO signal entry for each one. + if sig_inst['width'] > 1: + for idx in range(sig_inst['width']): + sig_inst_copy = deepcopy(sig_inst) + sig_inst_copy.update({'idx': idx, + 'pad': sig['pad'], + 'attr': sig['attr'], + 'connection': sig['connection']}) + sig_inst_copy['name'] = sig['instance'] + '_' + sig_inst_copy['name'] + append_io_signal(temp, sig_inst_copy) + else: + sig_inst.update({'idx': -1, + 'pad': sig['pad'], + 'attr': sig['attr'], + 'connection': sig['connection']}) + sig_inst['name'] = sig['instance'] + '_' + sig_inst['name'] + append_io_signal(temp, sig_inst) + + # Now that we've collected all input and output signals, + # we can go through once again and stack them into one unified + # list, and calculate MIO/DIO global indices. + pinmux['ios'] = (temp['inouts'] + + temp['inputs'] + + temp['outputs']) + + # Remember these counts to facilitate the RTL generation + pinmux['io_counts'] = {'dedicated': {'inouts': 0, 'inputs': 0, 'outputs': 0, 'pads': 0}, + 'muxed': {'inouts': 0, 'inputs': 0, 'outputs': 0, 'pads': 0}} + + for sig in pinmux['ios']: + glob_idx = get_index_and_incr(pinmux['io_counts'], sig['connection'], sig['type']) + sig['glob_idx'] = glob_idx + + # Calculate global indices for pads. + j = k = 0 + for pad in pinout['pads']: + if pad['connection'] == 'muxed': + pad['idx'] = j + j += 1 + else: + pad['idx'] = k + k += 1 + pinmux['io_counts']['muxed']['pads'] = j + pinmux['io_counts']['dedicated']['pads'] = k + + # For each target configuration, calculate the special signal indices. + known_muxed_pads = {} + for pad in pinout['pads']: + if pad['connection'] == 'muxed': + known_muxed_pads[pad['name']] = pad + + known_mapped_dio_pads = {} + for sig in pinmux['ios']: + if sig['connection'] in ['muxed', 'manual']: + continue + if sig['pad'] in known_mapped_dio_pads: + raise SystemExit('Cannot have multiple IOs mapped to the same DIO pad {}' + .format(sig['pad'])) + known_mapped_dio_pads[sig['pad']] = sig + + for target in targets: + for entry in target['pinmux']['special_signals']: + # If this is a muxed pad, the resolution is + # straightforward. I.e., we just assign the MIO index. + if entry['pad'] in known_muxed_pads: + entry['idx'] = known_muxed_pads[entry['pad']]['idx'] + # Otherwise we need to find out which DIO this pad is mapped to. + # Note that we can't have special_signals that are manual, since + # there needs to exist a DIO connection. + elif entry['pad'] in known_mapped_dio_pads: + # This index refers to the stacked {dio, mio} array + # on the chip-level, hence we have to add the amount of MIO pads. + idx = (known_mapped_dio_pads[entry['pad']]['glob_idx'] + + pinmux['io_counts']['muxed']['pads']) + entry['idx'] = idx + else: + assert(0) # Entry should be guaranteed to exist at this point + + +def merge_top(topcfg: OrderedDict, + name_to_block: Dict[str, IpBlock], + xbarobjs: OrderedDict) -> OrderedDict: + + # Combine ip cfg into topcfg + elaborate_instances(topcfg, name_to_block) + + # Create clock connections for each block + # Assign clocks into appropriate groups + # Note, elaborate_instances references clock information to establish async handling + # as part of alerts. + # amend_clocks(topcfg) + + # Combine the wakeups + amend_wkup(topcfg, name_to_block) + amend_reset_request(topcfg, name_to_block) + + # Combine the interrupt (should be processed prior to xbar) + amend_interrupt(topcfg, name_to_block) + + # Combine the alert (should be processed prior to xbar) + amend_alert(topcfg, name_to_block) + + # Creates input/output list in the pinmux + log.info("Processing PINMUX") + amend_pinmux_io(topcfg, name_to_block) + + # Combine xbar into topcfg + for xbar in xbarobjs: + amend_xbar(topcfg, name_to_block, xbar) + + # 2nd phase of xbar (gathering the devices address range) + for xbar in topcfg["xbar"]: + xbar_cross(xbar, topcfg["xbar"]) + + # Add path names to declared resets. + # Declare structure for exported resets. + amend_resets(topcfg) + + # remove unwanted fields 'debug_mem_base_addr' + topcfg.pop('debug_mem_base_addr', None) + + return topcfg diff --git a/hw/vendored_ips/gpio/util/reggen/topgen/templates/README.md b/hw/vendored_ips/gpio/util/reggen/topgen/templates/README.md new file mode 100644 index 00000000..afd488ac --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/topgen/templates/README.md @@ -0,0 +1,4 @@ +# OpenTitan topgen templates + +This directory contains templates used by topgen to assembly a chip toplevel. + diff --git a/hw/vendored_ips/gpio/util/reggen/topgen/templates/chip_env_pkg__params.sv.tpl b/hw/vendored_ips/gpio/util/reggen/topgen/templates/chip_env_pkg__params.sv.tpl new file mode 100644 index 00000000..34079006 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/topgen/templates/chip_env_pkg__params.sv.tpl @@ -0,0 +1,17 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Generated by topgen.py + +parameter string LIST_OF_ALERTS[] = { +% for alert in top["alert"]: + % if loop.last: + "${alert["name"]}" + % else: + "${alert["name"]}", + % endif +% endfor +}; + +parameter uint NUM_ALERTS = ${len(top["alert"])}; diff --git a/hw/vendored_ips/gpio/util/reggen/topgen/templates/chiplevel.sv.tpl b/hw/vendored_ips/gpio/util/reggen/topgen/templates/chiplevel.sv.tpl new file mode 100644 index 00000000..aafec5bf --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/topgen/templates/chiplevel.sv.tpl @@ -0,0 +1,1218 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +${gencmd} +<% +import re +import topgen.lib as lib +from copy import deepcopy + +# Provide shortcuts for some commonly used variables +pinmux = top['pinmux'] +pinout = top['pinout'] + +num_mio_inputs = pinmux['io_counts']['muxed']['inouts'] + \ + pinmux['io_counts']['muxed']['inputs'] +num_mio_outputs = pinmux['io_counts']['muxed']['inouts'] + \ + pinmux['io_counts']['muxed']['outputs'] +num_mio_pads = pinmux['io_counts']['muxed']['pads'] + +num_dio_inputs = pinmux['io_counts']['dedicated']['inouts'] + \ + pinmux['io_counts']['dedicated']['inputs'] +num_dio_outputs = pinmux['io_counts']['dedicated']['inouts'] + \ + pinmux['io_counts']['dedicated']['outputs'] +num_dio_total = pinmux['io_counts']['dedicated']['inouts'] + \ + pinmux['io_counts']['dedicated']['inputs'] + \ + pinmux['io_counts']['dedicated']['outputs'] + +def get_dio_sig(pinmux: {}, pad: {}): + '''Get DIO signal associated with this pad or return None''' + for sig in pinmux["ios"]: + if sig["connection"] == "direct" and pad["name"] == sig["pad"]: + return sig + else: + return None + +# Modify the pad lists on the fly, based on target config +maxwidth = 0 +muxed_pads = [] +dedicated_pads = [] +k = 0 +for pad in pinout["pads"]: + if pad["connection"] == "muxed": + if pad["name"] not in target["pinout"]["remove_pads"]: + maxwidth = max(maxwidth, len(pad["name"])) + muxed_pads.append(pad) + else: + k = pad["idx"] + if pad["name"] not in target["pinout"]["remove_pads"]: + maxwidth = max(maxwidth, len(pad["name"])) + dedicated_pads.append(pad) + +for pad in target["pinout"]["add_pads"]: + # Since these additional pads have not been elaborated in the merge phase, + # we need to add their global index here. + amended_pad = deepcopy(pad) + amended_pad.update({"idx" : k}) + dedicated_pads.append(pad) + k += 1 + +num_im = sum([x["width"] if "width" in x else 1 for x in top["inter_signal"]["external"]]) + +max_sigwidth = max([x["width"] if "width" in x else 1 for x in top["pinmux"]["ios"]]) +max_sigwidth = len("{}".format(max_sigwidth)) + +clks_attr = top['clocks'] +cpu_clk = top['clocks']['hier_paths']['top'] + "clk_proc_main" +cpu_rst = top["reset_paths"]["sys"] +dm_rst = top["reset_paths"]["lc"] +esc_clk = top['clocks']['hier_paths']['top'] + "clk_io_div4_timers" +esc_rst = top["reset_paths"]["sys_io_div4"] + +unused_resets = lib.get_unused_resets(top) +unused_im_defs, undriven_im_defs = lib.get_dangling_im_def(top["inter_signal"]["definitions"]) + +%>\ +% if target["name"] != "asic": +module chip_${top["name"]}_${target["name"]} #( + // Path to a VMEM file containing the contents of the boot ROM, which will be + // baked into the FPGA bitstream. + parameter BootRomInitFile = "boot_rom_fpga_${target["name"]}.32.vmem", + // Path to a VMEM file containing the contents of the emulated OTP, which will be + // baked into the FPGA bitstream. + parameter OtpCtrlMemInitFile = "otp_img_fpga_${target["name"]}.vmem", + // TODO: Remove this 0 once infra is ready + parameter bit RomCtrlSkipCheck = 1 +) ( +% else: +module chip_${top["name"]}_${target["name"]} #( + // TODO: Remove this 0 once infra is ready + parameter bit RomCtrlSkipCheck = 1 +) ( +% endif +<% + +%>\ + // Dedicated Pads +% for pad in dedicated_pads: +<% + sig = get_dio_sig(pinmux, pad) + if sig is not None: + comment = "// Dedicated Pad for {}".format(sig["name"]) + else: + comment = "// Manual Pad" +%>\ + inout ${pad["name"]}, ${comment} +% endfor + + // Muxed Pads +% for pad in muxed_pads: + inout ${pad["name"]}${" " if loop.last else ","} // MIO Pad ${pad["idx"]} +% endfor +); + + import top_${top["name"]}_pkg::*; + import prim_pad_wrapper_pkg::*; + +% if target["pinmux"]["special_signals"]: + //////////////////////////// + // Special Signal Indices // + //////////////////////////// + + % for entry in target["pinmux"]["special_signals"]: +<% param_name = (lib.Name.from_snake_case(entry["name"]) + + lib.Name(["pad", "idx"])).as_camel_case() +%>\ + parameter int ${param_name} = ${entry["idx"]}; + % endfor +% endif + + // DFT and Debug signal positions in the pinout. + localparam pinmux_pkg::target_cfg_t PinmuxTargetCfg = '{ + tck_idx: TckPadIdx, + tms_idx: TmsPadIdx, + trst_idx: TrstNPadIdx, + tdi_idx: TdiPadIdx, + tdo_idx: TdoPadIdx, + tap_strap0_idx: Tap0PadIdx, + tap_strap1_idx: Tap1PadIdx, + dft_strap0_idx: Dft0PadIdx, + dft_strap1_idx: Dft1PadIdx, + // TODO: check whether there is a better way to pass these USB-specific params + usb_dp_idx: DioUsbdevDp, + usb_dn_idx: DioUsbdevDn, + usb_dp_pullup_idx: DioUsbdevDpPullup, + usb_dn_pullup_idx: DioUsbdevDnPullup, + // Pad types for attribute WARL behavior + dio_pad_type: { +<% + pad_attr = [] + for sig in list(reversed(top["pinmux"]["ios"])): + if sig["connection"] != "muxed": + pad_attr.append((sig['name'], sig["attr"])) +%>\ +% for name, attr in pad_attr: + ${attr}${" " if loop.last else ","} // DIO ${name} +% endfor + }, + mio_pad_type: { +<% + pad_attr = [] + for pad in list(reversed(pinout["pads"])): + if pad["connection"] == "muxed": + pad_attr.append(pad["type"]) +%>\ +% for attr in pad_attr: + ${attr}${" " if loop.last else ","} // MIO Pad ${len(pad_attr) - loop.index - 1} +% endfor + } + }; + + //////////////////////// + // Signal definitions // + //////////////////////// + + pad_attr_t [pinmux_reg_pkg::NMioPads-1:0] mio_attr; + pad_attr_t [pinmux_reg_pkg::NDioPads-1:0] dio_attr; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_out; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_oe; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_in; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_in_raw; + logic [pinmux_reg_pkg::NDioPads-1:0] dio_out; + logic [pinmux_reg_pkg::NDioPads-1:0] dio_oe; + logic [pinmux_reg_pkg::NDioPads-1:0] dio_in; + + logic unused_mio_in_raw; + assign unused_mio_in_raw = ^mio_in_raw; + + // Manual pads +% for pad in dedicated_pads: +<% + pad_prefix = pad["name"].lower() +%>\ +% if not get_dio_sig(pinmux, pad): + logic manual_in_${pad_prefix}, manual_out_${pad_prefix}, manual_oe_${pad_prefix}; +% endif +% endfor + +% for pad in dedicated_pads: +<% + pad_prefix = pad["name"].lower() +%>\ +% if not get_dio_sig(pinmux, pad): + pad_attr_t manual_attr_${pad_prefix}; +% endif +% endfor + +% if target["pinout"]["remove_pads"]: + ///////////////////////// + // Stubbed pad tie-off // + ///////////////////////// + + // Only signals going to non-custom pads need to be tied off. + logic [${len(pinout["pads"])-1}:0] unused_sig; +% for pad in pinout["pads"]: + % if pad["connection"] == 'muxed': + % if pad["name"] in target["pinout"]["remove_pads"]: + assign mio_in[${pad["idx"]}] = 1'b0; + assign unused_sig[${loop.index}] = mio_out[${pad["idx"]}] ^ mio_oe[${pad["idx"]}]; + % endif + % else: + % if pad["name"] in target["pinout"]["remove_pads"]: +<% + ## Only need to tie off if this is not a custom pad. + sig = get_dio_sig(pinmux, pad) + if sig is not None: + sig_index = lib.get_io_enum_literal(sig, 'dio') +%>\ + % if sig is not None: + assign dio_in[${lib.get_io_enum_literal(sig, 'dio')}] = 1'b0; + assign unused_sig[${loop.index}] = dio_out[${sig_index}] ^ dio_oe[${sig_index}]; + % endif + % endif + % endif +% endfor +%endif + + ////////////////////// + // Padring Instance // + ////////////////////// + +% if target["name"] == "asic": + // AST signals needed in padring + ast_pkg::ast_clks_t ast_base_clks; + logic scan_rst_n; + lc_ctrl_pkg::lc_tx_t scanmode; +% endif + + padring #( + // Padring specific counts may differ from pinmux config due + // to custom, stubbed or added pads. + .NDioPads(${len(dedicated_pads)}), + .NMioPads(${len(muxed_pads)}), +% if target["name"] == "asic": + .PhysicalPads(1), + .NIoBanks(int'(IoBankCount)), + .DioScanRole ({ +% for pad in list(reversed(dedicated_pads)): + scan_role_pkg::${lib.Name.from_snake_case('dio_pad_' + pad["name"] + '_scan_role').as_camel_case()}${"" if loop.last else ","} +% endfor + }), + .MioScanRole ({ +% for pad in list(reversed(muxed_pads)): + scan_role_pkg::${lib.Name.from_snake_case('mio_pad_' + pad["name"] + '_scan_role').as_camel_case()}${"" if loop.last else ","} +% endfor + }), + .DioPadBank ({ +% for pad in list(reversed(dedicated_pads)): + ${lib.Name.from_snake_case('io_bank_' + pad["bank"]).as_camel_case()}${" " if loop.last else ","} // ${pad['name']} +% endfor + }), + .MioPadBank ({ +% for pad in list(reversed(muxed_pads)): + ${lib.Name.from_snake_case('io_bank_' + pad["bank"]).as_camel_case()}${" " if loop.last else ","} // ${pad['name']} +% endfor + }), +% endif +\ +\ + .DioPadType ({ +% for pad in list(reversed(dedicated_pads)): + ${pad["type"]}${" " if loop.last else ","} // ${pad['name']} +% endfor + }), + .MioPadType ({ +% for pad in list(reversed(muxed_pads)): + ${pad["type"]}${" " if loop.last else ","} // ${pad['name']} +% endfor + }) + ) u_padring ( + // This is only used for scan and DFT purposes +% if target["name"] == "asic": + .clk_scan_i ( ast_base_clks.clk_sys ), + .scanmode_i ( scanmode ), +% else: + .clk_scan_i ( 1'b0 ), + .scanmode_i ( lc_ctrl_pkg::Off ), + % endif + .dio_in_raw_o ( ), + .mio_in_raw_o ( mio_in_raw ), + // Chip IOs + .dio_pad_io ({ +% for pad in list(reversed(dedicated_pads)): + ${pad["name"]}${"" if loop.last else ","} +% endfor + }), + + .mio_pad_io ({ +% for pad in list(reversed(muxed_pads)): + ${pad["name"]}${"" if loop.last else ","} +% endfor + }), + + // Core-facing +% for port in ["in_o", "out_i", "oe_i", "attr_i"]: + .dio_${port} ({ + % for pad in list(reversed(dedicated_pads)): + <% + sig = get_dio_sig(pinmux, pad) + %>\ + % if sig is None: + manual_${port[:-2]}_${pad["name"].lower()}${"" if loop.last else ","} + % else: + dio_${port[:-2]}[${lib.get_io_enum_literal(sig, 'dio')}]${"" if loop.last else ","} + % endif + % endfor + }), +% endfor + +% for port in ["in_o", "out_i", "oe_i", "attr_i"]: +<% + sig_name = 'mio_' + port[:-2] + indices = list(reversed(list(pad['idx'] for pad in muxed_pads))) +%>\ + .mio_${port} (${lib.make_bit_concatenation(sig_name, indices, 6)})${"" if loop.last else ","} +% endfor + ); + + +################################################################### +## USB for CW305 ## +################################################################### +% if target["name"] == "cw305": + // Connect the DP pad + assign dio_in[DioUsbdevDp] = manual_in_usb_p; + assign manual_out_usb_p = dio_out[DioUsbdevDp]; + assign manual_oe_usb_p = dio_oe[DioUsbdevDp]; + assign manual_attr_usb_p = dio_attr[DioUsbdevDp]; + + // Connect the DN pad + assign dio_in[DioUsbdevDn] = manual_in_usb_n; + assign manual_out_usb_n = dio_out[DioUsbdevDn]; + assign manual_oe_usb_n = dio_oe[DioUsbdevDn]; + assign manual_attr_usb_n = dio_attr[DioUsbdevDn]; + + // Connect sense pad + assign dio_in[DioUsbdevSense] = manual_in_io_usb_sense0; + assign manual_out_io_usb_sense0 = dio_out[DioUsbdevSense]; + assign manual_oe_io_usb_sense0 = dio_oe[DioUsbdevSense]; + assign manual_attr_io_sense0 = dio_attr[DioUsbdevSense]; + + // Connect DN pullup + assign dio_in[DioUsbdevDnPullup] = manual_in_io_usb_dnpullup0; + assign manual_out_io_usb_dnpullup0 = dio_out[DioUsbdevDnPullup]; + assign manual_oe_io_usb_dnpullup0 = dio_oe[DioUsbdevDnPullup]; + assign manual_attr_io_dnpullup0 = dio_attr[DioUsbdevDnPullup]; + + // Connect DP pullup + assign dio_in[DioUsbdevDpPullup] = manual_in_io_usb_dppullup0; + assign manual_out_io_usb_dppullup0 = dio_out[DioUsbdevDpPullup]; + assign manual_oe_io_usb_dppullup0 = dio_oe[DioUsbdevDpPullup]; + assign manual_attr_io_dppullup0 = dio_attr[DioUsbdevDpPullup]; + + // Tie-off unused signals + assign dio_in[DioUsbdevSe0] = 1'b0; + assign dio_in[DioUsbdevTxModeSe] = 1'b0; + assign dio_in[DioUsbdevSuspend] = 1'b0; + + logic unused_usb_sigs; + assign unused_usb_sigs = ^{ + // SE0 + dio_out[DioUsbdevSe0], + dio_oe[DioUsbdevSe0], + dio_attr[DioUsbdevSe0], + // TX Mode + dio_out[DioUsbdevTxModeSe], + dio_oe[DioUsbdevTxModeSe], + dio_attr[DioUsbdevTxModeSe], + // Suspend + dio_out[DioUsbdevSuspend], + dio_oe[DioUsbdevSuspend], + dio_attr[DioUsbdevSuspend], + // D is used as an input only + dio_out[DioUsbdevD], + dio_oe[DioUsbdevD], + dio_attr[DioUsbdevD] + }; + +% endif + +################################################################### +## USB for Nexysvideo ## +################################################################### +% if target["name"] == "nexysvideo": + + ///////////////////// + // USB Overlay Mux // + ///////////////////// + + // TODO: generalize this USB mux code and align with other tops. + + // Software can enable the pinflip feature inside usbdev. + // The example hello_usbdev does this based on GPIO0 (a switch on the board) + // + // Here, we use the state of the DN pullup to effectively undo the + // swapping such that the PCB always sees the unflipped D+/D-. We + // could do the same inside the .xdc file but then two FPGA + // bitstreams would be needed for testing. + // + // dio_in/out/oe map is: PADS <- _padring <- JTAG mux -> _umux -> USB mux -> _core + + // Split out for differential PHY testing + + // Outputs always drive and just copy the value + // Let them go to the normal place too because it won't do any harm + // and it simplifies the changes needed + + // The output enable for IO_USB_DNPULLUP0 is used to decide whether we need to undo the swapping. + logic undo_swap; + assign undo_swap = dio_oe[DioUsbdevDnPullup]; + + // GPIO[2] = Switch 2 on board is used to select using the UPHY + // Keep GPIO[1] for selecting differential in sw + logic use_uphy; + assign use_uphy = mio_in[MioPadIoa2]; + + // DioUsbdevDn + assign manual_attr_usb_n = '0; + assign manual_attr_io_uphy_dn_tx = '0; + + assign manual_out_io_uphy_dn_tx = manual_out_usb_n; + assign manual_out_usb_n = undo_swap ? dio_out[DioUsbdevDp] : + dio_out[DioUsbdevDn]; + + assign manual_oe_io_uphy_dn_tx = manual_oe_usb_n; + assign manual_oe_usb_n = undo_swap ? dio_oe[DioUsbdevDp] : + dio_oe[DioUsbdevDn]; + + assign dio_in[DioUsbdevDn] = use_uphy ? + (undo_swap ? manual_in_io_uphy_dp_rx : + manual_in_io_uphy_dn_rx) : + (undo_swap ? manual_in_usb_p : + manual_in_usb_n); + // DioUsbdevDp + assign manual_attr_usb_p = '0; + assign manual_attr_io_uphy_dp_tx = '0; + + assign manual_out_io_uphy_dp_tx = manual_out_usb_p; + assign manual_out_usb_p = undo_swap ? dio_out[DioUsbdevDn] : + dio_out[DioUsbdevDp]; + + assign manual_oe_io_uphy_dp_tx = manual_oe_usb_p; + assign manual_oe_usb_p = undo_swap ? dio_oe[DioUsbdevDn] : + dio_oe[DioUsbdevDp]; + assign dio_in[DioUsbdevDp] = use_uphy ? + (undo_swap ? manual_in_io_uphy_dn_rx : + manual_in_io_uphy_dp_rx) : + (undo_swap ? manual_in_usb_n : + manual_in_usb_p); + // DioUsbdevD + // This is not connected at the moment + logic unused_out_usb_d; + assign unused_out_usb_d = dio_out[DioUsbdevD] ^ + dio_oe[DioUsbdevD]; + assign dio_in[DioUsbdevD] = use_uphy ? + (undo_swap ? ~manual_in_io_uphy_d_rx : + manual_in_io_uphy_d_rx) : + // This is not connected at the moment + (undo_swap ? 1'b1 : 1'b0); + assign manual_out_io_uphy_d_rx = 1'b0; + assign manual_oe_io_uphy_d_rx = 1'b0; + + // DioUsbdevDnPullup + assign manual_attr_io_usb_dnpullup0 = '0; + assign manual_out_io_usb_dnpullup0 = undo_swap ? dio_out[DioUsbdevDpPullup] : + dio_out[DioUsbdevDnPullup]; + assign manual_oe_io_usb_dnpullup0 = undo_swap ? dio_oe[DioUsbdevDpPullup] : + dio_oe[DioUsbdevDnPullup]; + assign dio_in[DioUsbdevDnPullup] = manual_in_io_usb_dnpullup0; + + // DioUsbdevDpPullup + assign manual_attr_io_usb_dppullup0 = '0; + assign manual_out_io_usb_dppullup0 = undo_swap ? dio_out[DioUsbdevDnPullup] : + dio_out[DioUsbdevDpPullup]; + assign manual_oe_io_usb_dppullup0 = undo_swap ? dio_oe[DioUsbdevDnPullup] : + dio_oe[DioUsbdevDpPullup]; + assign dio_in[DioUsbdevDpPullup] = manual_in_io_usb_dppullup0; + + // DioUsbdevSense + assign manual_out_io_usb_sense0 = dio_out[DioUsbdevSense]; + assign manual_oe_io_usb_sense0 = dio_oe[DioUsbdevSense]; + assign dio_in[DioUsbdevSense] = use_uphy ? manual_in_io_uphy_sense : + manual_in_io_usb_sense0; + assign manual_out_io_uphy_sense = 1'b0; + assign manual_oe_io_uphy_sense = 1'b0; + + // DioUsbdevRxEnable + assign dio_in[DioUsbdevRxEnable] = 1'b0; + + // Additional outputs for uphy + assign manual_oe_io_uphy_dppullup = 1'b1; + assign manual_out_io_uphy_dppullup = manual_out_io_usb_dppullup0 & + manual_oe_io_usb_dppullup0; + + logic unused_in_io_uphy_dppullup; + assign unused_in_io_uphy_dppullup = manual_in_io_uphy_dppullup; + + assign manual_oe_io_uphy_oe_n = 1'b1; + assign manual_out_io_uphy_oe_n = ~manual_oe_usb_p; + + logic unused_in_io_uphy_oe_n; + assign unused_in_io_uphy_oe_n = manual_in_io_uphy_oe_n; + +% endif + +################################################################### +## ASIC ## +################################################################### +% if target["name"] == "asic": + + ////////////////////////////////// + // Manual Pad / Signal Tie-offs // + ////////////////////////////////// + + assign manual_out_por_n = 1'b0; + assign manual_oe_por_n = 1'b0; + + assign manual_out_cc1 = 1'b0; + assign manual_oe_cc1 = 1'b0; + assign manual_out_cc2 = 1'b0; + assign manual_oe_cc2 = 1'b0; + + assign manual_out_flash_test_mode0 = 1'b0; + assign manual_oe_flash_test_mode0 = 1'b0; + assign manual_out_flash_test_mode1 = 1'b0; + assign manual_oe_flash_test_mode1 = 1'b0; + assign manual_out_flash_test_volt = 1'b0; + assign manual_oe_flash_test_volt = 1'b0; + assign manual_out_otp_ext_volt = 1'b0; + assign manual_oe_otp_ext_volt = 1'b0; + + // These pad attributes currently tied off permanently (these are all input-only pads). + assign manual_attr_por_n = '0; + assign manual_attr_cc1 = '0; + assign manual_attr_cc2 = '0; + assign manual_attr_flash_test_mode0 = '0; + assign manual_attr_flash_test_mode1 = '0; + assign manual_attr_flash_test_volt = '0; + assign manual_attr_otp_ext_volt = '0; + + logic unused_manual_sigs; + assign unused_manual_sigs = ^{ + manual_in_cc2, + manual_in_cc1, + manual_in_flash_test_volt, + manual_in_flash_test_mode0, + manual_in_flash_test_mode1, + manual_in_otp_ext_volt + }; + + /////////////////////////////// + // Differential USB Receiver // + /////////////////////////////// + + // TODO: generalize this USB mux code and align with other tops. + + // Connect the DP pad + assign dio_in[DioUsbdevDp] = manual_in_usb_p; + assign manual_out_usb_p = dio_out[DioUsbdevDp]; + assign manual_oe_usb_p = dio_oe[DioUsbdevDp]; + assign manual_attr_usb_p = dio_attr[DioUsbdevDp]; + + // Connect the DN pad + assign dio_in[DioUsbdevDn] = manual_in_usb_n; + assign manual_out_usb_n = dio_out[DioUsbdevDn]; + assign manual_oe_usb_n = dio_oe[DioUsbdevDn]; + assign manual_attr_usb_n = dio_attr[DioUsbdevDn]; + + // Pullups + logic usb_pullup_p_en, usb_pullup_n_en; + assign usb_pullup_p_en = dio_out[DioUsbdevDpPullup] & dio_oe[DioUsbdevDpPullup]; + assign usb_pullup_n_en = dio_out[DioUsbdevDnPullup] & dio_oe[DioUsbdevDnPullup]; + + logic usb_rx_enable; + assign usb_rx_enable = dio_out[DioUsbdevRxEnable] & dio_oe[DioUsbdevRxEnable]; + + logic [ast_pkg::UsbCalibWidth-1:0] usb_io_pu_cal; + + // pwrmgr interface + pwrmgr_pkg::pwr_ast_req_t base_ast_pwr; + pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr; + + prim_usb_diff_rx #( + .CalibW(ast_pkg::UsbCalibWidth) + ) u_prim_usb_diff_rx ( + .input_pi ( USB_P ), + .input_ni ( USB_N ), + .input_en_i ( usb_rx_enable ), + .core_pok_i ( ast_base_pwr.main_pok ), + .pullup_p_en_i ( usb_pullup_p_en ), + .pullup_n_en_i ( usb_pullup_n_en ), + .calibration_i ( usb_io_pu_cal ), + .input_o ( dio_in[DioUsbdevD] ) + ); + + // Tie-off unused signals + assign dio_in[DioUsbdevSense] = 1'b0; + assign dio_in[DioUsbdevSe0] = 1'b0; + assign dio_in[DioUsbdevDpPullup] = 1'b0; + assign dio_in[DioUsbdevDnPullup] = 1'b0; + assign dio_in[DioUsbdevTxModeSe] = 1'b0; + assign dio_in[DioUsbdevSuspend] = 1'b0; + assign dio_in[DioUsbdevRxEnable] = 1'b0; + + logic unused_usb_sigs; + assign unused_usb_sigs = ^{ + // Sense + dio_out[DioUsbdevSense], + dio_oe[DioUsbdevSense], + dio_attr[DioUsbdevSense], + // SE0 + dio_out[DioUsbdevSe0], + dio_oe[DioUsbdevSe0], + dio_attr[DioUsbdevSe0], + // TX Mode + dio_out[DioUsbdevTxModeSe], + dio_oe[DioUsbdevTxModeSe], + dio_attr[DioUsbdevTxModeSe], + // Suspend + dio_out[DioUsbdevSuspend], + dio_oe[DioUsbdevSuspend], + dio_attr[DioUsbdevSuspend], + // Rx enable + dio_attr[DioUsbdevRxEnable], + // D is used as an input only + dio_out[DioUsbdevD], + dio_oe[DioUsbdevD], + dio_attr[DioUsbdevD], + // Pullup/down + dio_attr[DioUsbdevDpPullup], + dio_attr[DioUsbdevDnPullup] + }; + + ////////////////////// + // AST // + ////////////////////// + // TLUL interface + tlul_pkg::tl_h2d_t base_ast_bus; + tlul_pkg::tl_d2h_t ast_base_bus; + + // assorted ast status + ast_pkg::ast_status_t ast_status; + + // ast clocks and resets + logic aon_pok; + + // synchronization clocks / rests + clkmgr_pkg::clkmgr_ast_out_t clks_ast; + rstmgr_pkg::rstmgr_ast_out_t rsts_ast; + + // otp power sequence + otp_ctrl_pkg::otp_ast_req_t otp_ctrl_otp_ast_pwr_seq; + otp_ctrl_pkg::otp_ast_rsp_t otp_ctrl_otp_ast_pwr_seq_h; + + logic usb_ref_pulse; + logic usb_ref_val; + + // adc + ast_pkg::adc_ast_req_t adc_req; + ast_pkg::adc_ast_rsp_t adc_rsp; + + // entropy source interface + // The entropy source pacakge definition should eventually be moved to es + entropy_src_pkg::entropy_src_rng_req_t es_rng_req; + entropy_src_pkg::entropy_src_rng_rsp_t es_rng_rsp; + logic es_rng_fips; + + // entropy distribution network + edn_pkg::edn_req_t ast_edn_edn_req; + edn_pkg::edn_rsp_t ast_edn_edn_rsp; + + // alerts interface + ast_pkg::ast_alert_rsp_t ast_alert_rsp; + ast_pkg::ast_alert_req_t ast_alert_req; + + // Flash connections + lc_ctrl_pkg::lc_tx_t flash_bist_enable; + logic flash_power_down_h; + logic flash_power_ready_h; + + // Life cycle clock bypass req/ack + lc_ctrl_pkg::lc_tx_t ast_clk_byp_req; + lc_ctrl_pkg::lc_tx_t ast_clk_byp_ack; + + // DFT connections + logic scan_en; + lc_ctrl_pkg::lc_tx_t dft_en; + pinmux_pkg::dft_strap_test_req_t dft_strap_test; + + // Debug connections + logic [ast_pkg::Ast2PadOutWidth-1:0] ast2pinmux; + logic [ast_pkg::Pad2AstInWidth-1:0] pad2ast; + + assign pad2ast = { + mio_in_raw[MioPadIoc3], + mio_in_raw[MioPadIob8], + mio_in_raw[MioPadIob7], + mio_in_raw[MioPadIob2], + mio_in_raw[MioPadIob1], + mio_in_raw[MioPadIob0] + }; + + + // Jitter enable + logic jen; + + // reset domain connections + import rstmgr_pkg::PowerDomains; + import rstmgr_pkg::DomainAonSel; + import rstmgr_pkg::Domain0Sel; + + // external clock comes in at a fixed position + logic ext_clk; + assign ext_clk = mio_in_raw[MioPadIoc6]; + + // Memory configuration connections + ast_pkg::spm_rm_t ast_ram_1p_cfg; + ast_pkg::spm_rm_t ast_rf_cfg; + ast_pkg::spm_rm_t ast_rom_cfg; + ast_pkg::dpm_rm_t ast_ram_2p_fcfg; + ast_pkg::dpm_rm_t ast_ram_2p_lcfg; + + prim_ram_1p_pkg::ram_1p_cfg_t ram_1p_cfg; + prim_ram_2p_pkg::ram_2p_cfg_t ram_2p_cfg; + prim_rom_pkg::rom_cfg_t rom_cfg; + + // conversion from ast structure to memory centric structures + assign ram_1p_cfg = '{ + ram_cfg: '{ + cfg_en: ast_ram_1p_cfg.marg_en, + cfg: ast_ram_1p_cfg.marg + }, + rf_cfg: '{ + cfg_en: ast_rf_cfg.marg_en, + cfg: ast_rf_cfg.marg + } + }; + + assign ram_2p_cfg = '{ + a_ram_fcfg: '{ + cfg_en: ast_ram_2p_fcfg.marg_en_a, + cfg: ast_ram_2p_fcfg.marg_a + }, + a_ram_lcfg: '{ + cfg_en: ast_ram_2p_lcfg.marg_en_a, + cfg: ast_ram_2p_lcfg.marg_a + }, + b_ram_fcfg: '{ + cfg_en: ast_ram_2p_fcfg.marg_en_b, + cfg: ast_ram_2p_fcfg.marg_b + }, + b_ram_lcfg: '{ + cfg_en: ast_ram_2p_lcfg.marg_en_b, + cfg: ast_ram_2p_lcfg.marg_b + } + }; + + assign rom_cfg = '{ + cfg_en: ast_rom_cfg.marg_en, + cfg: ast_rom_cfg.marg + }; + + + // AST does not use all clocks / resets forwarded to it + logic unused_slow_clk_en; + logic unused_usb_clk_aon; + logic unused_usb_clk_io_div4; + assign unused_slow_clk_en = base_ast_pwr.slow_clk_en; + assign unused_usb_clk_aon = clks_ast.clk_ast_usbdev_aon_peri; + assign unused_usb_clk_io_div4 = clks_ast.clk_ast_usbdev_io_div4_peri; + + logic unused_usb_usb_rst; + logic [PowerDomains-1:0] unused_usb_sys_io_div4_rst; + logic [PowerDomains-1:0] unused_usb_sys_aon_rst; + logic unused_ast_sys_io_div4_rst; + logic unused_sensor_ctrl_sys_io_div4_rst; + logic unused_adc_ctrl_sys_io_div4_rst; + logic unused_entropy_sys_rst; + logic unused_edn_sys_rst; + assign unused_usb_usb_rst = rsts_ast.rst_ast_usbdev_usb_n[DomainAonSel]; + assign unused_usb_sys_io_div4_rst = rsts_ast.rst_ast_usbdev_sys_io_div4_n; + assign unused_usb_sys_aon_rst = rsts_ast.rst_ast_usbdev_sys_aon_n; + assign unused_ast_sys_io_div4_rst = + rsts_ast.rst_ast_ast_sys_io_div4_n[Domain0Sel]; + assign unused_sensor_ctrl_sys_io_div4_rst = + rsts_ast.rst_ast_sensor_ctrl_aon_sys_io_div4_n[Domain0Sel]; + assign unused_adc_ctrl_sys_io_div4_rst = + rsts_ast.rst_ast_adc_ctrl_aon_sys_io_div4_n[Domain0Sel]; + assign unused_entropy_sys_rst = rsts_ast.rst_ast_entropy_src_sys_n[DomainAonSel]; + assign unused_edn_sys_rst = rsts_ast.rst_ast_edn0_sys_n[DomainAonSel]; + + ast_pkg::ast_dif_t flash_alert; + ast_pkg::ast_dif_t otp_alert; + logic ast_init_done; + + ast #( + .EntropyStreams(ast_pkg::EntropyStreams), + .AdcChannels(ast_pkg::AdcChannels), + .AdcDataWidth(ast_pkg::AdcDataWidth), + .UsbCalibWidth(ast_pkg::UsbCalibWidth), + .Ast2PadOutWidth(ast_pkg::Ast2PadOutWidth), + .Pad2AstInWidth(ast_pkg::Pad2AstInWidth) + ) u_ast ( + // tlul + .tl_i ( base_ast_bus ), + .tl_o ( ast_base_bus ), + // init done indication + .ast_init_done_o ( ast_init_done ), + // buffered clocks & resets + // Reset domain connection is manual at the moment + .clk_ast_adc_i ( clks_ast.clk_ast_adc_ctrl_aon_io_div4_peri ), + .rst_ast_adc_ni ( rsts_ast.rst_ast_adc_ctrl_aon_sys_io_div4_n[DomainAonSel] ), + .clk_ast_alert_i ( clks_ast.clk_ast_sensor_ctrl_aon_io_div4_secure ), + .rst_ast_alert_ni ( rsts_ast.rst_ast_sensor_ctrl_aon_sys_io_div4_n[DomainAonSel] ), + .clk_ast_es_i ( clks_ast.clk_ast_edn0_main_secure ), + .rst_ast_es_ni ( rsts_ast.rst_ast_edn0_sys_n[Domain0Sel] ), + .clk_ast_rng_i ( clks_ast.clk_ast_entropy_src_main_secure ), + .rst_ast_rng_ni ( rsts_ast.rst_ast_entropy_src_sys_n[Domain0Sel] ), + .clk_ast_tlul_i ( clks_ast.clk_ast_ast_io_div4_secure ), + .rst_ast_tlul_ni ( rsts_ast.rst_ast_ast_sys_io_div4_n[DomainAonSel] ), + .clk_ast_usb_i ( clks_ast.clk_ast_usbdev_usb_peri ), + .rst_ast_usb_ni ( rsts_ast.rst_ast_usbdev_usb_n[Domain0Sel] ), + .clk_ast_ext_i ( ext_clk ), + .por_ni ( manual_in_por_n ), + // pok test for FPGA + .vcc_supp_i ( 1'b1 ), + .vcaon_supp_i ( 1'b1 ), + .vcmain_supp_i ( 1'b1 ), + .vioa_supp_i ( 1'b1 ), + .viob_supp_i ( 1'b1 ), + // pok + .vcaon_pok_o ( aon_pok ), + .vcmain_pok_o ( ast_base_pwr.main_pok ), + .vioa_pok_o ( ast_status.io_pok[0] ), + .viob_pok_o ( ast_status.io_pok[1] ), + // main regulator + .main_env_iso_en_i ( base_ast_pwr.pwr_clamp_env ), + .main_pd_ni ( base_ast_pwr.main_pd_n ), + // pdm control (flash)/otp + .flash_power_down_h_o ( flash_power_down_h ), + .flash_power_ready_h_o ( flash_power_ready_h ), + .otp_power_seq_i ( otp_ctrl_otp_ast_pwr_seq ), + .otp_power_seq_h_o ( otp_ctrl_otp_ast_pwr_seq_h ), + // system source clock + .clk_src_sys_en_i ( base_ast_pwr.core_clk_en ), + // need to add function in clkmgr + .clk_src_sys_jen_i ( jen ), + .clk_src_sys_o ( ast_base_clks.clk_sys ), + .clk_src_sys_val_o ( ast_base_pwr.core_clk_val ), + // aon source clock + .clk_src_aon_o ( ast_base_clks.clk_aon ), + .clk_src_aon_val_o ( ast_base_pwr.slow_clk_val ), + // io source clock + .clk_src_io_en_i ( base_ast_pwr.io_clk_en ), + .clk_src_io_o ( ast_base_clks.clk_io ), + .clk_src_io_val_o ( ast_base_pwr.io_clk_val ), + // usb source clock + .usb_ref_pulse_i ( usb_ref_pulse ), + .usb_ref_val_i ( usb_ref_val ), + .clk_src_usb_en_i ( base_ast_pwr.usb_clk_en ), + .clk_src_usb_o ( ast_base_clks.clk_usb ), + .clk_src_usb_val_o ( ast_base_pwr.usb_clk_val ), + // USB IO Pull-up Calibration Setting + .usb_io_pu_cal_o ( usb_io_pu_cal ), + // adc + .adc_a0_ai ( CC1 ), + .adc_a1_ai ( CC2 ), + .adc_pd_i ( adc_req.pd ), + .adc_chnsel_i ( adc_req.channel_sel ), + .adc_d_o ( adc_rsp.data ), + .adc_d_val_o ( adc_rsp.data_valid ), + // rng + .rng_en_i ( es_rng_req.rng_enable ), + .rng_fips_i ( es_rng_fips ), + .rng_val_o ( es_rng_rsp.rng_valid ), + .rng_b_o ( es_rng_rsp.rng_b ), + // entropy + .entropy_rsp_i ( ast_edn_edn_rsp ), + .entropy_req_o ( ast_edn_edn_req ), + // alerts + .fla_alert_in_i ( flash_alert ), + .otp_alert_in_i ( otp_alert ), + .alert_rsp_i ( ast_alert_rsp ), + .alert_req_o ( ast_alert_req ), + // dft + .dft_strap_test_i ( dft_strap_test ), + .lc_dft_en_i ( dft_en ), + // pinmux related + .padmux2ast_i ( pad2ast ), + .ast2padmux_o ( ast2pinmux ), + // Direct short to PAD + .pad2ast_t0_ai ( IOA4 ), + .pad2ast_t1_ai ( IOA5 ), + .ast2pad_t0_ao ( IOA2 ), + .ast2pad_t1_ao ( IOA3 ), + .lc_clk_byp_req_i ( ast_clk_byp_req ), + .lc_clk_byp_ack_o ( ast_clk_byp_ack ), + .flash_bist_en_o ( flash_bist_enable ), + // Memory configuration connections + .dpram_rmf_o ( ast_ram_2p_fcfg ), + .dpram_rml_o ( ast_ram_2p_lcfg ), + .spram_rm_o ( ast_ram_1p_cfg ), + .sprgf_rm_o ( ast_rf_cfg ), + .sprom_rm_o ( ast_rom_cfg ), + // scan + .dft_scan_md_o ( scanmode ), + .scan_shift_en_o ( scan_en ), + .scan_reset_no ( scan_rst_n ) + ); + + ////////////////////// + // Top-level design // + ////////////////////// + + top_${top["name"]} #( + .AesMasking(1'b1), + .AesSBoxImpl(aes_pkg::SBoxImplDom), + .SecAesStartTriggerDelay(0), + .SecAesAllowForcingMasks(1'b0), + .KmacEnMasking(1), // DOM AND + Masking scheme + .KmacReuseShare(0), + .SramCtrlRetAonInstrExec(0), + .SramCtrlMainInstrExec(1), + .PinmuxAonTargetCfg(PinmuxTargetCfg), + .RomCtrlSkipCheck(RomCtrlSkipCheck) + ) top_${top["name"]} ( + .rst_ni ( aon_pok ), + // ast connections + .clk_main_i ( ast_base_clks.clk_sys ), + .clk_io_i ( ast_base_clks.clk_io ), + .clk_usb_i ( ast_base_clks.clk_usb ), + .clk_aon_i ( ast_base_clks.clk_aon ), + .clks_ast_o ( clks_ast ), + .clk_main_jitter_en_o ( jen ), + .rsts_ast_o ( rsts_ast ), + .pwrmgr_ast_req_o ( base_ast_pwr ), + .pwrmgr_ast_rsp_i ( ast_base_pwr ), + .sensor_ctrl_ast_alert_req_i ( ast_alert_req ), + .sensor_ctrl_ast_alert_rsp_o ( ast_alert_rsp ), + .sensor_ctrl_ast_status_i ( ast_status ), + .usbdev_usb_ref_val_o ( usb_ref_pulse ), + .usbdev_usb_ref_pulse_o ( usb_ref_val ), + .ast_tl_req_o ( base_ast_bus ), + .ast_tl_rsp_i ( ast_base_bus ), + .adc_req_o ( adc_req ), + .adc_rsp_i ( adc_rsp ), + .ast_edn_req_i ( ast_edn_edn_req ), + .ast_edn_rsp_o ( ast_edn_edn_rsp ), + .otp_ctrl_otp_ast_pwr_seq_o ( otp_ctrl_otp_ast_pwr_seq ), + .otp_ctrl_otp_ast_pwr_seq_h_i ( otp_ctrl_otp_ast_pwr_seq_h ), + .otp_alert_o ( otp_alert ), + .flash_bist_enable_i ( flash_bist_enable ), + .flash_power_down_h_i ( flash_power_down_h ), + .flash_power_ready_h_i ( flash_power_ready_h ), + .flash_alert_o ( flash_alert ), + .es_rng_req_o ( es_rng_req ), + .es_rng_rsp_i ( es_rng_rsp ), + .es_rng_fips_o ( es_rng_fips ), + .ast_clk_byp_req_o ( ast_clk_byp_req ), + .ast_clk_byp_ack_i ( ast_clk_byp_ack ), + .ast2pinmux_i ( ast2pinmux ), + .ast_init_done_i ( ast_init_done ), + + // Flash test mode voltages + .flash_test_mode_a_io ( {FLASH_TEST_MODE1, + FLASH_TEST_MODE0} ), + .flash_test_voltage_h_io ( FLASH_TEST_VOLT ), + + // OTP external voltage + .otp_ext_voltage_h_io ( OTP_EXT_VOLT ), + + // Multiplexed I/O + .mio_in_i ( mio_in ), + .mio_out_o ( mio_out ), + .mio_oe_o ( mio_oe ), + + // Dedicated I/O + .dio_in_i ( dio_in ), + .dio_out_o ( dio_out ), + .dio_oe_o ( dio_oe ), + + // Pad attributes + .mio_attr_o ( mio_attr ), + .dio_attr_o ( dio_attr ), + + // Memory attributes + .ram_1p_cfg_i ( ram_1p_cfg ), + .ram_2p_cfg_i ( ram_2p_cfg ), + .rom_cfg_i ( rom_cfg ), + + // DFT signals + .ast_lc_dft_en_o ( dft_en ), + .dft_strap_test_o ( dft_strap_test ), + .dft_hold_tap_sel_i ( '0 ), + .scan_rst_ni ( scan_rst_n ), + .scan_en_i ( scan_en ), + .scanmode_i ( scanmode ) + ); +% endif + +################################################################### +## FPGA shared ## +################################################################### +% if target["name"] in ["cw305", "nexysvideo"]: + ////////////////// + // PLL for FPGA // + ////////////////// + + assign manual_out_io_clk = 1'b0; + assign manual_oe_io_clk = 1'b0; + assign manual_out_por_n = 1'b0; + assign manual_oe_por_n = 1'b0; + assign manual_out_io_jsrst_n = 1'b0; + assign manual_oe_io_jsrst_n = 1'b0; + + logic clk_main, clk_usb_48mhz, clk_aon, rst_n; + clkgen_xil7series # ( + .AddClkBuf(0) + ) clkgen ( + .clk_i(manual_in_io_clk), + .rst_ni(manual_in_por_n), + .jtag_srst_ni(manual_in_io_jsrst_n), + .clk_main_o(clk_main), + .clk_48MHz_o(clk_usb_48mhz), + .clk_aon_o(clk_aon), + .rst_no(rst_n) + ); + + ////////////////////// + // Top-level design // + ////////////////////// + pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr; + ast_pkg::ast_alert_req_t ast_base_alerts; + ast_pkg::ast_status_t ast_base_status; + + assign ast_base_pwr.slow_clk_val = 1'b1; + assign ast_base_pwr.core_clk_val = 1'b1; + assign ast_base_pwr.io_clk_val = 1'b1; + assign ast_base_pwr.usb_clk_val = 1'b1; + assign ast_base_pwr.main_pok = 1'b1; + + ast_pkg::ast_dif_t silent_alert = '{ + p: 1'b0, + n: 1'b1 + }; + + assign ast_base_alerts.alerts = {ast_pkg::NumAlerts{silent_alert}}; + assign ast_base_status.io_pok = {ast_pkg::NumIoRails{1'b1}}; + + // the rst_ni pin only goes to AST + // the rest of the logic generates reset based on the 'pok' signal. + // for verilator purposes, make these two the same. + lc_ctrl_pkg::lc_tx_t lc_clk_bypass; + +% if target["name"] == "cw305": + // This is used for outputting the capture trigger + logic [pinmux_reg_pkg::NMioPads-1:0] mio_out_pre; +% endif + +// TODO: align this with ASIC version to minimize the duplication. +// Also need to add AST simulation and FPGA emulation models for things like entropy source - +// otherwise Verilator / FPGA will hang. + top_${top["name"]} #( +% if target["name"] == "cw305": + .AesMasking(1'b1), + .AesSBoxImpl(aes_pkg::SBoxImplDom), + .SecAesStartTriggerDelay(40), + .SecAesAllowForcingMasks(1'b1), + .SecAesSkipPRNGReseeding(1'b1), + .IbexICache(0), + .BootRomInitFile(BootRomInitFile), +% else: + .AesMasking(1'b0), + .AesSBoxImpl(aes_pkg::SBoxImplLut), + .SecAesStartTriggerDelay(0), + .SecAesAllowForcingMasks(1'b0), + .SecAesSkipPRNGReseeding(1'b0), + .EntropySrcStub(1'b1), + .CsrngSBoxImpl(aes_pkg::SBoxImplLut), + .OtbnRegFile(otbn_pkg::RegFileFPGA), + .OtbnStub(1'b1), + .OtpCtrlMemInitFile(OtpCtrlMemInitFile), + .RomCtrlBootRomInitFile(BootRomInitFile), +% endif + .IbexRegFile(ibex_pkg::RegFileFPGA), + .IbexPipeLine(1), + .SecureIbex(0), + .SramCtrlRetAonInstrExec(0), + .SramCtrlMainInstrExec(1), + .PinmuxAonTargetCfg(PinmuxTargetCfg) + ) top_${top["name"]} ( + .rst_ni ( rst_n ), + .clk_main_i ( clk_main ), + .clk_io_i ( clk_main ), + .clk_usb_i ( clk_usb_48mhz ), + .clk_aon_i ( clk_aon ), + .clks_ast_o ( ), + .clk_main_jitter_en_o ( ), + .rsts_ast_o ( ), + .pwrmgr_ast_req_o ( ), + .pwrmgr_ast_rsp_i ( ast_base_pwr ), + .sensor_ctrl_ast_alert_req_i ( ast_base_alerts ), + .sensor_ctrl_ast_alert_rsp_o ( ), + .sensor_ctrl_ast_status_i ( ast_base_status ), + .usbdev_usb_ref_val_o ( ), + .usbdev_usb_ref_pulse_o ( ), + .ast_edn_req_i ( '0 ), + .ast_edn_rsp_o ( ), + .flash_bist_enable_i ( lc_ctrl_pkg::Off ), + .flash_power_down_h_i ( 1'b0 ), + .flash_power_ready_h_i ( 1'b1 ), + .ast_clk_byp_req_o ( lc_clk_bypass ), + .ast_clk_byp_ack_i ( lc_clk_bypass ), + +% if target["name"] != "cw305": + .ast_tl_req_o ( ), + .ast_tl_rsp_i ( '0 ), + .otp_ctrl_otp_ast_pwr_seq_o ( ), + .otp_ctrl_otp_ast_pwr_seq_h_i ( '0 ), + .otp_alert_o ( ), + .es_rng_req_o ( ), + .es_rng_rsp_i ( '0 ), + .es_rng_fips_o ( ), + .ast2pinmux_i ( '0 ), +% endif + + // Multiplexed I/O + .mio_in_i ( mio_in ), +% if target["name"] == "cw305": + .mio_out_o ( mio_out_pre ), +% else: + .mio_out_o ( mio_out ), +% endif + .mio_oe_o ( mio_oe ), + + // Dedicated I/O + .dio_in_i ( dio_in ), + .dio_out_o ( dio_out ), + .dio_oe_o ( dio_oe ), + + // Pad attributes + .mio_attr_o ( mio_attr ), + .dio_attr_o ( dio_attr ), + + // Memory attributes + .ram_1p_cfg_i ( '0 ), + .ram_2p_cfg_i ( '0 ), + .rom_cfg_i ( '0 ), + + // DFT signals + .dft_hold_tap_sel_i ( '0 ), + .scan_rst_ni ( 1'b1 ), + .scan_en_i ( 1'b0 ), + .scanmode_i ( lc_ctrl_pkg::Off ) + ); +% endif + + +################################################################### +## CW305 capture trigger ## +################################################################### +% if target["name"] == "cw305": + + ////////////////////////////////////// + // Generate precise capture trigger // + ////////////////////////////////////// + + // TODO: make this a "manual" IO specific to the CW305 target + // such that we can decouple this from the MIO signals. + localparam int MioIdxTrigger = 15; + + // To obtain a more precise capture trigger for side-channel analysis, we only forward the + // software-controlled capture trigger when the AES module is actually busy (performing + // either encryption/decryption or clearing internal registers). + // GPIO15 is used as capture trigger (mapped to IOB9 at the moment in pinmux.c). + always_comb begin : p_trigger + mio_out = mio_out_pre; + mio_out[MioIdxTrigger] = mio_out_pre[MioIdxTrigger] & + ~top_englishbreakfast.clkmgr_aon_idle[clkmgr_pkg::Aes]; + end + + ////////////////////// + // ChipWhisperer IO // + ////////////////////// + + logic unused_inputs; + assign unused_inputs = manual_in_tio_clkout ^ manual_in_io_utx_debug; + + // Clock ouput to capture board. + assign manual_out_tio_clkout = manual_in_io_clk; + assign manual_oe_tio_clkout = 1'b1; + + // UART Tx for debugging. The UART itself is connected to the capture board. + assign manual_out_io_utx_debug = top_${top["name"]}.cio_uart0_tx_d2p; + assign manual_oe_io_utx_debug = 1'b1; + +% endif + +endmodule : chip_${top["name"]}_${target["name"]} diff --git a/hw/vendored_ips/gpio/util/reggen/topgen/templates/clang-format b/hw/vendored_ips/gpio/util/reggen/topgen/templates/clang-format new file mode 100644 index 00000000..7cb47a7a --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/topgen/templates/clang-format @@ -0,0 +1,4 @@ +# This disables clang-format on all files in the sw/autogen directory. +# This is needed so that git-clang-format and similar scripts work. +DisableFormat: true +SortIncludes: false diff --git a/hw/vendored_ips/gpio/util/reggen/topgen/templates/tb__alert_handler_connect.sv.tpl b/hw/vendored_ips/gpio/util/reggen/topgen/templates/tb__alert_handler_connect.sv.tpl new file mode 100644 index 00000000..559926a7 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/topgen/templates/tb__alert_handler_connect.sv.tpl @@ -0,0 +1,21 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// tb__alert_handler_connect.sv is auto-generated by `topgen.py` tool + +<% + index = 0 + module_name = "" +%>\ +% for alert in top["alert"]: + % if alert["module_name"] == module_name: +<% index = index + 1 %>\ + % else: +<% + module_name = alert["module_name"] + index = 0 +%>\ + % endif +assign alert_if[${loop.index}].alert_tx = `CHIP_HIER.u_${module_name}.alert_tx_o[${index}]; +% endfor diff --git a/hw/vendored_ips/gpio/util/reggen/topgen/templates/tb__xbar_connect.sv.tpl b/hw/vendored_ips/gpio/util/reggen/topgen/templates/tb__xbar_connect.sv.tpl new file mode 100644 index 00000000..d4910958 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/topgen/templates/tb__xbar_connect.sv.tpl @@ -0,0 +1,124 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// tb__xbar_connect generated by `topgen.py` tool +<% +from collections import OrderedDict +import topgen.lib as lib + +top_hier = 'tb.dut.top_' + top["name"] + '.' +clk_hier = top_hier + top["clocks"]["hier_paths"]["top"] + +clk_src = OrderedDict() +for xbar in top["xbar"]: + for clk, src in xbar["clock_srcs"].items(): + clk_src[clk] = src + +clk_freq = OrderedDict() +for clock in top["clocks"]["srcs"] + top["clocks"]["derived_srcs"]: + if clock["name"] in clk_src.values(): + clk_freq[clock["name"]] = clock["freq"] + +hosts = OrderedDict() +devices = OrderedDict() +for xbar in top["xbar"]: + for node in xbar["nodes"]: + if node["type"] == "host" and not node["xbar"]: + hosts[node["name"]] = "clk_" + clk_src[node["clock"]] + elif node["type"] == "device" and not node["xbar"]: + devices[node["name"]] = "clk_" + clk_src[node["clock"]] + +def escape_if_name(qual_if_name): + return qual_if_name.replace('.', '__') + +%>\ +<%text> +`define DRIVE_CHIP_TL_HOST_IF(tl_name, inst_name, sig_name) \ + force ``tl_name``_tl_if.d2h = dut.top_earlgrey.u_``inst_name``.``sig_name``_i; \ + force dut.top_earlgrey.u_``inst_name``.``sig_name``_o = ``tl_name``_tl_if.h2d; \ + force dut.top_earlgrey.u_``inst_name``.clk_i = 0; \ + uvm_config_db#(virtual tl_if)::set(null, $sformatf("*%0s*", `"tl_name`"), "vif", \ + ``tl_name``_tl_if); + +`define DRIVE_CHIP_TL_DEVICE_IF(tl_name, inst_name, sig_name) \ + force ``tl_name``_tl_if.h2d = dut.top_earlgrey.u_``inst_name``.``sig_name``_i; \ + force dut.top_earlgrey.u_``inst_name``.``sig_name``_o = ``tl_name``_tl_if.d2h; \ + force dut.top_earlgrey.u_``inst_name``.clk_i = 0; \ + uvm_config_db#(virtual tl_if)::set(null, $sformatf("*%0s*", `"tl_name`"), "vif", \ + ``tl_name``_tl_if); + +`define DRIVE_CHIP_TL_EXT_DEVICE_IF(tl_name, port_name) \ + force ``tl_name``_tl_if.h2d = dut.top_earlgrey.``port_name``_req_o; \ + force dut.top_earlgrey.``port_name``_rsp_i = ``tl_name``_tl_if.d2h; \ + uvm_config_db#(virtual tl_if)::set(null, $sformatf("*%0s*", `"tl_name`"), "vif", \ + ``tl_name``_tl_if); +\ + +% for c in clk_freq.keys(): +wire clk_${c}; +clk_rst_if clk_rst_if_${c}(.clk(clk_${c}), .rst_n(rst_n)); +% endfor + +% for i, clk in hosts.items(): +tl_if ${escape_if_name(i)}_tl_if(${clk}, rst_n); +% endfor + +% for i, clk in devices.items(): +tl_if ${escape_if_name(i)}_tl_if(${clk}, rst_n); +% endfor + +initial begin + bit xbar_mode; + void'($value$plusargs("xbar_mode=%0b", xbar_mode)); + if (xbar_mode) begin + // only enable assertions in xbar as many pins are unconnected + $assertoff(0, tb); +% for xbar in top["xbar"]: + $asserton(0, tb.dut.top_${top["name"]}.u_xbar_${xbar["name"]}); +% endfor + +% for c in clk_freq.keys(): + clk_rst_if_${c}.set_active(.drive_rst_n_val(0)); + clk_rst_if_${c}.set_freq_khz(${clk_freq[c]} / 1000); +% endfor + + // bypass clkmgr, force clocks directly +% for xbar in top["xbar"]: + % for clk, src in xbar["clock_srcs"].items(): + force ${top_hier}u_xbar_${xbar["name"]}.${clk} = clk_${src}; + % endfor +% endfor + + // bypass rstmgr, force resets directly +% for xbar in top["xbar"]: + % for rst in xbar["reset_connections"]: + force ${top_hier}u_xbar_${xbar["name"]}.${rst} = rst_n; + % endfor +% endfor + +% for xbar in top["xbar"]: + % for node in xbar["nodes"]: +<% +clk = 'clk_' + clk_src[node["clock"]] +esc_name = node['name'].replace('.', '__') +inst_sig_list = lib.find_otherside_modules(top, xbar["name"], 'tl_' + esc_name) +inst_name = inst_sig_list[0][1] +sig_name = inst_sig_list[0][2] + +%>\ + % if node["type"] == "host" and not node["xbar"]: + `DRIVE_CHIP_TL_HOST_IF(${esc_name}, ${inst_name}, ${sig_name}) + % elif node["type"] == "device" and not node["xbar"] and node["stub"]: + `DRIVE_CHIP_TL_EXT_DEVICE_IF(${esc_name}, ${inst_name}_${sig_name}) + % elif node["type"] == "device" and not node["xbar"]: + `DRIVE_CHIP_TL_DEVICE_IF(${esc_name}, ${inst_name}, ${sig_name}) + % endif + % endfor +% endfor + end +end + +`undef DRIVE_CHIP_TL_HOST_IF +`undef DRIVE_CHIP_TL_DEVICE_IF +`undef DRIVE_CHIP_TL_EXT_DEVICE_IF diff --git a/hw/vendored_ips/gpio/util/reggen/topgen/templates/toplevel.c.tpl b/hw/vendored_ips/gpio/util/reggen/topgen/templates/toplevel.c.tpl new file mode 100644 index 00000000..4cfbabe2 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/topgen/templates/toplevel.c.tpl @@ -0,0 +1,21 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#include "${helper.header_path}" + +/** + * PLIC Interrupt Source to Peripheral Map + * + * This array is a mapping from `${helper.plic_interrupts.name.as_c_type()}` to + * `${helper.plic_sources.name.as_c_type()}`. + */ +${helper.plic_mapping.render_definition()} + +/** + * Alert Handler Alert Source to Peripheral Map + * + * This array is a mapping from `${helper.alert_alerts.name.as_c_type()}` to + * `${helper.alert_sources.name.as_c_type()}`. + */ +${helper.alert_mapping.render_definition()} diff --git a/hw/vendored_ips/gpio/util/reggen/topgen/templates/toplevel.h.tpl b/hw/vendored_ips/gpio/util/reggen/topgen/templates/toplevel.h.tpl new file mode 100644 index 00000000..24ba4100 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/topgen/templates/toplevel.h.tpl @@ -0,0 +1,201 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#ifndef _TOP_${top["name"].upper()}_H_ +#define _TOP_${top["name"].upper()}_H_ + +/** + * @file + * @brief Top-specific Definitions + * + * This file contains preprocessor and type definitions for use within the + * device C/C++ codebase. + * + * These definitions are for information that depends on the top-specific chip + * configuration, which includes: + * - Device Memory Information (for Peripherals and Memory) + * - PLIC Interrupt ID Names and Source Mappings + * - Alert ID Names and Source Mappings + * - Pinmux Pin/Select Names + * - Power Manager Wakeups + */ + +#ifdef __cplusplus +extern "C" { +#endif + +% for (inst_name, if_name), region in helper.devices(): +<% + if_desc = inst_name if if_name is None else '{} device on {}'.format(if_name, inst_name) + hex_base_addr = "0x{:X}u".format(region.base_addr) + hex_size_bytes = "0x{:X}u".format(region.size_bytes) + + base_addr_name = region.base_addr_name().as_c_define() + size_bytes_name = region.size_bytes_name().as_c_define() + +%>\ +/** + * Peripheral base address for ${if_desc} in top ${top["name"]}. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define ${base_addr_name} ${hex_base_addr} + +/** + * Peripheral size for ${if_desc} in top ${top["name"]}. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #${base_addr_name} and + * `${base_addr_name} + ${size_bytes_name}`. + */ +#define ${size_bytes_name} ${hex_size_bytes} + +% endfor + +% for name, region in helper.memories(): +<% + hex_base_addr = "0x{:X}u".format(region.base_addr) + hex_size_bytes = "0x{:X}u".format(region.size_bytes) + + base_addr_name = region.base_addr_name().as_c_define() + size_bytes_name = region.size_bytes_name().as_c_define() + +%>\ +/** + * Memory base address for ${name} in top ${top["name"]}. + */ +#define ${base_addr_name} ${hex_base_addr} + +/** + * Memory size for ${name} in top ${top["name"]}. + */ +#define ${size_bytes_name} ${hex_size_bytes} + +% endfor + +/** + * PLIC Interrupt Source Peripheral. + * + * Enumeration used to determine which peripheral asserted the corresponding + * interrupt. + */ +${helper.plic_sources.render()} + +/** + * PLIC Interrupt Source. + * + * Enumeration of all PLIC interrupt sources. The interrupt sources belonging to + * the same peripheral are guaranteed to be consecutive. + */ +${helper.plic_interrupts.render()} + +/** + * PLIC Interrupt Source to Peripheral Map + * + * This array is a mapping from `${helper.plic_interrupts.name.as_c_type()}` to + * `${helper.plic_sources.name.as_c_type()}`. + */ +${helper.plic_mapping.render_declaration()} + +/** + * PLIC Interrupt Target. + * + * Enumeration used to determine which set of IE, CC, threshold registers to + * access for a given interrupt target. + */ +${helper.plic_targets.render()} + +/** + * Alert Handler Source Peripheral. + * + * Enumeration used to determine which peripheral asserted the corresponding + * alert. + */ +${helper.alert_sources.render()} + +/** + * Alert Handler Alert Source. + * + * Enumeration of all Alert Handler Alert Sources. The alert sources belonging to + * the same peripheral are guaranteed to be consecutive. + */ +${helper.alert_alerts.render()} + +/** + * Alert Handler Alert Source to Peripheral Map + * + * This array is a mapping from `${helper.alert_alerts.name.as_c_type()}` to + * `${helper.alert_sources.name.as_c_type()}`. + */ +${helper.alert_mapping.render_declaration()} + +#define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2 + +// PERIPH_INSEL ranges from 0 to NUM_MIO_PADS + 2 -1} +// 0 and 1 are tied to value 0 and 1 +#define NUM_MIO_PADS ${top["pinmux"]["io_counts"]["muxed"]["pads"]} +#define NUM_DIO_PADS ${top["pinmux"]["io_counts"]["dedicated"]["inouts"] + \ + top["pinmux"]["io_counts"]["dedicated"]["inputs"] + \ + top["pinmux"]["io_counts"]["dedicated"]["outputs"] } + +#define PINMUX_PERIPH_OUTSEL_IDX_OFFSET 3 + +/** + * Pinmux Peripheral Input. + */ +${helper.pinmux_peripheral_in.render()} + +/** + * Pinmux MIO Input Selector. + */ +${helper.pinmux_insel.render()} + +/** + * Pinmux MIO Output. + */ +${helper.pinmux_mio_out.render()} + +/** + * Pinmux Peripheral Output Selector. + */ +${helper.pinmux_outsel.render()} + +/** + * Power Manager Wakeup Signals + */ +${helper.pwrmgr_wakeups.render()} + +/** + * Reset Manager Software Controlled Resets + */ +${helper.rstmgr_sw_rsts.render()} + +/** + * Power Manager Reset Request Signals + */ +${helper.pwrmgr_reset_requests.render()} + +/** + * Clock Manager Software-Controlled ("Gated") Clocks. + * + * The Software has full control over these clocks. + */ +${helper.clkmgr_gateable_clocks.render()} + +/** + * Clock Manager Software-Hinted Clocks. + * + * The Software has partial control over these clocks. It can ask them to stop, + * but the clock manager is in control of whether the clock actually is stopped. + */ +${helper.clkmgr_hintable_clocks.render()} + +// Header Extern Guard +#ifdef __cplusplus +} // extern "C" +#endif + +#endif // _TOP_${top["name"].upper()}_H_ diff --git a/hw/vendored_ips/gpio/util/reggen/topgen/templates/toplevel.sv.tpl b/hw/vendored_ips/gpio/util/reggen/topgen/templates/toplevel.sv.tpl new file mode 100644 index 00000000..f0248b3c --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/topgen/templates/toplevel.sv.tpl @@ -0,0 +1,832 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +${gencmd} +<% +import re +import topgen.lib as lib + +num_mio_inputs = top['pinmux']['io_counts']['muxed']['inouts'] + \ + top['pinmux']['io_counts']['muxed']['inputs'] +num_mio_outputs = top['pinmux']['io_counts']['muxed']['inouts'] + \ + top['pinmux']['io_counts']['muxed']['outputs'] +num_mio_pads = top['pinmux']['io_counts']['muxed']['pads'] + +num_dio_inputs = top['pinmux']['io_counts']['dedicated']['inouts'] + \ + top['pinmux']['io_counts']['dedicated']['inputs'] +num_dio_outputs = top['pinmux']['io_counts']['dedicated']['inouts'] + \ + top['pinmux']['io_counts']['dedicated']['outputs'] +num_dio_total = top['pinmux']['io_counts']['dedicated']['inouts'] + \ + top['pinmux']['io_counts']['dedicated']['inputs'] + \ + top['pinmux']['io_counts']['dedicated']['outputs'] + +num_im = sum([x["width"] if "width" in x else 1 for x in top["inter_signal"]["external"]]) + +max_sigwidth = max([x["width"] if "width" in x else 1 for x in top["pinmux"]["ios"]]) +max_sigwidth = len("{}".format(max_sigwidth)) + +clks_attr = top['clocks'] +cpu_clk = top['clocks']['hier_paths']['top'] + "clk_proc_main" +cpu_rst = top["reset_paths"]["sys"] +dm_rst = top["reset_paths"]["lc"] +esc_clk = top['clocks']['hier_paths']['top'] + "clk_io_div4_timers" +esc_rst = top["reset_paths"]["sys_io_div4"] + +unused_resets = lib.get_unused_resets(top) +unused_im_defs, undriven_im_defs = lib.get_dangling_im_def(top["inter_signal"]["definitions"]) + +has_toplevel_rom = False +for m in top['memory']: + if m['type'] == 'rom': + has_toplevel_rom = True + +%>\ +module top_${top["name"]} #( + // Auto-inferred parameters +% for m in top["module"]: + % if not lib.is_inst(m): +<% continue %> + % endif + % for p_exp in filter(lambda p: p.get("expose") == "true", m["param_list"]): + parameter ${p_exp["type"]} ${p_exp["name_top"]} = ${p_exp["default"]}, + % endfor +% endfor + + // Manually defined parameters +% if has_toplevel_rom: + parameter BootRomInitFile = "", +% endif + parameter ibex_pkg::regfile_e IbexRegFile = ibex_pkg::RegFileFF, + parameter bit IbexICache = 1, + parameter bit IbexPipeLine = 0, + parameter bit SecureIbex = 1 +) ( + // Reset, clocks defined as part of intermodule + input rst_ni, + +% if num_mio_pads != 0: + // Multiplexed I/O + input ${lib.bitarray(num_mio_pads, max_sigwidth)} mio_in_i, + output logic ${lib.bitarray(num_mio_pads, max_sigwidth)} mio_out_o, + output logic ${lib.bitarray(num_mio_pads, max_sigwidth)} mio_oe_o, +% endif +% if num_dio_total != 0: + // Dedicated I/O + input ${lib.bitarray(num_dio_total, max_sigwidth)} dio_in_i, + output logic ${lib.bitarray(num_dio_total, max_sigwidth)} dio_out_o, + output logic ${lib.bitarray(num_dio_total, max_sigwidth)} dio_oe_o, +% endif + +% if "pinmux" in top: + // pad attributes to padring + output prim_pad_wrapper_pkg::pad_attr_t [pinmux_reg_pkg::NMioPads-1:0] mio_attr_o, + output prim_pad_wrapper_pkg::pad_attr_t [pinmux_reg_pkg::NDioPads-1:0] dio_attr_o, +% endif + +% if num_im != 0: + + // Inter-module Signal External type + % for sig in top["inter_signal"]["external"]: + ${"input " if sig["direction"] == "in" else "output"} ${lib.im_defname(sig)} ${lib.bitarray(sig["width"],1)} ${sig["signame"]}, + % endfor + + // Flash specific voltages + inout [1:0] flash_test_mode_a_io, + inout flash_test_voltage_h_io, + + // OTP specific voltages + inout otp_ext_voltage_h_io, + +% endif + input scan_rst_ni, // reset used for test mode + input scan_en_i, + input lc_ctrl_pkg::lc_tx_t scanmode_i // lc_ctrl_pkg::On for Scan +); + + // JTAG IDCODE for development versions of this code. + // Manufacturers of OpenTitan chips must replace this code with one of their + // own IDs. + // Field structure as defined in the IEEE 1149.1 (JTAG) specification, + // section 12.1.1. + localparam logic [31:0] JTAG_IDCODE = { + 4'h0, // Version + 16'h4F54, // Part Number: "OT" + 11'h426, // Manufacturer Identity: Google + 1'b1 // (fixed) + }; + + import tlul_pkg::*; + import top_pkg::*; + import tl_main_pkg::*; + import top_${top["name"]}_pkg::*; + // Compile-time random constants + import top_${top["name"]}_rnd_cnst_pkg::*; + + // Signals + logic [${num_mio_inputs - 1}:0] mio_p2d; + logic [${num_mio_outputs - 1}:0] mio_d2p; + logic [${num_mio_outputs - 1}:0] mio_en_d2p; + logic [${num_dio_total - 1}:0] dio_p2d; + logic [${num_dio_total - 1}:0] dio_d2p; + logic [${num_dio_total - 1}:0] dio_en_d2p; +% for m in top["module"]: + % if not lib.is_inst(m): +<% continue %> + % endif +<% + block = name_to_block[m['type']] + inouts, inputs, outputs = block.xputs +%>\ + // ${m["name"]} + % for p_in in inputs + inouts: + logic ${lib.bitarray(p_in.bits.width(), max_sigwidth)} cio_${m["name"]}_${p_in.name}_p2d; + % endfor + % for p_out in outputs + inouts: + logic ${lib.bitarray(p_out.bits.width(), max_sigwidth)} cio_${m["name"]}_${p_out.name}_d2p; + logic ${lib.bitarray(p_out.bits.width(), max_sigwidth)} cio_${m["name"]}_${p_out.name}_en_d2p; + % endfor +% endfor + + +<% + # Interrupt source 0 is tied to 0 to conform RISC-V PLIC spec. + # So, total number of interrupts are the number of entries in the list + 1 + interrupt_num = sum([x["width"] if "width" in x else 1 for x in top["interrupt"]]) + 1 +%>\ + logic [${interrupt_num-1}:0] intr_vector; + // Interrupt source list +% for m in top["module"]: +<% + block = name_to_block[m['type']] +%>\ + % if not lib.is_inst(m): +<% continue %> + % endif + % for intr in block.interrupts: + % if intr.bits.width() != 1: + logic [${intr.bits.width()-1}:0] intr_${m["name"]}_${intr.name}; + % else: + logic intr_${m["name"]}_${intr.name}; + % endif + % endfor +% endfor + + +<% add_spaces = " " * len(str((interrupt_num-1).bit_length()-1)) %> + logic [0:0]${add_spaces}irq_plic; + logic [0:0]${add_spaces}msip; + logic [${(interrupt_num-1).bit_length()-1}:0] irq_id[1]; + logic [${(interrupt_num-1).bit_length()-1}:0] unused_irq_id[1]; + + // this avoids lint errors + assign unused_irq_id = irq_id; + + // Alert list + prim_alert_pkg::alert_tx_t [alert_pkg::NAlerts-1:0] alert_tx; + prim_alert_pkg::alert_rx_t [alert_pkg::NAlerts-1:0] alert_rx; + +% if not top["alert"]: + for (genvar k = 0; k < alert_pkg::NAlerts; k++) begin : gen_alert_tie_off + // tie off if no alerts present in the system + assign alert_tx[k].alert_p = 1'b0; + assign alert_tx[k].alert_n = 1'b1; + end +% endif + +## Inter-module Definitions +% if len(top["inter_signal"]["definitions"]) >= 1: + // define inter-module signals +% endif +% for sig in top["inter_signal"]["definitions"]: + ${lib.im_defname(sig)} ${lib.bitarray(sig["width"],1)} ${sig["signame"]}; +% endfor + +## Mixed connection to port +## Index greater than 0 means a port is assigned to an inter-module array +## whereas an index of 0 means a port is directly driven by a module + // define mixed connection to port +% for port in top['inter_signal']['external']: + % if port['conn_type'] and port['index'] > 0: + % if port['direction'] == 'in': + assign ${port['netname']}[${port['index']}] = ${port['signame']}; + % else: + assign ${port['signame']} = ${port['netname']}[${port['index']}]; + % endif + % elif port['conn_type']: + % if port['direction'] == 'in': + assign ${port['netname']} = ${port['signame']}; + % else: + assign ${port['signame']} = ${port['netname']}; + % endif + % endif +% endfor + +## Partial inter-module definition tie-off + // define partial inter-module tie-off +% for sig in unused_im_defs: + % for idx in range(sig['end_idx'], sig['width']): + ${lib.im_defname(sig)} unused_${sig["signame"]}${idx}; + % endfor +% endfor + + // assign partial inter-module tie-off +% for sig in unused_im_defs: + % for idx in range(sig['end_idx'], sig['width']): + assign unused_${sig["signame"]}${idx} = ${sig["signame"]}[${idx}]; + % endfor +% endfor +% for sig in undriven_im_defs: + % for idx in range(sig['end_idx'], sig['width']): + assign ${sig["signame"]}[${idx}] = ${sig["default"]}; + % endfor +% endfor + +## Inter-module signal collection + + // Unused reset signals +% for k, v in unused_resets.items(): + logic unused_d${v.lower()}_rst_${k}; +% endfor +% for k, v in unused_resets.items(): + assign unused_d${v.lower()}_rst_${k} = ${lib.get_reset_path(k, v, top['resets'])}; +% endfor + + // Non-debug module reset == reset for everything except for the debug module + logic ndmreset_req; + + // debug request from rv_dm to core + logic debug_req; + + // processor core + rv_core_ibex #( + .PMPEnable (1), + .PMPGranularity (0), // 2^(PMPGranularity+2) == 4 byte granularity + .PMPNumRegions (16), + .MHPMCounterNum (10), + .MHPMCounterWidth (32), + .RV32E (0), + .RV32M (ibex_pkg::RV32MSingleCycle), + .RV32B (ibex_pkg::RV32BNone), + .RegFile (IbexRegFile), + .BranchTargetALU (1), + .WritebackStage (1), + .ICache (IbexICache), + .ICacheECC (1), + .BranchPredictor (0), + .DbgTriggerEn (1), + .SecureIbex (SecureIbex), + .DmHaltAddr (ADDR_SPACE_DEBUG_MEM + dm::HaltAddress[31:0]), + .DmExceptionAddr (ADDR_SPACE_DEBUG_MEM + dm::ExceptionAddress[31:0]), + .PipeLine (IbexPipeLine) + ) u_rv_core_ibex ( + // clock and reset + .clk_i (${cpu_clk}), + .rst_ni (${cpu_rst}[rstmgr_pkg::Domain0Sel]), + .clk_esc_i (${esc_clk}), + .rst_esc_ni (${esc_rst}[rstmgr_pkg::Domain0Sel]), + .ram_cfg_i (ast_ram_1p_cfg), + // static pinning + .hart_id_i (32'b0), + .boot_addr_i (ADDR_SPACE_ROM_CTRL__ROM), + // TL-UL buses + .tl_i_o (main_tl_corei_req), + .tl_i_i (main_tl_corei_rsp), + .tl_d_o (main_tl_cored_req), + .tl_d_i (main_tl_cored_rsp), + // interrupts + .irq_software_i (msip), + .irq_timer_i (intr_rv_timer_timer_expired_0_0), + .irq_external_i (irq_plic), + // escalation input from alert handler (NMI) + .esc_tx_i (alert_handler_esc_tx[0]), + .esc_rx_o (alert_handler_esc_rx[0]), + // debug interface + .debug_req_i (debug_req), + // crash dump interface + .crash_dump_o (rv_core_ibex_crash_dump), + // CPU control signals + .lc_cpu_en_i (lc_ctrl_lc_cpu_en), + .pwrmgr_cpu_en_i (pwrmgr_aon_fetch_en), + .core_sleep_o (pwrmgr_aon_pwr_cpu.core_sleeping), + + // dft bypass + .scan_rst_ni, + .scanmode_i + ); + + // Debug Module (RISC-V Debug Spec 0.13) + // + + rv_dm #( + .NrHarts (1), + .IdcodeValue (JTAG_IDCODE) + ) u_dm_top ( + .clk_i (${cpu_clk}), + .rst_ni (${dm_rst}[rstmgr_pkg::Domain0Sel]), + .hw_debug_en_i (lc_ctrl_lc_hw_debug_en), + .scanmode_i, + .scan_rst_ni, + .ndmreset_o (ndmreset_req), + .dmactive_o (), + .debug_req_o (debug_req), + .unavailable_i (1'b0), + + // bus device with debug memory (for execution-based debug) + .tl_d_i (main_tl_debug_mem_req), + .tl_d_o (main_tl_debug_mem_rsp), + + // bus host (for system bus accesses, SBA) + .tl_h_o (main_tl_dm_sba_req), + .tl_h_i (main_tl_dm_sba_rsp), + + //JTAG + .jtag_req_i (pinmux_aon_rv_jtag_req), + .jtag_rsp_o (pinmux_aon_rv_jtag_rsp) + ); + + assign rstmgr_aon_cpu.ndmreset_req = ndmreset_req; + assign rstmgr_aon_cpu.rst_cpu_n = ${top["reset_paths"]["sys"]}[rstmgr_pkg::Domain0Sel]; + +## Memory Instantiation +% for m in top["memory"]: +<% + resets = m['reset_connections'] + clocks = m['clock_connections'] +%>\ + % if m["type"] == "ram_1p_scr": +<% + data_width = int(top["datawidth"]) + full_data_width = data_width + int(m["integ_width"]) + dw_byte = data_width // 8 + addr_width = ((int(m["size"], 0) // dw_byte) -1).bit_length() + sram_depth = (int(m["size"], 0) // dw_byte) + max_char = len(str(max(data_width, addr_width))) +%>\ + // sram device + logic ${lib.bitarray(1, max_char)} ${m["name"]}_req; + logic ${lib.bitarray(1, max_char)} ${m["name"]}_gnt; + logic ${lib.bitarray(1, max_char)} ${m["name"]}_we; + logic ${lib.bitarray(1, max_char)} ${m["name"]}_intg_err; + logic ${lib.bitarray(addr_width, max_char)} ${m["name"]}_addr; + logic ${lib.bitarray(full_data_width, max_char)} ${m["name"]}_wdata; + logic ${lib.bitarray(full_data_width, max_char)} ${m["name"]}_wmask; + logic ${lib.bitarray(full_data_width, max_char)} ${m["name"]}_rdata; + logic ${lib.bitarray(1, max_char)} ${m["name"]}_rvalid; + logic ${lib.bitarray(2, max_char)} ${m["name"]}_rerror; + + tlul_adapter_sram #( + .SramAw(${addr_width}), + .SramDw(${data_width}), + .Outstanding(2), + .CmdIntgCheck(1), + .EnableRspIntgGen(1), + .EnableDataIntgGen(0), + .EnableDataIntgPt(1) + ) u_tl_adapter_${m["name"]} ( + % for key in clocks: + .${key} (${clocks[key]}), + % endfor + % for key, value in resets.items(): + .${key} (${value}), + % endfor + .tl_i (${m["name"]}_tl_req), + .tl_o (${m["name"]}_tl_rsp), + .en_ifetch_i (${m["inter_signal_list"][3]["top_signame"]}), + .req_o (${m["name"]}_req), + .req_type_o (), + .gnt_i (${m["name"]}_gnt), + .we_o (${m["name"]}_we), + .addr_o (${m["name"]}_addr), + .wdata_o (${m["name"]}_wdata), + .wmask_o (${m["name"]}_wmask), + .intg_error_o(${m["name"]}_intg_err), + .rdata_i (${m["name"]}_rdata), + .rvalid_i (${m["name"]}_rvalid), + .rerror_i (${m["name"]}_rerror) + ); + +<% +mem_name = m["name"].split("_") +mem_name = lib.Name(mem_name[1:]) +%>\ + prim_ram_1p_scr #( + .Width(${full_data_width}), + .Depth(${sram_depth}), + .EnableParity(0), + .LfsrWidth(${data_width}), + .StatePerm(RndCnstSramCtrl${mem_name.as_camel_case()}SramLfsrPerm), + .DataBitsPerMask(1), // TODO: Temporary change to ensure byte updates can still be done + .DiffWidth(8) + ) u_ram1p_${m["name"]} ( + % for key in clocks: + .${key} (${clocks[key]}), + % endfor + % for key, value in resets.items(): + .${key} (${value}), + % endfor + + .key_valid_i (${m["inter_signal_list"][1]["top_signame"]}_req.valid), + .key_i (${m["inter_signal_list"][1]["top_signame"]}_req.key), + .nonce_i (${m["inter_signal_list"][1]["top_signame"]}_req.nonce), + .init_req_i (${m["inter_signal_list"][2]["top_signame"]}_req.req), + .init_seed_i (${m["inter_signal_list"][2]["top_signame"]}_req.seed), + .init_ack_o (${m["inter_signal_list"][2]["top_signame"]}_rsp.ack), + + .req_i (${m["name"]}_req), + .intg_error_i(${m["name"]}_intg_err), + .gnt_o (${m["name"]}_gnt), + .write_i (${m["name"]}_we), + .addr_i (${m["name"]}_addr), + .wdata_i (${m["name"]}_wdata), + .wmask_i (${m["name"]}_wmask), + .rdata_o (${m["name"]}_rdata), + .rvalid_o (${m["name"]}_rvalid), + .rerror_o (${m["name"]}_rerror), + .raddr_o (${m["inter_signal_list"][1]["top_signame"]}_rsp.raddr), + .intg_error_o(${m["inter_signal_list"][4]["top_signame"]}), + .cfg_i (ram_1p_cfg_i) + ); + + assign ${m["inter_signal_list"][1]["top_signame"]}_rsp.rerror = ${m["name"]}_rerror; + + % elif m["type"] == "rom": +<% + data_width = int(top["datawidth"]) + full_data_width = data_width + int(m['integ_width']) + dw_byte = data_width // 8 + addr_width = ((int(m["size"], 0) // dw_byte) -1).bit_length() + rom_depth = (int(m["size"], 0) // dw_byte) + max_char = len(str(max(data_width, addr_width))) +%>\ + // ROM device + logic ${lib.bitarray(1, max_char)} ${m["name"]}_req; + logic ${lib.bitarray(addr_width, max_char)} ${m["name"]}_addr; + logic ${lib.bitarray(full_data_width, max_char)} ${m["name"]}_rdata; + logic ${lib.bitarray(1, max_char)} ${m["name"]}_rvalid; + + tlul_adapter_sram #( + .SramAw(${addr_width}), + .SramDw(${data_width}), + .Outstanding(2), + .ErrOnWrite(1), + .CmdIntgCheck(1), + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) // TODO: Needs to be updated for intgerity passthrough + ) u_tl_adapter_${m["name"]} ( + % for key in clocks: + .${key} (${clocks[key]}), + % endfor + % for key, value in resets.items(): + .${key} (${value}), + % endfor + + .tl_i (${m["name"]}_tl_req), + .tl_o (${m["name"]}_tl_rsp), + .en_ifetch_i (tlul_pkg::InstrEn), + .req_o (${m["name"]}_req), + .req_type_o (), + .gnt_i (1'b1), // Always grant as only one requester exists + .we_o (), + .addr_o (${m["name"]}_addr), + .wdata_o (), + .wmask_o (), + .intg_error_o(), // Connect to ROM checker and ROM scramble later + .rdata_i (${m["name"]}_rdata[${data_width-1}:0]), + .rvalid_i (${m["name"]}_rvalid), + .rerror_i (2'b00) + ); + + prim_rom_adv #( + .Width(${full_data_width}), + .Depth(${rom_depth}), + .MemInitFile(BootRomInitFile) + ) u_rom_${m["name"]} ( + % for key in clocks: + .${key} (${clocks[key]}), + % endfor + % for key, value in resets.items(): + .${key} (${value}), + % endfor + .req_i (${m["name"]}_req), + .addr_i (${m["name"]}_addr), + .rdata_o (${m["name"]}_rdata), + .rvalid_o (${m["name"]}_rvalid), + .cfg_i (rom_cfg_i) + ); + + % elif m["type"] == "eflash": + + // host to flash communication + logic flash_host_req; + tlul_pkg::tl_type_e flash_host_req_type; + logic flash_host_req_rdy; + logic flash_host_req_done; + logic flash_host_rderr; + logic [flash_ctrl_pkg::BusWidth-1:0] flash_host_rdata; + logic [flash_ctrl_pkg::BusAddrW-1:0] flash_host_addr; + logic flash_host_intg_err; + + tlul_adapter_sram #( + .SramAw(flash_ctrl_pkg::BusAddrW), + .SramDw(flash_ctrl_pkg::BusWidth), + .Outstanding(2), + .ByteAccess(0), + .ErrOnWrite(1), + .CmdIntgCheck(1), + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_tl_adapter_${m["name"]} ( + % for key in clocks: + .${key} (${clocks[key]}), + % endfor + % for key, value in resets.items(): + .${key} (${value}), + % endfor + + .tl_i (${m["name"]}_tl_req), + .tl_o (${m["name"]}_tl_rsp), + .en_ifetch_i (tlul_pkg::InstrEn), // tie this to secure boot somehow + .req_o (flash_host_req), + .req_type_o (flash_host_req_type), + .gnt_i (flash_host_req_rdy), + .we_o (), + .addr_o (flash_host_addr), + .wdata_o (), + .wmask_o (), + .intg_error_o(flash_host_intg_err), + .rdata_i (flash_host_rdata), + .rvalid_i (flash_host_req_done), + .rerror_i ({flash_host_rderr,1'b0}) + ); + + flash_phy u_flash_${m["name"]} ( + % for key in clocks: + .${key} (${clocks[key]}), + % endfor + % for key, value in resets.items(): + .${key} (${value}), + % endfor + .host_req_i (flash_host_req), + .host_intg_err_i (flash_host_intg_err), + .host_req_type_i (flash_host_req_type), + .host_addr_i (flash_host_addr), + .host_req_rdy_o (flash_host_req_rdy), + .host_req_done_o (flash_host_req_done), + .host_rderr_o (flash_host_rderr), + .host_rdata_o (flash_host_rdata), + .flash_ctrl_i (${m["inter_signal_list"][0]["top_signame"]}_req), + .flash_ctrl_o (${m["inter_signal_list"][0]["top_signame"]}_rsp), + .lc_nvm_debug_en_i (${m["inter_signal_list"][2]["top_signame"]}), + .flash_bist_enable_i, + .flash_power_down_h_i, + .flash_power_ready_h_i, + .flash_test_mode_a_io, + .flash_test_voltage_h_io, + .flash_alert_o, + .scanmode_i, + .scan_en_i, + .scan_rst_ni + ); + + % else: + // flash memory is embedded within controller + % endif +% endfor +## Peripheral Instantiation + +<% alert_idx = 0 %> +% for m in top["module"]: +<% +if not lib.is_inst(m): + continue + +block = name_to_block[m['type']] +inouts, inputs, outputs = block.xputs + +port_list = inputs + outputs + inouts +max_sigwidth = max(len(x.name) for x in port_list) if port_list else 0 +max_intrwidth = (max(len(x.name) for x in block.interrupts) + if block.interrupts else 0) +%>\ + % if m["param_list"] or block.alerts: + ${m["type"]} #( + % if block.alerts: +<% +w = len(block.alerts) +slice = str(alert_idx+w-1) + ":" + str(alert_idx) +%>\ + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[${slice}])${"," if m["param_list"] else ""} + % endif + % for i in m["param_list"]: + .${i["name"]}(${i["name_top" if i.get("expose") == "true" or i.get("randtype", "none") != "none" else "default"]})${"," if not loop.last else ""} + % endfor + ) u_${m["name"]} ( + % else: + ${m["type"]} u_${m["name"]} ( + % endif + % for p_in in inputs + inouts: + % if loop.first: + + // Input + % endif + .${lib.ljust("cio_"+p_in.name+"_i",max_sigwidth+9)} (cio_${m["name"]}_${p_in.name}_p2d), + % endfor + % for p_out in outputs + inouts: + % if loop.first: + + // Output + % endif + .${lib.ljust("cio_"+p_out.name+"_o", max_sigwidth+9)} (cio_${m["name"]}_${p_out.name}_d2p), + .${lib.ljust("cio_"+p_out.name+"_en_o",max_sigwidth+9)} (cio_${m["name"]}_${p_out.name}_en_d2p), + % endfor + % for intr in block.interrupts: + % if loop.first: + + // Interrupt + % endif + .${lib.ljust("intr_"+intr.name+"_o",max_intrwidth+7)} (intr_${m["name"]}_${intr.name}), + % endfor + % if block.alerts: + % for alert in block.alerts: + // [${alert_idx}]: ${alert.name}<% alert_idx += 1 %> + % endfor + .alert_tx_o ( alert_tx[${slice}] ), + .alert_rx_i ( alert_rx[${slice}] ), + % endif + ## TODO: Inter-module Connection + % if m.get('inter_signal_list'): + + // Inter-module signals + % for sig in m['inter_signal_list']: + ## TODO: handle below condition in lib.py + % if sig['type'] == "req_rsp": + .${lib.im_portname(sig,"req")}(${lib.im_netname(sig, "req")}), + .${lib.im_portname(sig,"rsp")}(${lib.im_netname(sig, "rsp")}), + % elif sig['type'] == "uni": + ## TODO: Broadcast type + ## TODO: default for logic type + .${lib.im_portname(sig)}(${lib.im_netname(sig)}), + % endif + % endfor + % endif + % if m["type"] == "rv_plic": + + .intr_src_i (intr_vector), + .irq_o (irq_plic), + .irq_id_o (irq_id), + .msip_o (msip), + % endif + % if m["type"] == "pinmux": + + .periph_to_mio_i (mio_d2p ), + .periph_to_mio_oe_i (mio_en_d2p ), + .mio_to_periph_o (mio_p2d ), + + .mio_attr_o, + .mio_out_o, + .mio_oe_o, + .mio_in_i, + + .periph_to_dio_i (dio_d2p ), + .periph_to_dio_oe_i (dio_en_d2p ), + .dio_to_periph_o (dio_p2d ), + + .dio_attr_o, + .dio_out_o, + .dio_oe_o, + .dio_in_i, + + % endif + % if m["type"] == "alert_handler": + // alert signals + .alert_rx_o ( alert_rx ), + .alert_tx_i ( alert_tx ), + % endif + % if m["type"] == "otp_ctrl": + .otp_ext_voltage_h_io, + % endif + % if block.scan: + .scanmode_i, + % endif + % if block.scan_reset: + .scan_rst_ni, + % endif + % if block.scan_en: + .scan_en_i, + % endif + + // Clock and reset connections + % for k, v in m["clock_connections"].items(): + .${k} (${v}), + % endfor + % for k, v in m["reset_connections"].items(): + .${k} (${v})${"," if not loop.last else ""} + % endfor + ); + +% endfor + // interrupt assignments +<% base = interrupt_num %>\ + assign intr_vector = { + % for intr in top["interrupt"][::-1]: +<% base -= intr["width"] %>\ + intr_${intr["name"]}, // IDs [${base} +: ${intr['width']}] + % endfor + 1'b 0 // ID [0 +: 1] is a special case and tied to zero. + }; + + // TL-UL Crossbar +% for xbar in top["xbar"]: +<% + name_len = max([len(x["name"]) for x in xbar["nodes"]]); +%>\ + xbar_${xbar["name"]} u_xbar_${xbar["name"]} ( + % for k, v in xbar["clock_connections"].items(): + .${k} (${v}), + % endfor + % for k, v in xbar["reset_connections"].items(): + .${k} (${v}), + % endfor + + ## Inter-module signal + % for sig in xbar["inter_signal_list"]: +<% assert sig['type'] == "req_rsp" %>\ + // port: ${sig['name']} + .${lib.im_portname(sig,"req")}(${lib.im_netname(sig, "req")}), + .${lib.im_portname(sig,"rsp")}(${lib.im_netname(sig, "rsp")}), + + % endfor + + .scanmode_i + ); +% endfor + +% if "pinmux" in top: + // Pinmux connections + // All muxed inputs + % for sig in top["pinmux"]["ios"]: + % if sig["connection"] == "muxed" and sig["type"] in ["inout", "input"]: +<% literal = lib.get_io_enum_literal(sig, 'mio_in') %>\ + assign cio_${sig["name"]}_p2d${"[" + str(sig["idx"]) +"]" if sig["idx"] !=-1 else ""} = mio_p2d[${literal}]; + % endif + % endfor + + // All muxed outputs + % for sig in top["pinmux"]["ios"]: + % if sig["connection"] == "muxed" and sig["type"] in ["inout", "output"]: +<% literal = lib.get_io_enum_literal(sig, 'mio_out') %>\ + assign mio_d2p[${literal}] = cio_${sig["name"]}_d2p${"[" + str(sig["idx"]) +"]" if sig["idx"] !=-1 else ""}; + % endif + % endfor + + // All muxed output enables + % for sig in top["pinmux"]["ios"]: + % if sig["connection"] == "muxed" and sig["type"] in ["inout", "output"]: +<% literal = lib.get_io_enum_literal(sig, 'mio_out') %>\ + assign mio_en_d2p[${literal}] = cio_${sig["name"]}_en_d2p${"[" + str(sig["idx"]) +"]" if sig["idx"] !=-1 else ""}; + % endif + % endfor + + // All dedicated inputs +<% idx = 0 %>\ + logic [${num_dio_total-1}:0] unused_dio_p2d; + assign unused_dio_p2d = dio_p2d; + % for sig in top["pinmux"]["ios"]: +<% literal = lib.get_io_enum_literal(sig, 'dio') %>\ + % if sig["connection"] != "muxed" and sig["type"] in ["inout"]: + assign cio_${sig["name"]}_p2d${"[" + str(sig["idx"]) +"]" if sig["idx"] !=-1 else ""} = dio_p2d[${literal}]; + % elif sig["connection"] != "muxed" and sig["type"] in ["input"]: + assign cio_${sig["name"]}_p2d${"[" + str(sig["idx"]) +"]" if sig["idx"] !=-1 else ""} = dio_p2d[${literal}]; + % endif + % endfor + + // All dedicated outputs + % for sig in top["pinmux"]["ios"]: +<% literal = lib.get_io_enum_literal(sig, 'dio') %>\ + % if sig["connection"] != "muxed" and sig["type"] in ["inout"]: + assign dio_d2p[${literal}] = cio_${sig["name"]}_d2p${"[" + str(sig["idx"]) +"]" if sig["idx"] !=-1 else ""}; + % elif sig["connection"] != "muxed" and sig["type"] in ["input"]: + assign dio_d2p[${literal}] = 1'b0; + % elif sig["connection"] != "muxed" and sig["type"] in ["output"]: + assign dio_d2p[${literal}] = cio_${sig["name"]}_d2p${"[" + str(sig["idx"]) +"]" if sig["idx"] !=-1 else ""}; + % endif + % endfor + + // All dedicated output enables + % for sig in top["pinmux"]["ios"]: +<% literal = lib.get_io_enum_literal(sig, 'dio') %>\ + % if sig["connection"] != "muxed" and sig["type"] in ["inout"]: + assign dio_en_d2p[${literal}] = cio_${sig["name"]}_en_d2p${"[" + str(sig["idx"]) +"]" if sig["idx"] !=-1 else ""}; + % elif sig["connection"] != "muxed" and sig["type"] in ["input"]: + assign dio_en_d2p[${literal}] = 1'b0; + % elif sig["connection"] != "muxed" and sig["type"] in ["output"]: + assign dio_en_d2p[${literal}] = cio_${sig["name"]}_en_d2p${"[" + str(sig["idx"]) +"]" if sig["idx"] !=-1 else ""}; + % endif + % endfor + +% endif + + // make sure scanmode_i is never X (including during reset) + `ASSERT_KNOWN(scanmodeKnown, scanmode_i, clk_main_i, 0) + +endmodule diff --git a/hw/vendored_ips/gpio/util/reggen/topgen/templates/toplevel_memory.h.tpl b/hw/vendored_ips/gpio/util/reggen/topgen/templates/toplevel_memory.h.tpl new file mode 100644 index 00000000..bfb0274a --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/topgen/templates/toplevel_memory.h.tpl @@ -0,0 +1,62 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#ifndef _TOP_${top["name"].upper()}_MEMORY_H_ +#define _TOP_${top["name"].upper()}_MEMORY_H_ + +/** + * @file + * @brief Assembler-only Top-Specific Definitions. + * + * This file contains preprocessor definitions for use within assembly code. + * + * These are not shared with C/C++ code because these are only allowed to be + * preprocessor definitions, no data or type declarations are allowed. The + * assembler is also stricter about literals (not allowing suffixes for + * signed/unsigned which are sensible to use for unsigned values in C/C++). + */ + +// Include guard for assembler +#ifdef __ASSEMBLER__ + +/** + * Memory base address for rom in top earlgrey. + */ +#define TOP_EARLGREY_ROM_BASE_ADDR 0x00008000 + +/** + * Memory size for rom in top earlgrey. + */ +#define TOP_EARLGREY_ROM_SIZE_BYTES 0x4000 + +% for m in top["memory"]: +/** + * Memory base address for ${m["name"]} in top ${top["name"]}. + */ +#define TOP_${top["name"].upper()}_${m["name"].upper()}_BASE_ADDR ${m["base_addr"]} + +/** + * Memory size for ${m["name"]} in top ${top["name"]}. + */ +#define TOP_${top["name"].upper()}_${m["name"].upper()}_SIZE_BYTES ${m["size"]} + +% endfor + +% for (inst_name, if_name), region in helper.devices(): +<% + if_desc = inst_name if if_name is None else '{} device on {}'.format(if_name, inst_name) + hex_base_addr = "0x{:X}".format(region.base_addr) + base_addr_name = region.base_addr_name().as_c_define() +%>\ +/** + * Peripheral base address for ${if_desc} in top ${top["name"]}. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define ${base_addr_name} ${hex_base_addr} +% endfor +#endif // __ASSEMBLER__ + +#endif // _TOP_${top["name"].upper()}_MEMORY_H_ diff --git a/hw/vendored_ips/gpio/util/reggen/topgen/templates/toplevel_memory.ld.tpl b/hw/vendored_ips/gpio/util/reggen/topgen/templates/toplevel_memory.ld.tpl new file mode 100644 index 00000000..42c41989 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/topgen/templates/toplevel_memory.ld.tpl @@ -0,0 +1,30 @@ +/* Copyright lowRISC contributors. */ +/* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ +/* SPDX-License-Identifier: Apache-2.0 */ +<%! +def memory_to_flags(memory): + memory_type = memory["type"] + memory_access = memory.get("swaccess", "rw") + assert memory_access in ["ro", "rw"] + + flags_str = "" + if memory_access == "ro": + flags_str += "r" + else: + flags_str += "rw" + + if memory_type in ["rom", "eflash"]: + flags_str += "x" + + return flags_str +%>\ + +/** + * Partial linker script for chip memory configuration. + */ +MEMORY { + rom(rx) : ORIGIN = 0x00008000, LENGTH = 0x4000 +% for m in top["memory"]: + ${m["name"]}(${memory_to_flags(m)}) : ORIGIN = ${m["base_addr"]}, LENGTH = ${m["size"]} +% endfor +} diff --git a/hw/vendored_ips/gpio/util/reggen/topgen/templates/toplevel_pkg.sv.tpl b/hw/vendored_ips/gpio/util/reggen/topgen/templates/toplevel_pkg.sv.tpl new file mode 100644 index 00000000..a25d4fd7 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/topgen/templates/toplevel_pkg.sv.tpl @@ -0,0 +1,112 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +${gencmd} +<% +import topgen.lib as lib +%>\ +package top_${top["name"]}_pkg; +% for (inst_name, if_name), region in helper.devices(): +<% + if_desc = inst_name if if_name is None else '{} device on {}'.format(if_name, inst_name) + hex_base_addr = "32'h{:X}".format(region.base_addr) + hex_size_bytes = "32'h{:X}".format(region.size_bytes) +%>\ + /** + * Peripheral base address for ${if_desc} in top ${top["name"]}. + */ + parameter int unsigned ${region.base_addr_name().as_c_define()} = ${hex_base_addr}; + + /** + * Peripheral size in bytes for ${if_desc} in top ${top["name"]}. + */ + parameter int unsigned ${region.size_bytes_name().as_c_define()} = ${hex_size_bytes}; + +% endfor +% for name, region in helper.memories(): +<% + hex_base_addr = "32'h{:x}".format(region.base_addr) + hex_size_bytes = "32'h{:x}".format(region.size_bytes) +%>\ + /** + * Memory base address for ${name} in top ${top["name"]}. + */ + parameter int unsigned ${region.base_addr_name().as_c_define()} = ${hex_base_addr}; + + /** + * Memory size for ${name} in top ${top["name"]}. + */ + parameter int unsigned ${region.size_bytes_name().as_c_define()} = ${hex_size_bytes}; + +% endfor + + // Enumeration of IO power domains. + // Only used in ASIC target. + typedef enum logic [${len(top["pinout"]["banks"]).bit_length()-1}:0] { +% for bank in top["pinout"]["banks"]: + ${lib.Name(['io', 'bank', bank]).as_camel_case()} = ${loop.index}, +% endfor + IoBankCount = ${len(top["pinout"]["banks"])} + } pwr_dom_e; + + // Enumeration for MIO signals on the top-level. + typedef enum int unsigned { +% for sig in top["pinmux"]["ios"]: + % if sig['type'] in ['inout', 'input'] and sig['connection'] == 'muxed': + ${lib.get_io_enum_literal(sig, 'mio_in')} = ${sig['glob_idx']}, + % endif +% endfor +<% total = top["pinmux"]['io_counts']['muxed']['inouts'] + \ + top["pinmux"]['io_counts']['muxed']['inputs'] %>\ + ${lib.Name.from_snake_case("mio_in_count").as_camel_case()} = ${total} + } mio_in_e; + + typedef enum { +% for sig in top["pinmux"]["ios"]: + % if sig['type'] in ['inout', 'output'] and sig['connection'] == 'muxed': + ${lib.get_io_enum_literal(sig, 'mio_out')} = ${sig['glob_idx']}, + % endif +% endfor +<% total = top["pinmux"]['io_counts']['muxed']['inouts'] + \ + top["pinmux"]['io_counts']['muxed']['outputs'] %>\ + ${lib.Name.from_snake_case("mio_out_count").as_camel_case()} = ${total} + } mio_out_e; + + // Enumeration for DIO signals, used on both the top and chip-levels. + typedef enum int unsigned { +% for sig in top["pinmux"]["ios"]: + % if sig['connection'] != 'muxed': + ${lib.get_io_enum_literal(sig, 'dio')} = ${sig['glob_idx']}, + % endif +% endfor +<% total = top["pinmux"]['io_counts']['dedicated']['inouts'] + \ + top["pinmux"]['io_counts']['dedicated']['inputs'] + \ + top["pinmux"]['io_counts']['dedicated']['outputs'] %>\ + ${lib.Name.from_snake_case("dio_count").as_camel_case()} = ${total} + } dio_e; + + // Raw MIO/DIO input array indices on chip-level. + // TODO: Does not account for target specific stubbed/added pads. + // Need to make a target-specific package for those. + typedef enum int unsigned { +% for pad in top["pinout"]["pads"]: + % if pad["connection"] == "muxed": + ${lib.Name.from_snake_case("mio_pad_" + pad["name"]).as_camel_case()} = ${pad["idx"]}, + % endif +% endfor + ${lib.Name.from_snake_case("mio_pad_count").as_camel_case()} + } mio_pad_e; + + typedef enum int unsigned { +% for pad in top["pinout"]["pads"]: + % if pad["connection"] != "muxed": + ${lib.Name.from_snake_case("dio_pad_" + pad["name"]).as_camel_case()} = ${pad["idx"]}, + % endif +% endfor + ${lib.Name.from_snake_case("dio_pad_count").as_camel_case()} + } dio_pad_e; + + // TODO: Enumeration for PLIC Interrupt source peripheral. + // TODO: Enumeration for PLIC Interrupt Ids. + +endpackage diff --git a/hw/vendored_ips/gpio/util/reggen/topgen/templates/toplevel_rnd_cnst_pkg.sv.tpl b/hw/vendored_ips/gpio/util/reggen/topgen/templates/toplevel_rnd_cnst_pkg.sv.tpl new file mode 100644 index 00000000..9700c3d5 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/topgen/templates/toplevel_rnd_cnst_pkg.sv.tpl @@ -0,0 +1,44 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +${gencmd} +<% + def make_blocked_sv_literal(hexstr, randwidth): + """This chops the random hexstring into manageable blocks of 64 chars such that the + lines do not get too long. + """ + # Make all-caps and drop '0x' preamble + hexstr = str(hexstr[2:]).upper() + # Block width in hex chars + blockwidth = 64 + remainder = randwidth % (4*blockwidth) + numbits = remainder if remainder else 4*blockwidth + idx = 0 + hexblocks = [] + while randwidth > 0: + hexstr = hexstr[idx:] + randwidth -= numbits + idx = (numbits + 3) // 4 + hexblocks.append(str(numbits) + "'h" + hexstr[0:idx]) + numbits = 4*blockwidth + return hexblocks +%> +package top_${top["name"]}_rnd_cnst_pkg; + +% for m in top["module"]: + % for p in filter(lambda p: p.get("randtype") in ["data", "perm"], m["param_list"]): + % if loop.first: + //////////////////////////////////////////// + // ${m['name']} + //////////////////////////////////////////// + % endif + // ${p['desc']} + parameter ${p["type"]} ${p["name_top"]} = { + % for block in make_blocked_sv_literal(p["default"], p["randwidth"]): + ${block}${"" if loop.last else ","} + % endfor + }; + + % endfor +% endfor +endpackage : top_${top["name"]}_rnd_cnst_pkg diff --git a/hw/vendored_ips/gpio/util/reggen/topgen/templates/xbar_env_pkg__params.sv.tpl b/hw/vendored_ips/gpio/util/reggen/topgen/templates/xbar_env_pkg__params.sv.tpl new file mode 100644 index 00000000..63c59fe1 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/topgen/templates/xbar_env_pkg__params.sv.tpl @@ -0,0 +1,88 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_env_pkg__params generated by `topgen.py` tool + +<% + from collections import OrderedDict + + def is_device_a_xbar(dev_name): + for xbar in top["xbar"]: + if xbar["name"] == dev_name: + return 1 + return 0 + + # recursively find all non-xbar devices under this xbar + def get_xbar_edge_nodes(xbar_name): + edge_devices = [] + for xbar in top["xbar"]: + if xbar["name"] == xbar_name: + for host, devices in xbar["connections"].items(): + for dev_name in devices: + if is_device_a_xbar(dev_name): + edge_devices.extend(get_xbar_edge_nodes()) + else: + edge_devices.append(dev_name) + + return edge_devices + + # find device xbar and assign all its device nodes to it: "peri" -> "uart, gpio, ..." + xbar_device_dict = OrderedDict() + + for xbar in top["xbar"]: + for n in xbar["nodes"]: + if n["type"] == "device" and n["xbar"]: + xbar_device_dict[n["name"]] = get_xbar_edge_nodes(n["name"]) + + # create the mapping: host with the corresponding devices map + host_dev_map = OrderedDict() + for host, devices in top["xbar"][0]["connections"].items(): + dev_list = [] + for dev in devices: + if dev not in xbar_device_dict.keys(): + dev_list.append(dev) + else: + dev_list.extend(xbar_device_dict[dev]) + host_dev_map[host] = dev_list + +%>\ + +// List of Xbar device memory map +tl_device_t xbar_devices[$] = '{ +% for xbar in top["xbar"]: + % for device in xbar["nodes"]: + % if device["type"] == "device" and not device["xbar"]: + '{"${device["name"].replace('.', '__')}", '{ + % for addr in device["addr_range"]: +<% + start_addr = int(addr["base_addr"], 0) + end_addr = start_addr + int(addr["size_byte"], 0) - 1 +%>\ + '{32'h${"%08x" % start_addr}, 32'h${"%08x" % end_addr}}${"," if not loop.last else ""} + % endfor + }}${"," if not loop.last or xbar != top["xbar"][-1] else "};"} + % endif + % endfor +% endfor + + // List of Xbar hosts +tl_host_t xbar_hosts[$] = '{ +% for host in host_dev_map.keys(): + '{"${host}", ${loop.index}, '{ +<% + host_devices = host_dev_map[host]; +%>\ + % for device in host_devices: + % if loop.last: + "${device}"}} + % else: + "${device}", + % endif + % endfor + % if loop.last: +}; + % else: + , + % endif +% endfor diff --git a/hw/vendored_ips/gpio/util/reggen/topgen/top.py b/hw/vendored_ips/gpio/util/reggen/topgen/top.py new file mode 100644 index 00000000..dcdf1cae --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/topgen/top.py @@ -0,0 +1,122 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +'''Code representing the entire chip for reggen''' + +from typing import Dict, List, Optional, Tuple, Union + +from reggen.ip_block import IpBlock +from reggen.params import ReggenParams +from reggen.reg_block import RegBlock +from reggen.window import Window + +_IFName = Tuple[str, Optional[str]] +_Triple = Tuple[int, str, IpBlock] + + +class Top: + '''An object representing the entire chip, as seen by reggen. + + This contains instances of some blocks (possibly multiple instances of each + block), starting at well-defined base addresses. It may also contain some + windows. These are memories that don't have their own comportable IP (so + aren't defined in a block), but still take up address space. + + ''' + + def __init__(self, + regwidth: int, + blocks: Dict[str, IpBlock], + instances: Dict[str, str], + if_addrs: Dict[Tuple[str, Optional[str]], int], + windows: List[Window], + attrs: Dict[str, str]): + '''Class initializer. + + regwidth is the width of the registers (which must match for all the + blocks) in bits. + + blocks is a map from block name to IpBlock object. + + instances is a map from instance name to the name of the block it + instantiates. Every block name that appears in instances must be a key + of blocks. + + if_addrs is a dictionary that maps the name of a device interface on + some instance of some block to its base address. A key of the form (n, + i) means "the device interface called i on an instance called n". If i + is None, this is an unnamed device interface. Every instance name (n) + that appears in connections must be a key of instances. + + windows is a list of windows (these contain base addresses already). + + attrs is a map from instance name to attr field of the block + + ''' + + self.regwidth = regwidth + self.blocks = blocks + self.instances = instances + self.if_addrs = if_addrs + self.attrs = attrs + + self.window_block = RegBlock(regwidth, ReggenParams()) + + # Generate one list of base addresses and objects (with each object + # either a block name and interface name or a window). While we're at + # it, construct inst_to_block_name and if_addrs. + merged = [] # type: List[Tuple[int, Union[_IFName, Window]]] + for full_if_name, addr in if_addrs.items(): + merged.append((addr, full_if_name)) + + inst_name, if_name = full_if_name + + # The instance name must match some key in instances, whose value + # should in turn match some key in blocks. + assert inst_name in instances + block_name = instances[inst_name] + assert block_name in blocks + + # Check that if_name is indeed the name of a device interface for + # that block. + block = blocks[block_name] + assert block.bus_interfaces.has_interface(False, if_name) + + for window in sorted(windows, key=lambda w: w.offset): + merged.append((window.offset, window)) + self.window_block.add_window(window) + + # A map from block name to the list of its instances. These instances + # are listed in increasing order of the lowest base address of one of + # their interfaces. The entries are added into the dict in the same + # order, so an iteration over items() will give blocks ordered by their + # first occurrence in the address map. + self.block_instances = {} # type: Dict[str, List[str]] + + # Walk the merged list in order of increasing base address. Check for + # overlaps and construct block_instances. + offset = 0 + for base_addr, item in sorted(merged, key=lambda pr: pr[0]): + # Make sure that this item doesn't overlap with the previous one + assert offset <= base_addr, item + + if isinstance(item, Window): + addrsep = (regwidth + 7) // 8 + offset = item.next_offset(addrsep) + continue + + inst_name, if_name = item + block_name = instances[inst_name] + block = blocks[block_name] + + lst = self.block_instances.setdefault(block_name, []) + if inst_name not in lst: + lst.append(inst_name) + + # This should be guaranteed by the fact that we've already checked + # the existence of a device interface. + assert if_name in block.reg_blocks + reg_block = block.reg_blocks[if_name] + + offset = base_addr + reg_block.offset diff --git a/hw/vendored_ips/gpio/util/reggen/topgen/top_uvm_reg.sv.tpl b/hw/vendored_ips/gpio/util/reggen/topgen/top_uvm_reg.sv.tpl new file mode 100644 index 00000000..1486a926 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/topgen/top_uvm_reg.sv.tpl @@ -0,0 +1,151 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// UVM registers auto-generated by `reggen` containing UVM definitions for the entire top-level +<%! + from topgen.gen_dv import sv_base_addr + from reggen.gen_dv import bcname, mcname, miname +%> +## +## This template is used for chip-wide tests. It expects to be run with the +## following arguments +## +## top a Top object +## +## dv_base_prefix a string for the base register type. If it is FOO, then +## we will inherit from FOO_reg (assumed to be a subclass +## of uvm_reg). +## +## Like uvm_reg.sv.tpl, we use functions from uvm_reg_base.sv.tpl to define +## per-device-interface code. +## +<%namespace file="uvm_reg_base.sv.tpl" import="*"/>\ +## +## +## Waive the package-filename check: we're going to be defining all sorts of +## packages in a single file. + +// verilog_lint: waive-start package-filename +## +## Iterate over the device interfaces of blocks in Top, constructing a package +## for each. Sorting items like this guarantees we'll work alphabetically in +## block name. +% for block_name, block in sorted(top.blocks.items()): +% for if_name, rb in block.reg_blocks.items(): +<% + if_suffix = '' if if_name is None else '_' + if_name + esc_if_name = block_name.lower() + if_suffix + if_desc = '' if if_name is None else '; interface {}'.format(if_name) + reg_block_path = 'u_reg' + if_suffix + reg_block_path = reg_block_path if block.hier_path is None else block.hier_path + "." + reg_block_path +%>\ +// Block: ${block_name.lower()}${if_desc} +${make_ral_pkg(dv_base_prefix, top.regwidth, reg_block_path, rb, esc_if_name)} +% endfor +% endfor +## +## +## Now that we've made the block-level packages, re-instate the +## package-filename check. The only package left is chip_ral_pkg, which should +## match the generated filename. + +// verilog_lint: waive-start package-filename + +// Block: chip +package chip_ral_pkg; +<% + if_packages = [] + for block_name, block in sorted(top.blocks.items()): + for if_name in block.reg_blocks: + if_suffix = '' if if_name is None else '_' + if_name + if_packages.append('{}{}_ral_pkg'.format(block_name.lower(), if_suffix)) + + windows = top.window_block.windows +%>\ +${make_ral_pkg_hdr(dv_base_prefix, if_packages)} +${make_ral_pkg_fwd_decls('chip', [], windows)} +% for window in windows: + +${make_ral_pkg_window_class(dv_base_prefix, 'chip', window)} +% endfor + + class chip_reg_block extends ${dv_base_prefix}_reg_block; + // sub blocks +% for block_name, block in sorted(top.blocks.items()): +% for inst_name in top.block_instances[block_name.lower()]: +% for if_name, rb in block.reg_blocks.items(): +<% + if_suffix = '' if if_name is None else '_' + if_name + esc_if_name = block_name.lower() + if_suffix + if_inst = inst_name + if_suffix +%>\ + rand ${bcname(esc_if_name)} ${if_inst}; +% endfor +% endfor +% endfor +% if windows: + // memories +% for window in windows: + rand ${mcname('chip', window)} ${miname(window)}; +% endfor +% endif + + `uvm_object_utils(chip_reg_block) + + function new(string name = "chip_reg_block", + int has_coverage = UVM_NO_COVERAGE); + super.new(name, has_coverage); + endfunction : new + + virtual function void build(uvm_reg_addr_t base_addr, + csr_excl_item csr_excl = null); + // create default map + this.default_map = create_map(.name("default_map"), + .base_addr(base_addr), + .n_bytes(${top.regwidth//8}), + .endian(UVM_LITTLE_ENDIAN)); + if (csr_excl == null) begin + csr_excl = csr_excl_item::type_id::create("csr_excl"); + this.csr_excl = csr_excl; + end + + // create sub blocks and add their maps +% for block_name, block in sorted(top.blocks.items()): +% for inst_name in top.block_instances[block_name.lower()]: +% for if_name, rb in block.reg_blocks.items(): +<% + if_suffix = '' if if_name is None else '_' + if_name + esc_if_name = block_name.lower() + if_suffix + if_inst = inst_name + if_suffix + + if top.attrs.get(inst_name) == 'reggen_only': + hdl_path = 'tb.dut.u_' + inst_name + else: + hdl_path = 'tb.dut.top_earlgrey.u_' + inst_name + qual_if_name = (inst_name, if_name) + base_addr = top.if_addrs[qual_if_name] + base_addr_txt = sv_base_addr(top, qual_if_name) + + hpr_indent = (len(if_inst) + len('.set_hdl_path_root(')) * ' ' +%>\ + ${if_inst} = ${bcname(esc_if_name)}::type_id::create("${if_inst}"); + ${if_inst}.configure(.parent(this)); + ${if_inst}.build(.base_addr(base_addr + ${base_addr_txt}), .csr_excl(csr_excl)); + ${if_inst}.set_hdl_path_root("${hdl_path}", + ${hpr_indent}"BkdrRegPathRtl"); + ${if_inst}.set_hdl_path_root("${hdl_path}", + ${hpr_indent}"BkdrRegPathRtlCommitted"); + ${if_inst}.set_hdl_path_root("${hdl_path}", + ${hpr_indent}"BkdrRegPathRtlShadow"); + default_map.add_submap(.child_map(${if_inst}.default_map), + .offset(base_addr + ${base_addr_txt})); +% endfor +% endfor +% endfor +${make_ral_pkg_window_instances(top.regwidth, 'chip', top.window_block)} + + endfunction : build + endclass : chip_reg_block + +endpackage diff --git a/hw/vendored_ips/gpio/util/reggen/topgen/validate.py b/hw/vendored_ips/gpio/util/reggen/topgen/validate.py new file mode 100644 index 00000000..bfb42987 --- /dev/null +++ b/hw/vendored_ips/gpio/util/reggen/topgen/validate.py @@ -0,0 +1,878 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +import re +import logging as log +from collections import OrderedDict +from enum import Enum +from typing import Dict, List + +from reggen.validate import check_keys +from reggen.ip_block import IpBlock + +# For the reference +# val_types = { +# 'd': ["int", "integer (binary 0b, octal 0o, decimal, hex 0x)"], +# 'x': ["xint", "x for undefined otherwise int"], +# 'b': [ +# "bitrange", "bit number as decimal integer, \ +# or bit-range as decimal integers msb:lsb" +# ], +# 'l': ["list", "comma separated list enclosed in `[]`"], +# 'ln': ["name list", 'comma separated list enclosed in `[]` of '\ +# 'one or more groups that have just name and dscr keys.'\ +# ' e.g. `{ name: "name", desc: "description"}`'], +# 'lnw': ["name list+", 'name list that optionally contains a width'], +# 'lp': ["parameter list", 'parameter list having default value optionally'], +# 'g': ["group", "comma separated group of key:value enclosed in `{}`"], +# 's': ["string", "string, typically short"], +# 't': ["text", "string, may be multi-line enclosed in `'''` "\ +# "may use `**bold**`, `*italic*` or `!!Reg` markup"], +# 'T': ["tuple", "tuple enclosed in ()"], +# 'pi': ["python int", "Native Python type int (generated)"], +# 'pb': ["python Bool", "Native Python type Bool (generated)"], +# 'pl': ["python list", "Native Python type list (generated)"], +# 'pe': ["python enum", "Native Python type enum (generated)"] +# } + +# Required/optional field in top hjson +top_required = { + 'name': ['s', 'Top name'], + 'type': ['s', 'type of hjson. Shall be "top" always'], + 'clocks': ['g', 'group of clock properties'], + 'resets': ['l', 'list of resets'], + 'module': ['l', 'list of modules to instantiate'], + 'memory': ['l', 'list of memories. At least one memory ' + 'is needed to run the software'], + 'debug_mem_base_addr': ['d', 'Base address of RV_DM. ' + 'Planned to move to module'], + 'xbar': ['l', 'List of the xbar used in the top'], + 'rnd_cnst_seed': ['int', "Seed for random netlist constant computation"], + 'pinout': ['g', 'Pinout configuration'], + 'targets': ['l', ' Target configurations'], + 'pinmux': ['g', 'pinmux configuration'], +} + +top_optional = { + 'alert_async': ['l', 'async alerts (generated)'], + 'alert': ['lnw', 'alerts (generated)'], + 'alert_module': [ + 'l', + 'list of the modules that connects to alert_handler' + ], + 'datawidth': ['pn', "default data width"], + 'exported_clks': ['g', 'clock signal routing rules'], + 'host': ['g', 'list of host-only components in the system'], + 'inter_module': ['g', 'define the signal connections between the modules'], + 'interrupt': ['lnw', 'interrupts (generated)'], + 'interrupt_module': ['l', 'list of the modules that connects to rv_plic'], + 'num_cores': ['pn', "number of computing units"], + 'power': ['g', 'power domains supported by the design'], + 'port': ['g', 'assign special attributes to specific ports'] +} + +top_added = {} + +pinmux_required = {} +pinmux_optional = { + 'num_wkup_detect': [ + 'd', 'Number of wakeup detectors' + ], + 'wkup_cnt_width': [ + 'd', 'Number of bits in wakeup detector counters' + ], + 'signals': ['l', 'List of Dedicated IOs.'], +} +pinmux_added = { + 'ios': ['l', 'Full list of IO'], +} + +pinmux_sig_required = { + 'instance': ['s', 'Module instance name'], + 'connection': ['s', 'Specification of connection type, ' + 'can be direct, manual or muxed'], +} +pinmux_sig_optional = { + 'port': ['s', 'Port name of module'], + 'pad': ['s', 'Pad name for direct connections'], + 'desc': ['s', 'Signal description'], + 'attr': ['s', 'Pad type for generating the correct attribute CSR'] +} +pinmux_sig_added = {} + +pinout_required = { + 'banks': ['l', 'List of IO power banks'], + 'pads': ['l', 'List of pads'] +} +pinout_optional = { +} +pinout_added = {} + +pad_required = { + 'name': ['l', 'Pad name'], + 'type': ['s', 'Pad type'], + 'bank': ['s', 'IO power bank for the pad'], + 'connection': ['s', 'Specification of connection type, ' + 'can be direct, manual or muxed'], +} +pad_optional = { + 'desc': ['s', 'Pad description'], +} +pad_added = {} + +target_required = { + 'name': ['s', 'Name of target'], + 'pinout': ['g', 'Target-specific pinout configuration'], + 'pinmux': ['g', 'Target-specific pinmux configuration'] +} +target_optional = { +} +target_added = {} + +target_pinmux_required = { + 'special_signals': ['l', 'List of special signals and the pad they are mapped to.'], +} +target_pinmux_optional = {} +target_pinmux_added = {} + +target_pinout_required = { + 'remove_pads': ['l', 'List of pad names to remove and stub out'], + 'add_pads': ['l', 'List of manual pads to add'], +} +target_pinout_optional = {} +target_pinout_added = {} + +straps_required = { + 'tap0': ['s', 'Name of tap0 pad'], + 'tap1': ['s', 'Name of tap1 pad'], + 'dft0': ['s', 'Name of dft0 pad'], + 'dft1': ['s', 'Name of dft1 pad'], +} +straps_optional = {} +straps_added = {} + +straps_required = { + 'tap0': ['s', 'Name of tap0 pad'], + 'tap1': ['s', 'Name of tap1 pad'], + 'dft0': ['s', 'Name of dft0 pad'], + 'dft1': ['s', 'Name of dft1 pad'], +} +straps_optional = {} +straps_added = {} + +special_sig_required = { + 'name': ['s', 'DIO name'], + 'pad': ['s', 'Pad name'], +} +special_sig_optional = { + 'desc': ['s', 'Description of signal connection'], +} +special_sig_added = {} + +clock_srcs_required = { + 'name': ['s', 'name of clock group'], + 'aon': ['s', 'yes, no. aon attribute of a clock'], + 'freq': ['s', 'frequency of clock in Hz'], +} + +clock_srcs_optional = { + 'derived': ['s', 'whether clock is derived'], + 'params': ['s', 'extra clock parameters'] +} + +derived_clock_srcs_required = { + 'name': ['s', 'name of clock group'], + 'aon': ['s', 'yes, no. aon attribute of a clock'], + 'freq': ['s', 'frequency of clock in Hz'], + 'src': ['s', 'source clock'], + 'div': ['d', 'ratio between source clock and derived clock'], +} + +clock_groups_required = { + 'name': ['s', 'name of clock group'], + 'src': ['s', 'yes, no. This clock group is directly from source'], + 'sw_cg': ['s', 'yes, no, hint. Software clock gate attributes'], +} +clock_groups_optional = { + 'unique': ['s', 'whether clocks in the group are unique'], + 'clocks': ['g', 'groups of clock name to source'], +} +clock_groups_added = {} + +eflash_required = { + 'banks': ['d', 'number of flash banks'], + 'base_addr': ['s', 'strarting hex address of memory'], + 'clock_connections': ['g', 'generated, elaborated version of clock_srcs'], + 'clock_group': ['s', 'associated clock attribute group'], + 'clock_srcs': ['g', 'clock connections'], + 'inter_signal_list': ['lg', 'intersignal list'], + 'name': ['s', 'name of flash memory'], + 'pages_per_bank': ['d', 'number of data pages per flash bank'], + 'program_resolution': ['d', 'maximum number of flash words allowed to program'], + 'reset_connections': ['g', 'reset connections'], + 'swaccess': ['s', 'software accessibility'], + 'type': ['s', 'type of memory'] +} + +eflash_optional = {} + +eflash_added = {} + + +# Supported PAD types. +# Needs to coincide with enum definition in prim_pad_wrapper_pkg.sv +class PadType(Enum): + INPUT_STD = 'InputStd' + BIDIR_STD = 'BidirStd' + BIDIR_TOL = 'BidirTol' + BIDIR_OD = 'BidirOd' + ANALOG_IN0 = 'AnalogIn0' + + +def is_valid_pad_type(obj): + try: + PadType(obj) + except ValueError: + return False + return True + + +class TargetType(Enum): + MODULE = "module" + XBAR = "xbar" + + +class Target: + """Target class informs the checkers if we are validating a module or xbar + """ + def __init__(self, target_type): + # The type of this target + self.target_type = target_type + # The key to search against + if target_type == TargetType.MODULE: + self.key = "type" + else: + self.key = "name" + + +class Flash: + """Flash class contains information regarding parameter defaults. + For now, only expose banks / pages_per_bank for user configuration. + For now, also enforce power of 2 requiremnt. + """ + max_banks = 4 + max_pages_per_bank = 1024 + + def __init__(self, mem): + self.banks = mem['banks'] + self.pages_per_bank = mem['pages_per_bank'] + self.program_resolution = mem['program_resolution'] + self.words_per_page = 256 + self.data_width = 64 + self.metadata_width = 12 + self.info_types = 3 + self.infos_per_bank = [10, 1, 2] + + def is_pow2(self, n): + return (n != 0) and (n & (n - 1) == 0) + + def check_values(self): + pow2_check = (self.is_pow2(self.banks) and + self.is_pow2(self.pages_per_bank) and + self.is_pow2(self.program_resolution)) + limit_check = ((self.banks <= Flash.max_banks) and + (self.pages_per_bank <= Flash.max_pages_per_bank)) + + return pow2_check and limit_check + + def calc_size(self): + word_bytes = self.data_width / 8 + bytes_per_page = word_bytes * self.words_per_page + bytes_per_bank = bytes_per_page * self.pages_per_bank + return bytes_per_bank * self.banks + + def populate(self, mem): + mem['words_per_page'] = self.words_per_page + mem['data_width'] = self.data_width + mem['metadata_width'] = self.metadata_width + mem['info_types'] = self.info_types + mem['infos_per_bank'] = self.infos_per_bank + mem['size'] = hex(int(self.calc_size())) + + word_bytes = self.data_width / 8 + mem['pgm_resolution_bytes'] = int(self.program_resolution * word_bytes) + + +# Check to see if each module/xbar defined in top.hjson exists as ip/xbar.hjson +# Also check to make sure there are not multiple definitions of ip/xbar.hjson for each +# top level definition +# If it does, return a dictionary of instance names to index in ip/xbarobjs +def check_target(top, objs, tgtobj): + error = 0 + idxs = OrderedDict() + + # Collect up counts of object names. We support entries of objs that are + # either dicts (for top-levels) or IpBlock objects. + name_indices = {} + for idx, obj in enumerate(objs): + if isinstance(obj, IpBlock): + name = obj.name.lower() + else: + name = obj['name'].lower() + + log.info("%d Order is %s" % (idx, name)) + name_indices.setdefault(name, []).append(idx) + + tgt_type = tgtobj.target_type.value + inst_key = tgtobj.key + + for cfg in top[tgt_type]: + cfg_name = cfg['name'].lower() + log.info("Checking target %s %s" % (tgt_type, cfg_name)) + + indices = name_indices.get(cfg[inst_key], []) + if not indices: + log.error("Could not find %s.hjson" % cfg_name) + error += 1 + elif len(indices) > 1: + log.error("Duplicate %s.hjson" % cfg_name) + error += 1 + else: + idxs[cfg_name] = indices[0] + + log.info("Current state %s" % idxs) + return error, idxs + + +def check_pad(top: Dict, + pad: Dict, + known_pad_names: Dict, + valid_connections: List[str], + prefix: str) -> int: + error = 0 + error += check_keys(pad, pad_required, pad_optional, + pad_added, prefix) + + # check name uniqueness + if pad['name'] in known_pad_names: + log.warning('Pad name {} is not unique'.format(pad['name'])) + error += 1 + known_pad_names[pad['name']] = 1 + + if not is_valid_pad_type(pad['type']): + log.warning('Unkown pad type {}'.format(pad['type'])) + error += 1 + + if pad['bank'] not in top['pinout']['banks']: + log.warning('Unkown io power bank {}'.format(pad['bank'])) + error += 1 + + if pad['connection'] not in valid_connections: + log.warning('Connection type {} of pad {} is invalid' + .format(pad['connection'], pad['name'])) + error += 1 + + return error + + +def check_pinout(top: Dict, prefix: str) -> int: + error = check_keys(top['pinout'], pinout_required, pinout_optional, + pinout_added, prefix + ' Pinout') + + known_names = {} + for pad in top['pinout']['pads']: + error += check_keys(pad, pad_required, pad_optional, + pad_added, prefix + ' Pinout') + + error += check_pad(top, pad, known_names, + ['direct', 'manual', 'muxed'], + prefix + ' Pad') + + return error + + +def check_pinmux(top: Dict, prefix: str) -> int: + error = check_keys(top['pinmux'], pinmux_required, pinmux_optional, + pinmux_added, prefix + ' Pinmux') + + # This is used for the direct connection accounting below, + # where we tick off already connected direct pads. + known_direct_pads = {} + direct_pad_attr = {} + for pad in top['pinout']['pads']: + if pad['connection'] == 'direct': + known_direct_pads[pad['name']] = 1 + direct_pad_attr[pad['name']] = pad['type'] + + # Note: the actual signal crosscheck is deferred until the merge stage, + # since we have no idea at this point which IOs comportable IPs expose. + for sig in top['pinmux']['signals']: + error += check_keys(sig, pinmux_sig_required, pinmux_sig_optional, + pinmux_sig_added, prefix + ' Pinmux signal') + + if sig['connection'] not in ['direct', 'manual', 'muxed']: + log.warning('Invalid connection type {}'.format(sig['connection'])) + error += 1 + + # The pad needs to refer to a valid pad name in the pinout that is of + # connection type "direct". We tick off all direct pads that have been + # referenced in order to make sure there are no double connections + # and unconnected direct pads. + padname = sig.setdefault('pad', '') + if padname != '': + if padname in known_direct_pads: + if known_direct_pads[padname] == 1: + known_direct_pads[padname] = 0 + padattr = direct_pad_attr[padname] + else: + log.warning('Warning, direct pad {} is already connected' + .format(padname)) + error += 1 + else: + log.warning('Unknown direct pad {}'.format(padname)) + error += 1 + + # Check port naming scheme. + port = sig.setdefault('port', '') + pattern = r'^[a-zA-Z0-9_]*(\[[0-9]*\]){0,1}' + matches = re.match(pattern, port) + if matches is None: + log.warning('Port name {} has wrong format' + .format(port)) + error += 1 + + # Check that only direct connections have pad keys + if sig['connection'] == 'direct': + if sig.setdefault('attr', '') != '': + log.warning('Direct connection of instance {} port {} ' + 'must not have an associated pad attribute field' + .format(sig['instance'], + sig['port'])) + error += 1 + # Since the signal is directly connected, we can automatically infer + # the pad type needed to instantiate the correct attribute CSR WARL + # module inside the pinmux. + sig['attr'] = padattr + + if padname == '': + log.warning('Instance {} port {} connection is of direct type ' + 'and therefore must have an associated pad name.' + .format(sig['instance'], + sig['port'])) + error += 1 + if port == '': + log.warning('Instance {} port {} connection is of direct type ' + 'and therefore must have an associated port name.' + .format(sig['instance'], + sig['port'])) + error += 1 + elif sig['connection'] == 'muxed': + # Muxed signals do not have a corresponding pad and attribute CSR, + # since they first go through the pinmux matrix. + if sig.setdefault('attr', '') != '': + log.warning('Muxed connection of instance {} port {} ' + 'must not have an associated pad attribute field' + .format(sig['instance'], + sig['port'])) + error += 1 + if padname != '': + log.warning('Muxed connection of instance {} port {} ' + 'must not have an associated pad' + .format(sig['instance'], + sig['port'])) + error += 1 + elif sig['connection'] == 'manual': + # This pad attr key is only allowed in the manual case, + # as there is no way to infer the pad type automatically. + sig.setdefault('attr', 'BidirStd') + if padname != '': + log.warning('Manual connection of instance {} port {} ' + 'must not have an associated pad' + .format(sig['instance'], + sig['port'])) + error += 1 + + # At this point, all direct pads should have been ticked off. + for key, val in known_direct_pads.items(): + if val == 1: + log.warning('Direct pad {} has not been connected' + .format(key)) + error += 1 + + return error + + +def check_implementation_targets(top: Dict, prefix: str) -> int: + error = 0 + known_names = {} + for target in top['targets']: + error += check_keys(target, target_required, target_optional, + target_added, prefix + ' Targets') + + # check name uniqueness + if target['name'] in known_names: + log.warning('Target name {} is not unique'.format(target['name'])) + error += 1 + known_names[target['name']] = 1 + + error += check_keys(target['pinmux'], target_pinmux_required, target_pinmux_optional, + target_pinmux_added, prefix + ' Target pinmux') + + error += check_keys(target['pinout'], target_pinout_required, target_pinout_optional, + target_pinout_added, prefix + ' Target pinout') + + # Check special pad signals + known_entry_names = {} + for entry in target['pinmux']['special_signals']: + error += check_keys(entry, special_sig_required, special_sig_optional, + special_sig_added, prefix + ' Special signal') + + # check name uniqueness + if entry['name'] in known_entry_names: + log.warning('Special pad name {} is not unique'.format(entry['name'])) + error += 1 + known_entry_names[entry['name']] = 1 + + # The pad key needs to refer to a valid pad name. + is_muxed = False + for pad in top['pinout']['pads']: + if entry['pad'] == pad['name']: + is_muxed = pad['connection'] == 'muxed' + break + else: + log.warning('Unknown pad {}'.format(entry['pad'])) + error += 1 + + if not is_muxed: + # If this is not a muxed pad, we need to make sure this refers to + # DIO that is NOT a manual pad. + for sig in top['pinmux']['signals']: + if entry['pad'] == sig['pad']: + break + else: + log.warning('Special pad {} cannot refer to a manual pad'.format(entry['pad'])) + error += 1 + + # Check pads to remove and stub out + for entry in target['pinout']['remove_pads']: + # The pad key needs to refer to a valid pad name. + for pad in top['pinout']['pads']: + if entry == pad['name']: + break + else: + log.warning('Unknown pad {}'.format(entry)) + error += 1 + + # Check pads to add + known_pad_names = {} + for pad in top['pinout']['pads']: + known_pad_names.update({pad['name']: 1}) + + for pad in target['pinout']['add_pads']: + error += check_pad(top, pad, known_pad_names, ['manual'], + prefix + ' Additional Pad') + + return error + + +# check for inconsistent clock group definitions +def check_clock_groups(top): + + # default empty assignment + if "groups" not in top['clocks']: + top['clocks']['groups'] = [] + + error = 0 + for group in top['clocks']['groups']: + error = check_keys(group, clock_groups_required, clock_groups_optional, + clock_groups_added, "Clock Groups") + + # Check sw_cg values are valid + if group['sw_cg'] not in ['yes', 'no', 'hint']: + log.error("Incorrect attribute for sw_cg: {}".format( + group['sw_cg'])) + error += 1 + + # Check combination of src and sw are valid + if group['src'] == 'yes' and group['sw_cg'] != 'no': + log.error("Invalid combination of src and sw_cg: {} and {}".format( + group['src'], group['sw_cg'])) + error += 1 + + # Check combination of sw_cg and unique are valid + unique = group['unique'] if 'unique' in group else 'no' + if group['sw_cg'] == 'no' and unique != 'no': + log.error( + "Incorrect attribute combination. When sw_cg is no, unique must be no" + ) + error += 1 + + if error: + break + + return error + + +def check_clocks_resets(top, ipobjs, ip_idxs, xbarobjs, xbar_idxs): + + error = 0 + + # there should only be one each of pwrmgr/clkmgr/rstmgr + pwrmgrs = [m for m in top['module'] if m['type'] == 'pwrmgr'] + clkmgrs = [m for m in top['module'] if m['type'] == 'clkmgr'] + rstmgrs = [m for m in top['module'] if m['type'] == 'rstmgr'] + + if len(pwrmgrs) == 1 * len(clkmgrs) == 1 * len(rstmgrs) != 1: + log.error("Incorrect number of pwrmgr/clkmgr/rstmgr") + error += 1 + + # check clock fields are all there + ext_srcs = [] + for src in top['clocks']['srcs']: + check_keys(src, clock_srcs_required, clock_srcs_optional, {}, + "Clock source") + ext_srcs.append(src['name']) + + # check derived clock sources + log.info("Collected clocks are {}".format(ext_srcs)) + for src in top['clocks']['derived_srcs']: + check_keys(src, derived_clock_srcs_required, {}, {}, "Derived clocks") + try: + ext_srcs.index(src['src']) + except Exception: + error += 1 + log.error("{} is not a valid src for {}".format( + src['src'], src['name'])) + + # all defined clock/reset nets + reset_nets = [reset['name'] for reset in top['resets']['nodes']] + clock_srcs = [ + clock['name'] + for clock in top['clocks']['srcs'] + top['clocks']['derived_srcs'] + ] + + # Check clock/reset port connection for all IPs + for ipcfg in top['module']: + ipcfg_name = ipcfg['name'].lower() + log.info("Checking clock/resets for %s" % ipcfg_name) + error += validate_reset(ipcfg, ipobjs[ip_idxs[ipcfg_name]], reset_nets) + error += validate_clock(ipcfg, ipobjs[ip_idxs[ipcfg_name]], clock_srcs) + + if error: + log.error("module clock/reset checking failed") + break + + # Check clock/reset port connection for all xbars + for xbarcfg in top['xbar']: + xbarcfg_name = xbarcfg['name'].lower() + log.info("Checking clock/resets for xbar %s" % xbarcfg_name) + error += validate_reset(xbarcfg, xbarobjs[xbar_idxs[xbarcfg_name]], + reset_nets, "xbar") + error += validate_clock(xbarcfg, xbarobjs[xbar_idxs[xbarcfg_name]], + clock_srcs, "xbar") + + if error: + log.error("xbar clock/reset checking failed") + break + + return error + + +# Checks the following +# For each defined reset connection in top*.hjson, there exists a defined port at the destination +# and defined reset net +# There are the same number of defined connections as there are ports +def validate_reset(top, inst, reset_nets, prefix=""): + # Gather inst port list + error = 0 + + # Handle either an IpBlock (generated by reggen) or an OrderedDict + # (generated by topgen for a crossbar) + if isinstance(inst, IpBlock): + name = inst.name + reset_signals = inst.reset_signals + else: + name = inst['name'] + reset_signals = ([inst.get('reset_primary', 'rst_ni')] + + inst.get('other_reset_list', [])) + + log.info("%s %s resets are %s" % + (prefix, name, reset_signals)) + + if len(top['reset_connections']) != len(reset_signals): + error += 1 + log.error("%s %s mismatched number of reset ports and nets" % + (prefix, name)) + + missing_port = [ + port for port in top['reset_connections'].keys() + if port not in reset_signals + ] + + if missing_port: + error += 1 + log.error("%s %s Following reset ports do not exist:" % + (prefix, name)) + [log.error("%s" % port) for port in missing_port] + + missing_net = [ + net for port, net in top['reset_connections'].items() + if net not in reset_nets + ] + + if missing_net: + error += 1 + log.error("%s %s Following reset nets do not exist:" % + (prefix, name)) + [log.error("%s" % net) for net in missing_net] + + return error + + +# Checks the following +# For each defined clock_src in top*.hjson, there exists a defined port at the destination +# and defined clock source +# There are the same number of defined connections as there are ports +def validate_clock(top, inst, clock_srcs, prefix=""): + # Gather inst port list + error = 0 + + # Handle either an IpBlock (generated by reggen) or an OrderedDict + # (generated by topgen for a crossbar) + if isinstance(inst, IpBlock): + name = inst.name + clock_signals = inst.clock_signals + else: + name = inst['name'] + clock_signals = ([inst.get('clock_primary', 'rst_ni')] + + inst.get('other_clock_list', [])) + + if len(top['clock_srcs']) != len(clock_signals): + error += 1 + log.error("%s %s mismatched number of clock ports and nets" % + (prefix, name)) + + missing_port = [ + port for port in top['clock_srcs'].keys() + if port not in clock_signals + ] + + if missing_port: + error += 1 + log.error("%s %s Following clock ports do not exist:" % + (prefix, name)) + [log.error("%s" % port) for port in missing_port] + + missing_net = [ + net for port, net in top['clock_srcs'].items() if net not in clock_srcs + ] + + if missing_net: + error += 1 + log.error("%s %s Following clock nets do not exist:" % + (prefix, name)) + [log.error("%s" % net) for net in missing_net] + + return error + + +def check_flash(top): + error = 0 + + for mem in top['memory']: + if mem['type'] == "eflash": + error = check_keys(mem, eflash_required, eflash_optional, + eflash_added, "Eflash") + + flash = Flash(mem) + error += 1 if not flash.check_values() else 0 + + if error: + log.error("Flash check failed") + else: + flash.populate(mem) + + return error + + +def check_power_domains(top): + error = 0 + + # check that the default domain is valid + if top['power']['default'] not in top['power']['domains']: + error += 1 + return error + + # check that power domain definition is consistent with reset and module definition + for reset in top['resets']['nodes']: + if reset['gen']: + if 'domains' not in reset: + log.error("{} missing domain definition".format(reset['name'])) + error += 1 + return error + else: + for domain in reset['domains']: + if domain not in top['power']['domains']: + log.error("{} defined invalid domain {}".format( + reset['name'], domain)) + error += 1 + return error + + # Check that each module, xbar, memory has a power domain defined. + # If not, give it a default. + # If there is one defined, check that it is a valid definition + for end_point in top['module'] + top['memory'] + top['xbar']: + if 'domain' not in end_point: + end_point['domain'] = top['power']['default'] + + if end_point['domain'] not in top['power']['domains']: + log.error("{} defined invalid domain {}" + .format(end_point['name'], + end_point['domain'])) + error += 1 + return error + + # arrived without incident, return + return error + + +def validate_top(top, ipobjs, xbarobjs): + # return as it is for now + error = check_keys(top, top_required, top_optional, top_added, "top") + + if error != 0: + log.error("Top HJSON has top level errors. Aborting") + return top, error + + component = top['name'] + + # MODULE check + err, ip_idxs = check_target(top, ipobjs, Target(TargetType.MODULE)) + error += err + + # XBAR check + err, xbar_idxs = check_target(top, xbarobjs, Target(TargetType.XBAR)) + error += err + + # MEMORY check + error += check_flash(top) + + # Power domain check + error += check_power_domains(top) + + # Clock / Reset check + error += check_clocks_resets(top, ipobjs, ip_idxs, xbarobjs, xbar_idxs) + + # Clock group check + error += check_clock_groups(top) + + # RV_PLIC check + + # Pinout, pinmux and target checks + # Note that these checks must happen in this order, as + # the pinmux and target configs depend on the pinout. + error += check_pinout(top, component) + error += check_pinmux(top, component) + error += check_implementation_targets(top, component) + + return top, error diff --git a/hw/vendored_ips/patches/gpio/0001-Update-AXI.patch b/hw/vendored_ips/patches/gpio/0001-Update-AXI.patch new file mode 100644 index 00000000..e500dad4 --- /dev/null +++ b/hw/vendored_ips/patches/gpio/0001-Update-AXI.patch @@ -0,0 +1,25 @@ +From 7499f1bfc986840811802e9662faf3f4ad106a46 Mon Sep 17 00:00:00 2001 +From: Michael Rogenmoser +Date: Tue, 7 May 2024 14:24:48 +0200 +Subject: [PATCH] Update AXI + +--- + Bender.yml | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/Bender.yml b/Bender.yml +index 96ef8ce..843bd42 100644 +--- a/Bender.yml ++++ b/Bender.yml +@@ -9,7 +9,7 @@ dependencies: + common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0} + register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.1} + apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } # To be udpated once PR #6 got merged. +- axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.38.0 } ++ axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.2 } + + sources: + - src/gpio_reg_pkg.sv +-- +2.39.3 + diff --git a/rtl/includes/soc_mem_map.svh b/rtl/includes/soc_mem_map.svh deleted file mode 100644 index 21bb29e1..00000000 --- a/rtl/includes/soc_mem_map.svh +++ /dev/null @@ -1,40 +0,0 @@ -//----------------------------------------------------------------------------- -// Title : SoC Memory Region Definitions -//----------------------------------------------------------------------------- -// File : soc_mem_map.svh -// Author : Manuel Eggimann -// Created : 30.10.2020 -//----------------------------------------------------------------------------- -// Description : -// This file contains start and end address definitions for the soc_interconnect. -//----------------------------------------------------------------------------- -// Copyright (C) 2013-2020 ETH Zurich, University of Bologna -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. -//----------------------------------------------------------------------------- - -`define SOC_MEM_MAP_TCDM_START_ADDR 32'h1C01_0000 -`define SOC_MEM_MAP_TCDM_END_ADDR 32'h1C09_0000 - -`define SOC_MEM_MAP_PRIVATE_BANK0_START_ADDR 32'h1C00_0000 -`define SOC_MEM_MAP_PRIVATE_BANK0_END_ADDR 32'h1C00_8000 - -`define SOC_MEM_MAP_PRIVATE_BANK1_START_ADDR 32'h1C00_8000 -`define SOC_MEM_MAP_PRIVATE_BANK1_END_ADDR 32'h1C01_0000 - -`define SOC_MEM_MAP_BOOT_ROM_START_ADDR 32'h1A00_0000 -`define SOC_MEM_MAP_BOOT_ROM_END_ADDR 32'h1A04_0000 - -`define SOC_MEM_MAP_AXI_PLUG_START_ADDR 32'h1000_0000 -`define SOC_MEM_MAP_AXI_PLUG_END_ADDR 32'h1040_0000 - -`define SOC_MEM_MAP_PERIPHERALS_START_ADDR 32'h1A10_0000 -`define SOC_MEM_MAP_PERIPHERALS_END_ADDR 32'h1A40_0000 - - diff --git a/rtl/pulpissimo/jtag_tap_top.sv b/rtl/pulpissimo/jtag_tap_top.sv deleted file mode 100644 index 52a8c5c8..00000000 --- a/rtl/pulpissimo/jtag_tap_top.sv +++ /dev/null @@ -1,119 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - - -module jtag_tap_top #( - parameter logic [31:0] IDCODE_VALUE = 32'h10000db3 -)( - input logic tck_i, - input logic trst_ni, - input logic tms_i, - input logic td_i, - output logic td_o, - - input logic test_clk_i, - input logic test_rstn_i, - - input logic [7:0] soc_jtag_reg_i, - output logic [7:0] soc_jtag_reg_o, - output logic sel_fll_clk_o, - - // tap - output logic jtag_shift_dr_o, - output logic jtag_update_dr_o, - output logic jtag_capture_dr_o, - output logic axireg_sel_o, - - output logic dbg_axi_scan_in_o, - input logic dbg_axi_scan_out_i -); - - logic s_scan_i; - logic [8:0] s_confreg; - logic confscan; - logic confreg_sel; - logic td_o_int; - - logic [7:0] r_soc_reg0; - logic [7:0] r_soc_reg1; - - logic [7:0] s_soc_jtag_reg_sync; - - - - // jtag tap controller - tap_top #( - .IDCODE_VALUE ( IDCODE_VALUE ) - ) tap_top_i ( - .tms_i ( tms_i ), - .tck_i ( tck_i ), - .rst_ni ( trst_ni ), - .td_i ( td_i ), - .td_o ( td_o ), - - .shift_dr_o ( jtag_shift_dr_o ), - .update_dr_o ( jtag_update_dr_o ), - .capture_dr_o ( jtag_capture_dr_o ), - - .memory_sel_o ( axireg_sel_o ), - .fifo_sel_o ( ), - .confreg_sel_o ( confreg_sel ), - .observ_sel_o ( ), - .clk_byp_sel_o ( ), - - .scan_in_o ( s_scan_i ), - - .observ_out_i ( 1'b0 ), - .clk_byp_out_i ( 1'b0 ), - .memory_out_i ( dbg_axi_scan_out_i ), - .fifo_out_i ( 1'b0 ), - .confreg_out_i ( confscan ) - ); - - // pulp configuration register - jtagreg - #( - .JTAGREGSIZE(9), - .SYNC(0) - ) - confreg - ( - .clk_i ( tck_i ), - .rst_ni ( trst_ni ), - .enable_i ( confreg_sel ), - .capture_dr_i ( jtag_capture_dr_o ), - .shift_dr_i ( jtag_shift_dr_o ), - .update_dr_i ( jtag_update_dr_o ), - .jtagreg_in_i ( {1'b0, s_soc_jtag_reg_sync} ), //at sys rst enable the fll - .mode_i ( 1'b1 ), - .scan_in_i ( s_scan_i ), - .jtagreg_out_o ( s_confreg ), - .scan_out_o ( confscan ) - ); - - always_ff @(posedge tck_i or negedge trst_ni) begin - if(~trst_ni) begin - r_soc_reg0 <= 0; - r_soc_reg1 <= 0; - end else begin - r_soc_reg1 <= soc_jtag_reg_i; - r_soc_reg0 <= r_soc_reg1; - end - end - - assign s_soc_jtag_reg_sync =r_soc_reg0; - - assign dbg_axi_scan_in_o = s_scan_i; - - assign soc_jtag_reg_o = s_confreg[7:0]; - - assign sel_fll_clk_o = s_confreg[8]; - -endmodule diff --git a/rtl/pulpissimo/pad_control.sv b/rtl/pulpissimo/pad_control.sv deleted file mode 100644 index 60034d1b..00000000 --- a/rtl/pulpissimo/pad_control.sv +++ /dev/null @@ -1,403 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -`define SPI_STD_TX 2'b00 -`define SPI_STD_RX 2'b01 -`define SPI_QUAD_TX 2'b10 -`define SPI_QUAD_RX 2'b11 - -module pad_control #( - parameter int unsigned N_UART = 1, - parameter int unsigned N_SPI = 1, - parameter int unsigned N_I2C = 2 -) ( - - //********************************************************************// - //*** PERIPHERALS SIGNALS ********************************************// - //********************************************************************// - - // PAD CONTROL REGISTER - input logic [63:0][1:0] pad_mux_i , - input logic [63:0][5:0] pad_cfg_i , - output logic [47:0][5:0] pad_cfg_o , - - input logic sdio_clk_i, - input logic sdio_cmd_i, - output logic sdio_cmd_o, - input logic sdio_cmd_oen_i, - input logic [3:0] sdio_data_i, - output logic [3:0] sdio_data_o, - input logic [3:0] sdio_data_oen_i, - - // GPIOS - input logic [31:0] gpio_out_i , - output logic [31:0] gpio_in_o , - input logic [31:0] gpio_dir_i , - input logic [31:0][5:0] gpio_cfg_i , - - // UART - input logic uart_tx_i , - output logic uart_rx_o , - - // I2C - input logic [N_I2C-1:0] i2c_scl_out_i, - output logic [N_I2C-1:0] i2c_scl_in_o, - input logic [N_I2C-1:0] i2c_scl_oe_i, - input logic [N_I2C-1:0] i2c_sda_out_i, - output logic [N_I2C-1:0] i2c_sda_in_o, - input logic [N_I2C-1:0] i2c_sda_oe_i, - - // I2S - output logic i2s_slave_sd0_o , - output logic i2s_slave_sd1_o , - output logic i2s_slave_ws_o , - input logic i2s_slave_ws_i , - input logic i2s_slave_ws_oe , - output logic i2s_slave_sck_o , - input logic i2s_slave_sck_i , - input logic i2s_slave_sck_oe , - - // SPI MASTER - input logic [N_SPI-1:0] spi_clk_i, - input logic [N_SPI-1:0][3:0] spi_csn_i, - input logic [N_SPI-1:0][3:0] spi_oen_i, - input logic [N_SPI-1:0][3:0] spi_sdo_i, - output logic [N_SPI-1:0][3:0] spi_sdi_o, - - // CAMERA INTERFACE - output logic cam_pclk_o , - output logic [7:0] cam_data_o , - output logic cam_hsync_o , - output logic cam_vsync_o , - - // TIMER - input logic [3:0] timer0_i , - input logic [3:0] timer1_i , - input logic [3:0] timer2_i , - input logic [3:0] timer3_i , - - //********************************************************************// - //*** PAD FRAME SIGNALS **********************************************// - //********************************************************************// - - // PADS OUTPUTS - output logic out_spim_sdio0_o , - output logic out_spim_sdio1_o , - output logic out_spim_sdio2_o , - output logic out_spim_sdio3_o , - output logic out_spim_csn0_o , - output logic out_spim_csn1_o , - output logic out_spim_sck_o , - output logic out_sdio_clk_o , - output logic out_sdio_cmd_o , - output logic out_sdio_data0_o , - output logic out_sdio_data1_o , - output logic out_sdio_data2_o , - output logic out_sdio_data3_o , - output logic out_uart_rx_o , - output logic out_uart_tx_o , - output logic out_cam_pclk_o , - output logic out_cam_hsync_o , - output logic out_cam_data0_o , - output logic out_cam_data1_o , - output logic out_cam_data2_o , - output logic out_cam_data3_o , - output logic out_cam_data4_o , - output logic out_cam_data5_o , - output logic out_cam_data6_o , - output logic out_cam_data7_o , - output logic out_cam_vsync_o , - output logic out_i2c0_sda_o , - output logic out_i2c0_scl_o , - output logic out_i2s0_sck_o , - output logic out_i2s0_ws_o , - output logic out_i2s0_sdi_o , - output logic out_i2s1_sdi_o , - - // PAD INPUTS - input logic in_spim_sdio0_i , - input logic in_spim_sdio1_i , - input logic in_spim_sdio2_i , - input logic in_spim_sdio3_i , - input logic in_spim_csn0_i , - input logic in_spim_csn1_i , - input logic in_spim_sck_i , - input logic in_sdio_clk_i , - input logic in_sdio_cmd_i , - input logic in_sdio_data0_i , - input logic in_sdio_data1_i , - input logic in_sdio_data2_i , - input logic in_sdio_data3_i , - input logic in_uart_rx_i , - input logic in_uart_tx_i , - input logic in_cam_pclk_i , - input logic in_cam_hsync_i , - input logic in_cam_data0_i , - input logic in_cam_data1_i , - input logic in_cam_data2_i , - input logic in_cam_data3_i , - input logic in_cam_data4_i , - input logic in_cam_data5_i , - input logic in_cam_data6_i , - input logic in_cam_data7_i , - input logic in_cam_vsync_i , - input logic in_i2c0_sda_i , - input logic in_i2c0_scl_i , - input logic in_i2s0_sck_i , - input logic in_i2s0_ws_i , - input logic in_i2s0_sdi_i , - input logic in_i2s1_sdi_i , - - // OUTPUT ENABLE - output logic oe_spim_sdio0_o , - output logic oe_spim_sdio1_o , - output logic oe_spim_sdio2_o , - output logic oe_spim_sdio3_o , - output logic oe_spim_csn0_o , - output logic oe_spim_csn1_o , - output logic oe_spim_sck_o , - output logic oe_sdio_clk_o , - output logic oe_sdio_cmd_o , - output logic oe_sdio_data0_o , - output logic oe_sdio_data1_o , - output logic oe_sdio_data2_o , - output logic oe_sdio_data3_o , - output logic oe_uart_rx_o , - output logic oe_uart_tx_o , - output logic oe_cam_pclk_o , - output logic oe_cam_hsync_o , - output logic oe_cam_data0_o , - output logic oe_cam_data1_o , - output logic oe_cam_data2_o , - output logic oe_cam_data3_o , - output logic oe_cam_data4_o , - output logic oe_cam_data5_o , - output logic oe_cam_data6_o , - output logic oe_cam_data7_o , - output logic oe_cam_vsync_o , - output logic oe_i2c0_sda_o , - output logic oe_i2c0_scl_o , - output logic oe_i2s0_sck_o , - output logic oe_i2s0_ws_o , - output logic oe_i2s0_sdi_o , - output logic oe_i2s1_sdi_o - ); - - - logic s_alt0,s_alt1,s_alt2,s_alt3; - - // check invariants - if (N_SPI < 1 || N_SPI > 2) $error("The current verion of Pad control supports only 1 or 2 SPI peripherals"); - if (N_I2C != 2) $error("The current version of Pad control only supports exactly 2 I2C peripherals"); - if (N_UART != 1) $error("The current version of Pad control only supports exactly 1 UART peripherals"); - - // DEFINE DEFAULT FOR NOT USED ALTERNATIVES - assign s_alt0 = 1'b0; - assign s_alt1 = 1'b0; - assign s_alt2 = 1'b0; - assign s_alt3 = 1'b0; - - ///////////////////////////////////////////////////////////////////////////////////////////// - // OUTPUT ENABLE - ///////////////////////////////////////////////////////////////////////////////////////////// - assign oe_spim_sdio0_o = (pad_mux_i[0 ] == 2'b00) ? ~spi_oen_i[0][0] : ((pad_mux_i[0 ] == 2'b01) ? gpio_dir_i[0 ] : ((pad_mux_i[0 ] == 2'b10) ? s_alt2 : s_alt3 )); - assign oe_spim_sdio1_o = (pad_mux_i[1 ] == 2'b00) ? ~spi_oen_i[0][1] : ((pad_mux_i[1 ] == 2'b01) ? gpio_dir_i[1 ] : ((pad_mux_i[1 ] == 2'b10) ? s_alt2 : s_alt3 )); - assign oe_spim_sdio2_o = (pad_mux_i[2 ] == 2'b00) ? ~spi_oen_i[0][2] : ((pad_mux_i[2 ] == 2'b01) ? gpio_dir_i[2 ] : ((pad_mux_i[2 ] == 2'b10) ? i2c_sda_oe_i[1] : s_alt3 )); - assign oe_spim_sdio3_o = (pad_mux_i[3 ] == 2'b00) ? ~spi_oen_i[0][3] : ((pad_mux_i[3 ] == 2'b01) ? gpio_dir_i[3 ] : ((pad_mux_i[3 ] == 2'b10) ? i2c_scl_oe_i[1] : s_alt3 )); - assign oe_spim_csn0_o = (pad_mux_i[4 ] == 2'b00) ? 1'b1 : ((pad_mux_i[4 ] == 2'b01) ? gpio_dir_i[4 ] : ((pad_mux_i[4 ] == 2'b10) ? s_alt2 : s_alt3 )); - assign oe_spim_csn1_o = (pad_mux_i[5 ] == 2'b00) ? 1'b1 : ((pad_mux_i[5 ] == 2'b01) ? gpio_dir_i[5 ] : ((pad_mux_i[5 ] == 2'b10) ? s_alt2 : s_alt3 )); - assign oe_spim_sck_o = (pad_mux_i[6 ] == 2'b00) ? 1'b1 : ((pad_mux_i[6 ] == 2'b01) ? gpio_dir_i[6 ] : ((pad_mux_i[6 ] == 2'b10) ? s_alt2 : s_alt3 )); - assign oe_uart_rx_o = (pad_mux_i[7 ] == 2'b00) ? 1'b0 : ((pad_mux_i[7 ] == 2'b01) ? gpio_dir_i[7 ] : ((pad_mux_i[7 ] == 2'b10) ? i2c_sda_oe_i[1] : s_alt3 )); - assign oe_uart_tx_o = (pad_mux_i[8 ] == 2'b00) ? 1'b1 : ((pad_mux_i[8 ] == 2'b01) ? gpio_dir_i[8 ] : ((pad_mux_i[8 ] == 2'b10) ? i2c_scl_oe_i[1] : s_alt3 )); - assign oe_cam_pclk_o = (pad_mux_i[9 ] == 2'b00) ? 1'b0 : ((pad_mux_i[9 ] == 2'b01) ? gpio_dir_i[9 ] : ((pad_mux_i[9 ] == 2'b10) ? 1'b1 : s_alt3 )); - assign oe_cam_hsync_o = (pad_mux_i[10] == 2'b00) ? 1'b0 : ((pad_mux_i[10] == 2'b01) ? gpio_dir_i[10] : ((pad_mux_i[10] == 2'b10) ? 1'b1 : s_alt3 )); - assign oe_cam_data0_o = (pad_mux_i[11] == 2'b00) ? 1'b0 : ((pad_mux_i[11] == 2'b01) ? gpio_dir_i[11] : ((pad_mux_i[11] == 2'b10) ? 1'b1 : s_alt3 )); - assign oe_cam_data1_o = (pad_mux_i[12] == 2'b00) ? 1'b0 : ((pad_mux_i[12] == 2'b01) ? gpio_dir_i[12] : ((pad_mux_i[12] == 2'b10) ? 1'b1 : s_alt3 )); - assign oe_cam_data2_o = (pad_mux_i[13] == 2'b00) ? 1'b0 : ((pad_mux_i[13] == 2'b01) ? gpio_dir_i[13] : ((pad_mux_i[13] == 2'b10) ? 1'b1 : s_alt3 )); - assign oe_cam_data3_o = (pad_mux_i[14] == 2'b00) ? 1'b0 : ((pad_mux_i[14] == 2'b01) ? gpio_dir_i[14] : ((pad_mux_i[14] == 2'b10) ? 1'b1 : s_alt3 )); - assign oe_cam_data4_o = (pad_mux_i[15] == 2'b00) ? 1'b0 : ((pad_mux_i[15] == 2'b01) ? gpio_dir_i[15] : ((pad_mux_i[15] == 2'b10) ? 1'b1 : s_alt3 )); - assign oe_cam_data5_o = (pad_mux_i[16] == 2'b00) ? 1'b0 : ((pad_mux_i[16] == 2'b01) ? gpio_dir_i[16] : ((pad_mux_i[16] == 2'b10) ? 1'b1 : s_alt3 )); - assign oe_cam_data6_o = (pad_mux_i[17] == 2'b00) ? 1'b0 : ((pad_mux_i[17] == 2'b01) ? gpio_dir_i[17] : ((pad_mux_i[17] == 2'b10) ? 1'b1 : s_alt3 )); - assign oe_cam_data7_o = (pad_mux_i[18] == 2'b00) ? 1'b0 : ((pad_mux_i[18] == 2'b01) ? gpio_dir_i[18] : ((pad_mux_i[18] == 2'b10) ? 1'b1 : s_alt3 )); - assign oe_cam_vsync_o = (pad_mux_i[19] == 2'b00) ? 1'b0 : ((pad_mux_i[19] == 2'b01) ? gpio_dir_i[19] : ((pad_mux_i[19] == 2'b10) ? 1'b1 : s_alt3 )); - assign oe_sdio_clk_o = (pad_mux_i[20] == 2'b00) ? 1'b1 : ((pad_mux_i[20] == 2'b01) ? gpio_dir_i[20] : ((pad_mux_i[20] == 2'b10) ? 1'b0 : s_alt3 )); - assign oe_sdio_cmd_o = (pad_mux_i[21] == 2'b00) ? ~sdio_cmd_oen_i : ((pad_mux_i[21] == 2'b01) ? gpio_dir_i[21] : ((pad_mux_i[21] == 2'b10) ? 1'b0 : s_alt3 )); - assign oe_sdio_data0_o = (pad_mux_i[22] == 2'b00) ? ~sdio_data_oen_i[0] : ((pad_mux_i[22] == 2'b01) ? gpio_dir_i[22] : ((pad_mux_i[22] == 2'b10) ? 1'b0 : s_alt3 )); - assign oe_sdio_data1_o = (pad_mux_i[23] == 2'b00) ? ~sdio_data_oen_i[1] : ((pad_mux_i[23] == 2'b01) ? gpio_dir_i[23] : ((pad_mux_i[23] == 2'b10) ? 1'b0 : s_alt3 )); - assign oe_sdio_data2_o = (pad_mux_i[24] == 2'b00) ? ~sdio_data_oen_i[2] : ((pad_mux_i[24] == 2'b01) ? gpio_dir_i[24] : ((pad_mux_i[24] == 2'b10) ? i2c_sda_oe_i[1] : s_alt3 )); - assign oe_sdio_data3_o = (pad_mux_i[25] == 2'b00) ? ~sdio_data_oen_i[3] : ((pad_mux_i[25] == 2'b01) ? gpio_dir_i[25] : ((pad_mux_i[25] == 2'b10) ? i2c_scl_oe_i[1] : s_alt3 )); - assign oe_i2c0_sda_o = (pad_mux_i[33] == 2'b00) ? i2c_sda_oe_i[0] : ((pad_mux_i[33] == 2'b01) ? gpio_dir_i[26] : ((pad_mux_i[33] == 2'b10) ? s_alt2 : s_alt3 )); - assign oe_i2c0_scl_o = (pad_mux_i[34] == 2'b00) ? i2c_scl_oe_i[0] : ((pad_mux_i[34] == 2'b01) ? gpio_dir_i[27] : ((pad_mux_i[34] == 2'b10) ? s_alt2 : s_alt3 )); - assign oe_i2s0_sck_o = (pad_mux_i[35] == 2'b00) ? i2s_slave_sck_oe : ((pad_mux_i[35] == 2'b01) ? gpio_dir_i[28] : ((pad_mux_i[35] == 2'b10) ? s_alt2 : s_alt3 )); - assign oe_i2s0_ws_o = (pad_mux_i[36] == 2'b00) ? i2s_slave_ws_oe : ((pad_mux_i[36] == 2'b01) ? gpio_dir_i[29] : ((pad_mux_i[36] == 2'b10) ? s_alt2 : s_alt3 )); - assign oe_i2s0_sdi_o = (pad_mux_i[37] == 2'b00) ? 1'b0 : ((pad_mux_i[37] == 2'b01) ? gpio_dir_i[30] : ((pad_mux_i[37] == 2'b10) ? s_alt2 : s_alt3 )); - assign oe_i2s1_sdi_o = (pad_mux_i[38] == 2'b00) ? 1'b0 : ((pad_mux_i[38] == 2'b01) ? gpio_dir_i[31] : ((pad_mux_i[38] == 2'b10) ? s_alt2 : s_alt3 )); - - ///////////////////////////////////////////////////////////////////////////////////////////// - // DATA OUTPUT - ///////////////////////////////////////////////////////////////////////////////////////////// - assign out_spim_sdio0_o = (pad_mux_i[0 ] == 2'b00) ? spi_sdo_i[0][0] : ((pad_mux_i[0 ] == 2'b01) ? gpio_out_i[0 ] : ((pad_mux_i[0 ] == 2'b10) ? s_alt2 : s_alt3 )); - assign out_spim_sdio1_o = (pad_mux_i[1 ] == 2'b00) ? spi_sdo_i[0][1] : ((pad_mux_i[1 ] == 2'b01) ? gpio_out_i[1 ] : ((pad_mux_i[1 ] == 2'b10) ? s_alt2 : s_alt3 )); - assign out_spim_sdio2_o = (pad_mux_i[2 ] == 2'b00) ? spi_sdo_i[0][2] : ((pad_mux_i[2 ] == 2'b01) ? gpio_out_i[2 ] : ((pad_mux_i[2 ] == 2'b10) ? i2c_sda_out_i[1] : s_alt3 )); - assign out_spim_sdio3_o = (pad_mux_i[3 ] == 2'b00) ? spi_sdo_i[0][3] : ((pad_mux_i[3 ] == 2'b01) ? gpio_out_i[3 ] : ((pad_mux_i[3 ] == 2'b10) ? i2c_scl_out_i[1] : s_alt3 )); - assign out_spim_csn0_o = (pad_mux_i[4 ] == 2'b00) ? spi_csn_i[0][0] : ((pad_mux_i[4 ] == 2'b01) ? gpio_out_i[4 ] : ((pad_mux_i[4 ] == 2'b10) ? s_alt2 : s_alt3 )); - assign out_spim_csn1_o = (pad_mux_i[5 ] == 2'b00) ? spi_csn_i[0][1] : ((pad_mux_i[5 ] == 2'b01) ? gpio_out_i[5 ] : ((pad_mux_i[5 ] == 2'b10) ? s_alt2 : s_alt3 )); - assign out_spim_sck_o = (pad_mux_i[6 ] == 2'b00) ? spi_clk_i[0] : ((pad_mux_i[6 ] == 2'b01) ? gpio_out_i[6 ] : ((pad_mux_i[6 ] == 2'b10) ? s_alt2 : s_alt3 )); - assign out_uart_rx_o = (pad_mux_i[7 ] == 2'b00) ? 1'b0 : ((pad_mux_i[7 ] == 2'b01) ? gpio_out_i[7 ] : ((pad_mux_i[7 ] == 2'b10) ? i2c_sda_out_i[1] : s_alt3 )); - assign out_uart_tx_o = (pad_mux_i[8 ] == 2'b00) ? uart_tx_i : ((pad_mux_i[8 ] == 2'b01) ? gpio_out_i[8 ] : ((pad_mux_i[8 ] == 2'b10) ? i2c_scl_out_i[1] : s_alt3 )); - assign out_cam_pclk_o = (pad_mux_i[9 ] == 2'b00) ? 1'b0 : ((pad_mux_i[9 ] == 2'b01) ? gpio_out_i[9 ] : ((pad_mux_i[9 ] == 2'b10) ? timer1_i[0] : s_alt3 )); - assign out_cam_hsync_o = (pad_mux_i[10] == 2'b00) ? 1'b0 : ((pad_mux_i[10] == 2'b01) ? gpio_out_i[10] : ((pad_mux_i[10] == 2'b10) ? timer1_i[1] : s_alt3 )); - assign out_cam_data0_o = (pad_mux_i[11] == 2'b00) ? 1'b0 : ((pad_mux_i[11] == 2'b01) ? gpio_out_i[11] : ((pad_mux_i[11] == 2'b10) ? timer1_i[2] : s_alt3 )); - assign out_cam_data1_o = (pad_mux_i[12] == 2'b00) ? 1'b0 : ((pad_mux_i[12] == 2'b01) ? gpio_out_i[12] : ((pad_mux_i[12] == 2'b10) ? timer1_i[3] : s_alt3 )); - assign out_cam_data2_o = (pad_mux_i[13] == 2'b00) ? 1'b0 : ((pad_mux_i[13] == 2'b01) ? gpio_out_i[13] : ((pad_mux_i[13] == 2'b10) ? timer2_i[0] : s_alt3 )); - assign out_cam_data3_o = (pad_mux_i[14] == 2'b00) ? 1'b0 : ((pad_mux_i[14] == 2'b01) ? gpio_out_i[14] : ((pad_mux_i[14] == 2'b10) ? timer2_i[1] : s_alt3 )); - assign out_cam_data4_o = (pad_mux_i[15] == 2'b00) ? 1'b0 : ((pad_mux_i[15] == 2'b01) ? gpio_out_i[15] : ((pad_mux_i[15] == 2'b10) ? timer2_i[2] : s_alt3 )); - assign out_cam_data5_o = (pad_mux_i[16] == 2'b00) ? 1'b0 : ((pad_mux_i[16] == 2'b01) ? gpio_out_i[16] : ((pad_mux_i[16] == 2'b10) ? timer2_i[3] : s_alt3 )); - assign out_cam_data6_o = (pad_mux_i[17] == 2'b00) ? 1'b0 : ((pad_mux_i[17] == 2'b01) ? gpio_out_i[17] : ((pad_mux_i[17] == 2'b10) ? timer3_i[0] : s_alt3 )); - assign out_cam_data7_o = (pad_mux_i[18] == 2'b00) ? 1'b0 : ((pad_mux_i[18] == 2'b01) ? gpio_out_i[18] : ((pad_mux_i[18] == 2'b10) ? timer3_i[1] : s_alt3 )); - assign out_cam_vsync_o = (pad_mux_i[19] == 2'b00) ? 1'b0 : ((pad_mux_i[19] == 2'b01) ? gpio_out_i[19] : ((pad_mux_i[19] == 2'b10) ? timer3_i[2] : s_alt3 )); - assign out_sdio_clk_o = (pad_mux_i[20] == 2'b00) ? sdio_clk_i : ((pad_mux_i[20] == 2'b01) ? gpio_out_i[20] : ((pad_mux_i[20] == 2'b10) ? s_alt2 : s_alt3 )); - assign out_sdio_cmd_o = (pad_mux_i[21] == 2'b00) ? sdio_cmd_i : ((pad_mux_i[21] == 2'b01) ? gpio_out_i[21] : ((pad_mux_i[21] == 2'b10) ? s_alt2 : s_alt3 )); - assign out_sdio_data0_o = (pad_mux_i[22] == 2'b00) ? sdio_data_i[0] : ((pad_mux_i[22] == 2'b01) ? gpio_out_i[22] : ((pad_mux_i[22] == 2'b10) ? s_alt2 : s_alt3 )); - assign out_sdio_data1_o = (pad_mux_i[23] == 2'b00) ? sdio_data_i[1] : ((pad_mux_i[23] == 2'b01) ? gpio_out_i[23] : ((pad_mux_i[23] == 2'b10) ? s_alt2 : s_alt3 )); - assign out_sdio_data2_o = (pad_mux_i[24] == 2'b00) ? sdio_data_i[2] : ((pad_mux_i[24] == 2'b01) ? gpio_out_i[24] : ((pad_mux_i[24] == 2'b10) ? i2c_sda_out_i[1] : s_alt3 )); - assign out_sdio_data3_o = (pad_mux_i[25] == 2'b00) ? sdio_data_i[3] : ((pad_mux_i[25] == 2'b01) ? gpio_out_i[25] : ((pad_mux_i[25] == 2'b10) ? i2c_scl_out_i[1] : s_alt3 )); - assign out_i2c0_sda_o = (pad_mux_i[33] == 2'b00) ? i2c_sda_out_i[0] : ((pad_mux_i[33] == 2'b01) ? gpio_out_i[26] : ((pad_mux_i[33] == 2'b10) ? s_alt2 : s_alt3 )); - assign out_i2c0_scl_o = (pad_mux_i[34] == 2'b00) ? i2c_scl_out_i[0] : ((pad_mux_i[34] == 2'b01) ? gpio_out_i[27] : ((pad_mux_i[34] == 2'b10) ? s_alt2 : s_alt3 )); - assign out_i2s0_sck_o = (pad_mux_i[35] == 2'b00) ? i2s_slave_sck_i : ((pad_mux_i[35] == 2'b01) ? gpio_out_i[28] : ((pad_mux_i[35] == 2'b10) ? s_alt2 : s_alt3 )); - assign out_i2s0_ws_o = (pad_mux_i[36] == 2'b00) ? i2s_slave_ws_i : ((pad_mux_i[36] == 2'b01) ? gpio_out_i[29] : ((pad_mux_i[36] == 2'b10) ? s_alt2 : s_alt3 )); - assign out_i2s0_sdi_o = (pad_mux_i[37] == 2'b00) ? 1'b0 : ((pad_mux_i[37] == 2'b01) ? gpio_out_i[30] : ((pad_mux_i[37] == 2'b10) ? s_alt2 : s_alt3 )); - assign out_i2s1_sdi_o = (pad_mux_i[38] == 2'b00) ? 1'b0 : ((pad_mux_i[38] == 2'b01) ? gpio_out_i[31] : ((pad_mux_i[38] == 2'b10) ? s_alt2 : s_alt3 )); - - ///////////////////////////////////////////////////////////////////////////////////////////// - // DATA INPUT - ///////////////////////////////////////////////////////////////////////////////////////////// - // SPI MASTER1 - // assign spi_master1_sdi_o = (pad_mux_i[0] == 2'b00) ? in_rf_miso_i: (pad_mux_i[40] == 2'b00) ? in_spim1_miso_i : 1'b0; - // assign spi_sdi_o[1] = 1'b0; - - assign sdio_cmd_o = (pad_mux_i[21] == 2'b00) ? in_sdio_cmd_i : 1'b0; - assign sdio_data_o[0] = (pad_mux_i[22] == 2'b00) ? in_sdio_data0_i : 1'b0; - assign sdio_data_o[1] = (pad_mux_i[23] == 2'b00) ? in_sdio_data1_i : 1'b0; - assign sdio_data_o[2] = (pad_mux_i[24] == 2'b00) ? in_sdio_data2_i : 1'b0; - assign sdio_data_o[3] = (pad_mux_i[25] == 2'b00) ? in_sdio_data3_i : 1'b0; - - // CAMERA - assign cam_pclk_o = (pad_mux_i[ 9] == 2'b00) ? in_cam_pclk_i : 1'b0; - assign cam_hsync_o = (pad_mux_i[10] == 2'b00) ? in_cam_hsync_i : 1'b0; - assign cam_data_o[0] = (pad_mux_i[11] == 2'b00) ? in_cam_data0_i : 1'b0; - assign cam_data_o[1] = (pad_mux_i[12] == 2'b00) ? in_cam_data1_i : 1'b0; - assign cam_data_o[2] = (pad_mux_i[13] == 2'b00) ? in_cam_data2_i : 1'b0; - assign cam_data_o[3] = (pad_mux_i[14] == 2'b00) ? in_cam_data3_i : 1'b0; - assign cam_data_o[4] = (pad_mux_i[15] == 2'b00) ? in_cam_data4_i : 1'b0; - assign cam_data_o[5] = (pad_mux_i[16] == 2'b00) ? in_cam_data5_i : 1'b0; - assign cam_data_o[6] = (pad_mux_i[17] == 2'b00) ? in_cam_data6_i : 1'b0; - assign cam_data_o[7] = (pad_mux_i[18] == 2'b00) ? in_cam_data7_i : 1'b0; - assign cam_vsync_o = (pad_mux_i[19] == 2'b00) ? in_cam_vsync_i : 1'b0; - - // I2C1 - assign i2c_sda_in_o[1] = (pad_mux_i[2] == 2'b10) ? in_spim_sdio2_i : (pad_mux_i[7] == 2'b10) ? in_uart_rx_i : (pad_mux_i[24] == 2'b10) ? in_sdio_data2_i: 1'b1 ; - assign i2c_scl_in_o[1] = (pad_mux_i[3] == 2'b10) ? in_spim_sdio3_i : (pad_mux_i[8] == 2'b10) ? in_uart_tx_i : (pad_mux_i[25] == 2'b10) ? in_sdio_data3_i: 1'b1 ; - - assign i2s_slave_sd1_o = (pad_mux_i[29] == 2'b00) ? in_i2s1_sdi_i : (pad_mux_i[27] == 2'b11) ? in_i2s1_sdi_i : 1'b0; - - // UART - assign uart_rx_o = (pad_mux_i[38] == 2'b00) ? in_uart_rx_i : 1'b1; - - assign spi_sdi_o[0][0] = (pad_mux_i[33] == 2'b00) ? in_spim_sdio0_i : 1'b0; - assign spi_sdi_o[0][1] = (pad_mux_i[34] == 2'b00) ? in_spim_sdio1_i : 1'b0; - assign spi_sdi_o[0][2] = (pad_mux_i[35] == 2'b00) ? in_spim_sdio2_i : 1'b0; - assign spi_sdi_o[0][3] = (pad_mux_i[36] == 2'b00) ? in_spim_sdio3_i : 1'b0; - - // I2C0 - assign i2c_sda_in_o[0] = (pad_mux_i[43] == 2'b00) ? in_i2c0_sda_i : 1'b1; - assign i2c_scl_in_o[0] = (pad_mux_i[44] == 2'b00) ? in_i2c0_scl_i : 1'b1; - - - assign i2s_slave_sck_o = (pad_mux_i[45] == 2'b00) ? in_i2s0_sck_i : 1'b0; - assign i2s_slave_ws_o = (pad_mux_i[46] == 2'b00) ? in_i2s0_ws_i : 1'b0; - assign i2s_slave_sd0_o = (pad_mux_i[47] == 2'b00) ? in_i2s0_sdi_i : 1'b0; - - // GPIO - assign gpio_in_o[0] = (pad_mux_i[0] == 2'b01) ? in_spim_sdio0_i : 1'b0 ; - assign gpio_in_o[1] = (pad_mux_i[1] == 2'b01) ? in_spim_sdio1_i : 1'b0 ; - assign gpio_in_o[2] = (pad_mux_i[2] == 2'b01) ? in_spim_sdio2_i : 1'b0 ; - assign gpio_in_o[3] = (pad_mux_i[3] == 2'b01) ? in_spim_sdio3_i : 1'b0 ; - assign gpio_in_o[4] = (pad_mux_i[4] == 2'b01) ? in_spim_csn0_i : 1'b0 ; - assign gpio_in_o[5] = (pad_mux_i[5] == 2'b01) ? in_spim_csn1_i : 1'b0 ; - assign gpio_in_o[6] = (pad_mux_i[6] == 2'b01) ? in_spim_sck_i : 1'b0 ; - assign gpio_in_o[7] = (pad_mux_i[7] == 2'b01) ? in_uart_rx_i : 1'b0 ; - assign gpio_in_o[8] = (pad_mux_i[8] == 2'b01) ? in_uart_tx_i : 1'b0 ; - assign gpio_in_o[9] = (pad_mux_i[9] == 2'b01) ? in_cam_pclk_i : 1'b0 ; - assign gpio_in_o[10] = (pad_mux_i[10] == 2'b01) ? in_cam_hsync_i : 1'b0 ; - assign gpio_in_o[11] = (pad_mux_i[11] == 2'b01) ? in_cam_data0_i : 1'b0 ; - assign gpio_in_o[12] = (pad_mux_i[12] == 2'b01) ? in_cam_data1_i : 1'b0 ; - assign gpio_in_o[13] = (pad_mux_i[13] == 2'b01) ? in_cam_data2_i : 1'b0 ; - assign gpio_in_o[14] = (pad_mux_i[14] == 2'b01) ? in_cam_data3_i : 1'b0 ; - assign gpio_in_o[15] = (pad_mux_i[15] == 2'b01) ? in_cam_data4_i : 1'b0 ; - assign gpio_in_o[16] = (pad_mux_i[16] == 2'b01) ? in_cam_data5_i : 1'b0 ; - assign gpio_in_o[17] = (pad_mux_i[17] == 2'b01) ? in_cam_data6_i : 1'b0 ; - assign gpio_in_o[18] = (pad_mux_i[18] == 2'b01) ? in_cam_data7_i : 1'b0 ; - assign gpio_in_o[19] = (pad_mux_i[19] == 2'b01) ? in_cam_vsync_i : 1'b0 ; - assign gpio_in_o[20] = (pad_mux_i[20] == 2'b01) ? in_sdio_clk_i : 1'b0 ; - assign gpio_in_o[21] = (pad_mux_i[21] == 2'b01) ? in_sdio_cmd_i : 1'b0 ; - assign gpio_in_o[22] = (pad_mux_i[22] == 2'b01) ? in_sdio_data0_i : 1'b0 ; - assign gpio_in_o[23] = (pad_mux_i[23] == 2'b01) ? in_sdio_data1_i : 1'b0 ; - assign gpio_in_o[24] = (pad_mux_i[24] == 2'b01) ? in_sdio_data2_i : 1'b0 ; - assign gpio_in_o[25] = (pad_mux_i[25] == 2'b01) ? in_sdio_data3_i : 1'b0 ; - assign gpio_in_o[26] = (pad_mux_i[33] == 2'b01) ? in_i2c0_sda_i : 1'b0 ; - assign gpio_in_o[27] = (pad_mux_i[34] == 2'b01) ? in_i2c0_scl_i : 1'b0 ; - assign gpio_in_o[28] = (pad_mux_i[35] == 2'b01) ? in_i2s0_sck_i : 1'b0 ; - assign gpio_in_o[29] = (pad_mux_i[36] == 2'b01) ? in_i2s0_ws_i : 1'b0 ; - assign gpio_in_o[30] = (pad_mux_i[37] == 2'b01) ? in_i2s0_sdi_i : 1'b0 ; - assign gpio_in_o[31] = (pad_mux_i[38] == 2'b01) ? in_i2s1_sdi_i : 1'b0 ; - - // PAD CFG mux between default and GPIO - assign pad_cfg_o[0] = (pad_mux_i[0] == 2'b01) ? gpio_cfg_i[0] : pad_cfg_i[0]; - assign pad_cfg_o[1] = (pad_mux_i[1] == 2'b01) ? gpio_cfg_i[1] : pad_cfg_i[1]; - assign pad_cfg_o[2] = (pad_mux_i[2] == 2'b01) ? gpio_cfg_i[2] : pad_cfg_i[2]; - assign pad_cfg_o[3] = (pad_mux_i[3] == 2'b01) ? gpio_cfg_i[3] : pad_cfg_i[3]; - assign pad_cfg_o[4] = (pad_mux_i[4] == 2'b01) ? gpio_cfg_i[4] : pad_cfg_i[4]; - assign pad_cfg_o[5] = (pad_mux_i[5] == 2'b01) ? gpio_cfg_i[5] : pad_cfg_i[5]; - assign pad_cfg_o[6] = (pad_mux_i[6] == 2'b01) ? gpio_cfg_i[6] : pad_cfg_i[6]; - assign pad_cfg_o[7] = (pad_mux_i[7] == 2'b01) ? gpio_cfg_i[7] : pad_cfg_i[7]; - assign pad_cfg_o[8] = (pad_mux_i[8] == 2'b01) ? gpio_cfg_i[8] : pad_cfg_i[8]; - assign pad_cfg_o[9] = (pad_mux_i[9] == 2'b01) ? gpio_cfg_i[9] : pad_cfg_i[9]; - assign pad_cfg_o[10] = (pad_mux_i[10] == 2'b01) ? gpio_cfg_i[10] : pad_cfg_i[10]; - assign pad_cfg_o[11] = (pad_mux_i[11] == 2'b01) ? gpio_cfg_i[11] : pad_cfg_i[11]; - assign pad_cfg_o[12] = (pad_mux_i[12] == 2'b01) ? gpio_cfg_i[12] : pad_cfg_i[12]; - assign pad_cfg_o[13] = (pad_mux_i[13] == 2'b01) ? gpio_cfg_i[13] : pad_cfg_i[13]; - assign pad_cfg_o[14] = (pad_mux_i[14] == 2'b01) ? gpio_cfg_i[14] : pad_cfg_i[14]; - assign pad_cfg_o[15] = (pad_mux_i[15] == 2'b01) ? gpio_cfg_i[15] : pad_cfg_i[15]; - assign pad_cfg_o[16] = (pad_mux_i[16] == 2'b01) ? gpio_cfg_i[16] : pad_cfg_i[16]; - assign pad_cfg_o[17] = (pad_mux_i[17] == 2'b01) ? gpio_cfg_i[17] : pad_cfg_i[17]; - assign pad_cfg_o[18] = (pad_mux_i[18] == 2'b01) ? gpio_cfg_i[18] : pad_cfg_i[18]; - assign pad_cfg_o[19] = (pad_mux_i[19] == 2'b01) ? gpio_cfg_i[19] : pad_cfg_i[19]; - assign pad_cfg_o[20] = (pad_mux_i[20] == 2'b01) ? gpio_cfg_i[20] : pad_cfg_i[20]; - assign pad_cfg_o[21] = (pad_mux_i[21] == 2'b01) ? gpio_cfg_i[21] : pad_cfg_i[21]; - assign pad_cfg_o[22] = (pad_mux_i[22] == 2'b01) ? gpio_cfg_i[22] : pad_cfg_i[22]; - assign pad_cfg_o[23] = (pad_mux_i[23] == 2'b01) ? gpio_cfg_i[23] : pad_cfg_i[23]; - assign pad_cfg_o[24] = (pad_mux_i[24] == 2'b01) ? gpio_cfg_i[24] : pad_cfg_i[24]; - assign pad_cfg_o[25] = (pad_mux_i[25] == 2'b01) ? gpio_cfg_i[25] : pad_cfg_i[25]; - assign pad_cfg_o[26] = pad_cfg_i[26]; - assign pad_cfg_o[27] = pad_cfg_i[27]; - assign pad_cfg_o[28] = pad_cfg_i[28]; - assign pad_cfg_o[29] = pad_cfg_i[29]; - assign pad_cfg_o[30] = pad_cfg_i[30]; - assign pad_cfg_o[31] = pad_cfg_i[31]; - assign pad_cfg_o[32] = pad_cfg_i[32]; - assign pad_cfg_o[33] = (pad_mux_i[33] == 2'b01) ? gpio_cfg_i[26] : pad_cfg_i[33]; - assign pad_cfg_o[34] = (pad_mux_i[34] == 2'b01) ? gpio_cfg_i[27] : pad_cfg_i[34]; - assign pad_cfg_o[35] = (pad_mux_i[35] == 2'b01) ? gpio_cfg_i[28] : pad_cfg_i[35]; - assign pad_cfg_o[36] = (pad_mux_i[36] == 2'b01) ? gpio_cfg_i[29] : pad_cfg_i[36]; - assign pad_cfg_o[37] = (pad_mux_i[37] == 2'b01) ? gpio_cfg_i[30] : pad_cfg_i[37]; - assign pad_cfg_o[38] = (pad_mux_i[38] == 2'b01) ? gpio_cfg_i[31] : pad_cfg_i[38]; - -endmodule diff --git a/rtl/pulpissimo/pad_frame.sv b/rtl/pulpissimo/pad_frame.sv deleted file mode 100644 index 1a79aaa3..00000000 --- a/rtl/pulpissimo/pad_frame.sv +++ /dev/null @@ -1,240 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - - -module pad_frame - ( - - input logic [47:0][5:0] pad_cfg_i , - - // REF CLOCK - output logic ref_clk_o , - - // RESET SIGNALS - output logic rstn_o , - - // JTAG SIGNALS - output logic jtag_tck_o , - output logic jtag_tdi_o , - input logic jtag_tdo_i , - output logic jtag_tms_o , - output logic jtag_trst_o , - - input logic oe_sdio_clk_i , - input logic oe_sdio_cmd_i , - input logic oe_sdio_data0_i , - input logic oe_sdio_data1_i , - input logic oe_sdio_data2_i , - input logic oe_sdio_data3_i , - input logic oe_spim_sdio0_i , - input logic oe_spim_sdio1_i , - input logic oe_spim_sdio2_i , - input logic oe_spim_sdio3_i , - input logic oe_spim_csn0_i , - input logic oe_spim_csn1_i , - input logic oe_spim_sck_i , - input logic oe_i2s0_sck_i , - input logic oe_i2s0_ws_i , - input logic oe_i2s0_sdi_i , - input logic oe_i2s1_sdi_i , - input logic oe_cam_pclk_i , - input logic oe_cam_hsync_i , - input logic oe_cam_data0_i , - input logic oe_cam_data1_i , - input logic oe_cam_data2_i , - input logic oe_cam_data3_i , - input logic oe_cam_data4_i , - input logic oe_cam_data5_i , - input logic oe_cam_data6_i , - input logic oe_cam_data7_i , - input logic oe_cam_vsync_i , - input logic oe_i2c0_sda_i , - input logic oe_i2c0_scl_i , - input logic oe_uart_rx_i , - input logic oe_uart_tx_i , - - // INPUTS SIGNALS TO THE PADS - input logic out_sdio_clk_i , - input logic out_sdio_cmd_i , - input logic out_sdio_data0_i , - input logic out_sdio_data1_i , - input logic out_sdio_data2_i , - input logic out_sdio_data3_i , - input logic out_spim_sdio0_i , - input logic out_spim_sdio1_i , - input logic out_spim_sdio2_i , - input logic out_spim_sdio3_i , - input logic out_spim_csn0_i , - input logic out_spim_csn1_i , - input logic out_spim_sck_i , - input logic out_i2s0_sck_i , - input logic out_i2s0_ws_i , - input logic out_i2s0_sdi_i , - input logic out_i2s1_sdi_i , - input logic out_cam_pclk_i , - input logic out_cam_hsync_i , - input logic out_cam_data0_i , - input logic out_cam_data1_i , - input logic out_cam_data2_i , - input logic out_cam_data3_i , - input logic out_cam_data4_i , - input logic out_cam_data5_i , - input logic out_cam_data6_i , - input logic out_cam_data7_i , - input logic out_cam_vsync_i , - input logic out_i2c0_sda_i , - input logic out_i2c0_scl_i , - input logic out_uart_rx_i , - input logic out_uart_tx_i , - - // OUTPUT SIGNALS FROM THE PADS - output logic in_sdio_clk_o , - output logic in_sdio_cmd_o , - output logic in_sdio_data0_o , - output logic in_sdio_data1_o , - output logic in_sdio_data2_o , - output logic in_sdio_data3_o , - output logic in_spim_sdio0_o , - output logic in_spim_sdio1_o , - output logic in_spim_sdio2_o , - output logic in_spim_sdio3_o , - output logic in_spim_csn0_o , - output logic in_spim_csn1_o , - output logic in_spim_sck_o , - output logic in_i2s0_sck_o , - output logic in_i2s0_ws_o , - output logic in_i2s0_sdi_o , - output logic in_i2s1_sdi_o , - output logic in_cam_pclk_o , - output logic in_cam_hsync_o , - output logic in_cam_data0_o , - output logic in_cam_data1_o , - output logic in_cam_data2_o , - output logic in_cam_data3_o , - output logic in_cam_data4_o , - output logic in_cam_data5_o , - output logic in_cam_data6_o , - output logic in_cam_data7_o , - output logic in_cam_vsync_o , - output logic in_i2c0_sda_o , - output logic in_i2c0_scl_o , - output logic in_uart_rx_o , - output logic in_uart_tx_o , - - output logic [1:0] bootsel_o , - - // EXT CHIP TP PADS - inout wire pad_sdio_clk , - inout wire pad_sdio_cmd , - inout wire pad_sdio_data0 , - inout wire pad_sdio_data1 , - inout wire pad_sdio_data2 , - inout wire pad_sdio_data3 , - inout wire pad_spim_sdio0 , - inout wire pad_spim_sdio1 , - inout wire pad_spim_sdio2 , - inout wire pad_spim_sdio3 , - inout wire pad_spim_csn0 , - inout wire pad_spim_csn1 , - inout wire pad_spim_sck , - inout wire pad_i2s0_sck , - inout wire pad_i2s0_ws , - inout wire pad_i2s0_sdi , - inout wire pad_i2s1_sdi , - inout wire pad_cam_pclk , - inout wire pad_cam_hsync , - inout wire pad_cam_data0 , - inout wire pad_cam_data1 , - inout wire pad_cam_data2 , - inout wire pad_cam_data3 , - inout wire pad_cam_data4 , - inout wire pad_cam_data5 , - inout wire pad_cam_data6 , - inout wire pad_cam_data7 , - inout wire pad_cam_vsync , - inout wire pad_i2c0_sda , - inout wire pad_i2c0_scl , - inout wire pad_uart_rx , - inout wire pad_uart_tx , - - inout wire pad_reset_n , - inout wire pad_bootsel0 , - inout wire pad_bootsel1 , - inout wire pad_jtag_tck , - inout wire pad_jtag_tdi , - inout wire pad_jtag_tdo , - inout wire pad_jtag_tms , - inout wire pad_jtag_trst , - inout wire pad_xtal_in - ); - - pad_functional_pd padinst_sdio_data0 (.OEN(~oe_sdio_data0_i ), .I(out_sdio_data0_i ), .O(in_sdio_data0_o ), .PAD(pad_sdio_data0 ), .PEN(~pad_cfg_i[22][0]) ); - pad_functional_pd padinst_sdio_data1 (.OEN(~oe_sdio_data1_i ), .I(out_sdio_data1_i ), .O(in_sdio_data1_o ), .PAD(pad_sdio_data1 ), .PEN(~pad_cfg_i[23][0]) ); - pad_functional_pd padinst_sdio_data2 (.OEN(~oe_sdio_data2_i ), .I(out_sdio_data2_i ), .O(in_sdio_data2_o ), .PAD(pad_sdio_data2 ), .PEN(~pad_cfg_i[24][0]) ); - pad_functional_pd padinst_sdio_data3 (.OEN(~oe_sdio_data3_i ), .I(out_sdio_data3_i ), .O(in_sdio_data3_o ), .PAD(pad_sdio_data3 ), .PEN(~pad_cfg_i[25][0]) ); - pad_functional_pd padinst_sdio_clk (.OEN(~oe_sdio_clk_i ), .I(out_sdio_clk_i ), .O(in_sdio_clk_o ), .PAD(pad_sdio_clk ), .PEN(~pad_cfg_i[20][0]) ); - pad_functional_pd padinst_sdio_cmd (.OEN(~oe_sdio_cmd_i ), .I(out_sdio_cmd_i ), .O(in_sdio_cmd_o ), .PAD(pad_sdio_cmd ), .PEN(~pad_cfg_i[21][0]) ); - pad_functional_pd padinst_spim_sck (.OEN(~oe_spim_sck_i ), .I(out_spim_sck_i ), .O(in_spim_sck_o ), .PAD(pad_spim_sck ), .PEN(~pad_cfg_i[6][0] ) ); - pad_functional_pd padinst_spim_sdio0 (.OEN(~oe_spim_sdio0_i), .I(out_spim_sdio0_i), .O(in_spim_sdio0_o), .PAD(pad_spim_sdio0), .PEN(~pad_cfg_i[0][0] ) ); - pad_functional_pd padinst_spim_sdio1 (.OEN(~oe_spim_sdio1_i), .I(out_spim_sdio1_i), .O(in_spim_sdio1_o), .PAD(pad_spim_sdio1), .PEN(~pad_cfg_i[1][0] ) ); - pad_functional_pd padinst_spim_sdio2 (.OEN(~oe_spim_sdio2_i), .I(out_spim_sdio2_i), .O(in_spim_sdio2_o), .PAD(pad_spim_sdio2), .PEN(~pad_cfg_i[2][0] ) ); - pad_functional_pd padinst_spim_sdio3 (.OEN(~oe_spim_sdio3_i), .I(out_spim_sdio3_i), .O(in_spim_sdio3_o), .PAD(pad_spim_sdio3), .PEN(~pad_cfg_i[3][0] ) ); - pad_functional_pd padinst_spim_csn1 (.OEN(~oe_spim_csn1_i ), .I(out_spim_csn1_i ), .O(in_spim_csn1_o ), .PAD(pad_spim_csn1 ), .PEN(~pad_cfg_i[5][0] ) ); - pad_functional_pd padinst_spim_csn0 (.OEN(~oe_spim_csn0_i ), .I(out_spim_csn0_i ), .O(in_spim_csn0_o ), .PAD(pad_spim_csn0 ), .PEN(~pad_cfg_i[4][0] ) ); - - pad_functional_pd padinst_i2s1_sdi (.OEN(~oe_i2s1_sdi_i ), .I(out_i2s1_sdi_i ), .O(in_i2s1_sdi_o ), .PAD(pad_i2s1_sdi ), .PEN(~pad_cfg_i[38][0]) ); - pad_functional_pd padinst_i2s0_ws (.OEN(~oe_i2s0_ws_i ), .I(out_i2s0_ws_i ), .O(in_i2s0_ws_o ), .PAD(pad_i2s0_ws ), .PEN(~pad_cfg_i[36][0]) ); - pad_functional_pd padinst_i2s0_sdi (.OEN(~oe_i2s0_sdi_i ), .I(out_i2s0_sdi_i ), .O(in_i2s0_sdi_o ), .PAD(pad_i2s0_sdi ), .PEN(~pad_cfg_i[37][0]) ); - pad_functional_pd padinst_i2s0_sck (.OEN(~oe_i2s0_sck_i ), .I(out_i2s0_sck_i ), .O(in_i2s0_sck_o ), .PAD(pad_i2s0_sck ), .PEN(~pad_cfg_i[35][0]) ); - - - pad_functional_pd padinst_cam_pclk (.OEN(~oe_cam_pclk_i ), .I(out_cam_pclk_i ), .O(in_cam_pclk_o ), .PAD(pad_cam_pclk ), .PEN(~pad_cfg_i[9][0] ) ); - pad_functional_pd padinst_cam_hsync (.OEN(~oe_cam_hsync_i ), .I(out_cam_hsync_i ), .O(in_cam_hsync_o ), .PAD(pad_cam_hsync ), .PEN(~pad_cfg_i[10][0]) ); - pad_functional_pd padinst_cam_data0 (.OEN(~oe_cam_data0_i ), .I(out_cam_data0_i ), .O(in_cam_data0_o ), .PAD(pad_cam_data0 ), .PEN(~pad_cfg_i[11][0]) ); - pad_functional_pd padinst_cam_data1 (.OEN(~oe_cam_data1_i ), .I(out_cam_data1_i ), .O(in_cam_data1_o ), .PAD(pad_cam_data1 ), .PEN(~pad_cfg_i[12][0]) ); - pad_functional_pd padinst_cam_data2 (.OEN(~oe_cam_data2_i ), .I(out_cam_data2_i ), .O(in_cam_data2_o ), .PAD(pad_cam_data2 ), .PEN(~pad_cfg_i[13][0]) ); - pad_functional_pd padinst_cam_data3 (.OEN(~oe_cam_data3_i ), .I(out_cam_data3_i ), .O(in_cam_data3_o ), .PAD(pad_cam_data3 ), .PEN(~pad_cfg_i[14][0]) ); - pad_functional_pd padinst_cam_data4 (.OEN(~oe_cam_data4_i ), .I(out_cam_data4_i ), .O(in_cam_data4_o ), .PAD(pad_cam_data4 ), .PEN(~pad_cfg_i[15][0]) ); - pad_functional_pd padinst_cam_data5 (.OEN(~oe_cam_data5_i ), .I(out_cam_data5_i ), .O(in_cam_data5_o ), .PAD(pad_cam_data5 ), .PEN(~pad_cfg_i[16][0]) ); - pad_functional_pd padinst_cam_data6 (.OEN(~oe_cam_data6_i ), .I(out_cam_data6_i ), .O(in_cam_data6_o ), .PAD(pad_cam_data6 ), .PEN(~pad_cfg_i[17][0]) ); - pad_functional_pd padinst_cam_data7 (.OEN(~oe_cam_data7_i ), .I(out_cam_data7_i ), .O(in_cam_data7_o ), .PAD(pad_cam_data7 ), .PEN(~pad_cfg_i[18][0]) ); - pad_functional_pd padinst_cam_vsync (.OEN(~oe_cam_vsync_i ), .I(out_cam_vsync_i ), .O(in_cam_vsync_o ), .PAD(pad_cam_vsync ), .PEN(~pad_cfg_i[19][0]) ); - - pad_functional_pu padinst_uart_rx (.OEN(~oe_uart_rx_i ), .I(out_uart_rx_i ), .O(in_uart_rx_o ), .PAD(pad_uart_rx ), .PEN(~pad_cfg_i[33][0]) ); - pad_functional_pu padinst_uart_tx (.OEN(~oe_uart_tx_i ), .I(out_uart_tx_i ), .O(in_uart_tx_o ), .PAD(pad_uart_tx ), .PEN(~pad_cfg_i[34][0]) ); - pad_functional_pu padinst_i2c0_sda (.OEN(~oe_i2c0_sda_i ), .I(out_i2c0_sda_i ), .O(in_i2c0_sda_o ), .PAD(pad_i2c0_sda ), .PEN(~pad_cfg_i[7][0] ) ); - pad_functional_pu padinst_i2c0_scl (.OEN(~oe_i2c0_scl_i ), .I(out_i2c0_scl_i ), .O(in_i2c0_scl_o ), .PAD(pad_i2c0_scl ), .PEN(~pad_cfg_i[8][0] ) ); - - - pad_functional_pu padinst_bootsel0 (.OEN(1'b1 ), .I( ), .O(bootsel_o[0] ), .PAD(pad_bootsel0 ), .PEN(1'b1 ) ); - pad_functional_pu padinst_bootsel1 (.OEN(1'b1 ), .I( ), .O(bootsel_o[1] ), .PAD(pad_bootsel1 ), .PEN(1'b1 ) ); - - -`ifndef PULP_FPGA_EMUL - pad_functional_pu padinst_ref_clk (.OEN(1'b1 ), .I( ), .O(ref_clk_o ), .PAD(pad_xtal_in ), .PEN(1'b1 ) ); - pad_functional_pu padinst_reset_n (.OEN(1'b1 ), .I( ), .O(rstn_o ), .PAD(pad_reset_n ), .PEN(1'b1 ) ); - pad_functional_pu padinst_jtag_tck (.OEN(1'b1 ), .I( ), .O(jtag_tck_o ), .PAD(pad_jtag_tck ), .PEN(1'b1 ) ); - pad_functional_pu padinst_jtag_tms (.OEN(1'b1 ), .I( ), .O(jtag_tms_o ), .PAD(pad_jtag_tms ), .PEN(1'b1 ) ); - pad_functional_pu padinst_jtag_tdi (.OEN(1'b1 ), .I( ), .O(jtag_tdi_o ), .PAD(pad_jtag_tdi ), .PEN(1'b1 ) ); - pad_functional_pu padinst_jtag_trstn (.OEN(1'b1 ), .I( ), .O(jtag_trst_o ), .PAD(pad_jtag_trst ), .PEN(1'b1 ) ); - pad_functional_pd padinst_jtag_tdo (.OEN(1'b0 ), .I(jtag_tdo_i ), .O( ), .PAD(pad_jtag_tdo ), .PEN(1'b1 ) ); -`else - assign ref_clk_o = pad_xtal_in; - assign rstn_o = pad_reset_n; - - //JTAG signals - assign pad_jtag_tdo = jtag_tdo_i; - assign jtag_trst_o = pad_jtag_trst; - assign jtag_tms_o = pad_jtag_tms; - assign jtag_tck_o = pad_jtag_tck; - assign jtag_tdi_o = pad_jtag_tdi; -`endif - -endmodule // pad_frame diff --git a/rtl/pulpissimo/pulpissimo.sv b/rtl/pulpissimo/pulpissimo.sv deleted file mode 100644 index 2b4ad4f6..00000000 --- a/rtl/pulpissimo/pulpissimo.sv +++ /dev/null @@ -1,881 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -`include "pulp_soc_defines.sv" - -module pulpissimo #( - parameter CORE_TYPE = 0, // 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY) - parameter USE_FPU = 1, - parameter USE_ZFINX = 1, - parameter USE_HWPE = 0, - parameter SIM_STDOUT = 0 -) ( - inout wire pad_spim_sdio0, - inout wire pad_spim_sdio1, - inout wire pad_spim_sdio2, - inout wire pad_spim_sdio3, - inout wire pad_spim_csn0, - inout wire pad_spim_csn1, - inout wire pad_spim_sck, - - inout wire pad_uart_rx, - inout wire pad_uart_tx, - - inout wire pad_cam_pclk, - inout wire pad_cam_hsync, - inout wire pad_cam_data0, - inout wire pad_cam_data1, - inout wire pad_cam_data2, - inout wire pad_cam_data3, - inout wire pad_cam_data4, - inout wire pad_cam_data5, - inout wire pad_cam_data6, - inout wire pad_cam_data7, - inout wire pad_cam_vsync, - - inout wire pad_sdio_clk, - inout wire pad_sdio_cmd, - inout wire pad_sdio_data0, - inout wire pad_sdio_data1, - inout wire pad_sdio_data2, - inout wire pad_sdio_data3, - - inout wire pad_i2c0_sda, - inout wire pad_i2c0_scl, - - inout wire pad_i2s0_sck, - inout wire pad_i2s0_ws, - inout wire pad_i2s0_sdi, - inout wire pad_i2s1_sdi, - - inout wire pad_reset_n, - inout wire pad_bootsel0, - inout wire pad_bootsel1, - - inout wire pad_jtag_tck, - inout wire pad_jtag_tdi, - inout wire pad_jtag_tdo, - inout wire pad_jtag_tms, - inout wire pad_jtag_trst, - - inout wire pad_xtal_in -); - - localparam AXI_ADDR_WIDTH = 32; - localparam AXI_CLUSTER_SOC_DATA_WIDTH = 64; - localparam AXI_SOC_CLUSTER_DATA_WIDTH = 32; - localparam AXI_CLUSTER_SOC_ID_WIDTH = 6; - - localparam AXI_USER_WIDTH = 6; - localparam AXI_CLUSTER_SOC_STRB_WIDTH = AXI_CLUSTER_SOC_DATA_WIDTH/8; - localparam AXI_SOC_CLUSTER_STRB_WIDTH = AXI_SOC_CLUSTER_DATA_WIDTH/8; - - localparam BUFFER_WIDTH = 8; - localparam EVENT_WIDTH = 8; - - localparam CVP_ADDR_WIDTH = 32; - localparam CVP_DATA_WIDTH = 32; - - // - // PAD FRAME TO PAD CONTROL SIGNALS - // - - logic [47:0][5:0] s_pad_cfg ; - - logic s_out_spim_sdio0; - logic s_out_spim_sdio1; - logic s_out_spim_sdio2; - logic s_out_spim_sdio3; - logic s_out_spim_csn0; - logic s_out_spim_csn1; - logic s_out_spim_sck; - logic s_out_uart_rx; - logic s_out_uart_tx; - logic s_out_cam_pclk; - logic s_out_cam_hsync; - logic s_out_cam_data0; - logic s_out_cam_data1; - logic s_out_cam_data2; - logic s_out_cam_data3; - logic s_out_cam_data4; - logic s_out_cam_data5; - logic s_out_cam_data6; - logic s_out_cam_data7; - logic s_out_cam_vsync; - logic s_out_sdio_clk; - logic s_out_sdio_cmd; - logic s_out_sdio_data0; - logic s_out_sdio_data1; - logic s_out_sdio_data2; - logic s_out_sdio_data3; - logic s_out_i2c0_sda; - logic s_out_i2c0_scl; - logic s_out_i2s0_sck; - logic s_out_i2s0_ws; - logic s_out_i2s0_sdi; - logic s_out_i2s1_sdi; - - logic s_in_spim_sdio0; - logic s_in_spim_sdio1; - logic s_in_spim_sdio2; - logic s_in_spim_sdio3; - logic s_in_spim_csn0; - logic s_in_spim_csn1; - logic s_in_spim_sck; - logic s_in_uart_rx; - logic s_in_uart_tx; - logic s_in_cam_pclk; - logic s_in_cam_hsync; - logic s_in_cam_data0; - logic s_in_cam_data1; - logic s_in_cam_data2; - logic s_in_cam_data3; - logic s_in_cam_data4; - logic s_in_cam_data5; - logic s_in_cam_data6; - logic s_in_cam_data7; - logic s_in_cam_vsync; - logic s_in_sdio_clk; - logic s_in_sdio_cmd; - logic s_in_sdio_data0; - logic s_in_sdio_data1; - logic s_in_sdio_data2; - logic s_in_sdio_data3; - logic s_in_i2c0_sda; - logic s_in_i2c0_scl; - logic s_in_i2s0_sck; - logic s_in_i2s0_ws; - logic s_in_i2s0_sdi; - logic s_in_i2s1_sdi; - - logic s_oe_spim_sdio0; - logic s_oe_spim_sdio1; - logic s_oe_spim_sdio2; - logic s_oe_spim_sdio3; - logic s_oe_spim_csn0; - logic s_oe_spim_csn1; - logic s_oe_spim_sck; - logic s_oe_uart_rx; - logic s_oe_uart_tx; - logic s_oe_cam_pclk; - logic s_oe_cam_hsync; - logic s_oe_cam_data0; - logic s_oe_cam_data1; - logic s_oe_cam_data2; - logic s_oe_cam_data3; - logic s_oe_cam_data4; - logic s_oe_cam_data5; - logic s_oe_cam_data6; - logic s_oe_cam_data7; - logic s_oe_cam_vsync; - logic s_oe_sdio_clk; - logic s_oe_sdio_cmd; - logic s_oe_sdio_data0; - logic s_oe_sdio_data1; - logic s_oe_sdio_data2; - logic s_oe_sdio_data3; - logic s_oe_i2c0_sda; - logic s_oe_i2c0_scl; - logic s_oe_i2s0_sck; - logic s_oe_i2s0_ws; - logic s_oe_i2s0_sdi; - logic s_oe_i2s1_sdi; - - // - // OTHER PAD FRAME SIGNALS - // - - logic s_ref_clk; - logic s_rstn; - - logic s_jtag_tck; - logic s_jtag_tdi; - logic s_jtag_tdo; - logic s_jtag_tms; - logic s_jtag_trst; - - // - // SOC TO SAFE DOMAINS SIGNALS - // - - logic s_test_clk; - logic s_slow_clk; - logic s_sel_fll_clk; - - logic [11:0] s_pm_cfg_data; - logic s_pm_cfg_req; - logic s_pm_cfg_ack; - - logic s_cluster_busy; - - logic s_soc_tck; - logic s_soc_trstn; - logic s_soc_tms; - logic s_soc_tdi; - - logic s_test_mode; - logic s_dft_cg_enable; - logic s_mode_select; - - logic [31:0] s_gpio_out; - logic [31:0] s_gpio_in; - logic [31:0] s_gpio_dir; - logic [191:0] s_gpio_cfg; - - logic s_rf_tx_clk; - logic s_rf_tx_oeb; - logic s_rf_tx_enb; - logic s_rf_tx_mode; - logic s_rf_tx_vsel; - logic s_rf_tx_data; - logic s_rf_rx_clk; - logic s_rf_rx_enb; - logic s_rf_rx_data; - - logic s_uart_tx; - logic s_uart_rx; - - logic s_i2c0_scl_out; - logic s_i2c0_scl_in; - logic s_i2c0_scl_oe; - logic s_i2c0_sda_out; - logic s_i2c0_sda_in; - logic s_i2c0_sda_oe; - logic s_i2c1_scl_out; - logic s_i2c1_scl_in; - logic s_i2c1_scl_oe; - logic s_i2c1_sda_out; - logic s_i2c1_sda_in; - logic s_i2c1_sda_oe; - logic s_i2s_sd0_in; - logic s_i2s_sd1_in; - logic s_i2s_sck_in; - logic s_i2s_ws_in; - logic s_i2s_sck0_out; - logic s_i2s_ws0_out; - logic [1:0] s_i2s_mode0_out; - logic s_i2s_sck1_out; - logic s_i2s_ws1_out; - logic [1:0] s_i2s_mode1_out; - logic s_i2s_slave_sck_oe; - logic s_i2s_slave_ws_oe; - logic s_spi_master0_csn0; - logic s_spi_master0_csn1; - logic s_spi_master0_sck; - logic s_spi_master0_sdi0; - logic s_spi_master0_sdi1; - logic s_spi_master0_sdi2; - logic s_spi_master0_sdi3; - logic s_spi_master0_sdo0; - logic s_spi_master0_sdo1; - logic s_spi_master0_sdo2; - logic s_spi_master0_sdo3; - logic s_spi_master0_oen0; - logic s_spi_master0_oen1; - logic s_spi_master0_oen2; - logic s_spi_master0_oen3; - - logic s_spi_master1_csn0; - logic s_spi_master1_csn1; - logic s_spi_master1_sck; - logic s_spi_master1_sdi; - logic s_spi_master1_sdo; - logic [1:0] s_spi_master1_mode; - - logic s_sdio_clk; - logic s_sdio_cmdi; - logic s_sdio_cmdo; - logic s_sdio_cmd_oen ; - logic [3:0] s_sdio_datai; - logic [3:0] s_sdio_datao; - logic [3:0] s_sdio_data_oen; - - - logic s_cam_pclk; - logic [7:0] s_cam_data; - logic s_cam_hsync; - logic s_cam_vsync; - logic [3:0] s_timer0; - logic [3:0] s_timer1; - logic [3:0] s_timer2; - logic [3:0] s_timer3; - - logic s_jtag_shift_dr; - logic s_jtag_update_dr; - logic s_jtag_capture_dr; - - logic s_axireg_sel; - logic s_axireg_tdi; - logic s_axireg_tdo; - - logic [7:0] s_soc_jtag_regi; - logic [7:0] s_soc_jtag_rego; - - logic s_rstn_por; - logic s_cluster_pow; - logic s_cluster_byp; - - logic s_dma_pe_irq_ack; - logic s_dma_pe_irq_valid; - - logic [127:0] s_pad_mux_soc; - logic [383:0] s_pad_cfg_soc; - - // due to the pad frame these numbers are fixed. Adjust the padframe - // accordingly if you change these. - localparam int unsigned N_UART = 1; - localparam int unsigned N_SPI = 1; - localparam int unsigned N_I2C = 2; - - logic [N_SPI-1:0] s_spi_clk; - logic [N_SPI-1:0][3:0] s_spi_csn; - logic [N_SPI-1:0][3:0] s_spi_oen; - logic [N_SPI-1:0][3:0] s_spi_sdo; - logic [N_SPI-1:0][3:0] s_spi_sdi; - - logic [N_I2C-1:0] s_i2c_scl_in; - logic [N_I2C-1:0] s_i2c_scl_out; - logic [N_I2C-1:0] s_i2c_scl_oe; - logic [N_I2C-1:0] s_i2c_sda_in; - logic [N_I2C-1:0] s_i2c_sda_out; - logic [N_I2C-1:0] s_i2c_sda_oe; - - - // - // SOC TO CLUSTER DOMAINS SIGNALS - // - // PULPissimo doens't have a cluster so we ignore them - - logic s_dma_pe_evt_ack; - logic s_dma_pe_evt_valid; - logic s_dma_pe_int_ack; - logic s_dma_pe_int_valid; - logic s_pf_evt_ack; - logic s_pf_evt_valid; - - - - // - // OTHER PAD FRAME SIGNALS - // - logic [1:0] s_bootsel; - logic s_fc_fetch_en_valid; - logic s_fc_fetch_en; - - // - // PAD FRAME - // - pad_frame pad_frame_i ( - .pad_cfg_i ( s_pad_cfg ), - .ref_clk_o ( s_ref_clk ), - .rstn_o ( s_rstn ), - .jtag_tdo_i ( s_jtag_tdo ), - .jtag_tck_o ( s_jtag_tck ), - .jtag_tdi_o ( s_jtag_tdi ), - .jtag_tms_o ( s_jtag_tms ), - .jtag_trst_o ( s_jtag_trst ), - - .oe_spim_sdio0_i ( s_oe_spim_sdio0 ), - .oe_spim_sdio1_i ( s_oe_spim_sdio1 ), - .oe_spim_sdio2_i ( s_oe_spim_sdio2 ), - .oe_spim_sdio3_i ( s_oe_spim_sdio3 ), - .oe_spim_csn0_i ( s_oe_spim_csn0 ), - .oe_spim_csn1_i ( s_oe_spim_csn1 ), - .oe_spim_sck_i ( s_oe_spim_sck ), - .oe_sdio_clk_i ( s_oe_sdio_clk ), - .oe_sdio_cmd_i ( s_oe_sdio_cmd ), - .oe_sdio_data0_i ( s_oe_sdio_data0 ), - .oe_sdio_data1_i ( s_oe_sdio_data1 ), - .oe_sdio_data2_i ( s_oe_sdio_data2 ), - .oe_sdio_data3_i ( s_oe_sdio_data3 ), - .oe_i2s0_sck_i ( s_oe_i2s0_sck ), - .oe_i2s0_ws_i ( s_oe_i2s0_ws ), - .oe_i2s0_sdi_i ( s_oe_i2s0_sdi ), - .oe_i2s1_sdi_i ( s_oe_i2s1_sdi ), - .oe_cam_pclk_i ( s_oe_cam_pclk ), - .oe_cam_hsync_i ( s_oe_cam_hsync ), - .oe_cam_data0_i ( s_oe_cam_data0 ), - .oe_cam_data1_i ( s_oe_cam_data1 ), - .oe_cam_data2_i ( s_oe_cam_data2 ), - .oe_cam_data3_i ( s_oe_cam_data3 ), - .oe_cam_data4_i ( s_oe_cam_data4 ), - .oe_cam_data5_i ( s_oe_cam_data5 ), - .oe_cam_data6_i ( s_oe_cam_data6 ), - .oe_cam_data7_i ( s_oe_cam_data7 ), - .oe_cam_vsync_i ( s_oe_cam_vsync ), - .oe_i2c0_sda_i ( s_oe_i2c0_sda ), - .oe_i2c0_scl_i ( s_oe_i2c0_scl ), - .oe_uart_rx_i ( s_oe_uart_rx ), - .oe_uart_tx_i ( s_oe_uart_tx ), - - .out_spim_sdio0_i ( s_out_spim_sdio0 ), - .out_spim_sdio1_i ( s_out_spim_sdio1 ), - .out_spim_sdio2_i ( s_out_spim_sdio2 ), - .out_spim_sdio3_i ( s_out_spim_sdio3 ), - .out_spim_csn0_i ( s_out_spim_csn0 ), - .out_spim_csn1_i ( s_out_spim_csn1 ), - .out_spim_sck_i ( s_out_spim_sck ), - .out_sdio_clk_i ( s_out_sdio_clk ), - .out_sdio_cmd_i ( s_out_sdio_cmd ), - .out_sdio_data0_i ( s_out_sdio_data0 ), - .out_sdio_data1_i ( s_out_sdio_data1 ), - .out_sdio_data2_i ( s_out_sdio_data2 ), - .out_sdio_data3_i ( s_out_sdio_data3 ), - .out_i2s0_sck_i ( s_out_i2s0_sck ), - .out_i2s0_ws_i ( s_out_i2s0_ws ), - .out_i2s0_sdi_i ( s_out_i2s0_sdi ), - .out_i2s1_sdi_i ( s_out_i2s1_sdi ), - .out_cam_pclk_i ( s_out_cam_pclk ), - .out_cam_hsync_i ( s_out_cam_hsync ), - .out_cam_data0_i ( s_out_cam_data0 ), - .out_cam_data1_i ( s_out_cam_data1 ), - .out_cam_data2_i ( s_out_cam_data2 ), - .out_cam_data3_i ( s_out_cam_data3 ), - .out_cam_data4_i ( s_out_cam_data4 ), - .out_cam_data5_i ( s_out_cam_data5 ), - .out_cam_data6_i ( s_out_cam_data6 ), - .out_cam_data7_i ( s_out_cam_data7 ), - .out_cam_vsync_i ( s_out_cam_vsync ), - .out_i2c0_sda_i ( s_out_i2c0_sda ), - .out_i2c0_scl_i ( s_out_i2c0_scl ), - .out_uart_rx_i ( s_out_uart_rx ), - .out_uart_tx_i ( s_out_uart_tx ), - - .in_spim_sdio0_o ( s_in_spim_sdio0 ), - .in_spim_sdio1_o ( s_in_spim_sdio1 ), - .in_spim_sdio2_o ( s_in_spim_sdio2 ), - .in_spim_sdio3_o ( s_in_spim_sdio3 ), - .in_spim_csn0_o ( s_in_spim_csn0 ), - .in_spim_csn1_o ( s_in_spim_csn1 ), - .in_spim_sck_o ( s_in_spim_sck ), - .in_sdio_clk_o ( s_in_sdio_clk ), - .in_sdio_cmd_o ( s_in_sdio_cmd ), - .in_sdio_data0_o ( s_in_sdio_data0 ), - .in_sdio_data1_o ( s_in_sdio_data1 ), - .in_sdio_data2_o ( s_in_sdio_data2 ), - .in_sdio_data3_o ( s_in_sdio_data3 ), - .in_i2s0_sck_o ( s_in_i2s0_sck ), - .in_i2s0_ws_o ( s_in_i2s0_ws ), - .in_i2s0_sdi_o ( s_in_i2s0_sdi ), - .in_i2s1_sdi_o ( s_in_i2s1_sdi ), - .in_cam_pclk_o ( s_in_cam_pclk ), - .in_cam_hsync_o ( s_in_cam_hsync ), - .in_cam_data0_o ( s_in_cam_data0 ), - .in_cam_data1_o ( s_in_cam_data1 ), - .in_cam_data2_o ( s_in_cam_data2 ), - .in_cam_data3_o ( s_in_cam_data3 ), - .in_cam_data4_o ( s_in_cam_data4 ), - .in_cam_data5_o ( s_in_cam_data5 ), - .in_cam_data6_o ( s_in_cam_data6 ), - .in_cam_data7_o ( s_in_cam_data7 ), - .in_cam_vsync_o ( s_in_cam_vsync ), - .in_i2c0_sda_o ( s_in_i2c0_sda ), - .in_i2c0_scl_o ( s_in_i2c0_scl ), - .in_uart_rx_o ( s_in_uart_rx ), - .in_uart_tx_o ( s_in_uart_tx ), - .bootsel_o ( s_bootsel ), - - //EXT CHIP to PAD - .pad_spim_sdio0 ( pad_spim_sdio0 ), - .pad_spim_sdio1 ( pad_spim_sdio1 ), - .pad_spim_sdio2 ( pad_spim_sdio2 ), - .pad_spim_sdio3 ( pad_spim_sdio3 ), - .pad_spim_csn0 ( pad_spim_csn0 ), - .pad_spim_csn1 ( pad_spim_csn1 ), - .pad_spim_sck ( pad_spim_sck ), - .pad_sdio_clk ( pad_sdio_clk ), - .pad_sdio_cmd ( pad_sdio_cmd ), - .pad_sdio_data0 ( pad_sdio_data0 ), - .pad_sdio_data1 ( pad_sdio_data1 ), - .pad_sdio_data2 ( pad_sdio_data2 ), - .pad_sdio_data3 ( pad_sdio_data3 ), - .pad_i2s0_sck ( pad_i2s0_sck ), - .pad_i2s0_ws ( pad_i2s0_ws ), - .pad_i2s0_sdi ( pad_i2s0_sdi ), - .pad_i2s1_sdi ( pad_i2s1_sdi ), - .pad_cam_pclk ( pad_cam_pclk ), - .pad_cam_hsync ( pad_cam_hsync ), - .pad_cam_data0 ( pad_cam_data0 ), - .pad_cam_data1 ( pad_cam_data1 ), - .pad_cam_data2 ( pad_cam_data2 ), - .pad_cam_data3 ( pad_cam_data3 ), - .pad_cam_data4 ( pad_cam_data4 ), - .pad_cam_data5 ( pad_cam_data5 ), - .pad_cam_data6 ( pad_cam_data6 ), - .pad_cam_data7 ( pad_cam_data7 ), - .pad_cam_vsync ( pad_cam_vsync ), - .pad_i2c0_sda ( pad_i2c0_sda ), - .pad_i2c0_scl ( pad_i2c0_scl ), - .pad_uart_rx ( pad_uart_rx ), - .pad_uart_tx ( pad_uart_tx ), - - .pad_bootsel0 ( pad_bootsel0 ), - .pad_bootsel1 ( pad_bootsel1 ), - .pad_reset_n ( pad_reset_n ), - .pad_jtag_tck ( pad_jtag_tck ), - .pad_jtag_tdi ( pad_jtag_tdi ), - .pad_jtag_tdo ( pad_jtag_tdo ), - .pad_jtag_tms ( pad_jtag_tms ), - .pad_jtag_trst ( pad_jtag_trst ), - .pad_xtal_in ( pad_xtal_in ) - ); - - // - // SAFE DOMAIN - // - safe_domain safe_domain_i ( - - .ref_clk_i ( s_ref_clk ), - .slow_clk_o ( s_slow_clk ), - .rst_ni ( s_rstn ), - - .rst_no ( s_rstn_por ), - - .test_clk_o ( s_test_clk ), - .test_mode_o ( s_test_mode ), - .mode_select_o ( s_mode_select ), - .dft_cg_enable_o ( s_dft_cg_enable ), - - .pad_cfg_o ( s_pad_cfg ), - - .pad_cfg_i ( s_pad_cfg_soc ), - .pad_mux_i ( s_pad_mux_soc ), - - .gpio_out_i ( s_gpio_out ), - .gpio_in_o ( s_gpio_in ), - .gpio_dir_i ( s_gpio_dir ), - .gpio_cfg_i ( s_gpio_cfg ), - - .uart_tx_i ( s_uart_tx ), - .uart_rx_o ( s_uart_rx ), - - .i2c_scl_out_i ( s_i2c_scl_out ), - .i2c_scl_in_o ( s_i2c_scl_in ), - .i2c_scl_oe_i ( s_i2c_scl_oe ), - .i2c_sda_out_i ( s_i2c_sda_out ), - .i2c_sda_in_o ( s_i2c_sda_in ), - .i2c_sda_oe_i ( s_i2c_sda_oe ), - - .i2s_slave_sd0_o ( s_i2s_sd0_in ), - .i2s_slave_sd1_o ( s_i2s_sd1_in ), - .i2s_slave_ws_o ( s_i2s_ws_in ), - .i2s_slave_ws_i ( s_i2s_ws0_out ), - .i2s_slave_ws_oe ( s_i2s_slave_ws_oe ), - .i2s_slave_sck_o ( s_i2s_sck_in ), - .i2s_slave_sck_i ( s_i2s_sck0_out ), - .i2s_slave_sck_oe ( s_i2s_slave_sck_oe ), - - .spi_clk_i ( s_spi_clk ), - .spi_csn_i ( s_spi_csn ), - .spi_oen_i ( s_spi_oen ), - .spi_sdo_i ( s_spi_sdo ), - .spi_sdi_o ( s_spi_sdi ), - - .sdio_clk_i ( s_sdio_clk ), - .sdio_cmd_i ( s_sdio_cmdo ), - .sdio_cmd_o ( s_sdio_cmdi ), - .sdio_cmd_oen_i ( s_sdio_cmd_oen ), - .sdio_data_i ( s_sdio_datao ), - .sdio_data_o ( s_sdio_datai ), - .sdio_data_oen_i ( s_sdio_data_oen ), - - .cam_pclk_o ( s_cam_pclk ), - .cam_data_o ( s_cam_data ), - .cam_hsync_o ( s_cam_hsync ), - .cam_vsync_o ( s_cam_vsync ), - - .timer0_i ( s_timer0 ), - .timer1_i ( s_timer1 ), - .timer2_i ( s_timer2 ), - .timer3_i ( s_timer3 ), - - .out_spim_sdio0_o ( s_out_spim_sdio0 ), - .out_spim_sdio1_o ( s_out_spim_sdio1 ), - .out_spim_sdio2_o ( s_out_spim_sdio2 ), - .out_spim_sdio3_o ( s_out_spim_sdio3 ), - .out_spim_csn0_o ( s_out_spim_csn0 ), - .out_spim_csn1_o ( s_out_spim_csn1 ), - .out_spim_sck_o ( s_out_spim_sck ), - - .out_sdio_clk_o ( s_out_sdio_clk ), - .out_sdio_cmd_o ( s_out_sdio_cmd ), - .out_sdio_data0_o ( s_out_sdio_data0 ), - .out_sdio_data1_o ( s_out_sdio_data1 ), - .out_sdio_data2_o ( s_out_sdio_data2 ), - .out_sdio_data3_o ( s_out_sdio_data3 ), - - .out_uart_rx_o ( s_out_uart_rx ), - .out_uart_tx_o ( s_out_uart_tx ), - - .out_cam_pclk_o ( s_out_cam_pclk ), - .out_cam_hsync_o ( s_out_cam_hsync ), - .out_cam_data0_o ( s_out_cam_data0 ), - .out_cam_data1_o ( s_out_cam_data1 ), - .out_cam_data2_o ( s_out_cam_data2 ), - .out_cam_data3_o ( s_out_cam_data3 ), - .out_cam_data4_o ( s_out_cam_data4 ), - .out_cam_data5_o ( s_out_cam_data5 ), - .out_cam_data6_o ( s_out_cam_data6 ), - .out_cam_data7_o ( s_out_cam_data7 ), - .out_cam_vsync_o ( s_out_cam_vsync ), - - .out_i2c0_sda_o ( s_out_i2c0_sda ), - .out_i2c0_scl_o ( s_out_i2c0_scl ), - .out_i2s0_sck_o ( s_out_i2s0_sck ), - .out_i2s0_ws_o ( s_out_i2s0_ws ), - .out_i2s0_sdi_o ( s_out_i2s0_sdi ), - .out_i2s1_sdi_o ( s_out_i2s1_sdi ), - - .in_spim_sdio0_i ( s_in_spim_sdio0 ), - .in_spim_sdio1_i ( s_in_spim_sdio1 ), - .in_spim_sdio2_i ( s_in_spim_sdio2 ), - .in_spim_sdio3_i ( s_in_spim_sdio3 ), - .in_spim_csn0_i ( s_in_spim_csn0 ), - .in_spim_csn1_i ( s_in_spim_csn1 ), - .in_spim_sck_i ( s_in_spim_sck ), - - .in_sdio_clk_i ( s_in_sdio_clk ), - .in_sdio_cmd_i ( s_in_sdio_cmd ), - .in_sdio_data0_i ( s_in_sdio_data0 ), - .in_sdio_data1_i ( s_in_sdio_data1 ), - .in_sdio_data2_i ( s_in_sdio_data2 ), - .in_sdio_data3_i ( s_in_sdio_data3 ), - - .in_uart_rx_i ( s_in_uart_rx ), - .in_uart_tx_i ( s_in_uart_tx ), - .in_cam_pclk_i ( s_in_cam_pclk ), - .in_cam_hsync_i ( s_in_cam_hsync ), - .in_cam_data0_i ( s_in_cam_data0 ), - .in_cam_data1_i ( s_in_cam_data1 ), - .in_cam_data2_i ( s_in_cam_data2 ), - .in_cam_data3_i ( s_in_cam_data3 ), - .in_cam_data4_i ( s_in_cam_data4 ), - .in_cam_data5_i ( s_in_cam_data5 ), - .in_cam_data6_i ( s_in_cam_data6 ), - .in_cam_data7_i ( s_in_cam_data7 ), - .in_cam_vsync_i ( s_in_cam_vsync ), - - .in_i2c0_sda_i ( s_in_i2c0_sda ), - .in_i2c0_scl_i ( s_in_i2c0_scl ), - .in_i2s0_sck_i ( s_in_i2s0_sck ), - .in_i2s0_ws_i ( s_in_i2s0_ws ), - .in_i2s0_sdi_i ( s_in_i2s0_sdi ), - .in_i2s1_sdi_i ( s_in_i2s1_sdi ), - - .oe_spim_sdio0_o ( s_oe_spim_sdio0 ), - .oe_spim_sdio1_o ( s_oe_spim_sdio1 ), - .oe_spim_sdio2_o ( s_oe_spim_sdio2 ), - .oe_spim_sdio3_o ( s_oe_spim_sdio3 ), - .oe_spim_csn0_o ( s_oe_spim_csn0 ), - .oe_spim_csn1_o ( s_oe_spim_csn1 ), - .oe_spim_sck_o ( s_oe_spim_sck ), - - .oe_sdio_clk_o ( s_oe_sdio_clk ), - .oe_sdio_cmd_o ( s_oe_sdio_cmd ), - .oe_sdio_data0_o ( s_oe_sdio_data0 ), - .oe_sdio_data1_o ( s_oe_sdio_data1 ), - .oe_sdio_data2_o ( s_oe_sdio_data2 ), - .oe_sdio_data3_o ( s_oe_sdio_data3 ), - - .oe_uart_rx_o ( s_oe_uart_rx ), - .oe_uart_tx_o ( s_oe_uart_tx ), - .oe_cam_pclk_o ( s_oe_cam_pclk ), - .oe_cam_hsync_o ( s_oe_cam_hsync ), - .oe_cam_data0_o ( s_oe_cam_data0 ), - .oe_cam_data1_o ( s_oe_cam_data1 ), - .oe_cam_data2_o ( s_oe_cam_data2 ), - .oe_cam_data3_o ( s_oe_cam_data3 ), - .oe_cam_data4_o ( s_oe_cam_data4 ), - .oe_cam_data5_o ( s_oe_cam_data5 ), - .oe_cam_data6_o ( s_oe_cam_data6 ), - .oe_cam_data7_o ( s_oe_cam_data7 ), - .oe_cam_vsync_o ( s_oe_cam_vsync ), - - .oe_i2c0_sda_o ( s_oe_i2c0_sda ), - .oe_i2c0_scl_o ( s_oe_i2c0_scl ), - .oe_i2s0_sck_o ( s_oe_i2s0_sck ), - .oe_i2s0_ws_o ( s_oe_i2s0_ws ), - .oe_i2s0_sdi_o ( s_oe_i2s0_sdi ), - .oe_i2s1_sdi_o ( s_oe_i2s1_sdi ), - - .*); - - // - // SOC DOMAIN - // - soc_domain #( - .CORE_TYPE ( CORE_TYPE ), - .USE_FPU ( USE_FPU ), - .USE_ZFINX ( USE_ZFINX ), - .USE_HWPE ( USE_HWPE ), - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_IN_WIDTH ( AXI_CLUSTER_SOC_DATA_WIDTH ), - .AXI_DATA_OUT_WIDTH ( AXI_SOC_CLUSTER_DATA_WIDTH ), - .AXI_ID_IN_WIDTH ( AXI_CLUSTER_SOC_ID_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ), - .AXI_STRB_WIDTH_IN ( AXI_CLUSTER_SOC_STRB_WIDTH ), - .AXI_STRB_WIDTH_OUT ( AXI_SOC_CLUSTER_STRB_WIDTH ), - .EVNT_WIDTH ( EVENT_WIDTH ), - .CDC_FIFOS_LOG_DEPTH( 3 ), - .NB_CL_CORES ( 0 ), - .N_UART ( N_UART ), - .N_SPI ( N_SPI ), - .N_I2C ( N_I2C ), - .SIM_STDOUT ( SIM_STDOUT ) - ) soc_domain_i ( - - .ref_clk_i ( s_ref_clk ), - .slow_clk_i ( s_slow_clk ), - .test_clk_i ( s_test_clk ), - - .rstn_glob_i ( s_rstn_por ), - - .mode_select_i ( s_mode_select ), - .dft_cg_enable_i ( s_dft_cg_enable ), - .dft_test_mode_i ( s_test_mode ), - - .bootsel_i ( s_bootsel ), - - // we immediately start bootin g in the default setup - .fc_fetch_en_valid_i ( 1'b1 ), - .fc_fetch_en_i ( 1'b1 ), - - .jtag_tck_i ( s_jtag_tck ), - .jtag_trst_ni ( s_jtag_trst ), - .jtag_tms_i ( s_jtag_tms ), - .jtag_tdi_i ( s_jtag_tdi ), - .jtag_tdo_o ( s_jtag_tdo ), - - .pad_cfg_o ( s_pad_cfg_soc ), - .pad_mux_o ( s_pad_mux_soc ), - - .gpio_in_i ( s_gpio_in ), - .gpio_out_o ( s_gpio_out ), - .gpio_dir_o ( s_gpio_dir ), - .gpio_cfg_o ( s_gpio_cfg ), - - .uart_tx_o ( s_uart_tx ), - .uart_rx_i ( s_uart_rx ), - - .cam_clk_i ( s_cam_pclk ), - .cam_data_i ( s_cam_data ), - .cam_hsync_i ( s_cam_hsync ), - .cam_vsync_i ( s_cam_vsync ), - - .timer_ch0_o ( s_timer0 ), - .timer_ch1_o ( s_timer1 ), - .timer_ch2_o ( s_timer2 ), - .timer_ch3_o ( s_timer3 ), - - .i2c_scl_i ( s_i2c_scl_in ), - .i2c_scl_o ( s_i2c_scl_out ), - .i2c_scl_oe_o ( s_i2c_scl_oe ), - .i2c_sda_i ( s_i2c_sda_in ), - .i2c_sda_o ( s_i2c_sda_out ), - .i2c_sda_oe_o ( s_i2c_sda_oe ), - - .i2s_slave_sd0_i ( s_i2s_sd0_in ), - .i2s_slave_sd1_i ( s_i2s_sd1_in ), - .i2s_slave_ws_i ( s_i2s_ws_in ), - .i2s_slave_ws_o ( s_i2s_ws0_out ), - .i2s_slave_ws_oe ( s_i2s_slave_ws_oe ), - .i2s_slave_sck_i ( s_i2s_sck_in ), - .i2s_slave_sck_o ( s_i2s_sck0_out ), - .i2s_slave_sck_oe ( s_i2s_slave_sck_oe ), - - .spi_clk_o ( s_spi_clk ), - .spi_csn_o ( s_spi_csn ), - .spi_oen_o ( s_spi_oen ), - .spi_sdo_o ( s_spi_sdo ), - .spi_sdi_i ( s_spi_sdi ), - - .sdio_clk_o ( s_sdio_clk ), - .sdio_cmd_o ( s_sdio_cmdo ), - .sdio_cmd_i ( s_sdio_cmdi ), - .sdio_cmd_oen_o ( s_sdio_cmd_oen ), - .sdio_data_o ( s_sdio_datao ), - .sdio_data_i ( s_sdio_datai ), - .sdio_data_oen_o ( s_sdio_data_oen ), - - // TODO: wire up if needed - .hyper_cs_no ( ), - .hyper_ck_o ( ), - .hyper_ck_no ( ), - .hyper_rwds_o ( ), - .hyper_rwds_i ( '0 ), - .hyper_rwds_oe_o ( ), - .hyper_dq_i ( '0 ), - .hyper_dq_o ( ), - .hyper_dq_oe_o ( ), - .hyper_reset_no ( ), - - .cluster_busy_i ( s_cluster_busy ), - .cluster_irq_o ( ), - - .dma_pe_evt_ack_o ( s_dma_pe_evt_ack ), - .dma_pe_evt_valid_i ( s_dma_pe_evt_valid ), - .dma_pe_irq_ack_o ( s_dma_pe_irq_ack ), - .dma_pe_irq_valid_i ( s_dma_pe_irq_valid ), - .pf_evt_ack_o ( s_pf_evt_ack ), - .pf_evt_valid_i ( s_pf_evt_valid ), - - .cluster_pow_o ( s_cluster_pow ), - .cluster_byp_o ( s_cluster_byp ), - - - .cluster_clk_o ( ), - .cluster_rstn_o ( ), - - .cluster_rtc_o ( ), - .cluster_fetch_enable_o ( ), - .cluster_boot_addr_o ( ), - .cluster_test_en_o ( ), - .cluster_dbg_irq_valid_o ( ), // we dont' have a cluster - .async_data_slave_aw_rptr_o ( ), // we don't have a cluster - .async_data_slave_ar_rptr_o ( ), // we don't have a cluster - .async_data_slave_w_rptr_o ( ), // we don't have a cluster - .async_data_slave_r_wptr_o ( ), // we don't have a cluster - .async_data_slave_r_data_o ( ), // we don't have a cluster - .async_data_slave_b_wptr_o ( ), // we don't have a cluster - .async_data_slave_b_data_o ( ), // we don't have a cluster - .async_data_master_aw_wptr_o ( ), // we don't have a cluster - .async_data_master_aw_data_o ( ), // we don't have a cluster - .async_data_master_ar_wptr_o ( ), // we don't have a cluster - .async_data_master_ar_data_o ( ), // we don't have a cluster - .async_data_master_w_wptr_o ( ), // we don't have a cluster - .async_data_master_w_data_o ( ), // we don't have a cluster - .async_data_master_r_rptr_o ( ), // we don't have a cluster - .async_data_master_b_rptr_o ( ), // we don't have a cluster - .async_cluster_events_wptr_o ( ), // we don't have a cluster - .async_cluster_events_data_o ( ), // we don't have a cluster - .async_data_slave_aw_wptr_i ( '0 ), // We don't have a cluster - .async_data_slave_aw_data_i ( '0 ), // We don't have a cluster - .async_data_slave_ar_wptr_i ( '0 ), // We don't have a cluster - .async_data_slave_ar_data_i ( '0 ), // We don't have a cluster - .async_data_slave_w_wptr_i ( '0 ), // We don't have a cluster - .async_data_slave_w_data_i ( '0 ), // We don't have a cluster - .async_data_slave_r_rptr_i ( '0 ), // We don't have a cluster - .async_data_slave_b_rptr_i ( '0 ), // We don't have a cluster - .async_data_master_aw_rptr_i ( '0 ), // We don't have a cluster - .async_data_master_ar_rptr_i ( '0 ), // We don't have a cluster - .async_data_master_w_rptr_i ( '0 ), // We don't have a cluster - .async_data_master_r_wptr_i ( '0 ), // We don't have a cluster - .async_data_master_r_data_i ( '0 ), // We don't have a cluster - .async_data_master_b_wptr_i ( '0 ), // We don't have a cluster - .async_data_master_b_data_i ( '0 ), // We don't have a cluster - .async_cluster_events_rptr_i ( '0 ) // We don't have a cluster - ); - -assign s_dma_pe_evt_valid = '0; -assign s_dma_pe_irq_valid = '0; -assign s_pf_evt_valid = '0; -assign s_cluster_busy = '0; - -endmodule diff --git a/rtl/pulpissimo/rtc_clock.sv b/rtl/pulpissimo/rtc_clock.sv deleted file mode 100644 index 337e1b6a..00000000 --- a/rtl/pulpissimo/rtc_clock.sv +++ /dev/null @@ -1,233 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - - -module rtc_clock( - input logic clk_i, - input logic rstn_i, - - input logic clock_update_i, - output logic [21:0] clock_o, - input logic [21:0] clock_i, - - input logic [9:0] init_sec_cnt_i, - - input logic timer_update_i, - input logic timer_enable_i, - input logic timer_retrig_i, - input logic [16:0] timer_target_i, - output logic [16:0] timer_value_o, - - input logic alarm_enable_i, - input logic alarm_update_i, - input logic [21:0] alarm_clock_i, - output logic [21:0] alarm_clock_o, - - output logic event_o, - - output logic update_day_o -); - - logic [7:0] r_seconds; - logic [7:0] r_minutes; - logic [6:0] r_hours; - - logic [7:0] s_seconds; - logic [7:0] s_minutes; - logic [6:0] s_hours; - - logic [7:0] r_alarm_seconds; - logic [7:0] r_alarm_minutes; - logic [6:0] r_alarm_hours; - logic r_alarm_enable; - - logic [7:0] s_alarm_seconds; - logic [7:0] s_alarm_minutes; - logic [5:0] s_alarm_hours; - - logic [14:0] r_sec_counter; - - logic s_update_seconds; - logic s_update_minutes; - logic s_update_hours; - logic s_alarm_match; - logic r_alarm_match; - logic s_alarm_event; - logic s_timer_event; - logic s_timer_match; - - logic [16:0] r_timer; - logic [16:0] r_timer_target; - logic r_timer_en; - logic r_timer_retrig; - - - assign s_seconds = clock_i[7:0]; - assign s_minutes = clock_i[15:8]; - assign s_hours = clock_i[21:16]; - - assign s_alarm_seconds = alarm_clock_i[7:0]; - assign s_alarm_minutes = alarm_clock_i[15:8]; - assign s_alarm_hours = alarm_clock_i[21:16]; - - assign s_alarm_match = (r_seconds == s_alarm_seconds) & (r_minutes == s_alarm_minutes) & (r_hours == s_alarm_hours);//alarm condition(high for 1 sec) - assign s_alarm_event = r_alarm_enable & s_alarm_match & ~r_alarm_match; //edge detect on alarm event - - assign s_timer_match = r_timer == r_timer_target; - assign s_timer_event = r_timer_en & s_timer_match; - - assign s_update_seconds = r_sec_counter == 15'h7FFF; - assign s_update_minutes = s_update_seconds & (r_seconds == 8'h59); - assign s_update_hours = s_update_minutes & (r_minutes == 8'h59); - - assign event_o = s_alarm_event | s_timer_event; - assign update_day_o = s_update_hours & (r_hours == 6'h23); - assign clock_o = {r_hours,r_minutes,r_seconds}; - assign alarm_clock_o = {r_alarm_hours,r_alarm_minutes,r_alarm_seconds}; - - assign timer_value_o = r_timer; - - always @ (posedge clk_i or negedge rstn_i) - begin - if(~rstn_i) - begin - r_alarm_seconds <= 'h0; - r_alarm_minutes <= 'h0; - r_alarm_hours <= 'h0; - r_alarm_enable <= 'h0; - end - else - begin - if (alarm_update_i) - begin - r_alarm_enable <= alarm_enable_i; - r_alarm_seconds <= s_alarm_seconds; - r_alarm_minutes <= s_alarm_minutes; - r_alarm_hours <= s_alarm_hours ; - end - else if(s_alarm_event) //disable alarm when alarm event is generated(sw must retrigger) - r_alarm_enable <= 'h0; - end - end - - always @ (posedge clk_i or negedge rstn_i) - begin - if(~rstn_i) - r_alarm_match <= 'h0; - else - r_alarm_match <= s_alarm_match; - end - - always @ (posedge clk_i or negedge rstn_i) - begin - if(~rstn_i) - begin - r_timer_en <= 'h0; - r_timer_target <= 'h0; - r_timer <= 'h0; - r_timer_retrig <= 'h0; - end - else - begin - if (timer_update_i) - begin - r_timer_en <= timer_enable_i; - r_timer_target <= timer_target_i; - r_timer_retrig <= timer_retrig_i; - r_timer <= 'h0; - end - else if(r_timer_en) - begin - if(s_timer_match) - begin - if(!r_timer_retrig) - r_timer_en <= 0; - r_timer <= 'h0; - end - else - r_timer <= r_timer + 1; - end - end - end - - always @ (posedge clk_i or negedge rstn_i) - begin - if(~rstn_i) - r_sec_counter <= 'h0; - else - begin - if (clock_update_i) - r_sec_counter <= {init_sec_cnt_i,5'h0}; - else - r_sec_counter <= r_sec_counter + 1; - end - end - - always @(posedge clk_i or negedge rstn_i) - begin - if(~rstn_i) - begin - r_seconds <= 0; - r_minutes <= 0; - r_hours <= 0; - end - else - begin - if (clock_update_i) - begin - r_seconds <= s_seconds; - r_minutes <= s_minutes; - r_hours <= s_hours; - end - else - begin - if (s_update_seconds) - begin // advance the seconds - if (r_seconds[3:0] >= 4'h9) - r_seconds[3:0] <= 4'h0; - else - r_seconds[3:0] <= r_seconds[3:0] + 4'h1; - if (r_seconds >= 8'h59) - r_seconds[7:4] <= 4'h0; - else if (r_seconds[3:0] >= 4'h9) - r_seconds[7:4] <= r_seconds[7:4] + 4'h1; - end - - if (s_update_minutes) - begin // advance the minutes - if (r_minutes[3:0] >= 4'h9) - r_minutes[3:0] <= 4'h0; - else - r_minutes[3:0] <= r_minutes[3:0] + 4'h1; - if (r_minutes >= 8'h59) - r_minutes[7:4] <= 4'h0; - else if (r_minutes[3:0] >= 4'h9) - r_minutes[7:4] <= r_minutes[7:4] + 4'h1; - end - - if (s_update_hours) - begin // advance the hours - if (r_hours >= 6'h23) - begin - r_hours <= 6'h00; - end else if (r_hours[3:0] >= 4'h9) - begin - r_hours[3:0] <= 4'h0; - r_hours[5:4] <= r_hours[5:4] + 2'h1; - end else begin - r_hours[3:0] <= r_hours[3:0] + 4'h1; - end - end - end - end - end - - -endmodule diff --git a/rtl/pulpissimo/rtc_date.sv b/rtl/pulpissimo/rtc_date.sv deleted file mode 100644 index 26aab39d..00000000 --- a/rtl/pulpissimo/rtc_date.sv +++ /dev/null @@ -1,135 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - - -module rtc_date( - input logic clk_i, - input logic rstn_i, - - input logic date_update_i, - input logic [31:0] date_i, - output logic [31:0] date_o, - - input logic new_day_i -); - logic [5:0] s_day; - logic [4:0] s_month; - logic [13:0] s_year; - logic [5:0] r_day; - logic [4:0] r_month; - logic [13:0] r_year; - - logic s_end_of_month; - logic s_end_of_year; - logic s_year_century; - logic s_year_400; - logic s_year_leap; - logic s_year_div_4; - - assign s_day = date_i[5:0]; - assign s_month = date_i[12:8]; - assign s_year = date_i[29:16]; - - assign date_o = {2'b00,r_year,3'b000,r_month,2'b00,r_day}; - - assign s_end_of_year = s_end_of_month & (r_month == 5'h12); - - always_comb - begin - case(r_month) - 5'h01: s_end_of_month = (r_day == 6'h31); // Jan - 5'h02: s_end_of_month = (r_day == 6'h29) || ((~s_year_leap)&&(r_day == 6'h28)); - 5'h03: s_end_of_month = (r_day == 6'h31); // March - 5'h04: s_end_of_month = (r_day == 6'h30); // April - 5'h05: s_end_of_month = (r_day == 6'h31); // May - 5'h06: s_end_of_month = (r_day == 6'h30); // June - 5'h07: s_end_of_month = (r_day == 6'h31); // July - 5'h08: s_end_of_month = (r_day == 6'h31); // August - 5'h09: s_end_of_month = (r_day == 6'h30); // Sept - 5'h10: s_end_of_month = (r_day == 6'h31); // October - 5'h11: s_end_of_month = (r_day == 6'h30); // November - 5'h12: s_end_of_month = (r_day == 6'h31); // December - default: s_end_of_month = 1'b0; - endcase - end - - assign s_year_div_4 = ((~r_year[0])&&(r_year[4]==r_year[1])); - assign s_year_century = (r_year[7:0] == 8'h00); - assign s_year_400 = ((~r_year[8])&&((r_year[12]==r_year[9]))); - assign s_year_leap = (s_year_div_4) && ( (~s_year_century) || ((s_year_century)&&(s_year_400)) ); - - - // Adjust the day of month - always_ff @(posedge clk_i or negedge rstn_i) begin : proc_r_day - if(~rstn_i) begin - r_day <= 6'h1; - end else begin - if (date_update_i) - r_day <= s_day; - else if ((new_day_i)&&(s_end_of_month)) - r_day <= 6'h01; - else if ((new_day_i)&&(r_day[3:0] != 4'h9)) - r_day[3:0] <= r_day[3:0] + 4'h1; - else if (new_day_i) - begin - r_day[3:0] <= 4'h0; - r_day[5:4] <= r_day[5:4] + 2'h1; - end - - end - end - - always_ff @(posedge clk_i or negedge rstn_i) begin : proc_r_month - if(~rstn_i) begin - r_month <= 5'h01; - end else begin - if (date_update_i) - r_month <= s_month; - else if ((new_day_i)&&(s_end_of_year)) - r_month <= 5'h01; - else if ((new_day_i)&&(s_end_of_month)&&(r_month[3:0] != 4'h9)) - r_month[3:0] <= r_month[3:0] + 4'h1; - else if ((new_day_i)&&(s_end_of_month)) - begin - r_month[3:0] <= 4'h0; - r_month[4] <= 1; - end - end - end // proc_r_month - - always_ff @(posedge clk_i or negedge rstn_i) begin : proc_r_year - if(~rstn_i) begin - r_year <= 14'h2000; - end else begin - if (date_update_i) - r_year <= s_year; - else if ((new_day_i)&&(s_end_of_year)) - begin - if (r_year[3:0] != 4'h9) - r_year[3:0] <= r_year[3:0] + 4'h1; - else begin - r_year[3:0] <= 4'h0; - if (r_year[7:4] != 4'h9) - r_year[7:4] <= r_year[7:4] + 4'h1; - else begin - r_year[7:4] <= 4'h0; - if (r_year[11:8] != 4'h9) - r_year[11:8] <= r_year[11:8]+4'h1; - else begin - r_year[11:8] <= 4'h0; - r_year[13:12] <= r_year[13:12]+2'h1; - end - end - end - end - end - end - -endmodule diff --git a/rtl/pulpissimo/safe_domain.sv b/rtl/pulpissimo/safe_domain.sv deleted file mode 100644 index c800da6a..00000000 --- a/rtl/pulpissimo/safe_domain.sv +++ /dev/null @@ -1,436 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. -`include "pulp_soc_defines.sv" - -module safe_domain #( - parameter int unsigned FLL_DATA_WIDTH = 32, - parameter int unsigned FLL_ADDR_WIDTH = 32, - parameter int unsigned N_UART = 1, - parameter int unsigned N_SPI = 1, - parameter int unsigned N_I2C = 2 -) ( - input logic ref_clk_i , - output logic slow_clk_o , - input logic rst_ni , - output logic rst_no , - - output logic test_clk_o , - output logic test_mode_o , - output logic mode_select_o , - output logic dft_cg_enable_o , - - //********************************************************** - //*** PERIPHERALS SIGNALS ********************************** - //********************************************************** - - // PAD CONTROL REGISTER - input logic [127:0] pad_mux_i , - input logic [383:0] pad_cfg_i , - - output logic [47:0][5:0] pad_cfg_o , - - // GPIOS - input logic [31:0] gpio_out_i , - output logic [31:0] gpio_in_o , - input logic [31:0] gpio_dir_i , - input logic [191:0] gpio_cfg_i , - - // UART - input logic uart_tx_i , - output logic uart_rx_o , - - input logic [N_I2C-1:0] i2c_scl_out_i, - output logic [N_I2C-1:0] i2c_scl_in_o, - input logic [N_I2C-1:0] i2c_scl_oe_i, - input logic [N_I2C-1:0] i2c_sda_out_i, - output logic [N_I2C-1:0] i2c_sda_in_o, - input logic [N_I2C-1:0] i2c_sda_oe_i, - - // I2S - output logic i2s_slave_sd0_o , - output logic i2s_slave_sd1_o , - output logic i2s_slave_ws_o , - input logic i2s_slave_ws_i , - input logic i2s_slave_ws_oe , - output logic i2s_slave_sck_o , - input logic i2s_slave_sck_i , - input logic i2s_slave_sck_oe , - - // SPI MASTER - input logic [N_SPI-1:0] spi_clk_i, - input logic [N_SPI-1:0][3:0] spi_csn_i, - input logic [N_SPI-1:0][3:0] spi_oen_i, - input logic [N_SPI-1:0][3:0] spi_sdo_i, - output logic [N_SPI-1:0][3:0] spi_sdi_o, - - // SDIO - input logic sdio_clk_i, - input logic sdio_cmd_i, - output logic sdio_cmd_o, - input logic sdio_cmd_oen_i, - input logic [3:0] sdio_data_i, - output logic [3:0] sdio_data_o, - input logic [3:0] sdio_data_oen_i, - - // CAMERA INTERFACE - output logic cam_pclk_o , - output logic [7:0] cam_data_o , - output logic cam_hsync_o , - output logic cam_vsync_o , - - // TIMER - input logic [3:0] timer0_i , - input logic [3:0] timer1_i , - input logic [3:0] timer2_i , - input logic [3:0] timer3_i , - - //********************************************************** - //*** PAD FRAME SIGNALS ************************************ - //********************************************************** - - // PADS OUTPUTS - output logic out_spim_sdio0_o , - output logic out_spim_sdio1_o , - output logic out_spim_sdio2_o , - output logic out_spim_sdio3_o , - output logic out_spim_csn0_o , - output logic out_spim_csn1_o , - output logic out_spim_sck_o , - output logic out_sdio_clk_o , - output logic out_sdio_cmd_o , - output logic out_sdio_data0_o , - output logic out_sdio_data1_o , - output logic out_sdio_data2_o , - output logic out_sdio_data3_o , - output logic out_uart_rx_o , - output logic out_uart_tx_o , - output logic out_cam_pclk_o , - output logic out_cam_hsync_o , - output logic out_cam_data0_o , - output logic out_cam_data1_o , - output logic out_cam_data2_o , - output logic out_cam_data3_o , - output logic out_cam_data4_o , - output logic out_cam_data5_o , - output logic out_cam_data6_o , - output logic out_cam_data7_o , - output logic out_cam_vsync_o , - output logic out_i2c0_sda_o , - output logic out_i2c0_scl_o , - output logic out_i2s0_sck_o , - output logic out_i2s0_ws_o , - output logic out_i2s0_sdi_o , - output logic out_i2s1_sdi_o , - - - // PAD INPUTS - input logic in_spim_sdio0_i , - input logic in_spim_sdio1_i , - input logic in_spim_sdio2_i , - input logic in_spim_sdio3_i , - input logic in_spim_csn0_i , - input logic in_spim_csn1_i , - input logic in_spim_sck_i , - input logic in_sdio_clk_i , - input logic in_sdio_cmd_i , - input logic in_sdio_data0_i , - input logic in_sdio_data1_i , - input logic in_sdio_data2_i , - input logic in_sdio_data3_i , - input logic in_uart_rx_i , - input logic in_uart_tx_i , - input logic in_cam_pclk_i , - input logic in_cam_hsync_i , - input logic in_cam_data0_i , - input logic in_cam_data1_i , - input logic in_cam_data2_i , - input logic in_cam_data3_i , - input logic in_cam_data4_i , - input logic in_cam_data5_i , - input logic in_cam_data6_i , - input logic in_cam_data7_i , - input logic in_cam_vsync_i , - input logic in_i2c0_sda_i , - input logic in_i2c0_scl_i , - input logic in_i2s0_sck_i , - input logic in_i2s0_ws_i , - input logic in_i2s0_sdi_i , - input logic in_i2s1_sdi_i , - - // OUTPUT ENABLE - output logic oe_spim_sdio0_o , - output logic oe_spim_sdio1_o , - output logic oe_spim_sdio2_o , - output logic oe_spim_sdio3_o , - output logic oe_spim_csn0_o , - output logic oe_spim_csn1_o , - output logic oe_spim_sck_o , - output logic oe_sdio_clk_o , - output logic oe_sdio_cmd_o , - output logic oe_sdio_data0_o , - output logic oe_sdio_data1_o , - output logic oe_sdio_data2_o , - output logic oe_sdio_data3_o , - output logic oe_uart_rx_o , - output logic oe_uart_tx_o , - output logic oe_cam_pclk_o , - output logic oe_cam_hsync_o , - output logic oe_cam_data0_o , - output logic oe_cam_data1_o , - output logic oe_cam_data2_o , - output logic oe_cam_data3_o , - output logic oe_cam_data4_o , - output logic oe_cam_data5_o , - output logic oe_cam_data6_o , - output logic oe_cam_data7_o , - output logic oe_cam_vsync_o , - output logic oe_i2c0_sda_o , - output logic oe_i2c0_scl_o , - output logic oe_i2s0_sck_o , - output logic oe_i2s0_ws_o , - output logic oe_i2s0_sdi_o , - output logic oe_i2s1_sdi_o - ); - - logic s_test_clk; - - logic s_rtc_int; - logic s_gpio_wake; - logic s_rstn_sync; - logic s_rstn; - - - //********************************************************** - //*** GPIO CONFIGURATIONS ********************************** - //********************************************************** - - logic [31:0][5:0] s_gpio_cfg; - - genvar i,j; - - pad_control #( - .N_UART ( N_UART ), - .N_SPI ( N_SPI ), - .N_I2C ( N_I2C ) - ) pad_control_i ( - - //********************************************************************// - //*** PERIPHERALS SIGNALS ********************************************// - //********************************************************************// - .pad_mux_i ( pad_mux_i ), - .pad_cfg_i ( pad_cfg_i ), - .pad_cfg_o ( pad_cfg_o ), - - .gpio_out_i ( gpio_out_i ), - .gpio_in_o ( gpio_in_o ), - .gpio_dir_i ( gpio_dir_i ), - .gpio_cfg_i ( s_gpio_cfg ), - - .uart_tx_i ( uart_tx_i ), - .uart_rx_o ( uart_rx_o ), - - .i2c_scl_out_i ( i2c_scl_out_i ), - .i2c_scl_in_o ( i2c_scl_in_o ), - .i2c_scl_oe_i ( i2c_scl_oe_i ), - .i2c_sda_out_i ( i2c_sda_out_i ), - .i2c_sda_in_o ( i2c_sda_in_o ), - .i2c_sda_oe_i ( i2c_sda_oe_i ), - - .i2s_slave_sd0_o ( i2s_slave_sd0_o ), - .i2s_slave_sd1_o ( i2s_slave_sd1_o ), - .i2s_slave_ws_o ( i2s_slave_ws_o ), - .i2s_slave_ws_i ( i2s_slave_ws_i ), - .i2s_slave_ws_oe ( i2s_slave_ws_oe ), - .i2s_slave_sck_o ( i2s_slave_sck_o ), - .i2s_slave_sck_i ( i2s_slave_sck_i ), - .i2s_slave_sck_oe ( i2s_slave_sck_oe ), - - .spi_clk_i ( spi_clk_i ), - .spi_csn_i ( spi_csn_i ), - .spi_oen_i ( spi_oen_i ), - .spi_sdo_i ( spi_sdo_i ), - .spi_sdi_o ( spi_sdi_o ), - - .sdio_clk_i ( sdio_clk_i ), - .sdio_cmd_i ( sdio_cmd_i ), - .sdio_cmd_o ( sdio_cmd_o ), - .sdio_cmd_oen_i ( sdio_cmd_oen_i ), - .sdio_data_i ( sdio_data_i ), - .sdio_data_o ( sdio_data_o ), - .sdio_data_oen_i ( sdio_data_oen_i ), - - .cam_pclk_o ( cam_pclk_o ), - .cam_data_o ( cam_data_o ), - .cam_hsync_o ( cam_hsync_o ), - .cam_vsync_o ( cam_vsync_o ), - - .timer0_i ( timer0_i ), - .timer1_i ( timer1_i ), - .timer2_i ( timer2_i ), - .timer3_i ( timer3_i ), - - .out_spim_sdio0_o ( out_spim_sdio0_o ), - .out_spim_sdio1_o ( out_spim_sdio1_o ), - .out_spim_sdio2_o ( out_spim_sdio2_o ), - .out_spim_sdio3_o ( out_spim_sdio3_o ), - .out_spim_csn0_o ( out_spim_csn0_o ), - .out_spim_csn1_o ( out_spim_csn1_o ), - .out_spim_sck_o ( out_spim_sck_o ), - .out_sdio_clk_o ( out_sdio_clk_o ), - .out_sdio_cmd_o ( out_sdio_cmd_o ), - .out_sdio_data0_o ( out_sdio_data0_o ), - .out_sdio_data1_o ( out_sdio_data1_o ), - .out_sdio_data2_o ( out_sdio_data2_o ), - .out_sdio_data3_o ( out_sdio_data3_o ), - .out_uart_rx_o ( out_uart_rx_o ), - .out_uart_tx_o ( out_uart_tx_o ), - .out_cam_pclk_o ( out_cam_pclk_o ), - .out_cam_hsync_o ( out_cam_hsync_o ), - .out_cam_data0_o ( out_cam_data0_o ), - .out_cam_data1_o ( out_cam_data1_o ), - .out_cam_data2_o ( out_cam_data2_o ), - .out_cam_data3_o ( out_cam_data3_o ), - .out_cam_data4_o ( out_cam_data4_o ), - .out_cam_data5_o ( out_cam_data5_o ), - .out_cam_data6_o ( out_cam_data6_o ), - .out_cam_data7_o ( out_cam_data7_o ), - .out_cam_vsync_o ( out_cam_vsync_o ), - .out_i2c0_sda_o ( out_i2c0_sda_o ), - .out_i2c0_scl_o ( out_i2c0_scl_o ), - .out_i2s0_sck_o ( out_i2s0_sck_o ), - .out_i2s0_ws_o ( out_i2s0_ws_o ), - .out_i2s0_sdi_o ( out_i2s0_sdi_o ), - .out_i2s1_sdi_o ( out_i2s1_sdi_o ), - - .in_spim_sdio0_i ( in_spim_sdio0_i ), - .in_spim_sdio1_i ( in_spim_sdio1_i ), - .in_spim_sdio2_i ( in_spim_sdio2_i ), - .in_spim_sdio3_i ( in_spim_sdio3_i ), - .in_spim_csn0_i ( in_spim_csn0_i ), - .in_spim_csn1_i ( in_spim_csn1_i ), - .in_spim_sck_i ( in_spim_sck_i ), - .in_sdio_clk_i ( in_sdio_clk_i ), - .in_sdio_cmd_i ( in_sdio_cmd_i ), - .in_sdio_data0_i ( in_sdio_data0_i ), - .in_sdio_data1_i ( in_sdio_data1_i ), - .in_sdio_data2_i ( in_sdio_data2_i ), - .in_sdio_data3_i ( in_sdio_data3_i ), - .in_uart_rx_i ( in_uart_rx_i ), - .in_uart_tx_i ( in_uart_tx_i ), - .in_cam_pclk_i ( in_cam_pclk_i ), - .in_cam_hsync_i ( in_cam_hsync_i ), - .in_cam_data0_i ( in_cam_data0_i ), - .in_cam_data1_i ( in_cam_data1_i ), - .in_cam_data2_i ( in_cam_data2_i ), - .in_cam_data3_i ( in_cam_data3_i ), - .in_cam_data4_i ( in_cam_data4_i ), - .in_cam_data5_i ( in_cam_data5_i ), - .in_cam_data6_i ( in_cam_data6_i ), - .in_cam_data7_i ( in_cam_data7_i ), - .in_cam_vsync_i ( in_cam_vsync_i ), - .in_i2c0_sda_i ( in_i2c0_sda_i ), - .in_i2c0_scl_i ( in_i2c0_scl_i ), - .in_i2s0_sck_i ( in_i2s0_sck_i ), - .in_i2s0_ws_i ( in_i2s0_ws_i ), - .in_i2s0_sdi_i ( in_i2s0_sdi_i ), - .in_i2s1_sdi_i ( in_i2s1_sdi_i ), - - .oe_spim_sdio0_o ( oe_spim_sdio0_o ), - .oe_spim_sdio1_o ( oe_spim_sdio1_o ), - .oe_spim_sdio2_o ( oe_spim_sdio2_o ), - .oe_spim_sdio3_o ( oe_spim_sdio3_o ), - .oe_spim_csn0_o ( oe_spim_csn0_o ), - .oe_spim_csn1_o ( oe_spim_csn1_o ), - .oe_spim_sck_o ( oe_spim_sck_o ), - .oe_sdio_clk_o ( oe_sdio_clk_o ), - .oe_sdio_cmd_o ( oe_sdio_cmd_o ), - .oe_sdio_data0_o ( oe_sdio_data0_o ), - .oe_sdio_data1_o ( oe_sdio_data1_o ), - .oe_sdio_data2_o ( oe_sdio_data2_o ), - .oe_sdio_data3_o ( oe_sdio_data3_o ), - .oe_uart_rx_o ( oe_uart_rx_o ), - .oe_uart_tx_o ( oe_uart_tx_o ), - .oe_cam_pclk_o ( oe_cam_pclk_o ), - .oe_cam_hsync_o ( oe_cam_hsync_o ), - .oe_cam_data0_o ( oe_cam_data0_o ), - .oe_cam_data1_o ( oe_cam_data1_o ), - .oe_cam_data2_o ( oe_cam_data2_o ), - .oe_cam_data3_o ( oe_cam_data3_o ), - .oe_cam_data4_o ( oe_cam_data4_o ), - .oe_cam_data5_o ( oe_cam_data5_o ), - .oe_cam_data6_o ( oe_cam_data6_o ), - .oe_cam_data7_o ( oe_cam_data7_o ), - .oe_cam_vsync_o ( oe_cam_vsync_o ), - .oe_i2c0_sda_o ( oe_i2c0_sda_o ), - .oe_i2c0_scl_o ( oe_i2c0_scl_o ), - .oe_i2s0_sck_o ( oe_i2s0_sck_o ), - .oe_i2s0_ws_o ( oe_i2s0_ws_o ), - .oe_i2s0_sdi_o ( oe_i2s0_sdi_o ), - .oe_i2s1_sdi_o ( oe_i2s1_sdi_o ), - - .* - ); - - -`ifndef PULP_FPGA_EMUL - rstgen i_rstgen - ( - .clk_i ( ref_clk_i ), - .rst_ni ( s_rstn ), - .test_mode_i ( test_mode_o ), - .rst_no ( s_rstn_sync ), //to be used by logic clocked with ref clock in AO domain - .init_no ( ) //not used - ); - - assign slow_clk_o = ref_clk_i; - -`else - assign s_rstn_sync = s_rstn; - //Don't use the supplied clock directly for the FPGA target. On some boards - //the reference clock is a very fast (e.g. 200MHz) clock that cannot be used - //directly as the "slow_clk". Therefore we slow it down if a FPGA/board - //dependent module fpga_slow_clk_gen. Dividing the fast reference clock - //internally instead of doing so in the toplevel prevents unecessary clock - //division just to generate a faster clock once again in the SoC and - //Peripheral clock PLLs in soc_domain.sv. Instead all PLL use directly the - //board reference clock as input. - - fpga_slow_clk_gen i_slow_clk_gen - ( - .rst_ni(s_rstn_sync), - .ref_clk_i(ref_clk_i), - .slow_clk_o(slow_clk_o) - ); -`endif - - - assign s_rstn = rst_ni; - assign rst_no = s_rstn; - - assign test_clk_o = 1'b0; - assign dft_cg_enable_o = 1'b0; - assign test_mode_o = 1'b0; - assign mode_select_o = 1'b0; - - //******************************************************** - //*** PAD AND GPIO CONFIGURATION SIGNALS PACK ************ - //******************************************************** - - generate - for (i=0; i<32; i++) - begin : GEN_GPIO_CFG_I - for (j=0; j<6; j++) - begin : GEN_GPIO_CFG_J - assign s_gpio_cfg[i][j] = gpio_cfg_i[j+6*i]; - end - end - endgenerate - -endmodule // safe_domain diff --git a/rtl/pulpissimo/safe_domain_reg_if.sv b/rtl/pulpissimo/safe_domain_reg_if.sv deleted file mode 100644 index 0bb24b08..00000000 --- a/rtl/pulpissimo/safe_domain_reg_if.sv +++ /dev/null @@ -1,368 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - - -// NOTE: Safe regs will be mapped starting from BASEADDR+0x100. -// Have a look in apb_soc_ctrl for details (7th address bit is used -// to dispatch reg access req between safe_domain_reg_if and -// apb_soc_ctrl) - -// PMU REGISTERS -`define REG_RAR 6'b000000 //BASEADDR+0x100 -`define REG_SLEEP_CTRL 6'b000001 //BASEADDR+0x104 -`define REG_NOTUSED 6'b000010 //BASEADDR+0x108 -`define REG_PGCFG 6'b000011 //BASEADDR+0x10C - -// PAD MUXING - -`define REG_SLEEPPADCFG0 6'b010100 //BASEADDR+0x150 sets the pad sleep mode for pins 0 (bits [1:0]) to 15 (bits [31:30]) BITS 0 = OUTPUT ENABLE, BITS 1 = OUTPUT DATA -`define REG_SLEEPPADCFG1 6'b010101 //BASEADDR+0x154 sets the pad sleep mode for pins 16 (bits [1:0]) to 31 (bits [31:30]) BITS 0 = OUTPUT ENABLE, BITS 1 = OUTPUT DATA -`define REG_SLEEPPADCFG2 6'b010110 //BASEADDR+0x158 sets the pad sleep mode for pins 32 (bits [1:0]) to 47 (bits [31:30]) BITS 0 = OUTPUT ENABLE, BITS 1 = OUTPUT DATA -`define REG_SLEEPPADCFG3 6'b010111 //BASEADDR+0x15C sets the pad sleep mode for pins 48 (bits [1:0]) to 63 (bits [31:30]) BITS 0 = OUTPUT ENABLE, BITS 1 = OUTPUT DATA -`define REG_PADSLEEP 6'b011000 //BASEADDR+0x160 sets the pad sleep mode on (1= on, 0= off) - -`define REG_RTC_CLOCK 6'b110100 //BASEADDR+0x1D0 -`define REG_RTC_ALARM 6'b110101 //BASEADDR+0x1D4 -`define REG_RTC_TIMER 6'b110110 //BASEADDR+0x1D8 -`define REG_RTC_DATE 6'b110111 //BASEADDR+0x1DC - - -module safe_domain_reg_if - ( - input logic clk_i, - input logic rstn_i, - - output logic [11:0] cfg_mem_ret_o, - output logic [1:0] cfg_fll_ret_o, - - output logic [4:0] cfg_rar_nv_volt_o, - output logic [4:0] cfg_rar_mv_volt_o, - output logic [4:0] cfg_rar_lv_volt_o, - output logic [4:0] cfg_rar_rv_volt_o, - - output logic [1:0] cfg_wakeup_o, - - input logic [31:0] wake_gpio_i, - output logic wake_event_o, - - output logic boot_l2_o, - - output logic rtc_event_o, - - output logic pad_sleep_mode_o, - output logic [63:0][1:0] pad_sleep_cfg_o, - - input logic reg_if_req_i, - input logic reg_if_wrn_i, - input logic [5:0] reg_if_add_i, - input logic [31:0] reg_if_wdata_i, - output logic reg_if_ack_o, - output logic [31:0] reg_if_rdata_o, - - output logic [31:0] pmu_sleep_control_o - ); - - logic [4:0] r_rar_nv_volt; - logic [4:0] r_rar_mv_volt; - logic [4:0] r_rar_lv_volt; - logic [4:0] r_rar_rv_volt; - - logic [4:0] r_extwake_sel; - logic r_extwake_en; - logic [1:0] r_extwake_type; - logic r_extevent; - logic [2:0] r_extevent_sync; - logic [2:0] r_reboot; - - logic s_extwake_rise; - logic s_extwake_fall; - logic s_extwake_in; - - logic [1:0] r_wakeup; - logic r_cluster_wake; - - logic [13:0] r_cfg_ret; - - logic s_rise; - logic s_fall; - - logic [63:0] r_sleep_pad_cfg0; - logic [63:0] r_sleep_pad_cfg1; - logic r_pad_sleep; - - logic s_req_sync; - - logic r_boot_l2; - - logic [31:0] s_pmu_sleep_control; - - logic [21:0] s_rtc_clock; - logic [21:0] s_rtc_alarm; - logic [31:0] s_rtc_date; - logic [16:0] s_rtc_timer; - - logic s_rtc_date_select; - logic s_rtc_clock_select; - logic s_rtc_timer_select; - logic s_rtc_alarm_select; - - logic s_rtc_date_update; - logic s_rtc_clock_update; - logic s_rtc_timer_update; - logic s_rtc_alarm_update; - - logic s_rtc_update_day; - - - pulp_sync_wedge i_sync - ( - .clk_i(clk_i), - .rstn_i(rstn_i), - .en_i(1'b1), - .serial_i(reg_if_req_i), - .r_edge_o(s_rise), - .f_edge_o(s_fall), - .serial_o(s_req_sync) - ); - - assign cfg_rar_nv_volt_o = r_rar_nv_volt; - assign cfg_rar_mv_volt_o = r_rar_mv_volt; - assign cfg_rar_lv_volt_o = r_rar_lv_volt; - assign cfg_rar_rv_volt_o = r_rar_rv_volt; - - assign cfg_mem_ret_o = r_cfg_ret[11:0]; - assign cfg_fll_ret_o = r_cfg_ret[13:12]; - - assign wake_event_o = r_extevent; - assign cfg_wakeup_o = r_wakeup; - - assign boot_l2_o = r_boot_l2; - - always_ff @(posedge clk_i, negedge rstn_i) - begin - if(!rstn_i) - reg_if_ack_o <= 1'b0; - else if (s_rise) - reg_if_ack_o <= 1'b1; - else if (s_fall) - reg_if_ack_o <= 1'b0; - end - - assign s_extwake_in = wake_gpio_i[r_extwake_sel]; - assign s_extwake_rise = r_extevent_sync[1] & ~r_extevent_sync[0]; - assign s_extwake_fall = ~r_extevent_sync[1] & r_extevent_sync[0]; - - assign s_rtc_date_select = reg_if_add_i == `REG_RTC_DATE; - assign s_rtc_clock_select = reg_if_add_i == `REG_RTC_CLOCK; - assign s_rtc_timer_select = reg_if_add_i == `REG_RTC_TIMER; - assign s_rtc_alarm_select = reg_if_add_i == `REG_RTC_ALARM; - - assign s_rtc_date_update = s_rtc_date_select & (s_rise & ~reg_if_wrn_i); - assign s_rtc_alarm_update = s_rtc_alarm_select & (s_rise & ~reg_if_wrn_i); - assign s_rtc_clock_update = s_rtc_clock_select & (s_rise & ~reg_if_wrn_i); - assign s_rtc_timer_update = s_rtc_timer_select & (s_rise & ~reg_if_wrn_i); - - rtc_clock i_rtc_clock ( - .clk_i ( clk_i ), - .rstn_i ( rstn_i ), - .clock_update_i ( s_rtc_clock_update ), - .clock_o ( s_rtc_clock ), - .clock_i ( reg_if_wdata_i[21:0] ), - .init_sec_cnt_i ( reg_if_wdata_i[31:22] ), - .timer_update_i ( s_rtc_timer_update ), - .timer_enable_i ( reg_if_wdata_i[31] ), - .timer_retrig_i ( reg_if_wdata_i[30] ), - .timer_target_i ( reg_if_wdata_i[16:0] ), - .timer_value_o ( s_rtc_timer ), - .alarm_enable_i ( reg_if_wdata_i[31] ), - .alarm_update_i ( s_rtc_alarm_update ), - .alarm_clock_i ( reg_if_wdata_i[21:0] ), - .alarm_clock_o ( s_rtc_alarm ), - .event_o ( rtc_event_o ), - .update_day_o ( s_rtc_update_day ) - ); - - rtc_date i_rtc_date ( - .clk_i ( clk_i ), - .rstn_i ( rstn_i ), - .date_update_i ( s_rtc_date_update ), - .date_i ( reg_if_wdata_i[31:0] ), - .date_o ( s_rtc_date ), - .new_day_i ( s_rtc_update_day ) - ); - - always_ff @(posedge clk_i, negedge rstn_i) - begin - if(!rstn_i) - begin - r_cfg_ret <= 13'h0; - r_rar_nv_volt <= 5'h0D; //1.2V - r_rar_mv_volt <= 5'h09; //1.0V - r_rar_lv_volt <= 5'h09; //1.0V - r_rar_rv_volt <= 5'h05; //0.8V - r_sleep_pad_cfg0 <= '0; - r_sleep_pad_cfg1 <= '0; - r_pad_sleep <= '0; - r_extwake_sel <= '0; - r_extwake_en <= '0; - r_extwake_type <= '0; - r_extevent <= 0; - r_extevent_sync <= 0; - r_wakeup <= 0; - r_cluster_wake <= 1'b0; - r_boot_l2 <= 0; - r_reboot <= 2'b00; - end - else if (s_rise & ~reg_if_wrn_i) - begin - case(reg_if_add_i) - `REG_RAR: - begin - r_rar_nv_volt <= reg_if_wdata_i[4:0]; - r_rar_mv_volt <= reg_if_wdata_i[12:8]; - r_rar_lv_volt <= reg_if_wdata_i[20:16]; - r_rar_rv_volt <= reg_if_wdata_i[28:24]; - end - `REG_SLEEP_CTRL: - begin - r_cfg_ret[13:12] <= reg_if_wdata_i[1:0]; - r_cfg_ret[11] <= reg_if_wdata_i[2]; - r_extwake_sel <= reg_if_wdata_i[10:6]; - r_extwake_type <= reg_if_wdata_i[12:11]; - r_extwake_en <= reg_if_wdata_i[13]; - r_wakeup <= reg_if_wdata_i[15:14]; - r_boot_l2 <= reg_if_wdata_i[16]; - // pmu extint readonly [17] - r_reboot <= reg_if_wdata_i[19:18]; - r_cluster_wake <= reg_if_wdata_i[20]; - r_cfg_ret[10:0] <= reg_if_wdata_i[31:21]; - end - - `REG_SLEEPPADCFG0: - for (int i=0;i<16;i++) - begin - r_sleep_pad_cfg0[i] <= reg_if_wdata_i[i*2]; - r_sleep_pad_cfg1[i] <= reg_if_wdata_i[i*2+1]; - end - `REG_SLEEPPADCFG1: - for (int i=0;i<16;i++) - begin - r_sleep_pad_cfg0[16+i] <= reg_if_wdata_i[i*2]; - r_sleep_pad_cfg1[16+i] <= reg_if_wdata_i[i*2+1]; - end - `REG_SLEEPPADCFG2: - for (int i=0;i<16;i++) - begin - r_sleep_pad_cfg0[32+i] <= reg_if_wdata_i[i*2]; - r_sleep_pad_cfg1[32+i] <= reg_if_wdata_i[i*2+1]; - end - `REG_SLEEPPADCFG3: - for (int i=0;i<16;i++) - begin - r_sleep_pad_cfg0[48+i] <= reg_if_wdata_i[i*2]; - r_sleep_pad_cfg1[48+i] <= reg_if_wdata_i[i*2+1]; - end - - `REG_PADSLEEP: - begin - r_pad_sleep <= reg_if_wdata_i[0]; - end - - endcase - end - else if (s_rise & reg_if_wrn_i) - begin - case(reg_if_add_i) - `REG_SLEEP_CTRL: - begin - if (r_extevent) - r_extevent <= 1'b0; - end - endcase // reg_if_add_i - end - else - begin - if (r_extwake_en) - begin - r_extevent_sync <= {s_extwake_in,r_extevent_sync[2:1]}; - case(r_extwake_type) - 2'b00: - if(s_extwake_rise) r_extevent <= 1'b1; - 2'b01: - if(s_extwake_fall) r_extevent <= 1'b1; - 2'b10: - if(r_extevent_sync[0]) r_extevent <= 1'b1; - 2'b11: - if(!r_extevent_sync[0]) r_extevent <= 1'b1; - endcase // r_extwake_sel - end - end - end - - always_comb begin - case(reg_if_add_i) - `REG_RAR: - reg_if_rdata_o = {3'h0,r_rar_rv_volt,3'h0,r_rar_lv_volt,3'h0,r_rar_mv_volt,3'h0,r_rar_nv_volt}; - `REG_SLEEP_CTRL: - reg_if_rdata_o = s_pmu_sleep_control; - `REG_SLEEPPADCFG0: - for (int i=0;i<16;i++) - begin - reg_if_rdata_o[i*2] = r_sleep_pad_cfg0[i]; - reg_if_rdata_o[i*2+1] = r_sleep_pad_cfg1[i]; - end - `REG_SLEEPPADCFG1: - for (int i=0;i<16;i++) - begin - reg_if_rdata_o[i*2] = r_sleep_pad_cfg0[16+i]; - reg_if_rdata_o[i*2+1] = r_sleep_pad_cfg1[16+i]; - end - `REG_SLEEPPADCFG2: - for (int i=0;i<16;i++) - begin - reg_if_rdata_o[i*2] = r_sleep_pad_cfg0[32+i]; - reg_if_rdata_o[i*2+1] = r_sleep_pad_cfg1[32+i]; - end - `REG_SLEEPPADCFG3: - for (int i=0;i<16;i++) - begin - reg_if_rdata_o[i*2] = r_sleep_pad_cfg0[48+i]; - reg_if_rdata_o[i*2+1] = r_sleep_pad_cfg1[48+i]; - end - `REG_PADSLEEP: - reg_if_rdata_o = {31'h0,r_pad_sleep}; - `REG_RTC_DATE: - reg_if_rdata_o = s_rtc_date; - `REG_RTC_CLOCK: - reg_if_rdata_o = s_rtc_clock; - `REG_RTC_TIMER: - reg_if_rdata_o = s_rtc_timer; - `REG_RTC_ALARM: - reg_if_rdata_o = s_rtc_alarm; - default: - reg_if_rdata_o = 'h0; - endcase - end - - always_comb begin - for (int i=0;i<64;i++) - begin - pad_sleep_cfg_o[i][0] = r_sleep_pad_cfg0[i]; - pad_sleep_cfg_o[i][1] = r_sleep_pad_cfg1[i]; - end - end - - assign pad_sleep_mode_o = r_pad_sleep; - - assign s_pmu_sleep_control = {r_cfg_ret[10:0],r_cluster_wake,r_reboot,r_extevent,r_boot_l2,r_wakeup,r_extwake_en,r_extwake_type,r_extwake_sel,3'h0,r_cfg_ret[11],r_cfg_ret[13:12]}; - - assign pmu_sleep_control_o = s_pmu_sleep_control; - -endmodule // safe_domain_reg_if diff --git a/rtl/pulpissimo/soc_domain.sv b/rtl/pulpissimo/soc_domain.sv deleted file mode 100644 index 0117a626..00000000 --- a/rtl/pulpissimo/soc_domain.sv +++ /dev/null @@ -1,369 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -`include "pulp_soc_defines.sv" - -module soc_domain #( - parameter CORE_TYPE = 0, - parameter USE_FPU = 1, - parameter USE_ZFINX = 1, - parameter USE_HWPE = 1, - parameter USE_CLUSTER_EVENT = 1, - parameter SIM_STDOUT = 1, - parameter NB_CL_CORES = 8, - parameter AXI_ADDR_WIDTH = 32, - parameter AXI_DATA_IN_WIDTH = 64, - parameter AXI_DATA_OUT_WIDTH = 32, - parameter AXI_ID_IN_WIDTH = 4, - localparam AXI_ID_OUT_WIDTH = pkg_soc_interconnect::AXI_ID_OUT_WIDTH, //Must be large enough to accomodate the additional - //bits for the axi XBAR ($clog2(nr_master), rightnow - //we have 9 masters 5 for fc_data, fc_instr, udma_rx, - //udma_tx, debug_access and 4 for the 64-bit - //cluster2soc axi plug - parameter AXI_USER_WIDTH = 6, - parameter AXI_STRB_WIDTH_IN = AXI_DATA_IN_WIDTH/8, - parameter AXI_STRB_WIDTH_OUT = AXI_DATA_OUT_WIDTH/8, - - parameter EVNT_WIDTH = 8, - parameter CDC_FIFOS_LOG_DEPTH = 3, - - parameter int unsigned N_UART = 1, - parameter int unsigned N_SPI = 1, - parameter int unsigned N_I2C = 2, - localparam C2S_AW_WIDTH = AXI_ID_IN_WIDTH+AXI_ADDR_WIDTH+AXI_USER_WIDTH+$bits(axi_pkg::len_t)+$bits(axi_pkg::size_t)+$bits(axi_pkg::burst_t)+$bits(axi_pkg::cache_t)+$bits(axi_pkg::prot_t)+$bits(axi_pkg::qos_t)+$bits(axi_pkg::region_t)+$bits(axi_pkg::atop_t)+1, - localparam C2S_W_WIDTH = AXI_USER_WIDTH+AXI_STRB_WIDTH_IN+AXI_DATA_IN_WIDTH+1, - localparam C2S_R_WIDTH = AXI_ID_IN_WIDTH+AXI_DATA_IN_WIDTH+AXI_USER_WIDTH+$bits(axi_pkg::resp_t)+1, - localparam C2S_B_WIDTH = AXI_USER_WIDTH+AXI_ID_IN_WIDTH+$bits(axi_pkg::resp_t), - localparam C2S_AR_WIDTH = AXI_ID_IN_WIDTH+AXI_ADDR_WIDTH+AXI_USER_WIDTH+$bits(axi_pkg::len_t)+$bits(axi_pkg::size_t)+$bits(axi_pkg::burst_t)+$bits(axi_pkg::cache_t)+$bits(axi_pkg::prot_t)+$bits(axi_pkg::qos_t)+$bits(axi_pkg::region_t)+1, - localparam S2C_AW_WIDTH = AXI_ID_OUT_WIDTH+AXI_ADDR_WIDTH+AXI_USER_WIDTH+$bits(axi_pkg::len_t)+$bits(axi_pkg::size_t)+$bits(axi_pkg::burst_t)+$bits(axi_pkg::cache_t)+$bits(axi_pkg::prot_t)+$bits(axi_pkg::qos_t)+$bits(axi_pkg::region_t)+$bits(axi_pkg::atop_t)+1, - localparam S2C_W_WIDTH = AXI_USER_WIDTH+AXI_STRB_WIDTH_OUT+AXI_DATA_OUT_WIDTH+1, - localparam S2C_R_WIDTH = AXI_ID_OUT_WIDTH+AXI_DATA_OUT_WIDTH+AXI_USER_WIDTH+$bits(axi_pkg::resp_t)+1, - localparam S2C_B_WIDTH = AXI_USER_WIDTH+AXI_ID_OUT_WIDTH+$bits(axi_pkg::resp_t), - localparam S2C_AR_WIDTH = AXI_ID_OUT_WIDTH+AXI_ADDR_WIDTH+AXI_USER_WIDTH+$bits(axi_pkg::len_t)+$bits(axi_pkg::size_t)+$bits(axi_pkg::burst_t)+$bits(axi_pkg::cache_t)+$bits(axi_pkg::prot_t)+$bits(axi_pkg::qos_t)+$bits(axi_pkg::region_t)+1 -)( - - input logic ref_clk_i, - input logic slow_clk_i, - input logic test_clk_i, - - input logic rstn_glob_i, - - input logic dft_test_mode_i, - input logic dft_cg_enable_i, - - input logic mode_select_i, - - input logic [1:0] bootsel_i, - - input logic fc_fetch_en_valid_i, - input logic fc_fetch_en_i, - - input logic jtag_tck_i, - input logic jtag_trst_ni, - input logic jtag_tms_i, - input logic jtag_tdi_i, - output logic jtag_tdo_o, - - output logic [NB_CL_CORES-1:0] cluster_dbg_irq_valid_o, - - input logic [31:0] gpio_in_i, - output logic [31:0] gpio_out_o, - output logic [31:0] gpio_dir_o, - output logic [191:0] gpio_cfg_o, - - output logic [127:0] pad_mux_o, - output logic [383:0] pad_cfg_o, - - output logic uart_tx_o, - input logic uart_rx_i, - - input logic cam_clk_i, - input logic [7:0] cam_data_i, - input logic cam_hsync_i, - input logic cam_vsync_i, - - output logic [3:0] timer_ch0_o, - output logic [3:0] timer_ch1_o, - output logic [3:0] timer_ch2_o, - output logic [3:0] timer_ch3_o, - - input logic [N_I2C-1:0] i2c_scl_i, - output logic [N_I2C-1:0] i2c_scl_o, - output logic [N_I2C-1:0] i2c_scl_oe_o, - input logic [N_I2C-1:0] i2c_sda_i, - output logic [N_I2C-1:0] i2c_sda_o, - output logic [N_I2C-1:0] i2c_sda_oe_o, - - input logic i2s_slave_sd0_i, - input logic i2s_slave_sd1_i, - input logic i2s_slave_ws_i, - output logic i2s_slave_ws_o, - output logic i2s_slave_ws_oe, - input logic i2s_slave_sck_i, - output logic i2s_slave_sck_o, - output logic i2s_slave_sck_oe, - - output logic [N_SPI-1:0] spi_clk_o, - output logic [N_SPI-1:0][3:0] spi_csn_o, - output logic [N_SPI-1:0][3:0] spi_oen_o, - output logic [N_SPI-1:0][3:0] spi_sdo_o, - input logic [N_SPI-1:0][3:0] spi_sdi_i, - - output logic sdio_clk_o, - output logic sdio_cmd_o, - input logic sdio_cmd_i, - output logic sdio_cmd_oen_o, - output logic [3:0] sdio_data_o, - input logic [3:0] sdio_data_i, - output logic [3:0] sdio_data_oen_o, - - output logic [1:0] hyper_cs_no, - output logic hyper_ck_o, - output logic hyper_ck_no, - output logic [1:0] hyper_rwds_o, - input logic hyper_rwds_i, - output logic [1:0] hyper_rwds_oe_o, - input logic [15:0] hyper_dq_i, - output logic [15:0] hyper_dq_o, - output logic [1:0] hyper_dq_oe_o, - output logic hyper_reset_no, - - // CLUSTER - output logic cluster_clk_o, - output logic cluster_rstn_o, - input logic cluster_busy_i, - output logic cluster_irq_o, - - output logic cluster_rtc_o, - output logic cluster_fetch_enable_o, - output logic [63:0] cluster_boot_addr_o, - output logic cluster_test_en_o, - output logic cluster_pow_o, - output logic cluster_byp_o, - // AXI4 SLAVE - input logic [CDC_FIFOS_LOG_DEPTH:0] async_data_slave_aw_wptr_i, - input logic [2**CDC_FIFOS_LOG_DEPTH-1:0][C2S_AW_WIDTH-1:0] async_data_slave_aw_data_i, - output logic [CDC_FIFOS_LOG_DEPTH:0] async_data_slave_aw_rptr_o, - - // READ ADDRESS CHANNEL - input logic [CDC_FIFOS_LOG_DEPTH:0] async_data_slave_ar_wptr_i, - input logic [2**CDC_FIFOS_LOG_DEPTH-1:0][C2S_AR_WIDTH-1:0] async_data_slave_ar_data_i, - output logic [CDC_FIFOS_LOG_DEPTH:0] async_data_slave_ar_rptr_o, - - // WRITE DATA CHANNEL - input logic [CDC_FIFOS_LOG_DEPTH:0] async_data_slave_w_wptr_i, - input logic [2**CDC_FIFOS_LOG_DEPTH-1:0][C2S_W_WIDTH-1:0] async_data_slave_w_data_i, - output logic [CDC_FIFOS_LOG_DEPTH:0] async_data_slave_w_rptr_o, - - // READ DATA CHANNEL - output logic [CDC_FIFOS_LOG_DEPTH:0] async_data_slave_r_wptr_o, - output logic [2**CDC_FIFOS_LOG_DEPTH-1:0][C2S_R_WIDTH-1:0] async_data_slave_r_data_o, - input logic [CDC_FIFOS_LOG_DEPTH:0] async_data_slave_r_rptr_i, - - // WRITE RESPONSE CHANNEL - output logic [CDC_FIFOS_LOG_DEPTH:0] async_data_slave_b_wptr_o, - output logic [2**CDC_FIFOS_LOG_DEPTH-1:0][C2S_B_WIDTH-1:0] async_data_slave_b_data_o, - input logic [CDC_FIFOS_LOG_DEPTH:0] async_data_slave_b_rptr_i, - - // AXI4 MASTER - output logic [CDC_FIFOS_LOG_DEPTH:0] async_data_master_aw_wptr_o, - output logic [2**CDC_FIFOS_LOG_DEPTH-1:0][S2C_AW_WIDTH-1:0] async_data_master_aw_data_o, - input logic [CDC_FIFOS_LOG_DEPTH:0] async_data_master_aw_rptr_i, - - // READ ADDRESS CHANNEL - output logic [CDC_FIFOS_LOG_DEPTH:0] async_data_master_ar_wptr_o, - output logic [2**CDC_FIFOS_LOG_DEPTH-1:0][S2C_AR_WIDTH-1:0] async_data_master_ar_data_o, - input logic [CDC_FIFOS_LOG_DEPTH:0] async_data_master_ar_rptr_i, - - // WRITE DATA CHANNEL - output logic [CDC_FIFOS_LOG_DEPTH:0] async_data_master_w_wptr_o, - output logic [2**CDC_FIFOS_LOG_DEPTH-1:0][S2C_W_WIDTH-1:0] async_data_master_w_data_o, - input logic [CDC_FIFOS_LOG_DEPTH:0] async_data_master_w_rptr_i, - - // READ DATA CHANNEL - input logic [CDC_FIFOS_LOG_DEPTH:0] async_data_master_r_wptr_i, - input logic [2**CDC_FIFOS_LOG_DEPTH-1:0][S2C_R_WIDTH-1:0] async_data_master_r_data_i, - output logic [CDC_FIFOS_LOG_DEPTH:0] async_data_master_r_rptr_o, - - // WRITE RESPONSE CHANNEL - input logic [CDC_FIFOS_LOG_DEPTH:0] async_data_master_b_wptr_i, - input logic [2**CDC_FIFOS_LOG_DEPTH-1:0][S2C_B_WIDTH-1:0] async_data_master_b_data_i, - output logic [CDC_FIFOS_LOG_DEPTH:0] async_data_master_b_rptr_o, - - // EVENT BUS - output logic [CDC_FIFOS_LOG_DEPTH:0] async_cluster_events_wptr_o, - input logic [CDC_FIFOS_LOG_DEPTH:0] async_cluster_events_rptr_i, - output logic [EVNT_WIDTH-1:0][2**CDC_FIFOS_LOG_DEPTH-1:0] async_cluster_events_data_o, - - output logic dma_pe_evt_ack_o, - input logic dma_pe_evt_valid_i, - - output logic dma_pe_irq_ack_o, - input logic dma_pe_irq_valid_i, - - output logic pf_evt_ack_o, - input logic pf_evt_valid_i - - /*AUTOINOUT*/ -); - - - pulp_soc #( - .CORE_TYPE ( CORE_TYPE ), - .USE_FPU ( USE_FPU ), - .USE_HWPE ( USE_HWPE ), - .USE_CLUSTER_EVENT ( USE_CLUSTER_EVENT ), - .SIM_STDOUT ( SIM_STDOUT ), - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_IN_WIDTH ( AXI_DATA_IN_WIDTH ), - .AXI_DATA_OUT_WIDTH ( AXI_DATA_OUT_WIDTH ), - .AXI_ID_IN_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ), - .AXI_STRB_WIDTH_IN ( AXI_STRB_WIDTH_IN ), - .AXI_STRB_WIDTH_OUT ( AXI_STRB_WIDTH_OUT ), - .CDC_FIFOS_LOG_DEPTH ( CDC_FIFOS_LOG_DEPTH ), - .EVNT_WIDTH ( EVNT_WIDTH ), - .NB_CORES ( NB_CL_CORES ), - .NGPIO ( 32 ), - .NPAD ( 64 ), - .NBIT_PADCFG ( 6 ), - .NBIT_PADMUX ( 2 ), - .N_UART ( N_UART ), - .N_SPI ( N_SPI ), - .N_I2C ( N_I2C ), - .USE_ZFINX ( USE_ZFINX ) - ) pulp_soc_i ( - .ref_clk_i, - .slow_clk_i, - .test_clk_i, - .rstn_glob_i, - .dft_test_mode_i, - .dft_cg_enable_i, - .mode_select_i, - .boot_l2_i(1'b0), - .bootsel_i, - .fc_fetch_en_valid_i, - .fc_fetch_en_i, - .cluster_rtc_o, - .cluster_fetch_enable_o, - .cluster_boot_addr_o, - .cluster_test_en_o, - .cluster_pow_o, - .cluster_byp_o, - .cluster_rstn_o, - .cluster_irq_o, - .async_data_slave_aw_wptr_i, - .async_data_slave_aw_data_i, - .async_data_slave_aw_rptr_o, - .async_data_slave_ar_wptr_i, - .async_data_slave_ar_data_i, - .async_data_slave_ar_rptr_o, - .async_data_slave_w_wptr_i, - .async_data_slave_w_data_i, - .async_data_slave_w_rptr_o, - .async_data_slave_r_wptr_o, - .async_data_slave_r_data_o, - .async_data_slave_r_rptr_i, - .async_data_slave_b_wptr_o, - .async_data_slave_b_data_o, - .async_data_slave_b_rptr_i, - .async_data_master_aw_wptr_o, - .async_data_master_aw_data_o, - .async_data_master_aw_rptr_i, - .async_data_master_ar_wptr_o, - .async_data_master_ar_data_o, - .async_data_master_ar_rptr_i, - .async_data_master_w_wptr_o, - .async_data_master_w_data_o, - .async_data_master_w_rptr_i, - .async_data_master_r_wptr_i, - .async_data_master_r_data_i, - .async_data_master_r_rptr_o, - .async_data_master_b_wptr_i, - .async_data_master_b_data_i, - .async_data_master_b_rptr_o, - .async_cluster_events_wptr_o, - .async_cluster_events_rptr_i, - .async_cluster_events_data_o, - .cluster_clk_o, - .cluster_busy_i, - .dma_pe_evt_ack_o, - .dma_pe_evt_valid_i, - .dma_pe_irq_ack_o, - .dma_pe_irq_valid_i, - .pf_evt_ack_o, - .pf_evt_valid_i, - .pad_mux_o, - .pad_cfg_o, - .gpio_in_i, - .gpio_out_o, - .gpio_dir_o, - .gpio_cfg_o, - .uart_tx_o, - .uart_rx_i, - .cam_clk_i, - .cam_data_i, - .cam_hsync_i, - .cam_vsync_i, - .timer_ch0_o, - .timer_ch1_o, - .timer_ch2_o, - .timer_ch3_o, - - .i2c_scl_i, - .i2c_scl_o, - .i2c_scl_oe_o, - .i2c_sda_i, - .i2c_sda_o, - .i2c_sda_oe_o, - - .i2s_slave_sd0_i, - .i2s_slave_sd1_i, - .i2s_slave_ws_i, - .i2s_slave_ws_o, - .i2s_slave_ws_oe, - .i2s_slave_sck_i, - .i2s_slave_sck_o, - .i2s_slave_sck_oe, - - .spi_clk_o, - .spi_csn_o, - .spi_oen_o, - .spi_sdo_o, - .spi_sdi_i, - - .sdio_clk_o, - .sdio_cmd_o, - .sdio_cmd_i, - .sdio_cmd_oen_o, - .sdio_data_o, - .sdio_data_i, - .sdio_data_oen_o, - - .hyper_cs_no, - .hyper_ck_o, - .hyper_ck_no, - .hyper_rwds_o, - .hyper_rwds_i, - .hyper_rwds_oe_o, - .hyper_dq_i, - .hyper_dq_o, - .hyper_dq_oe_o, - .hyper_reset_no, - - .jtag_tck_i, - .jtag_trst_ni, - .jtag_tms_i, - .jtag_tdi_i, - .jtag_tdo_o, - .cluster_dbg_irq_valid_o - ); - -endmodule diff --git a/rtl/pulpissimo/src_files.yml b/rtl/pulpissimo/src_files.yml deleted file mode 100644 index 3dc6720a..00000000 --- a/rtl/pulpissimo/src_files.yml +++ /dev/null @@ -1,18 +0,0 @@ -pulpissimo: - incdirs: [ - ../includes, - ] - files: [ - jtag_tap_top.sv, - pad_control.sv, - pad_frame.sv, - safe_domain.sv, - soc_domain.sv, - rtc_date.sv, - rtc_clock.sv, - pulpissimo.sv, - ] - vlog_opts: [ - -L pulp_soc_lib, - -L axi_lib - ] diff --git a/rtl/tb/dpi_models b/rtl/tb/dpi_models deleted file mode 120000 index 222d3cb5..00000000 --- a/rtl/tb/dpi_models +++ /dev/null @@ -1 +0,0 @@ -../../ips/tbtools/dpi_models/ \ No newline at end of file diff --git a/rtl/tb/src_files.yml b/rtl/tb/src_files.yml deleted file mode 100644 index f113aff5..00000000 --- a/rtl/tb/src_files.yml +++ /dev/null @@ -1,23 +0,0 @@ -tb: - targets: [ - rtl - ] - files: [ - riscv_pkg.sv, - jtag_pkg.sv, - pulp_tap_pkg.sv, - srec/srec_pkg.sv, - tb_clk_gen.sv, - tb_fs_handler.sv, - dpi_models/dpi_models.sv, - tb_driver/tb_driver.sv, - tb_pulp.sv, - SimJTAG.sv, - SimDTM.sv, - ] - vlog_opts : [ - -L riscv_dbg_lib, - ] - flags: [ - skip_synthesis - ] diff --git a/rtl/tb/tb_driver b/rtl/tb/tb_driver deleted file mode 120000 index f020b036..00000000 --- a/rtl/tb/tb_driver +++ /dev/null @@ -1 +0,0 @@ -../../ips/tbtools/tb_driver/ \ No newline at end of file diff --git a/rtl/vip/src_files.yml b/rtl/vip/src_files.yml deleted file mode 100644 index 39fe5a7e..00000000 --- a/rtl/vip/src_files.yml +++ /dev/null @@ -1,45 +0,0 @@ -S25FS256_model: - defines: [ - SPEEDSIM, - ] - files: [ - spi_flash/S25fs256s/model/s25fs256s.v, - ] - flags: [ - skip_synthesis, - ] - -24FC1025_model: - defines: [ - SPEEDSIM, - ] - files: [ - i2c_eeprom/24FC1025.v, - ] - flags: [ - skip_synthesis, - ] - -i2s_model: - defines: [ - SPEEDSIM, - ] - files: [ - i2s/i2c_if.v, - i2s/i2s_vip_channel.sv, - i2s/i2s_vip.sv, - ] - flags: [ - skip_synthesis, - ] - -open_models: - files: [ - spi_master_padframe.sv, - uart_sim.sv, - camera/cam_vip.sv - ] - flags: [ - skip_synthesis, - ] - diff --git a/sdk-releases/get-sdk-2019.06.06-CentOS_7.py b/sdk-releases/get-sdk-2019.06.06-CentOS_7.py deleted file mode 100755 index e3f4c8c5..00000000 --- a/sdk-releases/get-sdk-2019.06.06-CentOS_7.py +++ /dev/null @@ -1,118 +0,0 @@ -#!/usr/bin/env python3 - -# This file has been auto-generated and can be used for downloading the SDK it has -# been generated for. - -import os -import tarfile -import os.path -import argparse - - -src="59b44701b6ac8390a97936cbd049256fc2917212" - -artefacts=[ - ["https://iis-artifactory.ee.ethz.ch/artifactory/release/CentOS_7/pulp/sdk/mainstream/ece475907719cc96278ee907e48c2b801994a75f/0/sdk.tar.bz2", "pkg/sdk/2019.06.06"], - ["https://iis-artifactory.ee.ethz.ch/artifactory/release/CentOS_7/pulp/pulp_riscv_gcc/mainstream/1.0.13/0/pulp_riscv_gcc.tar.bz2", "pkg/pulp_riscv_gcc/1.0.13"] -] - -exports=[ - ["PULP_SDK_HOME", "$PULP_PROJECT_HOME/pkg/sdk/2019.06.06"], - ["PULP_SDK_INSTALL", "$PULP_SDK_HOME/install"], - ["PULP_SDK_WS_INSTALL", "$PULP_SDK_HOME/install/ws"], - ["PULP_RISCV_GCC_TOOLCHAIN_CI", "$PULP_PROJECT_HOME/pkg/pulp_riscv_gcc/1.0.13"], - ["CROSS_COMPILE", "$PULP_PROJECT_HOME/pkg/pulp_riscv_gcc/1.0.13/bin/riscv32-unknown-elf-"], - ["PULP_RISCV_GCC_VERSION", "3"], - ["ZEPHYR_GCC_VARIANT", "cross-compile"] -] - -sourceme=[ - ["$PULP_SDK_HOME/env/setup.sh", "$PULP_SDK_HOME/env/setup.csh"] -] - -pkg=["sdk", "2019.06.06"] - -parser = argparse.ArgumentParser(description='PULP downloader') - -parser.add_argument('command', metavar='CMD', type=str, nargs='*', - help='a command to be execute') - -parser.add_argument("--path", dest="path", default=None, help="Specify path where to install packages and sources") - -args = parser.parse_args() - -if len(args.command ) == 0: - args.command = ['get'] - -if args.path != None: - path = os.path.expanduser(args.path) - if not os.path.exists(path): - os.makedirs(path) - os.chdir(path) - -for command in args.command: - - if command == 'get' or command == 'download': - - dir = os.getcwd() - - if command == 'get': - if not os.path.exists('pkg'): os.makedirs('pkg') - - os.chdir('pkg') - - for artefactDesc in artefacts: - artefact = artefactDesc[0] - path = os.path.join(dir, artefactDesc[1]) - urlList = artefact.split('/') - fileName = urlList[len(urlList)-1] - - if command == 'download' or not os.path.exists(path): - - if os.path.exists(fileName): - os.remove(fileName) - - if os.system('wget --no-check-certificate %s' % (artefact)) != 0: - exit(-1) - - if command == 'get': - os.makedirs(path) - t = tarfile.open(os.path.basename(artefact), 'r') - t.extractall(path) - os.remove(os.path.basename(artefact)) - - os.chdir(dir) - - if command == 'get' or command == 'download' or command == 'env': - - if not os.path.exists('env'): - os.makedirs('env') - - filePath = 'env/env-%s-%s.sh' % (pkg[0], pkg[1]) - with open(filePath, 'w') as envFile: - #envFile.write('export PULP_ENV_FILE_PATH=%s\n' % os.path.join(os.getcwd(), filePath)) - #envFile.write('export PULP_SDK_SRC_PATH=%s\n' % os.environ.get("PULP_SDK_SRC_PATH")) - envFile.write('export %s=%s\n' % ('PULP_PROJECT_HOME', os.getcwd())) - for export in exports: - envFile.write('export %s=%s\n' % (export[0], export[1].replace('$PULP_PROJECT_HOME', os.getcwd()))) - for env in sourceme: - envFile.write('source %s\n' % (env[0].replace('$PULP_PROJECT_HOME', os.getcwd()))) - #envFile.write('if [ -e "$PULP_SDK_SRC_PATH/init.sh" ]; then source $PULP_SDK_SRC_PATH/init.sh; fi') - - #filePath = 'env/env-%s-%s.csh' % (pkg[0], pkg[1]) - #with open(filePath, 'w') as envFile: - # envFile.write('setenv PULP_ENV_FILE_PATH %s\n' % os.path.join(os.getcwd(), filePath)) - # envFile.write('setenv PULP_SDK_SRC_PATH %s\n' % os.environ.get("PULP_SDK_SRC_PATH")) - # for env in envFileStrCsh: - # envFile.write('%s\n' % (env.replace('@PULP_PKG_HOME@', os.getcwd()))) - # envFile.write('if ( -e "$PULP_SDK_SRC_PATH/init.sh" ) then source $PULP_SDK_SRC_PATH/init.sh; endif') - - if command == 'src': - - if os.path.exists('.git'): - os.system('git checkout %s' % (src)) - else: - os.system('git init .') - os.system('git remote add -t \* -f origin git@kesch.ee.ethz.ch:pulp-sw/pulp_pipeline.git') - os.system('git checkout %s' % (src)) - diff --git a/sdk-releases/get-sdk-2019.07.01-CentOS_7.py b/sdk-releases/get-sdk-2019.07.01-CentOS_7.py deleted file mode 100755 index a6585524..00000000 --- a/sdk-releases/get-sdk-2019.07.01-CentOS_7.py +++ /dev/null @@ -1,124 +0,0 @@ -#!/usr/bin/env python3 - -# This file has been auto-generated and can be used for downloading the SDK it has -# been generated for. - -import os -import tarfile -import os.path -import argparse - - -src="59b44701b6ac8390a97936cbd049256fc2917212" - -artefacts=[ - ["https://iis-artifactory.ee.ethz.ch/artifactory/release/CentOS_7/pulp/sdk/mainstream/5ca4920d55968ca2797d85a33aee62adf3663fd0/0/sdk.tar.bz2", "pkg/sdk/2019.07.01"], - ["https://iis-artifactory.ee.ethz.ch/artifactory/release/CentOS_7/pulp/pulp_riscv_gcc/mainstream/1.0.13/0/pulp_riscv_gcc.tar.bz2", "pkg/pulp_riscv_gcc/1.0.13"], - ["https://iis-artifactory.ee.ethz.ch/artifactory/release/pulp/gap/mainstream/1.3/0/gap.tar.bz2", "pkg/rtl/gap/1.3"] -] - -exports=[ - ["PULP_SDK_HOME", "$PULP_PROJECT_HOME/pkg/sdk/2019.07.01"], - ["PULP_SDK_INSTALL", "$PULP_SDK_HOME/install"], - ["PULP_SDK_WS_INSTALL", "$PULP_SDK_HOME/install/ws"], - ["PULP_RISCV_GCC_TOOLCHAIN_CI", "$PULP_PROJECT_HOME/pkg/pulp_riscv_gcc/1.0.13"], - ["CROSS_COMPILE", "$PULP_PROJECT_HOME/pkg/pulp_riscv_gcc/1.0.13/bin/riscv32-unknown-elf-"], - ["PULP_RISCV_GCC_VERSION", "3"], - ["ZEPHYR_GCC_VARIANT", "cross-compile"], - ["PULP_RTL_GAP", "$PULP_PROJECT_HOME/pkg/rtl/gap/1.3"] -] - -sourceme=[ - ["$PULP_SDK_HOME/env/setup.sh", "$PULP_SDK_HOME/env/setup.csh"] -] - -pkg=["sdk", "2019.07.01"] - -parser = argparse.ArgumentParser(description='PULP downloader') - -parser.add_argument('command', metavar='CMD', type=str, nargs='*', - help='a command to be execute') - -parser.add_argument("--path", dest="path", default=None, help="Specify path where to install packages and sources") - -args = parser.parse_args() - -if len(args.command ) == 0: - args.command = ['get'] - -if args.path != None: - path = os.path.expanduser(args.path) - if not os.path.exists(path): - os.makedirs(path) - os.chdir(path) - -for command in args.command: - - if command == 'get' or command == 'download': - - dir = os.getcwd() - - if command == 'get': - if not os.path.exists('pkg'): os.makedirs('pkg') - - os.chdir('pkg') - - for artefactDesc in artefacts: - artefact = artefactDesc[0] - path = os.path.join(dir, artefactDesc[1]) - urlList = artefact.split('/') - fileName = urlList[len(urlList)-1] - - if command == 'download' or not os.path.exists(path): - - if os.path.exists(fileName): - os.remove(fileName) - - print('ARTIFACTORY DUMP') - artifactory_user = os.environ['ARTIFACTORY_USER'] - artifactory_pw = os.environ['ARTIFACTORY_PASSWORD'] - - if os.system('wget -nv --timeout=2 --user %s --password %s --no-check-certificate %s' % (artifactory_user, artifactory_pw, artefact)) != 0: - exit(-1) - - if command == 'get': - os.makedirs(path) - t = tarfile.open(os.path.basename(artefact), 'r') - t.extractall(path) - os.remove(os.path.basename(artefact)) - - os.chdir(dir) - - if command == 'get' or command == 'download' or command == 'env': - - if not os.path.exists('env'): - os.makedirs('env') - - filePath = 'env/env-%s-%s.sh' % (pkg[0], pkg[1]) - with open(filePath, 'w') as envFile: - #envFile.write('export PULP_ENV_FILE_PATH=%s\n' % os.path.join(os.getcwd(), filePath)) - #envFile.write('export PULP_SDK_SRC_PATH=%s\n' % os.environ.get("PULP_SDK_SRC_PATH")) - envFile.write('export %s=%s\n' % ('PULP_PROJECT_HOME', os.getcwd())) - for export in exports: - envFile.write('export %s=%s\n' % (export[0], export[1].replace('$PULP_PROJECT_HOME', os.getcwd()))) - for env in sourceme: - envFile.write('source %s\n' % (env[0].replace('$PULP_PROJECT_HOME', os.getcwd()))) - #envFile.write('if [ -e "$PULP_SDK_SRC_PATH/init.sh" ]; then source $PULP_SDK_SRC_PATH/init.sh; fi') - - #filePath = 'env/env-%s-%s.csh' % (pkg[0], pkg[1]) - #with open(filePath, 'w') as envFile: - # envFile.write('setenv PULP_ENV_FILE_PATH %s\n' % os.path.join(os.getcwd(), filePath)) - # envFile.write('setenv PULP_SDK_SRC_PATH %s\n' % os.environ.get("PULP_SDK_SRC_PATH")) - # for env in envFileStrCsh: - # envFile.write('%s\n' % (env.replace('@PULP_PKG_HOME@', os.getcwd()))) - # envFile.write('if ( -e "$PULP_SDK_SRC_PATH/init.sh" ) then source $PULP_SDK_SRC_PATH/init.sh; endif') - - if command == 'src': - - if os.path.exists('.git'): - os.system('git checkout %s' % (src)) - else: - os.system('git init .') - os.system('git remote add -t \* -f origin git@kesch.ee.ethz.ch:pulp-sw/pulp_pipeline.git') - os.system('git checkout %s' % (src)) - diff --git a/sdk-releases/get-sdk-2019.10.02-CentOS_7.py b/sdk-releases/get-sdk-2019.10.02-CentOS_7.py deleted file mode 100755 index c5e7de13..00000000 --- a/sdk-releases/get-sdk-2019.10.02-CentOS_7.py +++ /dev/null @@ -1,121 +0,0 @@ -#!/usr/bin/env python3 - -# This file has been auto-generated and can be used for downloading the SDK it has -# been generated for. - -import os -import tarfile -import os.path -import argparse - - -src="59b44701b6ac8390a97936cbd049256fc2917212" - -artefacts=[ - ["https://iis-artifactory.ee.ethz.ch/artifactory/release/CentOS_7/pulp/sdk/mainstream/df5e21e69b569cb0956e281b9571a5d4a5db000e/0/sdk.tar.bz2", "pkg/sdk/2019.10.02"], - ["https://iis-artifactory.ee.ethz.ch/artifactory/release/CentOS_7/pulp/pulp_riscv_gcc/mainstream/1.0.14/0/pulp_riscv_gcc.tar.bz2", "pkg/pulp_riscv_gcc/1.0.14"] -] - -exports=[ - ["PULP_SDK_HOME", "$PULP_PROJECT_HOME/pkg/sdk/2019.10.02"], - ["PULP_SDK_INSTALL", "$PULP_SDK_HOME/install"], - ["PULP_SDK_WS_INSTALL", "$PULP_SDK_HOME/install/ws"], - ["PULP_RISCV_GCC_TOOLCHAIN_CI", "$PULP_PROJECT_HOME/pkg/pulp_riscv_gcc/1.0.14"], - ["CROSS_COMPILE", "$PULP_PROJECT_HOME/pkg/pulp_riscv_gcc/1.0.14/bin/riscv32-unknown-elf-"], - ["PULP_RISCV_GCC_VERSION", "3"], - ["ZEPHYR_GCC_VARIANT", "cross-compile"] -] - -sourceme=[ - ["$PULP_SDK_HOME/env/setup.sh", "$PULP_SDK_HOME/env/setup.csh"] -] - -pkg=["sdk", "2019.10.02"] - -parser = argparse.ArgumentParser(description='PULP downloader') - -parser.add_argument('command', metavar='CMD', type=str, nargs='*', - help='a command to be execute') - -parser.add_argument("--path", dest="path", default=None, help="Specify path where to install packages and sources") - -args = parser.parse_args() - -if len(args.command ) == 0: - args.command = ['get'] - -if args.path != None: - path = os.path.expanduser(args.path) - if not os.path.exists(path): - os.makedirs(path) - os.chdir(path) - -for command in args.command: - - if command == 'get' or command == 'download': - - dir = os.getcwd() - - if command == 'get': - if not os.path.exists('pkg'): os.makedirs('pkg') - - os.chdir('pkg') - - for artefactDesc in artefacts: - artefact = artefactDesc[0] - path = os.path.join(dir, artefactDesc[1]) - urlList = artefact.split('/') - fileName = urlList[len(urlList)-1] - - if command == 'download' or not os.path.exists(path): - - if os.path.exists(fileName): - os.remove(fileName) - - artifactory_user = os.environ['ARTIFACTORY_USER'] - artifactory_pw = os.environ['ARTIFACTORY_PASSWORD'] - - if os.system('wget -nv --timeout=2 --user %s --password %s --no-check-certificate %s' % (artifactory_user, artifactory_pw, artefact)) != 0: - exit(-1) - - if command == 'get': - os.makedirs(path) - t = tarfile.open(os.path.basename(artefact), 'r') - t.extractall(path) - os.remove(os.path.basename(artefact)) - - os.chdir(dir) - - if command == 'get' or command == 'download' or command == 'env': - - if not os.path.exists('env'): - os.makedirs('env') - - filePath = 'env/env-%s-%s.sh' % (pkg[0], pkg[1]) - with open(filePath, 'w') as envFile: - #envFile.write('export PULP_ENV_FILE_PATH=%s\n' % os.path.join(os.getcwd(), filePath)) - #envFile.write('export PULP_SDK_SRC_PATH=%s\n' % os.environ.get("PULP_SDK_SRC_PATH")) - envFile.write('export %s=%s\n' % ('PULP_PROJECT_HOME', os.getcwd())) - for export in exports: - envFile.write('export %s=%s\n' % (export[0], export[1].replace('$PULP_PROJECT_HOME', os.getcwd()))) - for env in sourceme: - envFile.write('source %s\n' % (env[0].replace('$PULP_PROJECT_HOME', os.getcwd()))) - #envFile.write('if [ -e "$PULP_SDK_SRC_PATH/init.sh" ]; then source $PULP_SDK_SRC_PATH/init.sh; fi') - - #filePath = 'env/env-%s-%s.csh' % (pkg[0], pkg[1]) - #with open(filePath, 'w') as envFile: - # envFile.write('setenv PULP_ENV_FILE_PATH %s\n' % os.path.join(os.getcwd(), filePath)) - # envFile.write('setenv PULP_SDK_SRC_PATH %s\n' % os.environ.get("PULP_SDK_SRC_PATH")) - # for env in envFileStrCsh: - # envFile.write('%s\n' % (env.replace('@PULP_PKG_HOME@', os.getcwd()))) - # envFile.write('if ( -e "$PULP_SDK_SRC_PATH/init.sh" ) then source $PULP_SDK_SRC_PATH/init.sh; endif') - - if command == 'src': - - if os.path.exists('.git'): - os.system('git checkout %s' % (src)) - else: - os.system('git init .') - os.system('git remote add -t \* -f origin git@kesch.ee.ethz.ch:pulp-sw/pulp_pipeline.git') - os.system('git checkout %s' % (src)) - diff --git a/sdk-releases/get-sdk-2019.11.02-CentOS_7.py b/sdk-releases/get-sdk-2019.11.02-CentOS_7.py deleted file mode 100755 index d378f270..00000000 --- a/sdk-releases/get-sdk-2019.11.02-CentOS_7.py +++ /dev/null @@ -1,121 +0,0 @@ -#!/usr/bin/env python3 - -# This file has been auto-generated and can be used for downloading the SDK it has -# been generated for. - -import os -import tarfile -import os.path -import argparse - - -src="59b44701b6ac8390a97936cbd049256fc2917212" - -artefacts=[ - ["https://iis-artifactory.ee.ethz.ch/artifactory/release/CentOS_7/pulp/sdk/mainstream/6d315498fd4a31a4f54f5afb2805fbc1a6c382b9/0/sdk.tar.bz2", "pkg/sdk/2019.11.02"], - ["https://iis-artifactory.ee.ethz.ch/artifactory/release/CentOS_7/pulp/pulp_riscv_gcc/mainstream/1.0.14/0/pulp_riscv_gcc.tar.bz2", "pkg/pulp_riscv_gcc/1.0.14"] -] - -exports=[ - ["PULP_SDK_HOME", "$PULP_PROJECT_HOME/pkg/sdk/2019.11.02"], - ["PULP_SDK_INSTALL", "$PULP_SDK_HOME/install"], - ["PULP_SDK_WS_INSTALL", "$PULP_SDK_HOME/install/ws"], - ["PULP_RISCV_GCC_TOOLCHAIN_CI", "$PULP_PROJECT_HOME/pkg/pulp_riscv_gcc/1.0.14"], - ["CROSS_COMPILE", "$PULP_PROJECT_HOME/pkg/pulp_riscv_gcc/1.0.14/bin/riscv32-unknown-elf-"], - ["PULP_RISCV_GCC_VERSION", "3"], - ["ZEPHYR_GCC_VARIANT", "cross-compile"] -] - -sourceme=[ - ["$PULP_SDK_HOME/env/setup.sh", "$PULP_SDK_HOME/env/setup.csh"] -] - -pkg=["sdk", "2019.11.02"] - -parser = argparse.ArgumentParser(description='PULP downloader') - -parser.add_argument('command', metavar='CMD', type=str, nargs='*', - help='a command to be execute') - -parser.add_argument("--path", dest="path", default=None, help="Specify path where to install packages and sources") - -args = parser.parse_args() - -if len(args.command ) == 0: - args.command = ['get'] - -if args.path != None: - path = os.path.expanduser(args.path) - if not os.path.exists(path): - os.makedirs(path) - os.chdir(path) - -for command in args.command: - - if command == 'get' or command == 'download': - - dir = os.getcwd() - - if command == 'get': - if not os.path.exists('pkg'): os.makedirs('pkg') - - os.chdir('pkg') - - for artefactDesc in artefacts: - artefact = artefactDesc[0] - path = os.path.join(dir, artefactDesc[1]) - urlList = artefact.split('/') - fileName = urlList[len(urlList)-1] - - if command == 'download' or not os.path.exists(path): - - if os.path.exists(fileName): - os.remove(fileName) - - artifactory_user = os.environ['ARTIFACTORY_USER'] - artifactory_pw = os.environ['ARTIFACTORY_PASSWORD'] - - if os.system('wget -nv --timeout=2 --user %s --password %s --no-check-certificate %s' % (artifactory_user, artifactory_pw, artefact)) != 0: - exit(-1) - - if command == 'get': - os.makedirs(path) - t = tarfile.open(os.path.basename(artefact), 'r') - t.extractall(path) - os.remove(os.path.basename(artefact)) - - os.chdir(dir) - - if command == 'get' or command == 'download' or command == 'env': - - if not os.path.exists('env'): - os.makedirs('env') - - filePath = 'env/env-%s-%s.sh' % (pkg[0], pkg[1]) - with open(filePath, 'w') as envFile: - #envFile.write('export PULP_ENV_FILE_PATH=%s\n' % os.path.join(os.getcwd(), filePath)) - #envFile.write('export PULP_SDK_SRC_PATH=%s\n' % os.environ.get("PULP_SDK_SRC_PATH")) - envFile.write('export %s=%s\n' % ('PULP_PROJECT_HOME', os.getcwd())) - for export in exports: - envFile.write('export %s=%s\n' % (export[0], export[1].replace('$PULP_PROJECT_HOME', os.getcwd()))) - for env in sourceme: - envFile.write('source %s\n' % (env[0].replace('$PULP_PROJECT_HOME', os.getcwd()))) - #envFile.write('if [ -e "$PULP_SDK_SRC_PATH/init.sh" ]; then source $PULP_SDK_SRC_PATH/init.sh; fi') - - #filePath = 'env/env-%s-%s.csh' % (pkg[0], pkg[1]) - #with open(filePath, 'w') as envFile: - # envFile.write('setenv PULP_ENV_FILE_PATH %s\n' % os.path.join(os.getcwd(), filePath)) - # envFile.write('setenv PULP_SDK_SRC_PATH %s\n' % os.environ.get("PULP_SDK_SRC_PATH")) - # for env in envFileStrCsh: - # envFile.write('%s\n' % (env.replace('@PULP_PKG_HOME@', os.getcwd()))) - # envFile.write('if ( -e "$PULP_SDK_SRC_PATH/init.sh" ) then source $PULP_SDK_SRC_PATH/init.sh; endif') - - if command == 'src': - - if os.path.exists('.git'): - os.system('git checkout %s' % (src)) - else: - os.system('git init .') - os.system('git remote add -t \* -f origin git@kesch.ee.ethz.ch:pulp-sw/pulp_pipeline.git') - os.system('git checkout %s' % (src)) - diff --git a/sdk-releases/get-sdk-2019.11.03-CentOS_7.py b/sdk-releases/get-sdk-2019.11.03-CentOS_7.py deleted file mode 100755 index 943b0a16..00000000 --- a/sdk-releases/get-sdk-2019.11.03-CentOS_7.py +++ /dev/null @@ -1,131 +0,0 @@ -#!/usr/bin/env python3 - -# This file has been auto-generated and can be used for downloading the SDK it has -# been generated for. - -import os -import tarfile -import os.path -import argparse - - -src="59b44701b6ac8390a97936cbd049256fc2917212" - -artefacts=[ - ["https://iis-artifactory.ee.ethz.ch/artifactory/release/CentOS_7/pulp/sdk/mainstream/77d1afe6d11d9935dd6a36617d420a5bdb19f95e/0/sdk.tar.bz2", "pkg/sdk/2019.11.03"], - ["https://iis-artifactory.ee.ethz.ch/artifactory/release/CentOS_7/pulp/pulp_riscv_gcc/mainstream/1.0.14/0/pulp_riscv_gcc.tar.bz2", "pkg/pulp_riscv_gcc/1.0.14"] -] - -exports=[ - ["PULP_SDK_HOME", "$PULP_PROJECT_HOME/pkg/sdk/2019.11.03"], - ["PULP_SDK_INSTALL", "$PULP_SDK_HOME/install"], - ["PULP_SDK_WS_INSTALL", "$PULP_SDK_HOME/install/ws"], - ["PULP_RISCV_GCC_TOOLCHAIN_CI", "$PULP_PROJECT_HOME/pkg/pulp_riscv_gcc/1.0.14"], - ["CROSS_COMPILE", "$PULP_PROJECT_HOME/pkg/pulp_riscv_gcc/1.0.14/bin/riscv32-unknown-elf-"], - ["PULP_RISCV_GCC_VERSION", "3"], - ["ZEPHYR_GCC_VARIANT", "cross-compile"] -] - -sourceme=[ - ["$PULP_SDK_HOME/env/setup.sh", "$PULP_SDK_HOME/env/setup.csh"] -] - -pkg=["sdk", "2019.11.03"] - -parser = argparse.ArgumentParser(description='PULP downloader') - -parser.add_argument('command', metavar='CMD', type=str, nargs='*', - help='a command to be execute') - -parser.add_argument("--path", dest="path", default=None, help="Specify path where to install packages and sources") -parser.add_argument("--nv", dest="nv", action="store_true", help="Deactivate verbosity") - -args = parser.parse_args() - -if len(args.command ) == 0: - args.command = ['get'] - -if args.path != None: - path = os.path.expanduser(args.path) - if not os.path.exists(path): - os.makedirs(path) - os.chdir(path) - -for command in args.command: - - if command == 'get' or command == 'download': - - dir = os.getcwd() - - if command == 'get': - if not os.path.exists('pkg'): os.makedirs('pkg') - - os.chdir('pkg') - - for artefactDesc in artefacts: - artefact = artefactDesc[0] - path = os.path.join(dir, artefactDesc[1]) - urlList = artefact.split('/') - fileName = urlList[len(urlList)-1] - - if command == 'download' or not os.path.exists(path): - - if os.path.exists(fileName): - os.remove(fileName) - - - artifactory_user = os.environ.get('PULP_ARTIFACTORY_USER') - - wget_opt = '' - if args.nv: - wget_opt += ' -nv' - - if artifactory_user is not None: - artifactory_user, artifactory_pw = artifactory_user.split(':') - if os.system('wget %s --timeout=2 --user %s --password %s --no-check-certificate %s' % (wget_opt, artifactory_user, artifactory_pw, artefact)) != 0: - exit(-1) - else: - if os.system('wget %s --timeout=2 --no-check-certificate %s' % (wget_opt, artefact)) != 0: - exit(-1) - - if command == 'get': - os.makedirs(path) - t = tarfile.open(os.path.basename(artefact), 'r') - t.extractall(path) - os.remove(os.path.basename(artefact)) - - os.chdir(dir) - - if command == 'get' or command == 'download' or command == 'env': - - if not os.path.exists('env'): - os.makedirs('env') - - filePath = 'env/env-%s-%s.sh' % (pkg[0], pkg[1]) - with open(filePath, 'w') as envFile: - #envFile.write('export PULP_ENV_FILE_PATH=%s\n' % os.path.join(os.getcwd(), filePath)) - #envFile.write('export PULP_SDK_SRC_PATH=%s\n' % os.environ.get("PULP_SDK_SRC_PATH")) - envFile.write('export %s=%s\n' % ('PULP_PROJECT_HOME', os.getcwd())) - for export in exports: - envFile.write('export %s=%s\n' % (export[0], export[1].replace('$PULP_PROJECT_HOME', os.getcwd()))) - for env in sourceme: - envFile.write('source %s\n' % (env[0].replace('$PULP_PROJECT_HOME', os.getcwd()))) - #envFile.write('if [ -e "$PULP_SDK_SRC_PATH/init.sh" ]; then source $PULP_SDK_SRC_PATH/init.sh; fi') - - #filePath = 'env/env-%s-%s.csh' % (pkg[0], pkg[1]) - #with open(filePath, 'w') as envFile: - # envFile.write('setenv PULP_ENV_FILE_PATH %s\n' % os.path.join(os.getcwd(), filePath)) - # envFile.write('setenv PULP_SDK_SRC_PATH %s\n' % os.environ.get("PULP_SDK_SRC_PATH")) - # for env in envFileStrCsh: - # envFile.write('%s\n' % (env.replace('@PULP_PKG_HOME@', os.getcwd()))) - # envFile.write('if ( -e "$PULP_SDK_SRC_PATH/init.sh" ) then source $PULP_SDK_SRC_PATH/init.sh; endif') - - if command == 'src': - - if os.path.exists('.git'): - os.system('git checkout %s' % (src)) - else: - os.system('git init .') - os.system('git remote add -t \* -f origin git@kesch.ee.ethz.ch:pulp-sw/pulp_pipeline.git') - os.system('git checkout %s' % (src)) - diff --git a/sdk-releases/get-sdk-2020.01.01-CentOS_7.py b/sdk-releases/get-sdk-2020.01.01-CentOS_7.py deleted file mode 100755 index 713b22d5..00000000 --- a/sdk-releases/get-sdk-2020.01.01-CentOS_7.py +++ /dev/null @@ -1,131 +0,0 @@ -#!/usr/bin/env python3 - -# This file has been auto-generated and can be used for downloading the SDK it has -# been generated for. - -import os -import tarfile -import os.path -import argparse - - -src="59b44701b6ac8390a97936cbd049256fc2917212" - -artefacts=[ - ["https://iis-artifactory.ee.ethz.ch/artifactory/release/CentOS_7/pulp/sdk/mainstream/7776c20fb990ad470b4f5edc14664747a7a65c1c/0/sdk.tar.bz2", "pkg/sdk/2020.01.01"], - ["https://iis-artifactory.ee.ethz.ch/artifactory/release/CentOS_7/pulp/pulp_riscv_gcc/mainstream/1.0.16/0/pulp_riscv_gcc.tar.bz2", "pkg/pulp_riscv_gcc/1.0.16"] -] - -exports=[ - ["PULP_SDK_HOME", "$PULP_PROJECT_HOME/pkg/sdk/2020.01.01"], - ["PULP_SDK_INSTALL", "$PULP_SDK_HOME/install"], - ["PULP_SDK_WS_INSTALL", "$PULP_SDK_HOME/install/ws"], - ["PULP_RISCV_GCC_TOOLCHAIN_CI", "$PULP_PROJECT_HOME/pkg/pulp_riscv_gcc/1.0.16"], - ["CROSS_COMPILE", "$PULP_PROJECT_HOME/pkg/pulp_riscv_gcc/1.0.16/bin/riscv32-unknown-elf-"], - ["PULP_RISCV_GCC_VERSION", "3"], - ["ZEPHYR_GCC_VARIANT", "cross-compile"] -] - -sourceme=[ - ["$PULP_SDK_HOME/env/setup.sh", "$PULP_SDK_HOME/env/setup.csh"] -] - -pkg=["sdk", "2020.01.01"] - -parser = argparse.ArgumentParser(description='PULP downloader') - -parser.add_argument('command', metavar='CMD', type=str, nargs='*', - help='a command to be execute') - -parser.add_argument("--path", dest="path", default=None, help="Specify path where to install packages and sources") -parser.add_argument("--nv", dest="nv", action="store_true", help="Deactivate verbosity") - -args = parser.parse_args() - -if len(args.command ) == 0: - args.command = ['get'] - -if args.path != None: - path = os.path.expanduser(args.path) - if not os.path.exists(path): - os.makedirs(path) - os.chdir(path) - -for command in args.command: - - if command == 'get' or command == 'download': - - dir = os.getcwd() - - if command == 'get': - if not os.path.exists('pkg'): os.makedirs('pkg') - - os.chdir('pkg') - - for artefactDesc in artefacts: - artefact = artefactDesc[0] - path = os.path.join(dir, artefactDesc[1]) - urlList = artefact.split('/') - fileName = urlList[len(urlList)-1] - - if command == 'download' or not os.path.exists(path): - - if os.path.exists(fileName): - os.remove(fileName) - - - artifactory_user = os.environ.get('PULP_ARTIFACTORY_USER') - - wget_opt = '' - if args.nv: - wget_opt += ' -nv' - - if artifactory_user is not None: - artifactory_user, artifactory_pw = artifactory_user.split(':') - if os.system('wget %s --timeout=2 --user %s --password %s --no-check-certificate %s' % (wget_opt, artifactory_user, artifactory_pw, artefact)) != 0: - exit(-1) - else: - if os.system('wget %s --timeout=2 --no-check-certificate %s' % (wget_opt, artefact)) != 0: - exit(-1) - - if command == 'get': - os.makedirs(path) - t = tarfile.open(os.path.basename(artefact), 'r') - t.extractall(path) - os.remove(os.path.basename(artefact)) - - os.chdir(dir) - - if command == 'get' or command == 'download' or command == 'env': - - if not os.path.exists('env'): - os.makedirs('env') - - filePath = 'env/env-%s-%s.sh' % (pkg[0], pkg[1]) - with open(filePath, 'w') as envFile: - #envFile.write('export PULP_ENV_FILE_PATH=%s\n' % os.path.join(os.getcwd(), filePath)) - #envFile.write('export PULP_SDK_SRC_PATH=%s\n' % os.environ.get("PULP_SDK_SRC_PATH")) - envFile.write('export %s=%s\n' % ('PULP_PROJECT_HOME', os.getcwd())) - for export in exports: - envFile.write('export %s=%s\n' % (export[0], export[1].replace('$PULP_PROJECT_HOME', os.getcwd()))) - for env in sourceme: - envFile.write('source %s\n' % (env[0].replace('$PULP_PROJECT_HOME', os.getcwd()))) - #envFile.write('if [ -e "$PULP_SDK_SRC_PATH/init.sh" ]; then source $PULP_SDK_SRC_PATH/init.sh; fi') - - #filePath = 'env/env-%s-%s.csh' % (pkg[0], pkg[1]) - #with open(filePath, 'w') as envFile: - # envFile.write('setenv PULP_ENV_FILE_PATH %s\n' % os.path.join(os.getcwd(), filePath)) - # envFile.write('setenv PULP_SDK_SRC_PATH %s\n' % os.environ.get("PULP_SDK_SRC_PATH")) - # for env in envFileStrCsh: - # envFile.write('%s\n' % (env.replace('@PULP_PKG_HOME@', os.getcwd()))) - # envFile.write('if ( -e "$PULP_SDK_SRC_PATH/init.sh" ) then source $PULP_SDK_SRC_PATH/init.sh; endif') - - if command == 'src': - - if os.path.exists('.git'): - os.system('git checkout %s' % (src)) - else: - os.system('git init .') - os.system('git remote add -t \* -f origin git@kesch.ee.ethz.ch:pulp-sw/pulp_pipeline.git') - os.system('git checkout %s' % (src)) - diff --git a/sdk-releases/patches/0001-Disable-forced-isa-flag-for-pulp.patch b/sdk-releases/patches/0001-Disable-forced-isa-flag-for-pulp.patch deleted file mode 100644 index 8768a32f..00000000 --- a/sdk-releases/patches/0001-Disable-forced-isa-flag-for-pulp.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 970f11980720d7cb40d03d5cfe0e5f496a42b148 Mon Sep 17 00:00:00 2001 -From: bluew -Date: Fri, 24 Jul 2020 15:12:19 +0000 -Subject: [PATCH] Disable forced isa flag for pulp - ---- - sdk/2020.01.01/install/ws/python/plpflags.py | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/sdk/2020.01.01/install/ws/python/plpflags.py b/sdk/2020.01.01/install/ws/python/plpflags.py -index 9c0bc5f..c05c6ba 100755 ---- a/sdk/2020.01.01/install/ws/python/plpflags.py -+++ b/sdk/2020.01.01/install/ws/python/plpflags.py -@@ -700,7 +700,7 @@ class Arch(object): - elif self.chip in ['vega', 'gap9', 'pulp']: - c_flags = ' -mPE=8 -mFC=1' - ld_flags = ' -mPE=8 -mFC=1' -- isa='imcXgap9' -+ # isa='imcXgap9' - elif self.chip.find('oprecomp') != -1: - isa='imcXgap9' - elif core_config.get('version') == 'zeroriscy': --- -2.25.0 - diff --git a/sdk-releases/pulp-sdk-2019.07.01-junit.patch b/sdk-releases/pulp-sdk-2019.07.01-junit.patch deleted file mode 100644 index f70437c3..00000000 --- a/sdk-releases/pulp-sdk-2019.07.01-junit.patch +++ /dev/null @@ -1,13 +0,0 @@ -diff --git a/sdk/2019.07.01/install/ws/python/plpobjects.py b/sdk/2019.07.01/install/ws/python/plpobjects.py -index ecf7ae7..3eae00f 100755 ---- a/sdk/2019.07.01/install/ws/python/plpobjects.py -+++ b/sdk/2019.07.01/install/ws/python/plpobjects.py -@@ -357,7 +357,7 @@ class Test(object): - - for run in self.runs: - -- testFile.write(' \n' % (test_prefix + ':' + name, run.config, run.duration)) -+ testFile.write(' \n' % (run.config, test_prefix + ':' + name, run.duration)) - if run.success: - testFile.write(' \n') - else: diff --git a/sdk-releases/pulp-sdk-2019.10.02-junit.patch b/sdk-releases/pulp-sdk-2019.10.02-junit.patch deleted file mode 100644 index 7e9e05e0..00000000 --- a/sdk-releases/pulp-sdk-2019.10.02-junit.patch +++ /dev/null @@ -1,14 +0,0 @@ -diff --git a/sdk/2019.10.02/install/ws/python/plpobjects.py b/sdk/2019.10.02/install/ws/python/plpobjects.py -index ecf7ae7..93cb1e9 100755 ---- a/sdk/2019.10.02/install/ws/python/plpobjects.py -+++ b/sdk/2019.10.02/install/ws/python/plpobjects.py -@@ -357,7 +357,7 @@ class Test(object): - - for run in self.runs: - -- testFile.write(' \n' % (test_prefix + ':' + name, run.config, run.duration)) -+ testFile.write(' \n' % (run.config, test_prefix + ':' + name, run.duration)) - if run.success: - testFile.write(' \n') - else: - diff --git a/sdk-releases/pulp-sdk-2019.11.02-junit.patch b/sdk-releases/pulp-sdk-2019.11.02-junit.patch deleted file mode 100644 index d2a58be0..00000000 --- a/sdk-releases/pulp-sdk-2019.11.02-junit.patch +++ /dev/null @@ -1,14 +0,0 @@ -diff --git a/sdk/2019.11.02/install/ws/python/plpobjects.py b/sdk/2019.11.02/install/ws/python/plpobjects.py -index ecf7ae7..93cb1e9 100755 ---- a/sdk/2019.11.02/install/ws/python/plpobjects.py -+++ b/sdk/2019.11.02/install/ws/python/plpobjects.py -@@ -357,7 +357,7 @@ class Test(object): - - for run in self.runs: - -- testFile.write(' \n' % (test_prefix + ':' + name, run.config, run.duration)) -+ testFile.write(' \n' % (run.config, test_prefix + ':' + name, run.duration)) - if run.success: - testFile.write(' \n') - else: - diff --git a/setup/sdk.sh b/setup/sdk.sh deleted file mode 100644 index 35c53cd0..00000000 --- a/setup/sdk.sh +++ /dev/null @@ -1,4 +0,0 @@ -ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) -export VSIM_PATH="$ROOT"/sim -source pulp-sdk/setup.sh -source pulp-sdk/sourceme.sh diff --git a/setup/vsim.sh b/setup/vsim.sh deleted file mode 100644 index 4bdd5ff6..00000000 --- a/setup/vsim.sh +++ /dev/null @@ -1,2 +0,0 @@ -ROOT=$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")/.." && pwd) -export VSIM_PATH="$ROOT"/sim diff --git a/sim/.gitignore b/sim/.gitignore deleted file mode 100644 index e8a85567..00000000 --- a/sim/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -fs/ -*.log -*.txt -transcript diff --git a/sim/Makefile b/sim/Makefile deleted file mode 100644 index 2ead97f7..00000000 --- a/sim/Makefile +++ /dev/null @@ -1,98 +0,0 @@ -# Copyright 2022 ETH Zurich and University of Bologna -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -mkfile_path := $(dir $(abspath $(firstword $(MAKEFILE_LIST)))) - -VSIM ?= vsim -VSIM_FLAGS = -gLOAD_L2=JTAG -VSIM_SUPPRESS = -suppress vsim-3009 -suppress vsim-8683 -suppress vsim-8386 - -VLOG ?= vlog -VLOG_FLAGS = - -VOPT ?= vopt -VOPT_FLAGS ?= +acc - -VLIB ?= vlib -VMAP ?= vmap - -SVLIB = ../rtl/tb/remote_bitbang/librbs - -# top-level (tesbench) -SIM_TOP = tb_pulp - -## Compile RTL with Questasim -all: lib build opt - -# build the bitbang library, needed for simulating a jtag bridge to OpenOCD -.PHONY: build-deps -build-deps: - $(MAKE) -C ../rtl/tb/remote_bitbang all - -.PHONY: clean-deps -clean-deps: - $(MAKE) -C ../rtl/tb/remote_bitbang clean - -## vsim targets -.PHONY: sim -## Simulate RTL with Questasim (GUI) -sim: - $(VSIM) -64 -gui vopt_tb \ - $(VSIM_SUPPRESS) \ - +UVM_NO_RELNOTES -stats -t ps \ - -sv_lib $(SVLIB) $(VSIM_FLAGS) \ - -do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1" -.PHONY: simc -## Simulate RTL with Questasim -simc: - $(VSIM) -64 -c vopt_tb \ - $(VSIM_SUPPRESS) \ - +UVM_NO_RELNOTES -stats -t ps \ - -sv_lib $(SVLIB) $(VSIM_FLAGS) \ - -do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1" \ - -do "run -all" \ - -do "quit -code [examine -radix decimal sim:/tb_pulp/exit_status]" - -.PHONY: opt -opt: - $(VOPT) $(VOPT_FLAGS) -o vopt_tb $(SIM_TOP) -work work - -.PHONY: opt -build: build-deps - $(VSIM) -c -do 'source compile.tcl; quit' - -.PHONY: lib -lib: - - -.PHONY: clean -## Remove all compiled RTL -clean: clean-deps - $(RM) -r work - $(RM) modelsim.ini - - -.PHONY: help -help: Makefile - @printf "PULPissimo\n" - @printf "Available targets\n\n" - @awk '/^[a-zA-Z\-\_0-9]+:/ { \ - helpMessage = match(lastLine, /^## (.*)/); \ - if (helpMessage) { \ - helpCommand = substr($$1, 0, index($$1, ":")-1); \ - helpMessage = substr(lastLine, RSTART + 3, RLENGTH); \ - printf "%-15s %s\n", helpCommand, helpMessage; \ - } \ - } \ - { lastLine = $$0 }' $(MAKEFILE_LIST) diff --git a/sim/boot/boot_code.cde b/sim/boot/boot_code.cde deleted file mode 100644 index 9d4a5a99..00000000 --- a/sim/boot/boot_code.cde +++ /dev/null @@ -1,2048 +0,0 @@ -00001000100000000000000001101111 -00001000010000000000000001101111 -00001000000000000000000001101111 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100755 index dca8bede..00000000 --- a/sim/tcl_files/config/export_all.tcl +++ /dev/null @@ -1,3 +0,0 @@ -vcd file -compress export.vcd.gz -vcd add -r -optcells -internal -ports {sim:/tb_pulp/i_dut/*} - diff --git a/sim/tcl_files/export_run.tcl b/sim/tcl_files/export_run.tcl deleted file mode 100755 index 1fb87948..00000000 --- a/sim/tcl_files/export_run.tcl +++ /dev/null @@ -1,7 +0,0 @@ -#!/bin/bash - -set TB "vopt_tb -L models_lib -L vip_lib" - -source ./tcl_files/config/vsim.tcl -source ./tcl_files/config/export_all.tcl - diff --git a/sim/tcl_files/rtl_vopt.tcl b/sim/tcl_files/rtl_vopt.tcl deleted file mode 100755 index 6d00d91e..00000000 --- a/sim/tcl_files/rtl_vopt.tcl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env tclsh - -source ./tcl_files/config/vsim_ips.tcl -source ./tcl_files/config/vsim_rtl.tcl - - -proc color {foreground text} { - # tput is a little Unix utility that lets you use the termcap database - # *much* more easily... - return [exec tput setaf $foreground]$text[exec tput sgr0] -} - -if {[catch { - info exists $::env(VSIM_PATH) -}]} { - puts [concat [color 1 "ERROR"] ": VSIM_PATH should be defined before building the RTL platform."] - exit 1 -} -eval exec vlib $::env(VSIM_PATH)/modelsim_libs/tb_lib -eval exec vmap work $::env(VSIM_PATH)/modelsim_libs/tb_lib - -set sub_str "-L ${::env(VSIM_PATH)}/modelsim_libs/" -set VSIM_IP_LIBS [regsub -all -- "-L " $VSIM_IP_LIBS $sub_str] -set VSIM_RTL_LIBS [regsub -all -- "-L " $VSIM_RTL_LIBS $sub_str] - -if {[info exists ::env(VSIM_PATH)]} { - #eval exec >@stdout vopt +acc=mnpr -o vopt_tb tb_pulp -floatparameters+tb_pulp -Ldir $::env(VSIM_PATH)/modelsim_libs $VSIM_IP_LIBS $VSIM_RTL_LIBS -work work - eval exec >@stdout vopt +acc=mnpr -o vopt_tb tb_pulp -floatparameters+tb_pulp $VSIM_IP_LIBS $VSIM_RTL_LIBS -work work -} else { - eval exec >@stdout vopt +acc=mnpr -o vopt_pulp_chip pulp_chip $VSIM_IP_LIBS $VSIM_RTL_LIBS -work pulpissimo_lib -} - diff --git a/spyglass/Makefile b/spyglass/Makefile deleted file mode 100644 index 74ad904d..00000000 --- a/spyglass/Makefile +++ /dev/null @@ -1,62 +0,0 @@ -# Copyright 2020 ETH Zurich and University of Bologna - -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at - -# http://www.apache.org/licenses/LICENSE-2.0 - -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -PROJECT_NAME ?= pulpissimo -PULP_PATH ?= $(shell git rev-parse --show-toplevel) -SG_SHELL_CMD ?= spyglass-2019.06 sg_shell -SG_GUI_CMD ?= spyglass-2019.06 spyglass - -.DEFAULT_GOAL := help - -.PHONY: $(PULP_PATH)/spyglass/working_dir/sources.f -$(PULP_PATH)/spyglass/working_dir/sources.f: $(PULP_PATH)/bender - mkdir -p $(PULP_PATH)/spyglass/working_dir - $(PULP_PATH)/bender script -t synthesis verilator > $(PULP_PATH)/spyglass/working_dir/sources.f - -.PHONY: lint_rtl -## Run spyglass lint with rtl_handoff methodology -lint_rtl: $(PULP_PATH)/spyglass/working_dir/reports/lint_rtl.report.xml - -$(PULP_PATH)/spyglass/working_dir/reports/moresimple.rpt: $(PULP_PATH)/spyglass/working_dir/sources.f - echo $(SG_SHELL_CMD) - cd $(PULP_PATH)/spyglass/working_dir && $(SG_SHELL_CMD) -tcl_file_continue_on_error -tcl $(PULP_PATH)/spyglass/run_lint_rtl_handoff.tcl - -# generate generate junit report from spyglass report -$(PULP_PATH)/spyglass/working_dir/reports/lint_rtl.report.xml: $(PULP_PATH)/spyglass/working_dir/reports/moresimple.rpt - ./convert_report_to_junit.py --error-level error $(PULP_PATH)/spyglass/working_dir/reports/moresimple.rpt > $(PULP_PATH)/spyglass/working_dir/reports/lint_rtl.report.xml - -.PHONY: show_results -## Open the generated lint results in Spyglass GUI -show_results: - cd $(PULP_PATH)/spyglass/working_dir && $(SG_GUI_CMD) -project $(PROJECT_NAME).prj - -## Delete the spyglass working directory -.PHONY: clean -clean: - rm -rf $(PULP_PATH)/spyglass/working_dir - -.PHONY: help -help: Makefile - @printf "PULP Platform\n" - @printf "Available targets\n\n" - @awk '/^[a-zA-Z\-\_0-9]+:/ { \ - helpMessage = match(lastLine, /^## (.*)/); \ - if (helpMessage) { \ - helpCommand = substr($$1, 0, index($$1, ":")-1); \ - helpMessage = substr(lastLine, RSTART + 3, RLENGTH); \ - printf "%-15s %s\n", helpCommand, helpMessage; \ - } \ - } \ - { lastLine = $$0 }' $(MAKEFILE_LIST) - diff --git a/boot/.gitignore b/sw/bootcode/.gitignore similarity index 95% rename from boot/.gitignore rename to sw/bootcode/.gitignore index f4c40629..a05fb04d 100644 --- a/boot/.gitignore +++ b/sw/bootcode/.gitignore @@ -9,3 +9,4 @@ rom.bin *.o.2 *.s19 *.map +.venv diff --git a/boot/LICENSE.srec b/sw/bootcode/LICENSE.srec similarity index 100% rename from boot/LICENSE.srec rename to sw/bootcode/LICENSE.srec diff --git a/boot/Makefile b/sw/bootcode/Makefile similarity index 63% rename from boot/Makefile rename to sw/bootcode/Makefile index 5d53d9e4..97a709b6 100644 --- a/boot/Makefile +++ b/sw/bootcode/Makefile @@ -15,15 +15,23 @@ # SPDX-License-Identifier: Apache-2.0 # Author: Robert Balas (balasr@iis.ee.ethz.ch) -# -flto, normal text 4378 rodata 394 4772 -# withouth no-jump-tables text 4144 rodata 562 4706 -# with save-restore text 4156 rodata 546 4702 +# -flto, normal text 4378 rodata 394 4772 +# withouth no-jump-tables text 4144 rodata 562 4706 +# with save-restore text 4156 rodata 546 4702 + +.DEFAULT_GOAL := help -PYTHON = python3.6 CTAGS = ctags -RISCV ?= $(HOME)/.riscv -RISCV_PREFIX ?= $(RISCV)/bin/riscv32-unknown-elf- +VENVDIR?=$(WORKDIR)/.venv +REQUIREMENTS_TXT?=$(wildcard requirements.txt) +include Makefile.venv + + +ifdef $(RISCV) +RISCV_BIN_PATH ?= $(RISCV)/bin/ +endif +RISCV_PREFIX ?= $(RISCV_BIN_PATH)riscv32-unknown-elf- CC = $(RISCV_PREFIX)gcc OBJCOPY = $(RISCV_PREFIX)objcopy OBJDUMP = $(RISCV_PREFIX)objdump @@ -51,9 +59,17 @@ CPPFLAGS += -DENABLE_UART_BOOT # UDMA UART periperal id and desired baudrate CPPFLAGS += -DUART_ID=0 CPPFLAGS += -DUART_BAUDRATE=115200 +# IO Pads to use for UART functions in bootmode +CPPFLAGS += -DUART_TX_PAD=PAD_GPIO00 +CPPFLAGS += -DUART_RX_PAD=PAD_GPIO01 # UDMA SPI periperhal id and max supported clock frequency CPPFLAGS += -DSPI_ID=7 CPPFLAGS += -DSPI_MAX_CLK=25000000 +# IO Pads to use for spi booting +CPPFLAGS += -DSPI_SCK_PAD=PAD_GPIO02 +CPPFLAGS += -DSPI_CSN_PAD=PAD_GPIO03 +CPPFLAGS += -DSPI_MOSI_PAD=PAD_GPIO04 +CPPFLAGS += -DSPI_MISO_PAD=PAD_GPIO05 CPPFLAGS += -DEXIT_REG_ADDR=0x1a1040a0 # Make error message more verbose instead of the default single letter error @@ -65,7 +81,7 @@ CPPFLAGS += -DZF_VERBOSE_ERRORS CPPFLAGS += -I$(CURDIR) -I$(CURDIR)/include -I$(CURDIR)/include/hal \ -I$(CURDIR)/include/archi -I$(CURDIR)/zforth \ - -I$(CURDIR)/zforth-riscv + -I$(CURDIR)/zforth-riscv -I$(CURDIR)/io_mux/include ASFLAGS = $(CFLAGS) -DLANGUAGE_ASSEMBLY @@ -81,7 +97,7 @@ BOOTCODE_FPGA = boot_code_fpga OBJS = boot_code.o crt0.o \ zforth-riscv/zforth-main.o zforth-riscv/libc.o zforth-riscv/udma.o \ - zforth-riscv/setjmp.o zforth/zforth.o kk_srec.o fll-v1.o + zforth-riscv/setjmp.o zforth/zforth.o kk_srec.o fll-v1.o io_mux/src/io_mux.o all: $(BOOTCODE) $(BOOTCODE_FPGA) boot.rtl boot.gvsoc @@ -118,16 +134,16 @@ $(BOOTCODE_FPGA): $(addsuffix .2,$(OBJS)) %_fpga: %.o.2 $(CC) $(LDFLAGS) $(TARGET_ARCH) $^ $(LOADLIBES) $(LDLIBS) -o $@ +## gvsoc bootrom boot.gvsoc: rom.bin -# gvsoc bootrom rom.bin: $(BOOTCODE) - ./stim_utils.py \ + $(VENV)/python stim_utils.py \ --binary=$(BOOTCODE) \ --stim-bin=rom.bin \ --area=0x1a000000:0x01000000 -# The rtl bootrom is just a verilog dump of the elf file +## Generates bootcode dump files boot_code_asic.cde and the boot_code_fpga.cde for use with ROM generators boot.rtl: boot_code_asic.cde boot_code_fpga.cde boot_code_asic.objdump: $(BOOTCODE) @@ -136,30 +152,54 @@ boot_code_asic.objdump: $(BOOTCODE) boot_code_fpga.objdump: $(BOOTCODE) $(OBJDUMP) -Sr boot_code > $@ -boot_code_asic.cde: $(BOOTCODE) boot_code_asic.objdump +boot_code_asic.cde: $(BOOTCODE) boot_code_asic.objdump | venv $(OBJCOPY) --srec-len 1 --output-target=srec $(BOOTCODE) $(BOOTCODE).s19 - ./s19toboot.py $(BOOTCODE).s19 boot_code_asic.cde pulpissimo + $(VENV)/python s19toboot.py $(BOOTCODE).s19 boot_code_asic.cde pulpissimo $(SIZE) -A $(BOOTCODE) -boot_code_fpga.cde: $(BOOTCODE_FPGA) boot_code_fpga.objdump +boot_code_fpga.cde: $(BOOTCODE_FPGA) boot_code_fpga.objdump | venv $(OBJCOPY) --srec-len 1 --output-target=srec $(BOOTCODE_FPGA) $(BOOTCODE_FPGA).s19 - ./s19toboot.py $(BOOTCODE_FPGA).s19 boot_code_fpga.cde pulpissimo + $(VENV)/python s19toboot.py $(BOOTCODE_FPGA).s19 boot_code_fpga.cde pulpissimo $(SIZE) -A $(BOOTCODE_FPGA) -asic_autogen_rom.sv: boot_code_asic.cde - $(PYTHON) gen_rom.py boot_code_asic.cde $@ --title "ASIC Bootrom for control_pulp" +## Synthesizable bootrom for ASICs +asic_autogen_rom.sv: boot_code_asic.cde | venv + $(VENV)/python gen_rom.py boot_code_asic.cde $@ --title "ASIC Bootrom for control_pulp" -fpga_autogen_rom.sv: boot_code_fpga.cde - $(PYTHON) gen_rom.py boot_code_fpga.cde $@ --title "FPGA Bootrom for control_pulp" +## Synthesizable bootrom for FPGA +fpga_autogen_rom.sv: boot_code_fpga.cde | venv + $(VENV)/python gen_rom.py boot_code_fpga.cde $@ --title "FPGA Bootrom for control_pulp" +## Generate disassembly of the bootcode +dis: + $(OBJDUMP) -d -S boot_code .PHONY: clean +## Delete all build files clean: $(RM) $(BOOTCODE) $(BOOTCODE_FPGA) $(OBJS) $(addsuffix .2,$(OBJS)) \ boot_code.cde boot_code.sv boot_code.s19 rom.bin \ boot_code_asic.cde boot_code_fpga.cde \ - boot_code.map asic_autogen_rom.sv fpga_autogen_rom.sv + boot_code.map asic_autogen_rom.sv fpga_autogen_rom.sv \ + boot_code_asic.objdump boot_code_fpga.objdump boot_code_fpga.s19 bootcode.s + .PHONY: TAGS TAGS: $(CTAGS) -R -e . + + +.PHONY: help +help: Makefile + @printf "Pulpissimo Bootcode Generation\n" + @printf "Use this Makefile to regenerate the bootcode for Pulpissimo in output formats suitable for simulation, FPGA implementation and ASIC synthesis.\n\n" + @printf "Available targets\n\n" + @awk '/^[a-zA-Z\-_\.0-9]+:/ { \ + helpMessage = match(lastLine, /^## (.*)/); \ + if (helpMessage) { \ + helpCommand = substr($$1, 0, index($$1, ":")-1); \ + helpMessage = substr(lastLine, RSTART + 3, RLENGTH); \ + printf "%-15s %s\n", helpCommand, helpMessage; \ + } \ + } \ + { lastLine = $$0 }' $(MAKEFILE_LIST) diff --git a/sw/bootcode/Makefile.venv b/sw/bootcode/Makefile.venv new file mode 100644 index 00000000..c79b9bbc --- /dev/null +++ b/sw/bootcode/Makefile.venv @@ -0,0 +1,274 @@ +# +# SEAMLESSLY MANAGE PYTHON VIRTUAL ENVIRONMENT WITH A MAKEFILE +# +# https://github.com/sio/Makefile.venv v2022.07.20 +# +# +# Insert `include Makefile.venv` at the bottom of your Makefile to enable these +# rules. +# +# When writing your Makefile use '$(VENV)/python' to refer to the Python +# interpreter within virtual environment and '$(VENV)/executablename' for any +# other executable in venv. +# +# This Makefile provides the following targets: +# venv +# Use this as a dependency for any target that requires virtual +# environment to be created and configured +# python, ipython +# Use these to launch interactive Python shell within virtual environment +# shell, bash, zsh +# Launch interactive command line shell. "shell" target launches the +# default shell Makefile executes its rules in (usually /bin/sh). +# "bash" and "zsh" can be used to refer to the specific desired shell. +# show-venv +# Show versions of Python and pip, and the path to the virtual environment +# clean-venv +# Remove virtual environment +# $(VENV)/executable_name +# Install `executable_name` with pip. Only packages with names matching +# the name of the corresponding executable are supported. +# Use this as a lightweight mechanism for development dependencies +# tracking. E.g. for one-off tools that are not required in every +# developer's environment, therefore are not included into +# requirements.txt or setup.py. +# Note: +# Rules using such target or dependency MUST be defined below +# `include` directive to make use of correct $(VENV) value. +# Example: +# codestyle: $(VENV)/pyflakes +# $(VENV)/pyflakes . +# See `ipython` target below for another example. +# +# This Makefile can be configured via following variables: +# PY +# Command name for system Python interpreter. It is used only initially to +# create the virtual environment +# Default: python3 +# REQUIREMENTS_TXT +# Space separated list of paths to requirements.txt files. +# Paths are resolved relative to current working directory. +# Default: requirements.txt +# +# Non-existent files are treated as hard dependencies, +# recipes for creating such files must be provided by the main Makefile. +# Providing empty value (REQUIREMENTS_TXT=) turns off processing of +# requirements.txt even when the file exists. +# SETUP_PY +# Space separated list of paths to setup.py files. +# Corresponding packages will be installed into venv in editable mode +# along with all their dependencies +# Default: setup.py +# +# Non-existent and empty values are treated in the same way as for REQUIREMENTS_TXT. +# WORKDIR +# Parent directory for the virtual environment. +# Default: current working directory. +# VENVDIR +# Python virtual environment directory. +# Default: $(WORKDIR)/.venv +# +# This Makefile was written for GNU Make and may not work with other make +# implementations. +# +# +# Copyright (c) 2019-2020 Vitaly Potyarkin +# +# Licensed under the Apache License, Version 2.0 +# +# + + +# +# Configuration variables +# + +WORKDIR?=. +VENVDIR?=$(WORKDIR)/.venv +REQUIREMENTS_TXT?=$(wildcard requirements.txt) # Multiple paths are supported (space separated) +SETUP_PY?=$(wildcard setup.py) # Multiple paths are supported (space separated) +SETUP_CFG?=$(foreach s,$(SETUP_PY),$(wildcard $(patsubst %setup.py,%setup.cfg,$(s)))) +MARKER=.initialized-with-Makefile.venv + + +# +# Python interpreter detection +# + +_PY_AUTODETECT_MSG=Detected Python interpreter: $(PY). Use PY environment variable to override + +ifeq (ok,$(shell test -e /dev/null 2>&1 && echo ok)) +NULL_STDERR=2>/dev/null +else +NULL_STDERR=2>NUL +endif + +ifndef PY +_PY_OPTION:=python3 +ifeq (ok,$(shell $(_PY_OPTION) -c "print('ok')" $(NULL_STDERR))) +PY=$(_PY_OPTION) +endif +endif + +ifndef PY +_PY_OPTION:=$(VENVDIR)/bin/python +ifeq (ok,$(shell $(_PY_OPTION) -c "print('ok')" $(NULL_STDERR))) +PY=$(_PY_OPTION) +$(info $(_PY_AUTODETECT_MSG)) +endif +endif + +ifndef PY +_PY_OPTION:=$(subst /,\,$(VENVDIR)/Scripts/python) +ifeq (ok,$(shell $(_PY_OPTION) -c "print('ok')" $(NULL_STDERR))) +PY=$(_PY_OPTION) +$(info $(_PY_AUTODETECT_MSG)) +endif +endif + +ifndef PY +_PY_OPTION:=py -3 +ifeq (ok,$(shell $(_PY_OPTION) -c "print('ok')" $(NULL_STDERR))) +PY=$(_PY_OPTION) +$(info $(_PY_AUTODETECT_MSG)) +endif +endif + +ifndef PY +_PY_OPTION:=python +ifeq (ok,$(shell $(_PY_OPTION) -c "print('ok')" $(NULL_STDERR))) +PY=$(_PY_OPTION) +$(info $(_PY_AUTODETECT_MSG)) +endif +endif + +ifndef PY +define _PY_AUTODETECT_ERR +Could not detect Python interpreter automatically. +Please specify path to interpreter via PY environment variable. +endef +$(error $(_PY_AUTODETECT_ERR)) +endif + + +# +# Internal variable resolution +# + +VENV=$(VENVDIR)/bin +EXE= +# Detect windows +ifeq (win32,$(shell $(PY) -c "import __future__, sys; print(sys.platform)")) +VENV=$(VENVDIR)/Scripts +EXE=.exe +endif + +touch=touch $(1) +ifeq (,$(shell command -v touch $(NULL_STDERR))) +# https://ss64.com/nt/touch.html +touch=type nul >> $(subst /,\,$(1)) && copy /y /b $(subst /,\,$(1))+,, $(subst /,\,$(1)) +endif + +RM?=rm -f +ifeq (,$(shell command -v $(firstword $(RM)) $(NULL_STDERR))) +RMDIR:=rd /s /q +else +RMDIR:=$(RM) -r +endif + + +# +# Virtual environment +# + +.PHONY: venv +venv: $(VENV)/$(MARKER) + +.PHONY: clean-venv +clean-venv: + -$(RMDIR) "$(VENVDIR)" + +.PHONY: show-venv +show-venv: venv + @$(VENV)/python -c "import sys; print('Python ' + sys.version.replace('\n',''))" + @$(VENV)/pip --version + @echo venv: $(VENVDIR) + +.PHONY: debug-venv +debug-venv: + @echo "PATH (Shell)=$$PATH" + @$(MAKE) --version + $(info PATH (GNU Make)="$(PATH)") + $(info SHELL="$(SHELL)") + $(info PY="$(PY)") + $(info REQUIREMENTS_TXT="$(REQUIREMENTS_TXT)") + $(info SETUP_PY="$(SETUP_PY)") + $(info SETUP_CFG="$(SETUP_CFG)") + $(info VENVDIR="$(VENVDIR)") + $(info VENVDEPENDS="$(VENVDEPENDS)") + $(info WORKDIR="$(WORKDIR)") + + +# +# Dependencies +# + +ifneq ($(strip $(REQUIREMENTS_TXT)),) +VENVDEPENDS+=$(REQUIREMENTS_TXT) +endif + +ifneq ($(strip $(SETUP_PY)),) +VENVDEPENDS+=$(SETUP_PY) +endif +ifneq ($(strip $(SETUP_CFG)),) +VENVDEPENDS+=$(SETUP_CFG) +endif + +$(VENV): + $(PY) -m venv $(VENVDIR) + $(VENV)/python -m pip install --upgrade pip setuptools wheel + +$(VENV)/$(MARKER): $(VENVDEPENDS) | $(VENV) +ifneq ($(strip $(REQUIREMENTS_TXT)),) + $(VENV)/pip install $(foreach path,$(REQUIREMENTS_TXT),-r $(path)) +endif +ifneq ($(strip $(SETUP_PY)),) + $(VENV)/pip install $(foreach path,$(SETUP_PY),-e $(dir $(path))) +endif + $(call touch,$(VENV)/$(MARKER)) + + +# +# Interactive shells +# + +.PHONY: python +python: venv + exec $(VENV)/python + +.PHONY: ipython +ipython: $(VENV)/ipython + exec $(VENV)/ipython + +.PHONY: shell +shell: venv + . $(VENV)/activate && exec $(notdir $(SHELL)) + +.PHONY: bash zsh +bash zsh: venv + . $(VENV)/activate && exec $@ + + +# +# Commandline tools (wildcard rule, executable name must match package name) +# + +ifneq ($(EXE),) +$(VENV)/%: $(VENV)/%$(EXE) ; +.PHONY: $(VENV)/% +.PRECIOUS: $(VENV)/%$(EXE) +endif + +$(VENV)/%$(EXE): $(VENV)/$(MARKER) + $(VENV)/pip install --upgrade $* + $(call touch,$@) diff --git a/boot/README.md b/sw/bootcode/README.md similarity index 100% rename from boot/README.md rename to sw/bootcode/README.md diff --git a/boot/boot_code.c b/sw/bootcode/boot_code.c similarity index 90% rename from boot/boot_code.c rename to sw/bootcode/boot_code.c index a4ca8e74..fa43d85c 100644 --- a/boot/boot_code.c +++ b/sw/bootcode/boot_code.c @@ -25,10 +25,42 @@ #include "libc.h" #include "udma.h" #include "kk_srec.h" +#include "io_mux.h" #define BOOT_STACK_SIZE 1024 #define MAX_NB_AREA 16 +#ifndef UART_TX_PAD +#define UART_TX_PAD PAD_GPIO00 +#endif +#ifndef UART_RX_PAD +#define UART_RX_PAD PAD_GPIO01 +#endif +#ifndef SPI_SCK_PAD +#define SPI_SCK_PAD PAD_GPIO02 +#endif +#ifndef SPI_CSN_PAD +#define SPI_CSN_PAD PAD_GPIO03 +#endif +#ifndef SPI_MOSI_PAD +#define SPI_MOSI_PAD PAD_GPIO04 +#endif +#ifndef SPI_MISO_PAD +#define SPI_MISO_PAD PAD_GPIO05 +#endif + +void io_mux_expose_uart() { + io_mux_mode_set(UART_TX_PAD, PAD_MODE_UART0_TX); + io_mux_mode_set(UART_RX_PAD, PAD_MODE_UART0_RX); +} + +void io_mux_expose_spi() { + io_mux_mode_set(SPI_SCK_PAD, PAD_MODE_QSPIM0_SCK); + io_mux_mode_set(SPI_CSN_PAD, PAD_MODE_QSPIM0_CSN0); + io_mux_mode_set(SPI_MOSI_PAD, PAD_MODE_QSPIM0_SDIO0); + io_mux_mode_set(SPI_MISO_PAD, PAD_MODE_QSPIM0_SDIO1); +} + #if FLASH_BLOCK_SIZE > HYPER_FLASH_BLOCK_SIZE # define BLOCK_SIZE FLASH_BLOCK_SIZE #else @@ -230,8 +262,10 @@ static void flash_init(boot_code_t *data) data->step = 0; #ifdef DEBUG_BOOTROM - plp_udma_cg_set((1 << UDMA_UART_ID(0))); - plp_uart_setup(0, UART_CLK_DIVIDER); + // Expose UART + io_mux_expose_uart(); + /* boot a srec dump of a binary over udma uart */ + uart_open(UART_ID, UART_BAUDRATE); #endif plp_udma_cg_set(plp_udma_cg_get() | (1 << ARCHI_UDMA_SPIM_ID(SPI_ID))); @@ -461,14 +495,18 @@ void __attribute__((noreturn)) main(void) switch (apb_soc_bootsel_get(ARCHI_APB_SOC_CTRL_ADDR) & 3) { case BOOT_MODE_DEFAULT: #ifdef CONFIG_FLL - /* zforth/srec need a stable periperal frequency */ - pos_fll_constructor(); - pos_fll_init(POS_FLL_PERIPH); - pos_fll_set_freq(POS_FLL_PERIPH, PERIPH_FREQUENCY); + /* zforth/srec need a stable periperal frequency */ + pos_fll_constructor(); + pos_fll_init(POS_FLL_PERIPH); + pos_fll_set_freq(POS_FLL_PERIPH, PERIPH_FREQUENCY); #endif #ifdef ENABLE_ZFORTH_BOOT + // Both, zforth and uart boot need the UART peripheral to be exposed. Configure the padmux + io_mux_expose_uart(); boot_zforth(); #elif ENABLE_UART_BOOT + // Both, zforth and uart boot need the UART peripheral to be exposed. Configure the padmux + io_mux_expose_uart(); boot_srec_uart(); #endif break; @@ -477,6 +515,8 @@ void __attribute__((noreturn)) main(void) break; case BOOT_MODE_QSPI: #ifdef ENABLE_QSPI_BOOT + // Expose to QSPI Pads + io_mux_expose_spi(); boot_qspi(0, 1); #endif break; diff --git a/boot/boot_code.h b/sw/bootcode/boot_code.h similarity index 100% rename from boot/boot_code.h rename to sw/bootcode/boot_code.h diff --git a/boot/boot_code_asic.objdump b/sw/bootcode/boot_code_asic.objdump similarity index 87% rename from boot/boot_code_asic.objdump rename to sw/bootcode/boot_code_asic.objdump index 7e1c1bf4..e5bed0d7 100644 --- a/boot/boot_code_asic.objdump +++ b/sw/bootcode/boot_code_asic.objdump @@ -95,7 +95,7 @@ default_handler: 1a00008c : 1a00008c: 1a1027b7 lui a5,0x1a102 -1a000090: 0a87a703 lw a4,168(a5) # 1a1020a8 <__clz_tab+0x100b84> +1a000090: 0a87a703 lw a4,168(a5) # 1a1020a8 <__clz_tab+0x100b34> 1a000094: 8b05 andi a4,a4,1 1a000096: cb19 beqz a4,1a0000ac 1a000098: 0a47a703 lw a4,164(a5) @@ -104,7 +104,7 @@ default_handler: 1a0000a4: fdf00713 li a4,-33 1a0000a8: 0ae7a223 sw a4,164(a5) 1a0000ac: 1a102737 lui a4,0x1a102 -1a0000b0: 0b072783 lw a5,176(a4) # 1a1020b0 <__clz_tab+0x100b8c> +1a0000b0: 0b072783 lw a5,176(a4) # 1a1020b0 <__clz_tab+0x100b3c> 1a0000b4: 8b85 andi a5,a5,1 1a0000b6: dfed beqz a5,1a0000b0 1a0000b8: 0b472503 lw a0,180(a4) @@ -126,7 +126,7 @@ default_handler: 1a0000de: c3d4 sw a3,4(a5) 1a0000e0: 009b07b7 lui a5,0x9b0 1a0000e4: 31678793 addi a5,a5,790 # 9b0316 <__stack_size+0x9afb16> -1a0000e8: 0af72223 sw a5,164(a4) # 1a1020a4 <__clz_tab+0x100b80> +1a0000e8: 0af72223 sw a5,164(a4) # 1a1020a4 <__clz_tab+0x100b30> 1a0000ec: 8082 ret 1a0000ee : @@ -168,7 +168,7 @@ default_handler: 1a00014c: 0785 addi a5,a5,1 1a00014e: cd1c sw a5,24(a0) 1a000150: 1a1027b7 lui a5,0x1a102 -1a000154: 10c7a023 sw a2,256(a5) # 1a102100 <__clz_tab+0x100bdc> +1a000154: 10c7a023 sw a2,256(a5) # 1a102100 <__clz_tab+0x100b8c> 1a000158: 10d7a223 sw a3,260(a5) 1a00015c: 4751 li a4,20 1a00015e: 10e7a423 sw a4,264(a5) @@ -178,7 +178,7 @@ default_handler: 1a00016c: 12e7a423 sw a4,296(a5) 1a000170: 1a10a7b7 lui a5,0x1a10a 1a000174: 04000737 lui a4,0x4000 -1a000178: 80e7a223 sw a4,-2044(a5) # 1a109804 <__clz_tab+0x1082e0> +1a000178: 80e7a223 sw a4,-2044(a5) # 1a109804 <__clz_tab+0x108290> 1a00017c: 80c7a683 lw a3,-2036(a5) 1a000180: 00569613 slli a2,a3,0x5 1a000184: 00065963 bgez a2,1a000196 @@ -264,7 +264,7 @@ default_handler: 1a000242: c3d8 sw a4,4(a5) 1a000244: 1a10a7b7 lui a5,0x1a10a 1a000248: 6711 lui a4,0x4 -1a00024a: 80e7a223 sw a4,-2044(a5) # 1a109804 <__clz_tab+0x1082e0> +1a00024a: 80e7a223 sw a4,-2044(a5) # 1a109804 <__clz_tab+0x108290> 1a00024e: 81478713 addi a4,a5,-2028 1a000252: 10500073 wfi 1a000256: c314 sw a3,0(a4) @@ -323,7 +323,7 @@ default_handler: 1a0002f4: c606 sw ra,12(sp) 1a0002f6: 842a mv s0,a0 1a0002f8: 559000ef jal ra,1a001050 <__clzsi2> -1a0002fc: ffe50793 addi a5,a0,-2 # 1bfffffe <__clz_tab+0x1ffeada> +1a0002fc: ffe50793 addi a5,a0,-2 # 1bfffffe <__clz_tab+0x1ffea8a> 1a000300: 8385 srli a5,a5,0x1 1a000302: e391 bnez a5,1a000306 1a000304: 4785 li a5,1 @@ -340,7 +340,7 @@ default_handler: 1a000326: 1c0036b7 lui a3,0x1c003 1a00032a: da56c683 lbu a3,-603(a3) # 1c002da5 1a00032e: c29d beqz a3,1a000354 -1a000330: 1a100637 lui a2,0x1a100 +1a000330: 1a120637 lui a2,0x1a120 1a000334: 4a54 lw a3,20(a2) 1a000336: 833d srli a4,a4,0xf 1a000338: 0742 slli a4,a4,0x10 @@ -367,7 +367,7 @@ default_handler: 1a000362: 1141 addi sp,sp,-16 1a000364: 93050513 addi a0,a0,-1744 # 1c001930 1a000368: c606 sw ra,12(sp) -1a00036a: 012010ef jal ra,1a00137c +1a00036a: 062010ef jal ra,1a0013cc 1a00036e : 1a00036e: 1141 addi sp,sp,-16 @@ -635,7 +635,7 @@ default_handler: 1a0005ec: 800007b7 lui a5,0x80000 1a0005f0: 8d5d or a0,a0,a5 1a0005f2: 1a1047b7 lui a5,0x1a104 -1a0005f6: 0aa7a023 sw a0,160(a5) # 1a1040a0 <__clz_tab+0x102b7c> +1a0005f6: 0aa7a023 sw a0,160(a5) # 1a1040a0 <__clz_tab+0x102b2c> 1a0005fa: a001 j 1a0005fa 1a0005fc : @@ -663,7 +663,7 @@ default_handler: 1a000630: c05a sw s6,0(sp) 1a000632: 843e mv s0,a5 1a000634: 1a102937 lui s2,0x1a102 -1a000638: 09892783 lw a5,152(s2) # 1a102098 <__clz_tab+0x100b74> +1a000638: 09892783 lw a5,152(s2) # 1a102098 <__clz_tab+0x100b24> 1a00063c: 0207f793 andi a5,a5,32 1a000640: ffe5 bnez a5,1a000638 1a000642: 1c003a37 lui s4,0x1c003 @@ -759,11 +759,11 @@ default_handler: 1a000722: 02500713 li a4,37 1a000726: 02f77763 bgeu a4,a5,1a000754 1a00072a: 1a001537 lui a0,0x1a001 -1a00072e: 62450513 addi a0,a0,1572 # 1a001624 <__clz_tab+0x100> +1a00072e: 67450513 addi a0,a0,1652 # 1a001674 <__clz_tab+0x100> 1a000732: 376d jal 1a0006dc 1a000734: 000a0763 beqz s4,1a000742 1a000738: 1a001537 lui a0,0x1a001 -1a00073c: 65c50513 addi a0,a0,1628 # 1a00165c <__clz_tab+0x138> +1a00073c: 6ac50513 addi a0,a0,1708 # 1a0016ac <__clz_tab+0x138> 1a000740: 3f71 jal 1a0006dc 1a000742: fff48793 addi a5,s1,-1 1a000746: 4709 li a4,2 @@ -772,7 +772,7 @@ default_handler: 1a00074e: 0297f263 bgeu a5,s1,1a000772 1a000752: 8402 jr s0 1a000754: 1a001537 lui a0,0x1a001 -1a000758: 64050513 addi a0,a0,1600 # 1a001640 <__clz_tab+0x11c> +1a000758: 69050513 addi a0,a0,1680 # 1a001690 <__clz_tab+0x11c> 1a00075c: bfd9 j 1a000732 1a00075e: 00f986b3 add a3,s3,a5 1a000762: 0006c683 lbu a3,0(a3) @@ -859,7 +859,7 @@ default_handler: 1a00082c: d0ea sw s10,96(sp) 1a00082e: 8caa mv s9,a0 1a000830: 1c0034b7 lui s1,0x1c003 -1a000834: 3b8a8a93 addi s5,s5,952 # 1a0013b8 <_endtext> +1a000834: 408a8a93 addi s5,s5,1032 # 1a001408 <_endtext> 1a000838: 1c0039b7 lui s3,0x1c003 1a00083c: 4b05 li s6,1 1a00083e: 4b85 li s7,1 @@ -1021,7 +1021,7 @@ default_handler: 1a0009ba: 4795 li a5,5 1a0009bc: 00a7ef63 bltu a5,a0,1a0009da 1a0009c0: 1a0017b7 lui a5,0x1a001 -1a0009c4: 44078793 addi a5,a5,1088 # 1a001440 <_endtext+0x88> +1a0009c4: 49078793 addi a5,a5,1168 # 1a001490 <_endtext+0x88> 1a0009c8: 050a slli a0,a0,0x2 1a0009ca: 953e add a0,a0,a5 1a0009cc: 411c lw a5,0(a0) @@ -1036,7 +1036,7 @@ default_handler: 1a0009e2: 1a0015b7 lui a1,0x1a001 1a0009e6: 842a mv s0,a0 1a0009e8: 02500613 li a2,37 -1a0009ec: 67858593 addi a1,a1,1656 # 1a001678 <__clz_tab+0x154> +1a0009ec: 6c858593 addi a1,a1,1736 # 1a0016c8 <__clz_tab+0x154> 1a0009f0: 1848 addi a0,sp,52 1a0009f2: 3129 jal 1a0005fc 1a0009f4: 105c addi a5,sp,36 @@ -1293,7 +1293,7 @@ default_handler: 1a000c9c: d85a sw s6,48(sp) 1a000c9e: d65e sw s7,44(sp) 1a000ca0: d462 sw s8,40(sp) -1a000ca2: 6a2000ef jal ra,1a001344 +1a000ca2: 6f2000ef jal ra,1a001394 1a000ca6: 892a mv s2,a0 1a000ca8: 26051263 bnez a0,1a000f0c 1a000cac: 1c0029b7 lui s3,0x1c002 @@ -1543,7 +1543,7 @@ default_handler: 1a000f74: 40c9a783 lw a5,1036(s3) 1a000f78: 02fded63 bltu s11,a5,1a000fb2 1a000f7c: 1a1026b7 lui a3,0x1a102 -1a000f80: 0a46a783 lw a5,164(a3) # 1a1020a4 <__clz_tab+0x100b80> +1a000f80: 0a46a783 lw a5,164(a3) # 1a1020a4 <__clz_tab+0x100b30> 1a000f84: 577d li a4,-1 1a000f86: 0af6a223 sw a5,164(a3) 1a000f8a: 1a1067b7 lui a5,0x1a106 @@ -1644,7 +1644,7 @@ default_handler: 1a001068: 02000693 li a3,32 1a00106c: 40f686b3 sub a3,a3,a5 1a001070: 00f55533 srl a0,a0,a5 -1a001074: 52470793 addi a5,a4,1316 # 1a001524 <__clz_tab> +1a001074: 57470793 addi a5,a4,1396 # 1a001574 <__clz_tab> 1a001078: 00a78533 add a0,a5,a0 1a00107c: 00054503 lbu a0,0(a0) 1a001080: 40a68533 sub a0,a3,a0 @@ -1678,21 +1678,21 @@ default_handler: 1a0010bc: 57fd li a5,-1 1a0010be: 30479073 csrw mie,a5 1a0010c2: 1a1047b7 lui a5,0x1a104 -1a0010c6: 0c47a783 lw a5,196(a5) # 1a1040c4 <__clz_tab+0x102ba0> +1a0010c6: 0c47a783 lw a5,196(a5) # 1a1040c4 <__clz_tab+0x102b50> 1a0010ca: 4709 li a4,2 1a0010cc: 8b8d andi a5,a5,3 -1a0010ce: 26e78863 beq a5,a4,1a00133e +1a0010ce: 28e78663 beq a5,a4,1a00135a 1a0010d2: 470d li a4,3 -1a0010d4: 26e78763 beq a5,a4,1a001342 +1a0010d4: 2ae78f63 beq a5,a4,1a001392 1a0010d8: 4705 li a4,1 -1a0010da: 24e78f63 beq a5,a4,1a001338 +1a0010da: 26e78d63 beq a5,a4,1a001354 1a0010de: 1c003637 lui a2,0x1c003 1a0010e2: da860793 addi a5,a2,-600 # 1c002da8 1a0010e6: 1c003437 lui s0,0x1c003 1a0010ea: 0007a023 sw zero,0(a5) 1a0010ee: 0007a223 sw zero,4(a5) 1a0010f2: da041223 sh zero,-604(s0) # 1c002da4 -1a0010f6: 1a1006b7 lui a3,0x1a100 +1a0010f6: 1a1206b7 lui a3,0x1a120 1a0010fa: 4ad8 lw a4,20(a3) 1a0010fc: da860613 addi a2,a2,-600 1a001100: 87ba mv a5,a4 @@ -1720,7 +1720,7 @@ default_handler: 1a001142: 8fcd or a5,a5,a1 1a001144: cadc sw a5,20(a3) 1a001146: 4248 lw a0,4(a2) -1a001148: 10050f63 beqz a0,1a001266 +1a001148: 12050d63 beqz a0,1a001282 1a00114c: 9a4ff0ef jal ra,1a0002f0 1a001150: 0112b537 lui a0,0x112b 1a001154: 4785 li a5,1 @@ -1728,245 +1728,271 @@ default_handler: 1a00115a: 88050513 addi a0,a0,-1920 # 112a880 <__stack_size+0x112a080> 1a00115e: 00f400a3 sb a5,1(s0) 1a001162: 98eff0ef jal ra,1a0002f0 -1a001166: f5dfe0ef jal ra,1a0000c2 -1a00116a: 1a001537 lui a0,0x1a001 -1a00116e: 1c0037b7 lui a5,0x1c003 -1a001172: 6a050513 addi a0,a0,1696 # 1a0016a0 <__clz_tab+0x17c> -1a001176: da07aa23 sw zero,-588(a5) # 1c002db4 -1a00117a: d62ff0ef jal ra,1a0006dc -1a00117e: 1c0027b7 lui a5,0x1c002 -1a001182: 4751 li a4,20 -1a001184: d8e7a823 sw a4,-624(a5) # 1c001d90 -1a001188: 1c003737 lui a4,0x1c003 -1a00118c: d9078793 addi a5,a5,-624 -1a001190: 1a001437 lui s0,0x1a001 -1a001194: d8072e23 sw zero,-612(a4) # 1c002d9c -1a001198: 1c003737 lui a4,0x1c003 -1a00119c: 48440493 addi s1,s0,1156 # 1a001484 -1a0011a0: 0007a423 sw zero,8(a5) -1a0011a4: 0007a223 sw zero,4(a5) -1a0011a8: da072023 sw zero,-608(a4) # 1c002da0 -1a0011ac: 0007a623 sw zero,12(a5) -1a0011b0: 4901 li s2,0 -1a0011b2: 48440413 addi s0,s0,1156 -1a0011b6: 05f00a13 li s4,95 -1a0011ba: 0004c783 lbu a5,0(s1) -1a0011be: efd5 bnez a5,1a00127a -1a0011c0: 4481 li s1,0 -1a0011c2: 07c40413 addi s0,s0,124 -1a0011c6: 4581 li a1,0 -1a0011c8: 8522 mv a0,s0 -1a0011ca: b16ff0ef jal ra,1a0004e0 -1a0011ce: 4505 li a0,1 -1a0011d0: b0cff0ef jal ra,1a0004dc -1a0011d4: 8526 mv a0,s1 -1a0011d6: b06ff0ef jal ra,1a0004dc -1a0011da: 4501 li a0,0 -1a0011dc: b00ff0ef jal ra,1a0004dc -1a0011e0: 8522 mv a0,s0 -1a0011e2: f0dfe0ef jal ra,1a0000ee -1a0011e6: 0505 addi a0,a0,1 -1a0011e8: 942a add s0,s0,a0 -1a0011ea: 00044783 lbu a5,0(s0) -1a0011ee: 0485 addi s1,s1,1 -1a0011f0: fbf9 bnez a5,1a0011c6 -1a0011f2: 1a001537 lui a0,0x1a001 -1a0011f6: 6b450513 addi a0,a0,1716 # 1a0016b4 <__clz_tab+0x190> -1a0011fa: ce2ff0ef jal ra,1a0006dc -1a0011fe: 1a001537 lui a0,0x1a001 -1a001202: 6bc50513 addi a0,a0,1724 # 1a0016bc <__clz_tab+0x198> -1a001206: a7dff0ef jal ra,1a000c82 -1a00120a: 1a001537 lui a0,0x1a001 -1a00120e: 1c0024b7 lui s1,0x1c002 -1a001212: 6c850513 addi a0,a0,1736 # 1a0016c8 <__clz_tab+0x1a4> -1a001216: 93048493 addi s1,s1,-1744 # 1c001930 -1a00121a: 1a001937 lui s2,0x1a001 -1a00121e: a65ff0ef jal ra,1a000c82 -1a001222: 4401 li s0,0 -1a001224: 36048993 addi s3,s1,864 -1a001228: 1a001a37 lui s4,0x1a001 -1a00122c: 45890913 addi s2,s2,1112 # 1a001458 <_endtext+0xa0> -1a001230: 1a001ab7 lui s5,0x1a001 -1a001234: 1a001b37 lui s6,0x1a001 -1a001238: 1a001bb7 lui s7,0x1a001 -1a00123c: e51fe0ef jal ra,1a00008c -1a001240: 8c2a mv s8,a0 -1a001242: c54ff0ef jal ra,1a000696 -1a001246: 47a9 li a5,10 -1a001248: 00fc0563 beq s8,a5,1a001252 -1a00124c: 47b5 li a5,13 -1a00124e: 0cfc1563 bne s8,a5,1a001318 -1a001252: 854e mv a0,s3 -1a001254: a2fff0ef jal ra,1a000c82 -1a001258: 47a9 li a5,10 -1a00125a: 0aa7ec63 bltu a5,a0,1a001312 -1a00125e: 050a slli a0,a0,0x2 -1a001260: 954a add a0,a0,s2 -1a001262: 411c lw a5,0(a0) -1a001264: 8782 jr a5 -1a001266: 0742 slli a4,a4,0x10 -1a001268: 83e9 srli a5,a5,0x1a -1a00126a: 8341 srli a4,a4,0x10 -1a00126c: 8bbd andi a5,a5,15 -1a00126e: 073e slli a4,a4,0xf -1a001270: 17fd addi a5,a5,-1 -1a001272: 00f757b3 srl a5,a4,a5 -1a001276: c25c sw a5,4(a2) -1a001278: bde1 j 1a001150 -1a00127a: 03479a63 bne a5,s4,1a0012ae -1a00127e: 00148513 addi a0,s1,1 -1a001282: 4985 li s3,1 -1a001284: 02000593 li a1,32 -1a001288: a58ff0ef jal ra,1a0004e0 -1a00128c: 854a mv a0,s2 -1a00128e: a4eff0ef jal ra,1a0004dc -1a001292: 4501 li a0,0 -1a001294: a48ff0ef jal ra,1a0004dc -1a001298: 00098463 beqz s3,1a0012a0 -1a00129c: 9f2ff0ef jal ra,1a00048e -1a0012a0: 8526 mv a0,s1 -1a0012a2: e4dfe0ef jal ra,1a0000ee -1a0012a6: 0505 addi a0,a0,1 -1a0012a8: 94aa add s1,s1,a0 -1a0012aa: 0905 addi s2,s2,1 -1a0012ac: b739 j 1a0011ba -1a0012ae: 8526 mv a0,s1 -1a0012b0: 4981 li s3,0 -1a0012b2: bfc9 j 1a001284 -1a0012b4: 1a001537 lui a0,0x1a001 -1a0012b8: 6dc50513 addi a0,a0,1756 # 1a0016dc <__clz_tab+0x1b8> -1a0012bc: c20ff0ef jal ra,1a0006dc -1a0012c0: 4401 li s0,0 -1a0012c2: a0b5 j 1a00132e -1a0012c4: 1a001537 lui a0,0x1a001 -1a0012c8: 6e850513 addi a0,a0,1768 # 1a0016e8 <__clz_tab+0x1c4> -1a0012cc: bfc5 j 1a0012bc -1a0012ce: 1a001537 lui a0,0x1a001 -1a0012d2: 6f450513 addi a0,a0,1780 # 1a0016f4 <__clz_tab+0x1d0> -1a0012d6: b7dd j 1a0012bc -1a0012d8: 1a001537 lui a0,0x1a001 -1a0012dc: 70050513 addi a0,a0,1792 # 1a001700 <__clz_tab+0x1dc> -1a0012e0: bff1 j 1a0012bc -1a0012e2: 1a001537 lui a0,0x1a001 -1a0012e6: 70c50513 addi a0,a0,1804 # 1a00170c <__clz_tab+0x1e8> -1a0012ea: bfc9 j 1a0012bc -1a0012ec: 1a001537 lui a0,0x1a001 -1a0012f0: 71850513 addi a0,a0,1816 # 1a001718 <__clz_tab+0x1f4> -1a0012f4: b7e1 j 1a0012bc -1a0012f6: 1a001537 lui a0,0x1a001 -1a0012fa: 72850513 addi a0,a0,1832 # 1a001728 <__clz_tab+0x204> -1a0012fe: bf7d j 1a0012bc -1a001300: 738b8513 addi a0,s7,1848 # 1a001738 <__clz_tab+0x214> -1a001304: bf65 j 1a0012bc -1a001306: 744b0513 addi a0,s6,1860 # 1a001744 <__clz_tab+0x220> -1a00130a: bf4d j 1a0012bc -1a00130c: 750a8513 addi a0,s5,1872 # 1a001750 <__clz_tab+0x22c> -1a001310: b775 j 1a0012bc -1a001312: 764a0513 addi a0,s4,1892 # 1a001764 <__clz_tab+0x240> -1a001316: b75d j 1a0012bc -1a001318: 0ff00793 li a5,255 -1a00131c: 00f40963 beq s0,a5,1a00132e -1a001320: 00140793 addi a5,s0,1 -1a001324: 9426 add s0,s0,s1 -1a001326: 37840023 sb s8,864(s0) -1a00132a: 0ff7f413 andi s0,a5,255 -1a00132e: 008487b3 add a5,s1,s0 -1a001332: 36078023 sb zero,864(a5) -1a001336: b719 j 1a00123c -1a001338: 10500073 wfi -1a00133c: bff5 j 1a001338 -1a00133e: eabfe0ef jal ra,1a0001e8 -1a001342: 3ba9 jal 1a00109c +1a001166: 1a121737 lui a4,0x1a121 +1a00116a: 471c lw a5,8(a4) +1a00116c: 1a001437 lui s0,0x1a001 +1a001170: 4d440493 addi s1,s0,1236 # 1a0014d4 +1a001174: fc07f793 andi a5,a5,-64 +1a001178: 0397e793 ori a5,a5,57 +1a00117c: c71c sw a5,8(a4) +1a00117e: 4b1c lw a5,16(a4) +1a001180: 4901 li s2,0 +1a001182: 4d440413 addi s0,s0,1236 +1a001186: fc07f793 andi a5,a5,-64 +1a00118a: 0387e793 ori a5,a5,56 +1a00118e: cb1c sw a5,16(a4) +1a001190: f33fe0ef jal ra,1a0000c2 +1a001194: 1a001537 lui a0,0x1a001 +1a001198: 1c0037b7 lui a5,0x1c003 +1a00119c: 6f050513 addi a0,a0,1776 # 1a0016f0 <__clz_tab+0x17c> +1a0011a0: da07aa23 sw zero,-588(a5) # 1c002db4 +1a0011a4: d38ff0ef jal ra,1a0006dc +1a0011a8: 1c0027b7 lui a5,0x1c002 +1a0011ac: 4751 li a4,20 +1a0011ae: d8e7a823 sw a4,-624(a5) # 1c001d90 +1a0011b2: 1c003737 lui a4,0x1c003 +1a0011b6: d9078793 addi a5,a5,-624 +1a0011ba: d8072e23 sw zero,-612(a4) # 1c002d9c +1a0011be: 1c003737 lui a4,0x1c003 +1a0011c2: 0007a423 sw zero,8(a5) +1a0011c6: 0007a223 sw zero,4(a5) +1a0011ca: da072023 sw zero,-608(a4) # 1c002da0 +1a0011ce: 0007a623 sw zero,12(a5) +1a0011d2: 05f00a13 li s4,95 +1a0011d6: 0004c783 lbu a5,0(s1) +1a0011da: efd5 bnez a5,1a001296 +1a0011dc: 4481 li s1,0 +1a0011de: 07c40413 addi s0,s0,124 +1a0011e2: 4581 li a1,0 +1a0011e4: 8522 mv a0,s0 +1a0011e6: afaff0ef jal ra,1a0004e0 +1a0011ea: 4505 li a0,1 +1a0011ec: af0ff0ef jal ra,1a0004dc +1a0011f0: 8526 mv a0,s1 +1a0011f2: aeaff0ef jal ra,1a0004dc +1a0011f6: 4501 li a0,0 +1a0011f8: ae4ff0ef jal ra,1a0004dc +1a0011fc: 8522 mv a0,s0 +1a0011fe: ef1fe0ef jal ra,1a0000ee +1a001202: 0505 addi a0,a0,1 +1a001204: 942a add s0,s0,a0 +1a001206: 00044783 lbu a5,0(s0) +1a00120a: 0485 addi s1,s1,1 +1a00120c: fbf9 bnez a5,1a0011e2 +1a00120e: 1a001537 lui a0,0x1a001 +1a001212: 70450513 addi a0,a0,1796 # 1a001704 <__clz_tab+0x190> +1a001216: cc6ff0ef jal ra,1a0006dc +1a00121a: 1a001537 lui a0,0x1a001 +1a00121e: 70c50513 addi a0,a0,1804 # 1a00170c <__clz_tab+0x198> +1a001222: a61ff0ef jal ra,1a000c82 +1a001226: 1a001537 lui a0,0x1a001 +1a00122a: 1c0024b7 lui s1,0x1c002 +1a00122e: 71850513 addi a0,a0,1816 # 1a001718 <__clz_tab+0x1a4> +1a001232: 93048493 addi s1,s1,-1744 # 1c001930 +1a001236: 1a001937 lui s2,0x1a001 +1a00123a: a49ff0ef jal ra,1a000c82 +1a00123e: 4401 li s0,0 +1a001240: 36048993 addi s3,s1,864 +1a001244: 1a001a37 lui s4,0x1a001 +1a001248: 4a890913 addi s2,s2,1192 # 1a0014a8 <_endtext+0xa0> +1a00124c: 1a001ab7 lui s5,0x1a001 +1a001250: 1a001b37 lui s6,0x1a001 +1a001254: 1a001bb7 lui s7,0x1a001 +1a001258: e35fe0ef jal ra,1a00008c +1a00125c: 8c2a mv s8,a0 +1a00125e: c38ff0ef jal ra,1a000696 +1a001262: 47a9 li a5,10 +1a001264: 00fc0563 beq s8,a5,1a00126e +1a001268: 47b5 li a5,13 +1a00126a: 0cfc1563 bne s8,a5,1a001334 +1a00126e: 854e mv a0,s3 +1a001270: a13ff0ef jal ra,1a000c82 +1a001274: 47a9 li a5,10 +1a001276: 0aa7ec63 bltu a5,a0,1a00132e +1a00127a: 050a slli a0,a0,0x2 +1a00127c: 954a add a0,a0,s2 +1a00127e: 411c lw a5,0(a0) +1a001280: 8782 jr a5 +1a001282: 0742 slli a4,a4,0x10 +1a001284: 83e9 srli a5,a5,0x1a +1a001286: 8341 srli a4,a4,0x10 +1a001288: 8bbd andi a5,a5,15 +1a00128a: 073e slli a4,a4,0xf +1a00128c: 17fd addi a5,a5,-1 +1a00128e: 00f757b3 srl a5,a4,a5 +1a001292: c25c sw a5,4(a2) +1a001294: bd75 j 1a001150 +1a001296: 03479a63 bne a5,s4,1a0012ca +1a00129a: 00148513 addi a0,s1,1 +1a00129e: 4985 li s3,1 +1a0012a0: 02000593 li a1,32 +1a0012a4: a3cff0ef jal ra,1a0004e0 +1a0012a8: 854a mv a0,s2 +1a0012aa: a32ff0ef jal ra,1a0004dc +1a0012ae: 4501 li a0,0 +1a0012b0: a2cff0ef jal ra,1a0004dc +1a0012b4: 00098463 beqz s3,1a0012bc +1a0012b8: 9d6ff0ef jal ra,1a00048e +1a0012bc: 8526 mv a0,s1 +1a0012be: e31fe0ef jal ra,1a0000ee +1a0012c2: 0505 addi a0,a0,1 +1a0012c4: 94aa add s1,s1,a0 +1a0012c6: 0905 addi s2,s2,1 +1a0012c8: b739 j 1a0011d6 +1a0012ca: 8526 mv a0,s1 +1a0012cc: 4981 li s3,0 +1a0012ce: bfc9 j 1a0012a0 +1a0012d0: 1a001537 lui a0,0x1a001 +1a0012d4: 72c50513 addi a0,a0,1836 # 1a00172c <__clz_tab+0x1b8> +1a0012d8: c04ff0ef jal ra,1a0006dc +1a0012dc: 4401 li s0,0 +1a0012de: a0b5 j 1a00134a +1a0012e0: 1a001537 lui a0,0x1a001 +1a0012e4: 73850513 addi a0,a0,1848 # 1a001738 <__clz_tab+0x1c4> +1a0012e8: bfc5 j 1a0012d8 +1a0012ea: 1a001537 lui a0,0x1a001 +1a0012ee: 74450513 addi a0,a0,1860 # 1a001744 <__clz_tab+0x1d0> +1a0012f2: b7dd j 1a0012d8 +1a0012f4: 1a001537 lui a0,0x1a001 +1a0012f8: 75050513 addi a0,a0,1872 # 1a001750 <__clz_tab+0x1dc> +1a0012fc: bff1 j 1a0012d8 +1a0012fe: 1a001537 lui a0,0x1a001 +1a001302: 75c50513 addi a0,a0,1884 # 1a00175c <__clz_tab+0x1e8> +1a001306: bfc9 j 1a0012d8 +1a001308: 1a001537 lui a0,0x1a001 +1a00130c: 76850513 addi a0,a0,1896 # 1a001768 <__clz_tab+0x1f4> +1a001310: b7e1 j 1a0012d8 +1a001312: 1a001537 lui a0,0x1a001 +1a001316: 77850513 addi a0,a0,1912 # 1a001778 <__clz_tab+0x204> +1a00131a: bf7d j 1a0012d8 +1a00131c: 788b8513 addi a0,s7,1928 # 1a001788 <__clz_tab+0x214> +1a001320: bf65 j 1a0012d8 +1a001322: 794b0513 addi a0,s6,1940 # 1a001794 <__clz_tab+0x220> +1a001326: bf4d j 1a0012d8 +1a001328: 7a0a8513 addi a0,s5,1952 # 1a0017a0 <__clz_tab+0x22c> +1a00132c: b775 j 1a0012d8 +1a00132e: 7b4a0513 addi a0,s4,1972 # 1a0017b4 <__clz_tab+0x240> +1a001332: b75d j 1a0012d8 +1a001334: 0ff00793 li a5,255 +1a001338: 00f40963 beq s0,a5,1a00134a +1a00133c: 00140793 addi a5,s0,1 +1a001340: 9426 add s0,s0,s1 +1a001342: 37840023 sb s8,864(s0) +1a001346: 0ff7f413 andi s0,a5,255 +1a00134a: 008487b3 add a5,s1,s0 +1a00134e: 36078023 sb zero,864(a5) +1a001352: b719 j 1a001258 +1a001354: 10500073 wfi +1a001358: bff5 j 1a001354 +1a00135a: 1a1217b7 lui a5,0x1a121 +1a00135e: 4f98 lw a4,24(a5) +1a001360: fc077713 andi a4,a4,-64 +1a001364: 01d76713 ori a4,a4,29 +1a001368: cf98 sw a4,24(a5) +1a00136a: 5398 lw a4,32(a5) +1a00136c: fc077713 andi a4,a4,-64 +1a001370: 01976713 ori a4,a4,25 +1a001374: d398 sw a4,32(a5) +1a001376: 5798 lw a4,40(a5) +1a001378: fc077713 andi a4,a4,-64 +1a00137c: 01e76713 ori a4,a4,30 +1a001380: d798 sw a4,40(a5) +1a001382: 5b98 lw a4,48(a5) +1a001384: fc077713 andi a4,a4,-64 +1a001388: 01f76713 ori a4,a4,31 +1a00138c: db98 sw a4,48(a5) +1a00138e: e5bfe0ef jal ra,1a0001e8 +1a001392: 3329 jal 1a00109c -1a001344 : +1a001394 : /* int setjmp (jmp_buf); */ .section .text.setjmp .globl setjmp .type setjmp, @function setjmp: REG_S ra, 0*SZREG(a0) -1a001344: 00152023 sw ra,0(a0) +1a001394: 00152023 sw ra,0(a0) REG_S s0, 1*SZREG(a0) -1a001348: c140 sw s0,4(a0) +1a001398: c140 sw s0,4(a0) REG_S s1, 2*SZREG(a0) -1a00134a: c504 sw s1,8(a0) +1a00139a: c504 sw s1,8(a0) #ifndef __riscv_32e REG_S s2, 3*SZREG(a0) -1a00134c: 01252623 sw s2,12(a0) +1a00139c: 01252623 sw s2,12(a0) REG_S s3, 4*SZREG(a0) -1a001350: 01352823 sw s3,16(a0) +1a0013a0: 01352823 sw s3,16(a0) REG_S s4, 5*SZREG(a0) -1a001354: 01452a23 sw s4,20(a0) +1a0013a4: 01452a23 sw s4,20(a0) REG_S s5, 6*SZREG(a0) -1a001358: 01552c23 sw s5,24(a0) +1a0013a8: 01552c23 sw s5,24(a0) REG_S s6, 7*SZREG(a0) -1a00135c: 01652e23 sw s6,28(a0) +1a0013ac: 01652e23 sw s6,28(a0) REG_S s7, 8*SZREG(a0) -1a001360: 03752023 sw s7,32(a0) +1a0013b0: 03752023 sw s7,32(a0) REG_S s8, 9*SZREG(a0) -1a001364: 03852223 sw s8,36(a0) +1a0013b4: 03852223 sw s8,36(a0) REG_S s9, 10*SZREG(a0) -1a001368: 03952423 sw s9,40(a0) +1a0013b8: 03952423 sw s9,40(a0) REG_S s10,11*SZREG(a0) -1a00136c: 03a52623 sw s10,44(a0) +1a0013bc: 03a52623 sw s10,44(a0) REG_S s11,12*SZREG(a0) -1a001370: 03b52823 sw s11,48(a0) +1a0013c0: 03b52823 sw s11,48(a0) REG_S sp, 13*SZREG(a0) -1a001374: 02252a23 sw sp,52(a0) +1a0013c4: 02252a23 sw sp,52(a0) FREG_S fs9, 14*SZREG+ 9*SZFREG(a0) FREG_S fs10,14*SZREG+10*SZFREG(a0) FREG_S fs11,14*SZREG+11*SZFREG(a0) #endif li a0, 0 -1a001378: 4501 li a0,0 +1a0013c8: 4501 li a0,0 ret -1a00137a: 8082 ret +1a0013ca: 8082 ret -1a00137c : +1a0013cc : /* volatile void longjmp (jmp_buf, int); */ .section .text.longjmp .globl longjmp .type longjmp, @function longjmp: REG_L ra, 0*SZREG(a0) -1a00137c: 00052083 lw ra,0(a0) +1a0013cc: 00052083 lw ra,0(a0) REG_L s0, 1*SZREG(a0) -1a001380: 4140 lw s0,4(a0) +1a0013d0: 4140 lw s0,4(a0) REG_L s1, 2*SZREG(a0) -1a001382: 4504 lw s1,8(a0) +1a0013d2: 4504 lw s1,8(a0) #ifndef __riscv_32e REG_L s2, 3*SZREG(a0) -1a001384: 00c52903 lw s2,12(a0) +1a0013d4: 00c52903 lw s2,12(a0) REG_L s3, 4*SZREG(a0) -1a001388: 01052983 lw s3,16(a0) +1a0013d8: 01052983 lw s3,16(a0) REG_L s4, 5*SZREG(a0) -1a00138c: 01452a03 lw s4,20(a0) +1a0013dc: 01452a03 lw s4,20(a0) REG_L s5, 6*SZREG(a0) -1a001390: 01852a83 lw s5,24(a0) +1a0013e0: 01852a83 lw s5,24(a0) REG_L s6, 7*SZREG(a0) -1a001394: 01c52b03 lw s6,28(a0) +1a0013e4: 01c52b03 lw s6,28(a0) REG_L s7, 8*SZREG(a0) -1a001398: 02052b83 lw s7,32(a0) +1a0013e8: 02052b83 lw s7,32(a0) REG_L s8, 9*SZREG(a0) -1a00139c: 02452c03 lw s8,36(a0) +1a0013ec: 02452c03 lw s8,36(a0) REG_L s9, 10*SZREG(a0) -1a0013a0: 02852c83 lw s9,40(a0) +1a0013f0: 02852c83 lw s9,40(a0) REG_L s10,11*SZREG(a0) -1a0013a4: 02c52d03 lw s10,44(a0) +1a0013f4: 02c52d03 lw s10,44(a0) REG_L s11,12*SZREG(a0) -1a0013a8: 03052d83 lw s11,48(a0) +1a0013f8: 03052d83 lw s11,48(a0) REG_L sp, 13*SZREG(a0) -1a0013ac: 03452103 lw sp,52(a0) +1a0013fc: 03452103 lw sp,52(a0) FREG_L fs9, 14*SZREG+ 9*SZFREG(a0) FREG_L fs10,14*SZREG+10*SZFREG(a0) FREG_L fs11,14*SZREG+11*SZFREG(a0) #endif seqz a0, a1 -1a0013b0: 0015b513 seqz a0,a1 +1a001400: 0015b513 seqz a0,a1 add a0, a0, a1 # a0 = (a1 == 0) ? 1 : a1 -1a0013b4: 952e add a0,a0,a1 +1a001404: 952e add a0,a0,a1 ret -1a0013b6: 8082 ret +1a001406: 8082 ret diff --git a/boot/boot_code_fpga.objdump b/sw/bootcode/boot_code_fpga.objdump similarity index 87% rename from boot/boot_code_fpga.objdump rename to sw/bootcode/boot_code_fpga.objdump index 7e1c1bf4..e5bed0d7 100644 --- a/boot/boot_code_fpga.objdump +++ b/sw/bootcode/boot_code_fpga.objdump @@ -95,7 +95,7 @@ default_handler: 1a00008c : 1a00008c: 1a1027b7 lui a5,0x1a102 -1a000090: 0a87a703 lw a4,168(a5) # 1a1020a8 <__clz_tab+0x100b84> +1a000090: 0a87a703 lw a4,168(a5) # 1a1020a8 <__clz_tab+0x100b34> 1a000094: 8b05 andi a4,a4,1 1a000096: cb19 beqz a4,1a0000ac 1a000098: 0a47a703 lw a4,164(a5) @@ -104,7 +104,7 @@ default_handler: 1a0000a4: fdf00713 li a4,-33 1a0000a8: 0ae7a223 sw a4,164(a5) 1a0000ac: 1a102737 lui a4,0x1a102 -1a0000b0: 0b072783 lw a5,176(a4) # 1a1020b0 <__clz_tab+0x100b8c> +1a0000b0: 0b072783 lw a5,176(a4) # 1a1020b0 <__clz_tab+0x100b3c> 1a0000b4: 8b85 andi a5,a5,1 1a0000b6: dfed beqz a5,1a0000b0 1a0000b8: 0b472503 lw a0,180(a4) @@ -126,7 +126,7 @@ default_handler: 1a0000de: c3d4 sw a3,4(a5) 1a0000e0: 009b07b7 lui a5,0x9b0 1a0000e4: 31678793 addi a5,a5,790 # 9b0316 <__stack_size+0x9afb16> -1a0000e8: 0af72223 sw a5,164(a4) # 1a1020a4 <__clz_tab+0x100b80> +1a0000e8: 0af72223 sw a5,164(a4) # 1a1020a4 <__clz_tab+0x100b30> 1a0000ec: 8082 ret 1a0000ee : @@ -168,7 +168,7 @@ default_handler: 1a00014c: 0785 addi a5,a5,1 1a00014e: cd1c sw a5,24(a0) 1a000150: 1a1027b7 lui a5,0x1a102 -1a000154: 10c7a023 sw a2,256(a5) # 1a102100 <__clz_tab+0x100bdc> +1a000154: 10c7a023 sw a2,256(a5) # 1a102100 <__clz_tab+0x100b8c> 1a000158: 10d7a223 sw a3,260(a5) 1a00015c: 4751 li a4,20 1a00015e: 10e7a423 sw a4,264(a5) @@ -178,7 +178,7 @@ default_handler: 1a00016c: 12e7a423 sw a4,296(a5) 1a000170: 1a10a7b7 lui a5,0x1a10a 1a000174: 04000737 lui a4,0x4000 -1a000178: 80e7a223 sw a4,-2044(a5) # 1a109804 <__clz_tab+0x1082e0> +1a000178: 80e7a223 sw a4,-2044(a5) # 1a109804 <__clz_tab+0x108290> 1a00017c: 80c7a683 lw a3,-2036(a5) 1a000180: 00569613 slli a2,a3,0x5 1a000184: 00065963 bgez a2,1a000196 @@ -264,7 +264,7 @@ default_handler: 1a000242: c3d8 sw a4,4(a5) 1a000244: 1a10a7b7 lui a5,0x1a10a 1a000248: 6711 lui a4,0x4 -1a00024a: 80e7a223 sw a4,-2044(a5) # 1a109804 <__clz_tab+0x1082e0> +1a00024a: 80e7a223 sw a4,-2044(a5) # 1a109804 <__clz_tab+0x108290> 1a00024e: 81478713 addi a4,a5,-2028 1a000252: 10500073 wfi 1a000256: c314 sw a3,0(a4) @@ -323,7 +323,7 @@ default_handler: 1a0002f4: c606 sw ra,12(sp) 1a0002f6: 842a mv s0,a0 1a0002f8: 559000ef jal ra,1a001050 <__clzsi2> -1a0002fc: ffe50793 addi a5,a0,-2 # 1bfffffe <__clz_tab+0x1ffeada> +1a0002fc: ffe50793 addi a5,a0,-2 # 1bfffffe <__clz_tab+0x1ffea8a> 1a000300: 8385 srli a5,a5,0x1 1a000302: e391 bnez a5,1a000306 1a000304: 4785 li a5,1 @@ -340,7 +340,7 @@ default_handler: 1a000326: 1c0036b7 lui a3,0x1c003 1a00032a: da56c683 lbu a3,-603(a3) # 1c002da5 1a00032e: c29d beqz a3,1a000354 -1a000330: 1a100637 lui a2,0x1a100 +1a000330: 1a120637 lui a2,0x1a120 1a000334: 4a54 lw a3,20(a2) 1a000336: 833d srli a4,a4,0xf 1a000338: 0742 slli a4,a4,0x10 @@ -367,7 +367,7 @@ default_handler: 1a000362: 1141 addi sp,sp,-16 1a000364: 93050513 addi a0,a0,-1744 # 1c001930 1a000368: c606 sw ra,12(sp) -1a00036a: 012010ef jal ra,1a00137c +1a00036a: 062010ef jal ra,1a0013cc 1a00036e : 1a00036e: 1141 addi sp,sp,-16 @@ -635,7 +635,7 @@ default_handler: 1a0005ec: 800007b7 lui a5,0x80000 1a0005f0: 8d5d or a0,a0,a5 1a0005f2: 1a1047b7 lui a5,0x1a104 -1a0005f6: 0aa7a023 sw a0,160(a5) # 1a1040a0 <__clz_tab+0x102b7c> +1a0005f6: 0aa7a023 sw a0,160(a5) # 1a1040a0 <__clz_tab+0x102b2c> 1a0005fa: a001 j 1a0005fa 1a0005fc : @@ -663,7 +663,7 @@ default_handler: 1a000630: c05a sw s6,0(sp) 1a000632: 843e mv s0,a5 1a000634: 1a102937 lui s2,0x1a102 -1a000638: 09892783 lw a5,152(s2) # 1a102098 <__clz_tab+0x100b74> +1a000638: 09892783 lw a5,152(s2) # 1a102098 <__clz_tab+0x100b24> 1a00063c: 0207f793 andi a5,a5,32 1a000640: ffe5 bnez a5,1a000638 1a000642: 1c003a37 lui s4,0x1c003 @@ -759,11 +759,11 @@ default_handler: 1a000722: 02500713 li a4,37 1a000726: 02f77763 bgeu a4,a5,1a000754 1a00072a: 1a001537 lui a0,0x1a001 -1a00072e: 62450513 addi a0,a0,1572 # 1a001624 <__clz_tab+0x100> +1a00072e: 67450513 addi a0,a0,1652 # 1a001674 <__clz_tab+0x100> 1a000732: 376d jal 1a0006dc 1a000734: 000a0763 beqz s4,1a000742 1a000738: 1a001537 lui a0,0x1a001 -1a00073c: 65c50513 addi a0,a0,1628 # 1a00165c <__clz_tab+0x138> +1a00073c: 6ac50513 addi a0,a0,1708 # 1a0016ac <__clz_tab+0x138> 1a000740: 3f71 jal 1a0006dc 1a000742: fff48793 addi a5,s1,-1 1a000746: 4709 li a4,2 @@ -772,7 +772,7 @@ default_handler: 1a00074e: 0297f263 bgeu a5,s1,1a000772 1a000752: 8402 jr s0 1a000754: 1a001537 lui a0,0x1a001 -1a000758: 64050513 addi a0,a0,1600 # 1a001640 <__clz_tab+0x11c> +1a000758: 69050513 addi a0,a0,1680 # 1a001690 <__clz_tab+0x11c> 1a00075c: bfd9 j 1a000732 1a00075e: 00f986b3 add a3,s3,a5 1a000762: 0006c683 lbu a3,0(a3) @@ -859,7 +859,7 @@ default_handler: 1a00082c: d0ea sw s10,96(sp) 1a00082e: 8caa mv s9,a0 1a000830: 1c0034b7 lui s1,0x1c003 -1a000834: 3b8a8a93 addi s5,s5,952 # 1a0013b8 <_endtext> +1a000834: 408a8a93 addi s5,s5,1032 # 1a001408 <_endtext> 1a000838: 1c0039b7 lui s3,0x1c003 1a00083c: 4b05 li s6,1 1a00083e: 4b85 li s7,1 @@ -1021,7 +1021,7 @@ default_handler: 1a0009ba: 4795 li a5,5 1a0009bc: 00a7ef63 bltu a5,a0,1a0009da 1a0009c0: 1a0017b7 lui a5,0x1a001 -1a0009c4: 44078793 addi a5,a5,1088 # 1a001440 <_endtext+0x88> +1a0009c4: 49078793 addi a5,a5,1168 # 1a001490 <_endtext+0x88> 1a0009c8: 050a slli a0,a0,0x2 1a0009ca: 953e add a0,a0,a5 1a0009cc: 411c lw a5,0(a0) @@ -1036,7 +1036,7 @@ default_handler: 1a0009e2: 1a0015b7 lui a1,0x1a001 1a0009e6: 842a mv s0,a0 1a0009e8: 02500613 li a2,37 -1a0009ec: 67858593 addi a1,a1,1656 # 1a001678 <__clz_tab+0x154> +1a0009ec: 6c858593 addi a1,a1,1736 # 1a0016c8 <__clz_tab+0x154> 1a0009f0: 1848 addi a0,sp,52 1a0009f2: 3129 jal 1a0005fc 1a0009f4: 105c addi a5,sp,36 @@ -1293,7 +1293,7 @@ default_handler: 1a000c9c: d85a sw s6,48(sp) 1a000c9e: d65e sw s7,44(sp) 1a000ca0: d462 sw s8,40(sp) -1a000ca2: 6a2000ef jal ra,1a001344 +1a000ca2: 6f2000ef jal ra,1a001394 1a000ca6: 892a mv s2,a0 1a000ca8: 26051263 bnez a0,1a000f0c 1a000cac: 1c0029b7 lui s3,0x1c002 @@ -1543,7 +1543,7 @@ default_handler: 1a000f74: 40c9a783 lw a5,1036(s3) 1a000f78: 02fded63 bltu s11,a5,1a000fb2 1a000f7c: 1a1026b7 lui a3,0x1a102 -1a000f80: 0a46a783 lw a5,164(a3) # 1a1020a4 <__clz_tab+0x100b80> +1a000f80: 0a46a783 lw a5,164(a3) # 1a1020a4 <__clz_tab+0x100b30> 1a000f84: 577d li a4,-1 1a000f86: 0af6a223 sw a5,164(a3) 1a000f8a: 1a1067b7 lui a5,0x1a106 @@ -1644,7 +1644,7 @@ default_handler: 1a001068: 02000693 li a3,32 1a00106c: 40f686b3 sub a3,a3,a5 1a001070: 00f55533 srl a0,a0,a5 -1a001074: 52470793 addi a5,a4,1316 # 1a001524 <__clz_tab> +1a001074: 57470793 addi a5,a4,1396 # 1a001574 <__clz_tab> 1a001078: 00a78533 add a0,a5,a0 1a00107c: 00054503 lbu a0,0(a0) 1a001080: 40a68533 sub a0,a3,a0 @@ -1678,21 +1678,21 @@ default_handler: 1a0010bc: 57fd li a5,-1 1a0010be: 30479073 csrw mie,a5 1a0010c2: 1a1047b7 lui a5,0x1a104 -1a0010c6: 0c47a783 lw a5,196(a5) # 1a1040c4 <__clz_tab+0x102ba0> +1a0010c6: 0c47a783 lw a5,196(a5) # 1a1040c4 <__clz_tab+0x102b50> 1a0010ca: 4709 li a4,2 1a0010cc: 8b8d andi a5,a5,3 -1a0010ce: 26e78863 beq a5,a4,1a00133e +1a0010ce: 28e78663 beq a5,a4,1a00135a 1a0010d2: 470d li a4,3 -1a0010d4: 26e78763 beq a5,a4,1a001342 +1a0010d4: 2ae78f63 beq a5,a4,1a001392 1a0010d8: 4705 li a4,1 -1a0010da: 24e78f63 beq a5,a4,1a001338 +1a0010da: 26e78d63 beq a5,a4,1a001354 1a0010de: 1c003637 lui a2,0x1c003 1a0010e2: da860793 addi a5,a2,-600 # 1c002da8 1a0010e6: 1c003437 lui s0,0x1c003 1a0010ea: 0007a023 sw zero,0(a5) 1a0010ee: 0007a223 sw zero,4(a5) 1a0010f2: da041223 sh zero,-604(s0) # 1c002da4 -1a0010f6: 1a1006b7 lui a3,0x1a100 +1a0010f6: 1a1206b7 lui a3,0x1a120 1a0010fa: 4ad8 lw a4,20(a3) 1a0010fc: da860613 addi a2,a2,-600 1a001100: 87ba mv a5,a4 @@ -1720,7 +1720,7 @@ default_handler: 1a001142: 8fcd or a5,a5,a1 1a001144: cadc sw a5,20(a3) 1a001146: 4248 lw a0,4(a2) -1a001148: 10050f63 beqz a0,1a001266 +1a001148: 12050d63 beqz a0,1a001282 1a00114c: 9a4ff0ef jal ra,1a0002f0 1a001150: 0112b537 lui a0,0x112b 1a001154: 4785 li a5,1 @@ -1728,245 +1728,271 @@ default_handler: 1a00115a: 88050513 addi a0,a0,-1920 # 112a880 <__stack_size+0x112a080> 1a00115e: 00f400a3 sb a5,1(s0) 1a001162: 98eff0ef jal ra,1a0002f0 -1a001166: f5dfe0ef jal ra,1a0000c2 -1a00116a: 1a001537 lui a0,0x1a001 -1a00116e: 1c0037b7 lui a5,0x1c003 -1a001172: 6a050513 addi a0,a0,1696 # 1a0016a0 <__clz_tab+0x17c> -1a001176: da07aa23 sw zero,-588(a5) # 1c002db4 -1a00117a: d62ff0ef jal ra,1a0006dc -1a00117e: 1c0027b7 lui a5,0x1c002 -1a001182: 4751 li a4,20 -1a001184: d8e7a823 sw a4,-624(a5) # 1c001d90 -1a001188: 1c003737 lui a4,0x1c003 -1a00118c: d9078793 addi a5,a5,-624 -1a001190: 1a001437 lui s0,0x1a001 -1a001194: d8072e23 sw zero,-612(a4) # 1c002d9c -1a001198: 1c003737 lui a4,0x1c003 -1a00119c: 48440493 addi s1,s0,1156 # 1a001484 -1a0011a0: 0007a423 sw zero,8(a5) -1a0011a4: 0007a223 sw zero,4(a5) -1a0011a8: da072023 sw zero,-608(a4) # 1c002da0 -1a0011ac: 0007a623 sw zero,12(a5) -1a0011b0: 4901 li s2,0 -1a0011b2: 48440413 addi s0,s0,1156 -1a0011b6: 05f00a13 li s4,95 -1a0011ba: 0004c783 lbu a5,0(s1) -1a0011be: efd5 bnez a5,1a00127a -1a0011c0: 4481 li s1,0 -1a0011c2: 07c40413 addi s0,s0,124 -1a0011c6: 4581 li a1,0 -1a0011c8: 8522 mv a0,s0 -1a0011ca: b16ff0ef jal ra,1a0004e0 -1a0011ce: 4505 li a0,1 -1a0011d0: b0cff0ef jal ra,1a0004dc -1a0011d4: 8526 mv a0,s1 -1a0011d6: b06ff0ef jal ra,1a0004dc -1a0011da: 4501 li a0,0 -1a0011dc: b00ff0ef jal ra,1a0004dc -1a0011e0: 8522 mv a0,s0 -1a0011e2: f0dfe0ef jal ra,1a0000ee -1a0011e6: 0505 addi a0,a0,1 -1a0011e8: 942a add s0,s0,a0 -1a0011ea: 00044783 lbu a5,0(s0) -1a0011ee: 0485 addi s1,s1,1 -1a0011f0: fbf9 bnez a5,1a0011c6 -1a0011f2: 1a001537 lui a0,0x1a001 -1a0011f6: 6b450513 addi a0,a0,1716 # 1a0016b4 <__clz_tab+0x190> -1a0011fa: ce2ff0ef jal ra,1a0006dc -1a0011fe: 1a001537 lui a0,0x1a001 -1a001202: 6bc50513 addi a0,a0,1724 # 1a0016bc <__clz_tab+0x198> -1a001206: a7dff0ef jal ra,1a000c82 -1a00120a: 1a001537 lui a0,0x1a001 -1a00120e: 1c0024b7 lui s1,0x1c002 -1a001212: 6c850513 addi a0,a0,1736 # 1a0016c8 <__clz_tab+0x1a4> -1a001216: 93048493 addi s1,s1,-1744 # 1c001930 -1a00121a: 1a001937 lui s2,0x1a001 -1a00121e: a65ff0ef jal ra,1a000c82 -1a001222: 4401 li s0,0 -1a001224: 36048993 addi s3,s1,864 -1a001228: 1a001a37 lui s4,0x1a001 -1a00122c: 45890913 addi s2,s2,1112 # 1a001458 <_endtext+0xa0> -1a001230: 1a001ab7 lui s5,0x1a001 -1a001234: 1a001b37 lui s6,0x1a001 -1a001238: 1a001bb7 lui s7,0x1a001 -1a00123c: e51fe0ef jal ra,1a00008c -1a001240: 8c2a mv s8,a0 -1a001242: c54ff0ef jal ra,1a000696 -1a001246: 47a9 li a5,10 -1a001248: 00fc0563 beq s8,a5,1a001252 -1a00124c: 47b5 li a5,13 -1a00124e: 0cfc1563 bne s8,a5,1a001318 -1a001252: 854e mv a0,s3 -1a001254: a2fff0ef jal ra,1a000c82 -1a001258: 47a9 li a5,10 -1a00125a: 0aa7ec63 bltu a5,a0,1a001312 -1a00125e: 050a slli a0,a0,0x2 -1a001260: 954a add a0,a0,s2 -1a001262: 411c lw a5,0(a0) -1a001264: 8782 jr a5 -1a001266: 0742 slli a4,a4,0x10 -1a001268: 83e9 srli a5,a5,0x1a -1a00126a: 8341 srli a4,a4,0x10 -1a00126c: 8bbd andi a5,a5,15 -1a00126e: 073e slli a4,a4,0xf -1a001270: 17fd addi a5,a5,-1 -1a001272: 00f757b3 srl a5,a4,a5 -1a001276: c25c sw a5,4(a2) -1a001278: bde1 j 1a001150 -1a00127a: 03479a63 bne a5,s4,1a0012ae -1a00127e: 00148513 addi a0,s1,1 -1a001282: 4985 li s3,1 -1a001284: 02000593 li a1,32 -1a001288: a58ff0ef jal ra,1a0004e0 -1a00128c: 854a mv a0,s2 -1a00128e: a4eff0ef jal ra,1a0004dc -1a001292: 4501 li a0,0 -1a001294: a48ff0ef jal ra,1a0004dc -1a001298: 00098463 beqz s3,1a0012a0 -1a00129c: 9f2ff0ef jal ra,1a00048e -1a0012a0: 8526 mv a0,s1 -1a0012a2: e4dfe0ef jal ra,1a0000ee -1a0012a6: 0505 addi a0,a0,1 -1a0012a8: 94aa add s1,s1,a0 -1a0012aa: 0905 addi s2,s2,1 -1a0012ac: b739 j 1a0011ba -1a0012ae: 8526 mv a0,s1 -1a0012b0: 4981 li s3,0 -1a0012b2: bfc9 j 1a001284 -1a0012b4: 1a001537 lui a0,0x1a001 -1a0012b8: 6dc50513 addi a0,a0,1756 # 1a0016dc <__clz_tab+0x1b8> -1a0012bc: c20ff0ef jal ra,1a0006dc -1a0012c0: 4401 li s0,0 -1a0012c2: a0b5 j 1a00132e -1a0012c4: 1a001537 lui a0,0x1a001 -1a0012c8: 6e850513 addi a0,a0,1768 # 1a0016e8 <__clz_tab+0x1c4> -1a0012cc: bfc5 j 1a0012bc -1a0012ce: 1a001537 lui a0,0x1a001 -1a0012d2: 6f450513 addi a0,a0,1780 # 1a0016f4 <__clz_tab+0x1d0> -1a0012d6: b7dd j 1a0012bc -1a0012d8: 1a001537 lui a0,0x1a001 -1a0012dc: 70050513 addi a0,a0,1792 # 1a001700 <__clz_tab+0x1dc> -1a0012e0: bff1 j 1a0012bc -1a0012e2: 1a001537 lui a0,0x1a001 -1a0012e6: 70c50513 addi a0,a0,1804 # 1a00170c <__clz_tab+0x1e8> -1a0012ea: bfc9 j 1a0012bc -1a0012ec: 1a001537 lui a0,0x1a001 -1a0012f0: 71850513 addi a0,a0,1816 # 1a001718 <__clz_tab+0x1f4> -1a0012f4: b7e1 j 1a0012bc -1a0012f6: 1a001537 lui a0,0x1a001 -1a0012fa: 72850513 addi a0,a0,1832 # 1a001728 <__clz_tab+0x204> -1a0012fe: bf7d j 1a0012bc -1a001300: 738b8513 addi a0,s7,1848 # 1a001738 <__clz_tab+0x214> -1a001304: bf65 j 1a0012bc -1a001306: 744b0513 addi a0,s6,1860 # 1a001744 <__clz_tab+0x220> -1a00130a: bf4d j 1a0012bc -1a00130c: 750a8513 addi a0,s5,1872 # 1a001750 <__clz_tab+0x22c> -1a001310: b775 j 1a0012bc -1a001312: 764a0513 addi a0,s4,1892 # 1a001764 <__clz_tab+0x240> -1a001316: b75d j 1a0012bc -1a001318: 0ff00793 li a5,255 -1a00131c: 00f40963 beq s0,a5,1a00132e -1a001320: 00140793 addi a5,s0,1 -1a001324: 9426 add s0,s0,s1 -1a001326: 37840023 sb s8,864(s0) -1a00132a: 0ff7f413 andi s0,a5,255 -1a00132e: 008487b3 add a5,s1,s0 -1a001332: 36078023 sb zero,864(a5) -1a001336: b719 j 1a00123c -1a001338: 10500073 wfi -1a00133c: bff5 j 1a001338 -1a00133e: eabfe0ef jal ra,1a0001e8 -1a001342: 3ba9 jal 1a00109c +1a001166: 1a121737 lui a4,0x1a121 +1a00116a: 471c lw a5,8(a4) +1a00116c: 1a001437 lui s0,0x1a001 +1a001170: 4d440493 addi s1,s0,1236 # 1a0014d4 +1a001174: fc07f793 andi a5,a5,-64 +1a001178: 0397e793 ori a5,a5,57 +1a00117c: c71c sw a5,8(a4) +1a00117e: 4b1c lw a5,16(a4) +1a001180: 4901 li s2,0 +1a001182: 4d440413 addi s0,s0,1236 +1a001186: fc07f793 andi a5,a5,-64 +1a00118a: 0387e793 ori a5,a5,56 +1a00118e: cb1c sw a5,16(a4) +1a001190: f33fe0ef jal ra,1a0000c2 +1a001194: 1a001537 lui a0,0x1a001 +1a001198: 1c0037b7 lui a5,0x1c003 +1a00119c: 6f050513 addi a0,a0,1776 # 1a0016f0 <__clz_tab+0x17c> +1a0011a0: da07aa23 sw zero,-588(a5) # 1c002db4 +1a0011a4: d38ff0ef jal ra,1a0006dc +1a0011a8: 1c0027b7 lui a5,0x1c002 +1a0011ac: 4751 li a4,20 +1a0011ae: d8e7a823 sw a4,-624(a5) # 1c001d90 +1a0011b2: 1c003737 lui a4,0x1c003 +1a0011b6: d9078793 addi a5,a5,-624 +1a0011ba: d8072e23 sw zero,-612(a4) # 1c002d9c +1a0011be: 1c003737 lui a4,0x1c003 +1a0011c2: 0007a423 sw zero,8(a5) +1a0011c6: 0007a223 sw zero,4(a5) +1a0011ca: da072023 sw zero,-608(a4) # 1c002da0 +1a0011ce: 0007a623 sw zero,12(a5) +1a0011d2: 05f00a13 li s4,95 +1a0011d6: 0004c783 lbu a5,0(s1) +1a0011da: efd5 bnez a5,1a001296 +1a0011dc: 4481 li s1,0 +1a0011de: 07c40413 addi s0,s0,124 +1a0011e2: 4581 li a1,0 +1a0011e4: 8522 mv a0,s0 +1a0011e6: afaff0ef jal ra,1a0004e0 +1a0011ea: 4505 li a0,1 +1a0011ec: af0ff0ef jal ra,1a0004dc +1a0011f0: 8526 mv a0,s1 +1a0011f2: aeaff0ef jal ra,1a0004dc +1a0011f6: 4501 li a0,0 +1a0011f8: ae4ff0ef jal ra,1a0004dc +1a0011fc: 8522 mv a0,s0 +1a0011fe: ef1fe0ef jal ra,1a0000ee +1a001202: 0505 addi a0,a0,1 +1a001204: 942a add s0,s0,a0 +1a001206: 00044783 lbu a5,0(s0) +1a00120a: 0485 addi s1,s1,1 +1a00120c: fbf9 bnez a5,1a0011e2 +1a00120e: 1a001537 lui a0,0x1a001 +1a001212: 70450513 addi a0,a0,1796 # 1a001704 <__clz_tab+0x190> +1a001216: cc6ff0ef jal ra,1a0006dc +1a00121a: 1a001537 lui a0,0x1a001 +1a00121e: 70c50513 addi a0,a0,1804 # 1a00170c <__clz_tab+0x198> +1a001222: a61ff0ef jal ra,1a000c82 +1a001226: 1a001537 lui a0,0x1a001 +1a00122a: 1c0024b7 lui s1,0x1c002 +1a00122e: 71850513 addi a0,a0,1816 # 1a001718 <__clz_tab+0x1a4> +1a001232: 93048493 addi s1,s1,-1744 # 1c001930 +1a001236: 1a001937 lui s2,0x1a001 +1a00123a: a49ff0ef jal ra,1a000c82 +1a00123e: 4401 li s0,0 +1a001240: 36048993 addi s3,s1,864 +1a001244: 1a001a37 lui s4,0x1a001 +1a001248: 4a890913 addi s2,s2,1192 # 1a0014a8 <_endtext+0xa0> +1a00124c: 1a001ab7 lui s5,0x1a001 +1a001250: 1a001b37 lui s6,0x1a001 +1a001254: 1a001bb7 lui s7,0x1a001 +1a001258: e35fe0ef jal ra,1a00008c +1a00125c: 8c2a mv s8,a0 +1a00125e: c38ff0ef jal ra,1a000696 +1a001262: 47a9 li a5,10 +1a001264: 00fc0563 beq s8,a5,1a00126e +1a001268: 47b5 li a5,13 +1a00126a: 0cfc1563 bne s8,a5,1a001334 +1a00126e: 854e mv a0,s3 +1a001270: a13ff0ef jal ra,1a000c82 +1a001274: 47a9 li a5,10 +1a001276: 0aa7ec63 bltu a5,a0,1a00132e +1a00127a: 050a slli a0,a0,0x2 +1a00127c: 954a add a0,a0,s2 +1a00127e: 411c lw a5,0(a0) +1a001280: 8782 jr a5 +1a001282: 0742 slli a4,a4,0x10 +1a001284: 83e9 srli a5,a5,0x1a +1a001286: 8341 srli a4,a4,0x10 +1a001288: 8bbd andi a5,a5,15 +1a00128a: 073e slli a4,a4,0xf +1a00128c: 17fd addi a5,a5,-1 +1a00128e: 00f757b3 srl a5,a4,a5 +1a001292: c25c sw a5,4(a2) +1a001294: bd75 j 1a001150 +1a001296: 03479a63 bne a5,s4,1a0012ca +1a00129a: 00148513 addi a0,s1,1 +1a00129e: 4985 li s3,1 +1a0012a0: 02000593 li a1,32 +1a0012a4: a3cff0ef jal ra,1a0004e0 +1a0012a8: 854a mv a0,s2 +1a0012aa: a32ff0ef jal ra,1a0004dc +1a0012ae: 4501 li a0,0 +1a0012b0: a2cff0ef jal ra,1a0004dc +1a0012b4: 00098463 beqz s3,1a0012bc +1a0012b8: 9d6ff0ef jal ra,1a00048e +1a0012bc: 8526 mv a0,s1 +1a0012be: e31fe0ef jal ra,1a0000ee +1a0012c2: 0505 addi a0,a0,1 +1a0012c4: 94aa add s1,s1,a0 +1a0012c6: 0905 addi s2,s2,1 +1a0012c8: b739 j 1a0011d6 +1a0012ca: 8526 mv a0,s1 +1a0012cc: 4981 li s3,0 +1a0012ce: bfc9 j 1a0012a0 +1a0012d0: 1a001537 lui a0,0x1a001 +1a0012d4: 72c50513 addi a0,a0,1836 # 1a00172c <__clz_tab+0x1b8> +1a0012d8: c04ff0ef jal ra,1a0006dc +1a0012dc: 4401 li s0,0 +1a0012de: a0b5 j 1a00134a +1a0012e0: 1a001537 lui a0,0x1a001 +1a0012e4: 73850513 addi a0,a0,1848 # 1a001738 <__clz_tab+0x1c4> +1a0012e8: bfc5 j 1a0012d8 +1a0012ea: 1a001537 lui a0,0x1a001 +1a0012ee: 74450513 addi a0,a0,1860 # 1a001744 <__clz_tab+0x1d0> +1a0012f2: b7dd j 1a0012d8 +1a0012f4: 1a001537 lui a0,0x1a001 +1a0012f8: 75050513 addi a0,a0,1872 # 1a001750 <__clz_tab+0x1dc> +1a0012fc: bff1 j 1a0012d8 +1a0012fe: 1a001537 lui a0,0x1a001 +1a001302: 75c50513 addi a0,a0,1884 # 1a00175c <__clz_tab+0x1e8> +1a001306: bfc9 j 1a0012d8 +1a001308: 1a001537 lui a0,0x1a001 +1a00130c: 76850513 addi a0,a0,1896 # 1a001768 <__clz_tab+0x1f4> +1a001310: b7e1 j 1a0012d8 +1a001312: 1a001537 lui a0,0x1a001 +1a001316: 77850513 addi a0,a0,1912 # 1a001778 <__clz_tab+0x204> +1a00131a: bf7d j 1a0012d8 +1a00131c: 788b8513 addi a0,s7,1928 # 1a001788 <__clz_tab+0x214> +1a001320: bf65 j 1a0012d8 +1a001322: 794b0513 addi a0,s6,1940 # 1a001794 <__clz_tab+0x220> +1a001326: bf4d j 1a0012d8 +1a001328: 7a0a8513 addi a0,s5,1952 # 1a0017a0 <__clz_tab+0x22c> +1a00132c: b775 j 1a0012d8 +1a00132e: 7b4a0513 addi a0,s4,1972 # 1a0017b4 <__clz_tab+0x240> +1a001332: b75d j 1a0012d8 +1a001334: 0ff00793 li a5,255 +1a001338: 00f40963 beq s0,a5,1a00134a +1a00133c: 00140793 addi a5,s0,1 +1a001340: 9426 add s0,s0,s1 +1a001342: 37840023 sb s8,864(s0) +1a001346: 0ff7f413 andi s0,a5,255 +1a00134a: 008487b3 add a5,s1,s0 +1a00134e: 36078023 sb zero,864(a5) +1a001352: b719 j 1a001258 +1a001354: 10500073 wfi +1a001358: bff5 j 1a001354 +1a00135a: 1a1217b7 lui a5,0x1a121 +1a00135e: 4f98 lw a4,24(a5) +1a001360: fc077713 andi a4,a4,-64 +1a001364: 01d76713 ori a4,a4,29 +1a001368: cf98 sw a4,24(a5) +1a00136a: 5398 lw a4,32(a5) +1a00136c: fc077713 andi a4,a4,-64 +1a001370: 01976713 ori a4,a4,25 +1a001374: d398 sw a4,32(a5) +1a001376: 5798 lw a4,40(a5) +1a001378: fc077713 andi a4,a4,-64 +1a00137c: 01e76713 ori a4,a4,30 +1a001380: d798 sw a4,40(a5) +1a001382: 5b98 lw a4,48(a5) +1a001384: fc077713 andi a4,a4,-64 +1a001388: 01f76713 ori a4,a4,31 +1a00138c: db98 sw a4,48(a5) +1a00138e: e5bfe0ef jal ra,1a0001e8 +1a001392: 3329 jal 1a00109c -1a001344 : +1a001394 : /* int setjmp (jmp_buf); */ .section .text.setjmp .globl setjmp .type setjmp, @function setjmp: REG_S ra, 0*SZREG(a0) -1a001344: 00152023 sw ra,0(a0) +1a001394: 00152023 sw ra,0(a0) REG_S s0, 1*SZREG(a0) -1a001348: c140 sw s0,4(a0) +1a001398: c140 sw s0,4(a0) REG_S s1, 2*SZREG(a0) -1a00134a: c504 sw s1,8(a0) +1a00139a: c504 sw s1,8(a0) #ifndef __riscv_32e REG_S s2, 3*SZREG(a0) -1a00134c: 01252623 sw s2,12(a0) +1a00139c: 01252623 sw s2,12(a0) REG_S s3, 4*SZREG(a0) -1a001350: 01352823 sw s3,16(a0) +1a0013a0: 01352823 sw s3,16(a0) REG_S s4, 5*SZREG(a0) -1a001354: 01452a23 sw s4,20(a0) +1a0013a4: 01452a23 sw s4,20(a0) REG_S s5, 6*SZREG(a0) -1a001358: 01552c23 sw s5,24(a0) +1a0013a8: 01552c23 sw s5,24(a0) REG_S s6, 7*SZREG(a0) -1a00135c: 01652e23 sw s6,28(a0) +1a0013ac: 01652e23 sw s6,28(a0) REG_S s7, 8*SZREG(a0) -1a001360: 03752023 sw s7,32(a0) +1a0013b0: 03752023 sw s7,32(a0) REG_S s8, 9*SZREG(a0) -1a001364: 03852223 sw s8,36(a0) +1a0013b4: 03852223 sw s8,36(a0) REG_S s9, 10*SZREG(a0) -1a001368: 03952423 sw s9,40(a0) +1a0013b8: 03952423 sw s9,40(a0) REG_S s10,11*SZREG(a0) -1a00136c: 03a52623 sw s10,44(a0) +1a0013bc: 03a52623 sw s10,44(a0) REG_S s11,12*SZREG(a0) -1a001370: 03b52823 sw s11,48(a0) +1a0013c0: 03b52823 sw s11,48(a0) REG_S sp, 13*SZREG(a0) -1a001374: 02252a23 sw sp,52(a0) +1a0013c4: 02252a23 sw sp,52(a0) FREG_S fs9, 14*SZREG+ 9*SZFREG(a0) FREG_S fs10,14*SZREG+10*SZFREG(a0) FREG_S fs11,14*SZREG+11*SZFREG(a0) #endif li a0, 0 -1a001378: 4501 li a0,0 +1a0013c8: 4501 li a0,0 ret -1a00137a: 8082 ret +1a0013ca: 8082 ret -1a00137c : +1a0013cc : /* volatile void longjmp (jmp_buf, int); */ .section .text.longjmp .globl longjmp .type longjmp, @function longjmp: REG_L ra, 0*SZREG(a0) -1a00137c: 00052083 lw ra,0(a0) +1a0013cc: 00052083 lw ra,0(a0) REG_L s0, 1*SZREG(a0) -1a001380: 4140 lw s0,4(a0) +1a0013d0: 4140 lw s0,4(a0) REG_L s1, 2*SZREG(a0) -1a001382: 4504 lw s1,8(a0) +1a0013d2: 4504 lw s1,8(a0) #ifndef __riscv_32e REG_L s2, 3*SZREG(a0) -1a001384: 00c52903 lw s2,12(a0) +1a0013d4: 00c52903 lw s2,12(a0) REG_L s3, 4*SZREG(a0) -1a001388: 01052983 lw s3,16(a0) +1a0013d8: 01052983 lw s3,16(a0) REG_L s4, 5*SZREG(a0) -1a00138c: 01452a03 lw s4,20(a0) +1a0013dc: 01452a03 lw s4,20(a0) REG_L s5, 6*SZREG(a0) -1a001390: 01852a83 lw s5,24(a0) +1a0013e0: 01852a83 lw s5,24(a0) REG_L s6, 7*SZREG(a0) -1a001394: 01c52b03 lw s6,28(a0) +1a0013e4: 01c52b03 lw s6,28(a0) REG_L s7, 8*SZREG(a0) -1a001398: 02052b83 lw s7,32(a0) +1a0013e8: 02052b83 lw s7,32(a0) REG_L s8, 9*SZREG(a0) -1a00139c: 02452c03 lw s8,36(a0) +1a0013ec: 02452c03 lw s8,36(a0) REG_L s9, 10*SZREG(a0) -1a0013a0: 02852c83 lw s9,40(a0) +1a0013f0: 02852c83 lw s9,40(a0) REG_L s10,11*SZREG(a0) -1a0013a4: 02c52d03 lw s10,44(a0) +1a0013f4: 02c52d03 lw s10,44(a0) REG_L s11,12*SZREG(a0) -1a0013a8: 03052d83 lw s11,48(a0) +1a0013f8: 03052d83 lw s11,48(a0) REG_L sp, 13*SZREG(a0) -1a0013ac: 03452103 lw sp,52(a0) +1a0013fc: 03452103 lw sp,52(a0) FREG_L fs9, 14*SZREG+ 9*SZFREG(a0) FREG_L fs10,14*SZREG+10*SZFREG(a0) FREG_L fs11,14*SZREG+11*SZFREG(a0) #endif seqz a0, a1 -1a0013b0: 0015b513 seqz a0,a1 +1a001400: 0015b513 seqz a0,a1 add a0, a0, a1 # a0 = (a1 == 0) ? 1 : a1 -1a0013b4: 952e add a0,a0,a1 +1a001404: 952e add a0,a0,a1 ret -1a0013b6: 8082 ret +1a001406: 8082 ret diff --git a/boot/crt0.S b/sw/bootcode/crt0.S similarity index 100% rename from boot/crt0.S rename to sw/bootcode/crt0.S diff --git a/boot/fll-v1.c b/sw/bootcode/fll-v1.c similarity index 100% rename from boot/fll-v1.c rename to sw/bootcode/fll-v1.c diff --git a/boot/gen_rom.py b/sw/bootcode/gen_rom.py similarity index 100% rename from boot/gen_rom.py rename to sw/bootcode/gen_rom.py diff --git a/boot/include/.clang-format b/sw/bootcode/include/.clang-format similarity index 100% rename from boot/include/.clang-format rename to sw/bootcode/include/.clang-format diff --git a/boot/include/archi/chips/control-pulp/apb_soc.h b/sw/bootcode/include/archi/chips/control-pulp/apb_soc.h similarity index 100% rename from boot/include/archi/chips/control-pulp/apb_soc.h rename to sw/bootcode/include/archi/chips/control-pulp/apb_soc.h diff --git a/boot/include/archi/chips/control-pulp/apb_soc_ctrl.h b/sw/bootcode/include/archi/chips/control-pulp/apb_soc_ctrl.h similarity index 100% rename from boot/include/archi/chips/control-pulp/apb_soc_ctrl.h rename to sw/bootcode/include/archi/chips/control-pulp/apb_soc_ctrl.h diff --git a/boot/include/archi/chips/control-pulp/memory_map.h b/sw/bootcode/include/archi/chips/control-pulp/memory_map.h similarity index 100% rename from boot/include/archi/chips/control-pulp/memory_map.h rename to sw/bootcode/include/archi/chips/control-pulp/memory_map.h diff --git a/boot/include/archi/chips/control-pulp/properties.h b/sw/bootcode/include/archi/chips/control-pulp/properties.h similarity index 100% rename from boot/include/archi/chips/control-pulp/properties.h rename to sw/bootcode/include/archi/chips/control-pulp/properties.h diff --git a/boot/include/archi/chips/control-pulp/pulp.h b/sw/bootcode/include/archi/chips/control-pulp/pulp.h similarity index 100% rename from boot/include/archi/chips/control-pulp/pulp.h rename to sw/bootcode/include/archi/chips/control-pulp/pulp.h diff --git a/boot/include/archi/chips/pulp/apb_soc.h b/sw/bootcode/include/archi/chips/pulp/apb_soc.h similarity index 100% rename from boot/include/archi/chips/pulp/apb_soc.h rename to sw/bootcode/include/archi/chips/pulp/apb_soc.h diff --git a/boot/include/archi/chips/pulp/apb_soc_ctrl.h b/sw/bootcode/include/archi/chips/pulp/apb_soc_ctrl.h similarity index 100% rename from boot/include/archi/chips/pulp/apb_soc_ctrl.h rename to sw/bootcode/include/archi/chips/pulp/apb_soc_ctrl.h diff --git a/boot/include/archi/chips/pulp/memory_map.h b/sw/bootcode/include/archi/chips/pulp/memory_map.h similarity index 100% rename from boot/include/archi/chips/pulp/memory_map.h rename to sw/bootcode/include/archi/chips/pulp/memory_map.h diff --git a/boot/include/archi/chips/pulp/properties.h b/sw/bootcode/include/archi/chips/pulp/properties.h similarity index 100% rename from boot/include/archi/chips/pulp/properties.h rename to sw/bootcode/include/archi/chips/pulp/properties.h diff --git a/boot/include/archi/chips/pulp/pulp.h b/sw/bootcode/include/archi/chips/pulp/pulp.h similarity index 100% rename from boot/include/archi/chips/pulp/pulp.h rename to sw/bootcode/include/archi/chips/pulp/pulp.h diff --git a/boot/include/archi/chips/pulpissimo/apb_soc.h b/sw/bootcode/include/archi/chips/pulpissimo/apb_soc.h similarity index 100% rename from boot/include/archi/chips/pulpissimo/apb_soc.h rename to sw/bootcode/include/archi/chips/pulpissimo/apb_soc.h diff --git a/boot/include/archi/chips/pulpissimo/apb_soc_ctrl.h b/sw/bootcode/include/archi/chips/pulpissimo/apb_soc_ctrl.h similarity index 100% rename from boot/include/archi/chips/pulpissimo/apb_soc_ctrl.h rename to sw/bootcode/include/archi/chips/pulpissimo/apb_soc_ctrl.h diff --git a/boot/include/archi/chips/pulpissimo/memory_map.h b/sw/bootcode/include/archi/chips/pulpissimo/memory_map.h similarity index 88% rename from boot/include/archi/chips/pulpissimo/memory_map.h rename to sw/bootcode/include/archi/chips/pulpissimo/memory_map.h index 4e226bbb..8e8314d0 100644 --- a/boot/include/archi/chips/pulpissimo/memory_map.h +++ b/sw/bootcode/include/archi/chips/pulpissimo/memory_map.h @@ -26,9 +26,8 @@ #define ARCHI_SOC_PERIPHERALS_ADDR 0x1A100000 -#define ARCHI_FC_TIMER_SIZE 0x00000800 +#define ARCHI_FC_TIMER_SIZE 0x00000800 -#define ARCHI_FLL_OFFSET 0x00000000 #define ARCHI_GPIO_OFFSET 0x00001000 #define ARCHI_UDMA_OFFSET 0x00002000 #define ARCHI_APB_SOC_CTRL_OFFSET 0x00004000 @@ -37,7 +36,9 @@ #define ARCHI_FC_TIMER_OFFSET 0x0000B000 #define ARCHI_FC_HWPE_OFFSET 0x0000C000 #define ARCHI_STDOUT_OFFSET 0x0000F000 - +// Chip control port +#define ARCHI_FLL_OFFSET 0x00020000 +#define ARCHI_PAD_CFG_OFFSET 0x00021000 #define ARCHI_GPIO_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_GPIO_OFFSET ) @@ -48,6 +49,8 @@ #define ARCHI_FC_TIMER_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_TIMER_OFFSET ) #define ARCHI_FC_HWPE_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_HWPE_OFFSET ) #define ARCHI_STDOUT_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_STDOUT_OFFSET ) +#define ARCHI_FLL_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FLL_OFFSET ) +#define ARCHI_PAD_CFG_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_PAD_CFG_OFFSET ) diff --git a/boot/include/archi/chips/pulpissimo/properties.h b/sw/bootcode/include/archi/chips/pulpissimo/properties.h similarity index 100% rename from boot/include/archi/chips/pulpissimo/properties.h rename to sw/bootcode/include/archi/chips/pulpissimo/properties.h diff --git a/boot/include/archi/chips/pulpissimo/pulp.h b/sw/bootcode/include/archi/chips/pulpissimo/pulp.h similarity index 100% rename from boot/include/archi/chips/pulpissimo/pulp.h rename to sw/bootcode/include/archi/chips/pulpissimo/pulp.h diff --git a/boot/include/archi/fll/fll_v1.h b/sw/bootcode/include/archi/fll/fll_v1.h similarity index 100% rename from boot/include/archi/fll/fll_v1.h rename to sw/bootcode/include/archi/fll/fll_v1.h diff --git a/boot/include/archi/itc/itc_v1.h b/sw/bootcode/include/archi/itc/itc_v1.h similarity index 100% rename from boot/include/archi/itc/itc_v1.h rename to sw/bootcode/include/archi/itc/itc_v1.h diff --git a/boot/include/archi/pulp.h b/sw/bootcode/include/archi/pulp.h similarity index 100% rename from boot/include/archi/pulp.h rename to sw/bootcode/include/archi/pulp.h diff --git a/boot/include/archi/pulp_defs.h b/sw/bootcode/include/archi/pulp_defs.h similarity index 100% rename from boot/include/archi/pulp_defs.h rename to sw/bootcode/include/archi/pulp_defs.h diff --git a/boot/include/archi/riscv/builtins_v2.h b/sw/bootcode/include/archi/riscv/builtins_v2.h similarity index 100% rename from boot/include/archi/riscv/builtins_v2.h rename to sw/bootcode/include/archi/riscv/builtins_v2.h diff --git a/boot/include/archi/riscv/builtins_v2_emu.h b/sw/bootcode/include/archi/riscv/builtins_v2_emu.h similarity index 100% rename from boot/include/archi/riscv/builtins_v2_emu.h rename to sw/bootcode/include/archi/riscv/builtins_v2_emu.h diff --git a/boot/include/archi/riscv/pcer_v2.h b/sw/bootcode/include/archi/riscv/pcer_v2.h similarity index 100% rename from boot/include/archi/riscv/pcer_v2.h rename to sw/bootcode/include/archi/riscv/pcer_v2.h diff --git a/boot/include/archi/riscv/priv_1_10.h b/sw/bootcode/include/archi/riscv/priv_1_10.h similarity index 100% rename from boot/include/archi/riscv/priv_1_10.h rename to sw/bootcode/include/archi/riscv/priv_1_10.h diff --git a/boot/include/archi/riscv/priv_1_11.h b/sw/bootcode/include/archi/riscv/priv_1_11.h similarity index 100% rename from boot/include/archi/riscv/priv_1_11.h rename to sw/bootcode/include/archi/riscv/priv_1_11.h diff --git a/boot/include/archi/riscv/priv_1_12.h b/sw/bootcode/include/archi/riscv/priv_1_12.h similarity index 100% rename from boot/include/archi/riscv/priv_1_12.h rename to sw/bootcode/include/archi/riscv/priv_1_12.h diff --git a/boot/include/archi/soc_eu/soc_eu_v2.h b/sw/bootcode/include/archi/soc_eu/soc_eu_v2.h similarity index 100% rename from boot/include/archi/soc_eu/soc_eu_v2.h rename to sw/bootcode/include/archi/soc_eu/soc_eu_v2.h diff --git a/boot/include/archi/soc_eu/soc_eu_v3.h b/sw/bootcode/include/archi/soc_eu/soc_eu_v3.h similarity index 100% rename from boot/include/archi/soc_eu/soc_eu_v3.h rename to sw/bootcode/include/archi/soc_eu/soc_eu_v3.h diff --git a/boot/include/archi/timer/timer_v2.h b/sw/bootcode/include/archi/timer/timer_v2.h similarity index 100% rename from boot/include/archi/timer/timer_v2.h rename to sw/bootcode/include/archi/timer/timer_v2.h diff --git a/boot/include/archi/udma/hyper/udma_hyper_v2.h b/sw/bootcode/include/archi/udma/hyper/udma_hyper_v2.h similarity index 100% rename from boot/include/archi/udma/hyper/udma_hyper_v2.h rename to sw/bootcode/include/archi/udma/hyper/udma_hyper_v2.h diff --git a/boot/include/archi/udma/spim/udma_spim_v3.h b/sw/bootcode/include/archi/udma/spim/udma_spim_v3.h similarity index 100% rename from boot/include/archi/udma/spim/udma_spim_v3.h rename to sw/bootcode/include/archi/udma/spim/udma_spim_v3.h diff --git a/boot/include/archi/udma/uart/udma_uart_v1.h b/sw/bootcode/include/archi/udma/uart/udma_uart_v1.h similarity index 100% rename from boot/include/archi/udma/uart/udma_uart_v1.h rename to sw/bootcode/include/archi/udma/uart/udma_uart_v1.h diff --git a/boot/include/archi/udma/udma_v3.h b/sw/bootcode/include/archi/udma/udma_v3.h similarity index 100% rename from boot/include/archi/udma/udma_v3.h rename to sw/bootcode/include/archi/udma/udma_v3.h diff --git a/boot/include/archi/utils.h b/sw/bootcode/include/archi/utils.h similarity index 100% rename from boot/include/archi/utils.h rename to sw/bootcode/include/archi/utils.h diff --git a/sw/bootcode/include/bitfield.h b/sw/bootcode/include/bitfield.h new file mode 100644 index 00000000..3177f149 --- /dev/null +++ b/sw/bootcode/include/bitfield.h @@ -0,0 +1,285 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#ifndef OPENTITAN_SW_DEVICE_LIB_BASE_BITFIELD_H_ +#define OPENTITAN_SW_DEVICE_LIB_BASE_BITFIELD_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +/** + * @file + * @brief Bitfield Manipulation Functions + */ + +/** + * All the bitfield functions are pure (they do not modify their arguments), so + * the result must be used. We enable warnings to ensure this happens. + */ +#define BITFIELD_WARN_UNUSED_RESULT __attribute__((warn_unused_result)) + +/** + * A field of a 32-bit bitfield. + * + * The following field definition: `{ .mask = 0b11, .index = 12 }` + * + * Denotes the X-marked bits in the following 32-bit bitfield: + * + * field: 0b--------'--------'--XX----'-------- + * index: 31 0 + * + * Restrictions: The index plus the width of the mask must not be greater than + * 31. + */ +typedef struct bitfield_field32 { + /** The field mask. Usually all ones. */ + uint32_t mask; + /** The field position in the bitfield, counting from the zero-bit. */ + uint32_t index; +} bitfield_field32_t; + +/** + * Reads a value from `field` in `bitfield`. + * + * This function uses the `field` parameter to read the value from `bitfield`. + * The resulting value will be shifted right and zero-extended so the field's + * zero-bit is the return value's zero-bit. + * + * @param bitfield Bitfield to get the field from. + * @param field Field to read out from. + * @return Zero-extended `field` from `bitfield`. + */ +BITFIELD_WARN_UNUSED_RESULT +inline uint32_t bitfield_field32_read(uint32_t bitfield, + bitfield_field32_t field) { + return (bitfield >> field.index) & field.mask; +} + +/** + * Writes `value` to `field` in `bitfield`. + * + * This function uses the `field` parameter to set specific bits in `bitfield`. + * The relevant portion of `bitfield` is zeroed before the bits are set to + * `value`. + * + * @param bitfield Bitfield to set the field in. + * @param field Field within bitfield to be set. + * @param value Value for the new field. + * @return `bitfield` with `field` set to `value`. + */ +BITFIELD_WARN_UNUSED_RESULT +inline uint32_t bitfield_field32_write(uint32_t bitfield, + bitfield_field32_t field, + uint32_t value) { + bitfield &= ~(field.mask << field.index); + bitfield |= (value & field.mask) << field.index; + return bitfield; +} + +/** + * A single bit in a 32-bit bitfield. + * + * This denotes the position of a single bit, counting from the zero-bit. + * + * For instance, `(bitfield_bit_index_t)4` denotes the X-marked bit in the + * following 32-bit bitfield: + * + * field: 0b--------'--------'--------'---X---- + * index: 31 0 + * + * Restrictions: The value must not be greater than 31. + */ +typedef uint32_t bitfield_bit32_index_t; + +/** + * Turns a `bitfield_bit32_index_t` into a `bitfield_field32_t` (which is more + * general). + * + * @param bit_index The corresponding single bit to turn into a field. + * @return A 1-bit field that corresponds to `bit_index`. + */ +BITFIELD_WARN_UNUSED_RESULT +inline bitfield_field32_t bitfield_bit32_to_field32( + bitfield_bit32_index_t bit_index) { + return (bitfield_field32_t){ + .mask = 0x1, .index = bit_index, + }; +} + +/** + * Reads the `bit_index`th bit in `bitfield`. + * + * @param bitfield Bitfield to get the bit from. + * @param bit_index Bit to read. + * @return `true` if the bit was one, `false` otherwise. + */ +BITFIELD_WARN_UNUSED_RESULT +inline bool bitfield_bit32_read(uint32_t bitfield, + bitfield_bit32_index_t bit_index) { + return bitfield_field32_read(bitfield, + bitfield_bit32_to_field32(bit_index)) == 0x1u; +} + +/** + * Writes `value` to the `bit_index`th bit in `bitfield`. + * + * @param bitfield Bitfield to update the bit in. + * @param bit_index Bit to update. + * @param value Bit value to write to `bitfield`. + * @return `bitfield` with the `bit_index`th bit set to `value`. + */ +BITFIELD_WARN_UNUSED_RESULT +inline uint32_t bitfield_bit32_write(uint32_t bitfield, + bitfield_bit32_index_t bit_index, + bool value) { + return bitfield_field32_write(bitfield, bitfield_bit32_to_field32(bit_index), + value ? 0x1u : 0x0u); +} + +/** + * Find First Set Bit + * + * Returns one plus the index of the least-significant 1-bit of a 32-bit word. + * + * For instance, `bitfield_find_first_set32(field)` of the below 32-bit value + * returns `5`. + * + * field: 0b00000000'00000000'11111111'00010000 + * index: 31 0 + * + * This is the canonical definition for the GCC/Clang builtin `__builtin_ffs`, + * and hence takes and returns a signed integer. + * + * @param bitfield Bitfield to find the first set bit in. + * @return One plus the index of the least-significant 1-bit of `bitfield`. + */ +BITFIELD_WARN_UNUSED_RESULT +inline int32_t bitfield_find_first_set32(int32_t bitfield) { + return __builtin_ffs(bitfield); +} + +/** + * Count Leading Zeroes + * + * Returns the number of leading 0-bits in `bitfield`, starting at the most + * significant bit position. If `bitfield` is 0, the result is 32, to match the + * RISC-V B Extension. + * + * For instance, `bitfield_count_leading_zeroes32(field)` of the below 32-bit + * value returns `16`. + * + * field: 0b00000000'00000000'11111111'00010000 + * index: 31 0 + * + * This is the canonical definition for the GCC/Clang builtin `__builtin_clz`, + * and hence returns a signed integer. + * + * @param bitfield Bitfield to count leading 0-bits from. + * @return The number of leading 0-bits in `bitfield`. + */ +BITFIELD_WARN_UNUSED_RESULT +inline int32_t bitfield_count_leading_zeroes32(uint32_t bitfield) { + return (bitfield != 0) ? __builtin_clz(bitfield) : 32; +} + +/** + * Count Trailing Zeroes + * + * Returns the number of trailing 0-bits in `bitfield`, starting at the least + * significant bit position. If `bitfield` is 0, the result is 32, to match the + * RISC-V B Extension. + * + * For instance, `bitfield_count_trailing_zeroes32(field)` of the below 32-bit + * value returns `4`. + * + * field: 0b00000000'00000000'11111111'00010000 + * index: 31 0 + * + * This is the canonical definition for the GCC/Clang builtin `__builtin_ctz`, + * and hence returns a signed integer. + * + * @param bitfield Bitfield to count trailing 0-bits from. + * @return The number of trailing 0-bits in `bitfield`. + */ +BITFIELD_WARN_UNUSED_RESULT +inline int32_t bitfield_count_trailing_zeroes32(uint32_t bitfield) { + return (bitfield != 0) ? __builtin_ctz(bitfield) : 32; +} + +/** + * Count Set Bits + * + * Returns the number of 1-bits in `bitfield`. + * + * For instance, `bitfield_popcount32(field)` of the below 32-bit value returns + * `9`. + * + * field: 0b00000000'00000000'11111111'00010000 + * index: 31 0 + * + * This is the canonical definition for the GCC/Clang builtin + * `__builtin_popcount`, and hence returns a signed integer. + * + * @param bitfield Bitfield to count 1-bits from. + * @return The number of 1-bits in `bitfield`. + */ +BITFIELD_WARN_UNUSED_RESULT +inline int32_t bitfield_popcount32(uint32_t bitfield) { + return __builtin_popcount(bitfield); +} + +/** + * Parity + * + * Returns the number of 1-bits in `bitfield`, modulo 2. + * + * For instance, `bitfield_parity32(field)` of the below 32-bit value returns + * `1`. + * + * field: 0b00000000'00000000'11111111'00010000 + * index: 31 0 + * + * This is the canonical definition for the GCC/Clang builtin + * `__builtin_parity`, and hence returns a signed integer. + * + * @param bitfield Bitfield to count 1-bits from. + * @return The number of 1-bits in `bitfield`, modulo 2. + */ +BITFIELD_WARN_UNUSED_RESULT +inline int32_t bitfield_parity32(uint32_t bitfield) { + return __builtin_parity(bitfield); +} + +/** + * Byte Swap + * + * Returns `field` with the order of the bytes reversed. Bytes here always means + * exactly 8 bits. + * + * For instance, `byteswap(field)` of the below 32-bit value returns `1`. + * + * field: 0bAAAAAAAA'BBBBBBBB'CCCCCCCC'DDDDDDDD + * index: 31 0 + * returns: 0bDDDDDDDD'CCCCCCCC'BBBBBBBB'AAAAAAAA + * + * This is the canonical definition for the GCC/Clang builtin + * `__builtin_bswap32`. + * + * @param bitfield Bitfield to reverse bytes of. + * @return `bitfield` with the order of bytes reversed. + */ +BITFIELD_WARN_UNUSED_RESULT +inline uint32_t bitfield_byteswap32(uint32_t bitfield) { + return __builtin_bswap32(bitfield); +} + +#ifdef __cplusplus +} // extern "C" +#endif // __cplusplus + +#endif // OPENTITAN_SW_DEVICE_LIB_BASE_BITFIELD_H_ diff --git a/boot/include/config.h b/sw/bootcode/include/config.h similarity index 100% rename from boot/include/config.h rename to sw/bootcode/include/config.h diff --git a/boot/include/hal/apb_soc/apb_soc_v3.h b/sw/bootcode/include/hal/apb_soc/apb_soc_v3.h similarity index 100% rename from boot/include/hal/apb_soc/apb_soc_v3.h rename to sw/bootcode/include/hal/apb_soc/apb_soc_v3.h diff --git a/boot/include/hal/apb_soc/apb_soc_v4.h b/sw/bootcode/include/hal/apb_soc/apb_soc_v4.h similarity index 100% rename from boot/include/hal/apb_soc/apb_soc_v4.h rename to sw/bootcode/include/hal/apb_soc/apb_soc_v4.h diff --git a/boot/include/hal/chips/control-pulp/pulp.h b/sw/bootcode/include/hal/chips/control-pulp/pulp.h similarity index 100% rename from boot/include/hal/chips/control-pulp/pulp.h rename to sw/bootcode/include/hal/chips/control-pulp/pulp.h diff --git a/boot/include/hal/chips/pulp/pulp.h b/sw/bootcode/include/hal/chips/pulp/pulp.h similarity index 100% rename from boot/include/hal/chips/pulp/pulp.h rename to sw/bootcode/include/hal/chips/pulp/pulp.h diff --git a/boot/include/hal/chips/pulpissimo/pulp.h b/sw/bootcode/include/hal/chips/pulpissimo/pulp.h similarity index 100% rename from boot/include/hal/chips/pulpissimo/pulp.h rename to sw/bootcode/include/hal/chips/pulpissimo/pulp.h diff --git a/boot/include/hal/fll/fll_v1.h b/sw/bootcode/include/hal/fll/fll_v1.h similarity index 86% rename from boot/include/hal/fll/fll_v1.h rename to sw/bootcode/include/hal/fll/fll_v1.h index 16574d90..c608d99b 100644 --- a/boot/include/hal/fll/fll_v1.h +++ b/sw/bootcode/include/hal/fll/fll_v1.h @@ -83,22 +83,22 @@ typedef enum { static inline unsigned int GetFllStatus(int Fll) { - return (unsigned int) IP_READ((int *) ARCHI_SOC_PERIPHERALS_ADDR, (int) (FLL_STATUS_OFFSET)); + return (unsigned int) IP_READ((int *) ARCHI_FLL_ADDR, (int) (FLL_STATUS_OFFSET)); } static inline unsigned int GetFllConfiguration(int Fll, hal_fll_config_e Reg) { int Offset = (int) (FLL_CONF1_OFFSET + Reg*4 + Fll*ARCHI_FLL_AREA_SIZE); - return (unsigned int) IP_READ(ARCHI_SOC_PERIPHERALS_ADDR, Offset); + return (unsigned int) IP_READ(ARCHI_FLL_ADDR, Offset); } static inline void SetFllConfiguration(int Fll, hal_fll_config_e Reg, unsigned int Value) { - IP_WRITE(ARCHI_SOC_PERIPHERALS_ADDR, FLL_CONF1_OFFSET + Reg*4 + Fll*ARCHI_FLL_AREA_SIZE, Value); + IP_WRITE(ARCHI_FLL_ADDR, FLL_CONF1_OFFSET + Reg*4 + Fll*ARCHI_FLL_AREA_SIZE, Value); } static inline unsigned int hal_fll_status_reg_get(int fll) { return IP_READ( - ARCHI_SOC_PERIPHERALS_ADDR, + ARCHI_FLL_ADDR, FLL_STATUS_OFFSET + fll*ARCHI_FLL_AREA_SIZE ); } @@ -106,7 +106,7 @@ static inline unsigned int hal_fll_status_reg_get(int fll) static inline void hal_fll_conf_reg1_set(int fll, unsigned int value) { IP_WRITE( - ARCHI_SOC_PERIPHERALS_ADDR, + ARCHI_FLL_ADDR, FLL_CONF1_OFFSET + fll*ARCHI_FLL_AREA_SIZE, value ); @@ -115,7 +115,7 @@ static inline void hal_fll_conf_reg1_set(int fll, unsigned int value) static inline unsigned int hal_fll_conf_reg1_get(int fll) { return IP_READ( - ARCHI_SOC_PERIPHERALS_ADDR, + ARCHI_FLL_ADDR, FLL_CONF1_OFFSET + fll*ARCHI_FLL_AREA_SIZE ); } @@ -123,7 +123,7 @@ static inline unsigned int hal_fll_conf_reg1_get(int fll) static inline void hal_fll_conf_reg2_set(int fll, unsigned int value) { IP_WRITE( - ARCHI_SOC_PERIPHERALS_ADDR, + ARCHI_FLL_ADDR, FLL_CONF2_OFFSET + fll*ARCHI_FLL_AREA_SIZE, value ); @@ -132,7 +132,7 @@ static inline void hal_fll_conf_reg2_set(int fll, unsigned int value) static inline unsigned int hal_fll_conf_reg2_get(int fll) { return IP_READ( - ARCHI_SOC_PERIPHERALS_ADDR, + ARCHI_FLL_ADDR, FLL_CONF2_OFFSET + fll*ARCHI_FLL_AREA_SIZE ); } @@ -140,7 +140,7 @@ static inline unsigned int hal_fll_conf_reg2_get(int fll) static inline void hal_fll_integrator_set(int fll, unsigned int value) { IP_WRITE( - ARCHI_SOC_PERIPHERALS_ADDR, + ARCHI_FLL_ADDR, FLL_INTEGRATOR_OFFSET + fll*ARCHI_FLL_AREA_SIZE, value ); @@ -149,7 +149,7 @@ static inline void hal_fll_integrator_set(int fll, unsigned int value) static inline unsigned int hal_fll_integrator_get(int fll) { return IP_READ( - ARCHI_SOC_PERIPHERALS_ADDR, + ARCHI_FLL_ADDR, FLL_INTEGRATOR_OFFSET + fll*ARCHI_FLL_AREA_SIZE ); } diff --git a/boot/include/hal/itc/itc_v1.h b/sw/bootcode/include/hal/itc/itc_v1.h similarity index 100% rename from boot/include/hal/itc/itc_v1.h rename to sw/bootcode/include/hal/itc/itc_v1.h diff --git a/boot/include/hal/pulp.h b/sw/bootcode/include/hal/pulp.h similarity index 100% rename from boot/include/hal/pulp.h rename to sw/bootcode/include/hal/pulp.h diff --git a/boot/include/hal/pulp_io.h b/sw/bootcode/include/hal/pulp_io.h similarity index 100% rename from boot/include/hal/pulp_io.h rename to sw/bootcode/include/hal/pulp_io.h diff --git a/boot/include/hal/riscv/riscv_v5.h b/sw/bootcode/include/hal/riscv/riscv_v5.h similarity index 100% rename from boot/include/hal/riscv/riscv_v5.h rename to sw/bootcode/include/hal/riscv/riscv_v5.h diff --git a/boot/include/hal/riscv/types.h b/sw/bootcode/include/hal/riscv/types.h similarity index 100% rename from boot/include/hal/riscv/types.h rename to sw/bootcode/include/hal/riscv/types.h diff --git a/boot/include/hal/rom/rom_v2.h b/sw/bootcode/include/hal/rom/rom_v2.h similarity index 100% rename from boot/include/hal/rom/rom_v2.h rename to sw/bootcode/include/hal/rom/rom_v2.h diff --git a/boot/include/hal/soc_eu/soc_eu_v2.h b/sw/bootcode/include/hal/soc_eu/soc_eu_v2.h similarity index 100% rename from boot/include/hal/soc_eu/soc_eu_v2.h rename to sw/bootcode/include/hal/soc_eu/soc_eu_v2.h diff --git a/boot/include/hal/soc_eu/soc_eu_v3.h b/sw/bootcode/include/hal/soc_eu/soc_eu_v3.h similarity index 100% rename from boot/include/hal/soc_eu/soc_eu_v3.h rename to sw/bootcode/include/hal/soc_eu/soc_eu_v3.h diff --git a/boot/include/hal/timer/timer_v2.h b/sw/bootcode/include/hal/timer/timer_v2.h similarity index 100% rename from boot/include/hal/timer/timer_v2.h rename to sw/bootcode/include/hal/timer/timer_v2.h diff --git a/boot/include/hal/udma/hyper/udma_hyper_v2.h b/sw/bootcode/include/hal/udma/hyper/udma_hyper_v2.h similarity index 100% rename from boot/include/hal/udma/hyper/udma_hyper_v2.h rename to sw/bootcode/include/hal/udma/hyper/udma_hyper_v2.h diff --git a/boot/include/hal/udma/spim/udma_spim_v3.h b/sw/bootcode/include/hal/udma/spim/udma_spim_v3.h similarity index 100% rename from boot/include/hal/udma/spim/udma_spim_v3.h rename to sw/bootcode/include/hal/udma/spim/udma_spim_v3.h diff --git a/boot/include/hal/udma/uart/uart_rb.h b/sw/bootcode/include/hal/udma/uart/uart_rb.h similarity index 100% rename from boot/include/hal/udma/uart/uart_rb.h rename to sw/bootcode/include/hal/udma/uart/uart_rb.h diff --git a/boot/include/hal/udma/uart/udma_uart_v1.h b/sw/bootcode/include/hal/udma/uart/udma_uart_v1.h similarity index 100% rename from boot/include/hal/udma/uart/udma_uart_v1.h rename to sw/bootcode/include/hal/udma/uart/udma_uart_v1.h diff --git a/boot/include/hal/udma/udma_v3.h b/sw/bootcode/include/hal/udma/udma_v3.h similarity index 100% rename from boot/include/hal/udma/udma_v3.h rename to sw/bootcode/include/hal/udma/udma_v3.h diff --git a/sw/bootcode/io_mux/include/io_mux.h b/sw/bootcode/io_mux/include/io_mux.h new file mode 100644 index 00000000..c716f368 --- /dev/null +++ b/sw/bootcode/io_mux/include/io_mux.h @@ -0,0 +1,198 @@ +/* + * Copyright (C) 2021 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Title: io_mux.h + * Author: Manuel Eggimann + * Date: 25.08.2021 + * + * Description: Control the pad configuration and multiplexing of the Siracusa chip + */ + +#ifndef IO_MUX_H +#define IO_MUX_H + +#ifndef LANGUAGE_ASSEMBLY + +#include +#include "pulpissimo_padframe_all_pads_regs.h" + +#define IO_MUX_PAD_CFG_REG_OFFSET 0x4 +#define IO_MUX_PAD_MUX_SEL_REG_OFFSET 0x8 +#define IO_MUX_PAD_REG_SEPARATION 0x8 + + +typedef enum { + IO_MUX_NO_PULL, ///< No pull resistor is enabled + IO_MUX_PULL_EN, ///< Enable internal pull-up/down (depends on pad kind) resistor +} io_mux_pull_cfg_e; + +/** + * Pad configuration struct + * + * Keep in mind, that certain peripherals might take over control of certain pad + * config signals (e.g. rx_en) if connected to a pad. The settings you provide + * through this API only take effect unless not overriden by the currently + * connected peripheral. + */ +typedef struct { + io_mux_pull_cfg_e pull_cfg; ///< Pull-up/down settings of the pad + uint8_t tx_en; ///< Tx enable + uint8_t rx_en; ///< Rx enable +} io_mux_cfg_t; + +/** + * Pad modes + * + * This enum defines all the different roles a particular IO pad can assume. + * Keep in mind, that except for the GPIO role you must not assign the same role + * to the more than one pad. + */ +typedef enum { + PAD_MODE_DISABLED = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_REGISTER, + PAD_MODE_CPI0_DATA0 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA0, + PAD_MODE_CPI0_DATA1 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA1, + PAD_MODE_CPI0_DATA2 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA2, + PAD_MODE_CPI0_DATA3 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA3, + PAD_MODE_CPI0_DATA4 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA4, + PAD_MODE_CPI0_DATA5 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA5, + PAD_MODE_CPI0_DATA6 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA6, + PAD_MODE_CPI0_DATA7 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA7, + PAD_MODE_CPI0_DATA8 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA8, + PAD_MODE_CPI0_DATA9 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA9, + PAD_MODE_CPI0_HSYNC = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_HSYNC, + PAD_MODE_CPI0_PCLK = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_PCLK, + PAD_MODE_CPI0_VSYNC = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_VSYNC, + PAD_MODE_GPIO = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_GPIO_GPIO00, + PAD_MODE_I2C0_SCL = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2C0_SCL, + PAD_MODE_I2C0_SDA = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2C0_SDA, + PAD_MODE_I2S0_MASTER_SCK = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK, + PAD_MODE_I2S0_MASTER_SD0 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0, + PAD_MODE_I2S0_MASTER_SD1 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1, + PAD_MODE_I2S0_MASTER_WS = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS, + PAD_MODE_I2S0_SLAVE_SCK = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK, + PAD_MODE_I2S0_SLAVE_SD0 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0, + PAD_MODE_I2S0_SLAVE_SD1 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1, + PAD_MODE_I2S0_SLAVE_WS = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS, + PAD_MODE_QSPIM0_CSN0 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_CSN0, + PAD_MODE_QSPIM0_CSN1 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_CSN1, + PAD_MODE_QSPIM0_CSN2 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_CSN2, + PAD_MODE_QSPIM0_CSN3 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_CSN3, + PAD_MODE_QSPIM0_SCK = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_SCK, + PAD_MODE_QSPIM0_SDIO0 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0, + PAD_MODE_QSPIM0_SDIO1 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1, + PAD_MODE_QSPIM0_SDIO2 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2, + PAD_MODE_QSPIM0_SDIO3 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3, + PAD_MODE_SDIO0_SDCLK = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDCLK, + PAD_MODE_SDIO0_SDCMD = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDCMD, + PAD_MODE_SDIO0_SDDATA0 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0, + PAD_MODE_SDIO0_SDDATA1 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1, + PAD_MODE_SDIO0_SDDATA2 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2, + PAD_MODE_SDIO0_SDDATA3 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3, + PAD_MODE_TIMER0_OUT0 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER0_OUT0, + PAD_MODE_TIMER0_OUT1 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER0_OUT1, + PAD_MODE_TIMER0_OUT2 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER0_OUT2, + PAD_MODE_TIMER0_OUT3 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER0_OUT3, + PAD_MODE_TIMER1_OUT0 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER1_OUT0, + PAD_MODE_TIMER1_OUT1 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER1_OUT1, + PAD_MODE_TIMER1_OUT2 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER1_OUT2, + PAD_MODE_TIMER1_OUT3 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER1_OUT3, + PAD_MODE_TIMER2_OUT0 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER2_OUT0, + PAD_MODE_TIMER2_OUT1 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER2_OUT1, + PAD_MODE_TIMER2_OUT2 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER2_OUT2, + PAD_MODE_TIMER2_OUT3 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER2_OUT3, + PAD_MODE_TIMER3_OUT0 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER3_OUT0, + PAD_MODE_TIMER3_OUT1 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER3_OUT1, + PAD_MODE_TIMER3_OUT2 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER3_OUT2, + PAD_MODE_TIMER3_OUT3 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER3_OUT3, + PAD_MODE_UART0_RX = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_UART0_RX, + PAD_MODE_UART0_TX = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_UART0_TX +} io_mux_mode_e; + +typedef enum { + PAD_GPIO00, + PAD_GPIO01, + PAD_GPIO02, + PAD_GPIO03, + PAD_GPIO04, + PAD_GPIO05, + PAD_GPIO06, + PAD_GPIO07, + PAD_GPIO08, + PAD_GPIO09, + PAD_GPIO10, + PAD_GPIO11, + PAD_GPIO12, + PAD_GPIO13, + PAD_GPIO14, + PAD_GPIO15, + PAD_GPIO16, + PAD_GPIO17, + PAD_GPIO18, + PAD_GPIO19, + PAD_GPIO20, + PAD_GPIO21, + PAD_GPIO22, + PAD_GPIO23, + PAD_GPIO24, + PAD_GPIO25, + PAD_GPIO26, + PAD_GPIO27, + PAD_GPIO28, + PAD_GPIO29, + PAD_GPIO30, + PAD_GPIO31, + NUM_PADS +} io_mux_pad_e; + +/** + * Change the pad configuration of the given pad + * + * @param pad The pad to configure + * @param cfg [in] The configuration settings for the pad + */ +void io_mux_config_set(io_mux_pad_e pad, io_mux_cfg_t const *cfg); + +/** + * Reads the current pad configuration from the pad control peripheral + * + * @param pad The pad from which to read the current configuration + * @param cfg [out] Pointer to the pad config structure where the obtained config will be written to + */ +void io_mux_config_get(io_mux_pad_e pad, io_mux_cfg_t *cfg); + +/** + * Change the pad mode (IO multiplex settings) + * + * This function reconfigures the pad multiplexer to route the given IO signal + * to the pad. You must only route the same IO signal to one pad. E.g. you must + * not put PAD_GPIO04 in mode PAD_MODE_I3C0_SCL while PAD_GPIO01 is already in + * the same mode. The only exception to this rule is the PAD_MODE_GPIO. You can + * put all pads into this mode simultaneously to have access to up to NUM_PADS + * GPIOs. + * + * @param pad The pad for which the pad multiplex setting should be changed + */ +void io_mux_mode_set(io_mux_pad_e pad, io_mux_mode_e mode); + +/** + * Obtain the current mode of a pad + * + * @param pad The pad for which to return the current pad mode + * @returns The current mode of the pad + */ +io_mux_mode_e io_mux_mode_get(io_mux_pad_e pad); + +#endif +#endif /* IO_MUX_H */ diff --git a/sw/bootcode/io_mux/include/pulpissimo_padframe_all_pads_regs.h b/sw/bootcode/io_mux/include/pulpissimo_padframe_all_pads_regs.h new file mode 100644 index 00000000..398806da --- /dev/null +++ b/sw/bootcode/io_mux/include/pulpissimo_padframe_all_pads_regs.h @@ -0,0 +1,4285 @@ +// Generated register defines for pulpissimo_padframe_all_pads_config + +// Licensing information found in source file: + +#ifndef _PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_REG_DEFS_ +#define _PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_REG_DEFS_ + +#ifdef __cplusplus +extern "C" { +#endif +// Register width +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PARAM_REG_WIDTH 32 + +// Read-only IP Information register +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_REG_OFFSET 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_HW_VERSION_MASK 0xffff +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_HW_VERSION_OFFSET 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_HW_VERSION_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_HW_VERSION_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_HW_VERSION_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_PADCOUNT_MASK 0xffff +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_PADCOUNT_OFFSET 16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_PADCOUNT_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_PADCOUNT_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_PADCOUNT_OFFSET }) + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_REG_OFFSET 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io00. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_REG_OFFSET 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_GPIO_GPIO00 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_CFG_REG_OFFSET 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io01. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_REG_OFFSET 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_GPIO_GPIO01 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_CFG_REG_OFFSET 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io02. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_REG_OFFSET 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_GPIO_GPIO02 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_CFG_REG_OFFSET 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io03. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_REG_OFFSET 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_GPIO_GPIO03 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_CFG_REG_OFFSET 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io04. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_REG_OFFSET 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_GPIO_GPIO04 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_CFG_REG_OFFSET 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io05. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_REG_OFFSET 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_GPIO_GPIO05 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_CFG_REG_OFFSET 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io06. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_REG_OFFSET 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_GPIO_GPIO06 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_CFG_REG_OFFSET 0x3c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io07. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_REG_OFFSET 0x40 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_GPIO_GPIO07 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_CFG_REG_OFFSET 0x44 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io08. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_REG_OFFSET 0x48 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_GPIO_GPIO08 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_CFG_REG_OFFSET 0x4c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io09. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_REG_OFFSET 0x50 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_GPIO_GPIO09 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_CFG_REG_OFFSET 0x54 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io10. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_REG_OFFSET 0x58 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_GPIO_GPIO10 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_CFG_REG_OFFSET 0x5c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io11. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_REG_OFFSET 0x60 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_GPIO_GPIO11 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_CFG_REG_OFFSET 0x64 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io12. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_REG_OFFSET 0x68 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_GPIO_GPIO12 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_CFG_REG_OFFSET 0x6c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io13. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_REG_OFFSET 0x70 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_GPIO_GPIO13 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_CFG_REG_OFFSET 0x74 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io14. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_REG_OFFSET 0x78 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_GPIO_GPIO14 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_CFG_REG_OFFSET 0x7c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io15. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_REG_OFFSET 0x80 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_GPIO_GPIO15 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_CFG_REG_OFFSET 0x84 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io16. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_REG_OFFSET 0x88 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_GPIO_GPIO16 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_CFG_REG_OFFSET 0x8c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io17. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_REG_OFFSET 0x90 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_GPIO_GPIO17 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_CFG_REG_OFFSET 0x94 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io18. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_REG_OFFSET 0x98 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_GPIO_GPIO18 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_CFG_REG_OFFSET 0x9c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io19. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_REG_OFFSET 0xa0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_GPIO_GPIO19 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_CFG_REG_OFFSET 0xa4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io20. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_REG_OFFSET 0xa8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_GPIO_GPIO20 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_CFG_REG_OFFSET 0xac +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io21. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_REG_OFFSET 0xb0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_GPIO_GPIO21 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_CFG_REG_OFFSET 0xb4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io22. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_REG_OFFSET 0xb8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_GPIO_GPIO22 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_CFG_REG_OFFSET 0xbc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io23. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_REG_OFFSET 0xc0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_GPIO_GPIO23 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_CFG_REG_OFFSET 0xc4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io24. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_REG_OFFSET 0xc8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_GPIO_GPIO24 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_CFG_REG_OFFSET 0xcc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io25. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_REG_OFFSET 0xd0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_GPIO_GPIO25 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_CFG_REG_OFFSET 0xd4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io26. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_REG_OFFSET 0xd8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_GPIO_GPIO26 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_CFG_REG_OFFSET 0xdc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io27. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_REG_OFFSET 0xe0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_GPIO_GPIO27 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_CFG_REG_OFFSET 0xe4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io28. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_REG_OFFSET 0xe8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_GPIO_GPIO28 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_CFG_REG_OFFSET 0xec +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io29. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_REG_OFFSET 0xf0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_GPIO_GPIO29 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_CFG_REG_OFFSET 0xf4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io30. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_REG_OFFSET 0xf8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_GPIO_GPIO30 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_CFG_REG_OFFSET 0xfc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io31. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_REG_OFFSET 0x100 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_GPIO_GPIO31 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_REG_DEFS_ +// End generated register defines for pulpissimo_padframe_all_pads_config \ No newline at end of file diff --git a/sw/bootcode/io_mux/pulpissimo_padframe_all_pads_regs.hjson b/sw/bootcode/io_mux/pulpissimo_padframe_all_pads_regs.hjson new file mode 100644 index 00000000..634d4356 --- /dev/null +++ b/sw/bootcode/io_mux/pulpissimo_padframe_all_pads_regs.hjson @@ -0,0 +1,4091 @@ + + +{ + # File auto-generated by Padrick unknown + name: "pulpissimo_padframe_all_pads_config" + clock_primary: "clk_i" + reset_primary: "rst_ni" + bus_interfaces: [ + { protocol: "reg_iface", direction: "device"} + ] + regwidth: 32, + registers: [ + {skipto: "0x0"}, + { + name: INFO + desc: "Read-only IP Information register" + swaccess: "ro" + hwaccess: "hro" + fields: [ + { + bits: "15:0" + name: HW_VERSION + desc: "Hardware version ID." + resval: 2 + }, + { + bits:"31:16" + name: PADCOUNT + desc: "The number of muxable pads in this IP." + resval: "32" + } + ] + } + + + + + + + + + + + + + + + + + + + + + + + + + { + name: PAD_IO00_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO00_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io00. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio00", desc: "Connect port gpio00 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO01_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO01_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io01. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio01", desc: "Connect port gpio01 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO02_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO02_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io02. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio02", desc: "Connect port gpio02 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO03_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO03_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io03. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio03", desc: "Connect port gpio03 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO04_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO04_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io04. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio04", desc: "Connect port gpio04 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO05_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO05_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io05. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio05", desc: "Connect port gpio05 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO06_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO06_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io06. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio06", desc: "Connect port gpio06 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO07_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO07_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io07. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio07", desc: "Connect port gpio07 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO08_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO08_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io08. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio08", desc: "Connect port gpio08 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO09_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO09_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io09. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio09", desc: "Connect port gpio09 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO10_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO10_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io10. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio10", desc: "Connect port gpio10 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO11_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO11_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io11. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio11", desc: "Connect port gpio11 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO12_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO12_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io12. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio12", desc: "Connect port gpio12 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO13_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO13_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io13. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio13", desc: "Connect port gpio13 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO14_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO14_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io14. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio14", desc: "Connect port gpio14 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO15_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO15_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io15. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio15", desc: "Connect port gpio15 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO16_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO16_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io16. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio16", desc: "Connect port gpio16 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO17_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO17_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io17. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio17", desc: "Connect port gpio17 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO18_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO18_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io18. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio18", desc: "Connect port gpio18 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO19_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO19_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io19. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio19", desc: "Connect port gpio19 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO20_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO20_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io20. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio20", desc: "Connect port gpio20 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO21_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO21_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io21. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio21", desc: "Connect port gpio21 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO22_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO22_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io22. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio22", desc: "Connect port gpio22 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO23_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO23_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io23. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio23", desc: "Connect port gpio23 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO24_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO24_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io24. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio24", desc: "Connect port gpio24 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO25_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO25_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io25. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio25", desc: "Connect port gpio25 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO26_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO26_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io26. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio26", desc: "Connect port gpio26 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO27_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO27_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io27. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio27", desc: "Connect port gpio27 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO28_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO28_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io28. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio28", desc: "Connect port gpio28 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO29_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO29_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io29. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio29", desc: "Connect port gpio29 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO30_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO30_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io30. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio30", desc: "Connect port gpio30 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO31_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO31_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io31. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio31", desc: "Connect port gpio31 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + ] +} diff --git a/sw/bootcode/io_mux/src/io_mux.c b/sw/bootcode/io_mux/src/io_mux.c new file mode 100644 index 00000000..732f959d --- /dev/null +++ b/sw/bootcode/io_mux/src/io_mux.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2021 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Title: io_mux.c + * Author: Manuel Eggimann + * Date: 25.08.2021 + * + * Description: Implementation for Siracusa's pad control IP driver + */ + +#include "io_mux.h" +#include "bitfield.h" + +#include "config.h" +#include "hal/pulp.h" +#include "archi/pulp.h" + +void io_mux_config_set(io_mux_pad_e pad, io_mux_cfg_t const *cfg) { + const uint32_t cfg_addr = ARCHI_PAD_CFG_ADDR + pad*IO_MUX_PAD_REG_SEPARATION + IO_MUX_PAD_CFG_REG_OFFSET; + uint32_t reg = pulp_read32(cfg_addr); + reg = bitfield_bit32_write(reg, PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_TX_EN_BIT, cfg->tx_en != 0); + reg = bitfield_bit32_write(reg, PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_RX_EN_BIT, cfg->rx_en != 0); + reg = bitfield_bit32_write(reg, PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_PULL_EN_BIT, cfg->pull_cfg != IO_MUX_NO_PULL); + pulp_write32(cfg_addr, reg); +} + +void io_mux_config_get(io_mux_pad_e pad, io_mux_cfg_t *cfg) { + const uint32_t cfg_addr = ARCHI_PAD_CFG_ADDR + pad*IO_MUX_PAD_REG_SEPARATION + IO_MUX_PAD_CFG_REG_OFFSET; + const uint32_t reg = pulp_read32(cfg_addr); + uint8_t pull_en; + cfg->tx_en = bitfield_bit32_read(reg, PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_TX_EN_BIT); + cfg->rx_en = bitfield_bit32_read(reg, PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_RX_EN_BIT); + pull_en = bitfield_bit32_read(reg, PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_PULL_EN_BIT); + cfg->pull_cfg = pull_en? IO_MUX_PULL_EN : IO_MUX_NO_PULL; +} + +void io_mux_mode_set(io_mux_pad_e pad, io_mux_mode_e mode) { + const uint32_t cfg_addr = ARCHI_PAD_CFG_ADDR + pad*IO_MUX_PAD_REG_SEPARATION + IO_MUX_PAD_MUX_SEL_REG_OFFSET; + uint32_t reg = pulp_read32(cfg_addr); + reg = bitfield_field32_write(reg, PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_FIELD, mode); + pulp_write32(cfg_addr, reg); +} + +io_mux_mode_e io_mux_mode_get(io_mux_pad_e pad) { + const uint32_t cfg_addr = ARCHI_PAD_CFG_ADDR + pad*IO_MUX_PAD_REG_SEPARATION + IO_MUX_PAD_MUX_SEL_REG_OFFSET; + const uint32_t reg = pulp_read32(cfg_addr); + return bitfield_field32_read(reg, PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_FIELD); +} diff --git a/boot/kk_srec.c b/sw/bootcode/kk_srec.c similarity index 100% rename from boot/kk_srec.c rename to sw/bootcode/kk_srec.c diff --git a/boot/kk_srec.h b/sw/bootcode/kk_srec.h similarity index 100% rename from boot/kk_srec.h rename to sw/bootcode/kk_srec.h diff --git a/boot/link.ld b/sw/bootcode/link.ld similarity index 100% rename from boot/link.ld rename to sw/bootcode/link.ld diff --git a/sw/bootcode/requirements.txt b/sw/bootcode/requirements.txt new file mode 100644 index 00000000..2d83f3fd --- /dev/null +++ b/sw/bootcode/requirements.txt @@ -0,0 +1 @@ +pyelftools==0.29 diff --git a/boot/s19toboot.py b/sw/bootcode/s19toboot.py old mode 100755 new mode 100644 similarity index 80% rename from boot/s19toboot.py rename to sw/bootcode/s19toboot.py index fa805bde..2c85b36b --- a/boot/s19toboot.py +++ b/sw/bootcode/s19toboot.py @@ -1,4 +1,4 @@ -#!/usr/bin/python +#!/usr/bin/env python3 # Copyright (C) 2018 ETH Zurich, University of Bologna and GreenWaves # Technologies @@ -49,7 +49,7 @@ if(len(sys.argv) < 3): - print "Usage s19toboot.py FILENAME OUT_FILENAME ARCHI" + print("Usage s19toboot.py FILENAME OUT_FILENAME ARCHI") quit() @@ -66,25 +66,25 @@ # Function to dump single bytes of a string to a file ############################################################################### def dump_bytes( filetoprint, addr, data_s): - for i in xrange(0,4,1): - filetoprint.write("@%08X %s\n" % ( addr+i, data_s[i*2:(i+1)*2] )) + for i in range(0,4,1): + filetoprint.write(b"@%08X %s\n" % ( addr+i, data_s[i*2:(i+1)*2] )) ############################################################################### # Read s19 file and put data bytes into a dictionary ############################################################################### def s19_parse(filename, s19_dict): - s19_file = open(filename, 'r') + s19_file = open(filename, 'rb') for line in s19_file: rec_field = line[:2] prefix = line[:4] - if rec_field == "S0" or prefix == "S009" or prefix == "S505" or prefix == "S705" or prefix == "S017" or prefix == "S804" or line == "": + if rec_field == b"S0" or prefix == b"S009" or prefix == b"S505" or prefix == b"S705" or prefix == b"S017" or prefix == b"S804" or line == b"": continue data = line[-6:-4] # extract data byte str_addr = line[4:-6] - addr = int("0x%s" % str_addr, 0) + addr = int(b"0x%s" % str_addr, 0) s19_dict[addr] = data @@ -96,7 +96,7 @@ def s19_parse(filename, s19_dict): def bytes_to_words(byte_dict, word_dict): for addr in byte_dict: wordaddr = addr >> 2 - data = "00000000" + data = b"00000000" if wordaddr in word_dict: data = word_dict[wordaddr] @@ -109,14 +109,13 @@ def bytes_to_words(byte_dict, word_dict): new = byte_dict[addr] if byte == 0: - data = "%s%s%s%s" % (byte0, byte1, byte2, new) + data = b"%s%s%s%s" % (byte0, byte1, byte2, new) elif byte == 1: - data = "%s%s%s%s" % (byte0, byte1, new, byte3) + data = b"%s%s%s%s" % (byte0, byte1, new, byte3) elif byte == 2: - data = "%s%s%s%s" % (byte0, new, byte2, byte3) + data = b"%s%s%s%s" % (byte0, new, byte2, byte3) elif byte == 3: - data = "%s%s%s%s" % (new, byte1, byte2, byte3) - + data = b"%s%s%s%s" % (new, byte1, byte2, byte3) word_dict[wordaddr] = data @@ -130,12 +129,11 @@ def bytes_to_words(byte_dict, word_dict): if len(sys.argv) > 3: archi = sys.argv[3] # fill slm_dict with 0's -for wordaddr in xrange(rom_start >> 2, (rom_end>>2) + 1): - slm_dict[wordaddr] = "00000000" +for wordaddr in range(rom_start >> 2, (rom_end>>2) + 1): + slm_dict[wordaddr] = b"00000000" bytes_to_words(s19_dict, slm_dict) - # word align all addresses rom_start = rom_start >> 2 rom_end = rom_end >> 2 @@ -145,11 +143,11 @@ def bytes_to_words(byte_dict, word_dict): ############################################################################### # open files ############################################################################### -rom_file = open(outfile, 'w') -vlog_file = open("boot_code.sv", 'w') +rom_file = open(outfile, 'wb') +vlog_file = open("boot_code.sv", 'wb') # prepare file -vlog_file.write(""" +vlog_file.write(b""" module boot_code ( input logic CLK, @@ -177,7 +175,7 @@ def bytes_to_words(byte_dict, word_dict): # sanity check if addr != addr_last + 1: - print "ERROR: Santiy check failed. Current addr {0:08X}, last addr {1:08X}".format(addr << 2, addr_last << 2) + print("ERROR: Santiy check failed. Current addr {0:08X}, last addr {1:08X}".format(addr << 2, addr_last << 2)) addr_last = addr is64 = archi != 'patronus' @@ -187,30 +185,30 @@ def bytes_to_words(byte_dict, word_dict): data_even = data else: data_odd = data - if archi == 'GAP': rom_file.write("@%x %s%s\n" % ((addr & 0xffff) / 2, data_odd, data_even)) + if archi == 'GAP': rom_file.write(b"@%x %s%s\n" % ((addr & 0xffff) / 2, data_odd, data_even)) elif archi in [ 'gap9', 'vega', 'wolfe', 'quentin', 'devchip', 'pulp', 'pulpissimo']: - rom_file.write("{0:032b}\n" .format(int('0x' + data_even, 16))) - rom_file.write("{0:032b}\n" .format(int('0x' + data_odd, 16))) + rom_file.write("{0:032b}\n" .format(int(b'0x' + data_even, 16)).encode()) + rom_file.write("{0:032b}\n" .format(int(b'0x' + data_odd, 16)).encode()) #rom_file.write("@%x %s\n" % ((addr & 0xffff)-1, data_even)) #rom_file.write("@%x %s\n" % ((addr & 0xffff), data_odd)) elif archi == 'vivosoc3': - rom_file.write("@%x %s\n" % ((addr & 0xffff)-1, data_even)) - rom_file.write("@%x %s\n" % ((addr & 0xffff), data_odd)) - else: rom_file.write("%s%s\n" % (data_odd, data_even)) - vlog_file.write(" 64'h%s%s,\n" % (data_odd, data_even)) + rom_file.write(b"@%x %s\n" % ((addr & 0xffff)-1, data_even)) + rom_file.write(b"@%x %s\n" % ((addr & 0xffff), data_odd)) + else: rom_file.write(b"%s%s\n" % (data_odd, data_even)) + vlog_file.write(b" 64'h%s%s,\n" % (data_odd, data_even)) else: if((addr%2) == 0): data_even = data rom_file.write("%s\n" % (data)) - vlog_file.write(" 32'h%s,\n" % (data)) + vlog_file.write(b" 32'h%s,\n" % (data)) else: data_odd = data rom_file.write("%s\n" % (data)) - vlog_file.write(" 32'h%s,\n" % (data)) + vlog_file.write(b" 32'h%s,\n" % (data)) # remove ,\n vlog_file.seek(-2, os.SEEK_END) -vlog_file.write("""}; +vlog_file.write(b"""}; logic [%d:0] A_Q; diff --git a/sw/bootcode/s19toboot.py.bak b/sw/bootcode/s19toboot.py.bak new file mode 100755 index 00000000..63ac86f0 --- /dev/null +++ b/sw/bootcode/s19toboot.py.bak @@ -0,0 +1,234 @@ +#!/usr/bin/env python3 + +# Copyright (C) 2018 ETH Zurich, University of Bologna and GreenWaves +# Technologies +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# //////////////////////////////////////////////////////////////////////////////// +# // Company: Multitherman Laboratory @ DEIS - University of Bologna // +# // Viale Risorgimento 2 40136 // +# // Bologna - fax 0512093785 - // +# // // +# // Engineer: Davide Rossi - davide.rossi@unibo.it // +# // // +# // Additional contributions by: // +# // Andreas Traber - atraber@student.ethz.ch // +# // Michael Gautschi - gautschi@iis.ethz.ch // +# // // +# // Create Date: 05/04/2013 // +# // Design Name: ULPSoC // +# // Project Name: ULPSoC // +# // Language: tcl, now python // +# // // +# // Description: s19 to slm conversion tool for stxp70 cluster compilation // +# // // +# // Revision: // +# // Revision v0.1 - File Created // +# // Revision v0.2 - Modification: Compiler does now generate little endian // +# // directly. revert bytes! // +# // Revision v0.3 - Moved from 128 bit s19 to 8 bit s19 file. This solves our // +# // problems with misaligned addresses in s19 files. // +# // Revision v0.5 - Rewrote the whole thing in python to be consistent with // +# // s19toslm // +# //////////////////////////////////////////////////////////////////////////////// + +import sys +import math +import os + + +if(len(sys.argv) < 3): + print "Usage s19toboot.py FILENAME OUT_FILENAME ARCHI" + quit() + + +rom_size = 1024 # in double words (64 bit) +rom_start = 0x1A000000 +rom_end = rom_start + rom_size * 8 - 1 + +l2_size = 128 # in double words (64 bit) +l2_start = 0x1C02FE00 +l2_end = l2_start + l2_size * 8 - 1 + + +############################################################################### +# Function to dump single bytes of a string to a file +############################################################################### +def dump_bytes( filetoprint, addr, data_s): + for i in xrange(0,4,1): + filetoprint.write("@%08X %s\n" % ( addr+i, data_s[i*2:(i+1)*2] )) + +############################################################################### +# Read s19 file and put data bytes into a dictionary +############################################################################### +def s19_parse(filename, s19_dict): + s19_file = open(filename, 'r') + for line in s19_file: + rec_field = line[:2] + prefix = line[:4] + + if rec_field == "S0" or prefix == "S009" or prefix == "S505" or prefix == "S705" or prefix == "S017" or prefix == "S804" or line == "": + continue + + data = line[-6:-4] # extract data byte + str_addr = line[4:-6] + + addr = int("0x%s" % str_addr, 0) + + s19_dict[addr] = data + + s19_file.close() + +############################################################################### +# arrange bytes in words +############################################################################### +def bytes_to_words(byte_dict, word_dict): + for addr in byte_dict: + wordaddr = addr >> 2 + data = "00000000" + + if wordaddr in word_dict: + data = word_dict[wordaddr] + + byte = addr % 4 + byte0 = data[0:2] + byte1 = data[2:4] + byte2 = data[4:6] + byte3 = data[6:8] + new = byte_dict[addr] + + if byte == 0: + data = "%s%s%s%s" % (byte0, byte1, byte2, new) + elif byte == 1: + data = "%s%s%s%s" % (byte0, byte1, new, byte3) + elif byte == 2: + data = "%s%s%s%s" % (byte0, new, byte2, byte3) + elif byte == 3: + data = "%s%s%s%s" % (new, byte1, byte2, byte3) + + word_dict[wordaddr] = data + + +s19_dict = {} +slm_dict = {} + +s19_parse(sys.argv[1], s19_dict) +outfile = sys.argv[2] + +archi = None +if len(sys.argv) > 3: archi = sys.argv[3] + +# fill slm_dict with 0's +for wordaddr in xrange(rom_start >> 2, (rom_end>>2) + 1): + slm_dict[wordaddr] = "00000000" + +bytes_to_words(s19_dict, slm_dict) + + +# word align all addresses +rom_start = rom_start >> 2 +rom_end = rom_end >> 2 +l2_start = l2_start >> 2 +l2_end = l2_end >> 2 + +############################################################################### +# open files +############################################################################### +rom_file = open(outfile, 'w') +vlog_file = open("boot_code.sv", 'w') + +# prepare file +vlog_file.write(""" +module boot_code +( + input logic CLK, + input logic RSTN, + + input logic CSN, + input logic [8:0] A, + output logic [63:0] Q + ); + + const logic [63:0] mem[0:%d] = { +""" % (rom_size-1)); + +############################################################################### +# write the stimuli +############################################################################### +addr_last = rom_start - 1 +for addr in sorted(slm_dict.keys()): + data = slm_dict[addr] + + # rom address range + if(addr >= rom_start and addr <= rom_end): + rom_base = addr - rom_start + rom_addr = (rom_base >> 1) + + # sanity check + if addr != addr_last + 1: + print "ERROR: Santiy check failed. Current addr {0:08X}, last addr {1:08X}".format(addr << 2, addr_last << 2) + addr_last = addr + + is64 = archi != 'patronus' + + if is64: + if((addr%2) == 0): + data_even = data + else: + data_odd = data + if archi == 'GAP': rom_file.write("@%x %s%s\n" % ((addr & 0xffff) / 2, data_odd, data_even)) + elif archi in [ 'gap9', 'vega', 'wolfe', 'quentin', 'devchip', 'pulp', 'pulpissimo']: + rom_file.write("{0:032b}\n" .format(int('0x' + data_even, 16))) + rom_file.write("{0:032b}\n" .format(int('0x' + data_odd, 16))) + #rom_file.write("@%x %s\n" % ((addr & 0xffff)-1, data_even)) + #rom_file.write("@%x %s\n" % ((addr & 0xffff), data_odd)) + elif archi == 'vivosoc3': + rom_file.write("@%x %s\n" % ((addr & 0xffff)-1, data_even)) + rom_file.write("@%x %s\n" % ((addr & 0xffff), data_odd)) + else: rom_file.write("%s%s\n" % (data_odd, data_even)) + vlog_file.write(" 64'h%s%s,\n" % (data_odd, data_even)) + else: + if((addr%2) == 0): + data_even = data + rom_file.write("%s\n" % (data)) + vlog_file.write(" 32'h%s,\n" % (data)) + else: + data_odd = data + rom_file.write("%s\n" % (data)) + vlog_file.write(" 32'h%s,\n" % (data)) + +# remove ,\n +vlog_file.seek(-2, os.SEEK_END) +vlog_file.write("""}; + + logic [%d:0] A_Q; + + always_ff @(posedge CLK or negedge RSTN) + begin + if (~RSTN) + A_Q <= '0; + else + if (~CSN) + A_Q <= A; + end + + assign Q = mem[A_Q]; + +endmodule""" % (math.log(rom_size, 2))); + +############################################################################### +# close all files +############################################################################### +rom_file.close() +vlog_file.close() diff --git a/boot/stim_utils.py b/sw/bootcode/stim_utils.py similarity index 100% rename from boot/stim_utils.py rename to sw/bootcode/stim_utils.py diff --git a/boot/zforth-riscv/.clang-format b/sw/bootcode/zforth-riscv/.clang-format similarity index 100% rename from boot/zforth-riscv/.clang-format rename to sw/bootcode/zforth-riscv/.clang-format diff --git a/boot/zforth-riscv/asm.h b/sw/bootcode/zforth-riscv/asm.h similarity index 100% rename from boot/zforth-riscv/asm.h rename to sw/bootcode/zforth-riscv/asm.h diff --git a/boot/zforth-riscv/libc.c b/sw/bootcode/zforth-riscv/libc.c similarity index 100% rename from boot/zforth-riscv/libc.c rename to sw/bootcode/zforth-riscv/libc.c diff --git a/boot/zforth-riscv/libc.h b/sw/bootcode/zforth-riscv/libc.h similarity index 100% rename from boot/zforth-riscv/libc.h rename to sw/bootcode/zforth-riscv/libc.h diff --git a/boot/zforth-riscv/setjmp.S b/sw/bootcode/zforth-riscv/setjmp.S similarity index 100% rename from boot/zforth-riscv/setjmp.S rename to sw/bootcode/zforth-riscv/setjmp.S diff --git a/boot/zforth-riscv/udma.c b/sw/bootcode/zforth-riscv/udma.c similarity index 100% rename from boot/zforth-riscv/udma.c rename to sw/bootcode/zforth-riscv/udma.c diff --git a/boot/zforth-riscv/udma.h b/sw/bootcode/zforth-riscv/udma.h similarity index 100% rename from boot/zforth-riscv/udma.h rename to sw/bootcode/zforth-riscv/udma.h diff --git a/boot/zforth-riscv/zfconf.h b/sw/bootcode/zforth-riscv/zfconf.h similarity index 100% rename from boot/zforth-riscv/zfconf.h rename to sw/bootcode/zforth-riscv/zfconf.h diff --git a/boot/zforth-riscv/zforth-main.c b/sw/bootcode/zforth-riscv/zforth-main.c similarity index 100% rename from boot/zforth-riscv/zforth-main.c rename to sw/bootcode/zforth-riscv/zforth-main.c diff --git a/boot/zforth/zforth.c b/sw/bootcode/zforth/zforth.c similarity index 100% rename from boot/zforth/zforth.c rename to sw/bootcode/zforth/zforth.c diff --git a/boot/zforth/zforth.h b/sw/bootcode/zforth/zforth.h similarity index 100% rename from boot/zforth/zforth.h rename to sw/bootcode/zforth/zforth.h diff --git a/sw/pulp-runtime b/sw/pulp-runtime new file mode 160000 index 00000000..ad0f614a --- /dev/null +++ b/sw/pulp-runtime @@ -0,0 +1 @@ +Subproject commit ad0f614a1b805255cfe9cea9a563b5a434d8770a diff --git a/sw/regression_tests b/sw/regression_tests new file mode 160000 index 00000000..eae705b1 --- /dev/null +++ b/sw/regression_tests @@ -0,0 +1 @@ +Subproject commit eae705b1b0094a5619b7d9d3b37f5050f5abc398 diff --git a/fpga/.gitignore b/target/fpga/.gitignore similarity index 100% rename from fpga/.gitignore rename to target/fpga/.gitignore diff --git a/target/fpga/Makefile b/target/fpga/Makefile new file mode 100644 index 00000000..0d630891 --- /dev/null +++ b/target/fpga/Makefile @@ -0,0 +1,121 @@ +.DEFAULT_GOAL:=help + +PULPISSIMO_ROOT ?= $(shell git rev-parse --show-toplevel) +.DEFAULT_GOAL := help +PULPISSIMO_FPGA_ROOT = $(PULPISSIMO_ROOT)/target/fpga +include $(PULPISSIMO_ROOT)/utils/utils.mk + +## @section FPGA Bitstream Generation + +all: genesys2 zcu104 nexys_video nexys zedboard zcu102 zcu106 ## Generates the bitstream for all supported boards board. + +clean_all: clean_genesys2 clean_zcu104 clean_nexys_video clean_nexys clean_zedboard clean_zcu102 ## Removes synthesis output and bitstreams for all boards. + +.PHONY: $(PULPISSIMO_FPGA_ROOT)/pulpissimo/tcl/generated/compile.tcl +$(PULPISSIMO_FPGA_ROOT)/pulpissimo/tcl/generated/compile.tcl: + mkdir -p $(PULPISSIMO_FPGA_ROOT)/pulpissimo/tcl/generated + $(PULPISSIMO_UTILS)/bender script vivado -t fpga -t xilinx > $@ + +## Generates the bistream for the genesys2 board +genesys2: $(PULPISSIMO_FPGA_ROOT)/pulpissimo/tcl/generated/compile.tcl + $(MAKE) -C $(PULPISSIMO_FPGA_ROOT)/pulpissimo-genesys2 all + cp $(PULPISSIMO_FPGA_ROOT)/pulpissimo-genesys2/pulpissimo-genesys2.runs/impl_1/xilinx_pulpissimo.bit $(PULPISSIMO_FPGA_ROOT)/pulpissimo_genesys2.bit + cp $(PULPISSIMO_FPGA_ROOT)/pulpissimo-genesys2/pulpissimo-genesys2.runs/impl_1/xilinx_pulpissimo.bin $(PULPISSIMO_FPGA_ROOT)/pulpissimo_genesys2.bin + @echo "Bitstream generation for genesys2 board finished. The bitstream Configuration Memory File was copied to ./pulpissimo_genesys2.bit and ./pulpissimo_genesys2.bin" + +## Removes all bitstreams, *.log files and vivado related files (rm -rf vivado*) for the genesys2 board. +clean_genesys2: + $(MAKE) -C $(PULPISSIMO_FPGA_ROOT)/pulpissimo-genesys2 clean + rm -f $(PULPISSIMO_FPGA_ROOT)/pulpissimo_genesys2.bit + rm -f $(PULPISSIMO_FPGA_ROOT)/pulpissimo_genesys2.bin + +## Generates the bistream for the zcu104 board +zcu104: $(PULPISSIMO_FPGA_ROOT)/pulpissimo/tcl/generated/compile.tcl + $(MAKE) -C $(PULPISSIMO_FPGA_ROOT)/pulpissimo-zcu104 all + cp $(PULPISSIMO_FPGA_ROOT)/pulpissimo-zcu104/pulpissimo-zcu104.runs/impl_1/xilinx_pulpissimo.bit $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zcu104.bit + cp $(PULPISSIMO_FPGA_ROOT)/pulpissimo-zcu104/pulpissimo-zcu104.runs/impl_1/xilinx_pulpissimo.bin $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zcu104.bin + @echo "Bitstream generation for zcu104 board finished. The bitstream Configuration Memory File was copied to ./pulpissimo_zcu104.bit and ./pulpissimo_zcu104.bin" + +## Removes all bitstreams, *.log files and vivado related files (rm -rf vivado*) for the zcu104 board. +clean_zcu104: + $(MAKE) -C $(PULPISSIMO_FPGA_ROOT)/pulpissimo-zcu104 clean + rm -f $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zcu104.bit + rm -f $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zcu104.bin + +## Generates the bistream for the zcu104 board +zcu106: $(PULPISSIMO_FPGA_ROOT)/pulpissimo/tcl/generated/compile.tcl + $(MAKE) -C $(PULPISSIMO_FPGA_ROOT)/pulpissimo-zcu106 all + cp $(PULPISSIMO_FPGA_ROOT)/pulpissimo-zcu106/pulpissimo-zcu106.runs/impl_1/xilinx_pulpissimo.bit $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zcu106.bit + cp $(PULPISSIMO_FPGA_ROOT)/pulpissimo-zcu106/pulpissimo-zcu106.runs/impl_1/xilinx_pulpissimo.bin $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zcu106.bin + @echo "Bitstream generation for zcu106 board finished. The bitstream Configuration Memory File was copied to ./pulpissimo_zcu106.bit and ./pulpissimo_zcu106.bin" + +## Removes all bitstreams, *.log files and vivado related files (rm -rf vivado*) for the zcu104 board. +clean_zcu106: + $(MAKE) -C $(PULPISSIMO_FPGA_ROOT)/pulpissimo-zcu106 clean + rm -f $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zcu106.bit + rm -f $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zcu106.bin + +## Generates the bistream for the nexys_video board +nexys_video: $(PULPISSIMO_FPGA_ROOT)/pulpissimo/tcl/generated/compile.tcl + $(MAKE) -C $(PULPISSIMO_FPGA_ROOT)/pulpissimo-nexys_video all + cp $(PULPISSIMO_FPGA_ROOT)/pulpissimo-nexys_video/pulpissimo-nexys_video.runs/impl_1/xilinx_pulpissimo.bit $(PULPISSIMO_FPGA_ROOT)/pulpissimo_nexys_video.bit + cp $(PULPISSIMO_FPGA_ROOT)/pulpissimo-nexys_video/pulpissimo-nexys_video.runs/impl_1/xilinx_pulpissimo.bin $(PULPISSIMO_FPGA_ROOT)/pulpissimo_nexys_video.bin + @echo "Bitstream generation for nexys_video board finished. The bitstream Configuration Memory File was copied to ./pulpissimo_nexys_video.bit and ./pulpissimo_nexys_video.bin" + +## Removes all bitstreams, *.log files and vivado related files (rm -rf vivado*) for the nexys_video board. +clean_nexys_video: + $(MAKE) -C $(PULPISSIMO_FPGA_ROOT)/pulpissimo-nexys_video clean + rm -f $(PULPISSIMO_FPGA_ROOT)/pulpissimo_nexys_video.bit + rm -f $(PULPISSIMO_FPGA_ROOT)/pulpissimo_nexys_video.bin + +## Generates the bistream for the nexys board. Use make nexys rev=[nexys4|nexys4DDR|nexysA7-50T|nexysA7-100T] +nexys: $(PULPISSIMO_FPGA_ROOT)/pulpissimo/tcl/generated/compile.tcl + $(MAKE) -C $(PULPISSIMO_FPGA_ROOT)/pulpissimo-nexys all + cp $(PULPISSIMO_FPGA_ROOT)/pulpissimo-nexys/pulpissimo-nexys.runs/impl_1/xilinx_pulpissimo.bit $(PULPISSIMO_FPGA_ROOT)/pulpissimo_nexys.bit + cp $(PULPISSIMO_FPGA_ROOT)/pulpissimo-nexys/pulpissimo-nexys.runs/impl_1/xilinx_pulpissimo.bin $(PULPISSIMO_FPGA_ROOT)/pulpissimo_nexys.bin + @echo "Bitstream generation for nexys board finished. The bitstream Configuration Memory File was copied to ./pulpissimo_nexys.bit and ./pulpissimo_nexys.bin" + +## Removes all bitstreams, *.log files and vivado related files (rm -rf vivado*) for the nexys board. +clean_nexys: + $(MAKE) -C $(PULPISSIMO_FPGA_ROOT)/pulpissimo-nexys clean + rm -f $(PULPISSIMO_FPGA_ROOT)/pulpissimo_nexys.bit + rm -f $(PULPISSIMO_FPGA_ROOT)/pulpissimo_nexys.bin + +## Generates the bistream for the vcu108 board +vcu108: $(PULPISSIMO_FPGA_ROOT)/pulpissimo/tcl/generated/compile.tcl + $(MAKE) -C $(PULPISSIMO_FPGA_ROOT)/pulpissimo-vcu108 all + cp $(PULPISSIMO_FPGA_ROOT)/pulpissimo-vcu108/pulpissimo-vcu108.runs/impl_1/xilinx_pulpissimo.bit $(PULPISSIMO_FPGA_ROOT)/pulpissimo_vcu108.bit + cp $(PULPISSIMO_FPGA_ROOT)/pulpissimo-vcu108/pulpissimo-vcu108.runs/impl_1/xilinx_pulpissimo.bin $(PULPISSIMO_FPGA_ROOT)/pulpissimo_vcu108.bin + @echo "Bitstream generation for vcu108 board finished. The bitstream Configuration Memory File was copied to ./pulpissimo_vcu108.bit and ./pulpissimo_vcu108.bin" + +## Removes all bitstreams, *.log files and vivado related files (rm -rf vivado*) for the vcu108 board. +clean_vcu108: + $(MAKE) -C $(PULPISSIMO_FPGA_ROOT)/pulpissimo-vcu108 clean + rm -f $(PULPISSIMO_FPGA_ROOT)/pulpissimo_vcu108.bit + rm -f $(PULPISSIMO_FPGA_ROOT)/pulpissimo_vcu108.bin + +## Generates the bistream for the ZedBoard +zedboard: $(PULPISSIMO_FPGA_ROOT)/pulpissimo/tcl/generated/compile.tcl + $(MAKE) -C $(PULPISSIMO_FPGA_ROOT)/pulpissimo-zedboard all + cp $(PULPISSIMO_FPGA_ROOT)/pulpissimo-zedboard/pulpissimo-zedboard.runs/impl_1/xilinx_pulpissimo.bit $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zedboard.bit + cp $(PULPISSIMO_FPGA_ROOT)/pulpissimo-zedboard/pulpissimo-zedboard.runs/impl_1/xilinx_pulpissimo.bin $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zedboard.bin + @echo "Bitstream generation for ZedBoard finished. The bitstream Configuration Memory File was copied to ./pulpissimo_zedboard.bit and ./pulpissimo_zedboard.bin" + +## Removes all bitstreams, *.log files and vivado related files (rm -rf vivado*) for the ZedBoard. +clean_zedboard: + $(MAKE) -C $(PULPISSIMO_FPGA_ROOT)/pulpissimo-zedboard clean + rm -f $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zedboard.bit + rm -f $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zedboard.bin + +## Generates the bistream for the zcu102 board +zcu102: $(PULPISSIMO_FPGA_ROOT)/pulpissimo/tcl/generated/compile.tcl + $(MAKE) -C $(PULPISSIMO_FPGA_ROOT)/pulpissimo-zcu102 all + cp $(PULPISSIMO_FPGA_ROOT)/pulpissimo-zcu102/pulpissimo-zcu102.runs/impl_1/xilinx_pulpissimo.bit $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zcu102.bit + cp $(PULPISSIMO_FPGA_ROOT)/pulpissimo-zcu102/pulpissimo-zcu102.runs/impl_1/xilinx_pulpissimo.bin $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zcu102.bin + @echo "Bitstream generation for zcu102 board finished. The bitstream Configuration Memory File was copied to ./pulpissimo_zcu102.bit and ./pulpissimo_zcu102.bin" + +## Removes all bitstreams, *.log files and vivado related files (rm -rf vivado*) for the zcu102 board. +clean_zcu102: + $(MAKE) -C $(PULPISSIMO_FPGA_ROOT)/pulpissimo-zcu102 clean + rm -f $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zcu102.bit + rm -f $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zcu102.bin diff --git a/fpga/pulpissimo-genesys2/.gitignore b/target/fpga/pulpissimo-genesys2/.gitignore similarity index 100% rename from fpga/pulpissimo-genesys2/.gitignore rename to target/fpga/pulpissimo-genesys2/.gitignore diff --git a/fpga/pulpissimo-genesys2/Makefile b/target/fpga/pulpissimo-genesys2/Makefile similarity index 100% rename from fpga/pulpissimo-genesys2/Makefile rename to target/fpga/pulpissimo-genesys2/Makefile diff --git a/fpga/pulpissimo-genesys2/README.md b/target/fpga/pulpissimo-genesys2/README.md similarity index 100% rename from fpga/pulpissimo-genesys2/README.md rename to target/fpga/pulpissimo-genesys2/README.md diff --git a/fpga/pulpissimo-genesys2/constraints/genesys2.xdc b/target/fpga/pulpissimo-genesys2/constraints/genesys2.xdc similarity index 81% rename from fpga/pulpissimo-genesys2/constraints/genesys2.xdc rename to target/fpga/pulpissimo-genesys2/constraints/genesys2.xdc index 6fb72ef5..4f4191ec 100644 --- a/fpga/pulpissimo-genesys2/constraints/genesys2.xdc +++ b/target/fpga/pulpissimo-genesys2/constraints/genesys2.xdc @@ -13,12 +13,6 @@ #Create constraint for the clock input of the genesys2 board create_clock -period 5.000 -name ref_clk [get_ports ref_clk_p] -#I2S and CAM interface are not used in this FPGA port. Set constraints to -#disable the clock -set_case_analysis 0 i_pulpissimo/safe_domain_i/cam_pclk_o -set_case_analysis 0 i_pulpissimo/safe_domain_i/i2s_slave_sck_o -#set_input_jitter tck 1.000 - ## JTAG create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports pad_jtag_tck] set_input_jitter tck 1.000 @@ -35,34 +29,49 @@ set_max_delay -from [get_ports pad_jtag_tms] 20.000 set_max_delay -from [get_ports pad_jtag_tdi] 20.000 set_max_delay -from [get_ports pad_jtag_trst] 20.000 -set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000 -set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000 -set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000 # reset signal set_false_path -from [get_ports pad_reset_n] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pad_reset_n_IBUF] + +set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_pulpissimo/i_clock_gen/i_slow_clk_div/i_clk_mux/clk_o] +set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_pulpissimo/i_clock_gen/i_slow_clk_mngr/inst/clk_out1] # Set ASYNC_REG attribute for ff synchronizers to place them closer together and # increase MTBF -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim0/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim1/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim2/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim3/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_timer_unit/s_ref_clk*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_ref_clk_sync/i_pulp_sync/r_reg_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/u_evnt_gen/r_ls_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim0/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim1/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim2/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim3/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_timer_unit/s_ref_clk*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_ref_clk_sync/i_pulp_sync/r_reg_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/u_evnt_gen/r_ls_sync_reg*] # Create asynchronous clock group between slow-clk and SoC clock. Those clocks # are considered asynchronously and proper synchronization regs are in place -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/safe_domain_i/i_slow_clk_gen/i_slow_clk_mngr/inst/mmcm_adv_inst/CLKOUT0]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/i_fpga_clk_gen/i_clk_manager/inst/mmcm_adv_inst/CLKOUT0]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/slow_clk_o]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] # Create asynchronous clock group between Per Clock and SoC clock. Those clocks # are considered asynchronously and proper synchronization regs are in place -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/clk_per_o]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/clk_soc_o]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out2]] # Create asynchronous clock group between JTAG TCK and SoC clock. -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/clk_soc_o]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] + +# Create asynchronous clock group between JTAG TCK and per clock. +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out2]] + +# Create asynchronous clock group between slow clock and JTAG TCK. +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/slow_clk_o]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] ############################################################# # _____ ____ _____ _ _ _ # @@ -124,6 +133,8 @@ set_property -dict {PACKAGE_PIN AE30 IOSTANDARD LVCMOS33} [get_ports pad_i2c0_sc set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS33} [get_ports pad_i2c0_sda] ## QSPI Flash +# This is unlikely to be correct, setting the pin just to have a connection +set_property -dict {PACKAGE_PIN P24 IOSTANDARD LVCMOS33} [get_ports pad_spim_sck] set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS33} [get_ports pad_spim_csn0] #set_property -dict { PACKAGE_PIN P24 IOSTANDARD LVCMOS33 } [get_ports { pad_spim_sdio0 }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_d[0] set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVCMOS33} [get_ports pad_spim_sdio1] diff --git a/fpga/pulpissimo-genesys2/elf_run.gdb b/target/fpga/pulpissimo-genesys2/elf_run.gdb similarity index 100% rename from fpga/pulpissimo-genesys2/elf_run.gdb rename to target/fpga/pulpissimo-genesys2/elf_run.gdb diff --git a/fpga/pulpissimo-genesys2/elf_run.sh b/target/fpga/pulpissimo-genesys2/elf_run.sh similarity index 100% rename from fpga/pulpissimo-genesys2/elf_run.sh rename to target/fpga/pulpissimo-genesys2/elf_run.sh diff --git a/fpga/pulpissimo-genesys2/fpga-settings.mk b/target/fpga/pulpissimo-genesys2/fpga-settings.mk similarity index 100% rename from fpga/pulpissimo-genesys2/fpga-settings.mk rename to target/fpga/pulpissimo-genesys2/fpga-settings.mk diff --git a/fpga/pulpissimo-genesys2/ips/xilinx_clk_mngr/.gitignore b/target/fpga/pulpissimo-genesys2/ips/xilinx_clk_mngr/.gitignore similarity index 100% rename from fpga/pulpissimo-genesys2/ips/xilinx_clk_mngr/.gitignore rename to target/fpga/pulpissimo-genesys2/ips/xilinx_clk_mngr/.gitignore diff --git a/fpga/pulpissimo-genesys2/ips/xilinx_clk_mngr/Makefile b/target/fpga/pulpissimo-genesys2/ips/xilinx_clk_mngr/Makefile similarity index 100% rename from fpga/pulpissimo-genesys2/ips/xilinx_clk_mngr/Makefile rename to target/fpga/pulpissimo-genesys2/ips/xilinx_clk_mngr/Makefile diff --git a/fpga/pulpissimo-genesys2/ips/xilinx_clk_mngr/tcl/run.tcl b/target/fpga/pulpissimo-genesys2/ips/xilinx_clk_mngr/tcl/run.tcl similarity index 100% rename from fpga/pulpissimo-genesys2/ips/xilinx_clk_mngr/tcl/run.tcl rename to target/fpga/pulpissimo-genesys2/ips/xilinx_clk_mngr/tcl/run.tcl diff --git a/fpga/pulpissimo-genesys2/ips/xilinx_slow_clk_mngr/.gitignore b/target/fpga/pulpissimo-genesys2/ips/xilinx_slow_clk_mngr/.gitignore similarity index 100% rename from fpga/pulpissimo-genesys2/ips/xilinx_slow_clk_mngr/.gitignore rename to target/fpga/pulpissimo-genesys2/ips/xilinx_slow_clk_mngr/.gitignore diff --git a/fpga/pulpissimo-genesys2/ips/xilinx_slow_clk_mngr/Makefile b/target/fpga/pulpissimo-genesys2/ips/xilinx_slow_clk_mngr/Makefile similarity index 100% rename from fpga/pulpissimo-genesys2/ips/xilinx_slow_clk_mngr/Makefile rename to target/fpga/pulpissimo-genesys2/ips/xilinx_slow_clk_mngr/Makefile diff --git a/fpga/pulpissimo-genesys2/ips/xilinx_slow_clk_mngr/tcl/run.tcl b/target/fpga/pulpissimo-genesys2/ips/xilinx_slow_clk_mngr/tcl/run.tcl similarity index 100% rename from fpga/pulpissimo-genesys2/ips/xilinx_slow_clk_mngr/tcl/run.tcl rename to target/fpga/pulpissimo-genesys2/ips/xilinx_slow_clk_mngr/tcl/run.tcl diff --git a/fpga/pulpissimo-genesys2/openocd-genesys2.cfg b/target/fpga/pulpissimo-genesys2/openocd-genesys2.cfg similarity index 100% rename from fpga/pulpissimo-genesys2/openocd-genesys2.cfg rename to target/fpga/pulpissimo-genesys2/openocd-genesys2.cfg diff --git a/fpga/pulpissimo-genesys2/rtl/cv32e40p_clock_gate_xilinx.sv b/target/fpga/pulpissimo-genesys2/rtl/cv32e40p_clock_gate_xilinx.sv similarity index 100% rename from fpga/pulpissimo-genesys2/rtl/cv32e40p_clock_gate_xilinx.sv rename to target/fpga/pulpissimo-genesys2/rtl/cv32e40p_clock_gate_xilinx.sv diff --git a/fpga/pulpissimo-genesys2/rtl/fpga_bootrom.sv b/target/fpga/pulpissimo-genesys2/rtl/fpga_bootrom.sv similarity index 100% rename from fpga/pulpissimo-genesys2/rtl/fpga_bootrom.sv rename to target/fpga/pulpissimo-genesys2/rtl/fpga_bootrom.sv diff --git a/fpga/pulpissimo-genesys2/rtl/fpga_clk_gen.sv b/target/fpga/pulpissimo-genesys2/rtl/fpga_clk_gen.sv similarity index 100% rename from fpga/pulpissimo-genesys2/rtl/fpga_clk_gen.sv rename to target/fpga/pulpissimo-genesys2/rtl/fpga_clk_gen.sv diff --git a/fpga/pulpissimo-genesys2/rtl/fpga_slow_clk_gen.sv b/target/fpga/pulpissimo-genesys2/rtl/fpga_slow_clk_gen.sv similarity index 100% rename from fpga/pulpissimo-genesys2/rtl/fpga_slow_clk_gen.sv rename to target/fpga/pulpissimo-genesys2/rtl/fpga_slow_clk_gen.sv diff --git a/fpga/pulpissimo-genesys2/rtl/pad_functional_xilinx.sv b/target/fpga/pulpissimo-genesys2/rtl/pad_functional_xilinx.sv similarity index 100% rename from fpga/pulpissimo-genesys2/rtl/pad_functional_xilinx.sv rename to target/fpga/pulpissimo-genesys2/rtl/pad_functional_xilinx.sv diff --git a/fpga/pulpissimo-genesys2/rtl/pulp_clock_gating_xilinx.sv b/target/fpga/pulpissimo-genesys2/rtl/pulp_clock_gating_xilinx.sv similarity index 100% rename from fpga/pulpissimo-genesys2/rtl/pulp_clock_gating_xilinx.sv rename to target/fpga/pulpissimo-genesys2/rtl/pulp_clock_gating_xilinx.sv diff --git a/target/fpga/pulpissimo-genesys2/rtl/xilinx_pulpissimo.v b/target/fpga/pulpissimo-genesys2/rtl/xilinx_pulpissimo.v new file mode 100644 index 00000000..fb0a11b6 --- /dev/null +++ b/target/fpga/pulpissimo-genesys2/rtl/xilinx_pulpissimo.v @@ -0,0 +1,157 @@ +//----------------------------------------------------------------------------- +// Title : PULPissimo Verilog Wrapper +//----------------------------------------------------------------------------- +// File : xilinx_pulpissimo.v +// Author : Manuel Eggimann +// Created : 21.05.2019 +//----------------------------------------------------------------------------- +// Description : +// Verilog Wrapper of PULPissimo to use the module within Xilinx IP integrator. +//----------------------------------------------------------------------------- +// Copyright (C) 2013-2019 ETH Zurich, University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +//----------------------------------------------------------------------------- + +module xilinx_pulpissimo ( + input wire ref_clk_p, + input wire ref_clk_n, + + // inout wire pad_spim_sdio0, + inout wire pad_spim_sdio1, + inout wire pad_spim_sdio2, + inout wire pad_spim_sdio3, + inout wire pad_spim_csn0, + inout wire pad_spim_sck, + + inout wire pad_uart_rx, + inout wire pad_uart_tx, + + inout wire led0_o, //Mapped to spim_csn1 + inout wire led1_o, //Mapped to cam_pclk + inout wire led2_o, //Mapped to cam_hsync + inout wire led3_o, //Mapped to cam_data0 + + inout wire switch0_i, //Mapped to cam_data1 + inout wire switch1_i, //Mapped to cam_data2 + + inout wire btnc_i, //Mapped to cam_data3 + inout wire btnd_i, //Mapped to cam_data4 + inout wire btnl_i, //Mapped to cam_data5 + inout wire btnr_i, //Mapped to cam_data6 + inout wire btnu_i, //Mapped to cam_data7 + + inout wire oled_spim_sck_o, //Mapped to spim_sck + inout wire oled_spim_mosi_o, //Mapped to spim_sdio0 + inout wire oled_rst_o, //Mapped to i2s0_sck + inout wire oled_dc_o, //Mapped to i2s0_ws + inout wire oled_vbat_o, // Mapped to i2s0_sdi + inout wire oled_vdd_o, // Mapped to i2s1_sdi + + inout wire sdio_reset_o, //Reset signal for SD card need to be driven low to + //power the onboard sd-card. Mapped to cam_vsync. + inout wire pad_sdio_clk, + inout wire pad_sdio_cmd, + inout wire pad_sdio_data0, + inout wire pad_sdio_data1, + inout wire pad_sdio_data2, + inout wire pad_sdio_data3, + + inout wire pad_i2c0_sda, + inout wire pad_i2c0_scl, + + input wire pad_reset_n, + + inout wire pad_jtag_tck, + inout wire pad_jtag_tdi, + inout wire pad_jtag_tdo, + inout wire pad_jtag_tms, + inout wire pad_jtag_trst +); + + localparam CORE_TYPE = 0; // 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY) + localparam USE_FPU = 1; + localparam USE_HWPE = 0; + + wire ref_clk; + + + //Differential to single ended clock conversion + IBUFGDS #( + .IOSTANDARD("LVDS"), + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") + ) i_sysclk_iobuf ( + .I(ref_clk_p), + .IB(ref_clk_n), + .O(ref_clk) + ); + + pulpissimo #( + .CORE_TYPE(CORE_TYPE), + .USE_FPU(USE_FPU), + .USE_HWPE(USE_HWPE) + ) i_pulpissimo ( + .pad_ref_clk ( ref_clk ), + .pad_reset_n ( pad_reset_n ), + .pad_clk_byp_en ( 1'b0 ), + + .pad_bootsel0 ( ), // Tied to 0 in run.tcl + .pad_bootsel1 ( ), // Tied to 0 in run.tcl + + .pad_jtag_tck ( pad_jtag_tck ), + .pad_jtag_tdi ( pad_jtag_tdi ), + .pad_jtag_tdo ( pad_jtag_tdo ), + .pad_jtag_tms ( pad_jtag_tms ), + .pad_jtag_trstn ( pad_jtag_trst ), + + .pad_hyper_csn ( ), // Tied to 0 in run.tcl + .pad_hyper_reset_n ( ), // Tied to 0 in run.tcl + .pad_hyper_ck ( ), // Tied to 0 in run.tcl + .pad_hyper_ckn ( ), // Tied to 0 in run.tcl + .pad_hyper_dq ( ), // Tied to 0 in run.tcl + .pad_hyper_rwds ( ), // Tied to 0 in run.tcl + + .pad_io ( { + pad_i2c0_scl, // io_31 + pad_i2c0_sda, // io_30 + pad_sdio_data3, // io_29 + pad_sdio_data2, // io_28 + pad_sdio_data1, // io_27 + pad_sdio_data0, // io_26 + pad_sdio_cmd, // io_25 + pad_sdio_clk, // io_24 + oled_vdd_o, // io_23 + oled_vbat_o, // io_22 + oled_dc_o, // io_21 + oled_rst_o, // io_20 + oled_spim_sck_o, // io_19 + btnu_i, // io_18 + btnr_i, // io_17 + btnl_i, // io_16 + btnd_i, // io_15 + btnc_i, // io_14 + switch1_i, // io_13 + switch0_i, // io_12 + led3_o, // io_11 + led2_o, // io_10 + led1_o, // io_09 + led0_o, // io_08 + pad_spim_sdio3, // io_07 + pad_spim_sdio2, // io_06 + pad_spim_sdio1, // io_05 + oled_spim_mosi_o, // io_04 + pad_spim_csn0, // io_03 + pad_spim_sck, // io_02 + pad_uart_rx, // io_01 + pad_uart_tx // io_00 + } ) + ); + +endmodule diff --git a/fpga/pulpissimo-genesys2/tcl/.gitignore b/target/fpga/pulpissimo-genesys2/tcl/.gitignore similarity index 100% rename from fpga/pulpissimo-genesys2/tcl/.gitignore rename to target/fpga/pulpissimo-genesys2/tcl/.gitignore diff --git a/fpga/pulpissimo-genesys2/tcl/common.tcl b/target/fpga/pulpissimo-genesys2/tcl/common.tcl similarity index 100% rename from fpga/pulpissimo-genesys2/tcl/common.tcl rename to target/fpga/pulpissimo-genesys2/tcl/common.tcl diff --git a/fpga/pulpissimo-genesys2/tcl/download_bitstream.tcl b/target/fpga/pulpissimo-genesys2/tcl/download_bitstream.tcl similarity index 100% rename from fpga/pulpissimo-genesys2/tcl/download_bitstream.tcl rename to target/fpga/pulpissimo-genesys2/tcl/download_bitstream.tcl diff --git a/fpga/pulpissimo-genesys2/tcl/run.tcl b/target/fpga/pulpissimo-genesys2/tcl/run.tcl similarity index 85% rename from fpga/pulpissimo-genesys2/tcl/run.tcl rename to target/fpga/pulpissimo-genesys2/tcl/run.tcl index bb826638..1e1ef1e4 100644 --- a/fpga/pulpissimo-genesys2/tcl/run.tcl +++ b/target/fpga/pulpissimo-genesys2/tcl/run.tcl @@ -73,10 +73,15 @@ open_run synth_1 -name netlist_1 set_property needs_refresh false [get_runs synth_1] # Remove unused IOBUF cells in padframe (they are not optimized away since the -# pad driver also drives the input creating a datapath from pad_xy_o to pad_xy_i -# ) -remove_cell i_pulpissimo/pad_frame_i/padinst_bootsel0 -remove_cell i_pulpissimo/pad_frame_i/padinst_bootsel1 +# pad driver also drives the input creating a datapath from pad_xy_o to pad_xy_i) +# Disconnect the nets and connect them to ground to avoid issues in optimization +remove_cell i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_bootsel* +disconnect_net -objects [get_nets i_pulpissimo/i_soc_domain/bootsel_i*] +connect_net -objects [get_nets i_pulpissimo/i_soc_domain/bootsel_i*] -net i_pulpissimo/ + +remove_cell i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_hyper* +disconnect_net -objects [get_nets i_pulpissimo/i_soc_domain/pad_to_hyper_i*] +connect_net -objects [get_nets i_pulpissimo/i_soc_domain/pad_to_hyper_i*] -net i_pulpissimo/ # Launch Implementation diff --git a/fpga/pulpissimo-nexys/.gitignore b/target/fpga/pulpissimo-nexys/.gitignore similarity index 100% rename from fpga/pulpissimo-nexys/.gitignore rename to target/fpga/pulpissimo-nexys/.gitignore diff --git a/fpga/pulpissimo-nexys/Makefile b/target/fpga/pulpissimo-nexys/Makefile similarity index 100% rename from fpga/pulpissimo-nexys/Makefile rename to target/fpga/pulpissimo-nexys/Makefile diff --git a/fpga/pulpissimo-nexys/README.md b/target/fpga/pulpissimo-nexys/README.md similarity index 100% rename from fpga/pulpissimo-nexys/README.md rename to target/fpga/pulpissimo-nexys/README.md diff --git a/fpga/pulpissimo-nexys/constraints/nexys4.xdc b/target/fpga/pulpissimo-nexys/constraints/nexys4.xdc similarity index 69% rename from fpga/pulpissimo-nexys/constraints/nexys4.xdc rename to target/fpga/pulpissimo-nexys/constraints/nexys4.xdc index 5cf3d2aa..ffe52459 100644 --- a/fpga/pulpissimo-nexys/constraints/nexys4.xdc +++ b/target/fpga/pulpissimo-nexys/constraints/nexys4.xdc @@ -24,16 +24,10 @@ #Create constraint for the clock input of the nexys 4 board create_clock -period 10.000 -name ref_clk [get_ports sys_clk] -#I2S and CAM interface are not used in this FPGA port. Set constraints to -#disable the clock -set_case_analysis 0 i_pulpissimo/safe_domain_i/cam_pclk_o -set_case_analysis 0 i_pulpissimo/safe_domain_i/i2s_slave_sck_o -#set_input_jitter tck 1.000 - ## JTAG create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports pad_jtag_tck] set_input_jitter tck 1.000 -set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets tck_int] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_jtag_tck/O] # minimize routing delay @@ -46,34 +40,49 @@ set_max_delay -to [get_ports pad_jtag_tdo] 20.000 set_max_delay -from [get_ports pad_jtag_tms] 20.000 set_max_delay -from [get_ports pad_jtag_tdi] 20.000 -set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000 -set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000 -set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000 # reset signal set_false_path -from [get_ports pad_reset_n] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pad_reset_n_IBUF] + +set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_pulpissimo/i_clock_gen/i_slow_clk_div/i_clk_mux/clk_o] +set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_pulpissimo/i_clock_gen/i_slow_clk_mngr/inst/clk_out1] # Set ASYNC_REG attribute for ff synchronizers to place them closer together and # increase MTBF -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim0/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim1/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim2/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim3/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_timer_unit/s_ref_clk*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_ref_clk_sync/i_pulp_sync/r_reg_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/u_evnt_gen/r_ls_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim0/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim1/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim2/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim3/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc_i/soc_peripherals_i/i_apb_timer_unit/s_ref_clk*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc_i/soc_peripherals_i/i_ref_clk_sync/i_pulp_sync/r_reg_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc_i/soc_peripherals_i/u_evnt_gen/r_ls_sync_reg*] # Create asynchronous clock group between slow-clk and SoC clock. Those clocks # are considered asynchronously and proper synchronization regs are in place -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/safe_domain_i/i_slow_clk_gen/i_slow_clk_mngr/inst/mmcm_adv_inst/CLKOUT0]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/i_fpga_clk_gen/i_clk_manager/inst/mmcm_adv_inst/CLKOUT0]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/slow_clk_o]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] # Create asynchronous clock group between Per Clock and SoC clock. Those clocks # are considered asynchronously and proper synchronization regs are in place -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/clk_per_o]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/clk_soc_o]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out2]] # Create asynchronous clock group between JTAG TCK and SoC clock. -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/clk_soc_o]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] + +# Create asynchronous clock group between JTAG TCK and per clock. +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out2]] + +# Create asynchronous clock group between slow clock and JTAG TCK. +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/slow_clk_o]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] ############################################################# # _____ ____ _____ _ _ _ # diff --git a/fpga/pulpissimo-nexys/constraints/nexys4DDR.xdc b/target/fpga/pulpissimo-nexys/constraints/nexys4DDR.xdc similarity index 69% rename from fpga/pulpissimo-nexys/constraints/nexys4DDR.xdc rename to target/fpga/pulpissimo-nexys/constraints/nexys4DDR.xdc index ee338cc2..219592f6 100644 --- a/fpga/pulpissimo-nexys/constraints/nexys4DDR.xdc +++ b/target/fpga/pulpissimo-nexys/constraints/nexys4DDR.xdc @@ -7,10 +7,8 @@ # __/ | # |___/ - ### Constraint File for the Nexys 4 DDR and Nexys A7-100T/A7-50T boards - ####################################### # _______ _ _ # # |__ __(_) (_) # @@ -26,16 +24,10 @@ #Create constraint for the clock input of the nexys board create_clock -period 10.000 -name ref_clk [get_ports sys_clk] -#I2S and CAM interface are not used in this FPGA port. Set constraints to -#disable the clock -set_case_analysis 0 i_pulpissimo/safe_domain_i/cam_pclk_o -set_case_analysis 0 i_pulpissimo/safe_domain_i/i2s_slave_sck_o -#set_input_jitter tck 1.000 - ## JTAG create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports pad_jtag_tck] set_input_jitter tck 1.000 -set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets tck_int] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_jtag_tck/O] # minimize routing delay @@ -48,35 +40,49 @@ set_max_delay -to [get_ports pad_jtag_tdo] 20.000 set_max_delay -from [get_ports pad_jtag_tms] 20.000 set_max_delay -from [get_ports pad_jtag_tdi] 20.000 - -set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000 -set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000 -set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000 # reset signal set_false_path -from [get_ports pad_reset_n] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pad_reset_n_IBUF] + +set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_pulpissimo/i_clock_gen/i_slow_clk_div/i_clk_mux/clk_o] +set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_pulpissimo/i_clock_gen/i_slow_clk_mngr/inst/clk_out1] # Set ASYNC_REG attribute for ff synchronizers to place them closer together and # increase MTBF -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim0/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim1/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim2/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim3/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_timer_unit/s_ref_clk*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_ref_clk_sync/i_pulp_sync/r_reg_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/u_evnt_gen/r_ls_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim0/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim1/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim2/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim3/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc_i/soc_peripherals_i/i_apb_timer_unit/s_ref_clk*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc_i/soc_peripherals_i/i_ref_clk_sync/i_pulp_sync/r_reg_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc_i/soc_peripherals_i/u_evnt_gen/r_ls_sync_reg*] # Create asynchronous clock group between slow-clk and SoC clock. Those clocks # are considered asynchronously and proper synchronization regs are in place -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/safe_domain_i/i_slow_clk_gen/i_slow_clk_mngr/inst/mmcm_adv_inst/CLKOUT0]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/i_fpga_clk_gen/i_clk_manager/inst/mmcm_adv_inst/CLKOUT0]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/slow_clk_o]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] # Create asynchronous clock group between Per Clock and SoC clock. Those clocks # are considered asynchronously and proper synchronization regs are in place -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/clk_per_o]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/clk_soc_o]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out2]] # Create asynchronous clock group between JTAG TCK and SoC clock. -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/clk_soc_o]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] + +# Create asynchronous clock group between JTAG TCK and per clock. +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out2]] + +# Create asynchronous clock group between slow clock and JTAG TCK. +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/slow_clk_o]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] ############################################################# # _____ ____ _____ _ _ _ # diff --git a/fpga/pulpissimo-nexys/elf_run.gdb b/target/fpga/pulpissimo-nexys/elf_run.gdb similarity index 100% rename from fpga/pulpissimo-nexys/elf_run.gdb rename to target/fpga/pulpissimo-nexys/elf_run.gdb diff --git a/fpga/pulpissimo-nexys/elf_run.sh b/target/fpga/pulpissimo-nexys/elf_run.sh similarity index 100% rename from fpga/pulpissimo-nexys/elf_run.sh rename to target/fpga/pulpissimo-nexys/elf_run.sh diff --git a/fpga/pulpissimo-nexys/fpga-settings.mk b/target/fpga/pulpissimo-nexys/fpga-settings.mk similarity index 100% rename from fpga/pulpissimo-nexys/fpga-settings.mk rename to target/fpga/pulpissimo-nexys/fpga-settings.mk diff --git a/fpga/pulpissimo-nexys/ips/xilinx_clk_mngr/.gitignore b/target/fpga/pulpissimo-nexys/ips/xilinx_clk_mngr/.gitignore similarity index 100% rename from fpga/pulpissimo-nexys/ips/xilinx_clk_mngr/.gitignore rename to target/fpga/pulpissimo-nexys/ips/xilinx_clk_mngr/.gitignore diff --git a/fpga/pulpissimo-nexys/ips/xilinx_clk_mngr/Makefile b/target/fpga/pulpissimo-nexys/ips/xilinx_clk_mngr/Makefile similarity index 100% rename from fpga/pulpissimo-nexys/ips/xilinx_clk_mngr/Makefile rename to target/fpga/pulpissimo-nexys/ips/xilinx_clk_mngr/Makefile diff --git a/fpga/pulpissimo-nexys/ips/xilinx_clk_mngr/tcl/run.tcl b/target/fpga/pulpissimo-nexys/ips/xilinx_clk_mngr/tcl/run.tcl similarity index 100% rename from fpga/pulpissimo-nexys/ips/xilinx_clk_mngr/tcl/run.tcl rename to target/fpga/pulpissimo-nexys/ips/xilinx_clk_mngr/tcl/run.tcl diff --git a/fpga/pulpissimo-nexys/ips/xilinx_slow_clk_mngr/.gitignore b/target/fpga/pulpissimo-nexys/ips/xilinx_slow_clk_mngr/.gitignore similarity index 100% rename from fpga/pulpissimo-nexys/ips/xilinx_slow_clk_mngr/.gitignore rename to target/fpga/pulpissimo-nexys/ips/xilinx_slow_clk_mngr/.gitignore diff --git a/fpga/pulpissimo-nexys/ips/xilinx_slow_clk_mngr/Makefile b/target/fpga/pulpissimo-nexys/ips/xilinx_slow_clk_mngr/Makefile similarity index 100% rename from fpga/pulpissimo-nexys/ips/xilinx_slow_clk_mngr/Makefile rename to target/fpga/pulpissimo-nexys/ips/xilinx_slow_clk_mngr/Makefile diff --git a/fpga/pulpissimo-nexys/ips/xilinx_slow_clk_mngr/tcl/run.tcl b/target/fpga/pulpissimo-nexys/ips/xilinx_slow_clk_mngr/tcl/run.tcl similarity index 100% rename from fpga/pulpissimo-nexys/ips/xilinx_slow_clk_mngr/tcl/run.tcl rename to target/fpga/pulpissimo-nexys/ips/xilinx_slow_clk_mngr/tcl/run.tcl diff --git a/fpga/pulpissimo-nexys/openocd-nexys-hs2.cfg b/target/fpga/pulpissimo-nexys/openocd-nexys-hs2.cfg similarity index 100% rename from fpga/pulpissimo-nexys/openocd-nexys-hs2.cfg rename to target/fpga/pulpissimo-nexys/openocd-nexys-hs2.cfg diff --git a/fpga/pulpissimo-nexys/rtl/cv32e40p_clock_gate_xilinx.sv b/target/fpga/pulpissimo-nexys/rtl/cv32e40p_clock_gate_xilinx.sv similarity index 100% rename from fpga/pulpissimo-nexys/rtl/cv32e40p_clock_gate_xilinx.sv rename to target/fpga/pulpissimo-nexys/rtl/cv32e40p_clock_gate_xilinx.sv diff --git a/fpga/pulpissimo-nexys/rtl/fpga_bootrom.sv b/target/fpga/pulpissimo-nexys/rtl/fpga_bootrom.sv similarity index 100% rename from fpga/pulpissimo-nexys/rtl/fpga_bootrom.sv rename to target/fpga/pulpissimo-nexys/rtl/fpga_bootrom.sv diff --git a/fpga/pulpissimo-nexys/rtl/fpga_clk_gen.sv b/target/fpga/pulpissimo-nexys/rtl/fpga_clk_gen.sv similarity index 100% rename from fpga/pulpissimo-nexys/rtl/fpga_clk_gen.sv rename to target/fpga/pulpissimo-nexys/rtl/fpga_clk_gen.sv diff --git a/fpga/pulpissimo-nexys/rtl/fpga_slow_clk_gen.sv b/target/fpga/pulpissimo-nexys/rtl/fpga_slow_clk_gen.sv similarity index 100% rename from fpga/pulpissimo-nexys/rtl/fpga_slow_clk_gen.sv rename to target/fpga/pulpissimo-nexys/rtl/fpga_slow_clk_gen.sv diff --git a/fpga/pulpissimo-nexys/rtl/pad_functional_xilinx.sv b/target/fpga/pulpissimo-nexys/rtl/pad_functional_xilinx.sv similarity index 100% rename from fpga/pulpissimo-nexys/rtl/pad_functional_xilinx.sv rename to target/fpga/pulpissimo-nexys/rtl/pad_functional_xilinx.sv diff --git a/fpga/pulpissimo-nexys/rtl/pulp_clock_gating_xilinx.sv b/target/fpga/pulpissimo-nexys/rtl/pulp_clock_gating_xilinx.sv similarity index 100% rename from fpga/pulpissimo-nexys/rtl/pulp_clock_gating_xilinx.sv rename to target/fpga/pulpissimo-nexys/rtl/pulp_clock_gating_xilinx.sv diff --git a/target/fpga/pulpissimo-nexys/rtl/xilinx_pulpissimo.v b/target/fpga/pulpissimo-nexys/rtl/xilinx_pulpissimo.v new file mode 100644 index 00000000..607ca954 --- /dev/null +++ b/target/fpga/pulpissimo-nexys/rtl/xilinx_pulpissimo.v @@ -0,0 +1,189 @@ +//----------------------------------------------------------------------------- +// Title : PULPissimo Verilog Wrapper +//----------------------------------------------------------------------------- +// File : xilinx_pulpissimo.v +// Author : Manuel Eggimann +// Created : 21.05.2019 +//----------------------------------------------------------------------------- +// Description : +// Verilog Wrapper of PULPissimo to use the module within Xilinx IP integrator. +//----------------------------------------------------------------------------- +// Copyright (C) 2013-2019 ETH Zurich, University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +//----------------------------------------------------------------------------- + +module xilinx_pulpissimo ( + input wire sys_clk, + + inout wire pad_spim_sdio0, + inout wire pad_spim_sdio1, + inout wire pad_spim_sdio2, + inout wire pad_spim_sdio3, + inout wire pad_spim_csn0, + inout wire pad_spim_sck, + + inout wire pad_uart_rx, //Mapped to uart_rx + inout wire pad_uart_tx, //Mapped to uart_tx + //inout wire pad_uart_cts, //Not mapped, optional + //inout wire pad_uart_rts, //Not mapped, optional + + inout wire led0_o, //Mapped to spim_csn1 + inout wire led1_o, //Mapped to cam_pclk + inout wire led2_o, //Mapped to cam_hsync + inout wire led3_o, //Mapped to cam_data0 + + inout wire switch0_i, //Mapped to cam_data1 + inout wire switch1_i, //Mapped to cam_data2 + + inout wire btnc_i, //Mapped to cam_data3 + inout wire btnd_i, //Mapped to cam_data4 + inout wire btnl_i, //Mapped to cam_data5 + inout wire btnr_i, //Mapped to cam_data6 + inout wire btnu_i, //Mapped to cam_data7 + + + inout wire sdio_reset_o, //Reset signal for SD card need to be driven low to + //power the onboard sd-card. Mapped to cam_vsync. + inout wire pad_sdio_clk, + inout wire pad_sdio_cmd, + inout wire pad_sdio_data0, + inout wire pad_sdio_data1, + inout wire pad_sdio_data2, + inout wire pad_sdio_data3, + + inout wire pad_i2c0_sda, + inout wire pad_i2c0_scl, + + inout wire pad_i2s0_sck, + inout wire pad_i2s0_ws, + inout wire pad_i2s0_sdi, + inout wire pad_i2s1_sdi, + + input wire pad_reset_n, + + inout wire pad_jtag_tck, + inout wire pad_jtag_tdi, + input wire pad_jtag_tdo, + inout wire pad_jtag_tms + //input wire pad_jtag_trst + ); + + localparam CORE_TYPE = 0; // 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY) + localparam USE_FPU = 1; + localparam USE_HWPE = 0; + + wire ref_clk; + // wire tck_int; + //wire pad_spim_sck; + + // Input clock buffer + IBUFG #( + .IOSTANDARD("LVCMOS33"), + .IBUF_LOW_PWR("FALSE") + ) i_sysclk_iobuf ( + .I(sys_clk), + .O(ref_clk) + ); + + //JTAG TCK clock buffer (dedicated route is false in constraints) + // IBUF i_tck_iobuf ( + // .I(pad_jtag_tck), + // .O(tck_int) + // ); + + // The SPI-Flash SCK Pin P8 is a configuration pin + // Therefore we must use a primitive to access it + // Thes SPI flash is currently not in use as an extended modification of the pad_frame is nessecary + // (IOBUF of the Pads can only drive signal connected to an I/O pin and not a signal to another primitive). + + //wire [3:0] su_nc; // Startup primitive output, no connect + // STARTUPE2 #( + // .PROG_USR("FALSE"), // Activate program event security feature. Requires encrypted bitstreams. + // .SIM_CCLK_FREQ(0.0) // Set the Configuration Clock Frequency(ns) for simulation. + // ) + // STARTUPE2_inst ( + // .CFGCLK(su_nc[0]), // 1-bit output: Configuration main clock output + // .CFGMCLK(su_nc[1]), // 1-bit output: Configuration internal oscillator clock output + // .EOS(su_nc[2]), // 1-bit output: Active high output signal indicating the End Of Startup. + // .PREQ(su_nc[3]), // 1-bit output: PROGRAM request to fabric output + // .CLK(1'b0), // 1-bit input: User start-up clock input + // .GSR(1'b0), // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name) + // .GTS(1'b0), // 1-bit input: Global 3-state input (GTS cannot be used for the port name) + // .KEYCLEARB(1'b0), // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM) + // .PACK(1'b0), // 1-bit input: PROGRAM acknowledge input + // .USRCCLKO(pad_spim_sck), // 1-bit input: User CCLK input -> the access to SPI SCK + // .USRCCLKTS(1'b0), // 1-bit input: User CCLK 3-state enable input + // .USRDONEO(1'b1), // 1-bit input: User DONE pin output control + // .USRDONETS(1'b1) // 1-bit input: User DONE 3-state enable outpu + + // ); + + pulpissimo #( + .CORE_TYPE(CORE_TYPE), + .USE_FPU(USE_FPU), + .USE_HWPE(USE_HWPE) + ) i_pulpissimo ( + .pad_ref_clk ( ref_clk ), + .pad_reset_n ( pad_reset_n ), + .pad_clk_byp_en ( 1'b0 ), + + .pad_bootsel0 (), // Tied to 0 in run.tcl + .pad_bootsel1 (), // Tied to 0 in run.tcl + + .pad_jtag_tck (pad_jtag_tck), + .pad_jtag_tdi (pad_jtag_tdi), + .pad_jtag_tdo (pad_jtag_tdo), + .pad_jtag_tms (pad_jtag_tms), + .pad_jtag_trstn (), // tied to 1 in run.tcl + + .pad_hyper_csn ( ), // Tied to 0 in run.tcl + .pad_hyper_reset_n ( ), // Tied to 0 in run.tcl + .pad_hyper_ck ( ), // Tied to 0 in run.tcl + .pad_hyper_ckn ( ), // Tied to 0 in run.tcl + .pad_hyper_dq ( ), // Tied to 0 in run.tcl + .pad_hyper_rwds ( ), // Tied to 0 in run.tcl + + .pad_io ( { + pad_i2c0_scl, // io_31 + pad_i2c0_sda, // io_30 + pad_sdio_data3, // io_29 + pad_sdio_data2, // io_28 + pad_sdio_data1, // io_27 + pad_sdio_data0, // io_26 + pad_sdio_cmd, // io_25 + pad_sdio_clk, // io_24 + sdio_reset_o, // io_23 + pad_i2s1_sdi, // io_22 + pad_i2s0_sdi, // io_21 + pad_i2s0_ws, // io_20 + pad_i2s0_sck, // io_19 + btnu_i, // io_18 + btnr_i, // io_17 + btnl_i, // io_16 + btnd_i, // io_15 + btnc_i, // io_14 + switch1_i, // io_13 + switch0_i, // io_12 + led3_o, // io_11 + led2_o, // io_10 + led1_o, // io_09 + led0_o, // io_08 + pad_spim_sdio3, // io_07 + pad_spim_sdio2, // io_06 + pad_spim_sdio1, // io_05 + pad_spim_sdio0, // io_04 + pad_spim_csn0, // io_03 + pad_spim_sck, // io_02 + pad_uart_rx, // io_01 + pad_uart_tx // io_00 + } ) + ); + +endmodule diff --git a/fpga/pulpissimo-nexys/tcl/.gitignore b/target/fpga/pulpissimo-nexys/tcl/.gitignore similarity index 100% rename from fpga/pulpissimo-nexys/tcl/.gitignore rename to target/fpga/pulpissimo-nexys/tcl/.gitignore diff --git a/fpga/pulpissimo-nexys/tcl/common.tcl b/target/fpga/pulpissimo-nexys/tcl/common.tcl similarity index 100% rename from fpga/pulpissimo-nexys/tcl/common.tcl rename to target/fpga/pulpissimo-nexys/tcl/common.tcl diff --git a/fpga/pulpissimo-nexys/tcl/download_bitstream.tcl b/target/fpga/pulpissimo-nexys/tcl/download_bitstream.tcl similarity index 100% rename from fpga/pulpissimo-nexys/tcl/download_bitstream.tcl rename to target/fpga/pulpissimo-nexys/tcl/download_bitstream.tcl diff --git a/fpga/pulpissimo-nexys/tcl/run.tcl b/target/fpga/pulpissimo-nexys/tcl/run.tcl similarity index 81% rename from fpga/pulpissimo-nexys/tcl/run.tcl rename to target/fpga/pulpissimo-nexys/tcl/run.tcl index ce65333b..49b2a1f5 100644 --- a/fpga/pulpissimo-nexys/tcl/run.tcl +++ b/target/fpga/pulpissimo-nexys/tcl/run.tcl @@ -83,10 +83,19 @@ open_run synth_1 -name netlist_1 set_property needs_refresh false [get_runs synth_1] # Remove unused IOBUF cells in padframe (they are not optimized away since the -# pad driver also drives the input creating a datapath from pad_xy_o to pad_xy_i -# ) -remove_cell i_pulpissimo/pad_frame_i/padinst_bootsel0 -remove_cell i_pulpissimo/pad_frame_i/padinst_bootsel1 +# pad driver also drives the input creating a datapath from pad_xy_o to pad_xy_i) +# Disconnect the nets and connect them to ground to avoid issues in optimization +remove_cell i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_bootsel* +disconnect_net -objects [get_nets i_pulpissimo/i_soc_domain/bootsel_i*] +connect_net -objects [get_nets i_pulpissimo/i_soc_domain/bootsel_i*] -net i_pulpissimo/ + +remove_cell i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_hyper* +disconnect_net -objects [get_nets i_pulpissimo/i_soc_domain/pad_to_hyper_i*] +connect_net -objects [get_nets i_pulpissimo/i_soc_domain/pad_to_hyper_i*] -net i_pulpissimo/ + +remove_cell i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_jtag_trst* +disconnect_net -objects [get_nets i_pulpissimo/i_soc_domain/jtag_trst_ni] +connect_net -objects [get_nets i_pulpissimo/i_soc_domain/jtag_trst_ni] -net i_pulpissimo/ # Launch Implementation diff --git a/fpga/pulpissimo-nexys_video/.gitignore b/target/fpga/pulpissimo-nexys_video/.gitignore similarity index 100% rename from fpga/pulpissimo-nexys_video/.gitignore rename to target/fpga/pulpissimo-nexys_video/.gitignore diff --git a/fpga/pulpissimo-nexys_video/Makefile b/target/fpga/pulpissimo-nexys_video/Makefile similarity index 100% rename from fpga/pulpissimo-nexys_video/Makefile rename to target/fpga/pulpissimo-nexys_video/Makefile diff --git a/fpga/pulpissimo-nexys_video/README.md b/target/fpga/pulpissimo-nexys_video/README.md similarity index 100% rename from fpga/pulpissimo-nexys_video/README.md rename to target/fpga/pulpissimo-nexys_video/README.md diff --git a/fpga/pulpissimo-nexys_video/constraints/nexys_video.xdc b/target/fpga/pulpissimo-nexys_video/constraints/nexys_video.xdc similarity index 69% rename from fpga/pulpissimo-nexys_video/constraints/nexys_video.xdc rename to target/fpga/pulpissimo-nexys_video/constraints/nexys_video.xdc index 713d8839..6be20fb0 100644 --- a/fpga/pulpissimo-nexys_video/constraints/nexys_video.xdc +++ b/target/fpga/pulpissimo-nexys_video/constraints/nexys_video.xdc @@ -13,12 +13,6 @@ #Create constraint for the clock input of the nexys video board create_clock -period 10.000 -name ref_clk [get_ports sys_clk] -#I2S and CAM interface are not used in this FPGA port. Set constraints to -#disable the clock -set_case_analysis 0 i_pulpissimo/safe_domain_i/cam_pclk_o -set_case_analysis 0 i_pulpissimo/safe_domain_i/i2s_slave_sck_o -#set_input_jitter tck 1.000 - ## JTAG create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports pad_jtag_tck] set_input_jitter tck 1.000 @@ -35,34 +29,49 @@ set_max_delay -from [get_ports pad_jtag_tms] 20.000 set_max_delay -from [get_ports pad_jtag_tdi] 20.000 set_max_delay -from [get_ports pad_jtag_trst] 20.000 -set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000 -set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000 -set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000 # reset signal set_false_path -from [get_ports pad_reset_n] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pad_reset_n_IBUF] + +set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_pulpissimo/i_clock_gen/i_slow_clk_mngr/inst/clk_out1] +set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_pulpissimo/i_clock_gen/i_slow_clk_div/i_clk_mux/clk_o] # Set ASYNC_REG attribute for ff synchronizers to place them closer together and # increase MTBF -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim0/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim1/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim2/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim3/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_timer_unit/s_ref_clk*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_ref_clk_sync/i_pulp_sync/r_reg_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/u_evnt_gen/r_ls_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim0/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim1/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim2/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim3/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_timer_unit/s_ref_clk*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_ref_clk_sync/i_pulp_sync/r_reg_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/u_evnt_gen/r_ls_sync_reg*] # Create asynchronous clock group between slow-clk and SoC clock. Those clocks # are considered asynchronously and proper synchronization regs are in place -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/safe_domain_i/i_slow_clk_gen/i_slow_clk_mngr/inst/mmcm_adv_inst/CLKOUT0]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/i_fpga_clk_gen/i_clk_manager/inst/mmcm_adv_inst/CLKOUT0]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/slow_clk_o]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] # Create asynchronous clock group between Per Clock and SoC clock. Those clocks # are considered asynchronously and proper synchronization regs are in place -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/clk_per_o]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/clk_soc_o]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out2]] # Create asynchronous clock group between JTAG TCK and SoC clock. -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/clk_soc_o]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] + +# Create asynchronous clock group between JTAG TCK and per clock. +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out2]] + +# Create asynchronous clock group between slow clock and JTAG TCK. +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/slow_clk_o]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] ############################################################# # _____ ____ _____ _ _ _ # diff --git a/fpga/pulpissimo-nexys_video/elf_run.gdb b/target/fpga/pulpissimo-nexys_video/elf_run.gdb similarity index 100% rename from fpga/pulpissimo-nexys_video/elf_run.gdb rename to target/fpga/pulpissimo-nexys_video/elf_run.gdb diff --git a/fpga/pulpissimo-nexys_video/elf_run.sh b/target/fpga/pulpissimo-nexys_video/elf_run.sh similarity index 100% rename from fpga/pulpissimo-nexys_video/elf_run.sh rename to target/fpga/pulpissimo-nexys_video/elf_run.sh diff --git a/fpga/pulpissimo-nexys_video/fpga-settings.mk b/target/fpga/pulpissimo-nexys_video/fpga-settings.mk similarity index 100% rename from fpga/pulpissimo-nexys_video/fpga-settings.mk rename to target/fpga/pulpissimo-nexys_video/fpga-settings.mk diff --git a/fpga/pulpissimo-nexys_video/ips/xilinx_clk_mngr/.gitignore b/target/fpga/pulpissimo-nexys_video/ips/xilinx_clk_mngr/.gitignore similarity index 100% rename from fpga/pulpissimo-nexys_video/ips/xilinx_clk_mngr/.gitignore rename to target/fpga/pulpissimo-nexys_video/ips/xilinx_clk_mngr/.gitignore diff --git a/fpga/pulpissimo-nexys_video/ips/xilinx_clk_mngr/Makefile b/target/fpga/pulpissimo-nexys_video/ips/xilinx_clk_mngr/Makefile similarity index 100% rename from fpga/pulpissimo-nexys_video/ips/xilinx_clk_mngr/Makefile rename to target/fpga/pulpissimo-nexys_video/ips/xilinx_clk_mngr/Makefile diff --git a/fpga/pulpissimo-nexys_video/ips/xilinx_clk_mngr/tcl/run.tcl b/target/fpga/pulpissimo-nexys_video/ips/xilinx_clk_mngr/tcl/run.tcl similarity index 100% rename from fpga/pulpissimo-nexys_video/ips/xilinx_clk_mngr/tcl/run.tcl rename to target/fpga/pulpissimo-nexys_video/ips/xilinx_clk_mngr/tcl/run.tcl diff --git a/fpga/pulpissimo-nexys_video/ips/xilinx_slow_clk_mngr/.gitignore b/target/fpga/pulpissimo-nexys_video/ips/xilinx_slow_clk_mngr/.gitignore similarity index 100% rename from fpga/pulpissimo-nexys_video/ips/xilinx_slow_clk_mngr/.gitignore rename to target/fpga/pulpissimo-nexys_video/ips/xilinx_slow_clk_mngr/.gitignore diff --git a/fpga/pulpissimo-nexys_video/ips/xilinx_slow_clk_mngr/Makefile b/target/fpga/pulpissimo-nexys_video/ips/xilinx_slow_clk_mngr/Makefile similarity index 100% rename from fpga/pulpissimo-nexys_video/ips/xilinx_slow_clk_mngr/Makefile rename to target/fpga/pulpissimo-nexys_video/ips/xilinx_slow_clk_mngr/Makefile diff --git a/fpga/pulpissimo-nexys_video/ips/xilinx_slow_clk_mngr/tcl/run.tcl b/target/fpga/pulpissimo-nexys_video/ips/xilinx_slow_clk_mngr/tcl/run.tcl similarity index 100% rename from fpga/pulpissimo-nexys_video/ips/xilinx_slow_clk_mngr/tcl/run.tcl rename to target/fpga/pulpissimo-nexys_video/ips/xilinx_slow_clk_mngr/tcl/run.tcl diff --git a/fpga/pulpissimo-nexys_video/openocd-nexys_video.cfg b/target/fpga/pulpissimo-nexys_video/openocd-nexys_video.cfg similarity index 100% rename from fpga/pulpissimo-nexys_video/openocd-nexys_video.cfg rename to target/fpga/pulpissimo-nexys_video/openocd-nexys_video.cfg diff --git a/fpga/pulpissimo-nexys_video/rtl/cv32e40p_clock_gate_xilinx.sv b/target/fpga/pulpissimo-nexys_video/rtl/cv32e40p_clock_gate_xilinx.sv similarity index 100% rename from fpga/pulpissimo-nexys_video/rtl/cv32e40p_clock_gate_xilinx.sv rename to target/fpga/pulpissimo-nexys_video/rtl/cv32e40p_clock_gate_xilinx.sv diff --git a/fpga/pulpissimo-nexys_video/rtl/fpga_bootrom.sv b/target/fpga/pulpissimo-nexys_video/rtl/fpga_bootrom.sv similarity index 100% rename from fpga/pulpissimo-nexys_video/rtl/fpga_bootrom.sv rename to target/fpga/pulpissimo-nexys_video/rtl/fpga_bootrom.sv diff --git a/fpga/pulpissimo-nexys_video/rtl/fpga_clk_gen.sv b/target/fpga/pulpissimo-nexys_video/rtl/fpga_clk_gen.sv similarity index 100% rename from fpga/pulpissimo-nexys_video/rtl/fpga_clk_gen.sv rename to target/fpga/pulpissimo-nexys_video/rtl/fpga_clk_gen.sv diff --git a/fpga/pulpissimo-nexys_video/rtl/fpga_slow_clk_gen.sv b/target/fpga/pulpissimo-nexys_video/rtl/fpga_slow_clk_gen.sv similarity index 100% rename from fpga/pulpissimo-nexys_video/rtl/fpga_slow_clk_gen.sv rename to target/fpga/pulpissimo-nexys_video/rtl/fpga_slow_clk_gen.sv diff --git a/fpga/pulpissimo-nexys_video/rtl/pad_functional_xilinx.sv b/target/fpga/pulpissimo-nexys_video/rtl/pad_functional_xilinx.sv similarity index 100% rename from fpga/pulpissimo-nexys_video/rtl/pad_functional_xilinx.sv rename to target/fpga/pulpissimo-nexys_video/rtl/pad_functional_xilinx.sv diff --git a/fpga/pulpissimo-nexys_video/rtl/pulp_clock_gating_xilinx.sv b/target/fpga/pulpissimo-nexys_video/rtl/pulp_clock_gating_xilinx.sv similarity index 100% rename from fpga/pulpissimo-nexys_video/rtl/pulp_clock_gating_xilinx.sv rename to target/fpga/pulpissimo-nexys_video/rtl/pulp_clock_gating_xilinx.sv diff --git a/fpga/pulpissimo-nexys_video/rtl/xilinx_pulpissimo.v b/target/fpga/pulpissimo-nexys_video/rtl/xilinx_pulpissimo.v similarity index 58% rename from fpga/pulpissimo-nexys_video/rtl/xilinx_pulpissimo.v rename to target/fpga/pulpissimo-nexys_video/rtl/xilinx_pulpissimo.v index b33a91f0..7036cf7a 100644 --- a/fpga/pulpissimo-nexys_video/rtl/xilinx_pulpissimo.v +++ b/target/fpga/pulpissimo-nexys_video/rtl/xilinx_pulpissimo.v @@ -68,11 +68,11 @@ module xilinx_pulpissimo input wire pad_reset_n, - input wire pad_jtag_tck, - input wire pad_jtag_tdi, - output wire pad_jtag_tdo, - input wire pad_jtag_tms, - input wire pad_jtag_trst + inout wire pad_jtag_tck, + inout wire pad_jtag_tdi, + inout wire pad_jtag_tdo, + inout wire pad_jtag_tms, + inout wire pad_jtag_trst ); localparam CORE_TYPE = 0; // 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY) @@ -82,63 +82,73 @@ module xilinx_pulpissimo wire ref_clk; // Input clock buffer - IBUFG - #( - .IOSTANDARD("LVCMOS33"), - .IBUF_LOW_PWR("FALSE")) - i_sysclk_iobuf - ( - .I(sys_clk), - .O(ref_clk) - ); - - pulpissimo - #(.CORE_TYPE(CORE_TYPE), - .USE_FPU(USE_FPU), - .USE_HWPE(USE_HWPE) - ) i_pulpissimo - ( - .pad_spim_sdio0(oled_spim_mosi_o), - .pad_spim_sdio1(pad_spim_sdio1), - .pad_spim_sdio2(pad_spim_sdio2), - .pad_spim_sdio3(pad_spim_sdio3), - .pad_spim_csn0(pad_spim_csn0), - .pad_spim_csn1(led0_o), - .pad_spim_sck(oled_spim_sck_o), - .pad_uart_rx(pad_uart_rx), - .pad_uart_tx(pad_uart_tx), - .pad_cam_pclk(led1_o), - .pad_cam_hsync(led2_o), - .pad_cam_data0(led3_o), - .pad_cam_data1(switch0_i), - .pad_cam_data2(switch1_i), - .pad_cam_data3(btnc_i), - .pad_cam_data4(btnd_i), - .pad_cam_data5(btnl_i), - .pad_cam_data6(btnr_i), - .pad_cam_data7(btnu_i), - .pad_cam_vsync(sdio_reset_o), - .pad_sdio_clk(pad_sdio_clk), - .pad_sdio_cmd(pad_sdio_cmd), - .pad_sdio_data0(pad_sdio_data0), - .pad_sdio_data1(pad_sdio_data1), - .pad_sdio_data2(pad_sdio_data2), - .pad_sdio_data3(pad_sdio_data3), - .pad_i2c0_sda(pad_i2c0_sda), - .pad_i2c0_scl(pad_i2c0_scl), - .pad_i2s0_sck(oled_rst_o), - .pad_i2s0_ws(oled_dc_o), - .pad_i2s0_sdi(oled_vbat_o), - .pad_i2s1_sdi(oled_vdd_o), - .pad_reset_n(pad_reset_n), - .pad_jtag_tck(pad_jtag_tck), - .pad_jtag_tdi(pad_jtag_tdi), - .pad_jtag_tdo(pad_jtag_tdo), - .pad_jtag_tms(pad_jtag_tms), - .pad_jtag_trst(pad_jtag_trst), - .pad_xtal_in(ref_clk), - .pad_bootsel0(), - .pad_bootsel1() - ); + IBUFG #( + .IOSTANDARD("LVCMOS33"), + .IBUF_LOW_PWR("FALSE") + ) i_sysclk_iobuf ( + .I(sys_clk), + .O(ref_clk) + ); + + pulpissimo #( + .CORE_TYPE(CORE_TYPE), + .USE_FPU(USE_FPU), + .USE_HWPE(USE_HWPE) + ) i_pulpissimo ( + .pad_ref_clk ( ref_clk ), + .pad_reset_n ( pad_reset_n ), + .pad_clk_byp_en ( 1'b0 ), + + .pad_bootsel0 (), // Tied to 0 in run.tcl + .pad_bootsel1 (), // Tied to 0 in run.tcl + + .pad_jtag_tck (pad_jtag_tck), + .pad_jtag_tdi (pad_jtag_tdi), + .pad_jtag_tdo (pad_jtag_tdo), + .pad_jtag_tms (pad_jtag_tms), + .pad_jtag_trstn (pad_jtag_trst), + + .pad_hyper_csn ( ), // Tied to 0 in run.tcl + .pad_hyper_reset_n ( ), // Tied to 0 in run.tcl + .pad_hyper_ck ( ), // Tied to 0 in run.tcl + .pad_hyper_ckn ( ), // Tied to 0 in run.tcl + .pad_hyper_dq ( ), // Tied to 0 in run.tcl + .pad_hyper_rwds ( ), // Tied to 0 in run.tcl + + .pad_io ( { + pad_i2c0_scl, // io_31 + pad_i2c0_sda, // io_30 + pad_sdio_data3, // io_29 + pad_sdio_data2, // io_28 + pad_sdio_data1, // io_27 + pad_sdio_data0, // io_26 + pad_sdio_cmd, // io_25 + pad_sdio_clk, // io_24 + sdio_reset_o, // io_23 + oled_vdd_o, // io_22 + oled_vbat_o, // io_21 + oled_dc_o, // io_20 + oled_rst_o, // io_19 + btnu_i, // io_18 + btnr_i, // io_17 + btnl_i, // io_16 + btnd_i, // io_15 + btnc_i, // io_14 + switch1_i, // io_13 + switch0_i, // io_12 + led3_o, // io_11 + led2_o, // io_10 + led1_o, // io_09 + led0_o, // io_08 + pad_spim_sdio3, // io_07 + pad_spim_sdio2, // io_06 + pad_spim_sdio1, // io_05 + oled_spim_mosi_o, // io_04 + pad_spim_csn0, // io_03 + oled_spim_sck_o, // io_02 + pad_uart_rx, // io_01 + pad_uart_tx // io_00 + } ) + ); endmodule diff --git a/fpga/pulpissimo-nexys_video/tcl/.gitignore b/target/fpga/pulpissimo-nexys_video/tcl/.gitignore similarity index 100% rename from fpga/pulpissimo-nexys_video/tcl/.gitignore rename to target/fpga/pulpissimo-nexys_video/tcl/.gitignore diff --git a/fpga/pulpissimo-nexys_video/tcl/common.tcl b/target/fpga/pulpissimo-nexys_video/tcl/common.tcl similarity index 100% rename from fpga/pulpissimo-nexys_video/tcl/common.tcl rename to target/fpga/pulpissimo-nexys_video/tcl/common.tcl diff --git a/fpga/pulpissimo-nexys_video/tcl/download_bitstream.tcl b/target/fpga/pulpissimo-nexys_video/tcl/download_bitstream.tcl similarity index 100% rename from fpga/pulpissimo-nexys_video/tcl/download_bitstream.tcl rename to target/fpga/pulpissimo-nexys_video/tcl/download_bitstream.tcl diff --git a/fpga/pulpissimo-nexys_video/tcl/run.tcl b/target/fpga/pulpissimo-nexys_video/tcl/run.tcl similarity index 85% rename from fpga/pulpissimo-nexys_video/tcl/run.tcl rename to target/fpga/pulpissimo-nexys_video/tcl/run.tcl index e59df611..8e455694 100644 --- a/fpga/pulpissimo-nexys_video/tcl/run.tcl +++ b/target/fpga/pulpissimo-nexys_video/tcl/run.tcl @@ -73,10 +73,15 @@ open_run synth_1 -name netlist_1 set_property needs_refresh false [get_runs synth_1] # Remove unused IOBUF cells in padframe (they are not optimized away since the -# pad driver also drives the input creating a datapath from pad_xy_o to pad_xy_i -# ) -remove_cell i_pulpissimo/pad_frame_i/padinst_bootsel0 -remove_cell i_pulpissimo/pad_frame_i/padinst_bootsel1 +# pad driver also drives the input creating a datapath from pad_xy_o to pad_xy_i) +# Disconnect the nets and connect them to ground to avoid issues in optimization +remove_cell i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_bootsel* +disconnect_net -objects [get_nets i_pulpissimo/i_soc_domain/bootsel_i*] +connect_net -objects [get_nets i_pulpissimo/i_soc_domain/bootsel_i*] -net i_pulpissimo/ + +remove_cell i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_hyper* +disconnect_net -objects [get_nets i_pulpissimo/i_soc_domain/pad_to_hyper_i*] +connect_net -objects [get_nets i_pulpissimo/i_soc_domain/pad_to_hyper_i*] -net i_pulpissimo/ # Launch Implementation diff --git a/fpga/pulpissimo-vcu108/.gitignore b/target/fpga/pulpissimo-vcu108/.gitignore similarity index 100% rename from fpga/pulpissimo-vcu108/.gitignore rename to target/fpga/pulpissimo-vcu108/.gitignore diff --git a/fpga/pulpissimo-vcu108/Makefile b/target/fpga/pulpissimo-vcu108/Makefile similarity index 100% rename from fpga/pulpissimo-vcu108/Makefile rename to target/fpga/pulpissimo-vcu108/Makefile diff --git a/fpga/pulpissimo-vcu108/constraints/vcu108.xdc b/target/fpga/pulpissimo-vcu108/constraints/vcu108.xdc similarity index 68% rename from fpga/pulpissimo-vcu108/constraints/vcu108.xdc rename to target/fpga/pulpissimo-vcu108/constraints/vcu108.xdc index 935a96d2..54e26e68 100644 --- a/fpga/pulpissimo-vcu108/constraints/vcu108.xdc +++ b/target/fpga/pulpissimo-vcu108/constraints/vcu108.xdc @@ -13,16 +13,10 @@ #Create constraint for the clock input of the vcu108 board create_clock -period 8.000 -name ref_clk [get_ports ref_clk_p] -#I2S and CAM interface are not used in this FPGA port. Set constraints to -#disable the clock -set_case_analysis 0 i_pulpissimo/safe_domain_i/cam_pclk_o -set_case_analysis 0 i_pulpissimo/safe_domain_i/i2s_slave_sck_o -#set_input_jitter tck 1.000 - ## JTAG create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports pad_jtag_tck] set_input_jitter tck 1.000 -set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pad_jtag_tck_IBUF_inst/O] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_jtag_tck/O] # minimize routing delay @@ -34,35 +28,50 @@ set_max_delay -to [get_ports pad_jtag_tdo] 20.000 set_max_delay -from [get_ports pad_jtag_tms] 20.000 set_max_delay -from [get_ports pad_jtag_tdi] 20.000 -set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000 -set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000 -set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000 # reset signal set_false_path -from [get_ports pad_reset] set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pad_reset_IBUF_inst/O] +set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_pulpissimo/i_clock_gen/i_slow_clk_div/i_clk_mux/clk_o] +set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_pulpissimo/i_clock_gen/i_slow_clk_mngr/inst/clk_out1] + # Set ASYNC_REG attribute for ff synchronizers to place them closer together and # increase MTBF -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim0/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim1/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim2/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim3/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_timer_unit/s_ref_clk*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_ref_clk_sync/i_pulp_sync/r_reg_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/u_evnt_gen/r_ls_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim0/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim1/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim2/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim3/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_timer_unit/s_ref_clk*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_ref_clk_sync/i_pulp_sync/r_reg_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/u_evnt_gen/r_ls_sync_reg*] # Create asynchronous clock group between slow-clk and SoC clock. Those clocks # are considered asynchronously and proper synchronization regs are in place -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/safe_domain_i/i_slow_clk_gen/slow_clk_o]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/i_fpga_clk_gen/soc_clk_o]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/slow_clk_o]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] # Create asynchronous clock group between Per Clock and SoC clock. Those clocks # are considered asynchronously and proper synchronization regs are in place -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/clk_per_o]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/clk_soc_o]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out2]] # Create asynchronous clock group between JTAG TCK and SoC clock. -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/clk_soc_o]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] + +# Create asynchronous clock group between JTAG TCK and per clock. +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out2]] + +# Create asynchronous clock group between slow clock and JTAG TCK. +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/slow_clk_o]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] + ############################################################# # _____ ____ _____ _ _ _ # diff --git a/fpga/pulpissimo-vcu108/elf_run.gdb b/target/fpga/pulpissimo-vcu108/elf_run.gdb similarity index 100% rename from fpga/pulpissimo-vcu108/elf_run.gdb rename to target/fpga/pulpissimo-vcu108/elf_run.gdb diff --git a/fpga/pulpissimo-vcu108/fpga-settings.mk b/target/fpga/pulpissimo-vcu108/fpga-settings.mk similarity index 100% rename from fpga/pulpissimo-vcu108/fpga-settings.mk rename to target/fpga/pulpissimo-vcu108/fpga-settings.mk diff --git a/fpga/pulpissimo-vcu108/ips/xilinx_clk_mngr/.gitignore b/target/fpga/pulpissimo-vcu108/ips/xilinx_clk_mngr/.gitignore similarity index 100% rename from fpga/pulpissimo-vcu108/ips/xilinx_clk_mngr/.gitignore rename to target/fpga/pulpissimo-vcu108/ips/xilinx_clk_mngr/.gitignore diff --git a/fpga/pulpissimo-vcu108/ips/xilinx_clk_mngr/Makefile b/target/fpga/pulpissimo-vcu108/ips/xilinx_clk_mngr/Makefile similarity index 100% rename from fpga/pulpissimo-vcu108/ips/xilinx_clk_mngr/Makefile rename to target/fpga/pulpissimo-vcu108/ips/xilinx_clk_mngr/Makefile diff --git a/fpga/pulpissimo-vcu108/ips/xilinx_clk_mngr/tcl/run.tcl b/target/fpga/pulpissimo-vcu108/ips/xilinx_clk_mngr/tcl/run.tcl similarity index 100% rename from fpga/pulpissimo-vcu108/ips/xilinx_clk_mngr/tcl/run.tcl rename to target/fpga/pulpissimo-vcu108/ips/xilinx_clk_mngr/tcl/run.tcl diff --git a/fpga/pulpissimo-vcu108/ips/xilinx_slow_clk_mngr/.gitignore b/target/fpga/pulpissimo-vcu108/ips/xilinx_slow_clk_mngr/.gitignore similarity index 100% rename from fpga/pulpissimo-vcu108/ips/xilinx_slow_clk_mngr/.gitignore rename to target/fpga/pulpissimo-vcu108/ips/xilinx_slow_clk_mngr/.gitignore diff --git a/fpga/pulpissimo-vcu108/ips/xilinx_slow_clk_mngr/Makefile b/target/fpga/pulpissimo-vcu108/ips/xilinx_slow_clk_mngr/Makefile similarity index 100% rename from fpga/pulpissimo-vcu108/ips/xilinx_slow_clk_mngr/Makefile rename to target/fpga/pulpissimo-vcu108/ips/xilinx_slow_clk_mngr/Makefile diff --git a/fpga/pulpissimo-vcu108/ips/xilinx_slow_clk_mngr/tcl/run.tcl b/target/fpga/pulpissimo-vcu108/ips/xilinx_slow_clk_mngr/tcl/run.tcl similarity index 100% rename from fpga/pulpissimo-vcu108/ips/xilinx_slow_clk_mngr/tcl/run.tcl rename to target/fpga/pulpissimo-vcu108/ips/xilinx_slow_clk_mngr/tcl/run.tcl diff --git a/fpga/pulpissimo-vcu108/openocd-vcu108-olimex-arm-usb-tiny-h.cfg b/target/fpga/pulpissimo-vcu108/openocd-vcu108-olimex-arm-usb-tiny-h.cfg similarity index 100% rename from fpga/pulpissimo-vcu108/openocd-vcu108-olimex-arm-usb-tiny-h.cfg rename to target/fpga/pulpissimo-vcu108/openocd-vcu108-olimex-arm-usb-tiny-h.cfg diff --git a/fpga/pulpissimo-vcu108/rtl/cv32e40p_clock_gate_xilinx.sv b/target/fpga/pulpissimo-vcu108/rtl/cv32e40p_clock_gate_xilinx.sv similarity index 100% rename from fpga/pulpissimo-vcu108/rtl/cv32e40p_clock_gate_xilinx.sv rename to target/fpga/pulpissimo-vcu108/rtl/cv32e40p_clock_gate_xilinx.sv diff --git a/fpga/pulpissimo-vcu108/rtl/fpga_bootrom.sv b/target/fpga/pulpissimo-vcu108/rtl/fpga_bootrom.sv similarity index 100% rename from fpga/pulpissimo-vcu108/rtl/fpga_bootrom.sv rename to target/fpga/pulpissimo-vcu108/rtl/fpga_bootrom.sv diff --git a/fpga/pulpissimo-vcu108/rtl/fpga_clk_gen.sv b/target/fpga/pulpissimo-vcu108/rtl/fpga_clk_gen.sv similarity index 100% rename from fpga/pulpissimo-vcu108/rtl/fpga_clk_gen.sv rename to target/fpga/pulpissimo-vcu108/rtl/fpga_clk_gen.sv diff --git a/fpga/pulpissimo-vcu108/rtl/fpga_slow_clk_gen.sv b/target/fpga/pulpissimo-vcu108/rtl/fpga_slow_clk_gen.sv similarity index 100% rename from fpga/pulpissimo-vcu108/rtl/fpga_slow_clk_gen.sv rename to target/fpga/pulpissimo-vcu108/rtl/fpga_slow_clk_gen.sv diff --git a/fpga/pulpissimo-vcu108/rtl/pad_functional_xilinx.sv b/target/fpga/pulpissimo-vcu108/rtl/pad_functional_xilinx.sv similarity index 100% rename from fpga/pulpissimo-vcu108/rtl/pad_functional_xilinx.sv rename to target/fpga/pulpissimo-vcu108/rtl/pad_functional_xilinx.sv diff --git a/fpga/pulpissimo-vcu108/rtl/pulp_clock_gating_xilinx.sv b/target/fpga/pulpissimo-vcu108/rtl/pulp_clock_gating_xilinx.sv similarity index 100% rename from fpga/pulpissimo-vcu108/rtl/pulp_clock_gating_xilinx.sv rename to target/fpga/pulpissimo-vcu108/rtl/pulp_clock_gating_xilinx.sv diff --git a/fpga/pulpissimo-zcu104/rtl/xilinx_pulpissimo.v b/target/fpga/pulpissimo-vcu108/rtl/xilinx_pulpissimo.v similarity index 59% rename from fpga/pulpissimo-zcu104/rtl/xilinx_pulpissimo.v rename to target/fpga/pulpissimo-vcu108/rtl/xilinx_pulpissimo.v index 729b6a37..d9f04366 100644 --- a/fpga/pulpissimo-zcu104/rtl/xilinx_pulpissimo.v +++ b/target/fpga/pulpissimo-vcu108/rtl/xilinx_pulpissimo.v @@ -66,10 +66,10 @@ module xilinx_pulpissimo input wire pad_reset, - input wire pad_jtag_tck, - input wire pad_jtag_tdi, - output wire pad_jtag_tdo, - input wire pad_jtag_tms + inout wire pad_jtag_tck, + inout wire pad_jtag_tdi, + inout wire pad_jtag_tdo, + inout wire pad_jtag_tms ); localparam CORE_TYPE = 0; // 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY) @@ -80,65 +80,75 @@ module xilinx_pulpissimo //Differential to single ended clock conversion - IBUFGDS - #( - .IOSTANDARD("LVDS"), - .DIFF_TERM("FALSE"), - .IBUF_LOW_PWR("FALSE")) - i_sysclk_iobuf - ( - .I(ref_clk_p), - .IB(ref_clk_n), - .O(ref_clk) - ); - - pulpissimo - #(.CORE_TYPE(CORE_TYPE), - .USE_FPU(USE_FPU), - .USE_HWPE(USE_HWPE) - ) i_pulpissimo - ( - .pad_spim_sdio0(pad_pmod0_4), - .pad_spim_sdio1(pad_pmod0_5), - .pad_spim_sdio2(pad_pmod0_6), - .pad_spim_sdio3(pad_pmod0_7), - .pad_spim_csn0(pad_uart_rts), - .pad_spim_csn1(led0_o), - .pad_spim_sck(pad_uart_cts), - .pad_uart_rx(pad_uart_rx), - .pad_uart_tx(pad_uart_tx), - .pad_cam_pclk(led1_o), - .pad_cam_hsync(led2_o), - .pad_cam_data0(led3_o), - .pad_cam_data1(switch0_i), - .pad_cam_data2(switch1_i), - .pad_cam_data3(btn0_i), - .pad_cam_data4(btn1_i), - .pad_cam_data5(btn2_i), - .pad_cam_data6(btn3_i), - .pad_cam_data7(switch2_i), - .pad_cam_vsync(switch3_i), - .pad_sdio_clk(pad_hdmi_scl), - .pad_sdio_cmd(pad_hdmi_sda), - .pad_sdio_data0(pad_pmod1_0), - .pad_sdio_data1(pad_pmod1_1), - .pad_sdio_data2(pad_pmod1_2), - .pad_sdio_data3(pad_pmod1_3), - .pad_i2c0_sda(pad_i2c0_sda), - .pad_i2c0_scl(pad_i2c0_scl), - .pad_i2s0_sck(pad_pmod1_4), - .pad_i2s0_ws(pad_pmod1_5), - .pad_i2s0_sdi(pad_pmod1_6), - .pad_i2s1_sdi(pad_pmod1_7), - .pad_reset_n(~pad_reset), - .pad_jtag_tck(pad_jtag_tck), - .pad_jtag_tdi(pad_jtag_tdi), - .pad_jtag_tdo(pad_jtag_tdo), - .pad_jtag_tms(pad_jtag_tms), - .pad_jtag_trst(1'b1), - .pad_xtal_in(ref_clk), - .pad_bootsel0(), - .pad_bootsel1() - ); + IBUFGDS #( + .IOSTANDARD("LVDS"), + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") + ) i_sysclk_iobuf ( + .I(ref_clk_p), + .IB(ref_clk_n), + .O(ref_clk) + ); + + pulpissimo #( + .CORE_TYPE(CORE_TYPE), + .USE_FPU(USE_FPU), + .USE_HWPE(USE_HWPE) + ) i_pulpissimo ( + .pad_ref_clk ( ref_clk ), + .pad_reset_n ( ~pad_reset ), + .pad_clk_byp_en ( 1'b0 ), + + .pad_bootsel0 ( ), // Tied to 0 in run.tcl + .pad_bootsel1 ( ), // Tied to 0 in run.tcl + + .pad_jtag_tck ( pad_jtag_tck ), + .pad_jtag_tdi ( pad_jtag_tdi ), + .pad_jtag_tdo ( pad_jtag_tdo ), + .pad_jtag_tms ( pad_jtag_tms ), + .pad_jtag_trstn ( ), // Tied to 1 in run.tcl + + .pad_hyper_csn ( ), // Tied to 0 in run.tcl + .pad_hyper_reset_n ( ), // Tied to 0 in run.tcl + .pad_hyper_ck ( ), // Tied to 0 in run.tcl + .pad_hyper_ckn ( ), // Tied to 0 in run.tcl + .pad_hyper_dq ( ), // Tied to 0 in run.tcl + .pad_hyper_rwds ( ), // Tied to 0 in run.tcl + + .pad_io ( { + pad_i2c0_scl, // io_31 + pad_i2c0_sda, // io_30 + pad_pmod1_3, // io_29 + pad_pmod1_2, // io_28 + pad_pmod1_1, // io_27 + pad_pmod1_0, // io_26 + pad_hdmi_sda, // io_25 + pad_hdmi_scl, // io_24 + switch3_i, // io_23 + pad_pmod1_7, // io_22 + pad_pmod1_6, // io_21 + pad_pmod1_5, // io_20 + pad_pmod1_4, // io_19 + switch2_i, // io_18 + btn3_i, // io_17 + btn2_i, // io_16 + btn1_i, // io_15 + btn0_i, // io_14 + switch1_i, // io_13 + switch0_i, // io_12 + led3_o, // io_11 + led2_o, // io_10 + led1_o, // io_09 + led0_o, // io_08 + pad_pmod0_7, // io_07 + pad_pmod0_6, // io_06 + pad_pmod0_5, // io_05 + pad_pmod0_4, // io_04 + pad_uart_rts, // io_03 + pad_uart_cts, // io_02 + pad_uart_rx, // io_01 + pad_uart_tx // io_00 + } ) + ); endmodule diff --git a/fpga/pulpissimo-vcu108/tcl/common.tcl b/target/fpga/pulpissimo-vcu108/tcl/common.tcl similarity index 100% rename from fpga/pulpissimo-vcu108/tcl/common.tcl rename to target/fpga/pulpissimo-vcu108/tcl/common.tcl diff --git a/fpga/pulpissimo-vcu108/tcl/download_bitstream.tcl b/target/fpga/pulpissimo-vcu108/tcl/download_bitstream.tcl similarity index 100% rename from fpga/pulpissimo-vcu108/tcl/download_bitstream.tcl rename to target/fpga/pulpissimo-vcu108/tcl/download_bitstream.tcl diff --git a/fpga/pulpissimo-vcu108/tcl/run.tcl b/target/fpga/pulpissimo-vcu108/tcl/run.tcl similarity index 82% rename from fpga/pulpissimo-vcu108/tcl/run.tcl rename to target/fpga/pulpissimo-vcu108/tcl/run.tcl index 87eba7f2..4243657a 100644 --- a/fpga/pulpissimo-vcu108/tcl/run.tcl +++ b/target/fpga/pulpissimo-vcu108/tcl/run.tcl @@ -73,10 +73,19 @@ open_run synth_1 -name netlist_1 set_property needs_refresh false [get_runs synth_1] # Remove unused IOBUF cells in padframe (they are not optimized away since the -# pad driver also drives the input creating a datapath from pad_xy_o to pad_xy_i -# ) -remove_cell i_pulpissimo/pad_frame_i/padinst_bootsel0 -remove_cell i_pulpissimo/pad_frame_i/padinst_bootsel1 +# pad driver also drives the input creating a datapath from pad_xy_o to pad_xy_i) +# Disconnect the nets and connect them to ground to avoid issues in optimization +remove_cell i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_bootsel* +disconnect_net -objects [get_nets i_pulpissimo/i_soc_domain/bootsel_i*] +connect_net -objects [get_nets i_pulpissimo/i_soc_domain/bootsel_i*] -net i_pulpissimo/ + +remove_cell i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_hyper* +disconnect_net -objects [get_nets i_pulpissimo/i_soc_domain/pad_to_hyper_i*] +connect_net -objects [get_nets i_pulpissimo/i_soc_domain/pad_to_hyper_i*] -net i_pulpissimo/ + +remove_cell i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_jtag_trst* +disconnect_net -objects [get_nets i_pulpissimo/i_soc_domain/jtag_trst_ni] +connect_net -objects [get_nets i_pulpissimo/i_soc_domain/jtag_trst_ni] -net i_pulpissimo/ # Launch Implementation diff --git a/fpga/pulpissimo-zcu102/.gitignore b/target/fpga/pulpissimo-zcu102/.gitignore similarity index 100% rename from fpga/pulpissimo-zcu102/.gitignore rename to target/fpga/pulpissimo-zcu102/.gitignore diff --git a/fpga/pulpissimo-zcu102/Makefile b/target/fpga/pulpissimo-zcu102/Makefile similarity index 100% rename from fpga/pulpissimo-zcu102/Makefile rename to target/fpga/pulpissimo-zcu102/Makefile diff --git a/fpga/pulpissimo-zcu102/README.md b/target/fpga/pulpissimo-zcu102/README.md similarity index 100% rename from fpga/pulpissimo-zcu102/README.md rename to target/fpga/pulpissimo-zcu102/README.md diff --git a/fpga/pulpissimo-zcu102/constraints/zcu102.xdc b/target/fpga/pulpissimo-zcu102/constraints/zcu102.xdc similarity index 67% rename from fpga/pulpissimo-zcu102/constraints/zcu102.xdc rename to target/fpga/pulpissimo-zcu102/constraints/zcu102.xdc index 9065c3ce..3e5656d9 100644 --- a/fpga/pulpissimo-zcu102/constraints/zcu102.xdc +++ b/target/fpga/pulpissimo-zcu102/constraints/zcu102.xdc @@ -14,16 +14,10 @@ create_clock -period 8.000 -name ref_clk [get_ports ref_clk_p] set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets ref_clk] -#I2S and CAM interface are not used in this FPGA port. Set constraints to -#disable the clock -set_case_analysis 0 i_pulpissimo/safe_domain_i/cam_pclk_o -set_case_analysis 0 i_pulpissimo/safe_domain_i/i2s_slave_sck_o -#set_input_jitter tck 1.000 - ## JTAG create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports pad_jtag_tck] set_input_jitter tck 1.000 -set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pad_jtag_tck_IBUF_inst/O] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_jtag_tck/O] # minimize routing delay @@ -35,35 +29,49 @@ set_max_delay -to [get_ports pad_jtag_tdo] 20.000 set_max_delay -from [get_ports pad_jtag_tms] 20.000 set_max_delay -from [get_ports pad_jtag_tdi] 20.000 -set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000 -set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000 -set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000 # reset signal set_false_path -from [get_ports pad_reset] set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pad_reset_IBUF_inst/O] +set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_pulpissimo/i_clock_gen/i_slow_clk_div/i_clk_mux/clk_o] +set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_pulpissimo/i_clock_gen/i_slow_clk_mngr/inst/clk_out1] + # Set ASYNC_REG attribute for ff synchronizers to place them closer together and # increase MTBF -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim0/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim1/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim2/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim3/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_timer_unit/s_ref_clk*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_ref_clk_sync/i_pulp_sync/r_reg_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/u_evnt_gen/r_ls_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim0/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim1/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim2/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim3/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_timer_unit/s_ref_clk*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_ref_clk_sync/i_pulp_sync/r_reg_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/u_evnt_gen/r_ls_sync_reg*] # Create asynchronous clock group between slow-clk and SoC clock. Those clocks # are considered asynchronously and proper synchronization regs are in place -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/safe_domain_i/i_slow_clk_gen/slow_clk_o]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/i_fpga_clk_gen/soc_clk_o]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/slow_clk_o]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] # Create asynchronous clock group between Per Clock and SoC clock. Those clocks # are considered asynchronously and proper synchronization regs are in place -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/clk_per_o]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/clk_soc_o]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out2]] # Create asynchronous clock group between JTAG TCK and SoC clock. -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/clk_soc_o]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] + +# Create asynchronous clock group between JTAG TCK and per clock. +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out2]] + +# Create asynchronous clock group between slow clock and JTAG TCK. +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/slow_clk_o]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] ############################################################# # _____ ____ _____ _ _ _ # diff --git a/fpga/pulpissimo-zcu102/elf_run.gdb b/target/fpga/pulpissimo-zcu102/elf_run.gdb similarity index 100% rename from fpga/pulpissimo-zcu102/elf_run.gdb rename to target/fpga/pulpissimo-zcu102/elf_run.gdb diff --git a/fpga/pulpissimo-zcu102/elf_run.sh b/target/fpga/pulpissimo-zcu102/elf_run.sh similarity index 100% rename from fpga/pulpissimo-zcu102/elf_run.sh rename to target/fpga/pulpissimo-zcu102/elf_run.sh diff --git a/fpga/pulpissimo-zcu102/errors b/target/fpga/pulpissimo-zcu102/errors similarity index 100% rename from fpga/pulpissimo-zcu102/errors rename to target/fpga/pulpissimo-zcu102/errors diff --git a/fpga/pulpissimo-zcu102/fpga-settings.mk b/target/fpga/pulpissimo-zcu102/fpga-settings.mk similarity index 88% rename from fpga/pulpissimo-zcu102/fpga-settings.mk rename to target/fpga/pulpissimo-zcu102/fpga-settings.mk index edb8aaf7..43f4aa18 100644 --- a/fpga/pulpissimo-zcu102/fpga-settings.mk +++ b/target/fpga/pulpissimo-zcu102/fpga-settings.mk @@ -1,7 +1,7 @@ export BOARD=zcu102 export XILINX_PART=xczu9eg-ffvb1156-2-e export XILINX_BOARD=xilinx.com:zcu102:part0:3.2 -export FC_CLK_PERIOD_NS=50 +export FC_CLK_PERIOD_NS=62.5 export PER_CLK_PERIOD_NS=100 export SLOW_CLK_PERIOD_NS=30517 $(info Setting environment variables for $(BOARD) board) diff --git a/fpga/pulpissimo-zcu102/ips/xilinx_clk_mngr/.gitignore b/target/fpga/pulpissimo-zcu102/ips/xilinx_clk_mngr/.gitignore similarity index 100% rename from fpga/pulpissimo-zcu102/ips/xilinx_clk_mngr/.gitignore rename to target/fpga/pulpissimo-zcu102/ips/xilinx_clk_mngr/.gitignore diff --git a/fpga/pulpissimo-zcu102/ips/xilinx_clk_mngr/Makefile b/target/fpga/pulpissimo-zcu102/ips/xilinx_clk_mngr/Makefile similarity index 100% rename from fpga/pulpissimo-zcu102/ips/xilinx_clk_mngr/Makefile rename to target/fpga/pulpissimo-zcu102/ips/xilinx_clk_mngr/Makefile diff --git a/fpga/pulpissimo-zcu102/ips/xilinx_clk_mngr/tcl/run.tcl b/target/fpga/pulpissimo-zcu102/ips/xilinx_clk_mngr/tcl/run.tcl similarity index 100% rename from fpga/pulpissimo-zcu102/ips/xilinx_clk_mngr/tcl/run.tcl rename to target/fpga/pulpissimo-zcu102/ips/xilinx_clk_mngr/tcl/run.tcl diff --git a/fpga/pulpissimo-zcu102/ips/xilinx_slow_clk_mngr/.gitignore b/target/fpga/pulpissimo-zcu102/ips/xilinx_slow_clk_mngr/.gitignore similarity index 100% rename from fpga/pulpissimo-zcu102/ips/xilinx_slow_clk_mngr/.gitignore rename to target/fpga/pulpissimo-zcu102/ips/xilinx_slow_clk_mngr/.gitignore diff --git a/fpga/pulpissimo-zcu102/ips/xilinx_slow_clk_mngr/Makefile b/target/fpga/pulpissimo-zcu102/ips/xilinx_slow_clk_mngr/Makefile similarity index 100% rename from fpga/pulpissimo-zcu102/ips/xilinx_slow_clk_mngr/Makefile rename to target/fpga/pulpissimo-zcu102/ips/xilinx_slow_clk_mngr/Makefile diff --git a/fpga/pulpissimo-zcu102/ips/xilinx_slow_clk_mngr/tcl/run.tcl b/target/fpga/pulpissimo-zcu102/ips/xilinx_slow_clk_mngr/tcl/run.tcl similarity index 100% rename from fpga/pulpissimo-zcu102/ips/xilinx_slow_clk_mngr/tcl/run.tcl rename to target/fpga/pulpissimo-zcu102/ips/xilinx_slow_clk_mngr/tcl/run.tcl diff --git a/fpga/pulpissimo-zcu102/openocd-zcu102-digilent-jtag-hs2.cfg b/target/fpga/pulpissimo-zcu102/openocd-zcu102-digilent-jtag-hs2.cfg similarity index 100% rename from fpga/pulpissimo-zcu102/openocd-zcu102-digilent-jtag-hs2.cfg rename to target/fpga/pulpissimo-zcu102/openocd-zcu102-digilent-jtag-hs2.cfg diff --git a/fpga/pulpissimo-zcu102/openocd-zcu102-olimex-arm-usb-ocd-h.cfg b/target/fpga/pulpissimo-zcu102/openocd-zcu102-olimex-arm-usb-ocd-h.cfg similarity index 100% rename from fpga/pulpissimo-zcu102/openocd-zcu102-olimex-arm-usb-ocd-h.cfg rename to target/fpga/pulpissimo-zcu102/openocd-zcu102-olimex-arm-usb-ocd-h.cfg diff --git a/fpga/pulpissimo-zcu102/rtl/cv32e40p_clock_gate_xilinx.sv b/target/fpga/pulpissimo-zcu102/rtl/cv32e40p_clock_gate_xilinx.sv similarity index 100% rename from fpga/pulpissimo-zcu102/rtl/cv32e40p_clock_gate_xilinx.sv rename to target/fpga/pulpissimo-zcu102/rtl/cv32e40p_clock_gate_xilinx.sv diff --git a/fpga/pulpissimo-zcu102/rtl/fpga_bootrom.sv b/target/fpga/pulpissimo-zcu102/rtl/fpga_bootrom.sv similarity index 100% rename from fpga/pulpissimo-zcu102/rtl/fpga_bootrom.sv rename to target/fpga/pulpissimo-zcu102/rtl/fpga_bootrom.sv diff --git a/fpga/pulpissimo-zcu102/rtl/fpga_clk_gen.sv b/target/fpga/pulpissimo-zcu102/rtl/fpga_clk_gen.sv similarity index 100% rename from fpga/pulpissimo-zcu102/rtl/fpga_clk_gen.sv rename to target/fpga/pulpissimo-zcu102/rtl/fpga_clk_gen.sv diff --git a/fpga/pulpissimo-zcu102/rtl/fpga_slow_clk_gen.sv b/target/fpga/pulpissimo-zcu102/rtl/fpga_slow_clk_gen.sv similarity index 100% rename from fpga/pulpissimo-zcu102/rtl/fpga_slow_clk_gen.sv rename to target/fpga/pulpissimo-zcu102/rtl/fpga_slow_clk_gen.sv diff --git a/fpga/pulpissimo-zcu102/rtl/pad_functional_xilinx.sv b/target/fpga/pulpissimo-zcu102/rtl/pad_functional_xilinx.sv similarity index 100% rename from fpga/pulpissimo-zcu102/rtl/pad_functional_xilinx.sv rename to target/fpga/pulpissimo-zcu102/rtl/pad_functional_xilinx.sv diff --git a/fpga/pulpissimo-zcu102/rtl/pulp_clock_gating_xilinx.sv b/target/fpga/pulpissimo-zcu102/rtl/pulp_clock_gating_xilinx.sv similarity index 100% rename from fpga/pulpissimo-zcu102/rtl/pulp_clock_gating_xilinx.sv rename to target/fpga/pulpissimo-zcu102/rtl/pulp_clock_gating_xilinx.sv diff --git a/fpga/pulpissimo-zcu102/rtl/xilinx_pulpissimo.v b/target/fpga/pulpissimo-zcu102/rtl/xilinx_pulpissimo.v similarity index 58% rename from fpga/pulpissimo-zcu102/rtl/xilinx_pulpissimo.v rename to target/fpga/pulpissimo-zcu102/rtl/xilinx_pulpissimo.v index 135639f8..5f2186d5 100644 --- a/fpga/pulpissimo-zcu102/rtl/xilinx_pulpissimo.v +++ b/target/fpga/pulpissimo-zcu102/rtl/xilinx_pulpissimo.v @@ -66,10 +66,10 @@ module xilinx_pulpissimo input wire pad_reset, - input wire pad_jtag_tck, - input wire pad_jtag_tdi, - output wire pad_jtag_tdo, - input wire pad_jtag_tms + inout wire pad_jtag_tck, + inout wire pad_jtag_tdi, + inout wire pad_jtag_tdo, + inout wire pad_jtag_tms ); localparam CORE_TYPE = 0; // 0 for RISCY, 1 for ZERORISCY, 2 for MICRORISCY @@ -77,68 +77,81 @@ module xilinx_pulpissimo localparam USE_HWPE = 0; wire ref_clk; + wire rst_n; + + assign rst_n = ~pad_reset; //Differential to single ended clock conversion - IBUFGDS - #( - .IOSTANDARD("LVDS"), - .DIFF_TERM("FALSE"), - .IBUF_LOW_PWR("FALSE")) - i_sysclk_iobuf - ( - .I(ref_clk_p), - .IB(ref_clk_n), - .O(ref_clk) - ); - - pulpissimo - #(.CORE_TYPE(CORE_TYPE), - .USE_FPU(USE_FPU), - .USE_HWPE(USE_HWPE) - ) i_pulpissimo - ( - .pad_spim_sdio0(pad_pmod0_4), - .pad_spim_sdio1(pad_pmod0_5), - .pad_spim_sdio2(pad_pmod0_6), - .pad_spim_sdio3(pad_pmod0_7), - .pad_spim_csn0(pad_uart_rts), - .pad_spim_csn1(led0_o), - .pad_spim_sck(pad_uart_cts), - .pad_uart_rx(pad_uart_rx), - .pad_uart_tx(pad_uart_tx), - .pad_cam_pclk(led1_o), - .pad_cam_hsync(led2_o), - .pad_cam_data0(led3_o), - .pad_cam_data1(switch0_i), - .pad_cam_data2(switch1_i), - .pad_cam_data3(btn0_i), - .pad_cam_data4(btn1_i), - .pad_cam_data5(btn2_i), - .pad_cam_data6(btn3_i), - .pad_cam_data7(switch2_i), - .pad_cam_vsync(switch3_i), - .pad_sdio_clk(pad_hdmi_scl), - .pad_sdio_cmd(pad_hdmi_sda), - .pad_sdio_data0(pad_pmod1_0), - .pad_sdio_data1(pad_pmod1_1), - .pad_sdio_data2(pad_pmod1_2), - .pad_sdio_data3(pad_pmod1_3), - .pad_i2c0_sda(pad_i2c0_sda), - .pad_i2c0_scl(pad_i2c0_scl), - .pad_i2s0_sck(pad_pmod1_4), - .pad_i2s0_ws(pad_pmod1_5), - .pad_i2s0_sdi(pad_pmod1_6), - .pad_i2s1_sdi(pad_pmod1_7), - .pad_reset_n(~pad_reset), - .pad_jtag_tck(pad_jtag_tck), - .pad_jtag_tdi(pad_jtag_tdi), - .pad_jtag_tdo(pad_jtag_tdo), - .pad_jtag_tms(pad_jtag_tms), - .pad_jtag_trst(1'b1), - .pad_xtal_in(ref_clk), - .pad_bootsel0(), - .pad_bootsel1() - ); + IBUFGDS #( + .IOSTANDARD("LVDS"), + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") + ) i_sysclk_iobuf ( + .I(ref_clk_p), + .IB(ref_clk_n), + .O(ref_clk) + ); + + pulpissimo #( + .CORE_TYPE(CORE_TYPE), + .USE_FPU(USE_FPU), + .USE_HWPE(USE_HWPE) + ) i_pulpissimo ( + .pad_ref_clk ( ref_clk ), + .pad_reset_n ( rst_n ), + .pad_clk_byp_en ( 1'b0 ), + + .pad_bootsel0 ( ), // Tied to 0 in run.tcl + .pad_bootsel1 ( ), // Tied to 0 in run.tcl + + .pad_jtag_tck ( pad_jtag_tck ), + .pad_jtag_tdi ( pad_jtag_tdi ), + .pad_jtag_tdo ( pad_jtag_tdo ), + .pad_jtag_tms ( pad_jtag_tms ), + .pad_jtag_trstn ( ), // Tied to 1 in run.tcl + + .pad_hyper_csn ( ), // Tied to 0 in run.tcl + .pad_hyper_reset_n ( ), // Tied to 0 in run.tcl + .pad_hyper_ck ( ), // Tied to 0 in run.tcl + .pad_hyper_ckn ( ), // Tied to 0 in run.tcl + .pad_hyper_dq ( ), // Tied to 0 in run.tcl + .pad_hyper_rwds ( ), // Tied to 0 in run.tcl + + .pad_io ( { + pad_i2c0_scl, // io_31 + pad_i2c0_sda, // io_30 + pad_pmod1_3, // io_29 + pad_pmod1_2, // io_28 + pad_pmod1_1, // io_27 + pad_pmod1_0, // io_26 + pad_hdmi_sda, // io_25 + pad_hdmi_scl, // io_24 + switch3_i, // io_23 + pad_pmod1_7, // io_22 + pad_pmod1_6, // io_21 + pad_pmod1_5, // io_20 + pad_pmod1_4, // io_19 + switch2_i, // io_18 + btn3_i, // io_17 + btn2_i, // io_16 + btn1_i, // io_15 + btn0_i, // io_14 + switch1_i, // io_13 + switch0_i, // io_12 + led3_o, // io_11 + led2_o, // io_10 + led1_o, // io_09 + led0_o, // io_08 + pad_pmod0_7, // io_07 + pad_pmod0_6, // io_06 + pad_pmod0_5, // io_05 + pad_pmod0_4, // io_04 + pad_uart_rts, // io_03 + pad_uart_cts, // io_02 + pad_uart_rx, // io_01 + pad_uart_tx // io_00 + } ) + ); endmodule diff --git a/fpga/pulpissimo-zcu102/tcl/.gitignore b/target/fpga/pulpissimo-zcu102/tcl/.gitignore similarity index 100% rename from fpga/pulpissimo-zcu102/tcl/.gitignore rename to target/fpga/pulpissimo-zcu102/tcl/.gitignore diff --git a/fpga/pulpissimo-zcu102/tcl/common.tcl b/target/fpga/pulpissimo-zcu102/tcl/common.tcl similarity index 100% rename from fpga/pulpissimo-zcu102/tcl/common.tcl rename to target/fpga/pulpissimo-zcu102/tcl/common.tcl diff --git a/fpga/pulpissimo-zcu102/tcl/download_bitstream.tcl b/target/fpga/pulpissimo-zcu102/tcl/download_bitstream.tcl similarity index 100% rename from fpga/pulpissimo-zcu102/tcl/download_bitstream.tcl rename to target/fpga/pulpissimo-zcu102/tcl/download_bitstream.tcl diff --git a/fpga/pulpissimo-zcu102/tcl/run.tcl b/target/fpga/pulpissimo-zcu102/tcl/run.tcl similarity index 82% rename from fpga/pulpissimo-zcu102/tcl/run.tcl rename to target/fpga/pulpissimo-zcu102/tcl/run.tcl index 00fa67b9..a5622a0a 100644 --- a/fpga/pulpissimo-zcu102/tcl/run.tcl +++ b/target/fpga/pulpissimo-zcu102/tcl/run.tcl @@ -73,10 +73,19 @@ open_run synth_1 -name netlist_1 set_property needs_refresh false [get_runs synth_1] # Remove unused IOBUF cells in padframe (they are not optimized away since the -# pad driver also drives the input creating a datapath from pad_xy_o to pad_xy_i -# ) -remove_cell i_pulpissimo/pad_frame_i/padinst_bootsel0 -remove_cell i_pulpissimo/pad_frame_i/padinst_bootsel1 +# pad driver also drives the input creating a datapath from pad_xy_o to pad_xy_i) +# Disconnect the nets and connect them to ground to avoid issues in optimization +remove_cell i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_bootsel* +disconnect_net -objects [get_nets i_pulpissimo/i_soc_domain/bootsel_i*] +connect_net -objects [get_nets i_pulpissimo/i_soc_domain/bootsel_i*] -net i_pulpissimo/ + +remove_cell i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_hyper* +disconnect_net -objects [get_nets i_pulpissimo/i_soc_domain/pad_to_hyper_i*] +connect_net -objects [get_nets i_pulpissimo/i_soc_domain/pad_to_hyper_i*] -net i_pulpissimo/ + +remove_cell i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_jtag_trst* +disconnect_net -objects [get_nets i_pulpissimo/i_soc_domain/jtag_trst_ni] +connect_net -objects [get_nets i_pulpissimo/i_soc_domain/jtag_trst_ni] -net i_pulpissimo/ # Launch Implementation diff --git a/fpga/pulpissimo-zcu104/.gitignore b/target/fpga/pulpissimo-zcu104/.gitignore similarity index 100% rename from fpga/pulpissimo-zcu104/.gitignore rename to target/fpga/pulpissimo-zcu104/.gitignore diff --git a/fpga/pulpissimo-zcu104/Makefile b/target/fpga/pulpissimo-zcu104/Makefile similarity index 100% rename from fpga/pulpissimo-zcu104/Makefile rename to target/fpga/pulpissimo-zcu104/Makefile diff --git a/fpga/pulpissimo-zcu104/README.md b/target/fpga/pulpissimo-zcu104/README.md similarity index 100% rename from fpga/pulpissimo-zcu104/README.md rename to target/fpga/pulpissimo-zcu104/README.md diff --git a/fpga/pulpissimo-zcu104/constraints/zcu104.xdc b/target/fpga/pulpissimo-zcu104/constraints/zcu104.xdc similarity index 63% rename from fpga/pulpissimo-zcu104/constraints/zcu104.xdc rename to target/fpga/pulpissimo-zcu104/constraints/zcu104.xdc index c53be58c..30ea1e16 100644 --- a/fpga/pulpissimo-zcu104/constraints/zcu104.xdc +++ b/target/fpga/pulpissimo-zcu104/constraints/zcu104.xdc @@ -12,17 +12,12 @@ #Create constraint for the clock input of the zcu104 board create_clock -period 8.000 -name ref_clk [get_ports ref_clk_p] - -#I2S and CAM interface are not used in this FPGA port. Set constraints to -#disable the clock -set_case_analysis 0 i_pulpissimo/safe_domain_i/cam_pclk_o -set_case_analysis 0 i_pulpissimo/safe_domain_i/i2s_slave_sck_o -#set_input_jitter tck 1.000 +set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets ref_clk] ## JTAG create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports pad_jtag_tck] set_input_jitter tck 1.000 -set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pad_jtag_tck_IBUF_inst/O] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_jtag_tck/O] # minimize routing delay @@ -34,35 +29,54 @@ set_max_delay -to [get_ports pad_jtag_tdo] 20.000 set_max_delay -from [get_ports pad_jtag_tms] 20.000 set_max_delay -from [get_ports pad_jtag_tdi] 20.000 -set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000 -set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000 -set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000 # reset signal set_false_path -from [get_ports pad_reset] set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pad_reset_IBUF_inst/O] +set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_pulpissimo/i_clock_gen/i_slow_clk_div/i_clk_mux/clk_o] +set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_pulpissimo/i_clock_gen/i_slow_clk_mngr/inst/clk_out1] + +set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_pulpissimo/i_clock_gen/i_clk_manager/inst/clk_out1] +set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_pulpissimo/i_clock_gen/i_clk_manager/inst/clk_out2] +set_property CLOCK_DEDICATED_ROUTE TRUE [get_nets i_pulpissimo/i_clock_gen/soc_clk_o] +set_property CLOCK_DEDICATED_ROUTE TRUE [get_nets i_pulpissimo/i_clock_gen/per_clk_o] + # Set ASYNC_REG attribute for ff synchronizers to place them closer together and # increase MTBF -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim0/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim1/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim2/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim3/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_timer_unit/s_ref_clk*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_ref_clk_sync/i_pulp_sync/r_reg_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/u_evnt_gen/r_ls_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim0/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim1/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim2/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim3/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_timer_unit/s_ref_clk*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_ref_clk_sync/i_pulp_sync/r_reg_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/u_evnt_gen/r_ls_sync_reg*] # Create asynchronous clock group between slow-clk and SoC clock. Those clocks # are considered asynchronously and proper synchronization regs are in place -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/safe_domain_i/i_slow_clk_gen/slow_clk_o]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/i_fpga_clk_gen/soc_clk_o]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/slow_clk_o]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] # Create asynchronous clock group between Per Clock and SoC clock. Those clocks # are considered asynchronously and proper synchronization regs are in place -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/clk_per_o]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/clk_soc_o]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out2]] # Create asynchronous clock group between JTAG TCK and SoC clock. -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/clk_soc_o]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] + +# Create asynchronous clock group between JTAG TCK and per clock. +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out2]] + +# Create asynchronous clock group between slow clock and JTAG TCK. +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/slow_clk_o]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] ############################################################# # _____ ____ _____ _ _ _ # diff --git a/fpga/pulpissimo-zcu104/elf_run.gdb b/target/fpga/pulpissimo-zcu104/elf_run.gdb similarity index 100% rename from fpga/pulpissimo-zcu104/elf_run.gdb rename to target/fpga/pulpissimo-zcu104/elf_run.gdb diff --git a/fpga/pulpissimo-zcu104/elf_run.sh b/target/fpga/pulpissimo-zcu104/elf_run.sh similarity index 100% rename from fpga/pulpissimo-zcu104/elf_run.sh rename to target/fpga/pulpissimo-zcu104/elf_run.sh diff --git a/fpga/pulpissimo-zcu104/fpga-settings.mk b/target/fpga/pulpissimo-zcu104/fpga-settings.mk similarity index 88% rename from fpga/pulpissimo-zcu104/fpga-settings.mk rename to target/fpga/pulpissimo-zcu104/fpga-settings.mk index cb7a5f87..a5a2dacc 100644 --- a/fpga/pulpissimo-zcu104/fpga-settings.mk +++ b/target/fpga/pulpissimo-zcu104/fpga-settings.mk @@ -1,7 +1,7 @@ export BOARD=zcu104 export XILINX_PART=xczu7ev-ffvc1156-2-e export XILINX_BOARD=xilinx.com:zcu104:part0:1.1 -export FC_CLK_PERIOD_NS=50 +export FC_CLK_PERIOD_NS=62.5 export PER_CLK_PERIOD_NS=100 export SLOW_CLK_PERIOD_NS=30517 $(info Setting environment variables for $(BOARD) board) diff --git a/fpga/pulpissimo-zcu104/ips/xilinx_clk_mngr/.gitignore b/target/fpga/pulpissimo-zcu104/ips/xilinx_clk_mngr/.gitignore similarity index 100% rename from fpga/pulpissimo-zcu104/ips/xilinx_clk_mngr/.gitignore rename to target/fpga/pulpissimo-zcu104/ips/xilinx_clk_mngr/.gitignore diff --git a/fpga/pulpissimo-zcu104/ips/xilinx_clk_mngr/Makefile b/target/fpga/pulpissimo-zcu104/ips/xilinx_clk_mngr/Makefile similarity index 100% rename from fpga/pulpissimo-zcu104/ips/xilinx_clk_mngr/Makefile rename to target/fpga/pulpissimo-zcu104/ips/xilinx_clk_mngr/Makefile diff --git a/fpga/pulpissimo-zcu104/ips/xilinx_clk_mngr/tcl/run.tcl b/target/fpga/pulpissimo-zcu104/ips/xilinx_clk_mngr/tcl/run.tcl similarity index 100% rename from fpga/pulpissimo-zcu104/ips/xilinx_clk_mngr/tcl/run.tcl rename to target/fpga/pulpissimo-zcu104/ips/xilinx_clk_mngr/tcl/run.tcl diff --git a/fpga/pulpissimo-zcu104/ips/xilinx_slow_clk_mngr/.gitignore b/target/fpga/pulpissimo-zcu104/ips/xilinx_slow_clk_mngr/.gitignore similarity index 100% rename from fpga/pulpissimo-zcu104/ips/xilinx_slow_clk_mngr/.gitignore rename to target/fpga/pulpissimo-zcu104/ips/xilinx_slow_clk_mngr/.gitignore diff --git a/fpga/pulpissimo-zcu104/ips/xilinx_slow_clk_mngr/Makefile b/target/fpga/pulpissimo-zcu104/ips/xilinx_slow_clk_mngr/Makefile similarity index 100% rename from fpga/pulpissimo-zcu104/ips/xilinx_slow_clk_mngr/Makefile rename to target/fpga/pulpissimo-zcu104/ips/xilinx_slow_clk_mngr/Makefile diff --git a/fpga/pulpissimo-zcu104/ips/xilinx_slow_clk_mngr/tcl/run.tcl b/target/fpga/pulpissimo-zcu104/ips/xilinx_slow_clk_mngr/tcl/run.tcl similarity index 100% rename from fpga/pulpissimo-zcu104/ips/xilinx_slow_clk_mngr/tcl/run.tcl rename to target/fpga/pulpissimo-zcu104/ips/xilinx_slow_clk_mngr/tcl/run.tcl diff --git a/fpga/pulpissimo-zcu104/openocd-zcu104-digilent-jtag-hs1.cfg b/target/fpga/pulpissimo-zcu104/openocd-zcu104-digilent-jtag-hs1.cfg similarity index 100% rename from fpga/pulpissimo-zcu104/openocd-zcu104-digilent-jtag-hs1.cfg rename to target/fpga/pulpissimo-zcu104/openocd-zcu104-digilent-jtag-hs1.cfg diff --git a/fpga/pulpissimo-zcu104/openocd-zcu104-olimex-arm-usb-ocd-h.cfg b/target/fpga/pulpissimo-zcu104/openocd-zcu104-olimex-arm-usb-ocd-h.cfg similarity index 100% rename from fpga/pulpissimo-zcu104/openocd-zcu104-olimex-arm-usb-ocd-h.cfg rename to target/fpga/pulpissimo-zcu104/openocd-zcu104-olimex-arm-usb-ocd-h.cfg diff --git a/fpga/pulpissimo-zcu104/rtl/cv32e40p_clock_gate_xilinx.sv b/target/fpga/pulpissimo-zcu104/rtl/cv32e40p_clock_gate_xilinx.sv similarity index 100% rename from fpga/pulpissimo-zcu104/rtl/cv32e40p_clock_gate_xilinx.sv rename to target/fpga/pulpissimo-zcu104/rtl/cv32e40p_clock_gate_xilinx.sv diff --git a/fpga/pulpissimo-zcu104/rtl/fpga_bootrom.sv b/target/fpga/pulpissimo-zcu104/rtl/fpga_bootrom.sv similarity index 100% rename from fpga/pulpissimo-zcu104/rtl/fpga_bootrom.sv rename to target/fpga/pulpissimo-zcu104/rtl/fpga_bootrom.sv diff --git a/fpga/pulpissimo-zcu104/rtl/fpga_clk_gen.sv b/target/fpga/pulpissimo-zcu104/rtl/fpga_clk_gen.sv similarity index 100% rename from fpga/pulpissimo-zcu104/rtl/fpga_clk_gen.sv rename to target/fpga/pulpissimo-zcu104/rtl/fpga_clk_gen.sv diff --git a/fpga/pulpissimo-zcu104/rtl/fpga_slow_clk_gen.sv b/target/fpga/pulpissimo-zcu104/rtl/fpga_slow_clk_gen.sv similarity index 100% rename from fpga/pulpissimo-zcu104/rtl/fpga_slow_clk_gen.sv rename to target/fpga/pulpissimo-zcu104/rtl/fpga_slow_clk_gen.sv diff --git a/fpga/pulpissimo-zcu104/rtl/pad_functional_xilinx.sv b/target/fpga/pulpissimo-zcu104/rtl/pad_functional_xilinx.sv similarity index 100% rename from fpga/pulpissimo-zcu104/rtl/pad_functional_xilinx.sv rename to target/fpga/pulpissimo-zcu104/rtl/pad_functional_xilinx.sv diff --git a/fpga/pulpissimo-zcu104/rtl/pulp_clock_gating_xilinx.sv b/target/fpga/pulpissimo-zcu104/rtl/pulp_clock_gating_xilinx.sv similarity index 100% rename from fpga/pulpissimo-zcu104/rtl/pulp_clock_gating_xilinx.sv rename to target/fpga/pulpissimo-zcu104/rtl/pulp_clock_gating_xilinx.sv diff --git a/target/fpga/pulpissimo-zcu104/rtl/xilinx_pulpissimo.v b/target/fpga/pulpissimo-zcu104/rtl/xilinx_pulpissimo.v new file mode 100644 index 00000000..aded4da9 --- /dev/null +++ b/target/fpga/pulpissimo-zcu104/rtl/xilinx_pulpissimo.v @@ -0,0 +1,153 @@ +//----------------------------------------------------------------------------- +// Title : PULPissimo Verilog Wrapper +//----------------------------------------------------------------------------- +// File : xilinx_pulpissimo.v +// Author : Manuel Eggimann +// Created : 21.05.2019 +//----------------------------------------------------------------------------- +// Description : +// Verilog Wrapper of PULPissimo to use the module within Xilinx IP integrator. +//----------------------------------------------------------------------------- +// Copyright (C) 2013-2019 ETH Zurich, University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +//----------------------------------------------------------------------------- + +module xilinx_pulpissimo ( + input wire ref_clk_p, + input wire ref_clk_n, + + inout wire pad_uart_rx, + inout wire pad_uart_tx, + inout wire pad_uart_rts, //Mapped to spim_csn0 + inout wire pad_uart_cts, //Mapped to spim_sck + + inout wire led0_o, //Mapped to spim_csn1 + inout wire led1_o, //Mapped to cam_pclk + inout wire led2_o, //Mapped to cam_hsync + inout wire led3_o, //Mapped to cam_data0 + + inout wire switch0_i, //Mapped to cam_data1 + inout wire switch1_i, //Mapped to cam_data2 + inout wire switch2_i, //Mapped to cam_data7 + inout wire switch3_i, //Mapped to cam_vsync + + inout wire btn0_i, //Mapped to cam_data3 + inout wire btn1_i, //Mapped to cam_data4 + inout wire btn2_i, //Mapped to cam_data5 + inout wire btn3_i, //Mapped to cam_data6 + + inout wire pad_i2c0_sda, + inout wire pad_i2c0_scl, + + inout wire pad_pmod0_4, //Mapped to spim_sdio0 + inout wire pad_pmod0_5, //Mapped to spim_sdio1 + inout wire pad_pmod0_6, //Mapped to spim_sdio2 + inout wire pad_pmod0_7, //Mapped to spim_sdio3 + + inout wire pad_pmod1_0, //Mapped to sdio_data0 + inout wire pad_pmod1_1, //Mapped to sdio_data1 + inout wire pad_pmod1_2, //Mapped to sdio_data2 + inout wire pad_pmod1_3, //Mapped to sdio_data3 + inout wire pad_pmod1_4, //Mapped to i2s0_sck + inout wire pad_pmod1_5, //Mapped to i2s0_ws + inout wire pad_pmod1_6, //Mapped to i2s0_sdi + inout wire pad_pmod1_7, //Mapped to i2s1_sdi + + inout wire pad_hdmi_scl, //Mapped to sdio_clk + inout wire pad_hdmi_sda, //Mapped to sdio_cmd + + input wire pad_reset, + + inout wire pad_jtag_tck, + inout wire pad_jtag_tdi, + inout wire pad_jtag_tdo, + inout wire pad_jtag_tms + ); + + localparam CORE_TYPE = 0; // 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY) + localparam USE_FPU = 1; + localparam USE_HWPE = 0; + + wire ref_clk; + + + //Differential to single ended clock conversion + IBUFGDS #( + .IOSTANDARD("LVDS"), + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") + ) i_sysclk_iobuf ( + .I(ref_clk_p), + .IB(ref_clk_n), + .O(ref_clk) + ); + + pulpissimo #( + .CORE_TYPE(CORE_TYPE), + .USE_FPU(USE_FPU), + .USE_HWPE(USE_HWPE) + ) i_pulpissimo ( + .pad_ref_clk ( ref_clk ), + .pad_reset_n ( ~pad_reset ), + .pad_clk_byp_en ( 1'b0 ), + + .pad_bootsel0 ( ), + .pad_bootsel1 ( ), + + .pad_jtag_tck ( pad_jtag_tck ), + .pad_jtag_tdi ( pad_jtag_tdi ), + .pad_jtag_tdo ( pad_jtag_tdo ), + .pad_jtag_tms ( pad_jtag_tms ), + .pad_jtag_trstn ( ), // Tied to 1 in run.tcl + + .pad_hyper_csn ( ), + .pad_hyper_reset_n ( ), + .pad_hyper_ck ( ), + .pad_hyper_ckn ( ), + .pad_hyper_dq ( ), + .pad_hyper_rwds ( ), + + .pad_io ( { + pad_i2c0_scl, // io_31 + pad_i2c0_sda, // io_30 + pad_pmod1_3, // io_29 + pad_pmod1_2, // io_28 + pad_pmod1_1, // io_27 + pad_pmod1_0, // io_26 + pad_hdmi_sda, // io_25 + pad_hdmi_scl, // io_24 + switch3_i, // io_23 + pad_pmod1_7, // io_22 + pad_pmod1_6, // io_21 + pad_pmod1_5, // io_20 + pad_pmod1_4, // io_19 + switch2_i, // io_18 + btn3_i, // io_17 + btn2_i, // io_16 + btn1_i, // io_15 + btn0_i, // io_14 + switch1_i, // io_13 + switch0_i, // io_12 + led3_o, // io_11 + led2_o, // io_10 + led1_o, // io_09 + led0_o, // io_08 + pad_pmod0_7, // io_07 + pad_pmod0_6, // io_06 + pad_pmod0_5, // io_05 + pad_pmod0_4, // io_04 + pad_uart_rts, // io_03 + pad_uart_cts, // io_02 + pad_uart_rx, // io_01 + pad_uart_tx // io_00 + } ) + ); + +endmodule diff --git a/fpga/pulpissimo-zcu104/tcl/.gitignore b/target/fpga/pulpissimo-zcu104/tcl/.gitignore similarity index 100% rename from fpga/pulpissimo-zcu104/tcl/.gitignore rename to target/fpga/pulpissimo-zcu104/tcl/.gitignore diff --git a/fpga/pulpissimo-zcu104/tcl/common.tcl b/target/fpga/pulpissimo-zcu104/tcl/common.tcl similarity index 100% rename from fpga/pulpissimo-zcu104/tcl/common.tcl rename to target/fpga/pulpissimo-zcu104/tcl/common.tcl diff --git a/fpga/pulpissimo-zcu104/tcl/download_bitstream.tcl b/target/fpga/pulpissimo-zcu104/tcl/download_bitstream.tcl similarity index 100% rename from fpga/pulpissimo-zcu104/tcl/download_bitstream.tcl rename to target/fpga/pulpissimo-zcu104/tcl/download_bitstream.tcl diff --git a/fpga/pulpissimo-zcu104/tcl/run.tcl b/target/fpga/pulpissimo-zcu104/tcl/run.tcl similarity index 82% rename from fpga/pulpissimo-zcu104/tcl/run.tcl rename to target/fpga/pulpissimo-zcu104/tcl/run.tcl index 9dc320cb..805863ba 100644 --- a/fpga/pulpissimo-zcu104/tcl/run.tcl +++ b/target/fpga/pulpissimo-zcu104/tcl/run.tcl @@ -73,10 +73,19 @@ open_run synth_1 -name netlist_1 set_property needs_refresh false [get_runs synth_1] # Remove unused IOBUF cells in padframe (they are not optimized away since the -# pad driver also drives the input creating a datapath from pad_xy_o to pad_xy_i -# ) -remove_cell i_pulpissimo/pad_frame_i/padinst_bootsel0 -remove_cell i_pulpissimo/pad_frame_i/padinst_bootsel1 +# pad driver also drives the input creating a datapath from pad_xy_o to pad_xy_i) +# Disconnect the nets and connect them to ground to avoid issues in optimization +remove_cell i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_bootsel* +disconnect_net -objects [get_nets i_pulpissimo/i_soc_domain/bootsel_i*] +connect_net -objects [get_nets i_pulpissimo/i_soc_domain/bootsel_i*] -net i_pulpissimo/ + +remove_cell i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_hyper* +disconnect_net -objects [get_nets i_pulpissimo/i_soc_domain/pad_to_hyper_i*] +connect_net -objects [get_nets i_pulpissimo/i_soc_domain/pad_to_hyper_i*] -net i_pulpissimo/ + +remove_cell i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_jtag_trst* +disconnect_net -objects [get_nets i_pulpissimo/i_soc_domain/jtag_trst_ni] +connect_net -objects [get_nets i_pulpissimo/i_soc_domain/jtag_trst_ni] -net i_pulpissimo/ # Launch Implementation diff --git a/fpga/pulpissimo-zcu106/.gitignore b/target/fpga/pulpissimo-zcu106/.gitignore similarity index 100% rename from fpga/pulpissimo-zcu106/.gitignore rename to target/fpga/pulpissimo-zcu106/.gitignore diff --git a/fpga/pulpissimo-zcu106/Makefile b/target/fpga/pulpissimo-zcu106/Makefile similarity index 100% rename from fpga/pulpissimo-zcu106/Makefile rename to target/fpga/pulpissimo-zcu106/Makefile diff --git a/fpga/pulpissimo-zcu106/README.md b/target/fpga/pulpissimo-zcu106/README.md similarity index 100% rename from fpga/pulpissimo-zcu106/README.md rename to target/fpga/pulpissimo-zcu106/README.md diff --git a/fpga/pulpissimo-zcu106/constraints/zcu106.xdc b/target/fpga/pulpissimo-zcu106/constraints/zcu106.xdc similarity index 64% rename from fpga/pulpissimo-zcu106/constraints/zcu106.xdc rename to target/fpga/pulpissimo-zcu106/constraints/zcu106.xdc index f5218176..01dfb2d0 100755 --- a/fpga/pulpissimo-zcu106/constraints/zcu106.xdc +++ b/target/fpga/pulpissimo-zcu106/constraints/zcu106.xdc @@ -12,18 +12,12 @@ #Create constraint for the clock input of the zcu106 board create_clock -period 8.000 -name ref_clk [get_ports ref_clk_p] - -#I2S and CAM interface are not used in this FPGA port. Set constraints to -#disable the clock -set_case_analysis 0 i_pulpissimo/safe_domain_i/cam_pclk_o -set_case_analysis 0 i_pulpissimo/safe_domain_i/i2s_slave_sck_o -#set_input_jitter tck 1.000 +set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets ref_clk] ## JTAG create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports pad_jtag_tck] set_input_jitter tck 1.000 -set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pad_jtag_tck_IBUF_inst/O] - +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_jtag_tck/O] # minimize routing delay set_input_delay -clock tck -clock_fall 5.000 [get_ports pad_jtag_tdi] @@ -34,35 +28,54 @@ set_max_delay -to [get_ports pad_jtag_tdo] 20.000 set_max_delay -from [get_ports pad_jtag_tms] 20.000 set_max_delay -from [get_ports pad_jtag_tdi] 20.000 -set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000 -set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000 -set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000 # reset signal set_false_path -from [get_ports pad_reset] set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pad_reset_IBUF_inst/O] +set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_pulpissimo/i_clock_gen/i_slow_clk_div/i_clk_mux/clk_o] +set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_pulpissimo/i_clock_gen/i_slow_clk_mngr/inst/clk_out1] + +set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_pulpissimo/i_clock_gen/i_clk_manager/inst/clk_out1] +set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_pulpissimo/i_clock_gen/i_clk_manager/inst/clk_out2] +set_property CLOCK_DEDICATED_ROUTE TRUE [get_nets i_pulpissimo/i_clock_gen/soc_clk_o] +set_property CLOCK_DEDICATED_ROUTE TRUE [get_nets i_pulpissimo/i_clock_gen/per_clk_o] + # Set ASYNC_REG attribute for ff synchronizers to place them closer together and # increase MTBF -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim0/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim1/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim2/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim3/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_timer_unit/s_ref_clk*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_ref_clk_sync/i_pulp_sync/r_reg_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/u_evnt_gen/r_ls_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim0/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim1/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim2/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim3/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_timer_unit/s_ref_clk*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_ref_clk_sync/i_pulp_sync/r_reg_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/u_evnt_gen/r_ls_sync_reg*] # Create asynchronous clock group between slow-clk and SoC clock. Those clocks # are considered asynchronously and proper synchronization regs are in place -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/safe_domain_i/i_slow_clk_gen/slow_clk_o]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/i_fpga_clk_gen/soc_clk_o]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/slow_clk_o]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] # Create asynchronous clock group between Per Clock and SoC clock. Those clocks # are considered asynchronously and proper synchronization regs are in place -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/clk_per_o]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/clk_soc_o]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out2]] # Create asynchronous clock group between JTAG TCK and SoC clock. -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/clk_soc_o]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] + +# Create asynchronous clock group between JTAG TCK and per clock. +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out2]] + +# Create asynchronous clock group between slow clock and JTAG TCK. +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/slow_clk_o]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] ############################################################# # _____ ____ _____ _ _ _ # diff --git a/fpga/pulpissimo-zcu106/elf_run.gdb b/target/fpga/pulpissimo-zcu106/elf_run.gdb similarity index 100% rename from fpga/pulpissimo-zcu106/elf_run.gdb rename to target/fpga/pulpissimo-zcu106/elf_run.gdb diff --git a/fpga/pulpissimo-zcu106/elf_run.sh b/target/fpga/pulpissimo-zcu106/elf_run.sh similarity index 100% rename from fpga/pulpissimo-zcu106/elf_run.sh rename to target/fpga/pulpissimo-zcu106/elf_run.sh diff --git a/fpga/pulpissimo-zcu106/fpga-settings.mk b/target/fpga/pulpissimo-zcu106/fpga-settings.mk similarity index 100% rename from fpga/pulpissimo-zcu106/fpga-settings.mk rename to target/fpga/pulpissimo-zcu106/fpga-settings.mk diff --git a/fpga/pulpissimo-zcu106/ips/xilinx_clk_mngr/.gitignore b/target/fpga/pulpissimo-zcu106/ips/xilinx_clk_mngr/.gitignore similarity index 100% rename from fpga/pulpissimo-zcu106/ips/xilinx_clk_mngr/.gitignore rename to target/fpga/pulpissimo-zcu106/ips/xilinx_clk_mngr/.gitignore diff --git a/fpga/pulpissimo-zcu106/ips/xilinx_clk_mngr/Makefile b/target/fpga/pulpissimo-zcu106/ips/xilinx_clk_mngr/Makefile similarity index 100% rename from fpga/pulpissimo-zcu106/ips/xilinx_clk_mngr/Makefile rename to target/fpga/pulpissimo-zcu106/ips/xilinx_clk_mngr/Makefile diff --git a/fpga/pulpissimo-zcu106/ips/xilinx_clk_mngr/tcl/run.tcl b/target/fpga/pulpissimo-zcu106/ips/xilinx_clk_mngr/tcl/run.tcl similarity index 100% rename from fpga/pulpissimo-zcu106/ips/xilinx_clk_mngr/tcl/run.tcl rename to target/fpga/pulpissimo-zcu106/ips/xilinx_clk_mngr/tcl/run.tcl diff --git a/fpga/pulpissimo-zcu106/ips/xilinx_slow_clk_mngr/.gitignore b/target/fpga/pulpissimo-zcu106/ips/xilinx_slow_clk_mngr/.gitignore similarity index 100% rename from fpga/pulpissimo-zcu106/ips/xilinx_slow_clk_mngr/.gitignore rename to target/fpga/pulpissimo-zcu106/ips/xilinx_slow_clk_mngr/.gitignore diff --git a/fpga/pulpissimo-zcu106/ips/xilinx_slow_clk_mngr/Makefile b/target/fpga/pulpissimo-zcu106/ips/xilinx_slow_clk_mngr/Makefile similarity index 100% rename from fpga/pulpissimo-zcu106/ips/xilinx_slow_clk_mngr/Makefile rename to target/fpga/pulpissimo-zcu106/ips/xilinx_slow_clk_mngr/Makefile diff --git a/fpga/pulpissimo-zcu106/ips/xilinx_slow_clk_mngr/tcl/run.tcl b/target/fpga/pulpissimo-zcu106/ips/xilinx_slow_clk_mngr/tcl/run.tcl similarity index 100% rename from fpga/pulpissimo-zcu106/ips/xilinx_slow_clk_mngr/tcl/run.tcl rename to target/fpga/pulpissimo-zcu106/ips/xilinx_slow_clk_mngr/tcl/run.tcl diff --git a/fpga/pulpissimo-zcu106/openocd-zcu106.cfg b/target/fpga/pulpissimo-zcu106/openocd-zcu106.cfg similarity index 100% rename from fpga/pulpissimo-zcu106/openocd-zcu106.cfg rename to target/fpga/pulpissimo-zcu106/openocd-zcu106.cfg diff --git a/fpga/pulpissimo-zcu106/rtl/cv32e40p_clock_gate_xilinx.sv b/target/fpga/pulpissimo-zcu106/rtl/cv32e40p_clock_gate_xilinx.sv similarity index 100% rename from fpga/pulpissimo-zcu106/rtl/cv32e40p_clock_gate_xilinx.sv rename to target/fpga/pulpissimo-zcu106/rtl/cv32e40p_clock_gate_xilinx.sv diff --git a/fpga/pulpissimo-zcu106/rtl/fpga_bootrom.sv b/target/fpga/pulpissimo-zcu106/rtl/fpga_bootrom.sv similarity index 100% rename from fpga/pulpissimo-zcu106/rtl/fpga_bootrom.sv rename to target/fpga/pulpissimo-zcu106/rtl/fpga_bootrom.sv diff --git a/fpga/pulpissimo-zcu106/rtl/fpga_clk_gen.sv b/target/fpga/pulpissimo-zcu106/rtl/fpga_clk_gen.sv similarity index 100% rename from fpga/pulpissimo-zcu106/rtl/fpga_clk_gen.sv rename to target/fpga/pulpissimo-zcu106/rtl/fpga_clk_gen.sv diff --git a/fpga/pulpissimo-zcu106/rtl/fpga_slow_clk_gen.sv b/target/fpga/pulpissimo-zcu106/rtl/fpga_slow_clk_gen.sv similarity index 100% rename from fpga/pulpissimo-zcu106/rtl/fpga_slow_clk_gen.sv rename to target/fpga/pulpissimo-zcu106/rtl/fpga_slow_clk_gen.sv diff --git a/fpga/pulpissimo-zcu106/rtl/pad_functional_xilinx.sv b/target/fpga/pulpissimo-zcu106/rtl/pad_functional_xilinx.sv similarity index 100% rename from fpga/pulpissimo-zcu106/rtl/pad_functional_xilinx.sv rename to target/fpga/pulpissimo-zcu106/rtl/pad_functional_xilinx.sv diff --git a/fpga/pulpissimo-zcu106/rtl/pulp_clock_gating_xilinx.sv b/target/fpga/pulpissimo-zcu106/rtl/pulp_clock_gating_xilinx.sv similarity index 100% rename from fpga/pulpissimo-zcu106/rtl/pulp_clock_gating_xilinx.sv rename to target/fpga/pulpissimo-zcu106/rtl/pulp_clock_gating_xilinx.sv diff --git a/fpga/pulpissimo-vcu108/rtl/xilinx_pulpissimo.v b/target/fpga/pulpissimo-zcu106/rtl/xilinx_pulpissimo.v old mode 100644 new mode 100755 similarity index 59% rename from fpga/pulpissimo-vcu108/rtl/xilinx_pulpissimo.v rename to target/fpga/pulpissimo-zcu106/rtl/xilinx_pulpissimo.v index 729b6a37..d9f04366 --- a/fpga/pulpissimo-vcu108/rtl/xilinx_pulpissimo.v +++ b/target/fpga/pulpissimo-zcu106/rtl/xilinx_pulpissimo.v @@ -66,10 +66,10 @@ module xilinx_pulpissimo input wire pad_reset, - input wire pad_jtag_tck, - input wire pad_jtag_tdi, - output wire pad_jtag_tdo, - input wire pad_jtag_tms + inout wire pad_jtag_tck, + inout wire pad_jtag_tdi, + inout wire pad_jtag_tdo, + inout wire pad_jtag_tms ); localparam CORE_TYPE = 0; // 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY) @@ -80,65 +80,75 @@ module xilinx_pulpissimo //Differential to single ended clock conversion - IBUFGDS - #( - .IOSTANDARD("LVDS"), - .DIFF_TERM("FALSE"), - .IBUF_LOW_PWR("FALSE")) - i_sysclk_iobuf - ( - .I(ref_clk_p), - .IB(ref_clk_n), - .O(ref_clk) - ); - - pulpissimo - #(.CORE_TYPE(CORE_TYPE), - .USE_FPU(USE_FPU), - .USE_HWPE(USE_HWPE) - ) i_pulpissimo - ( - .pad_spim_sdio0(pad_pmod0_4), - .pad_spim_sdio1(pad_pmod0_5), - .pad_spim_sdio2(pad_pmod0_6), - .pad_spim_sdio3(pad_pmod0_7), - .pad_spim_csn0(pad_uart_rts), - .pad_spim_csn1(led0_o), - .pad_spim_sck(pad_uart_cts), - .pad_uart_rx(pad_uart_rx), - .pad_uart_tx(pad_uart_tx), - .pad_cam_pclk(led1_o), - .pad_cam_hsync(led2_o), - .pad_cam_data0(led3_o), - .pad_cam_data1(switch0_i), - .pad_cam_data2(switch1_i), - .pad_cam_data3(btn0_i), - .pad_cam_data4(btn1_i), - .pad_cam_data5(btn2_i), - .pad_cam_data6(btn3_i), - .pad_cam_data7(switch2_i), - .pad_cam_vsync(switch3_i), - .pad_sdio_clk(pad_hdmi_scl), - .pad_sdio_cmd(pad_hdmi_sda), - .pad_sdio_data0(pad_pmod1_0), - .pad_sdio_data1(pad_pmod1_1), - .pad_sdio_data2(pad_pmod1_2), - .pad_sdio_data3(pad_pmod1_3), - .pad_i2c0_sda(pad_i2c0_sda), - .pad_i2c0_scl(pad_i2c0_scl), - .pad_i2s0_sck(pad_pmod1_4), - .pad_i2s0_ws(pad_pmod1_5), - .pad_i2s0_sdi(pad_pmod1_6), - .pad_i2s1_sdi(pad_pmod1_7), - .pad_reset_n(~pad_reset), - .pad_jtag_tck(pad_jtag_tck), - .pad_jtag_tdi(pad_jtag_tdi), - .pad_jtag_tdo(pad_jtag_tdo), - .pad_jtag_tms(pad_jtag_tms), - .pad_jtag_trst(1'b1), - .pad_xtal_in(ref_clk), - .pad_bootsel0(), - .pad_bootsel1() - ); + IBUFGDS #( + .IOSTANDARD("LVDS"), + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") + ) i_sysclk_iobuf ( + .I(ref_clk_p), + .IB(ref_clk_n), + .O(ref_clk) + ); + + pulpissimo #( + .CORE_TYPE(CORE_TYPE), + .USE_FPU(USE_FPU), + .USE_HWPE(USE_HWPE) + ) i_pulpissimo ( + .pad_ref_clk ( ref_clk ), + .pad_reset_n ( ~pad_reset ), + .pad_clk_byp_en ( 1'b0 ), + + .pad_bootsel0 ( ), // Tied to 0 in run.tcl + .pad_bootsel1 ( ), // Tied to 0 in run.tcl + + .pad_jtag_tck ( pad_jtag_tck ), + .pad_jtag_tdi ( pad_jtag_tdi ), + .pad_jtag_tdo ( pad_jtag_tdo ), + .pad_jtag_tms ( pad_jtag_tms ), + .pad_jtag_trstn ( ), // Tied to 1 in run.tcl + + .pad_hyper_csn ( ), // Tied to 0 in run.tcl + .pad_hyper_reset_n ( ), // Tied to 0 in run.tcl + .pad_hyper_ck ( ), // Tied to 0 in run.tcl + .pad_hyper_ckn ( ), // Tied to 0 in run.tcl + .pad_hyper_dq ( ), // Tied to 0 in run.tcl + .pad_hyper_rwds ( ), // Tied to 0 in run.tcl + + .pad_io ( { + pad_i2c0_scl, // io_31 + pad_i2c0_sda, // io_30 + pad_pmod1_3, // io_29 + pad_pmod1_2, // io_28 + pad_pmod1_1, // io_27 + pad_pmod1_0, // io_26 + pad_hdmi_sda, // io_25 + pad_hdmi_scl, // io_24 + switch3_i, // io_23 + pad_pmod1_7, // io_22 + pad_pmod1_6, // io_21 + pad_pmod1_5, // io_20 + pad_pmod1_4, // io_19 + switch2_i, // io_18 + btn3_i, // io_17 + btn2_i, // io_16 + btn1_i, // io_15 + btn0_i, // io_14 + switch1_i, // io_13 + switch0_i, // io_12 + led3_o, // io_11 + led2_o, // io_10 + led1_o, // io_09 + led0_o, // io_08 + pad_pmod0_7, // io_07 + pad_pmod0_6, // io_06 + pad_pmod0_5, // io_05 + pad_pmod0_4, // io_04 + pad_uart_rts, // io_03 + pad_uart_cts, // io_02 + pad_uart_rx, // io_01 + pad_uart_tx // io_00 + } ) + ); endmodule diff --git a/fpga/pulpissimo-zcu106/tcl/.gitignore b/target/fpga/pulpissimo-zcu106/tcl/.gitignore similarity index 100% rename from fpga/pulpissimo-zcu106/tcl/.gitignore rename to target/fpga/pulpissimo-zcu106/tcl/.gitignore diff --git a/fpga/pulpissimo-zcu106/tcl/common.tcl b/target/fpga/pulpissimo-zcu106/tcl/common.tcl similarity index 100% rename from fpga/pulpissimo-zcu106/tcl/common.tcl rename to target/fpga/pulpissimo-zcu106/tcl/common.tcl diff --git a/fpga/pulpissimo-zcu106/tcl/download_bitstream.tcl b/target/fpga/pulpissimo-zcu106/tcl/download_bitstream.tcl similarity index 100% rename from fpga/pulpissimo-zcu106/tcl/download_bitstream.tcl rename to target/fpga/pulpissimo-zcu106/tcl/download_bitstream.tcl diff --git a/fpga/pulpissimo-zcu106/tcl/run.tcl b/target/fpga/pulpissimo-zcu106/tcl/run.tcl similarity index 82% rename from fpga/pulpissimo-zcu106/tcl/run.tcl rename to target/fpga/pulpissimo-zcu106/tcl/run.tcl index fa47cbf5..f7978af7 100755 --- a/fpga/pulpissimo-zcu106/tcl/run.tcl +++ b/target/fpga/pulpissimo-zcu106/tcl/run.tcl @@ -74,10 +74,19 @@ open_run synth_1 -name netlist_1 set_property needs_refresh false [get_runs synth_1] # Remove unused IOBUF cells in padframe (they are not optimized away since the -# pad driver also drives the input creating a datapath from pad_xy_o to pad_xy_i -# ) -remove_cell i_pulpissimo/pad_frame_i/padinst_bootsel0 -remove_cell i_pulpissimo/pad_frame_i/padinst_bootsel1 +# pad driver also drives the input creating a datapath from pad_xy_o to pad_xy_i) +# Disconnect the nets and connect them to ground to avoid issues in optimization +remove_cell i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_bootsel* +disconnect_net -objects [get_nets i_pulpissimo/i_soc_domain/bootsel_i*] +connect_net -objects [get_nets i_pulpissimo/i_soc_domain/bootsel_i*] -net i_pulpissimo/ + +remove_cell i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_hyper* +disconnect_net -objects [get_nets i_pulpissimo/i_soc_domain/pad_to_hyper_i*] +connect_net -objects [get_nets i_pulpissimo/i_soc_domain/pad_to_hyper_i*] -net i_pulpissimo/ + +remove_cell i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_jtag_trst* +disconnect_net -objects [get_nets i_pulpissimo/i_soc_domain/jtag_trst_ni] +connect_net -objects [get_nets i_pulpissimo/i_soc_domain/jtag_trst_ni] -net i_pulpissimo/ # Launch Implementation diff --git a/fpga/pulpissimo-zedboard/.gitignore b/target/fpga/pulpissimo-zedboard/.gitignore similarity index 100% rename from fpga/pulpissimo-zedboard/.gitignore rename to target/fpga/pulpissimo-zedboard/.gitignore diff --git a/fpga/pulpissimo-zedboard/Makefile b/target/fpga/pulpissimo-zedboard/Makefile similarity index 100% rename from fpga/pulpissimo-zedboard/Makefile rename to target/fpga/pulpissimo-zedboard/Makefile diff --git a/fpga/pulpissimo-zedboard/README.md b/target/fpga/pulpissimo-zedboard/README.md similarity index 100% rename from fpga/pulpissimo-zedboard/README.md rename to target/fpga/pulpissimo-zedboard/README.md diff --git a/fpga/pulpissimo-zedboard/constraints/zedboard.xdc b/target/fpga/pulpissimo-zedboard/constraints/zedboard.xdc similarity index 65% rename from fpga/pulpissimo-zedboard/constraints/zedboard.xdc rename to target/fpga/pulpissimo-zedboard/constraints/zedboard.xdc index 856cddce..be7fd1f9 100644 --- a/fpga/pulpissimo-zedboard/constraints/zedboard.xdc +++ b/target/fpga/pulpissimo-zedboard/constraints/zedboard.xdc @@ -13,16 +13,10 @@ #Create constraint for the clock input of the ZedBoard create_clock -period 10.000 -name ref_clk_i [get_ports ref_clk_i] -#I2S and CAM interface are not used in this FPGA port. Set constraints to -#disable the clock -set_case_analysis 0 i_pulpissimo/safe_domain_i/cam_pclk_o -set_case_analysis 0 i_pulpissimo/safe_domain_i/i2s_slave_sck_o -#set_input_jitter tck 1.000 - ## JTAG create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports pad_jtag_tck] set_input_jitter tck 1.000 -set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets tck_int] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_jtag_tck/O] # minimize routing delay @@ -34,34 +28,49 @@ set_max_delay -to [get_ports pad_jtag_tdo] 20.000 set_max_delay -from [get_ports pad_jtag_tms] 20.000 set_max_delay -from [get_ports pad_jtag_tdi] 20.000 -set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000 -set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000 -set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000 # reset signal set_false_path -from [get_ports pad_reset] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pad_reset_n_IBUF] + +set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_pulpissimo/i_clock_gen/i_slow_clk_div/i_clk_mux/clk_o] +set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_pulpissimo/i_clock_gen/i_slow_clk_mngr/inst/clk_out1] # Set ASYNC_REG attribute for ff synchronizers to place them closer together and # increase MTBF -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim0/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim1/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim2/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim3/u_in_stage/r_ls_clk_sync_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_timer_unit/s_ref_clk*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_ref_clk_sync/i_pulp_sync/r_reg_reg*] -set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/u_evnt_gen/r_ls_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim0/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim1/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim2/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim3/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_timer_unit/s_ref_clk*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_ref_clk_sync/i_pulp_sync/r_reg_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/u_evnt_gen/r_ls_sync_reg*] # Create asynchronous clock group between slow-clk and SoC clock. Those clocks # are considered asynchronously and proper synchronization regs are in place -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/safe_domain_i/i_slow_clk_gen/slow_clk_o]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/i_fpga_clk_gen/soc_clk_o]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/slow_clk_o]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] # Create asynchronous clock group between Per Clock and SoC clock. Those clocks # are considered asynchronously and proper synchronization regs are in place -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/clk_per_o]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/clk_soc_o]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out2]] # Create asynchronous clock group between JTAG TCK and SoC clock. -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/clk_soc_o]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] + +# Create asynchronous clock group between JTAG TCK and per clock. +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out2]] + +# Create asynchronous clock group between slow clock and JTAG TCK. +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/slow_clk_o]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] ############################################################# # _____ ____ _____ _ _ _ # diff --git a/fpga/pulpissimo-zedboard/elf_run.gdb b/target/fpga/pulpissimo-zedboard/elf_run.gdb similarity index 100% rename from fpga/pulpissimo-zedboard/elf_run.gdb rename to target/fpga/pulpissimo-zedboard/elf_run.gdb diff --git a/fpga/pulpissimo-zedboard/elf_run.sh b/target/fpga/pulpissimo-zedboard/elf_run.sh similarity index 100% rename from fpga/pulpissimo-zedboard/elf_run.sh rename to target/fpga/pulpissimo-zedboard/elf_run.sh diff --git a/fpga/pulpissimo-zedboard/fpga-settings.mk b/target/fpga/pulpissimo-zedboard/fpga-settings.mk similarity index 100% rename from fpga/pulpissimo-zedboard/fpga-settings.mk rename to target/fpga/pulpissimo-zedboard/fpga-settings.mk diff --git a/fpga/pulpissimo-zedboard/ips/xilinx_clk_mngr/.gitignore b/target/fpga/pulpissimo-zedboard/ips/xilinx_clk_mngr/.gitignore similarity index 100% rename from fpga/pulpissimo-zedboard/ips/xilinx_clk_mngr/.gitignore rename to target/fpga/pulpissimo-zedboard/ips/xilinx_clk_mngr/.gitignore diff --git a/fpga/pulpissimo-zedboard/ips/xilinx_clk_mngr/Makefile b/target/fpga/pulpissimo-zedboard/ips/xilinx_clk_mngr/Makefile similarity index 100% rename from fpga/pulpissimo-zedboard/ips/xilinx_clk_mngr/Makefile rename to target/fpga/pulpissimo-zedboard/ips/xilinx_clk_mngr/Makefile diff --git a/fpga/pulpissimo-zedboard/ips/xilinx_clk_mngr/tcl/run.tcl b/target/fpga/pulpissimo-zedboard/ips/xilinx_clk_mngr/tcl/run.tcl similarity index 100% rename from fpga/pulpissimo-zedboard/ips/xilinx_clk_mngr/tcl/run.tcl rename to target/fpga/pulpissimo-zedboard/ips/xilinx_clk_mngr/tcl/run.tcl diff --git a/fpga/pulpissimo-zedboard/ips/xilinx_slow_clk_mngr/.gitignore b/target/fpga/pulpissimo-zedboard/ips/xilinx_slow_clk_mngr/.gitignore similarity index 100% rename from fpga/pulpissimo-zedboard/ips/xilinx_slow_clk_mngr/.gitignore rename to target/fpga/pulpissimo-zedboard/ips/xilinx_slow_clk_mngr/.gitignore diff --git a/fpga/pulpissimo-zedboard/ips/xilinx_slow_clk_mngr/Makefile b/target/fpga/pulpissimo-zedboard/ips/xilinx_slow_clk_mngr/Makefile similarity index 100% rename from fpga/pulpissimo-zedboard/ips/xilinx_slow_clk_mngr/Makefile rename to target/fpga/pulpissimo-zedboard/ips/xilinx_slow_clk_mngr/Makefile diff --git a/fpga/pulpissimo-zedboard/ips/xilinx_slow_clk_mngr/tcl/run.tcl b/target/fpga/pulpissimo-zedboard/ips/xilinx_slow_clk_mngr/tcl/run.tcl similarity index 100% rename from fpga/pulpissimo-zedboard/ips/xilinx_slow_clk_mngr/tcl/run.tcl rename to target/fpga/pulpissimo-zedboard/ips/xilinx_slow_clk_mngr/tcl/run.tcl diff --git a/fpga/pulpissimo-zedboard/openocd-zedboard-common.cfg b/target/fpga/pulpissimo-zedboard/openocd-zedboard-common.cfg similarity index 100% rename from fpga/pulpissimo-zedboard/openocd-zedboard-common.cfg rename to target/fpga/pulpissimo-zedboard/openocd-zedboard-common.cfg diff --git a/fpga/pulpissimo-zedboard/openocd-zedboard-ftdi2232.cfg b/target/fpga/pulpissimo-zedboard/openocd-zedboard-ftdi2232.cfg similarity index 100% rename from fpga/pulpissimo-zedboard/openocd-zedboard-ftdi2232.cfg rename to target/fpga/pulpissimo-zedboard/openocd-zedboard-ftdi2232.cfg diff --git a/fpga/pulpissimo-zedboard/openocd-zedboard-hs2.cfg b/target/fpga/pulpissimo-zedboard/openocd-zedboard-hs2.cfg similarity index 100% rename from fpga/pulpissimo-zedboard/openocd-zedboard-hs2.cfg rename to target/fpga/pulpissimo-zedboard/openocd-zedboard-hs2.cfg diff --git a/fpga/pulpissimo-zedboard/openocd-zedboard-usbblaster.cfg b/target/fpga/pulpissimo-zedboard/openocd-zedboard-usbblaster.cfg similarity index 100% rename from fpga/pulpissimo-zedboard/openocd-zedboard-usbblaster.cfg rename to target/fpga/pulpissimo-zedboard/openocd-zedboard-usbblaster.cfg diff --git a/fpga/pulpissimo-zedboard/rtl/cv32e40p_clock_gate_xilinx.sv b/target/fpga/pulpissimo-zedboard/rtl/cv32e40p_clock_gate_xilinx.sv similarity index 100% rename from fpga/pulpissimo-zedboard/rtl/cv32e40p_clock_gate_xilinx.sv rename to target/fpga/pulpissimo-zedboard/rtl/cv32e40p_clock_gate_xilinx.sv diff --git a/fpga/pulpissimo-zedboard/rtl/fpga_bootrom.sv b/target/fpga/pulpissimo-zedboard/rtl/fpga_bootrom.sv similarity index 100% rename from fpga/pulpissimo-zedboard/rtl/fpga_bootrom.sv rename to target/fpga/pulpissimo-zedboard/rtl/fpga_bootrom.sv diff --git a/fpga/pulpissimo-zedboard/rtl/fpga_clk_gen.sv b/target/fpga/pulpissimo-zedboard/rtl/fpga_clk_gen.sv similarity index 100% rename from fpga/pulpissimo-zedboard/rtl/fpga_clk_gen.sv rename to target/fpga/pulpissimo-zedboard/rtl/fpga_clk_gen.sv diff --git a/fpga/pulpissimo-zedboard/rtl/fpga_slow_clk_gen.sv b/target/fpga/pulpissimo-zedboard/rtl/fpga_slow_clk_gen.sv similarity index 100% rename from fpga/pulpissimo-zedboard/rtl/fpga_slow_clk_gen.sv rename to target/fpga/pulpissimo-zedboard/rtl/fpga_slow_clk_gen.sv diff --git a/fpga/pulpissimo-zedboard/rtl/pad_functional_xilinx.sv b/target/fpga/pulpissimo-zedboard/rtl/pad_functional_xilinx.sv similarity index 100% rename from fpga/pulpissimo-zedboard/rtl/pad_functional_xilinx.sv rename to target/fpga/pulpissimo-zedboard/rtl/pad_functional_xilinx.sv diff --git a/fpga/pulpissimo-zedboard/rtl/pulp_clock_gating_xilinx.sv b/target/fpga/pulpissimo-zedboard/rtl/pulp_clock_gating_xilinx.sv similarity index 100% rename from fpga/pulpissimo-zedboard/rtl/pulp_clock_gating_xilinx.sv rename to target/fpga/pulpissimo-zedboard/rtl/pulp_clock_gating_xilinx.sv diff --git a/fpga/pulpissimo-zedboard/rtl/xilinx_pulpissimo.v b/target/fpga/pulpissimo-zedboard/rtl/xilinx_pulpissimo.v similarity index 66% rename from fpga/pulpissimo-zedboard/rtl/xilinx_pulpissimo.v rename to target/fpga/pulpissimo-zedboard/rtl/xilinx_pulpissimo.v index c39a6973..ebc16288 100644 --- a/fpga/pulpissimo-zedboard/rtl/xilinx_pulpissimo.v +++ b/target/fpga/pulpissimo-zedboard/rtl/xilinx_pulpissimo.v @@ -62,10 +62,10 @@ module xilinx_pulpissimo ( input wire pad_reset, - input wire pad_jtag_tck, - input wire pad_jtag_tdi, - output wire pad_jtag_tdo, - input wire pad_jtag_tms + inout wire pad_jtag_tck, + inout wire pad_jtag_tdi, + inout wire pad_jtag_tdo, + inout wire pad_jtag_tms ); localparam CORE_TYPE = 0; // 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY) @@ -73,21 +73,15 @@ module xilinx_pulpissimo ( localparam USE_HWPE = 0; wire ref_clk_int; - wire tck_int; wire rst_n; assign rst_n = ~pad_reset; // Input clock buffer BUFG i_sysclk_bufg ( - .I(ref_clk_i), - .O(ref_clk_int) + .I(ref_clk_i), + .O(ref_clk_int) ); - // TCK clock buffer (dedicated route is false in constraints) - IBUF i_tck_iobuf ( - .I(pad_jtag_tck), - .O(tck_int) - ); // PULPissimo instance pulpissimo #( @@ -95,47 +89,60 @@ module xilinx_pulpissimo ( .USE_FPU(USE_FPU), .USE_HWPE(USE_HWPE) ) i_pulpissimo ( - .pad_spim_sdio0(led4_o), - .pad_spim_sdio1(led5_o), - .pad_spim_sdio2(led6_o), - .pad_spim_sdio3(led7_o), - .pad_spim_csn0(pad_uart_rts), - .pad_spim_csn1(led0_o), - .pad_spim_sck(pad_uart_cts), - .pad_uart_rx(pad_uart_rx), - .pad_uart_tx(pad_uart_tx), - .pad_cam_pclk(led1_o), - .pad_cam_hsync(led2_o), - .pad_cam_data0(led3_o), - .pad_cam_data1(switch0_i), - .pad_cam_data2(switch1_i), - .pad_cam_data3(btnu_i), - .pad_cam_data4(btnr_i), - .pad_cam_data5(btnd_i), - .pad_cam_data6(btnl_i), - .pad_cam_data7(switch2_i), - .pad_cam_vsync(switch3_i), - .pad_sdio_clk(pad_i2c1_scl), - .pad_sdio_cmd(pad_i2c1_sda), - .pad_sdio_data0(switch4_i), - .pad_sdio_data1(switch5_i), - .pad_sdio_data2(switch6_i), - .pad_sdio_data3(switch7_i), - .pad_i2c0_sda(pad_i2c0_sda), - .pad_i2c0_scl(pad_i2c0_scl), - .pad_i2s0_sck(pad_pmod1_4), - .pad_i2s0_ws(pad_pmod1_5), - .pad_i2s0_sdi(pad_pmod1_6), - .pad_i2s1_sdi(pad_pmod1_7), - .pad_reset_n(rst_n), - .pad_jtag_tck(tck_int), - .pad_jtag_tdi(pad_jtag_tdi), - .pad_jtag_tdo(pad_jtag_tdo), - .pad_jtag_tms(pad_jtag_tms), - .pad_jtag_trst(1'b1), - .pad_xtal_in(ref_clk_int), - .pad_bootsel0(), - .pad_bootsel1() + .pad_ref_clk ( ref_clk_int ), + .pad_reset_n ( rst_n ), + .pad_clk_byp_en ( 1'b0 ), + + .pad_bootsel0 ( ), + .pad_bootsel1 ( ), + + .pad_jtag_tck ( pad_jtag_tck ), + .pad_jtag_tdi ( pad_jtag_tdi ), + .pad_jtag_tdo ( pad_jtag_tdo ), + .pad_jtag_tms ( pad_jtag_tms ), + .pad_jtag_trstn ( ), // Tied to 1 in run.tcl + + .pad_hyper_csn ( ), + .pad_hyper_reset_n ( ), + .pad_hyper_ck ( ), + .pad_hyper_ckn ( ), + .pad_hyper_dq ( ), + .pad_hyper_rwds ( ), + + .pad_io ( { + pad_i2c0_scl, // io_31 + pad_i2c0_sda, // io_30 + switch7_i, // io_29 + switch6_i, // io_28 + switch5_i, // io_27 + switch4_i, // io_26 + pad_i2c1_sda, // io_25 + pad_i2c1_scl, // io_24 + switch3_i, // io_23 + pad_pmod1_7, // io_22 + pad_pmod1_6, // io_21 + pad_pmod1_5, // io_20 + pad_pmod1_4, // io_19 + switch2_i, // io_18 + btnu_i, // io_17 + btnr_i, // io_16 + btnl_i, // io_15 + btnd_i, // io_14 + switch1_i, // io_13 + switch0_i, // io_12 + led3_o, // io_11 + led2_o, // io_10 + led1_o, // io_09 + led0_o, // io_08 + led7_o, // io_07 + led6_o, // io_06 + led5_o, // io_05 + led4_o, // io_04 + pad_uart_rts, // io_03 + pad_uart_cts, // io_02 + pad_uart_rx, // io_01 + pad_uart_tx // io_00 + } ) ); endmodule diff --git a/fpga/pulpissimo-zedboard/tcl/.gitignore b/target/fpga/pulpissimo-zedboard/tcl/.gitignore similarity index 100% rename from fpga/pulpissimo-zedboard/tcl/.gitignore rename to target/fpga/pulpissimo-zedboard/tcl/.gitignore diff --git a/fpga/pulpissimo-zedboard/tcl/common.tcl b/target/fpga/pulpissimo-zedboard/tcl/common.tcl similarity index 100% rename from fpga/pulpissimo-zedboard/tcl/common.tcl rename to target/fpga/pulpissimo-zedboard/tcl/common.tcl diff --git a/fpga/pulpissimo-zedboard/tcl/download_bitstream.tcl b/target/fpga/pulpissimo-zedboard/tcl/download_bitstream.tcl similarity index 100% rename from fpga/pulpissimo-zedboard/tcl/download_bitstream.tcl rename to target/fpga/pulpissimo-zedboard/tcl/download_bitstream.tcl diff --git a/fpga/pulpissimo-zedboard/tcl/run.tcl b/target/fpga/pulpissimo-zedboard/tcl/run.tcl similarity index 80% rename from fpga/pulpissimo-zedboard/tcl/run.tcl rename to target/fpga/pulpissimo-zedboard/tcl/run.tcl index d2c293e9..a5e8487d 100644 --- a/fpga/pulpissimo-zedboard/tcl/run.tcl +++ b/target/fpga/pulpissimo-zedboard/tcl/run.tcl @@ -73,10 +73,19 @@ open_run synth_1 -name netlist_1 set_property needs_refresh false [get_runs synth_1] # Remove unused IOBUF cells in padframe (they are not optimized away since the -# pad driver also drives the input creating a datapath from pad_xy_o to pad_xy_i -# ) -remove_cell i_pulpissimo/pad_frame_i/padinst_bootsel0 -remove_cell i_pulpissimo/pad_frame_i/padinst_bootsel1 +# pad driver also drives the input creating a datapath from pad_xy_o to pad_xy_i) +# Disconnect the nets and connect them to ground to avoid issues in optimization +remove_cell i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_bootsel* +disconnect_net -objects [get_nets i_pulpissimo/i_soc_domain/bootsel_i*] +connect_net -objects [get_nets i_pulpissimo/i_soc_domain/bootsel_i*] -net i_pulpissimo/ + +remove_cell i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_hyper* +disconnect_net -objects [get_nets i_pulpissimo/i_soc_domain/pad_to_hyper_i*] +connect_net -objects [get_nets i_pulpissimo/i_soc_domain/pad_to_hyper_i*] -net i_pulpissimo/ + +remove_cell i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_jtag_trst* +disconnect_net -objects [get_nets i_pulpissimo/i_soc_domain/jtag_trst_ni] +connect_net -objects [get_nets i_pulpissimo/i_soc_domain/jtag_trst_ni] -net i_pulpissimo/ # Launch Implementation diff --git a/fpga/pulpissimo/tcl/add_sources.tcl b/target/fpga/pulpissimo/tcl/add_sources.tcl similarity index 100% rename from fpga/pulpissimo/tcl/add_sources.tcl rename to target/fpga/pulpissimo/tcl/add_sources.tcl diff --git a/spyglass/.gitignore b/target/lint/spyglass/.gitignore similarity index 100% rename from spyglass/.gitignore rename to target/lint/spyglass/.gitignore diff --git a/target/lint/spyglass/Makefile b/target/lint/spyglass/Makefile new file mode 100644 index 00000000..ed9c827a --- /dev/null +++ b/target/lint/spyglass/Makefile @@ -0,0 +1,54 @@ +# Copyright 2020 ETH Zurich and University of Bologna + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at + +# http://www.apache.org/licenses/LICENSE-2.0 + +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +PROJECT_NAME ?= pulpissimo +PULPISSIMO_ROOT ?= $(shell git rev-parse --show-toplevel) +SG_SHELL_CMD ?= spyglass-2022.06 sg_shell +SG_GUI_CMD ?= spyglass-2022.06 spyglass +SPYGLASS_DIR ?= $(PULPISSIMO_ROOT)/target/lint/spyglass +SPYGLASS_WORKING_DIR = $(PULPISSIMO_ROOT)/build/spyglass + +## @section Spyglass Lint + +.DEFAULT_GOAL := help +include $(PULPISSIMO_ROOT)/utils/utils.mk + +.PHONY: $(SPYGLASS_WORKING_DIR)/sources.f +$(SPYGLASS_WORKING_DIR)/sources.f: $(PULPISSIMO_UTILS)/bender + mkdir -p $(SPYGLASS_WORKING_DIR) + $(PULPISSIMO_UTILS)/bender script -t synthesis verilator > $(SPYGLASS_WORKING_DIR)/sources.f + +.PHONY: lint_rtl +## Run spyglass lint with rtl_handoff methodology +lint_rtl: $(SPYGLASS_WORKING_DIR)/reports/lint_rtl.report.xml + +$(SPYGLASS_WORKING_DIR)/reports/moresimple.rpt: $(SPYGLASS_WORKING_DIR)/sources.f + echo $(SG_SHELL_CMD) + cd $(SPYGLASS_WORKING_DIR) && $(SG_SHELL_CMD) -tcl_file_continue_on_error -tcl $(SPYGLASS_DIR)/run_lint_rtl_handoff.tcl + +# generate generate junit report from spyglass report +$(SPYGLASS_WORKING_DIR)/reports/lint_rtl.report.xml: $(SPYGLASS_WORKING_DIR)/reports/moresimple.rpt + $(SPYGLASS_DIR)/convert_report_to_junit.py --error-level error $(SPYGLASS_WORKING_DIR)/reports/moresimple.rpt > $(SPYGLASS_WORKING_DIR)/reports/lint_rtl.report.xml + +.PHONY: show_results +## Open the generated lint results in Spyglass GUI +show_results: + cd $(SPYGLASS_WORKING_DIR) && $(SG_GUI_CMD) -project $(PROJECT_NAME).prj + +.PHONY: clean_spyglass clean +## Clean all +clean: clean_spyglass +## Delete the spyglass working directory +clean_spyglass: + rm -rf $(SPYGLASS_WORKING_DIR) diff --git a/spyglass/convert_report_to_junit.py b/target/lint/spyglass/convert_report_to_junit.py similarity index 100% rename from spyglass/convert_report_to_junit.py rename to target/lint/spyglass/convert_report_to_junit.py diff --git a/spyglass/run_lint_rtl_handoff.tcl b/target/lint/spyglass/run_lint_rtl_handoff.tcl similarity index 100% rename from spyglass/run_lint_rtl_handoff.tcl rename to target/lint/spyglass/run_lint_rtl_handoff.tcl diff --git a/spyglass/waiver.awl b/target/lint/spyglass/waiver.awl similarity index 100% rename from spyglass/waiver.awl rename to target/lint/spyglass/waiver.awl diff --git a/target/sim/README.md b/target/sim/README.md new file mode 100644 index 00000000..f8679a78 --- /dev/null +++ b/target/sim/README.md @@ -0,0 +1,66 @@ +# Simulation Environments +Pulpissimo supports simulation on various environments like commercial RTL +simulators or Verilator. The scripts and source files for simulation are +contained in this directory grouped in subdirectories by environment. + + +## Supported Simulation Environments +### `Generic` +The default generic SV testbench is a regular non-UVM SystemVerilog testbench to +be simulated on conventional RTL simulators. There is a more complex testbench +based on the legacy PULPissimo testebnch (`tb_pulp.sv`) and a simplified version +to use as a template for your own TB (`tb_pulp_simple.sv`). + +### `Verilator` +TODO + +## Subdirectories +* `tb`: Contains the source-code like SystemVerilog, C (e.g. for DPI) or C++ + (for Verilator) for the testebenches. The folder might also contains +* `vip`: Contains **optional** additionalverification IP for the environments + that are not strictly necessary for the environment's TB. +* `simulators`: Contains the invocation scripts/makefiles to start the various + simulation environments. + +## Simulation Environment Invocation +In order to streamline switching between different simulation environments and +to allow for easy simulation invocation during software development for +Pulpissimo, we define a standard interface to invoke a simulation interface +based on environment variables. + +Each simulation environment shall contain a Makefile with a target called +`run_sim` to invoke the simulation. The `run_sim` target shall use the following +**mandatory** environment variables (supplied by the user or the development +SDK) to control simulation invocation: + +* `EXECUTABLE_PATH` The absolute path to the compiled ELF executable to be run + on PULPissimo. + +Besides the mandatory environment variables, the following optional envionment +variables shall be used for sim. environments supporting the relevant feature: + +* `GUI` [`0` or `1`] For tools with a graphical user interface, this switch + controls whether the user whishes to invoke the tool in GUI mode (1) or wants + to simulate in console only mode. + +* `BATCH` [`0` or `1`] If enabled, the `run_sim` target invocatoin shall exit + with the simulated `main` functions return value as exit code. I.e. the value + returned by the simulated firmware shall be returned by the the `run_sim** + target as well. This simplifies CI testing using tests written in the form of + C-applications. Simulation environments may expose optional custom environment + variables to modify this behavior e.g. in order to fail test with a non-zero + exit value based on the status of some optional verification IP. + +Each simulation environment may expose additional environment variables for +environment-specific behavior that cannot be easily supported by all +environments. + +Further, the simulation can be launched with built-in launchers configured in +the `pulp-runtime` and `pulp-sdk` by setting up the appropriate environment +variables, indicated at the end of the build flow. `VSIM_PATH` needs to point to +the questasim build directory for PULPissimo, and `VSIM` needs to containt the +same value as `VSIM_BIN`. + +**The ``run_sim`` target in the sim. environemts Makefile must be documented +using Makefile docs** (see ../../utils/utils.mk). All supported variables must +be documented including the mandatory and optional variables defined above. diff --git a/target/sim/questasim/Makefile b/target/sim/questasim/Makefile new file mode 100644 index 00000000..9adefd2f --- /dev/null +++ b/target/sim/questasim/Makefile @@ -0,0 +1,132 @@ +# Copyright 2024 ETH Zurich and University of Bologna + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at + +# http://www.apache.org/licenses/LICENSE-2.0 + +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +PULPISSIMO_ROOT ?= $(shell git rev-parse --show-toplevel) + +QUESTA_BUILD_DIR = $(PULPISSIMO_ROOT)/build/questasim + +include $(PULPISSIMO_ROOT)/utils/utils.mk + +## Configuration Variables for Bender, Questasim behavior +BENDER_SCRIPTS_ARGS += -t rtl -t test -t rtl_sim +BENDER_VIP_SCRIPT_ARGS ?= -t rt_dpi -t i2c_vip -t flash_vip -t i2s_vip -t use_vips +VSIM_ARGS ?= -64 +VLOG_ARGS += -suppress 2583 -suppress 13314 \"+incdir+\$$ROOT/hw/includes\" +VCOM_ARGS += "" +VOPT_ARGS ?= +acc +VSIM_BIN ?= "vsim" +VSIM_USER_PLUSARGS ?= "" +VSIM_DEFAULT_PLUSARGS ?= +nowarnTRAN +nowarnTSCALE +nowarnTFMPC -suppress 8386 +RISCV_OBJCOPY_BIN ?= 'riscv32-unknown-elf-objcopy' +SIM_TOP ?= 'tb_pulp' +SIM_TOP_OPT ?= vopt_tb +USE_VIPS ?= 0 + + + +## @section Questasim Simulation + +## Simulate the given executable using RTL simulationon with Siemens QuestaSIM. +## +## The simulation can be invoked in various bootmode controllable via the +## bootmode parameter. The 'jtag_legacy' boot mode uses the legacy PULP JTAG TAP +## to preload the binary into L2 memory. 'jtag_openocd' uses the newer, +## standardized RISC-V JTAG debug module for preloading (much slower than legacy +## in simulation). 'fastboot' Uses virtual through hierarchy connection in the +## testbench to provide very fast preloading. However this mode is not +## physically possible and cannot be used in real systems. Don't use this for +## bootability verification! +## +## @param EXECUTABLE_PATH=/path/to/elf_binary/build/app The absolute path to the ELF binary to simulate +## @param GUI=1 If 1, start QuestaSIM in GUI mode, otherwise start in batch mode. +## @param VSIM_BIN=vsim The command to invoke the vsim binary. +## @param BOOTMODE=jtag The bootmode to use to start PULPissimo. Possible values: jtag_legacy, jtag_openocd or fastboot. +.PHONY: run_sim +run_sim: $(QUESTA_BUILD_DIR)/app.s19 + ln -snf waves $(QUESTA_BUILD_DIR)/waves +ifeq ($(gui), 1) + cd $(QUESTA_BUILD_DIR) && $(VSIM_BIN) $(VSIM_ARGS) -gui -do "vsim -t ps $(SIM_TOP_OPT) $(VSIM_DEFAULT_PLUSARGS) $(VSIM_USER_PLUSARGS) +srec=$<" +else + cd $(QUESTA_BUILD_DIR) && $(VSIM_BIN) $(VSIM_ARGS) -c -do "vsim -t ps $(SIM_TOP_OPT) $(VSIM_DEFAULT_PLUSARGS) $(VSIM_USER_PLUSARGS) +srec=$<; run -all; exit" +endif + +.PHONY: relink +relink: + @mkdir -p $(QUESTA_BUILD_DIR) + @ln -snf $(PULPISSIMO_ROOT)/target/sim/questasim/waves $(QUESTA_BUILD_DIR)/waves + @ln -snf $(PULPISSIMO_ROOT)/target/sim/questasim/tcl_files $(QUESTA_BUILD_DIR)/tcl_files + +## (Re)Compile PULPissimo using Questasim. +## @param VSIM_BIN=vsim The command to invoke vsim. Default: 'vsim' +## @param VSIM_ARGS='-64' Additional args to supply to vsim during tool invocation +## @param SIM_TOP='tb_pulp' The toplevel module to optimize for simulation. Default: tb_pulp +## @param USE_VIPS=0 Use the VIPs in the simulation. Default: 0 +.PHONY: build +build: $(QUESTA_BUILD_DIR)/compile.tcl $(QUESTA_BUILD_DIR)/compile_vip.tcl relink +ifeq ($(USE_VIPS), 0) + cd $(QUESTA_BUILD_DIR) && $(VSIM_BIN) $(VSIM_ARGS) -c -do 'quit -code [source compile.tcl]' +else + cd $(QUESTA_BUILD_DIR) && $(VSIM_BIN) $(VSIM_ARGS) -c -do 'quit -code [source compile_vip.tcl]' + echo "Building with VIPS" +endif + cd $(QUESTA_BUILD_DIR) && $(VSIM_BIN) $(VSIM_ARGS) -c -do 'vopt $(VOPT_ARGS) -o $(SIM_TOP_OPT) $(SIM_TOP) -work work; quit' + @echo "Finished building design $(SIM_TOP). The optimized design has been stored in a unit called '$(SIM_TOP_OPT)'." +ifneq ($(VSIM_PATH), $(PULPISSIMO_ROOT)/build/questasim) + @echo "" + @echo "To run a simulation directly with the PULP runtime or SDK \`make run\` commands execute the following:" + @echo "" + @echo " export VSIM_PATH=$(PULPISSIMO_ROOT)/build/questasim" +ifneq ($(VSIM),$(VSIM_BIN)) + @echo " export VSIM=\"$(VSIM_BIN)\"" +endif + @echo "" +endif + +## Invoke bender to generate the TCL scripts for compilation with questasim +## @param BENDER_SCRIPTS_ARGS A list of additional arguments for source file filtering supplied to bender. +## @param VLOG_ARGS="-suppress 2583" Additional flags to supply to vlog +## @param VCOM_ARGS="-suppress 2444" Additional flags to supply to vcom +scripts: $(QUESTA_BUILD_DIR)/compile.tcl + +.PHONY: clean_questasim clean +## Clean all +clean: clean_questasim +## Clean up files left to build and run simulation +clean_questasim: + rm -rf $(QUESTA_BUILD_DIR) + +# Generate the compile scripts +.PHONY: $(QUESTA_BUILD_DIR)/compile.tcl +$(QUESTA_BUILD_DIR)/compile.tcl: $(PULPISSIMO_ROOT)/Bender.lock | $(PULPISSIMO_UTILS)/bender + mkdir -p $(QUESTA_BUILD_DIR) + echo 'set ROOT [file normalize [file dirname [info script]]/../..]' > $@ + $(PULPISSIMO_UTILS)/bender script vsim $(BENDER_SCRIPTS_ARGS) --vlog-arg="$(VLOG_ARGS)" --vcom-arg="" | grep -v "set ROOT" >> $@ + +.PHONY: $(QUESTA_BUILD_DIR)/compile_vip.tcl +$(QUESTA_BUILD_DIR)/compile_vip.tcl: $(PULPISSIMO_ROOT)/Bender.lock | $(PULPISSIMO_UTILS)/bender + mkdir -p $(QUESTA_BUILD_DIR) + echo 'set ROOT [file normalize [file dirname [info script]]/../..]' > $@ + $(PULPISSIMO_UTILS)/bender script vsim $(BENDER_SCRIPTS_ARGS) $(BENDER_VIP_SCRIPT_ARGS) --vlog-arg="$(VLOG_ARGS)" --vcom-arg="" | grep -v "set ROOT" >> $@ + +# Convert the ELF binary to SREC format for simulation +$(QUESTA_BUILD_DIR)/app.s19: $(EXECUTABLE_PATH) +ifndef EXECUTABLE_PATH + $(error EXECUTABLE_PATH not provided. Please specify which ELF binary to simulate.) +endif + $(RISCV_OBJCOPY_BIN) -O srec $(EXECUTABLE_PATH) $(QUESTA_BUILD_DIR)/app.s19 + +HELP_TITLE=PULPissimo Questasim Simulation +HELP_DESCRIPTION="Invocation targets for compilation and simulation of PULPissimo usin Questasim." +include $(PULPISSIMO_ROOT)/utils/help.mk +.DEFAULT_GOAL := help diff --git a/sim/tcl_files/config/run_and_exit.tcl b/target/sim/questasim/tcl_files/config/run_and_exit.tcl similarity index 100% rename from sim/tcl_files/config/run_and_exit.tcl rename to target/sim/questasim/tcl_files/config/run_and_exit.tcl diff --git a/sim/tcl_files/config/vsim.tcl b/target/sim/questasim/tcl_files/config/vsim.tcl similarity index 99% rename from sim/tcl_files/config/vsim.tcl rename to target/sim/questasim/tcl_files/config/vsim.tcl index 5c263108..bea20f09 100644 --- a/sim/tcl_files/config/vsim.tcl +++ b/target/sim/questasim/tcl_files/config/vsim.tcl @@ -99,4 +99,4 @@ proc run_and_exit {} { } else { quit -code [examine -radix decimal sim:/tb_pulp/exit_status] } -} +} \ No newline at end of file diff --git a/sim/tcl_files/run.tcl b/target/sim/questasim/tcl_files/run.tcl old mode 100755 new mode 100644 similarity index 100% rename from sim/tcl_files/run.tcl rename to target/sim/questasim/tcl_files/run.tcl diff --git a/sim/waves/FLL.tcl b/target/sim/questasim/waves/FLL.tcl similarity index 100% rename from sim/waves/FLL.tcl rename to target/sim/questasim/waves/FLL.tcl diff --git a/sim/waves/PAD.tcl b/target/sim/questasim/waves/PAD.tcl similarity index 100% rename from sim/waves/PAD.tcl rename to target/sim/questasim/waves/PAD.tcl diff --git a/sim/waves/PULPissimo.tcl b/target/sim/questasim/waves/PULPissimo.tcl similarity index 100% rename from sim/waves/PULPissimo.tcl rename to target/sim/questasim/waves/PULPissimo.tcl diff --git a/target/sim/questasim/waves/add_instance.do b/target/sim/questasim/waves/add_instance.do new file mode 100644 index 00000000..15fd5b33 --- /dev/null +++ b/target/sim/questasim/waves/add_instance.do @@ -0,0 +1,62 @@ +package require struct::set + +proc quote {arg} { + string map {"[" "\\[" "]" "\\]"} $arg +} + +proc get_design_name {inst} { + set res [find instance $inst] + return $res + #return string range $res [string first "(" $res] [string last ")" $res] +} + +echo Usage: +echo {add_instance instance to add to wave window> } +proc add_instance {inst {max_level 2} {parent_group_args ""} {parent_clocks {}} {parent_resets {}}} { + if {$max_level == 0} { + echo "max recursion reached" + return + } + set inst_name [lindex [split $inst /] end] + echo "Adding $inst_name to wave window" + set parent_group_args [append parent_group_args " " -group " " $inst_name] + set all_signals [find signals -ports $inst/*] + set clocks [lsort -dictionary [find signals -ports $inst/*clk*]] + set resets [lsort -dictionary [find signals -ports $inst/*rst*]] + set other_ports [lsort -dictionary [struct::set difference [find signals -ports $inst/*] [struct::set union $clocks $resets]]] + set internal_signals [lsort -dictionary [find signals -internal $inst/*]] + # If there are no internal signals just add the signals with wildcard. This + # is a workaround for the issue, that Questasim's find command does not work + # at all with SV interfaces. Wildcard adding to the wave window on the other + # hand works as expected so we just do it that way. + set all_sub_instances [find instance -nodu $inst/*] + set sub_instances [lsort -dictionary [find instance -nodu $inst/i_*]] + set sub_blocks [lsort -dictionary [find blocks -nodu $inst/*]] + set interface_instances [lsort -dictionary [find instance -nodu $inst/s_*]] + set interface_ports [lsort -dictionary [struct::set difference [find instance -nodu $inst/*] [struct::set union $sub_instances $interface_instances]]] + if {[llength $all_signals] == 0 && [llength $all_sub_instances] == 0 && [llength $sub_blocks] == 0} { + echo "Detected interface instance" + catch { + eval add wave [quote $parent_group_args] [quote $parent_clocks] + eval add wave [quote $parent_group_args] [quote $parent_resets] + eval add wave [quote $parent_group_args] [quote $inst/*] + return + } + } + + catch { + eval add wave [quote $parent_group_args] [quote $clocks] + eval add wave [quote $parent_group_args] [quote $resets] + eval add wave [quote $parent_group_args] [quote $other_ports] + # echo "interface ports: $interface_ports" + } + echo "sub_instances: $interface_ports" + # echo "Interface Instances: $interface_instances" + foreach sub_inst [concat $interface_ports " " $sub_instances " " $sub_blocks " " $interface_instances] { + add_instance $sub_inst [expr {$max_level - 1}] $parent_group_args $clocks $resets + } + catch { + eval add wave [quote $parent_group_args] [quote $internal_signals] + } + return +} diff --git a/sim/waves/apb_intc.tcl b/target/sim/questasim/waves/apb_intc.tcl similarity index 100% rename from sim/waves/apb_intc.tcl rename to target/sim/questasim/waves/apb_intc.tcl diff --git a/sim/waves/apb_soc_ctrl.tcl b/target/sim/questasim/waves/apb_soc_ctrl.tcl similarity index 100% rename from sim/waves/apb_soc_ctrl.tcl rename to target/sim/questasim/waves/apb_soc_ctrl.tcl diff --git a/sim/waves/apu.tcl b/target/sim/questasim/waves/apu.tcl similarity index 100% rename from sim/waves/apu.tcl rename to target/sim/questasim/waves/apu.tcl diff --git a/sim/waves/axi_xbar.tcl b/target/sim/questasim/waves/axi_xbar.tcl similarity index 67% rename from sim/waves/axi_xbar.tcl rename to target/sim/questasim/waves/axi_xbar.tcl index 6c462897..a6866e1b 100644 --- a/sim/waves/axi_xbar.tcl +++ b/target/sim/questasim/waves/axi_xbar.tcl @@ -1,273 +1,273 @@ onerror {resume} quietly WaveActivateNextPane {} 0 -add wave -noupdate -group axi_xbar /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/clk_i -add wave -noupdate -group axi_xbar /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/rst_ni -add wave -noupdate -group axi_xbar /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/test_i -add wave -noupdate -group axi_xbar /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/addr_map_i -add wave -noupdate -group axi_xbar /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/en_default_mst_port_i -add wave -noupdate -group axi_xbar /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/default_mst_port_i -add wave -noupdate -group axi_xbar /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_reqs -add wave -noupdate -group axi_xbar /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_resps -add wave -noupdate -group axi_xbar /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_reqs -add wave -noupdate -group axi_xbar /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_resps -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/aw_id} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/aw_addr} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/aw_len} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/aw_size} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/aw_burst} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/aw_lock} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/aw_cache} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/aw_prot} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/aw_qos} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/aw_region} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/aw_atop} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/aw_user} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/aw_valid} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/aw_ready} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/w_data} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/w_strb} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/w_last} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/w_user} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/w_valid} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/w_ready} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/b_id} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/b_resp} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/b_user} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/b_valid} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/b_ready} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/ar_id} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/ar_addr} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/ar_len} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/ar_size} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/ar_burst} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/ar_lock} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/ar_cache} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/ar_prot} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/ar_qos} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/ar_region} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/ar_user} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/ar_valid} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/ar_ready} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/r_id} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/r_data} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/r_resp} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/r_last} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/r_user} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/r_valid} -add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/r_ready} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/aw_id} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/aw_addr} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/aw_len} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/aw_size} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/aw_burst} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/aw_lock} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/aw_cache} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/aw_prot} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/aw_qos} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/aw_region} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/aw_atop} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/aw_user} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/aw_valid} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/aw_ready} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/w_data} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/w_strb} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/w_last} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/w_user} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/w_valid} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/w_ready} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/b_id} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/b_resp} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/b_user} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/b_valid} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/b_ready} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/ar_id} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/ar_addr} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/ar_len} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/ar_size} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/ar_burst} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/ar_lock} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/ar_cache} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/ar_prot} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/ar_qos} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/ar_region} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/ar_user} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/ar_valid} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/ar_ready} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/r_id} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/r_data} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/r_resp} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/r_last} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/r_user} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/r_valid} -add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/r_ready} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/aw_id} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/aw_addr} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/aw_len} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/aw_size} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/aw_burst} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/aw_lock} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/aw_cache} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/aw_prot} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/aw_qos} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/aw_region} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/aw_atop} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/aw_user} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/aw_valid} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/aw_ready} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/w_data} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/w_strb} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/w_last} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/w_user} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/w_valid} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/w_ready} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/b_id} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/b_resp} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/b_user} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/b_valid} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/b_ready} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/ar_id} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/ar_addr} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/ar_len} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/ar_size} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/ar_burst} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/ar_lock} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/ar_cache} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/ar_prot} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/ar_qos} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/ar_region} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/ar_user} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/ar_valid} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/ar_ready} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/r_id} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/r_data} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/r_resp} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/r_last} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/r_user} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/r_valid} -add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/r_ready} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/aw_id} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/aw_addr} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/aw_len} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/aw_size} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/aw_burst} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/aw_lock} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/aw_cache} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/aw_prot} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/aw_qos} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/aw_region} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/aw_atop} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/aw_user} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/aw_valid} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/aw_ready} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/w_data} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/w_strb} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/w_last} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/w_user} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/w_valid} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/w_ready} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/b_id} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/b_resp} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/b_user} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/b_valid} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/b_ready} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/ar_id} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/ar_addr} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/ar_len} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/ar_size} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/ar_burst} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/ar_lock} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/ar_cache} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/ar_prot} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/ar_qos} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/ar_region} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/ar_user} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/ar_valid} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/ar_ready} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/r_id} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/r_data} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/r_resp} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/r_last} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/r_user} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/r_valid} -add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/r_ready} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/aw_id} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/aw_addr} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/aw_len} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/aw_size} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/aw_burst} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/aw_lock} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/aw_cache} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/aw_prot} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/aw_qos} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/aw_region} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/aw_atop} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/aw_user} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/aw_valid} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/aw_ready} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/w_data} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/w_strb} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/w_last} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/w_user} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/w_valid} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/w_ready} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/b_id} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/b_resp} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/b_user} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/b_valid} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/b_ready} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/ar_id} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/ar_addr} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/ar_len} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/ar_size} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/ar_burst} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/ar_lock} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/ar_cache} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/ar_prot} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/ar_qos} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/ar_region} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/ar_user} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/ar_valid} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/ar_ready} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/r_id} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/r_data} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/r_resp} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/r_last} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/r_user} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/r_valid} -add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/r_ready} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/aw_id} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/aw_addr} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/aw_len} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/aw_size} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/aw_burst} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/aw_lock} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/aw_cache} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/aw_prot} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/aw_qos} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/aw_region} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/aw_atop} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/aw_user} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/aw_valid} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/aw_ready} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/w_data} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/w_strb} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/w_last} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/w_user} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/w_valid} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/w_ready} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/b_id} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/b_resp} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/b_user} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/b_valid} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/b_ready} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/ar_id} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/ar_addr} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/ar_len} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/ar_size} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/ar_burst} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/ar_lock} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/ar_cache} -add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/ar_prot} +add wave -noupdate -group axi_xbar /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/clk_i +add wave -noupdate -group axi_xbar /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/rst_ni +add wave -noupdate -group axi_xbar /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/test_i +add wave -noupdate -group axi_xbar /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/addr_map_i +add wave -noupdate -group axi_xbar /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/en_default_mst_port_i +add wave -noupdate -group axi_xbar /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/default_mst_port_i +add wave -noupdate -group axi_xbar /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_reqs +add wave -noupdate -group axi_xbar /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_resps +add wave -noupdate -group axi_xbar /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_reqs +add wave -noupdate -group axi_xbar /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_resps +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/aw_id} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/aw_addr} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/aw_len} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/aw_size} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/aw_burst} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/aw_lock} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/aw_cache} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/aw_prot} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/aw_qos} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/aw_region} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/aw_atop} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/aw_user} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/aw_valid} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/aw_ready} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/w_data} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/w_strb} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/w_last} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/w_user} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/w_valid} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/w_ready} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/b_id} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/b_resp} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/b_user} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/b_valid} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/b_ready} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/ar_id} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/ar_addr} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/ar_len} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/ar_size} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/ar_burst} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/ar_lock} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/ar_cache} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/ar_prot} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/ar_qos} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/ar_region} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/ar_user} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/ar_valid} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/ar_ready} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/r_id} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/r_data} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/r_resp} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/r_last} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/r_user} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/r_valid} +add wave -noupdate -group axi_xbar -group slv_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[0]/r_ready} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/aw_id} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/aw_addr} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/aw_len} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/aw_size} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/aw_burst} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/aw_lock} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/aw_cache} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/aw_prot} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/aw_qos} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/aw_region} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/aw_atop} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/aw_user} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/aw_valid} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/aw_ready} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/w_data} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/w_strb} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/w_last} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/w_user} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/w_valid} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/w_ready} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/b_id} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/b_resp} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/b_user} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/b_valid} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/b_ready} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/ar_id} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/ar_addr} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/ar_len} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/ar_size} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/ar_burst} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/ar_lock} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/ar_cache} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/ar_prot} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/ar_qos} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/ar_region} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/ar_user} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/ar_valid} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/ar_ready} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/r_id} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/r_data} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/r_resp} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/r_last} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/r_user} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/r_valid} +add wave -noupdate -group axi_xbar -group slv_port1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[1]/r_ready} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/aw_id} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/aw_addr} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/aw_len} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/aw_size} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/aw_burst} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/aw_lock} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/aw_cache} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/aw_prot} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/aw_qos} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/aw_region} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/aw_atop} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/aw_user} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/aw_valid} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/aw_ready} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/w_data} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/w_strb} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/w_last} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/w_user} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/w_valid} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/w_ready} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/b_id} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/b_resp} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/b_user} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/b_valid} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/b_ready} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/ar_id} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/ar_addr} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/ar_len} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/ar_size} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/ar_burst} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/ar_lock} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/ar_cache} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/ar_prot} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/ar_qos} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/ar_region} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/ar_user} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/ar_valid} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/ar_ready} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/r_id} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/r_data} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/r_resp} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/r_last} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/r_user} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/r_valid} +add wave -noupdate -group axi_xbar -group slv_port2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[2]/r_ready} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/aw_id} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/aw_addr} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/aw_len} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/aw_size} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/aw_burst} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/aw_lock} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/aw_cache} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/aw_prot} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/aw_qos} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/aw_region} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/aw_atop} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/aw_user} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/aw_valid} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/aw_ready} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/w_data} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/w_strb} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/w_last} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/w_user} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/w_valid} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/w_ready} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/b_id} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/b_resp} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/b_user} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/b_valid} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/b_ready} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/ar_id} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/ar_addr} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/ar_len} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/ar_size} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/ar_burst} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/ar_lock} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/ar_cache} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/ar_prot} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/ar_qos} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/ar_region} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/ar_user} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/ar_valid} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/ar_ready} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/r_id} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/r_data} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/r_resp} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/r_last} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/r_user} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/r_valid} +add wave -noupdate -group axi_xbar -group slv_port3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[3]/r_ready} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/aw_id} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/aw_addr} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/aw_len} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/aw_size} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/aw_burst} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/aw_lock} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/aw_cache} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/aw_prot} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/aw_qos} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/aw_region} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/aw_atop} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/aw_user} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/aw_valid} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/aw_ready} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/w_data} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/w_strb} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/w_last} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/w_user} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/w_valid} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/w_ready} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/b_id} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/b_resp} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/b_user} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/b_valid} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/b_ready} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/ar_id} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/ar_addr} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/ar_len} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/ar_size} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/ar_burst} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/ar_lock} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/ar_cache} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/ar_prot} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/ar_qos} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/ar_region} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/ar_user} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/ar_valid} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/ar_ready} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/r_id} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/r_data} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/r_resp} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/r_last} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/r_user} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/r_valid} +add wave -noupdate -group axi_xbar -group slv_port4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/slv_ports[4]/r_ready} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/aw_id} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/aw_addr} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/aw_len} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/aw_size} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/aw_burst} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/aw_lock} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/aw_cache} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/aw_prot} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/aw_qos} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/aw_region} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/aw_atop} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/aw_user} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/aw_valid} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/aw_ready} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/w_data} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/w_strb} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/w_last} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/w_user} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/w_valid} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/w_ready} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/b_id} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/b_resp} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/b_user} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/b_valid} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/b_ready} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/ar_id} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/ar_addr} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/ar_len} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/ar_size} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/ar_burst} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/ar_lock} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/ar_cache} +add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/ar_prot} add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/ar_qos} add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/ar_region} add wave -noupdate -group axi_xbar -group mst_port0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/i_axi_xbar/mst_ports[0]/ar_user} diff --git a/sim/waves/core.tcl b/target/sim/questasim/waves/core.tcl similarity index 100% rename from sim/waves/core.tcl rename to target/sim/questasim/waves/core.tcl diff --git a/sim/waves/debug_dm.tcl b/target/sim/questasim/waves/debug_dm.tcl similarity index 100% rename from sim/waves/debug_dm.tcl rename to target/sim/questasim/waves/debug_dm.tcl diff --git a/sim/waves/dm.tcl b/target/sim/questasim/waves/dm.tcl similarity index 100% rename from sim/waves/dm.tcl rename to target/sim/questasim/waves/dm.tcl diff --git a/sim/waves/dmi_jtag.tcl b/target/sim/questasim/waves/dmi_jtag.tcl similarity index 100% rename from sim/waves/dmi_jtag.tcl rename to target/sim/questasim/waves/dmi_jtag.tcl diff --git a/sim/waves/fc.tcl b/target/sim/questasim/waves/fc.tcl similarity index 100% rename from sim/waves/fc.tcl rename to target/sim/questasim/waves/fc.tcl diff --git a/sim/waves/memories.tcl b/target/sim/questasim/waves/memories.tcl similarity index 100% rename from sim/waves/memories.tcl rename to target/sim/questasim/waves/memories.tcl diff --git a/sim/waves/pad_control.tcl b/target/sim/questasim/waves/pad_control.tcl similarity index 100% rename from sim/waves/pad_control.tcl rename to target/sim/questasim/waves/pad_control.tcl diff --git a/sim/waves/safe_domain.tcl b/target/sim/questasim/waves/safe_domain.tcl similarity index 100% rename from sim/waves/safe_domain.tcl rename to target/sim/questasim/waves/safe_domain.tcl diff --git a/sim/waves/soc_clk_gen.tcl b/target/sim/questasim/waves/soc_clk_gen.tcl similarity index 100% rename from sim/waves/soc_clk_gen.tcl rename to target/sim/questasim/waves/soc_clk_gen.tcl diff --git a/sim/waves/soc_interconnect.tcl b/target/sim/questasim/waves/soc_interconnect.tcl similarity index 64% rename from sim/waves/soc_interconnect.tcl rename to target/sim/questasim/waves/soc_interconnect.tcl index 335d41ed..b25b68ac 100644 --- a/sim/waves/soc_interconnect.tcl +++ b/target/sim/questasim/waves/soc_interconnect.tcl @@ -1,526 +1,526 @@ onerror {resume} quietly WaveActivateNextPane {} 0 -add wave -noupdate -group soc_interconnect /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/clk_i -add wave -noupdate -group soc_interconnect /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/rst_ni -add wave -noupdate -group soc_interconnect /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/test_en_i -add wave -noupdate -group soc_interconnect /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/addr_space_l2_demux -add wave -noupdate -group soc_interconnect /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/addr_space_contiguous -add wave -noupdate -group soc_interconnect /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/addr_space_axi -add wave -noupdate -group soc_interconnect /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/error_valid_d -add wave -noupdate -group soc_interconnect /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/error_valid_q -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/aw_id} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/aw_addr} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/aw_len} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/aw_size} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/aw_burst} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/aw_lock} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/aw_cache} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/aw_prot} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/aw_qos} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/aw_region} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/aw_atop} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/aw_user} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/aw_valid} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/aw_ready} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/w_data} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/w_strb} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/w_last} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/w_user} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/w_valid} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/w_ready} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/b_id} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/b_resp} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/b_user} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/b_valid} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/b_ready} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/ar_id} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/ar_addr} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/ar_len} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/ar_size} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/ar_burst} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/ar_lock} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/ar_cache} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/ar_prot} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/ar_qos} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/ar_region} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/ar_user} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/ar_valid} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/ar_ready} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/r_id} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/r_data} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/r_resp} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/r_last} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/r_user} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/r_valid} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/r_ready} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/aw_id} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/aw_addr} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/aw_len} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/aw_size} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/aw_burst} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/aw_lock} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/aw_cache} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/aw_prot} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/aw_qos} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/aw_region} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/aw_atop} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/aw_user} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/aw_valid} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/aw_ready} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/w_data} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/w_strb} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/w_last} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/w_user} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/w_valid} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/w_ready} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/b_id} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/b_resp} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/b_user} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/b_valid} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/b_ready} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/ar_id} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/ar_addr} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/ar_len} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/ar_size} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/ar_burst} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/ar_lock} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/ar_cache} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/ar_prot} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/ar_qos} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/ar_region} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/ar_user} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/ar_valid} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/ar_ready} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/r_id} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/r_data} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/r_resp} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/r_last} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/r_user} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/r_valid} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/r_ready} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/aw_id} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/aw_addr} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/aw_len} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/aw_size} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/aw_burst} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/aw_lock} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/aw_cache} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/aw_prot} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/aw_qos} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/aw_region} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/aw_atop} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/aw_user} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/aw_valid} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/aw_ready} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/w_data} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/w_strb} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/w_last} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/w_user} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/w_valid} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/w_ready} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/b_id} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/b_resp} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/b_user} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/b_valid} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/b_ready} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/ar_id} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/ar_addr} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/ar_len} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/ar_size} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/ar_burst} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/ar_lock} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/ar_cache} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/ar_prot} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/ar_qos} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/ar_region} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/ar_user} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/ar_valid} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/ar_ready} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/r_id} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/r_data} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/r_resp} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/r_last} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/r_user} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/r_valid} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/r_ready} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/aw_id} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/aw_addr} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/aw_len} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/aw_size} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/aw_burst} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/aw_lock} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/aw_cache} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/aw_prot} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/aw_qos} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/aw_region} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/aw_atop} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/aw_user} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/aw_valid} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/aw_ready} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/w_data} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/w_strb} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/w_last} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/w_user} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/w_valid} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/w_ready} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/b_id} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/b_resp} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/b_user} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/b_valid} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/b_ready} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/ar_id} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/ar_addr} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/ar_len} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/ar_size} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/ar_burst} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/ar_lock} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/ar_cache} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/ar_prot} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/ar_qos} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/ar_region} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/ar_user} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/ar_valid} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/ar_ready} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/r_id} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/r_data} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/r_resp} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/r_last} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/r_user} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/r_valid} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/r_ready} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/aw_id} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/aw_addr} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/aw_len} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/aw_size} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/aw_burst} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/aw_lock} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/aw_cache} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/aw_prot} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/aw_qos} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/aw_region} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/aw_atop} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/aw_user} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/aw_valid} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/aw_ready} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/w_data} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/w_strb} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/w_last} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/w_user} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/w_valid} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/w_ready} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/b_id} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/b_resp} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/b_user} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/b_valid} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/b_ready} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/ar_id} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/ar_addr} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/ar_len} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/ar_size} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/ar_burst} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/ar_lock} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/ar_cache} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/ar_prot} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/ar_qos} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/ar_region} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/ar_user} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/ar_valid} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/ar_ready} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/r_id} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/r_data} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/r_resp} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/r_last} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/r_user} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/r_valid} -add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/r_ready} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/aw_id} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/aw_addr} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/aw_len} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/aw_size} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/aw_burst} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/aw_lock} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/aw_cache} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/aw_prot} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/aw_qos} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/aw_region} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/aw_atop} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/aw_user} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/aw_valid} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/aw_ready} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/w_data} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/w_strb} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/w_last} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/w_user} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/w_valid} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/w_ready} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/b_id} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/b_resp} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/b_user} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/b_valid} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/b_ready} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/ar_id} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/ar_addr} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/ar_len} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/ar_size} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/ar_burst} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/ar_lock} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/ar_cache} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/ar_prot} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/ar_qos} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/ar_region} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/ar_user} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/ar_valid} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/ar_ready} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/r_id} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/r_data} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/r_resp} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/r_last} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/r_user} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/r_valid} -add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/r_ready} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/aw_id} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/aw_addr} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/aw_len} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/aw_size} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/aw_burst} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/aw_lock} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/aw_cache} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/aw_prot} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/aw_qos} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/aw_region} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/aw_atop} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/aw_user} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/aw_valid} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/aw_ready} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/w_data} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/w_strb} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/w_last} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/w_user} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/w_valid} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/w_ready} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/b_id} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/b_resp} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/b_user} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/b_valid} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/b_ready} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/ar_id} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/ar_addr} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/ar_len} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/ar_size} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/ar_burst} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/ar_lock} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/ar_cache} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/ar_prot} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/ar_qos} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/ar_region} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/ar_user} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/ar_valid} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/ar_ready} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/r_id} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/r_data} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/r_resp} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/r_last} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/r_user} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/r_valid} -add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/r_ready} -add wave -noupdate -group soc_interconnect -group contiguous_slaves0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[0]/req} -add wave -noupdate -group soc_interconnect -group contiguous_slaves0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[0]/add} -add wave -noupdate -group soc_interconnect -group contiguous_slaves0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[0]/wen} -add wave -noupdate -group soc_interconnect -group contiguous_slaves0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[0]/wdata} -add wave -noupdate -group soc_interconnect -group contiguous_slaves0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[0]/be} -add wave -noupdate -group soc_interconnect -group contiguous_slaves0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[0]/gnt} -add wave -noupdate -group soc_interconnect -group contiguous_slaves0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[0]/r_opc} -add wave -noupdate -group soc_interconnect -group contiguous_slaves0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[0]/r_rdata} -add wave -noupdate -group soc_interconnect -group contiguous_slaves0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[0]/r_valid} -add wave -noupdate -group soc_interconnect -group contiguous_slaves1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[1]/req} -add wave -noupdate -group soc_interconnect -group contiguous_slaves1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[1]/add} -add wave -noupdate -group soc_interconnect -group contiguous_slaves1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[1]/wen} -add wave -noupdate -group soc_interconnect -group contiguous_slaves1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[1]/wdata} -add wave -noupdate -group soc_interconnect -group contiguous_slaves1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[1]/be} -add wave -noupdate -group soc_interconnect -group contiguous_slaves1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[1]/gnt} -add wave -noupdate -group soc_interconnect -group contiguous_slaves1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[1]/r_opc} -add wave -noupdate -group soc_interconnect -group contiguous_slaves1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[1]/r_rdata} -add wave -noupdate -group soc_interconnect -group contiguous_slaves1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[1]/r_valid} -add wave -noupdate -group soc_interconnect -group contiguous_slaves_2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[2]/req} -add wave -noupdate -group soc_interconnect -group contiguous_slaves_2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[2]/add} -add wave -noupdate -group soc_interconnect -group contiguous_slaves_2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[2]/wen} -add wave -noupdate -group soc_interconnect -group contiguous_slaves_2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[2]/wdata} -add wave -noupdate -group soc_interconnect -group contiguous_slaves_2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[2]/be} -add wave -noupdate -group soc_interconnect -group contiguous_slaves_2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[2]/gnt} -add wave -noupdate -group soc_interconnect -group contiguous_slaves_2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[2]/r_opc} -add wave -noupdate -group soc_interconnect -group contiguous_slaves_2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[2]/r_rdata} -add wave -noupdate -group soc_interconnect -group contiguous_slaves_2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[2]/r_valid} -add wave -noupdate -group soc_interconnect -group error_slave /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/error_slave/req -add wave -noupdate -group soc_interconnect -group error_slave /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/error_slave/add -add wave -noupdate -group soc_interconnect -group error_slave /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/error_slave/wen -add wave -noupdate -group soc_interconnect -group error_slave /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/error_slave/wdata -add wave -noupdate -group soc_interconnect -group error_slave /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/error_slave/be -add wave -noupdate -group soc_interconnect -group error_slave /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/error_slave/gnt -add wave -noupdate -group soc_interconnect -group error_slave /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/error_slave/r_opc -add wave -noupdate -group soc_interconnect -group error_slave /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/error_slave/r_rdata -add wave -noupdate -group soc_interconnect -group error_slave /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/error_slave/r_valid -add wave -noupdate -group soc_interconnect -group interleaved_masters0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[0]/req} -add wave -noupdate -group soc_interconnect -group interleaved_masters0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[0]/add} -add wave -noupdate -group soc_interconnect -group interleaved_masters0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[0]/wen} -add wave -noupdate -group soc_interconnect -group interleaved_masters0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[0]/wdata} -add wave -noupdate -group soc_interconnect -group interleaved_masters0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[0]/be} -add wave -noupdate -group soc_interconnect -group interleaved_masters0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[0]/gnt} -add wave -noupdate -group soc_interconnect -group interleaved_masters0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[0]/r_opc} -add wave -noupdate -group soc_interconnect -group interleaved_masters0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[0]/r_rdata} -add wave -noupdate -group soc_interconnect -group interleaved_masters0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[0]/r_valid} -add wave -noupdate -group soc_interconnect -group interleaved_masters1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[1]/req} -add wave -noupdate -group soc_interconnect -group interleaved_masters1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[1]/add} -add wave -noupdate -group soc_interconnect -group interleaved_masters1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[1]/wen} -add wave -noupdate -group soc_interconnect -group interleaved_masters1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[1]/wdata} -add wave -noupdate -group soc_interconnect -group interleaved_masters1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[1]/be} -add wave -noupdate -group soc_interconnect -group interleaved_masters1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[1]/gnt} -add wave -noupdate -group soc_interconnect -group interleaved_masters1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[1]/r_opc} -add wave -noupdate -group soc_interconnect -group interleaved_masters1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[1]/r_rdata} -add wave -noupdate -group soc_interconnect -group interleaved_masters1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[1]/r_valid} -add wave -noupdate -group soc_interconnect -group interleaved_masters2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[2]/req} -add wave -noupdate -group soc_interconnect -group interleaved_masters2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[2]/add} -add wave -noupdate -group soc_interconnect -group interleaved_masters2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[2]/wen} -add wave -noupdate -group soc_interconnect -group interleaved_masters2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[2]/wdata} -add wave -noupdate -group soc_interconnect -group interleaved_masters2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[2]/be} -add wave -noupdate -group soc_interconnect -group interleaved_masters2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[2]/gnt} -add wave -noupdate -group soc_interconnect -group interleaved_masters2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[2]/r_opc} -add wave -noupdate -group soc_interconnect -group interleaved_masters2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[2]/r_rdata} -add wave -noupdate -group soc_interconnect -group interleaved_masters2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[2]/r_valid} -add wave -noupdate -group soc_interconnect -group interleaved_masters3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[3]/req} -add wave -noupdate -group soc_interconnect -group interleaved_masters3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[3]/add} -add wave -noupdate -group soc_interconnect -group interleaved_masters3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[3]/wen} -add wave -noupdate -group soc_interconnect -group interleaved_masters3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[3]/wdata} -add wave -noupdate -group soc_interconnect -group interleaved_masters3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[3]/be} -add wave -noupdate -group soc_interconnect -group interleaved_masters3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[3]/gnt} -add wave -noupdate -group soc_interconnect -group interleaved_masters3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[3]/r_opc} -add wave -noupdate -group soc_interconnect -group interleaved_masters3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[3]/r_rdata} -add wave -noupdate -group soc_interconnect -group interleaved_masters3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[3]/r_valid} -add wave -noupdate -group soc_interconnect -group interleaved_masters4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[4]/req} -add wave -noupdate -group soc_interconnect -group interleaved_masters4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[4]/add} -add wave -noupdate -group soc_interconnect -group interleaved_masters4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[4]/wen} -add wave -noupdate -group soc_interconnect -group interleaved_masters4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[4]/wdata} -add wave -noupdate -group soc_interconnect -group interleaved_masters4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[4]/be} -add wave -noupdate -group soc_interconnect -group interleaved_masters4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[4]/gnt} -add wave -noupdate -group soc_interconnect -group interleaved_masters4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[4]/r_opc} -add wave -noupdate -group soc_interconnect -group interleaved_masters4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[4]/r_rdata} -add wave -noupdate -group soc_interconnect -group interleaved_masters4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[4]/r_valid} -add wave -noupdate -group soc_interconnect -group interleaved_masters5 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[5]/req} -add wave -noupdate -group soc_interconnect -group interleaved_masters5 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[5]/add} -add wave -noupdate -group soc_interconnect -group interleaved_masters5 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[5]/wen} -add wave -noupdate -group soc_interconnect -group interleaved_masters5 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[5]/wdata} -add wave -noupdate -group soc_interconnect -group interleaved_masters5 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[5]/be} -add wave -noupdate -group soc_interconnect -group interleaved_masters5 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[5]/gnt} -add wave -noupdate -group soc_interconnect -group interleaved_masters5 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[5]/r_opc} -add wave -noupdate -group soc_interconnect -group interleaved_masters5 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[5]/r_rdata} -add wave -noupdate -group soc_interconnect -group interleaved_masters5 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[5]/r_valid} -add wave -noupdate -group soc_interconnect -group interleaved_masters6 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[6]/req} -add wave -noupdate -group soc_interconnect -group interleaved_masters6 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[6]/add} -add wave -noupdate -group soc_interconnect -group interleaved_masters6 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[6]/wen} -add wave -noupdate -group soc_interconnect -group interleaved_masters6 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[6]/wdata} -add wave -noupdate -group soc_interconnect -group interleaved_masters6 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[6]/be} -add wave -noupdate -group soc_interconnect -group interleaved_masters6 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[6]/gnt} -add wave -noupdate -group soc_interconnect -group interleaved_masters6 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[6]/r_opc} -add wave -noupdate -group soc_interconnect -group interleaved_masters6 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[6]/r_rdata} -add wave -noupdate -group soc_interconnect -group interleaved_masters6 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[6]/r_valid} -add wave -noupdate -group soc_interconnect -group interleaved_masters7 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[7]/req} -add wave -noupdate -group soc_interconnect -group interleaved_masters7 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[7]/add} -add wave -noupdate -group soc_interconnect -group interleaved_masters7 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[7]/wen} -add wave -noupdate -group soc_interconnect -group interleaved_masters7 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[7]/wdata} -add wave -noupdate -group soc_interconnect -group interleaved_masters7 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[7]/be} -add wave -noupdate -group soc_interconnect -group interleaved_masters7 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[7]/gnt} -add wave -noupdate -group soc_interconnect -group interleaved_masters7 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[7]/r_opc} -add wave -noupdate -group soc_interconnect -group interleaved_masters7 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[7]/r_rdata} -add wave -noupdate -group soc_interconnect -group interleaved_masters7 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[7]/r_valid} -add wave -noupdate -group soc_interconnect -group interleaved_masters8 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[8]/req} -add wave -noupdate -group soc_interconnect -group interleaved_masters8 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[8]/add} -add wave -noupdate -group soc_interconnect -group interleaved_masters8 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[8]/wen} -add wave -noupdate -group soc_interconnect -group interleaved_masters8 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[8]/wdata} -add wave -noupdate -group soc_interconnect -group interleaved_masters8 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[8]/be} -add wave -noupdate -group soc_interconnect -group interleaved_masters8 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[8]/gnt} -add wave -noupdate -group soc_interconnect -group interleaved_masters8 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[8]/r_opc} -add wave -noupdate -group soc_interconnect -group interleaved_masters8 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[8]/r_rdata} -add wave -noupdate -group soc_interconnect -group interleaved_masters8 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[8]/r_valid} -add wave -noupdate -group soc_interconnect -group interleaved_slaves0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[0]/req} -add wave -noupdate -group soc_interconnect -group interleaved_slaves0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[0]/add} -add wave -noupdate -group soc_interconnect -group interleaved_slaves0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[0]/wen} -add wave -noupdate -group soc_interconnect -group interleaved_slaves0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[0]/wdata} -add wave -noupdate -group soc_interconnect -group interleaved_slaves0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[0]/be} -add wave -noupdate -group soc_interconnect -group interleaved_slaves0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[0]/gnt} -add wave -noupdate -group soc_interconnect -group interleaved_slaves0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[0]/r_opc} -add wave -noupdate -group soc_interconnect -group interleaved_slaves0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[0]/r_rdata} -add wave -noupdate -group soc_interconnect -group interleaved_slaves0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[0]/r_valid} -add wave -noupdate -group soc_interconnect -group interleaved_slaves1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[1]/req} -add wave -noupdate -group soc_interconnect -group interleaved_slaves1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[1]/add} -add wave -noupdate -group soc_interconnect -group interleaved_slaves1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[1]/wen} -add wave -noupdate -group soc_interconnect -group interleaved_slaves1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[1]/wdata} -add wave -noupdate -group soc_interconnect -group interleaved_slaves1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[1]/be} -add wave -noupdate -group soc_interconnect -group interleaved_slaves1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[1]/gnt} -add wave -noupdate -group soc_interconnect -group interleaved_slaves1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[1]/r_opc} -add wave -noupdate -group soc_interconnect -group interleaved_slaves1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[1]/r_rdata} -add wave -noupdate -group soc_interconnect -group interleaved_slaves1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[1]/r_valid} -add wave -noupdate -group soc_interconnect -group interleaved_slaves2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[2]/req} -add wave -noupdate -group soc_interconnect -group interleaved_slaves2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[2]/add} -add wave -noupdate -group soc_interconnect -group interleaved_slaves2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[2]/wen} -add wave -noupdate -group soc_interconnect -group interleaved_slaves2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[2]/wdata} -add wave -noupdate -group soc_interconnect -group interleaved_slaves2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[2]/be} -add wave -noupdate -group soc_interconnect -group interleaved_slaves2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[2]/gnt} -add wave -noupdate -group soc_interconnect -group interleaved_slaves2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[2]/r_opc} -add wave -noupdate -group soc_interconnect -group interleaved_slaves2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[2]/r_rdata} -add wave -noupdate -group soc_interconnect -group interleaved_slaves2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[2]/r_valid} -add wave -noupdate -group soc_interconnect -group interleaved_slaves3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[3]/req} -add wave -noupdate -group soc_interconnect -group interleaved_slaves3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[3]/add} -add wave -noupdate -group soc_interconnect -group interleaved_slaves3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[3]/wen} -add wave -noupdate -group soc_interconnect -group interleaved_slaves3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[3]/wdata} -add wave -noupdate -group soc_interconnect -group interleaved_slaves3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[3]/be} -add wave -noupdate -group soc_interconnect -group interleaved_slaves3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[3]/gnt} -add wave -noupdate -group soc_interconnect -group interleaved_slaves3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[3]/r_opc} -add wave -noupdate -group soc_interconnect -group interleaved_slaves3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[3]/r_rdata} -add wave -noupdate -group soc_interconnect -group interleaved_slaves3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[3]/r_valid} -add wave -noupdate -group soc_interconnect -group master_ports0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[0]/req} -add wave -noupdate -group soc_interconnect -group master_ports0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[0]/add} -add wave -noupdate -group soc_interconnect -group master_ports0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[0]/wen} -add wave -noupdate -group soc_interconnect -group master_ports0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[0]/wdata} -add wave -noupdate -group soc_interconnect -group master_ports0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[0]/be} -add wave -noupdate -group soc_interconnect -group master_ports0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[0]/gnt} -add wave -noupdate -group soc_interconnect -group master_ports0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[0]/r_opc} -add wave -noupdate -group soc_interconnect -group master_ports0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[0]/r_rdata} -add wave -noupdate -group soc_interconnect -group master_ports0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[0]/r_valid} -add wave -noupdate -group soc_interconnect -group master_ports1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[1]/req} -add wave -noupdate -group soc_interconnect -group master_ports1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[1]/add} -add wave -noupdate -group soc_interconnect -group master_ports1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[1]/wen} -add wave -noupdate -group soc_interconnect -group master_ports1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[1]/wdata} -add wave -noupdate -group soc_interconnect -group master_ports1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[1]/be} -add wave -noupdate -group soc_interconnect -group master_ports1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[1]/gnt} -add wave -noupdate -group soc_interconnect -group master_ports1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[1]/r_opc} -add wave -noupdate -group soc_interconnect -group master_ports1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[1]/r_rdata} -add wave -noupdate -group soc_interconnect -group master_ports1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[1]/r_valid} -add wave -noupdate -group soc_interconnect -group master_ports2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[2]/req} -add wave -noupdate -group soc_interconnect -group master_ports2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[2]/add} -add wave -noupdate -group soc_interconnect -group master_ports2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[2]/wen} -add wave -noupdate -group soc_interconnect -group master_ports2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[2]/wdata} -add wave -noupdate -group soc_interconnect -group master_ports2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[2]/be} -add wave -noupdate -group soc_interconnect -group master_ports2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[2]/gnt} -add wave -noupdate -group soc_interconnect -group master_ports2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[2]/r_opc} -add wave -noupdate -group soc_interconnect -group master_ports2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[2]/r_rdata} -add wave -noupdate -group soc_interconnect -group master_ports2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[2]/r_valid} -add wave -noupdate -group soc_interconnect -group master_ports3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[3]/req} -add wave -noupdate -group soc_interconnect -group master_ports3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[3]/add} -add wave -noupdate -group soc_interconnect -group master_ports3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[3]/wen} -add wave -noupdate -group soc_interconnect -group master_ports3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[3]/wdata} -add wave -noupdate -group soc_interconnect -group master_ports3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[3]/be} -add wave -noupdate -group soc_interconnect -group master_ports3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[3]/gnt} -add wave -noupdate -group soc_interconnect -group master_ports3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[3]/r_opc} -add wave -noupdate -group soc_interconnect -group master_ports3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[3]/r_rdata} -add wave -noupdate -group soc_interconnect -group master_ports3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[3]/r_valid} -add wave -noupdate -group soc_interconnect -group master_ports4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[4]/req} -add wave -noupdate -group soc_interconnect -group master_ports4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[4]/add} -add wave -noupdate -group soc_interconnect -group master_ports4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[4]/wen} -add wave -noupdate -group soc_interconnect -group master_ports4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[4]/wdata} -add wave -noupdate -group soc_interconnect -group master_ports4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[4]/be} -add wave -noupdate -group soc_interconnect -group master_ports4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[4]/gnt} -add wave -noupdate -group soc_interconnect -group master_ports4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[4]/r_opc} -add wave -noupdate -group soc_interconnect -group master_ports4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[4]/r_rdata} -add wave -noupdate -group soc_interconnect -group master_ports4 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[4]/r_valid} +add wave -noupdate -group soc_interconnect /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/clk_i +add wave -noupdate -group soc_interconnect /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/rst_ni +add wave -noupdate -group soc_interconnect /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/test_en_i +add wave -noupdate -group soc_interconnect /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/addr_space_l2_demux +add wave -noupdate -group soc_interconnect /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/addr_space_contiguous +add wave -noupdate -group soc_interconnect /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/addr_space_axi +add wave -noupdate -group soc_interconnect /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/error_valid_d +add wave -noupdate -group soc_interconnect /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/error_valid_q +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/aw_id} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/aw_addr} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/aw_len} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/aw_size} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/aw_burst} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/aw_lock} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/aw_cache} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/aw_prot} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/aw_qos} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/aw_region} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/aw_atop} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/aw_user} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/aw_valid} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/aw_ready} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/w_data} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/w_strb} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/w_last} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/w_user} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/w_valid} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/w_ready} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/b_id} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/b_resp} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/b_user} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/b_valid} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/b_ready} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/ar_id} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/ar_addr} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/ar_len} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/ar_size} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/ar_burst} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/ar_lock} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/ar_cache} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/ar_prot} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/ar_qos} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/ar_region} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/ar_user} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/ar_valid} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/ar_ready} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/r_id} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/r_data} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/r_resp} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/r_last} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/r_user} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/r_valid} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[0]/r_ready} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/aw_id} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/aw_addr} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/aw_len} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/aw_size} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/aw_burst} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/aw_lock} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/aw_cache} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/aw_prot} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/aw_qos} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/aw_region} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/aw_atop} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/aw_user} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/aw_valid} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/aw_ready} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/w_data} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/w_strb} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/w_last} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/w_user} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/w_valid} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/w_ready} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/b_id} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/b_resp} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/b_user} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/b_valid} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/b_ready} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/ar_id} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/ar_addr} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/ar_len} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/ar_size} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/ar_burst} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/ar_lock} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/ar_cache} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/ar_prot} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/ar_qos} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/ar_region} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/ar_user} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/ar_valid} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/ar_ready} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/r_id} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/r_data} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/r_resp} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/r_last} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/r_user} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/r_valid} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[1]/r_ready} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/aw_id} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/aw_addr} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/aw_len} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/aw_size} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/aw_burst} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/aw_lock} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/aw_cache} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/aw_prot} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/aw_qos} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/aw_region} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/aw_atop} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/aw_user} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/aw_valid} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/aw_ready} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/w_data} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/w_strb} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/w_last} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/w_user} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/w_valid} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/w_ready} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/b_id} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/b_resp} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/b_user} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/b_valid} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/b_ready} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/ar_id} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/ar_addr} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/ar_len} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/ar_size} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/ar_burst} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/ar_lock} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/ar_cache} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/ar_prot} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/ar_qos} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/ar_region} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/ar_user} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/ar_valid} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/ar_ready} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/r_id} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/r_data} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/r_resp} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/r_last} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/r_user} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/r_valid} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[2]/r_ready} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/aw_id} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/aw_addr} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/aw_len} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/aw_size} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/aw_burst} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/aw_lock} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/aw_cache} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/aw_prot} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/aw_qos} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/aw_region} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/aw_atop} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/aw_user} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/aw_valid} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/aw_ready} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/w_data} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/w_strb} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/w_last} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/w_user} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/w_valid} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/w_ready} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/b_id} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/b_resp} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/b_user} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/b_valid} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/b_ready} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/ar_id} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/ar_addr} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/ar_len} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/ar_size} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/ar_burst} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/ar_lock} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/ar_cache} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/ar_prot} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/ar_qos} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/ar_region} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/ar_user} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/ar_valid} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/ar_ready} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/r_id} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/r_data} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/r_resp} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/r_last} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/r_user} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/r_valid} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[3]/r_ready} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/aw_id} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/aw_addr} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/aw_len} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/aw_size} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/aw_burst} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/aw_lock} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/aw_cache} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/aw_prot} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/aw_qos} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/aw_region} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/aw_atop} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/aw_user} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/aw_valid} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/aw_ready} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/w_data} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/w_strb} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/w_last} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/w_user} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/w_valid} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/w_ready} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/b_id} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/b_resp} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/b_user} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/b_valid} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/b_ready} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/ar_id} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/ar_addr} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/ar_len} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/ar_size} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/ar_burst} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/ar_lock} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/ar_cache} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/ar_prot} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/ar_qos} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/ar_region} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/ar_user} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/ar_valid} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/ar_ready} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/r_id} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/r_data} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/r_resp} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/r_last} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/r_user} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/r_valid} +add wave -noupdate -group soc_interconnect -group axi_bridge_2_axi_xbar4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_bridge_2_axi_xbar[4]/r_ready} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/aw_id} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/aw_addr} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/aw_len} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/aw_size} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/aw_burst} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/aw_lock} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/aw_cache} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/aw_prot} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/aw_qos} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/aw_region} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/aw_atop} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/aw_user} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/aw_valid} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/aw_ready} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/w_data} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/w_strb} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/w_last} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/w_user} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/w_valid} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/w_ready} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/b_id} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/b_resp} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/b_user} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/b_valid} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/b_ready} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/ar_id} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/ar_addr} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/ar_len} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/ar_size} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/ar_burst} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/ar_lock} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/ar_cache} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/ar_prot} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/ar_qos} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/ar_region} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/ar_user} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/ar_valid} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/ar_ready} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/r_id} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/r_data} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/r_resp} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/r_last} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/r_user} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/r_valid} +add wave -noupdate -group soc_interconnect -group axi_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[0]/r_ready} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/aw_id} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/aw_addr} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/aw_len} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/aw_size} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/aw_burst} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/aw_lock} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/aw_cache} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/aw_prot} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/aw_qos} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/aw_region} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/aw_atop} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/aw_user} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/aw_valid} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/aw_ready} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/w_data} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/w_strb} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/w_last} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/w_user} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/w_valid} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/w_ready} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/b_id} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/b_resp} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/b_user} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/b_valid} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/b_ready} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/ar_id} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/ar_addr} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/ar_len} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/ar_size} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/ar_burst} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/ar_lock} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/ar_cache} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/ar_prot} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/ar_qos} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/ar_region} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/ar_user} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/ar_valid} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/ar_ready} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/r_id} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/r_data} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/r_resp} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/r_last} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/r_user} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/r_valid} +add wave -noupdate -group soc_interconnect -group axi_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/axi_slaves[1]/r_ready} +add wave -noupdate -group soc_interconnect -group contiguous_slaves0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[0]/req} +add wave -noupdate -group soc_interconnect -group contiguous_slaves0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[0]/add} +add wave -noupdate -group soc_interconnect -group contiguous_slaves0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[0]/wen} +add wave -noupdate -group soc_interconnect -group contiguous_slaves0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[0]/wdata} +add wave -noupdate -group soc_interconnect -group contiguous_slaves0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[0]/be} +add wave -noupdate -group soc_interconnect -group contiguous_slaves0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[0]/gnt} +add wave -noupdate -group soc_interconnect -group contiguous_slaves0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[0]/r_opc} +add wave -noupdate -group soc_interconnect -group contiguous_slaves0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[0]/r_rdata} +add wave -noupdate -group soc_interconnect -group contiguous_slaves0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[0]/r_valid} +add wave -noupdate -group soc_interconnect -group contiguous_slaves1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[1]/req} +add wave -noupdate -group soc_interconnect -group contiguous_slaves1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[1]/add} +add wave -noupdate -group soc_interconnect -group contiguous_slaves1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[1]/wen} +add wave -noupdate -group soc_interconnect -group contiguous_slaves1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[1]/wdata} +add wave -noupdate -group soc_interconnect -group contiguous_slaves1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[1]/be} +add wave -noupdate -group soc_interconnect -group contiguous_slaves1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[1]/gnt} +add wave -noupdate -group soc_interconnect -group contiguous_slaves1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[1]/r_opc} +add wave -noupdate -group soc_interconnect -group contiguous_slaves1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[1]/r_rdata} +add wave -noupdate -group soc_interconnect -group contiguous_slaves1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[1]/r_valid} +add wave -noupdate -group soc_interconnect -group contiguous_slaves_2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[2]/req} +add wave -noupdate -group soc_interconnect -group contiguous_slaves_2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[2]/add} +add wave -noupdate -group soc_interconnect -group contiguous_slaves_2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[2]/wen} +add wave -noupdate -group soc_interconnect -group contiguous_slaves_2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[2]/wdata} +add wave -noupdate -group soc_interconnect -group contiguous_slaves_2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[2]/be} +add wave -noupdate -group soc_interconnect -group contiguous_slaves_2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[2]/gnt} +add wave -noupdate -group soc_interconnect -group contiguous_slaves_2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[2]/r_opc} +add wave -noupdate -group soc_interconnect -group contiguous_slaves_2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[2]/r_rdata} +add wave -noupdate -group soc_interconnect -group contiguous_slaves_2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/contiguous_slaves[2]/r_valid} +add wave -noupdate -group soc_interconnect -group error_slave /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/error_slave/req +add wave -noupdate -group soc_interconnect -group error_slave /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/error_slave/add +add wave -noupdate -group soc_interconnect -group error_slave /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/error_slave/wen +add wave -noupdate -group soc_interconnect -group error_slave /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/error_slave/wdata +add wave -noupdate -group soc_interconnect -group error_slave /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/error_slave/be +add wave -noupdate -group soc_interconnect -group error_slave /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/error_slave/gnt +add wave -noupdate -group soc_interconnect -group error_slave /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/error_slave/r_opc +add wave -noupdate -group soc_interconnect -group error_slave /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/error_slave/r_rdata +add wave -noupdate -group soc_interconnect -group error_slave /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/error_slave/r_valid +add wave -noupdate -group soc_interconnect -group interleaved_masters0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[0]/req} +add wave -noupdate -group soc_interconnect -group interleaved_masters0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[0]/add} +add wave -noupdate -group soc_interconnect -group interleaved_masters0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[0]/wen} +add wave -noupdate -group soc_interconnect -group interleaved_masters0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[0]/wdata} +add wave -noupdate -group soc_interconnect -group interleaved_masters0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[0]/be} +add wave -noupdate -group soc_interconnect -group interleaved_masters0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[0]/gnt} +add wave -noupdate -group soc_interconnect -group interleaved_masters0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[0]/r_opc} +add wave -noupdate -group soc_interconnect -group interleaved_masters0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[0]/r_rdata} +add wave -noupdate -group soc_interconnect -group interleaved_masters0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[0]/r_valid} +add wave -noupdate -group soc_interconnect -group interleaved_masters1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[1]/req} +add wave -noupdate -group soc_interconnect -group interleaved_masters1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[1]/add} +add wave -noupdate -group soc_interconnect -group interleaved_masters1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[1]/wen} +add wave -noupdate -group soc_interconnect -group interleaved_masters1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[1]/wdata} +add wave -noupdate -group soc_interconnect -group interleaved_masters1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[1]/be} +add wave -noupdate -group soc_interconnect -group interleaved_masters1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[1]/gnt} +add wave -noupdate -group soc_interconnect -group interleaved_masters1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[1]/r_opc} +add wave -noupdate -group soc_interconnect -group interleaved_masters1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[1]/r_rdata} +add wave -noupdate -group soc_interconnect -group interleaved_masters1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[1]/r_valid} +add wave -noupdate -group soc_interconnect -group interleaved_masters2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[2]/req} +add wave -noupdate -group soc_interconnect -group interleaved_masters2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[2]/add} +add wave -noupdate -group soc_interconnect -group interleaved_masters2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[2]/wen} +add wave -noupdate -group soc_interconnect -group interleaved_masters2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[2]/wdata} +add wave -noupdate -group soc_interconnect -group interleaved_masters2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[2]/be} +add wave -noupdate -group soc_interconnect -group interleaved_masters2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[2]/gnt} +add wave -noupdate -group soc_interconnect -group interleaved_masters2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[2]/r_opc} +add wave -noupdate -group soc_interconnect -group interleaved_masters2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[2]/r_rdata} +add wave -noupdate -group soc_interconnect -group interleaved_masters2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[2]/r_valid} +add wave -noupdate -group soc_interconnect -group interleaved_masters3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[3]/req} +add wave -noupdate -group soc_interconnect -group interleaved_masters3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[3]/add} +add wave -noupdate -group soc_interconnect -group interleaved_masters3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[3]/wen} +add wave -noupdate -group soc_interconnect -group interleaved_masters3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[3]/wdata} +add wave -noupdate -group soc_interconnect -group interleaved_masters3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[3]/be} +add wave -noupdate -group soc_interconnect -group interleaved_masters3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[3]/gnt} +add wave -noupdate -group soc_interconnect -group interleaved_masters3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[3]/r_opc} +add wave -noupdate -group soc_interconnect -group interleaved_masters3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[3]/r_rdata} +add wave -noupdate -group soc_interconnect -group interleaved_masters3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[3]/r_valid} +add wave -noupdate -group soc_interconnect -group interleaved_masters4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[4]/req} +add wave -noupdate -group soc_interconnect -group interleaved_masters4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[4]/add} +add wave -noupdate -group soc_interconnect -group interleaved_masters4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[4]/wen} +add wave -noupdate -group soc_interconnect -group interleaved_masters4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[4]/wdata} +add wave -noupdate -group soc_interconnect -group interleaved_masters4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[4]/be} +add wave -noupdate -group soc_interconnect -group interleaved_masters4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[4]/gnt} +add wave -noupdate -group soc_interconnect -group interleaved_masters4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[4]/r_opc} +add wave -noupdate -group soc_interconnect -group interleaved_masters4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[4]/r_rdata} +add wave -noupdate -group soc_interconnect -group interleaved_masters4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[4]/r_valid} +add wave -noupdate -group soc_interconnect -group interleaved_masters5 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[5]/req} +add wave -noupdate -group soc_interconnect -group interleaved_masters5 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[5]/add} +add wave -noupdate -group soc_interconnect -group interleaved_masters5 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[5]/wen} +add wave -noupdate -group soc_interconnect -group interleaved_masters5 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[5]/wdata} +add wave -noupdate -group soc_interconnect -group interleaved_masters5 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[5]/be} +add wave -noupdate -group soc_interconnect -group interleaved_masters5 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[5]/gnt} +add wave -noupdate -group soc_interconnect -group interleaved_masters5 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[5]/r_opc} +add wave -noupdate -group soc_interconnect -group interleaved_masters5 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[5]/r_rdata} +add wave -noupdate -group soc_interconnect -group interleaved_masters5 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[5]/r_valid} +add wave -noupdate -group soc_interconnect -group interleaved_masters6 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[6]/req} +add wave -noupdate -group soc_interconnect -group interleaved_masters6 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[6]/add} +add wave -noupdate -group soc_interconnect -group interleaved_masters6 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[6]/wen} +add wave -noupdate -group soc_interconnect -group interleaved_masters6 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[6]/wdata} +add wave -noupdate -group soc_interconnect -group interleaved_masters6 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[6]/be} +add wave -noupdate -group soc_interconnect -group interleaved_masters6 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[6]/gnt} +add wave -noupdate -group soc_interconnect -group interleaved_masters6 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[6]/r_opc} +add wave -noupdate -group soc_interconnect -group interleaved_masters6 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[6]/r_rdata} +add wave -noupdate -group soc_interconnect -group interleaved_masters6 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[6]/r_valid} +add wave -noupdate -group soc_interconnect -group interleaved_masters7 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[7]/req} +add wave -noupdate -group soc_interconnect -group interleaved_masters7 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[7]/add} +add wave -noupdate -group soc_interconnect -group interleaved_masters7 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[7]/wen} +add wave -noupdate -group soc_interconnect -group interleaved_masters7 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[7]/wdata} +add wave -noupdate -group soc_interconnect -group interleaved_masters7 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[7]/be} +add wave -noupdate -group soc_interconnect -group interleaved_masters7 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[7]/gnt} +add wave -noupdate -group soc_interconnect -group interleaved_masters7 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[7]/r_opc} +add wave -noupdate -group soc_interconnect -group interleaved_masters7 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[7]/r_rdata} +add wave -noupdate -group soc_interconnect -group interleaved_masters7 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[7]/r_valid} +add wave -noupdate -group soc_interconnect -group interleaved_masters8 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[8]/req} +add wave -noupdate -group soc_interconnect -group interleaved_masters8 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[8]/add} +add wave -noupdate -group soc_interconnect -group interleaved_masters8 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[8]/wen} +add wave -noupdate -group soc_interconnect -group interleaved_masters8 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[8]/wdata} +add wave -noupdate -group soc_interconnect -group interleaved_masters8 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[8]/be} +add wave -noupdate -group soc_interconnect -group interleaved_masters8 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[8]/gnt} +add wave -noupdate -group soc_interconnect -group interleaved_masters8 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[8]/r_opc} +add wave -noupdate -group soc_interconnect -group interleaved_masters8 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[8]/r_rdata} +add wave -noupdate -group soc_interconnect -group interleaved_masters8 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_masters[8]/r_valid} +add wave -noupdate -group soc_interconnect -group interleaved_slaves0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[0]/req} +add wave -noupdate -group soc_interconnect -group interleaved_slaves0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[0]/add} +add wave -noupdate -group soc_interconnect -group interleaved_slaves0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[0]/wen} +add wave -noupdate -group soc_interconnect -group interleaved_slaves0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[0]/wdata} +add wave -noupdate -group soc_interconnect -group interleaved_slaves0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[0]/be} +add wave -noupdate -group soc_interconnect -group interleaved_slaves0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[0]/gnt} +add wave -noupdate -group soc_interconnect -group interleaved_slaves0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[0]/r_opc} +add wave -noupdate -group soc_interconnect -group interleaved_slaves0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[0]/r_rdata} +add wave -noupdate -group soc_interconnect -group interleaved_slaves0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[0]/r_valid} +add wave -noupdate -group soc_interconnect -group interleaved_slaves1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[1]/req} +add wave -noupdate -group soc_interconnect -group interleaved_slaves1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[1]/add} +add wave -noupdate -group soc_interconnect -group interleaved_slaves1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[1]/wen} +add wave -noupdate -group soc_interconnect -group interleaved_slaves1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[1]/wdata} +add wave -noupdate -group soc_interconnect -group interleaved_slaves1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[1]/be} +add wave -noupdate -group soc_interconnect -group interleaved_slaves1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[1]/gnt} +add wave -noupdate -group soc_interconnect -group interleaved_slaves1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[1]/r_opc} +add wave -noupdate -group soc_interconnect -group interleaved_slaves1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[1]/r_rdata} +add wave -noupdate -group soc_interconnect -group interleaved_slaves1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[1]/r_valid} +add wave -noupdate -group soc_interconnect -group interleaved_slaves2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[2]/req} +add wave -noupdate -group soc_interconnect -group interleaved_slaves2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[2]/add} +add wave -noupdate -group soc_interconnect -group interleaved_slaves2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[2]/wen} +add wave -noupdate -group soc_interconnect -group interleaved_slaves2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[2]/wdata} +add wave -noupdate -group soc_interconnect -group interleaved_slaves2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[2]/be} +add wave -noupdate -group soc_interconnect -group interleaved_slaves2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[2]/gnt} +add wave -noupdate -group soc_interconnect -group interleaved_slaves2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[2]/r_opc} +add wave -noupdate -group soc_interconnect -group interleaved_slaves2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[2]/r_rdata} +add wave -noupdate -group soc_interconnect -group interleaved_slaves2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[2]/r_valid} +add wave -noupdate -group soc_interconnect -group interleaved_slaves3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[3]/req} +add wave -noupdate -group soc_interconnect -group interleaved_slaves3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[3]/add} +add wave -noupdate -group soc_interconnect -group interleaved_slaves3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[3]/wen} +add wave -noupdate -group soc_interconnect -group interleaved_slaves3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[3]/wdata} +add wave -noupdate -group soc_interconnect -group interleaved_slaves3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[3]/be} +add wave -noupdate -group soc_interconnect -group interleaved_slaves3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[3]/gnt} +add wave -noupdate -group soc_interconnect -group interleaved_slaves3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[3]/r_opc} +add wave -noupdate -group soc_interconnect -group interleaved_slaves3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[3]/r_rdata} +add wave -noupdate -group soc_interconnect -group interleaved_slaves3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/interleaved_slaves[3]/r_valid} +add wave -noupdate -group soc_interconnect -group master_ports0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[0]/req} +add wave -noupdate -group soc_interconnect -group master_ports0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[0]/add} +add wave -noupdate -group soc_interconnect -group master_ports0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[0]/wen} +add wave -noupdate -group soc_interconnect -group master_ports0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[0]/wdata} +add wave -noupdate -group soc_interconnect -group master_ports0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[0]/be} +add wave -noupdate -group soc_interconnect -group master_ports0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[0]/gnt} +add wave -noupdate -group soc_interconnect -group master_ports0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[0]/r_opc} +add wave -noupdate -group soc_interconnect -group master_ports0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[0]/r_rdata} +add wave -noupdate -group soc_interconnect -group master_ports0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[0]/r_valid} +add wave -noupdate -group soc_interconnect -group master_ports1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[1]/req} +add wave -noupdate -group soc_interconnect -group master_ports1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[1]/add} +add wave -noupdate -group soc_interconnect -group master_ports1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[1]/wen} +add wave -noupdate -group soc_interconnect -group master_ports1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[1]/wdata} +add wave -noupdate -group soc_interconnect -group master_ports1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[1]/be} +add wave -noupdate -group soc_interconnect -group master_ports1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[1]/gnt} +add wave -noupdate -group soc_interconnect -group master_ports1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[1]/r_opc} +add wave -noupdate -group soc_interconnect -group master_ports1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[1]/r_rdata} +add wave -noupdate -group soc_interconnect -group master_ports1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[1]/r_valid} +add wave -noupdate -group soc_interconnect -group master_ports2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[2]/req} +add wave -noupdate -group soc_interconnect -group master_ports2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[2]/add} +add wave -noupdate -group soc_interconnect -group master_ports2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[2]/wen} +add wave -noupdate -group soc_interconnect -group master_ports2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[2]/wdata} +add wave -noupdate -group soc_interconnect -group master_ports2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[2]/be} +add wave -noupdate -group soc_interconnect -group master_ports2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[2]/gnt} +add wave -noupdate -group soc_interconnect -group master_ports2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[2]/r_opc} +add wave -noupdate -group soc_interconnect -group master_ports2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[2]/r_rdata} +add wave -noupdate -group soc_interconnect -group master_ports2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[2]/r_valid} +add wave -noupdate -group soc_interconnect -group master_ports3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[3]/req} +add wave -noupdate -group soc_interconnect -group master_ports3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[3]/add} +add wave -noupdate -group soc_interconnect -group master_ports3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[3]/wen} +add wave -noupdate -group soc_interconnect -group master_ports3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[3]/wdata} +add wave -noupdate -group soc_interconnect -group master_ports3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[3]/be} +add wave -noupdate -group soc_interconnect -group master_ports3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[3]/gnt} +add wave -noupdate -group soc_interconnect -group master_ports3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[3]/r_opc} +add wave -noupdate -group soc_interconnect -group master_ports3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[3]/r_rdata} +add wave -noupdate -group soc_interconnect -group master_ports3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[3]/r_valid} +add wave -noupdate -group soc_interconnect -group master_ports4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[4]/req} +add wave -noupdate -group soc_interconnect -group master_ports4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[4]/add} +add wave -noupdate -group soc_interconnect -group master_ports4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[4]/wen} +add wave -noupdate -group soc_interconnect -group master_ports4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[4]/wdata} +add wave -noupdate -group soc_interconnect -group master_ports4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[4]/be} +add wave -noupdate -group soc_interconnect -group master_ports4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[4]/gnt} +add wave -noupdate -group soc_interconnect -group master_ports4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[4]/r_opc} +add wave -noupdate -group soc_interconnect -group master_ports4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[4]/r_rdata} +add wave -noupdate -group soc_interconnect -group master_ports4 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/i_soc_interconnect/master_ports[4]/r_valid} TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {52879785 ps} 0} quietly wave cursor active 1 diff --git a/sim/waves/soc_interconnect_wrap.tcl b/target/sim/questasim/waves/soc_interconnect_wrap.tcl similarity index 56% rename from sim/waves/soc_interconnect_wrap.tcl rename to target/sim/questasim/waves/soc_interconnect_wrap.tcl index 0beda975..d77240fc 100644 --- a/sim/waves/soc_interconnect_wrap.tcl +++ b/target/sim/questasim/waves/soc_interconnect_wrap.tcl @@ -1,334 +1,334 @@ onerror {resume} quietly WaveActivateNextPane {} 0 -add wave -noupdate -group soc_interconnect_wrap /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/clk_i -add wave -noupdate -group soc_interconnect_wrap /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/rst_ni -add wave -noupdate -group soc_interconnect_wrap /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/test_en_i -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/AXI_ADDR_WIDTH -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/AXI_DATA_WIDTH -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/AXI_ID_WIDTH -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/AXI_USER_WIDTH -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/AXI_STRB_WIDTH -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/aw_id -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/aw_addr -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/aw_len -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/aw_size -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/aw_burst -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/aw_lock -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/aw_cache -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/aw_prot -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/aw_qos -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/aw_region -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/aw_atop -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/aw_user -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/aw_valid -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/aw_ready -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/w_data -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/w_strb -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/w_last -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/w_user -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/w_valid -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/w_ready -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/b_id -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/b_resp -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/b_user -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/b_valid -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/b_ready -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/ar_id -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/ar_addr -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/ar_len -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/ar_size -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/ar_burst -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/ar_lock -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/ar_cache -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/ar_prot -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/ar_qos -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/ar_region -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/ar_user -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/ar_valid -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/ar_ready -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/r_id -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/r_data -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/r_resp -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/r_last -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/r_user -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/r_valid -add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_in_bus/r_ready -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/AXI_ADDR_WIDTH -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/AXI_DATA_WIDTH -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/AXI_ID_WIDTH -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/AXI_USER_WIDTH -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/AXI_STRB_WIDTH -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/aw_id -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/aw_addr -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/aw_len -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/aw_size -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/aw_burst -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/aw_lock -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/aw_cache -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/aw_prot -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/aw_qos -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/aw_region -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/aw_atop -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/aw_user -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/aw_valid -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/aw_ready -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/w_data -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/w_strb -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/w_last -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/w_user -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/w_valid -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/w_ready -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/b_id -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/b_resp -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/b_user -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/b_valid -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/b_ready -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/ar_id -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/ar_addr -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/ar_len -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/ar_size -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/ar_burst -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/ar_lock -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/ar_cache -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/ar_prot -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/ar_qos -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/ar_region -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/ar_user -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/ar_valid -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/ar_ready -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/r_id -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/r_data -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/r_resp -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/r_last -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/r_user -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/r_valid -add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_data_out_bus/r_ready -add wave -noupdate -group soc_interconnect_wrap -group boot_rom_slave /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_rom_bus/req -add wave -noupdate -group soc_interconnect_wrap -group boot_rom_slave /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_rom_bus/add -add wave -noupdate -group soc_interconnect_wrap -group boot_rom_slave /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_rom_bus/wen -add wave -noupdate -group soc_interconnect_wrap -group boot_rom_slave /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_rom_bus/wdata -add wave -noupdate -group soc_interconnect_wrap -group boot_rom_slave /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_rom_bus/be -add wave -noupdate -group soc_interconnect_wrap -group boot_rom_slave /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_rom_bus/gnt -add wave -noupdate -group soc_interconnect_wrap -group boot_rom_slave /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_rom_bus/r_opc -add wave -noupdate -group soc_interconnect_wrap -group boot_rom_slave /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_rom_bus/r_rdata -add wave -noupdate -group soc_interconnect_wrap -group boot_rom_slave /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_rom_bus/r_valid -add wave -noupdate -group soc_interconnect_wrap -group apb_peripheral_bus /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_apb_periph_bus/APB_ADDR_WIDTH -add wave -noupdate -group soc_interconnect_wrap -group apb_peripheral_bus /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_apb_periph_bus/APB_DATA_WIDTH -add wave -noupdate -group soc_interconnect_wrap -group apb_peripheral_bus /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_apb_periph_bus/paddr -add wave -noupdate -group soc_interconnect_wrap -group apb_peripheral_bus /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_apb_periph_bus/pwdata -add wave -noupdate -group soc_interconnect_wrap -group apb_peripheral_bus /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_apb_periph_bus/pwrite -add wave -noupdate -group soc_interconnect_wrap -group apb_peripheral_bus /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_apb_periph_bus/psel -add wave -noupdate -group soc_interconnect_wrap -group apb_peripheral_bus /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_apb_periph_bus/penable -add wave -noupdate -group soc_interconnect_wrap -group apb_peripheral_bus /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_apb_periph_bus/prdata -add wave -noupdate -group soc_interconnect_wrap -group apb_peripheral_bus /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_apb_periph_bus/pready -add wave -noupdate -group soc_interconnect_wrap -group apb_peripheral_bus /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_apb_periph_bus/pslverr -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[3]/req} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[3]/add} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[3]/wen} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[3]/wdata} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[3]/be} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[3]/gnt} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[3]/r_opc} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[3]/r_rdata} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[3]/r_valid} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[2]/req} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[2]/add} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[2]/wen} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[2]/wdata} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[2]/be} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[2]/gnt} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[2]/r_opc} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[2]/r_rdata} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[2]/r_valid} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[1]/req} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[1]/add} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[1]/wen} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[1]/wdata} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[1]/be} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[1]/gnt} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[1]/r_opc} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[1]/r_rdata} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[1]/r_valid} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[0]/req} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[0]/add} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[0]/wen} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[0]/wdata} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[0]/be} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[0]/gnt} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[0]/r_opc} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[0]/r_rdata} -add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_bus[0]/r_valid} -add wave -noupdate -group soc_interconnect_wrap -group private_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_pri_bus[1]/req} -add wave -noupdate -group soc_interconnect_wrap -group private_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_pri_bus[1]/add} -add wave -noupdate -group soc_interconnect_wrap -group private_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_pri_bus[1]/wen} -add wave -noupdate -group soc_interconnect_wrap -group private_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_pri_bus[1]/wdata} -add wave -noupdate -group soc_interconnect_wrap -group private_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_pri_bus[1]/be} -add wave -noupdate -group soc_interconnect_wrap -group private_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_pri_bus[1]/gnt} -add wave -noupdate -group soc_interconnect_wrap -group private_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_pri_bus[1]/r_opc} -add wave -noupdate -group soc_interconnect_wrap -group private_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_pri_bus[1]/r_rdata} -add wave -noupdate -group soc_interconnect_wrap -group private_slave0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_pri_bus[1]/r_valid} -add wave -noupdate -group soc_interconnect_wrap -group private_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_pri_bus[0]/req} -add wave -noupdate -group soc_interconnect_wrap -group private_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_pri_bus[0]/add} -add wave -noupdate -group soc_interconnect_wrap -group private_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_pri_bus[0]/wen} -add wave -noupdate -group soc_interconnect_wrap -group private_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_pri_bus[0]/wdata} -add wave -noupdate -group soc_interconnect_wrap -group private_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_pri_bus[0]/be} -add wave -noupdate -group soc_interconnect_wrap -group private_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_pri_bus[0]/gnt} -add wave -noupdate -group soc_interconnect_wrap -group private_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_pri_bus[0]/r_opc} -add wave -noupdate -group soc_interconnect_wrap -group private_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_pri_bus[0]/r_rdata} -add wave -noupdate -group soc_interconnect_wrap -group private_slave1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_mem_l2_pri_bus[0]/r_valid} -add wave -noupdate -group soc_interconnect_wrap -group tcdm_debug_master /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_debug_bus/req -add wave -noupdate -group soc_interconnect_wrap -group tcdm_debug_master /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_debug_bus/add -add wave -noupdate -group soc_interconnect_wrap -group tcdm_debug_master /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_debug_bus/wen -add wave -noupdate -group soc_interconnect_wrap -group tcdm_debug_master /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_debug_bus/wdata -add wave -noupdate -group soc_interconnect_wrap -group tcdm_debug_master /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_debug_bus/be -add wave -noupdate -group soc_interconnect_wrap -group tcdm_debug_master /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_debug_bus/gnt -add wave -noupdate -group soc_interconnect_wrap -group tcdm_debug_master /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_debug_bus/r_opc -add wave -noupdate -group soc_interconnect_wrap -group tcdm_debug_master /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_debug_bus/r_rdata -add wave -noupdate -group soc_interconnect_wrap -group tcdm_debug_master /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_debug_bus/r_valid -add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_data /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_fc_data_bus/req -add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_data /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_fc_data_bus/add -add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_data /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_fc_data_bus/wen -add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_data /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_fc_data_bus/wdata -add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_data /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_fc_data_bus/be -add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_data /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_fc_data_bus/gnt -add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_data /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_fc_data_bus/r_opc -add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_data /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_fc_data_bus/r_rdata -add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_data /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_fc_data_bus/r_valid -add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_instr /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_fc_instr_bus/req -add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_instr /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_fc_instr_bus/add -add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_instr /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_fc_instr_bus/wen -add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_instr /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_fc_instr_bus/wdata -add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_instr /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_fc_instr_bus/be -add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_instr /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_fc_instr_bus/gnt -add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_instr /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_fc_instr_bus/r_opc -add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_instr /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_fc_instr_bus/r_rdata -add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_instr /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_fc_instr_bus/r_valid -add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_rx /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_udma_rx_bus/req -add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_rx /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_udma_rx_bus/add -add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_rx /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_udma_rx_bus/wen -add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_rx /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_udma_rx_bus/wdata -add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_rx /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_udma_rx_bus/be -add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_rx /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_udma_rx_bus/gnt -add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_rx /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_udma_rx_bus/r_opc -add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_rx /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_udma_rx_bus/r_rdata -add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_rx /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_udma_rx_bus/r_valid -add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_tx /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_udma_tx_bus/req -add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_tx /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_udma_tx_bus/add -add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_tx /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_udma_tx_bus/wen -add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_tx /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_udma_tx_bus/wdata -add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_tx /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_udma_tx_bus/be -add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_tx /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_udma_tx_bus/gnt -add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_tx /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_udma_tx_bus/r_opc -add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_tx /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_udma_tx_bus/r_rdata -add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_tx /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/s_lint_udma_tx_bus/r_valid -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/AXI_ADDR_WIDTH -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/AXI_DATA_WIDTH -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/AXI_ID_WIDTH -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/AXI_USER_WIDTH -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/AXI_STRB_WIDTH -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/aw_id -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/aw_addr -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/aw_len -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/aw_size -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/aw_burst -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/aw_lock -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/aw_cache -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/aw_prot -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/aw_qos -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/aw_region -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/aw_atop -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/aw_user -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/aw_valid -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/aw_ready -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/w_data -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/w_strb -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/w_last -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/w_user -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/w_valid -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/w_ready -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/b_id -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/b_resp -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/b_user -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/b_valid -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/b_ready -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/ar_id -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/ar_addr -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/ar_len -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/ar_size -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/ar_burst -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/ar_lock -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/ar_cache -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/ar_prot -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/ar_qos -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/ar_region -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/ar_user -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/ar_valid -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/ar_ready -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/r_id -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/r_data -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/r_resp -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/r_last -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/r_user -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/r_valid -add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/r_ready -add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/AXI_ADDR_WIDTH -add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/AXI_DATA_WIDTH -add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/AXI_STRB_WIDTH -add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/aw_addr -add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/aw_prot -add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/aw_valid -add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/aw_ready -add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/w_data -add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/w_strb -add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/w_valid -add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/w_ready -add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/b_resp -add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/b_valid -add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/b_ready -add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/ar_addr -add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/ar_prot -add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/ar_valid -add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/ar_ready -add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/r_data -add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/r_resp -add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/r_valid -add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/r_ready -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[0]/req} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[0]/add} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[0]/wen} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[0]/wdata} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[0]/be} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[0]/gnt} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[0]/r_opc} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[0]/r_rdata} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect0 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[0]/r_valid} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[1]/req} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[1]/add} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[1]/wen} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[1]/wdata} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[1]/be} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[1]/gnt} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[1]/r_opc} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[1]/r_rdata} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect1 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[1]/r_valid} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[2]/req} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[2]/add} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[2]/wen} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[2]/wdata} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[2]/be} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[2]/gnt} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[2]/r_opc} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[2]/r_rdata} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect2 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[2]/r_valid} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[3]/req} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[3]/add} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[3]/wen} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[3]/wdata} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[3]/be} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[3]/gnt} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[3]/r_opc} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[3]/r_rdata} -add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect3 {/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/axi_bridge_2_interconnect[3]/r_valid} +add wave -noupdate -group soc_interconnect_wrap /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/clk_i +add wave -noupdate -group soc_interconnect_wrap /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/rst_ni +add wave -noupdate -group soc_interconnect_wrap /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/test_en_i +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/AXI_ADDR_WIDTH +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/AXI_DATA_WIDTH +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/AXI_ID_WIDTH +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/AXI_USER_WIDTH +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/AXI_STRB_WIDTH +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/aw_id +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/aw_addr +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/aw_len +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/aw_size +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/aw_burst +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/aw_lock +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/aw_cache +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/aw_prot +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/aw_qos +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/aw_region +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/aw_atop +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/aw_user +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/aw_valid +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/aw_ready +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/w_data +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/w_strb +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/w_last +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/w_user +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/w_valid +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/w_ready +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/b_id +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/b_resp +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/b_user +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/b_valid +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/b_ready +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/ar_id +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/ar_addr +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/ar_len +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/ar_size +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/ar_burst +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/ar_lock +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/ar_cache +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/ar_prot +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/ar_qos +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/ar_region +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/ar_user +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/ar_valid +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/ar_ready +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/r_id +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/r_data +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/r_resp +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/r_last +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/r_user +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/r_valid +add wave -noupdate -group soc_interconnect_wrap -group axi_master_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_in_bus/r_ready +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/AXI_ADDR_WIDTH +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/AXI_DATA_WIDTH +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/AXI_ID_WIDTH +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/AXI_USER_WIDTH +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/AXI_STRB_WIDTH +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/aw_id +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/aw_addr +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/aw_len +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/aw_size +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/aw_burst +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/aw_lock +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/aw_cache +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/aw_prot +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/aw_qos +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/aw_region +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/aw_atop +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/aw_user +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/aw_valid +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/aw_ready +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/w_data +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/w_strb +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/w_last +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/w_user +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/w_valid +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/w_ready +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/b_id +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/b_resp +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/b_user +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/b_valid +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/b_ready +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/ar_id +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/ar_addr +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/ar_len +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/ar_size +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/ar_burst +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/ar_lock +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/ar_cache +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/ar_prot +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/ar_qos +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/ar_region +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/ar_user +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/ar_valid +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/ar_ready +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/r_id +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/r_data +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/r_resp +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/r_last +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/r_user +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/r_valid +add wave -noupdate -group soc_interconnect_wrap -group axi_slave_plug /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_data_out_bus/r_ready +add wave -noupdate -group soc_interconnect_wrap -group boot_rom_slave /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_rom_bus/req +add wave -noupdate -group soc_interconnect_wrap -group boot_rom_slave /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_rom_bus/add +add wave -noupdate -group soc_interconnect_wrap -group boot_rom_slave /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_rom_bus/wen +add wave -noupdate -group soc_interconnect_wrap -group boot_rom_slave /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_rom_bus/wdata +add wave -noupdate -group soc_interconnect_wrap -group boot_rom_slave /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_rom_bus/be +add wave -noupdate -group soc_interconnect_wrap -group boot_rom_slave /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_rom_bus/gnt +add wave -noupdate -group soc_interconnect_wrap -group boot_rom_slave /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_rom_bus/r_opc +add wave -noupdate -group soc_interconnect_wrap -group boot_rom_slave /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_rom_bus/r_rdata +add wave -noupdate -group soc_interconnect_wrap -group boot_rom_slave /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_rom_bus/r_valid +add wave -noupdate -group soc_interconnect_wrap -group apb_peripheral_bus /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_apb_periph_bus/APB_ADDR_WIDTH +add wave -noupdate -group soc_interconnect_wrap -group apb_peripheral_bus /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_apb_periph_bus/APB_DATA_WIDTH +add wave -noupdate -group soc_interconnect_wrap -group apb_peripheral_bus /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_apb_periph_bus/paddr +add wave -noupdate -group soc_interconnect_wrap -group apb_peripheral_bus /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_apb_periph_bus/pwdata +add wave -noupdate -group soc_interconnect_wrap -group apb_peripheral_bus /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_apb_periph_bus/pwrite +add wave -noupdate -group soc_interconnect_wrap -group apb_peripheral_bus /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_apb_periph_bus/psel +add wave -noupdate -group soc_interconnect_wrap -group apb_peripheral_bus /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_apb_periph_bus/penable +add wave -noupdate -group soc_interconnect_wrap -group apb_peripheral_bus /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_apb_periph_bus/prdata +add wave -noupdate -group soc_interconnect_wrap -group apb_peripheral_bus /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_apb_periph_bus/pready +add wave -noupdate -group soc_interconnect_wrap -group apb_peripheral_bus /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_apb_periph_bus/pslverr +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[3]/req} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[3]/add} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[3]/wen} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[3]/wdata} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[3]/be} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[3]/gnt} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[3]/r_opc} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[3]/r_rdata} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[3]/r_valid} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[2]/req} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[2]/add} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[2]/wen} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[2]/wdata} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[2]/be} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[2]/gnt} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[2]/r_opc} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[2]/r_rdata} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[2]/r_valid} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[1]/req} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[1]/add} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[1]/wen} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[1]/wdata} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[1]/be} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[1]/gnt} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[1]/r_opc} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[1]/r_rdata} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[1]/r_valid} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[0]/req} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[0]/add} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[0]/wen} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[0]/wdata} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[0]/be} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[0]/gnt} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[0]/r_opc} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[0]/r_rdata} +add wave -noupdate -group soc_interconnect_wrap -group interleaved_slave3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_bus[0]/r_valid} +add wave -noupdate -group soc_interconnect_wrap -group private_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_pri_bus[1]/req} +add wave -noupdate -group soc_interconnect_wrap -group private_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_pri_bus[1]/add} +add wave -noupdate -group soc_interconnect_wrap -group private_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_pri_bus[1]/wen} +add wave -noupdate -group soc_interconnect_wrap -group private_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_pri_bus[1]/wdata} +add wave -noupdate -group soc_interconnect_wrap -group private_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_pri_bus[1]/be} +add wave -noupdate -group soc_interconnect_wrap -group private_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_pri_bus[1]/gnt} +add wave -noupdate -group soc_interconnect_wrap -group private_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_pri_bus[1]/r_opc} +add wave -noupdate -group soc_interconnect_wrap -group private_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_pri_bus[1]/r_rdata} +add wave -noupdate -group soc_interconnect_wrap -group private_slave0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_pri_bus[1]/r_valid} +add wave -noupdate -group soc_interconnect_wrap -group private_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_pri_bus[0]/req} +add wave -noupdate -group soc_interconnect_wrap -group private_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_pri_bus[0]/add} +add wave -noupdate -group soc_interconnect_wrap -group private_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_pri_bus[0]/wen} +add wave -noupdate -group soc_interconnect_wrap -group private_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_pri_bus[0]/wdata} +add wave -noupdate -group soc_interconnect_wrap -group private_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_pri_bus[0]/be} +add wave -noupdate -group soc_interconnect_wrap -group private_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_pri_bus[0]/gnt} +add wave -noupdate -group soc_interconnect_wrap -group private_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_pri_bus[0]/r_opc} +add wave -noupdate -group soc_interconnect_wrap -group private_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_pri_bus[0]/r_rdata} +add wave -noupdate -group soc_interconnect_wrap -group private_slave1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_mem_l2_pri_bus[0]/r_valid} +add wave -noupdate -group soc_interconnect_wrap -group tcdm_debug_master /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_debug_bus/req +add wave -noupdate -group soc_interconnect_wrap -group tcdm_debug_master /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_debug_bus/add +add wave -noupdate -group soc_interconnect_wrap -group tcdm_debug_master /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_debug_bus/wen +add wave -noupdate -group soc_interconnect_wrap -group tcdm_debug_master /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_debug_bus/wdata +add wave -noupdate -group soc_interconnect_wrap -group tcdm_debug_master /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_debug_bus/be +add wave -noupdate -group soc_interconnect_wrap -group tcdm_debug_master /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_debug_bus/gnt +add wave -noupdate -group soc_interconnect_wrap -group tcdm_debug_master /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_debug_bus/r_opc +add wave -noupdate -group soc_interconnect_wrap -group tcdm_debug_master /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_debug_bus/r_rdata +add wave -noupdate -group soc_interconnect_wrap -group tcdm_debug_master /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_debug_bus/r_valid +add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_data /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_fc_data_bus/req +add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_data /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_fc_data_bus/add +add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_data /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_fc_data_bus/wen +add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_data /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_fc_data_bus/wdata +add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_data /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_fc_data_bus/be +add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_data /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_fc_data_bus/gnt +add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_data /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_fc_data_bus/r_opc +add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_data /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_fc_data_bus/r_rdata +add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_data /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_fc_data_bus/r_valid +add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_instr /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_fc_instr_bus/req +add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_instr /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_fc_instr_bus/add +add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_instr /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_fc_instr_bus/wen +add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_instr /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_fc_instr_bus/wdata +add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_instr /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_fc_instr_bus/be +add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_instr /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_fc_instr_bus/gnt +add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_instr /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_fc_instr_bus/r_opc +add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_instr /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_fc_instr_bus/r_rdata +add wave -noupdate -group soc_interconnect_wrap -group tcdm_fc_instr /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_fc_instr_bus/r_valid +add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_rx /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_udma_rx_bus/req +add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_rx /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_udma_rx_bus/add +add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_rx /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_udma_rx_bus/wen +add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_rx /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_udma_rx_bus/wdata +add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_rx /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_udma_rx_bus/be +add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_rx /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_udma_rx_bus/gnt +add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_rx /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_udma_rx_bus/r_opc +add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_rx /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_udma_rx_bus/r_rdata +add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_rx /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_udma_rx_bus/r_valid +add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_tx /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_udma_tx_bus/req +add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_tx /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_udma_tx_bus/add +add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_tx /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_udma_tx_bus/wen +add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_tx /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_udma_tx_bus/wdata +add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_tx /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_udma_tx_bus/be +add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_tx /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_udma_tx_bus/gnt +add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_tx /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_udma_tx_bus/r_opc +add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_tx /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_udma_tx_bus/r_rdata +add wave -noupdate -group soc_interconnect_wrap -group tcdm_udma_tx /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/s_lint_udma_tx_bus/r_valid +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/AXI_ADDR_WIDTH +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/AXI_DATA_WIDTH +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/AXI_ID_WIDTH +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/AXI_USER_WIDTH +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/AXI_STRB_WIDTH +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/aw_id +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/aw_addr +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/aw_len +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/aw_size +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/aw_burst +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/aw_lock +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/aw_cache +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/aw_prot +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/aw_qos +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/aw_region +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/aw_atop +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/aw_user +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/aw_valid +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/aw_ready +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/w_data +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/w_strb +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/w_last +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/w_user +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/w_valid +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/w_ready +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/b_id +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/b_resp +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/b_user +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/b_valid +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/b_ready +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/ar_id +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/ar_addr +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/ar_len +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/ar_size +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/ar_burst +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/ar_lock +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/ar_cache +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/ar_prot +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/ar_qos +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/ar_region +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/ar_user +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/ar_valid +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/ar_ready +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/r_id +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/r_data +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/r_resp +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/r_last +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/r_user +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/r_valid +add wave -noupdate -group soc_interconnect_wrap -group axi_to_axi_lite_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_to_axi_lite_bridge/r_ready +add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/AXI_ADDR_WIDTH +add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/AXI_DATA_WIDTH +add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/AXI_STRB_WIDTH +add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/aw_addr +add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/aw_prot +add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/aw_valid +add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/aw_ready +add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/w_data +add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/w_strb +add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/w_valid +add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/w_ready +add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/b_resp +add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/b_valid +add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/b_ready +add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/ar_addr +add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/ar_prot +add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/ar_valid +add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/ar_ready +add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/r_data +add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/r_resp +add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/r_valid +add wave -noupdate -group soc_interconnect_wrap -group axi_lite_to_apb_bridge /tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_lite_to_apb_bridge/r_ready +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[0]/req} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[0]/add} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[0]/wen} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[0]/wdata} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[0]/be} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[0]/gnt} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[0]/r_opc} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[0]/r_rdata} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect0 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[0]/r_valid} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[1]/req} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[1]/add} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[1]/wen} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[1]/wdata} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[1]/be} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[1]/gnt} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[1]/r_opc} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[1]/r_rdata} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect1 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[1]/r_valid} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[2]/req} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[2]/add} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[2]/wen} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[2]/wdata} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[2]/be} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[2]/gnt} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[2]/r_opc} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[2]/r_rdata} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect2 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[2]/r_valid} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[3]/req} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[3]/add} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[3]/wen} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[3]/wdata} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[3]/be} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[3]/gnt} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[3]/r_opc} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[3]/r_rdata} +add wave -noupdate -group soc_interconnect_wrap -group axi_bridge_2_interconnect3 {/tb_pulp/i_dut/i_soc_domain/i_pulp_soc/i_soc_interconnect_wrap/axi_bridge_2_interconnect[3]/r_valid} TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {0 ps} 0} quietly wave cursor active 0 diff --git a/sim/waves/software.tcl b/target/sim/questasim/waves/software.tcl similarity index 100% rename from sim/waves/software.tcl rename to target/sim/questasim/waves/software.tcl diff --git a/sim/waves/tb.tcl b/target/sim/questasim/waves/tb.tcl similarity index 100% rename from sim/waves/tb.tcl rename to target/sim/questasim/waves/tb.tcl diff --git a/sim/waves/uart_tb.tcl b/target/sim/questasim/waves/uart_tb.tcl similarity index 100% rename from sim/waves/uart_tb.tcl rename to target/sim/questasim/waves/uart_tb.tcl diff --git a/sim/waves/udma_ss.tcl b/target/sim/questasim/waves/udma_ss.tcl similarity index 100% rename from sim/waves/udma_ss.tcl rename to target/sim/questasim/waves/udma_ss.tcl diff --git a/sim/waves/ulpsoc.tcl b/target/sim/questasim/waves/ulpsoc.tcl similarity index 100% rename from sim/waves/ulpsoc.tcl rename to target/sim/questasim/waves/ulpsoc.tcl diff --git a/rtl/tb/README.md b/target/sim/tb/README.md similarity index 100% rename from rtl/tb/README.md rename to target/sim/tb/README.md diff --git a/rtl/tb/pulpissimo_compliance_test.cfg b/target/sim/tb/openocd_configs/pulpissimo_compliance_test.cfg similarity index 100% rename from rtl/tb/pulpissimo_compliance_test.cfg rename to target/sim/tb/openocd_configs/pulpissimo_compliance_test.cfg diff --git a/rtl/tb/pulpissimo_debug.cfg b/target/sim/tb/openocd_configs/pulpissimo_debug.cfg similarity index 100% rename from rtl/tb/pulpissimo_debug.cfg rename to target/sim/tb/openocd_configs/pulpissimo_debug.cfg diff --git a/rtl/tb/SimDTM.sv b/target/sim/tb/tb_lib/SimDTM.sv similarity index 100% rename from rtl/tb/SimDTM.sv rename to target/sim/tb/tb_lib/SimDTM.sv diff --git a/rtl/tb/SimJTAG.sv b/target/sim/tb/tb_lib/SimJTAG.sv similarity index 100% rename from rtl/tb/SimJTAG.sv rename to target/sim/tb/tb_lib/SimJTAG.sv diff --git a/rtl/tb/jtag_pkg.sv b/target/sim/tb/tb_lib/jtag_pkg.sv similarity index 100% rename from rtl/tb/jtag_pkg.sv rename to target/sim/tb/tb_lib/jtag_pkg.sv diff --git a/rtl/tb/pulp_tap_pkg.sv b/target/sim/tb/tb_lib/pulp_tap_pkg.sv similarity index 100% rename from rtl/tb/pulp_tap_pkg.sv rename to target/sim/tb/tb_lib/pulp_tap_pkg.sv diff --git a/rtl/tb/remote_bitbang/.gitignore b/target/sim/tb/tb_lib/remote_bitbang/.gitignore similarity index 100% rename from rtl/tb/remote_bitbang/.gitignore rename to target/sim/tb/tb_lib/remote_bitbang/.gitignore diff --git a/rtl/tb/remote_bitbang/LICENSE.Berkeley b/target/sim/tb/tb_lib/remote_bitbang/LICENSE.Berkeley similarity index 100% rename from rtl/tb/remote_bitbang/LICENSE.Berkeley rename to target/sim/tb/tb_lib/remote_bitbang/LICENSE.Berkeley diff --git a/rtl/tb/remote_bitbang/LICENSE.SiFive b/target/sim/tb/tb_lib/remote_bitbang/LICENSE.SiFive similarity index 100% rename from rtl/tb/remote_bitbang/LICENSE.SiFive rename to target/sim/tb/tb_lib/remote_bitbang/LICENSE.SiFive diff --git a/rtl/tb/remote_bitbang/Makefile b/target/sim/tb/tb_lib/remote_bitbang/Makefile similarity index 100% rename from rtl/tb/remote_bitbang/Makefile rename to target/sim/tb/tb_lib/remote_bitbang/Makefile diff --git a/rtl/tb/remote_bitbang/rbs_test.c b/target/sim/tb/tb_lib/remote_bitbang/rbs_test.c similarity index 100% rename from rtl/tb/remote_bitbang/rbs_test.c rename to target/sim/tb/tb_lib/remote_bitbang/rbs_test.c diff --git a/rtl/tb/remote_bitbang/remote_bitbang.c b/target/sim/tb/tb_lib/remote_bitbang/remote_bitbang.c similarity index 100% rename from rtl/tb/remote_bitbang/remote_bitbang.c rename to target/sim/tb/tb_lib/remote_bitbang/remote_bitbang.c diff --git a/rtl/tb/remote_bitbang/remote_bitbang.h b/target/sim/tb/tb_lib/remote_bitbang/remote_bitbang.h similarity index 100% rename from rtl/tb/remote_bitbang/remote_bitbang.h rename to target/sim/tb/tb_lib/remote_bitbang/remote_bitbang.h diff --git a/rtl/tb/remote_bitbang/sim_jtag.c b/target/sim/tb/tb_lib/remote_bitbang/sim_jtag.c similarity index 100% rename from rtl/tb/remote_bitbang/sim_jtag.c rename to target/sim/tb/tb_lib/remote_bitbang/sim_jtag.c diff --git a/rtl/tb/remote_bitbang/sim_jtag.h b/target/sim/tb/tb_lib/remote_bitbang/sim_jtag.h similarity index 100% rename from rtl/tb/remote_bitbang/sim_jtag.h rename to target/sim/tb/tb_lib/remote_bitbang/sim_jtag.h diff --git a/rtl/tb/riscv_pkg.sv b/target/sim/tb/tb_lib/riscv_pkg.sv similarity index 100% rename from rtl/tb/riscv_pkg.sv rename to target/sim/tb/tb_lib/riscv_pkg.sv diff --git a/rtl/tb/srec/min.srec b/target/sim/tb/tb_lib/srec/min.srec similarity index 100% rename from rtl/tb/srec/min.srec rename to target/sim/tb/tb_lib/srec/min.srec diff --git a/rtl/tb/srec/srec.sv b/target/sim/tb/tb_lib/srec/srec.sv similarity index 100% rename from rtl/tb/srec/srec.sv rename to target/sim/tb/tb_lib/srec/srec.sv diff --git a/rtl/tb/srec/srec_pkg.sv b/target/sim/tb/tb_lib/srec/srec_pkg.sv similarity index 100% rename from rtl/tb/srec/srec_pkg.sv rename to target/sim/tb/tb_lib/srec/srec_pkg.sv diff --git a/rtl/tb/tb_clk_gen.sv b/target/sim/tb/tb_lib/tb_clk_gen.sv similarity index 92% rename from rtl/tb/tb_clk_gen.sv rename to target/sim/tb/tb_lib/tb_clk_gen.sv index 39755e28..97ea624e 100644 --- a/rtl/tb/tb_clk_gen.sv +++ b/target/sim/tb/tb_lib/tb_clk_gen.sv @@ -15,10 +15,12 @@ */ module tb_clk_gen #( - parameter CLK_PERIOD = 1.0 + parameter realtime CLK_PERIOD = 1.0ns ) ( output logic clk_o ); + timeunit 1ns; + timeprecision 1ps; initial begin diff --git a/rtl/tb/tb_pulp.sv b/target/sim/tb/tb_pulp.sv similarity index 82% rename from rtl/tb/tb_pulp.sv rename to target/sim/tb/tb_pulp.sv index b30d99c4..ebad1770 100644 --- a/rtl/tb/tb_pulp.sv +++ b/target/sim/tb/tb_pulp.sv @@ -17,6 +17,8 @@ module tb_pulp; import srec_pkg::*; + timeunit 1ns; + timeprecision 100ps; parameter CONFIG_FILE = "NONE"; @@ -35,7 +37,7 @@ module tb_pulp; parameter SIM_STDOUT = 1; // period of the external reference clock (32.769kHz) - parameter REF_CLK_PERIOD = 30517ns; + parameter realtime REF_CLK_PERIOD = 30517ns; // UART baud rate in bps parameter BAUDRATE = 115200; @@ -66,6 +68,10 @@ module tb_pulp; localparam logic [1:0] SPI_QUAD_TX = 2'b01; localparam logic [1:0] SPI_QUAD_RX = 2'b10; + + // Check the README on how to modify the pad count + localparam IO_PAD_COUNT = gpio_reg_pkg::GPIOCount; + // simulation variables & flags string bootmode; logic uart_tb_rx_en = 1'b0; @@ -95,25 +101,28 @@ module tb_pulp; logic s_clk_ref; wire w_clk_ref; + wire w_clk_byp_en; + assign w_clk_byp_en = 1'b0; - tri w_spi_master_sdio0; - tri w_spi_master_sdio1; - tri w_spi_master_sdio2; - tri w_spi_master_sdio3; - tri w_spi_master_csn0; - tri w_spi_master_csn1; - tri w_spi_master_sck; + wire [IO_PAD_COUNT-1:0] w_pad_io; + wire w_spi_master_sdio0; + wire w_spi_master_sdio1; + wire w_spi_master_sdio2; + wire w_spi_master_sdio3; + wire w_spi_master_csn0; + wire w_spi_master_csn1; + wire w_spi_master_sck; - tri w_sdio_data0; + wire w_sdio_data0; wire w_i2c0_scl; wire w_i2c0_sda; - tri w_i2c1_scl; - tri w_i2c1_sda; + wire w_i2c1_scl; + wire w_i2c1_sda; - tri w_uart_rx; - tri w_uart_tx; + wire w_uart_rx; + wire w_uart_tx; wire w_cam_pclk; wire [7:0] w_cam_data; @@ -131,6 +140,25 @@ module tb_pulp; wire w_i2s_ws; wire [7:0] w_i2s_data; + // HyperBus/Flash + wire [1:0] w_pad_hyper_csn; + wire w_pad_hyper_reset_n; + wire w_pad_hyper_ck; + wire w_pad_hyper_ckn; + wire [7:0] w_pad_hyper_dq; + wire w_pad_hyper_rwds; + + // HyperBus + logic s_hyper_ck; + logic s_hyper_ckn; + logic [1:0] s_hyper_csn; + logic s_hyper_reset_n; + logic s_hyper_rwds; + logic [7:0] s_hyper_dq_from_chip; + logic [7:0] s_hyper_dq_to_chip = '0; + logic [7:0] s_hyper_dq_tx_en = '0; + + wire w_trstn; wire w_tck; wire w_tdi; @@ -299,6 +327,14 @@ module tb_pulp; assign w_bridge_tdo = tmp_bridge_tdo; assign sim_jtag_tdo = tmp_tdo; + // HyperBus (Not used at this point) + assign s_hyper_ck = w_pad_hyper_ck; + assign s_hyper_ckn = w_pad_hyper_ckn; + for (genvar i = 0; i < 8; i++) begin: gen_assign_hyper_dq_wires + assign s_hyper_dq_from_chip[i] = w_pad_hyper_dq[i]; + assign w_pad_hyper_dq[i] = s_hyper_dq_tx_en[i]? s_hyper_dq_to_chip: 1'bz; + end + if (CONFIG_FILE == "NONE") begin assign w_uart_tx = w_uart_rx; @@ -455,63 +491,72 @@ module tb_pulp; // PULPissimo chip (design under test) pulpissimo #( - .CORE_TYPE(CORE_TYPE), - .USE_FPU (USE_FPU), - .USE_ZFINX (USE_ZFINX), - .USE_HWPE (0), - .SIM_STDOUT (SIM_STDOUT) + .CORE_TYPE ( CORE_TYPE ), + .USE_FPU ( USE_FPU ), + .USE_ZFINX ( USE_ZFINX ), + .USE_HWPE ( 1'b0 ), //TODO Re-expose once debugged why it is not working + .SIM_STDOUT(SIM_STDOUT) ) i_dut ( - .pad_spim_sdio0(w_spi_master_sdio0), - .pad_spim_sdio1(w_spi_master_sdio1), - .pad_spim_sdio2(w_spi_master_sdio2), - .pad_spim_sdio3(w_spi_master_sdio3), - .pad_spim_csn0 (w_spi_master_csn0), - .pad_spim_csn1 (w_spi_master_csn1), - .pad_spim_sck (w_spi_master_sck), - - .pad_uart_rx(w_uart_tx), - .pad_uart_tx(w_uart_rx), - - .pad_cam_pclk (w_cam_pclk), - .pad_cam_hsync(w_cam_hsync), - .pad_cam_data0(w_cam_data[0]), - .pad_cam_data1(w_cam_data[1]), - .pad_cam_data2(w_cam_data[2]), - .pad_cam_data3(w_cam_data[3]), - .pad_cam_data4(w_cam_data[4]), - .pad_cam_data5(w_cam_data[5]), - .pad_cam_data6(w_cam_data[6]), - .pad_cam_data7(w_cam_data[7]), - .pad_cam_vsync(w_cam_vsync), - - .pad_sdio_clk (), - .pad_sdio_cmd (), - .pad_sdio_data0(w_sdio_data0), - .pad_sdio_data1(), - .pad_sdio_data2(), - .pad_sdio_data3(), - - .pad_i2c0_sda(w_i2c0_sda), - .pad_i2c0_scl(w_i2c0_scl), - - .pad_i2s0_sck(w_i2s0_sck), - .pad_i2s0_ws (w_i2s0_ws), - .pad_i2s0_sdi(w_i2s0_sdi), - .pad_i2s1_sdi(w_i2s1_sdi), - - .pad_reset_n (w_rst_n), - .pad_bootsel0(w_bootsel[0]), - .pad_bootsel1(w_bootsel[1]), - - .pad_jtag_tck (w_tck), - .pad_jtag_tdi (w_tdi), - .pad_jtag_tdo (w_tdo), - .pad_jtag_tms (w_tms), - .pad_jtag_trst(w_trstn), - - .pad_xtal_in(w_clk_ref) + .pad_ref_clk ( w_clk_ref ), + .pad_reset_n ( w_rst_n ), + .pad_clk_byp_en ( w_clk_byp_en ), + .pad_bootsel0 ( w_bootsel[0] ), + .pad_bootsel1 ( w_bootsel[1] ), + .pad_jtag_tck ( w_tck ), + .pad_jtag_tdi ( w_tdi ), + .pad_jtag_tdo ( w_tdo ), + .pad_jtag_tms ( w_tms ), + .pad_jtag_trstn ( w_trstn ), + .pad_hyper_csn ( w_pad_hyper_csn ), + .pad_hyper_reset_n ( w_pad_hyper_reset_n ), + .pad_hyper_ck ( w_pad_hyper_ck ), + .pad_hyper_ckn ( w_pad_hyper_ckn ), + .pad_hyper_dq ( w_pad_hyper_dq ), + .pad_hyper_rwds ( w_pad_hyper_rwds ), + .pad_io ( w_pad_io ) ); + // UART pads as assigned by default in bootrom's io mux config routine. User + // programs need to configure this themselves. + alias w_pad_io[0] = w_uart_rx; + alias w_pad_io[1] = w_uart_tx; + + // SPI pads as assigned by default in bootrom's io mux config routine. User + // programs need to configure this themselves. + alias w_pad_io[2] = w_spi_master_sck; + alias w_pad_io[3] = w_spi_master_csn0; + alias w_pad_io[4] = w_spi_master_sdio0; + alias w_pad_io[5] = w_spi_master_sdio1; + alias w_pad_io[6] = w_spi_master_sdio2; + alias w_pad_io[7] = w_spi_master_sdio3; + alias w_pad_io[8] = w_spi_master_csn1; + + // CPI Pads + alias w_pad_io[9] = w_cam_pclk; + alias w_pad_io[10] = w_cam_hsync; + alias w_pad_io[11] = w_cam_data[0]; + alias w_pad_io[12] = w_cam_data[1]; + alias w_pad_io[13] = w_cam_data[2]; + alias w_pad_io[14] = w_cam_data[3]; + alias w_pad_io[15] = w_cam_data[4]; + alias w_pad_io[16] = w_cam_data[5]; + alias w_pad_io[17] = w_cam_data[6]; + alias w_pad_io[18] = w_cam_data[7]; + alias w_pad_io[19] = w_cam_vsync; + + // I2C + alias w_pad_io[20] = w_i2c0_sda; + alias w_pad_io[21] = w_i2c0_scl; + + // GPIO 22 + alias w_pad_io[22] = w_sdio_data0; + + // I2S + alias w_pad_io[23] = w_i2s0_sck; + alias w_pad_io[24] = w_i2s0_ws; + alias w_pad_io[25] = w_i2s0_sdi; + alias w_pad_io[26] = w_i2s1_sdi; + tb_clk_gen #( .CLK_PERIOD(REF_CLK_PERIOD) ) i_ref_clk_gen ( @@ -607,7 +652,7 @@ module tb_pulp; // read in the stimuli vectors == address_value // we support two formats: - // + // // 1. stim.txt where each text line is 96 bits encoded in ascii. The // first 32 bits are the address the remaining 64 bits the data payload // 2. *.srec. Srecords is a standardized format to represent binary data @@ -798,23 +843,23 @@ module tb_pulp; logic more_stim; static logic [95:0] stim_entry; more_stim = 1'b1; - $info("Preloading L2 with stimuli through direct access."); + $display("[TB] %t: Preloading L2 with stimuli through direct access.", $realtime); while (more_stim == 1'b1) begin - @(posedge i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.clk_i); + @(posedge i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.clk_i); stim_entry = stimuli[num_stim]; - force i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.tcdm_debug.req = 1'b1; - force i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.tcdm_debug.add = stim_entry[95:64]; - force i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.tcdm_debug.wdata = stim_entry[31:0]; - force i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.tcdm_debug.wen = 1'b0; - force i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.tcdm_debug.be = '1; + force i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.tcdm_debug.req = 1'b1; + force i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.tcdm_debug.add = stim_entry[95:64]; + force i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.tcdm_debug.wdata = stim_entry[31:0]; + force i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.tcdm_debug.wen = 1'b0; + force i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.tcdm_debug.be = '1; do begin - @(posedge i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.clk_i); - end while (~i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.tcdm_debug.gnt); - force i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.tcdm_debug.add = stim_entry[95:64]+4; - force i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.tcdm_debug.wdata = stim_entry[63:32]; + @(posedge i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.clk_i); + end while (~i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.tcdm_debug.gnt); + force i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.tcdm_debug.add = stim_entry[95:64]+4; + force i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.tcdm_debug.wdata = stim_entry[63:32]; do begin - @(posedge i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.clk_i); - end while (~i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.tcdm_debug.gnt); + @(posedge i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.clk_i); + end while (~i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.tcdm_debug.gnt); num_stim = num_stim + 1; if (num_stim > $size(stimuli) || stimuli[num_stim] === 96'bx) begin // make sure we have more stimuli @@ -822,12 +867,12 @@ module tb_pulp; break; end end // while (more_stim == 1'b1) - release i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.tcdm_debug.req; - release i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.tcdm_debug.add; - release i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.tcdm_debug.wdata; - release i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.tcdm_debug.wen; - release i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.tcdm_debug.be; - @(posedge i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.clk_i); + release i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.tcdm_debug.req; + release i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.tcdm_debug.add; + release i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.tcdm_debug.wdata; + release i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.tcdm_debug.wen; + release i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.tcdm_debug.be; + @(posedge i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.clk_i); endtask diff --git a/target/sim/tb/tb_pulp_simple.sv b/target/sim/tb/tb_pulp_simple.sv new file mode 100644 index 00000000..57ebfe65 --- /dev/null +++ b/target/sim/tb/tb_pulp_simple.sv @@ -0,0 +1,481 @@ +//----------------------------------------------------------------------------- +// Title : Simplified PULP Testbench +//----------------------------------------------------------------------------- +// File : tb_pulp_simple.sv +// Author : Manuel Eggimann +// Created : 05.12.2022 +//----------------------------------------------------------------------------- +// Description : +// This is a simplified RTL testbench for PULPissimo that support simulation of +// arbitrary binaries that have been converted to srec format. Checkout the +// available plusargs for more information. +//----------------------------------------------------------------------------- +// Copyright (C) 2013-2022 ETH Zurich, University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +//----------------------------------------------------------------------------- + +`timescale 1ns/100ps + +module tb_pulp_simple; + + // Choose your core: 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY) + parameter CORE_TYPE = 0; + + // if RI5CY is instantiated (CORE_TYPE == 0), USE_FPU enables the FPU + parameter USE_FPU = 1; + + // if RI5CY uses ZFINX (merged float and integer register files) + parameter USE_ZFINX = 0; + + // Enables/Disables the virtual stdout feature within PULPissimo. The virtual + // stdout allows the TB to communicate through a stdout with the PULPissimo by + // means of through hierarchy connections. This is way faster than UART + // simulation but is purely virtual and cannot not be realized in hardware. + parameter SIM_STDOUT = 1; + + // UART baud rate in bps + parameter BAUDRATE = 115200; + + + // Available plusargs: + + // +BOOTMODE="jtag_openocd"|"jtag_legacy"|"fastboot" + // Description + // + // Selects the mode with which to bootstrap the firmware: + // "jtag_openocd" + // communicates with the internal RISC-V debug unit to preload + // the binary into memory. + // "jtag_legacy" uses the RISC-V debug unit to control + // the core but uses the faster legacy pulp_jtag_tap for binary preloading. + // "fastboot" + // In this bootmode, the binary is preloaded by directly tougling the + // soc_interconnect debug bus by means of through-hierarchy connections to + // the TB. This bootmode is very fast but is not physical and thus does not + // verify that we could correctly communicate with a real chip. + // + // Default: + // jtag_legacy + + // +BINARY_SREC_PATH="my_firmware.srec" + // Description: + // + // The executable to execute on PULPissimo in Srecord format. Srecords is a + // standardized format to represent binary data in ascii text format. Notably, + // it also encodes also the entry point. GNU objcopy (part of binutils) can + // easily convert and elf file to this format. + // + // Default: + // None, this is a required plusarg for simulation of binaries. + + string BOOTMODE; + string BINARY_SREC_PATH; + + // Parse plusargs + initial begin : parse_plus_args + if (!$value$plusargs("BOOTMODE=%s", BOOTMODE)) + BOOTMODE = "jtag_legacy"; + if (!$value$plusargs("BINARY_SREC_PATH=%s", BINARY_SREC_PATH)) + // At the moment, all bootmodes require a user provided binary. It is thus + // an error not to provide one. + $fatal("BINARY_SREC_PATH is a required plusarg. Please specify a binary to execute on PULPissimo", -1); + end + + ////////////////////////////////////////////////////////// + // Fixed Parameters. Just changing these thus not work! // + ////////////////////////////////////////////////////////// + + // period of the external reference clock (32.769kHz) + localparam time REF_CLK_PERIOD = 30517ns; + localparam IO_PAD_COUNT = gpio_reg_pkg::GPIOCount; // Check the README on how + // to modify the pad count + localparam logic [9:0] FC_CORE_ID = {5'd31, 5'd0}; + localparam EXIT_SUCCESS = 0; + localparam EXIT_FAIL = 1; + + + ///////////// + // Imports // + ///////////// + import srec_pkg::*; + + ///////////////////////// + // Signal Declarations // + ///////////////////////// + + // TB signals + logic [95:0] stimuli[$]; // array for the stimulus vectors + jtag_pkg::test_mode_if_t test_mode_if = new; + jtag_pkg::debug_mode_if_t debug_mode_if = new; + pulp_tap_pkg::pulp_tap_if_soc_t pulp_tap = new; + logic [255:0][31:0] jtag_data; + + // DUT Connection Signals + wire w_pad_ref_clk; + wire w_pad_clk_byp_en; + wire w_pad_reset_n; + wire [1:0] w_bootsel; + wire [1:0] w_pad_hyper_csn; + wire w_pad_hyper_reset_n; + wire w_pad_hyper_ck; + wire w_pad_hyper_ckn; + wire [7:0] w_pad_hyper_dq; + wire w_pad_hyper_rwds; + wire w_pad_jtag_tck; + wire w_pad_jtag_tdi; + wire w_pad_jtag_tdo; + wire w_pad_jtag_tms; + wire w_pad_jtag_trstn; + wire [IO_PAD_COUNT-1:0] w_pad_io; + + // DUT Control Signals + // Clock, Reset & Bootmode + logic s_clk_ref; + logic s_hard_reset_n = 1'b0; + logic [1:0] s_bootsel; + // JTAG + logic s_jtag_tck = 1'b0; + logic s_jtag_tdi = 1'b0; + logic s_jtag_tdo; + logic s_jtag_tms = 1'b0; + logic s_jtag_trstn = 1'b0; + // UART + logic s_uart_rx_en = 1'b1; + logic s_uart_chip2vip; // (from chip to TB) Connected to pad_io[0] + logic s_uart_vip2chip; // (from TB to chip) Connected to pad_io[1] + // HyperBus + logic s_hyper_ck; + logic s_hyper_ckn; + logic [1:0] s_hyper_csn; + logic s_hyper_reset_n; + logic s_hyper_rwds; + logic [7:0] s_hyper_dq_from_chip; + logic [7:0] s_hyper_dq_to_chip = '0; + logic [7:0] s_hyper_dq_tx_en = '0; + + ////////////////////// + // Wire Assignments // + ////////////////////// + + // Clock, Reset & Bootmode + assign w_pad_ref_clk = s_clk_ref; + assign w_pad_clk_byp_en = 1'b0; // Not used by this TB + assign w_pad_reset_n = s_hard_reset_n; + assign w_bootsel = s_bootsel; + + // JTAG + assign w_pad_jtag_tck = s_jtag_tck; + assign w_pad_jtag_tms = s_jtag_tms; + assign w_pad_jtag_trstn = s_jtag_trstn; + assign w_pad_jtag_tdi = s_jtag_tdi; + assign s_jtag_tdo = w_pad_jtag_tdo; + + // UART + assign s_uart_chip2vip = w_pad_io[0]; + assign w_pad_io[1] = s_uart_vip2chip; + + // HyperBus (Not used at this point) + assign s_hyper_ck = w_pad_hyper_ck; + assign s_hyper_ckn = w_pad_hyper_ckn; + for (genvar i = 0; i < 8; i++) begin: gen_assign_hyper_dq_wires + assign s_hyper_dq_from_chip[i] = w_pad_hyper_dq[i]; + assign w_pad_hyper_dq[i] = s_hyper_dq_tx_en[i]? s_hyper_dq_to_chip: 1'bz; + end + + + //////////////////////////////// + // Reference Clock generation // + //////////////////////////////// + + tb_clk_gen #( + .CLK_PERIOD(REF_CLK_PERIOD) + ) i_ref_clk_gen ( + .clk_o(s_clk_ref) + ); + + ////////// + // VIPs // + ////////// + + // UART receiver + uart_sim #( + .BAUD_RATE ( BAUDRATE ), + .PARITY_EN ( 0 ) + ) i_uart_sim ( + .rx ( s_uart_chip2vip ), + .rx_en ( s_uart_rx_en ), + .tx ( s_uart_vip2chip ) + ); + + + ///////// + // DUT // + ///////// + + pulpissimo #( + .CORE_TYPE ( CORE_TYPE ), + .USE_FPU ( USE_FPU ), + .USE_ZFINX ( USE_ZFINX ), + .USE_HWPE ( 1'b0 ), //TODO Re-expose once debugged why it is not working + .SIM_STDOUT(SIM_STDOUT) + ) i_dut ( + .pad_ref_clk ( w_pad_ref_clk ), + .pad_reset_n ( w_pad_reset_n ), + .pad_clk_byp_en ( w_pad_clk_byp_en ), + .pad_bootsel0 ( w_bootsel[0] ), + .pad_bootsel1 ( w_bootsel[1] ), + .pad_jtag_tck ( w_pad_jtag_tck ), + .pad_jtag_tdi ( w_pad_jtag_tdi ), + .pad_jtag_tdo ( w_pad_jtag_tdo ), + .pad_jtag_tms ( w_pad_jtag_tms ), + .pad_jtag_trstn ( w_pad_jtag_trstn ), + .pad_hyper_csn ( w_pad_hyper_csn ), + .pad_hyper_reset_n ( w_pad_hyper_reset_n ), + .pad_hyper_ck ( w_pad_hyper_ck ), + .pad_hyper_ckn ( w_pad_hyper_ckn ), + .pad_hyper_dq ( w_pad_hyper_dq ), + .pad_hyper_rwds ( w_pad_hyper_rwds ), + .pad_io ( w_pad_io ) + ); + + + ///////////////////// + // TB Boot Process // + ///////////////////// + + initial begin: load_and_run_binary + automatic srec_record_t records[$]; + int entry_point; + int exit_code; + + // Set timing format for %t format specifiers + $timeformat(-9, 0, "ns", 9); + + // Load Stimuli + $display("[TB] %t: PULPissimo Testbench started with bootmode %s", $realtime, BOOTMODE); + $display("[TB] %t: Loading Stimuli from stimuli file %s", $realtime, BINARY_SREC_PATH); + srec_read(BINARY_SREC_PATH, records); + srec_records_to_stimuli(records, stimuli, entry_point); + $display("[TB] %t: Finished loading stimuli from SREC file. Binary contains %0d words and has entrypoint %08h", $realtime, stimuli.size(), entry_point); + + case (BOOTMODE) + "jtag_legacy", "jtag_openocd": begin + s_bootsel = 2'd1; + end + + default: begin + s_bootsel = 2'd0; // Boot in default mode which enables either zforth or + // SREC over UART booting. Depends on the enabled + // features in the bootrom. + end + endcase + + + // Assert hard reset + $display("[TB] %t: Asserting hard reset for 5 ref_clk cycles...", $realtime); + s_hard_reset_n = 1'b0; + #(REF_CLK_PERIOD*5); + s_hard_reset_n = 1'b1; + + $display("[TB] %t: Hard reset released. Running some JTAG sanity tests", $realtime); + #(REF_CLK_PERIOD*5); // Wait another couple of ref clock cycles for the SoC to + // become ready (FLL init). + // before starting the actual boot procedure we do some light + // testing on the jtag link + jtag_sanity_tests(entry_point, s_jtag_tck, s_jtag_tms, s_jtag_trstn, s_jtag_tdi, s_jtag_tdo); + + $display("[TB] %t: Done. Starting boot sequence", $realtime); + case (BOOTMODE) + "jtag_legacy": begin + boot_jtag_legacy(entry_point, stimuli, s_jtag_tck, s_jtag_tms, s_jtag_trstn, s_jtag_tdi, s_jtag_tdo); + end + + "fastboot": begin + boot_fast(entry_point, stimuli, s_jtag_tck, s_jtag_tms, s_jtag_trstn, s_jtag_tdi, s_jtag_tdo); + end + + default: begin + //boot_jtag_legacy(entry_point, stimuli, s_jtag_tck, s_jtag_tms, s_jtag_trstn, s_jtag_tdi, s_jtag_tdo); + end + endcase + + + $display("[TB] %t: Waiting for end of computation", $realtime); + wait_for_end_of_computation(s_jtag_tck, s_jtag_tms, s_jtag_trstn, s_jtag_tdi, s_jtag_tdo, exit_code); + + $display("[TB] %t: TB Execution finished with exit code %0d", $realtime, exit_code); + $stop; + end + + + ////////////// + // TB Tasks // + ////////////// + + task automatic jtag_sanity_tests( + int entry_point, + ref logic s_tck, + ref logic s_tms, + ref logic s_trstn, + ref logic s_tdi, + ref logic s_tdo + ); + + jtag_pkg::jtag_reset(s_tck, s_tms, s_trstn, s_tdi); + jtag_pkg::jtag_softreset(s_tck, s_tms, s_trstn, s_tdi); + #5us; + + jtag_pkg::jtag_bypass_test(s_tck, s_tms, s_trstn, s_tdi, s_tdo); + #5us; + + jtag_pkg::jtag_get_idcode(s_tck, s_tms, s_trstn, s_tdi, s_tdo); + #5us; + test_mode_if.init(s_tck, s_tms, s_trstn, s_tdi); + $display("[TB] %t: Writing testpattern to L2 memory binary entrypoint", $realtime); + pulp_tap.init(s_tck, s_tms, s_trstn, s_tdi); + pulp_tap.write32(entry_point, 1, 32'hABBAABBA, s_tck, s_tms, s_trstn, s_tdi, s_tdo); + #50us; + pulp_tap.read32(entry_point, 1, jtag_data, s_tck, s_tms, s_trstn, s_tdi, s_tdo); + if (jtag_data[0] != 32'hABBAABBA) + $error("R/W Test of L2 memory entrypoint failed: %h != %h", jtag_data[0], 32'habbaabba); + else + $display("[TB] %t: Finished sanity tests", $realtime); + endtask + + task automatic boot_jtag_legacy( + int entry_point, + ref [95:0] stimuli[$], + ref logic s_tck, + ref logic s_tms, + ref logic s_trstn, + ref logic s_tdi, + ref logic s_tdo + ); + $display("[TB] %t: Starting boot procedure with legacy bootmode", $realtime); + halt_hart_write_boot_addr(entry_point, s_tck, s_tms, s_trstn, s_tdi, s_tdo); + $display("[TB] %t: Loading binary into memory uisng legacy pulp TAP", $realtime); + pulp_tap_pkg::load_L2(0, stimuli, s_tck, s_tms, s_trstn, s_tdi, s_tdo); + $display("[TB] %t: Done. Resuming HART", $realtime); + // configure for debug module dmi access again + debug_mode_if.init_dmi_access(s_tck, s_tms, s_trstn, s_tdi); + // we have set dpc and loaded the binary, we can go now + debug_mode_if.resume_harts(s_tck, s_tms, s_trstn, s_tdi, s_tdo); + endtask // boot_jtag_legacy + + task automatic boot_fast( + int entry_point, + ref [95:0] stimuli[$], + ref logic s_tck, + ref logic s_tms, + ref logic s_trstn, + ref logic s_tdi, + ref logic s_tdo + ); + $display("[TB] %t: Starting boot procedure in fastboot mode", $realtime); + halt_hart_write_boot_addr(entry_point, s_tck, s_tms, s_trstn, s_tdi, s_tdo); + $display("[TB] %t: Loading binary into memory uisng legacy pulp TAP", $realtime); + fastboot_preload_l2(0, stimuli); + $display("[TB] %t: Done. Resuming HART", $realtime); + // configure for debug module dmi access again + debug_mode_if.init_dmi_access(s_tck, s_tms, s_trstn, s_tdi); + // we have set dpc and loaded the binary, we can go now + debug_mode_if.resume_harts(s_tck, s_tms, s_trstn, s_tdi, s_tdo); + endtask // boot_jtag_legacy + + + task automatic halt_hart_write_boot_addr( + int entry_point, + ref logic s_tck, + ref logic s_tms, + ref logic s_trstn, + ref logic s_tdi, + ref logic s_tdo + ); + debug_mode_if.init_dmi_access(s_tck, s_tms, s_trstn, s_tdi); + debug_mode_if.set_dmactive(1'b1, s_tck, s_tms, s_trstn, s_tdi, s_tdo); + debug_mode_if.set_hartsel(FC_CORE_ID, s_tck, s_tms, s_trstn, s_tdi, s_tdo); + $display("[TB] %t: Halting the core", $realtime); + debug_mode_if.halt_harts(s_tck, s_tms, s_trstn, s_tdi, s_tdo); + $display("[TB] %t: Writing boot address into dpc", $realtime); + debug_mode_if.write_reg_abstract_cmd(riscv::CSR_DPC, entry_point, s_tck, s_tms, s_trstn, + s_tdi, s_tdo); + + endtask + + + task automatic fastboot_preload_l2(input int stimuli_start_offset, ref logic [95:0] stimuli[$]); + logic more_stim; + static logic [95:0] stim_entry; + more_stim = 1'b1; + $display("[TB] %t: Preloading L2 with stimuli through direct access.", $realtime); + while (more_stim == 1'b1) begin + @(posedge i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.clk_i); + stim_entry = stimuli[stimuli_start_offset]; + force i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.tcdm_debug.req = 1'b1; + force i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.tcdm_debug.add = stim_entry[95:64]; + force i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.tcdm_debug.wdata = stim_entry[31:0]; + force i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.tcdm_debug.wen = 1'b0; + force i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.tcdm_debug.be = '1; + do begin + @(posedge i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.clk_i); + end while (~i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.tcdm_debug.gnt); + force i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.tcdm_debug.add = stim_entry[95:64]+4; + force i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.tcdm_debug.wdata = stim_entry[63:32]; + do begin + @(posedge i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.clk_i); + end while (~i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.tcdm_debug.gnt); + + stimuli_start_offset = stimuli_start_offset + 1; + if (stimuli_start_offset > $size(stimuli) || stimuli[stimuli_start_offset] === 96'bx) begin // make sure we have more stimuli + more_stim = 0; // if not set variable to 0, will prevent additional stimuli to be applied + break; + end + end // while (more_stim == 1'b1) + release i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.tcdm_debug.req; + release i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.tcdm_debug.add; + release i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.tcdm_debug.wdata; + release i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.tcdm_debug.wen; + release i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.tcdm_debug.be; + @(posedge i_dut.i_soc_domain.i_pulp_soc.i_soc_interconnect_wrap.clk_i); + endtask + + task automatic wait_for_end_of_computation( + ref logic s_tck, + ref logic s_tms, + ref logic s_trstn, + ref logic s_tdi, + ref logic s_tdo, + output int exit_status + ); + int rd_cnt = 0; + // enable sb access for subsequent readMem calls + debug_mode_if.set_sbreadonaddr(1'b1, s_tck, s_tms, s_trstn, s_tdi, s_tdo); + jtag_data[0] = 0; + while (jtag_data[0][31] == 0) begin + // every 10th loop iteration, clear the debug module's SBA unit CSR to make + // sure there's no error blocking our reads. Sometimes a TCDM read + // request issued by the debug module takes longer than it takes + // for the read request to the debug module to arrive and it + // stores an error in the SBCS register. By clearing it + // periodically we make sure the test can terminate. + if (rd_cnt % 10 == 0) begin + debug_mode_if.clear_sbcserrors(s_tck, s_tms, s_trstn, s_tdi, s_tdo); + end + debug_mode_if.readMem(32'h1A1040A0, jtag_data[0], s_tck, s_tms, s_trstn, s_tdi, s_tdo); + rd_cnt++; + #50us; + end + + if (jtag_data[0][30:0] == 0) exit_status = EXIT_SUCCESS; + else exit_status = EXIT_FAIL; + $display("[TB] %t: Received status core: 0x%h", $realtime, jtag_data[0][30:0]); + endtask + +endmodule diff --git a/rtl/vip/.gitignore b/target/sim/vip/.gitignore similarity index 100% rename from rtl/vip/.gitignore rename to target/sim/vip/.gitignore diff --git a/target/sim/vip/Bender.yml b/target/sim/vip/Bender.yml new file mode 100644 index 00000000..97b54d33 --- /dev/null +++ b/target/sim/vip/Bender.yml @@ -0,0 +1,35 @@ +package: + name: pulpissimo_optional_vips + authors: + - "Manuel Eggimann " + +sources: + # Open models + - target: any(test,simulation) + files: + - spi_master_padframe.sv + - uart_sim.sv + - camera/cam_vip.sv + + # S25FS256_model (SPI Flash) + - target: all(any(test,simulation), flash_vip) + defines: + SPEEDSIM: ~ + files: + - spi_flash/S25fs256s/model/s25fs256s.v + + # 24FC1025 model (I2C flash) + - target: all(any(test,simulation), i2c_vip) + defines: + SPEEDSIM: ~ + files: + - i2c_eeprom/24FC1025.v + + # i2s model + - target: all(any(test,simulation), i2s_vip) + defines: + SPEEDSIM: ~ + files: + - i2s/i2c_if.v + - i2s/i2s_vip_channel.sv + - i2s/i2s_vip.sv diff --git a/rtl/vip/camera/cam_vip.sv b/target/sim/vip/camera/cam_vip.sv similarity index 100% rename from rtl/vip/camera/cam_vip.sv rename to target/sim/vip/camera/cam_vip.sv diff --git a/rtl/vip/camera/img/frame0.img b/target/sim/vip/camera/img/frame0.img similarity index 100% rename from rtl/vip/camera/img/frame0.img rename to target/sim/vip/camera/img/frame0.img diff --git a/rtl/vip/camera/img/frame0.pnm b/target/sim/vip/camera/img/frame0.pnm similarity index 100% rename from rtl/vip/camera/img/frame0.pnm rename to target/sim/vip/camera/img/frame0.pnm diff --git a/rtl/vip/camera/img/frame1.img b/target/sim/vip/camera/img/frame1.img similarity index 100% rename from rtl/vip/camera/img/frame1.img rename to target/sim/vip/camera/img/frame1.img diff --git a/rtl/vip/camera/img/frame1.pnm b/target/sim/vip/camera/img/frame1.pnm similarity index 100% rename from rtl/vip/camera/img/frame1.pnm rename to target/sim/vip/camera/img/frame1.pnm diff --git a/rtl/vip/camera/img/pnmparse.tcl b/target/sim/vip/camera/img/pnmparse.tcl similarity index 100% rename from rtl/vip/camera/img/pnmparse.tcl rename to target/sim/vip/camera/img/pnmparse.tcl diff --git a/rtl/vip/camera/img/pnmparse_checksum.tcl b/target/sim/vip/camera/img/pnmparse_checksum.tcl similarity index 100% rename from rtl/vip/camera/img/pnmparse_checksum.tcl rename to target/sim/vip/camera/img/pnmparse_checksum.tcl diff --git a/rtl/vip/get-vips.sh b/target/sim/vip/get-vips.sh similarity index 97% rename from rtl/vip/get-vips.sh rename to target/sim/vip/get-vips.sh index 96170fee..f4587f0a 100755 --- a/rtl/vip/get-vips.sh +++ b/target/sim/vip/get-vips.sh @@ -37,10 +37,12 @@ else echo "The directory ${VIP_DIR} already exists, skipping git clone" fi echo "Installing i2c eeprom model" +mkdir -p i2c_eeprom cp --verbose "$VIP_DIR"/24FC1025-i2c-eeprom/*.v i2c_eeprom/ echo "Installing spi flash model" mkdir -p spi_flash/S25fs256s cp --verbose -r "$VIP_DIR"/S25fs256s-spi-flash/* spi_flash/S25fs256s echo "Installing i2s model" +mkdir -p i2s cp --verbose "$VIP_DIR"/24FC1025-i2c-eeprom/24FC1025.v i2s/i2c_if.v patch i2s/i2c_if.v < i2s/i2c_if_timings.patch diff --git a/rtl/vip/i2c_eeprom/README.md b/target/sim/vip/i2c_eeprom/README.md similarity index 100% rename from rtl/vip/i2c_eeprom/README.md rename to target/sim/vip/i2c_eeprom/README.md diff --git a/rtl/vip/i2s/README.md b/target/sim/vip/i2s/README.md similarity index 100% rename from rtl/vip/i2s/README.md rename to target/sim/vip/i2s/README.md diff --git a/rtl/vip/i2s/i2c_if.patch b/target/sim/vip/i2s/i2c_if.patch similarity index 100% rename from rtl/vip/i2s/i2c_if.patch rename to target/sim/vip/i2s/i2c_if.patch diff --git a/rtl/vip/i2s/i2c_if_timings.patch b/target/sim/vip/i2s/i2c_if_timings.patch similarity index 100% rename from rtl/vip/i2s/i2c_if_timings.patch rename to target/sim/vip/i2s/i2c_if_timings.patch diff --git a/rtl/vip/i2s/i2s_buffer.hex b/target/sim/vip/i2s/i2s_buffer.hex similarity index 100% rename from rtl/vip/i2s/i2s_buffer.hex rename to target/sim/vip/i2s/i2s_buffer.hex diff --git a/rtl/vip/i2s/i2s_buffer_0.hex b/target/sim/vip/i2s/i2s_buffer_0.hex similarity index 100% rename from rtl/vip/i2s/i2s_buffer_0.hex rename to target/sim/vip/i2s/i2s_buffer_0.hex diff --git a/rtl/vip/i2s/i2s_buffer_1.hex b/target/sim/vip/i2s/i2s_buffer_1.hex similarity index 100% rename from rtl/vip/i2s/i2s_buffer_1.hex rename to target/sim/vip/i2s/i2s_buffer_1.hex diff --git a/rtl/vip/i2s/i2s_buffer_2.hex b/target/sim/vip/i2s/i2s_buffer_2.hex similarity index 100% rename from rtl/vip/i2s/i2s_buffer_2.hex rename to target/sim/vip/i2s/i2s_buffer_2.hex diff --git a/rtl/vip/i2s/i2s_buffer_3.hex b/target/sim/vip/i2s/i2s_buffer_3.hex similarity index 100% rename from rtl/vip/i2s/i2s_buffer_3.hex rename to target/sim/vip/i2s/i2s_buffer_3.hex diff --git a/rtl/vip/i2s/i2s_vip.sv b/target/sim/vip/i2s/i2s_vip.sv similarity index 100% rename from rtl/vip/i2s/i2s_vip.sv rename to target/sim/vip/i2s/i2s_vip.sv diff --git a/rtl/vip/i2s/i2s_vip_channel.sv b/target/sim/vip/i2s/i2s_vip_channel.sv similarity index 100% rename from rtl/vip/i2s/i2s_vip_channel.sv rename to target/sim/vip/i2s/i2s_vip_channel.sv diff --git a/rtl/vip/spi_flash/README.md b/target/sim/vip/spi_flash/README.md similarity index 100% rename from rtl/vip/spi_flash/README.md rename to target/sim/vip/spi_flash/README.md diff --git a/rtl/vip/spi_master_padframe.sv b/target/sim/vip/spi_master_padframe.sv similarity index 100% rename from rtl/vip/spi_master_padframe.sv rename to target/sim/vip/spi_master_padframe.sv diff --git a/rtl/vip/uart_sim.sv b/target/sim/vip/uart_sim.sv similarity index 97% rename from rtl/vip/uart_sim.sv rename to target/sim/vip/uart_sim.sv index 4d78e347..9d5b65fb 100644 --- a/rtl/vip/uart_sim.sv +++ b/target/sim/vip/uart_sim.sv @@ -26,10 +26,12 @@ module uart_sim #( output logic tx, input logic rx_en ); + timeunit 1ns; + timeprecision 1ns; /* pragma translate_off */ `ifndef VERILATOR - localparam time BIT_PERIOD = (1000000000 / BAUD_RATE) * 1ns; + localparam realtime BIT_PERIOD = 1s / BAUD_RATE; bit newline; logic [7:0] character; diff --git a/tests/README.md b/tests/README.md deleted file mode 100644 index 6ae05293..00000000 --- a/tests/README.md +++ /dev/null @@ -1,71 +0,0 @@ -# Tests -You can run tests either locally in a manual fashion or use your GitLab CI -instance. The latter is meant for internal usage. - -## Running software tests manually -Call the `./update-tests` script in the top-level directory. This populate this -directory with all software tests. - -Make sure you have [configured](https://github.com/pulp-platform/pulp-sdk) your -SDK. You can now run single tests by using the provided Makefiles or use -`plptest --testset path-to-testset.cfg`. Other useful flags you can set for -`plptest` are `--stdout` to dump the output to stdout and `--threads` to run -multiple tests at once. - -After the tests complete you will have JUnit reports for each `testset.cfg` -placed in the `junit-reports` directory. - -## Adding your own tests -You can add your own tests by putting them in a repository and adding them to -`update-tests` and `update-tests-gitlab` scripts in the top-level folder. Make -sure you define an appropriate `testset.cfg` that lists all the tests in your -repository and for each test provide another `testset.cfg` with instructions on -how to run it. Have a look at the already existing tests for an idea how such -files should look like. - -## Setting up CI -A brief explanation on how to set up GitLab CI for this project. - -### Prerequisites -- Questasim accessible from the GitLab instance -- Vivado accessible from the GitLab instance -- Access to the ETH Artifactory server. This is required to download the PULP - SDK release versions. Alternatively, you can also always fetch the latest SDK - sources and let it be built and used for running the tests. This approach is - not recommended. -- Centos7 runners - -### Steps -1. Import this repository to GitLab. Using the GitLab import functionality is - recommended. -2. Under Settings -> Repository -> Variables add the following environment - variables: - - `ARTIFACTORY_USER` - - `ARTIFACTORY_PASSWORD` - - `PULP_ARTIFACTORY_USER` - - `PULP_RUNTIME_GCC_TOOLCHAIN` - - with their respective values. Make sure you check the mask tick box on all of - these. - - This is a redundant set of variables for backward compatibility reasons -3. The `.gitlab-ci.yml` file should be auto-detected by GitLab and start running - test instances whenever you push commits. -4. Inspect the current running tests instances (pipelines) under CI/CD -> - Pipelines. Here you can stop instances you deem unnecessary but you can also - launch such manually for any branch by using the green `Run Pipeline` button. - -### Artifacts and Reports -Test instances produce a set of outputs called artifacts and reports. They can -be downloaded from the GitLab interface. - -Reports are `JUnit.xml` documents and for convenience HTML renderings -thereof. These are used to inspect test results. - -Artifacts are more general byproducts of the different execution stages of a -pipeline. In this repository each stage saves nearly all its relevant output. -While these artifacts can be used for debugging, what you mostly want is -inspecting the FPGA build results (bitstream, reports). - - - diff --git a/tests/runtime-tests.yaml b/tests/runtime-tests.yaml deleted file mode 100644 index fab5286c..00000000 --- a/tests/runtime-tests.yaml +++ /dev/null @@ -1,768 +0,0 @@ -parallel_bare_tests: - parMatrixMul8: - path: ./parallel_bare_tests/parMatrixMul8 - command: make clean all run - Sparse: - path: ./parallel_bare_tests/Sparse - command: make clean all run - Sparse/golden: - path: ./parallel_bare_tests/Sparse/golden - command: make clean all run - conv16: - path: ./parallel_bare_tests/conv16 - command: make clean all run - pooling: - path: ./parallel_bare_tests/pooling - command: make clean all run - parMatrixMul32: - path: ./parallel_bare_tests/parMatrixMul32 - command: make clean all run - cnn: - path: ./parallel_bare_tests/cnn - command: make clean all run - parWorkload: - path: ./parallel_bare_tests/parWorkload - command: make clean all run - FFT: - path: ./parallel_bare_tests/FFT - command: make clean all run - LU: - path: ./parallel_bare_tests/LU - command: make clean all run - LU/golden: - path: ./parallel_bare_tests/LU/golden - command: make clean all run - multicore: - path: ./parallel_bare_tests/multicore - command: make clean all run - multicore/sudokusolver: - path: ./parallel_bare_tests/multicore/sudokusolver - command: make clean all run - multicore/stencil: - path: ./parallel_bare_tests/multicore/stencil - command: make clean all run - fcOffload_parMatrixMul32: - path: ./parallel_bare_tests/fcOffload_parMatrixMul32 - command: make clean all run - dummypar1: - path: ./parallel_bare_tests/dummypar1 - command: make clean all run - logistic_regression_OvR: - path: ./parallel_bare_tests/logistic_regression_OvR - command: make clean all run - convolution2d: - path: ./parallel_bare_tests/convolution2d - command: make clean all run - Dijkstra/golden: - path: ./parallel_bare_tests/Dijkstra/golden - command: make clean all run - Dijkstra: - path: ./parallel_bare_tests/Dijkstra - command: make clean all run - convolution: - path: ./parallel_bare_tests/convolution - command: make clean all run - parMatrixMul: - path: ./parallel_bare_tests/parMatrixMul - command: make clean all run - testDMA_slave: - path: ./parallel_bare_tests/testDMA_slave - command: make clean all run - rms_float: - path: ./parallel_bare_tests/rms_float - command: make clean all run - parMatrixMul16: - path: ./parallel_bare_tests/parMatrixMul16 - command: make clean all run - fft_radix2: - path: ./parallel_bare_tests/fft_radix2 - command: make clean all run - fft_radix8: - path: ./parallel_bare_tests/fft_radix8 - command: make clean all run - -sequential_bare_test: - dct: - path: ./sequential_bare_tests/dct - command: make clean all run - tracking_seq: - path: ./sequential_bare_tests/tracking_seq - command: make clean all run - fft2: - path: ./sequential_bare_tests/fft2 - command: make clean all run - rijndael: - path: ./sequential_bare_tests/rijndael - command: make clean all run - matrixAdd: - path: ./sequential_bare_tests/matrixAdd - command: make clean all run - gradient: - path: ./sequential_bare_tests/gradient - command: make clean all run - jacobi-2d-imper: - path: ./sequential_bare_tests/jacobi-2d-imper - command: make clean all run - sha: - path: ./sequential_bare_tests/sha - command: make clean all run - sudokusolver: - path: ./sequential_bare_tests/sudokusolver - command: make clean all run - matrixMul8_dotp: - path: ./sequential_bare_tests/matrixMul8_dotp - command: make clean all run - bitDescriptor: - path: ./sequential_bare_tests/bitDescriptor - command: make clean all run - fdctfst: - path: ./sequential_bare_tests/fdctfst - command: make clean all run - stencil_vect: - path: ./sequential_bare_tests/stencil_vect - command: make clean all run - matrixMul32: - path: ./sequential_bare_tests/matrixMul32 - command: make clean all run - keccak: - path: ./sequential_bare_tests/keccak - command: make clean all run - fir: - path: ./sequential_bare_tests/fir - command: make clean all run - stencil: - path: ./sequential_bare_tests/stencil - command: make clean all run - ipm: - path: ./sequential_bare_tests/ipm - command: make clean all run - huffman: - path: ./sequential_bare_tests/huffman - command: make clean all run - matmul: - path: ./sequential_bare_tests/matmul - command: make clean all run - non_separable_2d_filter: - path: ./sequential_bare_tests/non_separable_2d_filter - command: make clean all run - towerofhanoi: - path: ./sequential_bare_tests/towerofhanoi - command: make clean all run - crc32: - path: ./sequential_bare_tests/crc32 - command: make clean all run - conv2d: - path: ./sequential_bare_tests/conv2d - command: make clean all run - fdct: - path: ./sequential_bare_tests/fdct - command: make clean all run - matrixMul16: - path: ./sequential_bare_tests/matrixMul16 - command: make clean all run - matrixMul16_dotp: - path: ./sequential_bare_tests/matrixMul16_dotp - command: make clean all run - seidel: - path: ./sequential_bare_tests/seidel - command: make clean all run - fibonacci: - path: ./sequential_bare_tests/fibonacci - command: make clean all run - gauss-2d: - path: ./sequential_bare_tests/gauss-2d - command: make clean all run - aes_cbc: - path: ./sequential_bare_tests/aes_cbc - command: make clean all run - bubblesort: - path: ./sequential_bare_tests/bubblesort - command: make clean all run - fdtd-1d: - path: ./sequential_bare_tests/fdtd-1d - command: make clean all run - jacobi-1d-imper: - path: ./sequential_bare_tests/jacobi-1d-imper - command: make clean all run - matrixMul8: - path: ./sequential_bare_tests/matrixMul8 - command: make clean all run - fft: - path: ./sequential_bare_tests/fft - command: make clean all run - motion_detection: - path: ./sequential_bare_tests/motion_detection - command: make clean all run - -pulp_tests: - mchan/v7: - path: ./pulp_tests/mchan/v7 - command: make clean all run - mchan/v6: - path: ./pulp_tests/mchan/v6 - command: make clean all run - efuse_test: - path: ./pulp_tests/efuse_test - command: make clean all run - hello: - path: ./pulp_tests/hello - command: make clean all run - bugs/pm/deep_sleep: - path: ./pulp_tests/bugs/pm/deep_sleep - command: make clean all run - bugs/cluster_clock_gating_bug0: - path: ./pulp_tests/bugs/cluster_clock_gating_bug0 - command: make clean all run - bugs/test_lvds: - path: ./pulp_tests/bugs/test_lvds - command: make clean all run - bugs/bug_i2c_scl_alt2/test_I2C: - path: ./pulp_tests/bugs/bug_i2c_scl_alt2/test_I2C - command: make clean all run - bugs/pads_ds_pe_check: - path: ./pulp_tests/bugs/pads_ds_pe_check - command: make clean all run - bugs/camera_HIMAX_slice_RTL: - path: ./pulp_tests/bugs/camera_HIMAX_slice_RTL - command: make clean all run - bugs/cluster_clock_gating_bug1: - path: ./pulp_tests/bugs/cluster_clock_gating_bug1 - command: make clean all run - bugs/fcTcdm_copy_to_L2: - path: ./pulp_tests/bugs/fcTcdm_copy_to_L2 - command: make clean all run - bugs/perf_cycle_lost: - path: ./pulp_tests/bugs/perf_cycle_lost - command: make clean all run - accelerators/xne/v1: - path: ./pulp_tests/accelerators/xne/v1 - command: make clean all run - test_power: - path: ./pulp_tests/test_power - command: make clean all run - memory/l2_shared_scm: - path: ./pulp_tests/memory/l2_shared_scm - command: make clean all run - memory/l2: - path: ./pulp_tests/memory/l2 - command: make clean all run - memory/l2_scm/matmul: - path: ./pulp_tests/memory/l2_scm/matmul - command: make clean all run - memory/l2_scm/iter: - path: ./pulp_tests/memory/l2_scm/iter - command: make clean all run - verif_tests/cluster_dma_subsystem/mchan/mchan_transfer_test: - path: ./pulp_tests/verif_tests/cluster_dma_subsystem/mchan/mchan_transfer_test - command: make clean all run - verif_tests/cluster_dma_subsystem/mchan/mchan_registers_test: - path: ./pulp_tests/verif_tests/cluster_dma_subsystem/mchan/mchan_registers_test - command: make clean all run - verif_tests/udma_subsystem/spi_master: - path: ./pulp_tests/verif_tests/udma_subsystem/spi_master - command: make clean all run - verif_tests/udma_subsystem/uart: - path: ./pulp_tests/verif_tests/udma_subsystem/uart - command: make clean all run - verif_tests/udma_subsystem/hyper/hyperram: - path: ./pulp_tests/verif_tests/udma_subsystem/hyper/hyperram - command: make clean all run - verif_tests/udma_subsystem/hyper/hyperflash: - path: ./pulp_tests/verif_tests/udma_subsystem/hyper/hyperflash - command: make clean all run - verif_tests/udma_subsystem/sdio: - path: ./pulp_tests/verif_tests/udma_subsystem/sdio - command: make clean all run - verif_tests/udma_subsystem/csi2: - path: ./pulp_tests/verif_tests/udma_subsystem/csi2 - command: make clean all run - verif_tests/udma_subsystem/i2c: - path: ./pulp_tests/verif_tests/udma_subsystem/i2c - command: make clean all run - verif_tests/ao_soc_io_subsystem/udma/udma_filter: - path: ./pulp_tests/verif_tests/ao_soc_io_subsystem/udma/udma_filter - command: make clean all run - verif_tests/ao_soc_io_subsystem/udma/udma_mram: - path: ./pulp_tests/verif_tests/ao_soc_io_subsystem/udma/udma_mram - command: make clean all run - verif_tests/ao_soc_io_subsystem/udma/udma_control/udma_ctrl_evt_test: - path: ./pulp_tests/verif_tests/ao_soc_io_subsystem/udma/udma_control/udma_ctrl_evt_test - command: make clean all run - verif_tests/ao_soc_io_subsystem/udma/udma_control/udma_ctrl_registers_test: - path: ./pulp_tests/verif_tests/ao_soc_io_subsystem/udma/udma_control/udma_ctrl_registers_test - command: make clean all run - verif_tests/ao_soc_io_subsystem/udma/udma_control/udma_ctrl_cg_test: - path: ./pulp_tests/verif_tests/ao_soc_io_subsystem/udma/udma_control/udma_ctrl_cg_test - command: make clean all run - verif_tests/quiddikey: - path: ./pulp_tests/verif_tests/quiddikey - command: make clean all run - verif_tests/ao_soc_mem_subsystem/soc_mem/rom/rom_access: - path: ./pulp_tests/verif_tests/ao_soc_mem_subsystem/soc_mem/rom/rom_access - command: make clean all run - verif_tests/ao_soc_security_subsystem/mpu/mpu_fc_test/test_cluster_test_and_set_access: - path: ./pulp_tests/verif_tests/ao_soc_security_subsystem/mpu/mpu_fc_test/test_cluster_test_and_set_access - command: make clean all run - verif_tests/ao_soc_security_subsystem/mpu/mpu_fc_test/test_l2_access: - path: ./pulp_tests/verif_tests/ao_soc_security_subsystem/mpu/mpu_fc_test/test_l2_access - command: make clean all run - verif_tests/ao_soc_security_subsystem/mpu/mpu_fc_test/test_cluster_tcdm_access: - path: ./pulp_tests/verif_tests/ao_soc_security_subsystem/mpu/mpu_fc_test/test_cluster_tcdm_access - command: make clean all run - verif_tests/ao_soc_security_subsystem/mpu/mpu_fc_test/test_apb_access: - path: ./pulp_tests/verif_tests/ao_soc_security_subsystem/mpu/mpu_fc_test/test_apb_access - command: make clean all run - verif_tests/ao_soc_security_subsystem/mpu/mpu_fc_test/test_rom_access: - path: ./pulp_tests/verif_tests/ao_soc_security_subsystem/mpu/mpu_fc_test/test_rom_access - command: make clean all run - verif_tests/ao_soc_security_subsystem/mpu/mpu_fc_test/test_instr_filter: - path: ./pulp_tests/verif_tests/ao_soc_security_subsystem/mpu/mpu_fc_test/test_instr_filter - command: make clean all run - verif_tests/ao_soc_security_subsystem/mpu/mpu_udma_test: - path: ./pulp_tests/verif_tests/ao_soc_security_subsystem/mpu/mpu_udma_test - command: make clean all run - verif_tests/ao_soc_security_subsystem/mpu/mpu_registers_test: - path: ./pulp_tests/verif_tests/ao_soc_security_subsystem/mpu/mpu_registers_test - command: make clean all run - verif_tests/ao_soc_security_subsystem/mpu/mpu_cluster_test/test_l2_access: - path: ./pulp_tests/verif_tests/ao_soc_security_subsystem/mpu/mpu_cluster_test/test_l2_access - command: make clean all run - verif_tests/ao_soc_security_subsystem/mpu/mpu_cluster_test/test_dma_l2_access: - path: ./pulp_tests/verif_tests/ao_soc_security_subsystem/mpu/mpu_cluster_test/test_dma_l2_access - command: make clean all run - verif_tests/ao_soc_security_subsystem/mpu/mpu_cluster_test/test_apb_access: - path: ./pulp_tests/verif_tests/ao_soc_security_subsystem/mpu/mpu_cluster_test/test_apb_access - command: make clean all run - verif_tests/ao_soc_security_subsystem/mpu/mpu_cluster_test: - path: ./pulp_tests/verif_tests/ao_soc_security_subsystem/mpu/mpu_cluster_test - command: make clean all run - verif_tests/ao_soc_security_subsystem/mpu/mpu_cluster_test/test_ROM_access: - path: ./pulp_tests/verif_tests/ao_soc_security_subsystem/mpu/mpu_cluster_test/test_ROM_access - command: make clean all run - verif_tests/timer_unit: - path: ./pulp_tests/verif_tests/timer_unit - command: make clean all run - testFPU: - path: ./pulp_tests/testFPU - command: make clean all run - event_unit/v3/hw_mutex: - path: ./pulp_tests/event_unit/v3/hw_mutex - command: make clean all run - event_unit/v3/test_barrier_with_irq: - path: ./pulp_tests/event_unit/v3/test_barrier_with_irq - command: make clean all run - event_unit/v3/dispatch: - path: ./pulp_tests/event_unit/v3/dispatch - command: make clean all run - old_tests/testSPI_slave: - path: ./pulp_tests/old_tests/testSPI_slave - command: make clean all run - old_tests/periphs/v2/I2S_pdm: - path: ./pulp_tests/old_tests/periphs/v2/I2S_pdm - command: make clean all run - old_tests/periphs/v2/SPI_SDVT/normal_device_read: - path: ./pulp_tests/old_tests/periphs/v2/SPI_SDVT/normal_device_read - command: make clean all run - old_tests/periphs/v2/SPI_SDVT/normal_device_burst_read: - path: ./pulp_tests/old_tests/periphs/v2/SPI_SDVT/normal_device_burst_read - command: make clean all run - old_tests/periphs/v2/SPI_SDVT/normal_device_write: - path: ./pulp_tests/old_tests/periphs/v2/SPI_SDVT/normal_device_write - command: make clean all run - old_tests/periphs/v2/SPI: - path: ./pulp_tests/old_tests/periphs/v2/SPI - command: make clean all run - old_tests/periphs/v2/CPI_SDVT: - path: ./pulp_tests/old_tests/periphs/v2/CPI_SDVT - command: make clean all run - old_tests/periphs/v1/testUDMA: - path: ./pulp_tests/old_tests/periphs/v1/testUDMA - command: make clean all run - old_tests/periphs/v1/testSPI: - path: ./pulp_tests/old_tests/periphs/v1/testSPI - command: make clean all run - old_tests/periphs/v1/I2C: - path: ./pulp_tests/old_tests/periphs/v1/I2C - command: make clean all run - old_tests/periphs/v1/SPIM: - path: ./pulp_tests/old_tests/periphs/v1/SPIM - command: make clean all run - old_tests/test_hwcrypt/v1: - path: ./pulp_tests/old_tests/test_hwcrypt/v1 - command: make clean all run - old_tests/test_icache_ctrl: - path: ./pulp_tests/old_tests/test_icache_ctrl - command: make clean all run - old_tests/testPipeStage: - path: ./pulp_tests/old_tests/testPipeStage - command: make clean all run - old_tests/testL2: - path: ./pulp_tests/old_tests/testL2 - command: make clean all run - old_tests/testCVP: - path: ./pulp_tests/old_tests/testCVP - command: make clean all run - old_tests/testClusterControl: - path: ./pulp_tests/old_tests/testClusterControl - command: make clean all run - old_tests/preloading: - path: ./pulp_tests/old_tests/preloading - command: make clean all run - old_tests/efuse: - path: ./pulp_tests/old_tests/efuse - command: make clean all run - old_tests/flash_programmer: - path: ./pulp_tests/old_tests/flash_programmer - command: make clean all run - old_tests/testLoader: - path: ./pulp_tests/old_tests/testLoader - command: make clean all run - old_tests/patronus/periphs/KECCAK: - path: ./pulp_tests/old_tests/patronus/periphs/KECCAK - command: make clean all run - old_tests/patronus/testCSR: - path: ./pulp_tests/old_tests/patronus/testCSR - command: make clean all run - old_tests/patronus/testPrivDelegate: - path: ./pulp_tests/old_tests/patronus/testPrivDelegate - command: make clean all run - old_tests/patronus/testPrivCSR: - path: ./pulp_tests/old_tests/patronus/testPrivCSR - command: make clean all run - old_tests/patronus/testMMU: - path: ./pulp_tests/old_tests/patronus/testMMU - command: make clean all run - old_tests/Matrix_mul_test/src: - path: ./pulp_tests/old_tests/Matrix_mul_test/src - command: make clean all run - old_tests/hostHello: - path: ./pulp_tests/old_tests/hostHello - command: make clean all run - old_tests/vivosoc2/testGate: - path: ./pulp_tests/old_tests/vivosoc2/testGate - command: make clean all run - old_tests/vivosoc2/testClkDiv: - path: ./pulp_tests/old_tests/vivosoc2/testClkDiv - command: make clean all run - old_tests/testClusterTimer: - path: ./pulp_tests/old_tests/testClusterTimer - command: make clean all run - old_tests/testFcTimer: - path: ./pulp_tests/old_tests/testFcTimer - command: make clean all run - old_tests/testTCDM: - path: ./pulp_tests/old_tests/testTCDM - command: make clean all run - old_tests/testI2S: - path: ./pulp_tests/old_tests/testI2S - command: make clean all run - old_tests/testAnalog: - path: ./pulp_tests/old_tests/testAnalog - command: make clean all run - old_tests/efuse_programming: - path: ./pulp_tests/old_tests/efuse_programming - command: make clean all run - old_tests/test_fctdcm: - path: ./pulp_tests/old_tests/test_fctdcm - command: make clean all run - old_tests/testFCicache: - path: ./pulp_tests/old_tests/testFCicache - command: make clean all run - old_tests/businesscardBlink: - path: ./pulp_tests/old_tests/businesscardBlink - command: make clean all run - old_tests/test_lvds_divider: - path: ./pulp_tests/old_tests/test_lvds_divider - command: make clean all run - old_tests/test_udma_igloocam: - path: ./pulp_tests/old_tests/test_udma_igloocam - command: make clean all run - old_tests/testHWCE/v2: - path: ./pulp_tests/old_tests/testHWCE/v2 - command: make clean all run - old_tests/testHWCE/v4: - path: ./pulp_tests/old_tests/testHWCE/v4 - command: make clean all run - old_tests/testHWCE/v3: - path: ./pulp_tests/old_tests/testHWCE/v3 - command: make clean all run - old_tests/eventUnit/v1/event_interrupt: - path: ./pulp_tests/old_tests/eventUnit/v1/event_interrupt - command: make clean all run - old_tests/test_vip_rdwr: - path: ./pulp_tests/old_tests/test_vip_rdwr - command: make clean all run - old_tests/testAdc_doubleBuff: - path: ./pulp_tests/old_tests/testAdc_doubleBuff - command: make clean all run - old_tests/test_fc_to_cluster_eu: - path: ./pulp_tests/old_tests/test_fc_to_cluster_eu - command: make clean all run - old_tests/testIcache/powerof2: - path: ./pulp_tests/old_tests/testIcache/powerof2 - command: make clean all run - old_tests/testIcache/large: - path: ./pulp_tests/old_tests/testIcache/large - command: make clean all run - old_tests/testIcache/prime: - path: ./pulp_tests/old_tests/testIcache/prime - command: make clean all run - old_tests/testBarrier: - path: ./pulp_tests/old_tests/testBarrier - command: make clean all run - old_tests/testAndSet: - path: ./pulp_tests/old_tests/testAndSet - command: make clean all run - old_tests/testMCHAN/v4: - path: ./pulp_tests/old_tests/testMCHAN/v4 - command: make clean all run - old_tests/testMCHAN/v5: - path: ./pulp_tests/old_tests/testMCHAN/v5 - command: make clean all run - old_tests/gap/riscy_dbg_via_spis: - path: ./pulp_tests/old_tests/gap/riscy_dbg_via_spis - command: make clean all run - old_tests/gap/periphs/tcdm_l2Tol2: - path: ./pulp_tests/old_tests/gap/periphs/tcdm_l2Tol2 - command: make clean all run - old_tests/gap/periphs/tcdm: - path: ./pulp_tests/old_tests/gap/periphs/tcdm - command: make clean all run - old_tests/helloworld: - path: ./pulp_tests/old_tests/helloworld - command: make clean all run - old_tests/testHWCE_onlyconv: - path: ./pulp_tests/old_tests/testHWCE_onlyconv - command: make clean all run - old_tests/testFLL: - path: ./pulp_tests/old_tests/testFLL - command: make clean all run - old_tests/initTCDM: - path: ./pulp_tests/old_tests/initTCDM - command: make clean all run - old_tests/testGPIO: - path: ./pulp_tests/old_tests/testGPIO - command: make clean all run - old_tests/bugs/irqDuringWhile: - path: ./pulp_tests/old_tests/bugs/irqDuringWhile - command: make clean all run - old_tests/bench_tiny: - path: ./pulp_tests/old_tests/bench_tiny - command: make clean all run - old_tests/test_fceu: - path: ./pulp_tests/old_tests/test_fceu - command: make clean all run - old_tests/test_debug_unit: - path: ./pulp_tests/old_tests/test_debug_unit - command: make clean all run - old_tests/test_cluster_to_fctcdm: - path: ./pulp_tests/old_tests/test_cluster_to_fctcdm - command: make clean all run - old_tests/fcHello_bug: - path: ./pulp_tests/old_tests/fcHello_bug - command: make clean all run - old_tests/testMMU: - path: ./pulp_tests/old_tests/testMMU - command: make clean all run - old_tests/test_cluster_to_fc_eu: - path: ./pulp_tests/old_tests/test_cluster_to_fc_eu - command: make clean all run - old_tests/test_udma_zynq: - path: ./pulp_tests/old_tests/test_udma_zynq - command: make clean all run - periphs/spi/v2/flash: - path: ./pulp_tests/periphs/spi/v2/flash - command: make clean all run - periphs/i2c/v1/m24fc1025_i2c_bare: - path: ./pulp_tests/periphs/i2c/v1/m24fc1025_i2c_bare - command: make clean all run - periphs/cpi/basic: - path: ./pulp_tests/periphs/cpi/basic - command: make clean all run - -ml_tests: - mlDotp: - path: ./ml_tests/mlDotp - command: make clean all run - mlSchur: - path: ./ml_tests/mlSchur - command: make clean all run - mlGemm: - path: ./ml_tests/mlGemm - command: make clean all run - mlSin: - path: ./ml_tests/mlSin - command: make clean all run - mlSvd: - path: ./ml_tests/mlSvd - command: make clean all run - mlButter: - path: ./ml_tests/mlButter - command: make clean all run - mlGradDir: - path: ./ml_tests/mlGradDir - command: make clean all run - mlRbf: - path: ./ml_tests/mlRbf - command: make clean all run - mlLog: - path: ./ml_tests/mlLog - command: make clean all run - testFPU: - path: ./ml_tests/testFPU - command: make clean all run - mlAxpy: - path: ./ml_tests/mlAxpy - command: make clean all run - mlHomErr: - path: ./ml_tests/mlHomErr - command: make clean all run - mlHom: - path: ./ml_tests/mlHom - command: make clean all run - mlFir: - path: ./ml_tests/mlFir - command: make clean all run - mlBilat: - path: ./ml_tests/mlBilat - command: make clean all run - mlGivens: - path: ./ml_tests/mlGivens - command: make clean all run - mlWdotp: - path: ./ml_tests/mlWdotp - command: make clean all run - seizure-detection_dma: - path: ./ml_tests/seizure/seizure-detection_dma - command: make clean all run - mlDist: - path: ./ml_tests/mlDist - command: make clean all run - testAPU: - path: ./ml_tests/testAPU - command: make clean all run - mlGemv: - path: ./ml_tests/mlGemv - command: make clean all run - mlChol: - path: ./ml_tests/mlChol - command: make clean all run - mlGrad: - path: ./ml_tests/mlGrad - command: make clean all run - mlDct: - path: ./ml_tests/mlDct - command: make clean all run - mlQr: - path: ./ml_tests/mlQr - command: make clean all run - -riscv_tests: - testBitManipulation: - path: ./riscv_tests/testBitManipulation - command: make clean all run - test_fc_itc: - path: ./riscv_tests/test_fc_itc - command: make clean all run - testVecCmp: - path: ./riscv_tests/testVecCmp - command: make clean all run - testAddSubNorm: - path: ./riscv_tests/testAddSubNorm - command: make clean all run - testIRQ: - path: ./riscv_tests/testIRQ - command: make clean all run - testCSR: - path: ./riscv_tests/testCSR - command: make clean all run - testExceptions: - path: ./riscv_tests/testExceptions - command: make clean all run - debug: - path: ./riscv_tests/debug - command: make clean all run - testSimpleFPU: - path: ./riscv_tests/testSimpleFPU - command: make clean all run - testMisaligned: - path: ./riscv_tests/testMisaligned - command: make clean all run - testALU: - path: ./riscv_tests/testALU - command: make clean all run - testMAC3: - path: ./riscv_tests/testMAC3 - command: make clean all run - testEventsFlex: - path: ./riscv_tests/testEventsFlex - command: make clean all run - testVecArith: - path: ./riscv_tests/testVecArith - command: make clean all run - testDotMul: - path: ./riscv_tests/testDotMul - command: make clean all run - testIRQ_dis_en: - path: ./riscv_tests/testIRQ_dis_en - command: make clean all run - testVecLogic: - path: ./riscv_tests/testVecLogic - command: make clean all run - testComplex: - path: ./riscv_tests/testComplex - command: make clean all run - testCnt: - path: ./riscv_tests/testCnt - command: make clean all run - testVecRelat: - path: ./riscv_tests/testVecRelat - command: make clean all run - testCSR_1.7: - path: ./riscv_tests/testCSR_1.7 - command: make clean all run - testShufflePack: - path: ./riscv_tests/testShufflePack - command: make clean all run - testMUL: - path: ./riscv_tests/testMUL - command: make clean all run - testHWLP: - path: ./riscv_tests/testHWLP - command: make clean all run - testMacNorm: - path: ./riscv_tests/testMacNorm - command: make clean all run - testDivRem: - path: ./riscv_tests/testDivRem - command: make clean all run - testDivRem/stimuli: - path: ./riscv_tests/testDivRem/stimuli - command: make clean all run - testVariadic: - path: ./riscv_tests/testVariadic - command: make clean all run - testMAC: - path: ./riscv_tests/testMAC - command: make clean all run - testSecure: - path: ./riscv_tests/testSecure - command: make clean all run - testClip: - path: ./riscv_tests/testClip - command: make clean all run - official: - path: ./riscv_tests/official - command: make clean all run - testLoadStore: - path: ./riscv_tests/testLoadStore - command: make clean all run - testALUExt: - path: ./riscv_tests/testALUExt - command: make clean all run - testBuiltins: - path: ./riscv_tests/testBuiltins - command: make clean all run - testDebug_FC: - path: ./riscv_tests/testDebug_FC - command: make clean all run diff --git a/tests/testset.cfg b/tests/testset.cfg deleted file mode 100644 index 4ab351fa..00000000 --- a/tests/testset.cfg +++ /dev/null @@ -1,18 +0,0 @@ - -from plptest import * - -TestConfig = c = {} - -tests = Testset( - name = 'PULP Software Tests', - files = [ - "ml_tests/testset.cfg", - "parallel_bare_tests/testset.cfg", - "riscv_tests/testset.cfg", - "sequential_bare_tests/testset.cfg", - "rt-tests/testset.cfg", - "pulp_tests/testset.cfg" - ] -) - -c['testsets'] = [ tests ] diff --git a/update-tests b/update-tests deleted file mode 100755 index d6d5d654..00000000 --- a/update-tests +++ /dev/null @@ -1,25 +0,0 @@ -#!/bin/bash -e - -# This is the script you use when you do a local test -# getting tests -git clone git@iis-git.ee.ethz.ch:pulp-tests/ml_tests.git \ - tests/ml_tests -git clone git@iis-git.ee.ethz.ch:pulp-sw/pulp_tests.git \ - tests/pulp_tests -git clone git@iis-git.ee.ethz.ch:pulp-tests/rt-tests.git \ - tests/rt-tests -git clone git@iis-git.ee.ethz.ch:pulp-sw/parallel_bare_tests.git \ - tests/parallel_bare_tests -git clone git@iis-git.ee.ethz.ch:pulp-sw/riscv_tests.git \ - tests/riscv_tests -git clone git@iis-git.ee.ethz.ch:pulp-sw/sequential_bare_tests.git \ - tests/sequential_bare_tests - -# using "stable" versions -echo "Using stable versions of tests" -git -C tests/ml_tests checkout -q 9c49595a3dd9a0a2a776518b7de6c2cda903142b -git -C tests/pulp_tests checkout -q ce367a85b9d4b15e92b57cdfa7b715ecf6a92a45 -git -C tests/rt-tests checkout -q f6bfda35cdbd363a94e7c8957fa7efc27093b106 -git -C tests/parallel_bare_tests checkout -q 91b1bad09d088df9140f5391a87df3f6ebfab344 -git -C tests/riscv_tests checkout -q 2ce43f33cc6f983e4deb3f79dec9663e02c10af5 -git -C tests/sequential_bare_tests checkout -q f2cf176414a779b7fae31836d137cfaf6e78b719 diff --git a/update-tests-gitlab b/update-tests-gitlab deleted file mode 100755 index ea4ae7e4..00000000 --- a/update-tests-gitlab +++ /dev/null @@ -1,27 +0,0 @@ -#!/bin/bash -e -# This script is solely used on gitlab - -GITLAB=iis-git.ee.ethz.ch - -# getting tests -git clone https://gitlab-ci-token:${CI_JOB_TOKEN}@${GITLAB}/pulp-tests/ml_tests.git \ - tests/ml_tests -git clone https://gitlab-ci-token:${CI_JOB_TOKEN}@${GITLAB}/pulp-sw/pulp_tests.git \ - tests/pulp_tests -git clone https://gitlab-ci-token:${CI_JOB_TOKEN}@${GITLAB}/pulp-tests/rt-tests.git \ - tests/rt-tests -git clone https://gitlab-ci-token:${CI_JOB_TOKEN}@${GITLAB}/pulp-sw/parallel_bare_tests.git \ - tests/parallel_bare_tests -git clone https://gitlab-ci-token:${CI_JOB_TOKEN}@${GITLAB}/pulp-sw/riscv_tests.git \ - tests/riscv_tests -git clone https://gitlab-ci-token:${CI_JOB_TOKEN}@${GITLAB}/pulp-sw/sequential_bare_tests.git \ - tests/sequential_bare_tests - -# using "stable" versions -echo "Using stable versions of tests" -git -C tests/ml_tests checkout -q 9c49595a3dd9a0a2a776518b7de6c2cda903142b -git -C tests/pulp_tests checkout -q ce367a85b9d4b15e92b57cdfa7b715ecf6a92a45 -git -C tests/rt-tests checkout -q f6bfda35cdbd363a94e7c8957fa7efc27093b106 -git -C tests/parallel_bare_tests checkout -q 91b1bad09d088df9140f5391a87df3f6ebfab344 -git -C tests/riscv_tests checkout -q 2ce43f33cc6f983e4deb3f79dec9663e02c10af5 -git -C tests/sequential_bare_tests checkout -q f2cf176414a779b7fae31836d137cfaf6e78b719 diff --git a/utils/generate-makefile-help.sh b/utils/generate-makefile-help.sh new file mode 100755 index 00000000..fb85ff38 --- /dev/null +++ b/utils/generate-makefile-help.sh @@ -0,0 +1,79 @@ +#!/bin/bash + +# Slightly modified versoin of hilnius excellent bash script for +# self-documenting makefiles +# (https://gist.github.com/klmr/575726c7e05d8780505a). This version of his +# script supports multiple makefiles (i.e. mk files that include other files). +# The bash script expects a MAKEFILES variable with a list of all makefiles to +# process. This list can obtained easily by passing the current content of the +# makefile specila variable $(MAKEFILE_LIST) at the very end of your file to be +# docummented. See the accompanying utils.mk how to properly use this bash script. + +RULE_COLOR="$(tput setaf 6)" +SECTION_COLOR="$(tput setaf 3)" +VARIABLE_COLOR="$(tput setaf 2)" +VALUE_COLOR="$(tput setaf 1)" +CLEAR_STYLE="$(tput sgr0)" +TARGET_STYLED_HELP_NAME="${RULE_COLOR}TARGET${CLEAR_STYLE}" +ARGUMENTS_HELP_NAME="${VARIABLE_COLOR}ARGUMENT${CLEAR_STYLE}=${VALUE_COLOR}VALUE${CLEAR_STYLE}" + +echo "Usage: make [$TARGET_STYLED_HELP_NAME [$TARGET_STYLED_HELP_NAME ...]] [$ARGUMENTS_HELP_NAME [$ARGUMENTS_HELP_NAME ...]]" +echo "${SECTION_COLOR}Targets:${CLEAR_STYLE}" +echo " ${RULE_COLOR}help${CLEAR_STYLE}" +echo " Get help for commands in this folder" +echo "" + +TARGET_REGEX="^[a-zA-Z0-9%_\/%-]+:" +SECTION_REGEX="^##\s*@section\s*(.*)$" +DOCBLOCK_REGEX="^##\s*(.*)$" +PARAM_REGEX="@param\s+([a-zA-Z_]+)(=([^\s]+))?\s*(.*$)?" + +COMMENT="" +PARAMS="" +PARAMS_DOC="" + +for FILE in $MAKEFILES +do +cat $FILE | while read line + do + # do something with $line here + if [[ ! -z $line ]] + then + if [[ $line =~ $SECTION_REGEX ]] + then + SECTION_NAME=$(echo $line | sed -e "s/^##\s*@section\s*\(.*\)$/\1/g") + echo "$SECTION_COLOR$SECTION_NAME$CLEAR_STYLE:" + elif [[ $line =~ $TARGET_REGEX ]] + then + # if there is no comment for this target, we don't display it in the docs to keep private targets hidden + if [[ ! -z $COMMENT ]] + then + TARGET=$(echo $line | sed -e "s/^\([a-zA-Z0-9%_\/%-]\+\):.*/\1/g") + echo " $RULE_COLOR$TARGET$CLEAR_STYLE $PARAMS" + echo -e "$COMMENT" + if [[ ! -z $PARAMS_DOC ]] + then + echo " Params:" + echo -e "$PARAMS_DOC" + fi + fi + COMMENT="" + PARAMS="" + PARAMS_DOC="" + elif [[ $line =~ $PARAM_REGEX ]] + then + PARAM=$(echo $line | sed -e "s/##\s*@param\s\+\([a-zA-Z_]\+\)\(=\([^[:space:]]\+\)\)\?\s*\(.*\)\?$/${VARIABLE_COLOR}\1${CLEAR_STYLE}=${VALUE_COLOR}\3${CLEAR_STYLE}/g") + PARAM_DOC=$(echo $line | sed -e "s/##\s*@param\s\+\([a-zA-Z_]\+\)\(=\([^[:space:]]\+\)\)\?\s*\(.*\)\?$/- \1 (example: \3) \4/g") + PARAMS="${PARAMS}${PARAM} " + PARAMS_DOC="${PARAMS_DOC} ${PARAM_DOC}\n" + elif [[ $line =~ $DOCBLOCK_REGEX ]] + then + # echo "doc : $line" + # echo $line | sed -e "s/^##\s*\(.*\)$/\1/g" + LINE_CLEANED=$(echo $line | sed -e "s/^##\s*\(.*\)$/\1/g") + COMMENT="${COMMENT} $LINE_CLEANED\n" + fi + fi + done +done + diff --git a/utils/help.mk b/utils/help.mk new file mode 100644 index 00000000..89045826 --- /dev/null +++ b/utils/help.mk @@ -0,0 +1,146 @@ +ifndef help_mk +help_mk = 1 + +mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST))) +mkfile_dir := $(dir $(mkfile_path)) + +# Makefile Autodocumentation: +# +# This utility makefile in combination with the generate-makefile-help.sh shell +# script (also in this folder) allows for self-documenting makefiles by means of +# special comments. To enable support for this, just include this utils.mk AT +# THE VERY END of your Makefile to be documented +# +# This will provide a new phony target called 'help' that will print all +# documented targets in very nice colored format. +# +# Here is the example on how to write documentation from the original author of +#the script (hilnius) + + + +# # Line to add to any Supermood Makefile - generates the 'help' target from the Makefile comments +# include ${SUPERMOOD_ROOT}/tools/Makefile-help.mk +# +# ## @section Installation +# +# ## Install the Supermood environment (adds $SUPERMOOD_ROOT to your shell) +# install: +# @echo Setting SUPERMOOD_ROOT environment +# @./tools/bashrc-setup +# +# ## @section Supermood Release log generation +# +# ## Generates the production release log from git history. +# ## Post the output to the #releases slack channel +# ## @param FROM=1.234.0 Git reference from which we show the log +# ## @param TO=1.235.0 Git reference to which we show the log +# releaselog: +# @./internal/releaselog/display-release-log $$FROM $$TO +# +# ## Generates the full release log (including [no-releaselog] commits) from git history. +# ## Post the output to your squad's channel or #tech-team +# ## @param FROM=1.234.0 Git reference from which we show the log +# ## @param TO=1.235.0 Git reference to which we show the log +# full-releaselog: +# @./internal/releaselog/display-full-release-log $$FROM $$TO +# +# # This is just hidden, probably a target we don't want people to call +# sometarget: any other file +# echo "hello" +# +# .PHONY: install releaselog full-releaselog +# include utils/utils.mk + + +# ANSI Text Effects + +# Reset +Color_Off='\033[0m' # Text Reset + +# Regular Colors +Black='\033[0;30m' # Black +Red='\033[0;31m' # Red +Green='\033[0;32m' # Green +Yellow='\033[0;33m' # Yellow +Blue='\033[0;34m' # Blue +Purple='\033[0;35m' # Purple +Cyan='\033[0;36m' # Cyan +White='\033[0;37m' # White + +# Bold +BBlack='\033[1;30m' # Black +BRed='\033[1;31m' # Red +BGreen='\033[1;32m' # Green +BYellow='\033[1;33m' # Yellow +BBlue='\033[1;34m' # Blue +BPurple='\033[1;35m' # Purple +BCyan='\033[1;36m' # Cyan +BWhite='\033[1;37m' # White + +# Underline +UBlack='\033[4;30m' # Black +URed='\033[4;31m' # Red +UGreen='\033[4;32m' # Green +UYellow='\033[4;33m' # Yellow +UBlue='\033[4;34m' # Blue +UPurple='\033[4;35m' # Purple +UCyan='\033[4;36m' # Cyan +UWhite='\033[4;37m' # White + +# Background +On_Black='\033[40m' # Black +On_Red='\033[41m' # Red +On_Green='\033[42m' # Green +On_Yellow='\033[43m' # Yellow +On_Blue='\033[44m' # Blue +On_Purple='\033[45m' # Purple +On_Cyan='\033[46m' # Cyan +On_White='\033[47m' # White + +# High Intensity +IBlack='\033[0;90m' # Black +IRed='\033[0;91m' # Red +IGreen='\033[0;92m' # Green +IYellow='\033[0;93m' # Yellow +IBlue='\033[0;94m' # Blue +IPurple='\033[0;95m' # Purple +ICyan='\033[0;96m' # Cyan +IWhite='\033[0;97m' # White + +# Bold High Intensity +BIBlack='\033[1;90m' # Black +BIRed='\033[1;91m' # Red +BIGreen='\033[1;92m' # Green +BIYellow='\033[1;93m' # Yellow +BIBlue='\033[1;94m' # Blue +BIPurple='\033[1;95m' # Purple +BICyan='\033[1;96m' # Cyan +BIWhite='\033[1;97m' # White + +# High Intensity backgrounds +On_IBlack='\033[0;100m' # Black +On_IRed='\033[0;101m' # Red +On_IGreen='\033[0;102m' # Green +On_IYellow='\033[0;103m' # Yellow +On_IBlue='\033[0;104m' # Blue +On_IPurple='\033[0;105m' # Purple +On_ICyan='\033[0;106m' # Cyan +On_IWhite='\033[0;107m' # White + + +.PHONY: help +help: +ifdef HELP_TITLE + @echo -e $(BPurple)$(HELP_TITLE)$(Color_Off) +endif +ifdef HELP_DESCRIPTION + @echo $(HELP_DESCRIPTION) +endif + @echo "" + @MAKEFILES="$(MAKEFILE_LIST)" $(mkfile_dir)generate-makefile-help.sh + +.PHONY: list-all-targets +list-all-targets: + @LC_ALL=C $(MAKE) -pRrq -f $(THIS_FILE) : 2>/dev/null | awk -v RS= -F: '/(^|\n)# Files(\n|$$)/,/(^|\n)# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$@$$' +endif diff --git a/utils/iis-env.mk b/utils/iis-env.mk new file mode 100644 index 00000000..7e4761ed --- /dev/null +++ b/utils/iis-env.mk @@ -0,0 +1,23 @@ +# Copyright 2024 ETH Zurich and University of Bologna +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Author: Michael Rogenmoser + +# This utility makefile sets up appropriate environment variables when +# working at IIS + +ifneq (,$(wildcard /etc/iis.version)) +$(info "Using IIS environment") +VSIM_BIN ?= questa-2023.4-zr vsim +endif diff --git a/utils/utils.mk b/utils/utils.mk new file mode 100644 index 00000000..7a807c6f --- /dev/null +++ b/utils/utils.mk @@ -0,0 +1,54 @@ +# Copyright 2022 ETH Zurich and University of Bologna +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Author: Manuel Eggimann + +# This utility makefile sets up a virtual environment in a newly create .venv +# subdirectory of this folder and install various commonly used python tools +# within it. + +ifndef utils_mk +utils_mk=1 + +mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST))) +mkfile_dir := $(dir $(mkfile_path)) +export PULPISSIMO_UTILS=$(mkfile_dir)/bin + +VENVDIR?=$(mkfile_path)/.venv +REQUIREMENTS_TXT?=$(wildcard requirements.txt) +include $(mkfile_dir)/venv.mk + +$(PULPISSIMO_UTILS)/padrick: +ifeq (,$(widlcard bin/padrick)) + mkdir -p $(PULPISSIMO_UTILS) + cd $(PULPISSIMO_UTILS) && curl https://api.github.com/repos/pulp-platform/padrick/releases/tags/v0.3.6 \ + | grep "browser_download_url.*Padrick-x86_64.AppImage" \ + | cut -d : -f 2,3 \ + | tr -d \" \ + | wget -qi - + mv $(PULPISSIMO_UTILS)/Padrick-x86_64.AppImage $(PULPISSIMO_UTILS)/padrick + chmod a+x $(PULPISSIMO_UTILS)/padrick +endif + +$(PULPISSIMO_UTILS)/bender: +ifeq (,$(wildcard bin/bender)) + mkdir -p $(PULPISSIMO_UTILS) + cd $(PULPISSIMO_UTILS) && curl --proto '=https' --tlsv1.2 -sSf https://pulp-platform.github.io/bender/init \ + | bash -s -- 0.28.0 + touch $(PULPISSIMO_UTILS)/bender +endif + + +export PULPISSIMO_UTILS=$(mkfile_dir)/bin +endif diff --git a/utils/venv.mk b/utils/venv.mk new file mode 100644 index 00000000..c79b9bbc --- /dev/null +++ b/utils/venv.mk @@ -0,0 +1,274 @@ +# +# SEAMLESSLY MANAGE PYTHON VIRTUAL ENVIRONMENT WITH A MAKEFILE +# +# https://github.com/sio/Makefile.venv v2022.07.20 +# +# +# Insert `include Makefile.venv` at the bottom of your Makefile to enable these +# rules. +# +# When writing your Makefile use '$(VENV)/python' to refer to the Python +# interpreter within virtual environment and '$(VENV)/executablename' for any +# other executable in venv. +# +# This Makefile provides the following targets: +# venv +# Use this as a dependency for any target that requires virtual +# environment to be created and configured +# python, ipython +# Use these to launch interactive Python shell within virtual environment +# shell, bash, zsh +# Launch interactive command line shell. "shell" target launches the +# default shell Makefile executes its rules in (usually /bin/sh). +# "bash" and "zsh" can be used to refer to the specific desired shell. +# show-venv +# Show versions of Python and pip, and the path to the virtual environment +# clean-venv +# Remove virtual environment +# $(VENV)/executable_name +# Install `executable_name` with pip. Only packages with names matching +# the name of the corresponding executable are supported. +# Use this as a lightweight mechanism for development dependencies +# tracking. E.g. for one-off tools that are not required in every +# developer's environment, therefore are not included into +# requirements.txt or setup.py. +# Note: +# Rules using such target or dependency MUST be defined below +# `include` directive to make use of correct $(VENV) value. +# Example: +# codestyle: $(VENV)/pyflakes +# $(VENV)/pyflakes . +# See `ipython` target below for another example. +# +# This Makefile can be configured via following variables: +# PY +# Command name for system Python interpreter. It is used only initially to +# create the virtual environment +# Default: python3 +# REQUIREMENTS_TXT +# Space separated list of paths to requirements.txt files. +# Paths are resolved relative to current working directory. +# Default: requirements.txt +# +# Non-existent files are treated as hard dependencies, +# recipes for creating such files must be provided by the main Makefile. +# Providing empty value (REQUIREMENTS_TXT=) turns off processing of +# requirements.txt even when the file exists. +# SETUP_PY +# Space separated list of paths to setup.py files. +# Corresponding packages will be installed into venv in editable mode +# along with all their dependencies +# Default: setup.py +# +# Non-existent and empty values are treated in the same way as for REQUIREMENTS_TXT. +# WORKDIR +# Parent directory for the virtual environment. +# Default: current working directory. +# VENVDIR +# Python virtual environment directory. +# Default: $(WORKDIR)/.venv +# +# This Makefile was written for GNU Make and may not work with other make +# implementations. +# +# +# Copyright (c) 2019-2020 Vitaly Potyarkin +# +# Licensed under the Apache License, Version 2.0 +# +# + + +# +# Configuration variables +# + +WORKDIR?=. +VENVDIR?=$(WORKDIR)/.venv +REQUIREMENTS_TXT?=$(wildcard requirements.txt) # Multiple paths are supported (space separated) +SETUP_PY?=$(wildcard setup.py) # Multiple paths are supported (space separated) +SETUP_CFG?=$(foreach s,$(SETUP_PY),$(wildcard $(patsubst %setup.py,%setup.cfg,$(s)))) +MARKER=.initialized-with-Makefile.venv + + +# +# Python interpreter detection +# + +_PY_AUTODETECT_MSG=Detected Python interpreter: $(PY). Use PY environment variable to override + +ifeq (ok,$(shell test -e /dev/null 2>&1 && echo ok)) +NULL_STDERR=2>/dev/null +else +NULL_STDERR=2>NUL +endif + +ifndef PY +_PY_OPTION:=python3 +ifeq (ok,$(shell $(_PY_OPTION) -c "print('ok')" $(NULL_STDERR))) +PY=$(_PY_OPTION) +endif +endif + +ifndef PY +_PY_OPTION:=$(VENVDIR)/bin/python +ifeq (ok,$(shell $(_PY_OPTION) -c "print('ok')" $(NULL_STDERR))) +PY=$(_PY_OPTION) +$(info $(_PY_AUTODETECT_MSG)) +endif +endif + +ifndef PY +_PY_OPTION:=$(subst /,\,$(VENVDIR)/Scripts/python) +ifeq (ok,$(shell $(_PY_OPTION) -c "print('ok')" $(NULL_STDERR))) +PY=$(_PY_OPTION) +$(info $(_PY_AUTODETECT_MSG)) +endif +endif + +ifndef PY +_PY_OPTION:=py -3 +ifeq (ok,$(shell $(_PY_OPTION) -c "print('ok')" $(NULL_STDERR))) +PY=$(_PY_OPTION) +$(info $(_PY_AUTODETECT_MSG)) +endif +endif + +ifndef PY +_PY_OPTION:=python +ifeq (ok,$(shell $(_PY_OPTION) -c "print('ok')" $(NULL_STDERR))) +PY=$(_PY_OPTION) +$(info $(_PY_AUTODETECT_MSG)) +endif +endif + +ifndef PY +define _PY_AUTODETECT_ERR +Could not detect Python interpreter automatically. +Please specify path to interpreter via PY environment variable. +endef +$(error $(_PY_AUTODETECT_ERR)) +endif + + +# +# Internal variable resolution +# + +VENV=$(VENVDIR)/bin +EXE= +# Detect windows +ifeq (win32,$(shell $(PY) -c "import __future__, sys; print(sys.platform)")) +VENV=$(VENVDIR)/Scripts +EXE=.exe +endif + +touch=touch $(1) +ifeq (,$(shell command -v touch $(NULL_STDERR))) +# https://ss64.com/nt/touch.html +touch=type nul >> $(subst /,\,$(1)) && copy /y /b $(subst /,\,$(1))+,, $(subst /,\,$(1)) +endif + +RM?=rm -f +ifeq (,$(shell command -v $(firstword $(RM)) $(NULL_STDERR))) +RMDIR:=rd /s /q +else +RMDIR:=$(RM) -r +endif + + +# +# Virtual environment +# + +.PHONY: venv +venv: $(VENV)/$(MARKER) + +.PHONY: clean-venv +clean-venv: + -$(RMDIR) "$(VENVDIR)" + +.PHONY: show-venv +show-venv: venv + @$(VENV)/python -c "import sys; print('Python ' + sys.version.replace('\n',''))" + @$(VENV)/pip --version + @echo venv: $(VENVDIR) + +.PHONY: debug-venv +debug-venv: + @echo "PATH (Shell)=$$PATH" + @$(MAKE) --version + $(info PATH (GNU Make)="$(PATH)") + $(info SHELL="$(SHELL)") + $(info PY="$(PY)") + $(info REQUIREMENTS_TXT="$(REQUIREMENTS_TXT)") + $(info SETUP_PY="$(SETUP_PY)") + $(info SETUP_CFG="$(SETUP_CFG)") + $(info VENVDIR="$(VENVDIR)") + $(info VENVDEPENDS="$(VENVDEPENDS)") + $(info WORKDIR="$(WORKDIR)") + + +# +# Dependencies +# + +ifneq ($(strip $(REQUIREMENTS_TXT)),) +VENVDEPENDS+=$(REQUIREMENTS_TXT) +endif + +ifneq ($(strip $(SETUP_PY)),) +VENVDEPENDS+=$(SETUP_PY) +endif +ifneq ($(strip $(SETUP_CFG)),) +VENVDEPENDS+=$(SETUP_CFG) +endif + +$(VENV): + $(PY) -m venv $(VENVDIR) + $(VENV)/python -m pip install --upgrade pip setuptools wheel + +$(VENV)/$(MARKER): $(VENVDEPENDS) | $(VENV) +ifneq ($(strip $(REQUIREMENTS_TXT)),) + $(VENV)/pip install $(foreach path,$(REQUIREMENTS_TXT),-r $(path)) +endif +ifneq ($(strip $(SETUP_PY)),) + $(VENV)/pip install $(foreach path,$(SETUP_PY),-e $(dir $(path))) +endif + $(call touch,$(VENV)/$(MARKER)) + + +# +# Interactive shells +# + +.PHONY: python +python: venv + exec $(VENV)/python + +.PHONY: ipython +ipython: $(VENV)/ipython + exec $(VENV)/ipython + +.PHONY: shell +shell: venv + . $(VENV)/activate && exec $(notdir $(SHELL)) + +.PHONY: bash zsh +bash zsh: venv + . $(VENV)/activate && exec $@ + + +# +# Commandline tools (wildcard rule, executable name must match package name) +# + +ifneq ($(EXE),) +$(VENV)/%: $(VENV)/%$(EXE) ; +.PHONY: $(VENV)/% +.PRECIOUS: $(VENV)/%$(EXE) +endif + +$(VENV)/%$(EXE): $(VENV)/$(MARKER) + $(VENV)/pip install --upgrade $* + $(call touch,$@)