fixing verilog placeholder pass #277
Open
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
|
@ptpan can you take a look? |
|
Hmm.. As I recall we had support for this before. Not sure why it is missing? |
Improve index handling in Bits and Signal classes
|
I also saw that in the Doc, which surprised me, this is not working. When I do a repo-wide search, the |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
The placeholder pass wrapper does not add a clock and reset signal, even when the metadata is set, which causes a missing pin warning from Verilator.
Furthermore, the name of the clock and reset might vary between designs; two new parameters are added so that the user can define the name of the clock signal and the reset signal.