rtl: code refactoring

rtl/channel_ctl.sv

@@ -48,19 +48,13 @@ logic [15:0] data_wr;
 wire addr_done = (wr_addr == reg_chan_len_i) & addr_en;
 wire data_done = (wr_addr == reg_chan_len_i) & data_en[0];
 
-genvar i;
-generate
-    for (i = 0; i < 16; i++) begin: ram_wr_en
-        assign ram_wr_en_o[i] = spi_byte_vld_i & data_wr[i];
-    end
-endgenerate
-
 assign reg_rd_addr_o = rd_addr;
 
-assign reg_wr_en_o   = spi_byte_vld_i & conf_wr;
+assign reg_wr_en_o   = conf_wr & spi_byte_vld_i;
 assign reg_wr_addr_o = wr_addr;
 
-assign ram_wr_done_o = spi_byte_vld_i & data_wr[reg_chan_cnt_i] & data_done;
+assign ram_wr_en_o   = data_wr & {16{spi_byte_vld_i}};
+assign ram_wr_done_o = data_wr[reg_chan_cnt_i] & data_done & spi_byte_vld_i;
 assign ram_wr_addr_o = wr_addr;
 
 assign ram_wr_byte_en_o = {addr_en, data_en};

rtl/regfile.sv

@@ -17,15 +17,15 @@ module regfile(
     input logic [2:0] reg_wr_addr_i,
     input logic [7:0] reg_wr_data_i,
 
+    output logic [7:0] reg_rd_data_o,
+
     output logic [7:0] reg_t0h_time_o,
     output logic [8:0] reg_t0s_time_o,
     output logic [7:0] reg_t1h_time_o,
     output logic [8:0] reg_t1s_time_o,
 
     output logic [7:0] reg_chan_len_o,
-    output logic [3:0] reg_chan_cnt_o,
-
-    output logic [7:0] reg_rd_data_o
+    output logic [3:0] reg_chan_cnt_o
 );
 
 logic [7:0] regs[5:0];
@@ -39,15 +39,15 @@ generate
     for (i = 0; i < 6; i++) begin: rd_data
         assign data[i + 2] = regs[i];
     end
-endgenerate
 
-assign reg_t0h_time_o = regs[0];
-assign reg_t0s_time_o = regs[0] + regs[1];
-assign reg_t1h_time_o = regs[2];
-assign reg_t1s_time_o = regs[2] + regs[3];
+    assign reg_t0h_time_o = regs[0];
+    assign reg_t0s_time_o = regs[0] + regs[1];
+    assign reg_t1h_time_o = regs[2];
+    assign reg_t1s_time_o = regs[2] + regs[3];
 
-assign reg_chan_len_o = regs[4];
-assign reg_chan_cnt_o = regs[5];
+    assign reg_chan_len_o = regs[4];
+    assign reg_chan_cnt_o = regs[5];
+endgenerate
 
 assign reg_rd_data_o = data[reg_rd_addr_i];
 

rtl/spi_slave.sv

@@ -21,26 +21,28 @@ module spi_slave(
     output logic [7:0] spi_byte_data_o
 );
 
-logic spi_sclk;
+logic spi_sclk_p;
+logic spi_sclk_n;
 
 logic [2:0] bit_sel;
 logic       bit_mosi;
 
-logic       byte_vld;
-logic [1:0] byte_rdy;
+logic byte_vld;
 
 logic [7:0] byte_mosi;
 logic [7:0] byte_miso;
 
-assign spi_miso_o      = byte_miso[7];
+assign spi_miso_o = byte_miso[7];
+
 assign spi_byte_vld_o  = byte_vld;
 assign spi_byte_data_o = byte_mosi;
 
 edge2en spi_sclk_en(
     .clk_i(clk_i),
     .rst_n_i(rst_n_i),
     .data_i(spi_sclk_i),
-    .pos_edge_o(spi_sclk)
+    .pos_edge_o(spi_sclk_p),
+    .neg_edge_o(spi_sclk_n)
 );
 
 always_ff @(posedge clk_i or negedge rst_n_i)
@@ -50,19 +52,17 @@ begin
         bit_mosi <= 1'b0;
 
         byte_vld <= 1'b0;
-        byte_rdy <= 2'b00;
 
         byte_mosi <= 8'h00;
         byte_miso <= 8'h00;
     end else begin
-        bit_sel  <= spi_cs_n_i ? 3'h0 : bit_sel + spi_sclk;
+        bit_sel  <= spi_cs_n_i ? 3'h0 : bit_sel + spi_sclk_p;
         bit_mosi <= spi_mosi_i;
 
-        byte_vld <= spi_sclk & (bit_sel == 3'h7);
-        byte_rdy <= {byte_rdy[0], byte_vld};
+        byte_vld <= spi_sclk_p & (bit_sel == 3'h7);
 
-        byte_mosi <= spi_sclk ? {byte_mosi[6:0], bit_mosi} : byte_mosi;
-        byte_miso <= byte_rdy[1] ? spi_byte_data_i : (spi_sclk ? {byte_miso[6:0], 1'b0} : byte_miso);
+        byte_mosi <= spi_sclk_p ? {byte_mosi[6:0], bit_mosi} : byte_mosi;
+        byte_miso <= spi_sclk_n ? ((bit_sel == 3'h0) ? spi_byte_data_i : {byte_miso[6:0], 1'b0}) : byte_miso;
     end
 end
 

sim/test_spi_slave.sv

@@ -43,7 +43,7 @@ initial begin
     clk_i   <= 1'b1;
     rst_n_i <= 1'b0;
 
-    spi_byte_data_i <= 8'h7e;
+    spi_byte_data_i <= 8'h6e;
 
     spi_cs_n_i <= 1'b1;
     spi_sclk_i <= 1'b0;
@@ -129,7 +129,7 @@ always begin
         spi_mosi_i <= 1'b1;  // BIT0
     #15 spi_sclk_i <= 1'b1;
 
-    for (integer i = 0; i < 24; i++) begin
+    for (integer i = 0; i < 1024; i++) begin
         #15 spi_sclk_i <= 1'b0;
             spi_mosi_i <= 1'b0;
         #15 spi_sclk_i <= 1'b1;