From cdee2f08d594172b1b0a940f99d6e74ee0fea1e8 Mon Sep 17 00:00:00 2001 From: Jack Chen Date: Wed, 10 Mar 2021 04:29:01 +0800 Subject: [PATCH] rtl: update to v4.0 --- README.md | 83 ++- ip/pll/pll.v | 33 +- ip/ram/{ram64.qip => ram256.qip} | 4 +- ip/ram/{ram64.v => ram256.v} | 50 +- ip/ram/{ram64_syn.v => ram256_syn.v} | 574 +++++++++--------- ...troller.qpf => neopixel_led_controller.qpf | 2 +- ...troller.qsf => neopixel_led_controller.qsf | 267 ++++---- ...troller.sdc => neopixel_led_controller.sdc | 3 +- rtl/channel_ctl.sv | 119 ++++ rtl/channel_out.sv | 76 +++ rtl/{edge_detect.sv => edge2en.sv} | 12 +- rtl/fps_counter.sv | 49 ++ rtl/layer_code.sv | 92 --- rtl/layer_conf.sv | 55 -- rtl/layer_ctrl.sv | 119 ---- rtl/pulse_counter.sv | 47 -- rtl/regfile.sv | 48 ++ rtl/{rst_sync.sv => rst_syn.sv} | 4 +- rtl/segment_led.sv | 28 +- rtl/spi_slave.sv | 56 +- rtl/{sys_ctrl.sv => sys_ctl.sv} | 16 +- rtl/top.sv | 246 +++----- rtl/{ws281x_ctrl.sv => waveform_ctl.sv} | 51 +- rtl/waveform_gen.sv | 56 ++ rtl/ws281x_code.sv | 53 -- rtl/ws281x_conf.sv | 36 -- sim/test_channel_ctl.sv | 146 +++++ sim/test_channel_out.sv | 133 ++++ sim/{test_edge_detect.sv => test_edge2en.sv} | 10 +- sim/test_layer_code.sv | 104 ---- sim/test_layer_conf.sv | 82 --- sim/test_layer_ctrl.sv | 119 ---- sim/test_regfile.sv | 100 +++ sim/{test_rst_sync.sv => test_rst_syn.sv} | 6 +- sim/test_spi_slave.sv | 31 +- ...st_ws281x_ctrl.sv => test_waveform_ctl.sv} | 39 +- ...st_ws281x_code.sv => test_waveform_gen.sv} | 30 +- sim/test_ws281x_conf.sv | 73 --- 38 files changed, 1433 insertions(+), 1619 deletions(-) rename ip/ram/{ram64.qip => ram256.qip} (87%) rename ip/ram/{ram64.v => ram256.v} (87%) rename ip/ram/{ram64_syn.v => ram256_syn.v} (84%) rename ws281x_cube_controller.qpf => neopixel_led_controller.qpf (96%) rename ws281x_cube_controller.qsf => neopixel_led_controller.qsf (64%) rename ws281x_cube_controller.sdc => neopixel_led_controller.sdc (80%) create mode 100644 rtl/channel_ctl.sv create mode 100644 rtl/channel_out.sv rename rtl/{edge_detect.sv => edge2en.sv} (71%) create mode 100644 rtl/fps_counter.sv delete mode 100644 rtl/layer_code.sv delete mode 100644 rtl/layer_conf.sv delete mode 100644 rtl/layer_ctrl.sv delete mode 100644 rtl/pulse_counter.sv create mode 100644 rtl/regfile.sv rename rtl/{rst_sync.sv => rst_syn.sv} (93%) rename rtl/{sys_ctrl.sv => sys_ctl.sv} (79%) rename rtl/{ws281x_ctrl.sv => waveform_ctl.sv} (51%) create mode 100644 rtl/waveform_gen.sv delete mode 100644 rtl/ws281x_code.sv delete mode 100644 rtl/ws281x_conf.sv create mode 100644 sim/test_channel_ctl.sv create mode 100644 sim/test_channel_out.sv rename sim/{test_edge_detect.sv => test_edge2en.sv} (83%) delete mode 100644 sim/test_layer_code.sv delete mode 100644 sim/test_layer_conf.sv delete mode 100644 sim/test_layer_ctrl.sv create mode 100644 sim/test_regfile.sv rename sim/{test_rst_sync.sv => test_rst_syn.sv} (87%) rename sim/{test_ws281x_ctrl.sv => test_waveform_ctl.sv} (54%) rename sim/{test_ws281x_code.sv => test_waveform_gen.sv} (61%) delete mode 100644 sim/test_ws281x_conf.sv diff --git a/README.md b/README.md index a57fc06..76f53c6 100644 --- a/README.md +++ b/README.md @@ -1,30 +1,30 @@ -WS281X Cube Controller -====================== +NeoPixel LED Controller +======================= -WS281X Cube Controller based on MAX10 FPGA. +NeoPixel LED Controller based on MAX10 FPGA. ## Main Features -* 4-wire SPI interface -* High refresh rate (up to 500fps@8x8x8) -* 8 parallel output data lines (64 LEDs per line) -* Configurable waveform generator (T0H, T0L, T1H, T1L) -* Configurable LED serial connection sequence (address linked list) +* 4-wire SPI interface (SCLK, MOSI, CS, DC) +* High refresh rate (500fps@8x8x8, 125fps@16x16x16) +* 16 parallel output channels (up to 256 LEDs per channel) +* Each output channel has a programmable circular linked list +* Each output channel has a programmable waveform generator (T0H, T0L, T1H, T1L) ## Pinout -| Input Port | FPGA Pin | Output Port | FPGA Pin | -| ---------: | :------- | :--------------: | :------: | -| clk_i | PIN_J5 | ws281x_code_o[7] | PIN_R5 | -| rst_n_i | PIN_R9 | ws281x_code_o[6] | PIN_L7 | -| dc_i | PIN_P15 | ws281x_code_o[5] | PIN_P4 | -| spi_sclk_i | PIN_R14 | ws281x_code_o[4] | PIN_L6 | -| spi_mosi_i | PIN_P12 | ws281x_code_o[3] | PIN_R3 | -| spi_cs_n_i | PIN_R11 | ws281x_code_o[2] | PIN_M5 | -| - | | ws281x_code_o[1] | PIN_P3 | -| - | | ws281x_code_o[0] | PIN_M4 | +| Input Port | FPGA Pin | Output Port | FPGA Pin | Output Port | FPGA Pin | +| ---------: | :------- | :----------------: | :------: | :-----------------: | :------: | +| clk_i | PIN_J5 | neopixel_code_o[7] | PIN_R5 | neopixel_code_o[15] | PIN_C8 | +| rst_n_i | PIN_R9 | neopixel_code_o[6] | PIN_L7 | neopixel_code_o[14] | PIN_B7 | +| dc_i | PIN_P15 | neopixel_code_o[5] | PIN_P4 | neopixel_code_o[13] | PIN_D7 | +| spi_sclk_i | PIN_R14 | neopixel_code_o[4] | PIN_L6 | neopixel_code_o[12] | PIN_E7 | +| spi_mosi_i | PIN_P12 | neopixel_code_o[3] | PIN_R3 | neopixel_code_o[11] | PIN_B6 | +| spi_cs_n_i | PIN_R11 | neopixel_code_o[2] | PIN_M5 | neopixel_code_o[10] | PIN_A7 | +| - | | neopixel_code_o[1] | PIN_P3 | neopixel_code_o[9] | PIN_A5 | +| - | | neopixel_code_o[0] | PIN_M4 | neopixel_code_o[8] | PIN_B4 | -* SPI slave mode: MODE 0, CPOL=0, CPHA=0, MSB first +* SPI slave mode: F_MAX=33MHz, CPOL=0, CPHA=0, MSB first ## Commands @@ -37,16 +37,15 @@ WS281X Cube Controller based on MAX10 FPGA. | 2nd Param | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | | | 3rd Param | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | | | 4th Param | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | | +| 5th Param | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | | +| 6th Param | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | | -* 1st Param: T0H time, range: 1-255, unit: 10 ns -* 2nd Param: T0L time, range: 1-255, unit: 10 ns -* 3rd Param: T1H time, range: 1-255, unit: 10 ns -* 4th Param: T1L time, range: 1-255, unit: 10 ns - -Limits: - -* T0H + T0L <= 257 = 2570 ns = 2.57 us -* T1H + T1L <= 257 = 2570 ns = 2.57 us +* 1st Param: T0H time (10 ns), range: 0 - 255 +* 2nd Param: T0L time (10 ns), range: 0 - 255 +* 3rd Param: T1H time (10 ns), range: 0 - 255 +* 4th Param: T1L time (10 ns), range: 0 - 255 +* 5th Param: channel length, range: 0 - 255 +* 6th Param: channel count, range: 0 - 15 ### ADDR_WR @@ -57,15 +56,12 @@ Limits: | ... | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | | | Nth Param | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | | -* 1st Param: 2nd LED address, range: 0-63 -* 2nd Param: 3rd LED address, range: 0-63 -* 3rd Param: 4th LED address, range: 0-63 +* 1st Param: channel 0, the next pointer of the 1st color data, range: 0 - 255 +* 2nd Param: channel 0, the next pointer of the 2nd color data, range: 0 - 255 * ... -* Nth Param: 1st LED address, range: 0-63 - -* N = 64 +* Nth Param: ... -* These configurations will be applied to all 8 layers +* N_MAX = 256 x 16 = 4096 ### DATA_WR @@ -76,26 +72,21 @@ Limits: | ... | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | | | Nth Param | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | | -* 1st Param: 1st LED color byte 2, range: 0-255 -* 2nd Param: 1st LED color byte 1, range: 0-255 -* 3rd Param: 1st LED color byte 0, range: 0-255 -* 4th Param: 2nd LED color byte 2, range: 0-255 -* 5th Param: 2nd LED color byte 1, range: 0-255 -* 6th Param: 2nd LED color byte 0, range: 0-255 +* 1st Param: channel 0, the 1st color data, byte 2, range: 0 - 255 +* 2nd Param: channel 0, the 1st color data, byte 1, range: 0 - 255 +* 3rd Param: channel 0, the 1st color data, byte 0, range: 0 - 255 +* 4th Param: channel 0, the 2nd color data, byte 2, range: 0 - 255 * ... * Nth Param: ... -* N = 8 x 8 x 8 x 3 = 1536 - -* Layer data order: layer 7 first (layer 7 - layer 0) -* Color byte order: high byte first (byte 2 - byte 0) +* N_MAX = 256 x 16 x 3 = 12288 ## Preparing ### Obtain the source ``` -git clone https://github.com/redchenjs/ws281x_cube_controller_max10.git +git clone https://github.com/redchenjs/neopixel_led_controller_max10.git ``` ### Update an existing repository diff --git a/ip/pll/pll.v b/ip/pll/pll.v index 0c94a89..bb29191 100644 --- a/ip/pll/pll.v +++ b/ip/pll/pll.v @@ -9,7 +9,7 @@ // altpll // // Simulation Library Files(s): -// +// altera_mf // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! @@ -55,20 +55,20 @@ module pll ( // synopsys translate_on `endif - wire [0:0] sub_wire2 = 1'h0; - wire [4:0] sub_wire3; - wire sub_wire5; - wire sub_wire0 = inclk0; - wire [1:0] sub_wire1 = {sub_wire2, sub_wire0}; - wire [0:0] sub_wire4 = sub_wire3[0:0]; - wire c0 = sub_wire4; - wire locked = sub_wire5; + wire [4:0] sub_wire0; + wire sub_wire2; + wire [0:0] sub_wire5 = 1'h0; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; + wire locked = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; altpll altpll_component ( .areset (areset), - .inclk (sub_wire1), - .clk (sub_wire3), - .locked (sub_wire5), + .inclk (sub_wire4), + .clk (sub_wire0), + .locked (sub_wire2), .activeclock (), .clkbad (), .clkena ({6{1'b1}}), @@ -106,7 +106,7 @@ module pll ( altpll_component.bandwidth_type = "AUTO", altpll_component.clk0_divide_by = 3, altpll_component.clk0_duty_cycle = 50, - altpll_component.clk0_multiply_by = 50, + altpll_component.clk0_multiply_by = 25, altpll_component.clk0_phase_shift = "0", altpll_component.compensate_clock = "CLK0", altpll_component.inclk0_input_frequency = 83333, @@ -183,7 +183,7 @@ endmodule // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "200.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -208,7 +208,7 @@ endmodule // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "50" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "200.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" @@ -253,7 +253,7 @@ endmodule // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3" // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "25" // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "83333" @@ -321,4 +321,5 @@ endmodule // Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf // Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/ip/ram/ram64.qip b/ip/ram/ram256.qip similarity index 87% rename from ip/ram/ram64.qip rename to ip/ram/ram256.qip index 435604c..5beba38 100644 --- a/ip/ram/ram64.qip +++ b/ip/ram/ram256.qip @@ -1,5 +1,5 @@ set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" set_global_assignment -name IP_TOOL_VERSION "20.1" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram64.v"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram64_syn.v"] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram256.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram256_syn.v"] diff --git a/ip/ram/ram64.v b/ip/ram/ram256.v similarity index 87% rename from ip/ram/ram64.v rename to ip/ram/ram256.v index e3bb12a..27e5d6f 100644 --- a/ip/ram/ram64.v +++ b/ip/ram/ram256.v @@ -4,7 +4,7 @@ // MODULE: altsyncram // ============================================================ -// File Name: ram64.v +// File Name: ram256.v // Megafunction Name(s): // altsyncram // @@ -37,7 +37,7 @@ // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on -module ram64 ( +module ram256 ( aclr, byteena_a, clock, @@ -52,9 +52,9 @@ module ram64 ( input [3:0] byteena_a; input clock; input [31:0] data; - input [5:0] rdaddress; + input [7:0] rdaddress; input rden; - input [5:0] wraddress; + input [7:0] wraddress; input wren; output [31:0] q; `ifndef ALTERA_RESERVED_QIS @@ -105,16 +105,16 @@ module ram64 ( altsyncram_component.clock_enable_output_b = "BYPASS", altsyncram_component.intended_device_family = "MAX 10", altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = 64, - altsyncram_component.numwords_b = 64, + altsyncram_component.numwords_a = 256, + altsyncram_component.numwords_b = 256, altsyncram_component.operation_mode = "DUAL_PORT", altsyncram_component.outdata_aclr_b = "CLEAR0", altsyncram_component.outdata_reg_b = "UNREGISTERED", altsyncram_component.power_up_uninitialized = "TRUE", altsyncram_component.rdcontrol_reg_b = "CLOCK0", altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", - altsyncram_component.widthad_a = 6, - altsyncram_component.widthad_b = 6, + altsyncram_component.widthad_a = 8, + altsyncram_component.widthad_b = 8, altsyncram_component.width_a = 32, altsyncram_component.width_b = 32, altsyncram_component.width_byteena_a = 4; @@ -155,9 +155,9 @@ endmodule // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -// Retrieval info: PRIVATE: MEMSIZE NUMERIC "2048" +// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192" // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" -// Retrieval info: PRIVATE: MIFfilename STRING "ram64.mif" +// Retrieval info: PRIVATE: MIFfilename STRING "ram256.mif" // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "1" // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" @@ -193,16 +193,16 @@ endmodule // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "64" -// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "64" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" +// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256" // Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "CLEAR0" // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "TRUE" // Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "CLOCK0" // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" -// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "6" -// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "6" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8" // Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" // Retrieval info: CONSTANT: WIDTH_B NUMERIC "32" // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4" @@ -211,24 +211,24 @@ endmodule // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" // Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]" // Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]" -// Retrieval info: USED_PORT: rdaddress 0 0 6 0 INPUT NODEFVAL "rdaddress[5..0]" +// Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL "rdaddress[7..0]" // Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden" -// Retrieval info: USED_PORT: wraddress 0 0 6 0 INPUT NODEFVAL "wraddress[5..0]" +// Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL "wraddress[7..0]" // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" // Retrieval info: CONNECT: @aclr0 0 0 0 0 aclr 0 0 0 0 -// Retrieval info: CONNECT: @address_a 0 0 6 0 wraddress 0 0 6 0 -// Retrieval info: CONNECT: @address_b 0 0 6 0 rdaddress 0 0 6 0 +// Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0 +// Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0 // Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena_a 0 0 4 0 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 // Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0 // Retrieval info: CONNECT: @rden_b 0 0 0 0 rden 0 0 0 0 // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 // Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0 -// Retrieval info: GEN_FILE: TYPE_NORMAL ram64.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL ram64.inc FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL ram64.cmp FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL ram64.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL ram64_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL ram64_bb.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL ram64_syn.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram256.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram256.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram256.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram256.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram256_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram256_bb.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram256_syn.v TRUE // Retrieval info: LIB_FILE: altera_mf diff --git a/ip/ram/ram64_syn.v b/ip/ram/ram256_syn.v similarity index 84% rename from ip/ram/ram64_syn.v rename to ip/ram/ram256_syn.v index 49dba46..ec28b31 100644 --- a/ip/ram/ram64_syn.v +++ b/ip/ram/ram256_syn.v @@ -4,7 +4,7 @@ // MODULE: altsyncram // ============================================================ -// File Name: ram64.v +// File Name: ram256.v // Megafunction Name(s): // altsyncram // @@ -34,8 +34,8 @@ //https://fpgasoftware.intel.com/eula. -//altsyncram ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" BYTE_SIZE=8 CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_B="BYPASS" DEVICE_FAMILY="MAX 10" NUMWORDS_A=64 NUMWORDS_B=64 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="CLEAR0" OUTDATA_REG_B="UNREGISTERED" POWER_UP_UNINITIALIZED="TRUE" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=32 WIDTH_B=32 WIDTH_BYTEENA_A=4 WIDTHAD_A=6 WIDTHAD_B=6 aclr0 address_a address_b byteena_a clock0 data_a q_b rden_b wren_a -//VERSION_BEGIN 20.1 cbx_altera_syncram_nd_impl 2020:06:05:12:04:51:SJ cbx_altsyncram 2020:06:05:12:04:51:SJ cbx_cycloneii 2020:06:05:12:04:51:SJ cbx_lpm_add_sub 2020:06:05:12:04:51:SJ cbx_lpm_compare 2020:06:05:12:04:51:SJ cbx_lpm_decode 2020:06:05:12:04:51:SJ cbx_lpm_mux 2020:06:05:12:04:51:SJ cbx_mgl 2020:06:05:12:11:10:SJ cbx_nadder 2020:06:05:12:04:51:SJ cbx_stratix 2020:06:05:12:04:51:SJ cbx_stratixii 2020:06:05:12:04:51:SJ cbx_stratixiii 2020:06:05:12:04:51:SJ cbx_stratixv 2020:06:05:12:04:51:SJ cbx_util_mgl 2020:06:05:12:04:51:SJ VERSION_END +//altsyncram ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" BYTE_SIZE=8 CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_B="BYPASS" DEVICE_FAMILY="MAX 10" NUMWORDS_A=256 NUMWORDS_B=256 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="CLEAR0" OUTDATA_REG_B="UNREGISTERED" POWER_UP_UNINITIALIZED="TRUE" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=32 WIDTH_B=32 WIDTH_BYTEENA_A=4 WIDTHAD_A=8 WIDTHAD_B=8 aclr0 address_a address_b byteena_a clock0 data_a q_b rden_b wren_a +//VERSION_BEGIN 20.1 cbx_altera_syncram_nd_impl 2020:06:05:12:04:24:SJ cbx_altsyncram 2020:06:05:12:04:24:SJ cbx_cycloneii 2020:06:05:12:04:24:SJ cbx_lpm_add_sub 2020:06:05:12:04:24:SJ cbx_lpm_compare 2020:06:05:12:04:24:SJ cbx_lpm_decode 2020:06:05:12:04:24:SJ cbx_lpm_mux 2020:06:05:12:04:24:SJ cbx_mgl 2020:06:05:13:25:21:SJ cbx_nadder 2020:06:05:12:04:24:SJ cbx_stratix 2020:06:05:12:04:24:SJ cbx_stratixii 2020:06:05:12:04:24:SJ cbx_stratixiii 2020:06:05:12:04:24:SJ cbx_stratixv 2020:06:05:12:04:24:SJ cbx_util_mgl 2020:06:05:12:04:24:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 @@ -45,7 +45,7 @@ `timescale 1 ps / 1 ps //synopsys translate_on (* ALTERA_ATTRIBUTE = {"OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"} *) -module ram64_altsyncram +module ram256_altsyncram ( aclr0, address_a, @@ -57,8 +57,8 @@ module ram64_altsyncram rden_b, wren_a) /* synthesis synthesis_clearbox=1 */; input aclr0; - input [5:0] address_a; - input [5:0] address_b; + input [7:0] address_a; + input [7:0] address_b; input [3:0] byteena_a; input clock0; input [31:0] data_a; @@ -69,7 +69,7 @@ module ram64_altsyncram // synopsys translate_off `endif tri0 aclr0; - tri1 [5:0] address_b; + tri1 [7:0] address_b; tri1 [3:0] byteena_a; tri1 clock0; tri1 [31:0] data_a; @@ -112,8 +112,8 @@ module ram64_altsyncram wire [0:0] wire_ram_block1a_29portbdataout; wire [0:0] wire_ram_block1a_30portbdataout; wire [0:0] wire_ram_block1a_31portbdataout; - wire [5:0] address_a_wire; - wire [5:0] address_b_wire; + wire [7:0] address_a_wire; + wire [7:0] address_b_wire; // synopsys translate_off initial @@ -128,12 +128,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[0]}), .portadatain({data_a[0]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_0portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -167,24 +167,24 @@ module ram64_altsyncram ram_block1a_0.logical_ram_name = "ALTSYNCRAM", ram_block1a_0.mixed_port_feed_through_mode = "dont_care", ram_block1a_0.operation_mode = "dual_port", - ram_block1a_0.port_a_address_width = 6, + ram_block1a_0.port_a_address_width = 8, ram_block1a_0.port_a_byte_enable_mask_width = 1, ram_block1a_0.port_a_byte_size = 1, ram_block1a_0.port_a_data_width = 1, ram_block1a_0.port_a_first_address = 0, ram_block1a_0.port_a_first_bit_number = 0, - ram_block1a_0.port_a_last_address = 63, - ram_block1a_0.port_a_logical_ram_depth = 64, + ram_block1a_0.port_a_last_address = 255, + ram_block1a_0.port_a_logical_ram_depth = 256, ram_block1a_0.port_a_logical_ram_width = 32, ram_block1a_0.port_b_address_clear = "none", ram_block1a_0.port_b_address_clock = "clock1", - ram_block1a_0.port_b_address_width = 6, + ram_block1a_0.port_b_address_width = 8, ram_block1a_0.port_b_data_out_clear = "clear0", ram_block1a_0.port_b_data_width = 1, ram_block1a_0.port_b_first_address = 0, ram_block1a_0.port_b_first_bit_number = 0, - ram_block1a_0.port_b_last_address = 63, - ram_block1a_0.port_b_logical_ram_depth = 64, + ram_block1a_0.port_b_last_address = 255, + ram_block1a_0.port_b_logical_ram_depth = 256, ram_block1a_0.port_b_logical_ram_width = 32, ram_block1a_0.port_b_read_enable_clock = "clock1", ram_block1a_0.power_up_uninitialized = "true", @@ -197,12 +197,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[0]}), .portadatain({data_a[1]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_1portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -236,24 +236,24 @@ module ram64_altsyncram ram_block1a_1.logical_ram_name = "ALTSYNCRAM", ram_block1a_1.mixed_port_feed_through_mode = "dont_care", ram_block1a_1.operation_mode = "dual_port", - ram_block1a_1.port_a_address_width = 6, + ram_block1a_1.port_a_address_width = 8, ram_block1a_1.port_a_byte_enable_mask_width = 1, ram_block1a_1.port_a_byte_size = 1, ram_block1a_1.port_a_data_width = 1, ram_block1a_1.port_a_first_address = 0, ram_block1a_1.port_a_first_bit_number = 1, - ram_block1a_1.port_a_last_address = 63, - ram_block1a_1.port_a_logical_ram_depth = 64, + ram_block1a_1.port_a_last_address = 255, + ram_block1a_1.port_a_logical_ram_depth = 256, ram_block1a_1.port_a_logical_ram_width = 32, ram_block1a_1.port_b_address_clear = "none", ram_block1a_1.port_b_address_clock = "clock1", - ram_block1a_1.port_b_address_width = 6, + ram_block1a_1.port_b_address_width = 8, ram_block1a_1.port_b_data_out_clear = "clear0", ram_block1a_1.port_b_data_width = 1, ram_block1a_1.port_b_first_address = 0, ram_block1a_1.port_b_first_bit_number = 1, - ram_block1a_1.port_b_last_address = 63, - ram_block1a_1.port_b_logical_ram_depth = 64, + ram_block1a_1.port_b_last_address = 255, + ram_block1a_1.port_b_logical_ram_depth = 256, ram_block1a_1.port_b_logical_ram_width = 32, ram_block1a_1.port_b_read_enable_clock = "clock1", ram_block1a_1.power_up_uninitialized = "true", @@ -266,12 +266,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[0]}), .portadatain({data_a[2]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_2portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -305,24 +305,24 @@ module ram64_altsyncram ram_block1a_2.logical_ram_name = "ALTSYNCRAM", ram_block1a_2.mixed_port_feed_through_mode = "dont_care", ram_block1a_2.operation_mode = "dual_port", - ram_block1a_2.port_a_address_width = 6, + ram_block1a_2.port_a_address_width = 8, ram_block1a_2.port_a_byte_enable_mask_width = 1, ram_block1a_2.port_a_byte_size = 1, ram_block1a_2.port_a_data_width = 1, ram_block1a_2.port_a_first_address = 0, ram_block1a_2.port_a_first_bit_number = 2, - ram_block1a_2.port_a_last_address = 63, - ram_block1a_2.port_a_logical_ram_depth = 64, + ram_block1a_2.port_a_last_address = 255, + ram_block1a_2.port_a_logical_ram_depth = 256, ram_block1a_2.port_a_logical_ram_width = 32, ram_block1a_2.port_b_address_clear = "none", ram_block1a_2.port_b_address_clock = "clock1", - ram_block1a_2.port_b_address_width = 6, + ram_block1a_2.port_b_address_width = 8, ram_block1a_2.port_b_data_out_clear = "clear0", ram_block1a_2.port_b_data_width = 1, ram_block1a_2.port_b_first_address = 0, ram_block1a_2.port_b_first_bit_number = 2, - ram_block1a_2.port_b_last_address = 63, - ram_block1a_2.port_b_logical_ram_depth = 64, + ram_block1a_2.port_b_last_address = 255, + ram_block1a_2.port_b_logical_ram_depth = 256, ram_block1a_2.port_b_logical_ram_width = 32, ram_block1a_2.port_b_read_enable_clock = "clock1", ram_block1a_2.power_up_uninitialized = "true", @@ -335,12 +335,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[0]}), .portadatain({data_a[3]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_3portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -374,24 +374,24 @@ module ram64_altsyncram ram_block1a_3.logical_ram_name = "ALTSYNCRAM", ram_block1a_3.mixed_port_feed_through_mode = "dont_care", ram_block1a_3.operation_mode = "dual_port", - ram_block1a_3.port_a_address_width = 6, + ram_block1a_3.port_a_address_width = 8, ram_block1a_3.port_a_byte_enable_mask_width = 1, ram_block1a_3.port_a_byte_size = 1, ram_block1a_3.port_a_data_width = 1, ram_block1a_3.port_a_first_address = 0, ram_block1a_3.port_a_first_bit_number = 3, - ram_block1a_3.port_a_last_address = 63, - ram_block1a_3.port_a_logical_ram_depth = 64, + ram_block1a_3.port_a_last_address = 255, + ram_block1a_3.port_a_logical_ram_depth = 256, ram_block1a_3.port_a_logical_ram_width = 32, ram_block1a_3.port_b_address_clear = "none", ram_block1a_3.port_b_address_clock = "clock1", - ram_block1a_3.port_b_address_width = 6, + ram_block1a_3.port_b_address_width = 8, ram_block1a_3.port_b_data_out_clear = "clear0", ram_block1a_3.port_b_data_width = 1, ram_block1a_3.port_b_first_address = 0, ram_block1a_3.port_b_first_bit_number = 3, - ram_block1a_3.port_b_last_address = 63, - ram_block1a_3.port_b_logical_ram_depth = 64, + ram_block1a_3.port_b_last_address = 255, + ram_block1a_3.port_b_logical_ram_depth = 256, ram_block1a_3.port_b_logical_ram_width = 32, ram_block1a_3.port_b_read_enable_clock = "clock1", ram_block1a_3.power_up_uninitialized = "true", @@ -404,12 +404,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[0]}), .portadatain({data_a[4]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_4portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -443,24 +443,24 @@ module ram64_altsyncram ram_block1a_4.logical_ram_name = "ALTSYNCRAM", ram_block1a_4.mixed_port_feed_through_mode = "dont_care", ram_block1a_4.operation_mode = "dual_port", - ram_block1a_4.port_a_address_width = 6, + ram_block1a_4.port_a_address_width = 8, ram_block1a_4.port_a_byte_enable_mask_width = 1, ram_block1a_4.port_a_byte_size = 1, ram_block1a_4.port_a_data_width = 1, ram_block1a_4.port_a_first_address = 0, ram_block1a_4.port_a_first_bit_number = 4, - ram_block1a_4.port_a_last_address = 63, - ram_block1a_4.port_a_logical_ram_depth = 64, + ram_block1a_4.port_a_last_address = 255, + ram_block1a_4.port_a_logical_ram_depth = 256, ram_block1a_4.port_a_logical_ram_width = 32, ram_block1a_4.port_b_address_clear = "none", ram_block1a_4.port_b_address_clock = "clock1", - ram_block1a_4.port_b_address_width = 6, + ram_block1a_4.port_b_address_width = 8, ram_block1a_4.port_b_data_out_clear = "clear0", ram_block1a_4.port_b_data_width = 1, ram_block1a_4.port_b_first_address = 0, ram_block1a_4.port_b_first_bit_number = 4, - ram_block1a_4.port_b_last_address = 63, - ram_block1a_4.port_b_logical_ram_depth = 64, + ram_block1a_4.port_b_last_address = 255, + ram_block1a_4.port_b_logical_ram_depth = 256, ram_block1a_4.port_b_logical_ram_width = 32, ram_block1a_4.port_b_read_enable_clock = "clock1", ram_block1a_4.power_up_uninitialized = "true", @@ -473,12 +473,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[0]}), .portadatain({data_a[5]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_5portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -512,24 +512,24 @@ module ram64_altsyncram ram_block1a_5.logical_ram_name = "ALTSYNCRAM", ram_block1a_5.mixed_port_feed_through_mode = "dont_care", ram_block1a_5.operation_mode = "dual_port", - ram_block1a_5.port_a_address_width = 6, + ram_block1a_5.port_a_address_width = 8, ram_block1a_5.port_a_byte_enable_mask_width = 1, ram_block1a_5.port_a_byte_size = 1, ram_block1a_5.port_a_data_width = 1, ram_block1a_5.port_a_first_address = 0, ram_block1a_5.port_a_first_bit_number = 5, - ram_block1a_5.port_a_last_address = 63, - ram_block1a_5.port_a_logical_ram_depth = 64, + ram_block1a_5.port_a_last_address = 255, + ram_block1a_5.port_a_logical_ram_depth = 256, ram_block1a_5.port_a_logical_ram_width = 32, ram_block1a_5.port_b_address_clear = "none", ram_block1a_5.port_b_address_clock = "clock1", - ram_block1a_5.port_b_address_width = 6, + ram_block1a_5.port_b_address_width = 8, ram_block1a_5.port_b_data_out_clear = "clear0", ram_block1a_5.port_b_data_width = 1, ram_block1a_5.port_b_first_address = 0, ram_block1a_5.port_b_first_bit_number = 5, - ram_block1a_5.port_b_last_address = 63, - ram_block1a_5.port_b_logical_ram_depth = 64, + ram_block1a_5.port_b_last_address = 255, + ram_block1a_5.port_b_logical_ram_depth = 256, ram_block1a_5.port_b_logical_ram_width = 32, ram_block1a_5.port_b_read_enable_clock = "clock1", ram_block1a_5.power_up_uninitialized = "true", @@ -542,12 +542,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[0]}), .portadatain({data_a[6]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_6portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -581,24 +581,24 @@ module ram64_altsyncram ram_block1a_6.logical_ram_name = "ALTSYNCRAM", ram_block1a_6.mixed_port_feed_through_mode = "dont_care", ram_block1a_6.operation_mode = "dual_port", - ram_block1a_6.port_a_address_width = 6, + ram_block1a_6.port_a_address_width = 8, ram_block1a_6.port_a_byte_enable_mask_width = 1, ram_block1a_6.port_a_byte_size = 1, ram_block1a_6.port_a_data_width = 1, ram_block1a_6.port_a_first_address = 0, ram_block1a_6.port_a_first_bit_number = 6, - ram_block1a_6.port_a_last_address = 63, - ram_block1a_6.port_a_logical_ram_depth = 64, + ram_block1a_6.port_a_last_address = 255, + ram_block1a_6.port_a_logical_ram_depth = 256, ram_block1a_6.port_a_logical_ram_width = 32, ram_block1a_6.port_b_address_clear = "none", ram_block1a_6.port_b_address_clock = "clock1", - ram_block1a_6.port_b_address_width = 6, + ram_block1a_6.port_b_address_width = 8, ram_block1a_6.port_b_data_out_clear = "clear0", ram_block1a_6.port_b_data_width = 1, ram_block1a_6.port_b_first_address = 0, ram_block1a_6.port_b_first_bit_number = 6, - ram_block1a_6.port_b_last_address = 63, - ram_block1a_6.port_b_logical_ram_depth = 64, + ram_block1a_6.port_b_last_address = 255, + ram_block1a_6.port_b_logical_ram_depth = 256, ram_block1a_6.port_b_logical_ram_width = 32, ram_block1a_6.port_b_read_enable_clock = "clock1", ram_block1a_6.power_up_uninitialized = "true", @@ -611,12 +611,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[0]}), .portadatain({data_a[7]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_7portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -650,24 +650,24 @@ module ram64_altsyncram ram_block1a_7.logical_ram_name = "ALTSYNCRAM", ram_block1a_7.mixed_port_feed_through_mode = "dont_care", ram_block1a_7.operation_mode = "dual_port", - ram_block1a_7.port_a_address_width = 6, + ram_block1a_7.port_a_address_width = 8, ram_block1a_7.port_a_byte_enable_mask_width = 1, ram_block1a_7.port_a_byte_size = 1, ram_block1a_7.port_a_data_width = 1, ram_block1a_7.port_a_first_address = 0, ram_block1a_7.port_a_first_bit_number = 7, - ram_block1a_7.port_a_last_address = 63, - ram_block1a_7.port_a_logical_ram_depth = 64, + ram_block1a_7.port_a_last_address = 255, + ram_block1a_7.port_a_logical_ram_depth = 256, ram_block1a_7.port_a_logical_ram_width = 32, ram_block1a_7.port_b_address_clear = "none", ram_block1a_7.port_b_address_clock = "clock1", - ram_block1a_7.port_b_address_width = 6, + ram_block1a_7.port_b_address_width = 8, ram_block1a_7.port_b_data_out_clear = "clear0", ram_block1a_7.port_b_data_width = 1, ram_block1a_7.port_b_first_address = 0, ram_block1a_7.port_b_first_bit_number = 7, - ram_block1a_7.port_b_last_address = 63, - ram_block1a_7.port_b_logical_ram_depth = 64, + ram_block1a_7.port_b_last_address = 255, + ram_block1a_7.port_b_logical_ram_depth = 256, ram_block1a_7.port_b_logical_ram_width = 32, ram_block1a_7.port_b_read_enable_clock = "clock1", ram_block1a_7.power_up_uninitialized = "true", @@ -680,12 +680,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[1]}), .portadatain({data_a[8]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_8portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -719,24 +719,24 @@ module ram64_altsyncram ram_block1a_8.logical_ram_name = "ALTSYNCRAM", ram_block1a_8.mixed_port_feed_through_mode = "dont_care", ram_block1a_8.operation_mode = "dual_port", - ram_block1a_8.port_a_address_width = 6, + ram_block1a_8.port_a_address_width = 8, ram_block1a_8.port_a_byte_enable_mask_width = 1, ram_block1a_8.port_a_byte_size = 1, ram_block1a_8.port_a_data_width = 1, ram_block1a_8.port_a_first_address = 0, ram_block1a_8.port_a_first_bit_number = 8, - ram_block1a_8.port_a_last_address = 63, - ram_block1a_8.port_a_logical_ram_depth = 64, + ram_block1a_8.port_a_last_address = 255, + ram_block1a_8.port_a_logical_ram_depth = 256, ram_block1a_8.port_a_logical_ram_width = 32, ram_block1a_8.port_b_address_clear = "none", ram_block1a_8.port_b_address_clock = "clock1", - ram_block1a_8.port_b_address_width = 6, + ram_block1a_8.port_b_address_width = 8, ram_block1a_8.port_b_data_out_clear = "clear0", ram_block1a_8.port_b_data_width = 1, ram_block1a_8.port_b_first_address = 0, ram_block1a_8.port_b_first_bit_number = 8, - ram_block1a_8.port_b_last_address = 63, - ram_block1a_8.port_b_logical_ram_depth = 64, + ram_block1a_8.port_b_last_address = 255, + ram_block1a_8.port_b_logical_ram_depth = 256, ram_block1a_8.port_b_logical_ram_width = 32, ram_block1a_8.port_b_read_enable_clock = "clock1", ram_block1a_8.power_up_uninitialized = "true", @@ -749,12 +749,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[1]}), .portadatain({data_a[9]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_9portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -788,24 +788,24 @@ module ram64_altsyncram ram_block1a_9.logical_ram_name = "ALTSYNCRAM", ram_block1a_9.mixed_port_feed_through_mode = "dont_care", ram_block1a_9.operation_mode = "dual_port", - ram_block1a_9.port_a_address_width = 6, + ram_block1a_9.port_a_address_width = 8, ram_block1a_9.port_a_byte_enable_mask_width = 1, ram_block1a_9.port_a_byte_size = 1, ram_block1a_9.port_a_data_width = 1, ram_block1a_9.port_a_first_address = 0, ram_block1a_9.port_a_first_bit_number = 9, - ram_block1a_9.port_a_last_address = 63, - ram_block1a_9.port_a_logical_ram_depth = 64, + ram_block1a_9.port_a_last_address = 255, + ram_block1a_9.port_a_logical_ram_depth = 256, ram_block1a_9.port_a_logical_ram_width = 32, ram_block1a_9.port_b_address_clear = "none", ram_block1a_9.port_b_address_clock = "clock1", - ram_block1a_9.port_b_address_width = 6, + ram_block1a_9.port_b_address_width = 8, ram_block1a_9.port_b_data_out_clear = "clear0", ram_block1a_9.port_b_data_width = 1, ram_block1a_9.port_b_first_address = 0, ram_block1a_9.port_b_first_bit_number = 9, - ram_block1a_9.port_b_last_address = 63, - ram_block1a_9.port_b_logical_ram_depth = 64, + ram_block1a_9.port_b_last_address = 255, + ram_block1a_9.port_b_logical_ram_depth = 256, ram_block1a_9.port_b_logical_ram_width = 32, ram_block1a_9.port_b_read_enable_clock = "clock1", ram_block1a_9.power_up_uninitialized = "true", @@ -818,12 +818,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[1]}), .portadatain({data_a[10]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_10portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -857,24 +857,24 @@ module ram64_altsyncram ram_block1a_10.logical_ram_name = "ALTSYNCRAM", ram_block1a_10.mixed_port_feed_through_mode = "dont_care", ram_block1a_10.operation_mode = "dual_port", - ram_block1a_10.port_a_address_width = 6, + ram_block1a_10.port_a_address_width = 8, ram_block1a_10.port_a_byte_enable_mask_width = 1, ram_block1a_10.port_a_byte_size = 1, ram_block1a_10.port_a_data_width = 1, ram_block1a_10.port_a_first_address = 0, ram_block1a_10.port_a_first_bit_number = 10, - ram_block1a_10.port_a_last_address = 63, - ram_block1a_10.port_a_logical_ram_depth = 64, + ram_block1a_10.port_a_last_address = 255, + ram_block1a_10.port_a_logical_ram_depth = 256, ram_block1a_10.port_a_logical_ram_width = 32, ram_block1a_10.port_b_address_clear = "none", ram_block1a_10.port_b_address_clock = "clock1", - ram_block1a_10.port_b_address_width = 6, + ram_block1a_10.port_b_address_width = 8, ram_block1a_10.port_b_data_out_clear = "clear0", ram_block1a_10.port_b_data_width = 1, ram_block1a_10.port_b_first_address = 0, ram_block1a_10.port_b_first_bit_number = 10, - ram_block1a_10.port_b_last_address = 63, - ram_block1a_10.port_b_logical_ram_depth = 64, + ram_block1a_10.port_b_last_address = 255, + ram_block1a_10.port_b_logical_ram_depth = 256, ram_block1a_10.port_b_logical_ram_width = 32, ram_block1a_10.port_b_read_enable_clock = "clock1", ram_block1a_10.power_up_uninitialized = "true", @@ -887,12 +887,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[1]}), .portadatain({data_a[11]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_11portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -926,24 +926,24 @@ module ram64_altsyncram ram_block1a_11.logical_ram_name = "ALTSYNCRAM", ram_block1a_11.mixed_port_feed_through_mode = "dont_care", ram_block1a_11.operation_mode = "dual_port", - ram_block1a_11.port_a_address_width = 6, + ram_block1a_11.port_a_address_width = 8, ram_block1a_11.port_a_byte_enable_mask_width = 1, ram_block1a_11.port_a_byte_size = 1, ram_block1a_11.port_a_data_width = 1, ram_block1a_11.port_a_first_address = 0, ram_block1a_11.port_a_first_bit_number = 11, - ram_block1a_11.port_a_last_address = 63, - ram_block1a_11.port_a_logical_ram_depth = 64, + ram_block1a_11.port_a_last_address = 255, + ram_block1a_11.port_a_logical_ram_depth = 256, ram_block1a_11.port_a_logical_ram_width = 32, ram_block1a_11.port_b_address_clear = "none", ram_block1a_11.port_b_address_clock = "clock1", - ram_block1a_11.port_b_address_width = 6, + ram_block1a_11.port_b_address_width = 8, ram_block1a_11.port_b_data_out_clear = "clear0", ram_block1a_11.port_b_data_width = 1, ram_block1a_11.port_b_first_address = 0, ram_block1a_11.port_b_first_bit_number = 11, - ram_block1a_11.port_b_last_address = 63, - ram_block1a_11.port_b_logical_ram_depth = 64, + ram_block1a_11.port_b_last_address = 255, + ram_block1a_11.port_b_logical_ram_depth = 256, ram_block1a_11.port_b_logical_ram_width = 32, ram_block1a_11.port_b_read_enable_clock = "clock1", ram_block1a_11.power_up_uninitialized = "true", @@ -956,12 +956,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[1]}), .portadatain({data_a[12]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_12portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -995,24 +995,24 @@ module ram64_altsyncram ram_block1a_12.logical_ram_name = "ALTSYNCRAM", ram_block1a_12.mixed_port_feed_through_mode = "dont_care", ram_block1a_12.operation_mode = "dual_port", - ram_block1a_12.port_a_address_width = 6, + ram_block1a_12.port_a_address_width = 8, ram_block1a_12.port_a_byte_enable_mask_width = 1, ram_block1a_12.port_a_byte_size = 1, ram_block1a_12.port_a_data_width = 1, ram_block1a_12.port_a_first_address = 0, ram_block1a_12.port_a_first_bit_number = 12, - ram_block1a_12.port_a_last_address = 63, - ram_block1a_12.port_a_logical_ram_depth = 64, + ram_block1a_12.port_a_last_address = 255, + ram_block1a_12.port_a_logical_ram_depth = 256, ram_block1a_12.port_a_logical_ram_width = 32, ram_block1a_12.port_b_address_clear = "none", ram_block1a_12.port_b_address_clock = "clock1", - ram_block1a_12.port_b_address_width = 6, + ram_block1a_12.port_b_address_width = 8, ram_block1a_12.port_b_data_out_clear = "clear0", ram_block1a_12.port_b_data_width = 1, ram_block1a_12.port_b_first_address = 0, ram_block1a_12.port_b_first_bit_number = 12, - ram_block1a_12.port_b_last_address = 63, - ram_block1a_12.port_b_logical_ram_depth = 64, + ram_block1a_12.port_b_last_address = 255, + ram_block1a_12.port_b_logical_ram_depth = 256, ram_block1a_12.port_b_logical_ram_width = 32, ram_block1a_12.port_b_read_enable_clock = "clock1", ram_block1a_12.power_up_uninitialized = "true", @@ -1025,12 +1025,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[1]}), .portadatain({data_a[13]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_13portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -1064,24 +1064,24 @@ module ram64_altsyncram ram_block1a_13.logical_ram_name = "ALTSYNCRAM", ram_block1a_13.mixed_port_feed_through_mode = "dont_care", ram_block1a_13.operation_mode = "dual_port", - ram_block1a_13.port_a_address_width = 6, + ram_block1a_13.port_a_address_width = 8, ram_block1a_13.port_a_byte_enable_mask_width = 1, ram_block1a_13.port_a_byte_size = 1, ram_block1a_13.port_a_data_width = 1, ram_block1a_13.port_a_first_address = 0, ram_block1a_13.port_a_first_bit_number = 13, - ram_block1a_13.port_a_last_address = 63, - ram_block1a_13.port_a_logical_ram_depth = 64, + ram_block1a_13.port_a_last_address = 255, + ram_block1a_13.port_a_logical_ram_depth = 256, ram_block1a_13.port_a_logical_ram_width = 32, ram_block1a_13.port_b_address_clear = "none", ram_block1a_13.port_b_address_clock = "clock1", - ram_block1a_13.port_b_address_width = 6, + ram_block1a_13.port_b_address_width = 8, ram_block1a_13.port_b_data_out_clear = "clear0", ram_block1a_13.port_b_data_width = 1, ram_block1a_13.port_b_first_address = 0, ram_block1a_13.port_b_first_bit_number = 13, - ram_block1a_13.port_b_last_address = 63, - ram_block1a_13.port_b_logical_ram_depth = 64, + ram_block1a_13.port_b_last_address = 255, + ram_block1a_13.port_b_logical_ram_depth = 256, ram_block1a_13.port_b_logical_ram_width = 32, ram_block1a_13.port_b_read_enable_clock = "clock1", ram_block1a_13.power_up_uninitialized = "true", @@ -1094,12 +1094,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[1]}), .portadatain({data_a[14]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_14portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -1133,24 +1133,24 @@ module ram64_altsyncram ram_block1a_14.logical_ram_name = "ALTSYNCRAM", ram_block1a_14.mixed_port_feed_through_mode = "dont_care", ram_block1a_14.operation_mode = "dual_port", - ram_block1a_14.port_a_address_width = 6, + ram_block1a_14.port_a_address_width = 8, ram_block1a_14.port_a_byte_enable_mask_width = 1, ram_block1a_14.port_a_byte_size = 1, ram_block1a_14.port_a_data_width = 1, ram_block1a_14.port_a_first_address = 0, ram_block1a_14.port_a_first_bit_number = 14, - ram_block1a_14.port_a_last_address = 63, - ram_block1a_14.port_a_logical_ram_depth = 64, + ram_block1a_14.port_a_last_address = 255, + ram_block1a_14.port_a_logical_ram_depth = 256, ram_block1a_14.port_a_logical_ram_width = 32, ram_block1a_14.port_b_address_clear = "none", ram_block1a_14.port_b_address_clock = "clock1", - ram_block1a_14.port_b_address_width = 6, + ram_block1a_14.port_b_address_width = 8, ram_block1a_14.port_b_data_out_clear = "clear0", ram_block1a_14.port_b_data_width = 1, ram_block1a_14.port_b_first_address = 0, ram_block1a_14.port_b_first_bit_number = 14, - ram_block1a_14.port_b_last_address = 63, - ram_block1a_14.port_b_logical_ram_depth = 64, + ram_block1a_14.port_b_last_address = 255, + ram_block1a_14.port_b_logical_ram_depth = 256, ram_block1a_14.port_b_logical_ram_width = 32, ram_block1a_14.port_b_read_enable_clock = "clock1", ram_block1a_14.power_up_uninitialized = "true", @@ -1163,12 +1163,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[1]}), .portadatain({data_a[15]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_15portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -1202,24 +1202,24 @@ module ram64_altsyncram ram_block1a_15.logical_ram_name = "ALTSYNCRAM", ram_block1a_15.mixed_port_feed_through_mode = "dont_care", ram_block1a_15.operation_mode = "dual_port", - ram_block1a_15.port_a_address_width = 6, + ram_block1a_15.port_a_address_width = 8, ram_block1a_15.port_a_byte_enable_mask_width = 1, ram_block1a_15.port_a_byte_size = 1, ram_block1a_15.port_a_data_width = 1, ram_block1a_15.port_a_first_address = 0, ram_block1a_15.port_a_first_bit_number = 15, - ram_block1a_15.port_a_last_address = 63, - ram_block1a_15.port_a_logical_ram_depth = 64, + ram_block1a_15.port_a_last_address = 255, + ram_block1a_15.port_a_logical_ram_depth = 256, ram_block1a_15.port_a_logical_ram_width = 32, ram_block1a_15.port_b_address_clear = "none", ram_block1a_15.port_b_address_clock = "clock1", - ram_block1a_15.port_b_address_width = 6, + ram_block1a_15.port_b_address_width = 8, ram_block1a_15.port_b_data_out_clear = "clear0", ram_block1a_15.port_b_data_width = 1, ram_block1a_15.port_b_first_address = 0, ram_block1a_15.port_b_first_bit_number = 15, - ram_block1a_15.port_b_last_address = 63, - ram_block1a_15.port_b_logical_ram_depth = 64, + ram_block1a_15.port_b_last_address = 255, + ram_block1a_15.port_b_logical_ram_depth = 256, ram_block1a_15.port_b_logical_ram_width = 32, ram_block1a_15.port_b_read_enable_clock = "clock1", ram_block1a_15.power_up_uninitialized = "true", @@ -1232,12 +1232,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[2]}), .portadatain({data_a[16]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_16portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -1271,24 +1271,24 @@ module ram64_altsyncram ram_block1a_16.logical_ram_name = "ALTSYNCRAM", ram_block1a_16.mixed_port_feed_through_mode = "dont_care", ram_block1a_16.operation_mode = "dual_port", - ram_block1a_16.port_a_address_width = 6, + ram_block1a_16.port_a_address_width = 8, ram_block1a_16.port_a_byte_enable_mask_width = 1, ram_block1a_16.port_a_byte_size = 1, ram_block1a_16.port_a_data_width = 1, ram_block1a_16.port_a_first_address = 0, ram_block1a_16.port_a_first_bit_number = 16, - ram_block1a_16.port_a_last_address = 63, - ram_block1a_16.port_a_logical_ram_depth = 64, + ram_block1a_16.port_a_last_address = 255, + ram_block1a_16.port_a_logical_ram_depth = 256, ram_block1a_16.port_a_logical_ram_width = 32, ram_block1a_16.port_b_address_clear = "none", ram_block1a_16.port_b_address_clock = "clock1", - ram_block1a_16.port_b_address_width = 6, + ram_block1a_16.port_b_address_width = 8, ram_block1a_16.port_b_data_out_clear = "clear0", ram_block1a_16.port_b_data_width = 1, ram_block1a_16.port_b_first_address = 0, ram_block1a_16.port_b_first_bit_number = 16, - ram_block1a_16.port_b_last_address = 63, - ram_block1a_16.port_b_logical_ram_depth = 64, + ram_block1a_16.port_b_last_address = 255, + ram_block1a_16.port_b_logical_ram_depth = 256, ram_block1a_16.port_b_logical_ram_width = 32, ram_block1a_16.port_b_read_enable_clock = "clock1", ram_block1a_16.power_up_uninitialized = "true", @@ -1301,12 +1301,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[2]}), .portadatain({data_a[17]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_17portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -1340,24 +1340,24 @@ module ram64_altsyncram ram_block1a_17.logical_ram_name = "ALTSYNCRAM", ram_block1a_17.mixed_port_feed_through_mode = "dont_care", ram_block1a_17.operation_mode = "dual_port", - ram_block1a_17.port_a_address_width = 6, + ram_block1a_17.port_a_address_width = 8, ram_block1a_17.port_a_byte_enable_mask_width = 1, ram_block1a_17.port_a_byte_size = 1, ram_block1a_17.port_a_data_width = 1, ram_block1a_17.port_a_first_address = 0, ram_block1a_17.port_a_first_bit_number = 17, - ram_block1a_17.port_a_last_address = 63, - ram_block1a_17.port_a_logical_ram_depth = 64, + ram_block1a_17.port_a_last_address = 255, + ram_block1a_17.port_a_logical_ram_depth = 256, ram_block1a_17.port_a_logical_ram_width = 32, ram_block1a_17.port_b_address_clear = "none", ram_block1a_17.port_b_address_clock = "clock1", - ram_block1a_17.port_b_address_width = 6, + ram_block1a_17.port_b_address_width = 8, ram_block1a_17.port_b_data_out_clear = "clear0", ram_block1a_17.port_b_data_width = 1, ram_block1a_17.port_b_first_address = 0, ram_block1a_17.port_b_first_bit_number = 17, - ram_block1a_17.port_b_last_address = 63, - ram_block1a_17.port_b_logical_ram_depth = 64, + ram_block1a_17.port_b_last_address = 255, + ram_block1a_17.port_b_logical_ram_depth = 256, ram_block1a_17.port_b_logical_ram_width = 32, ram_block1a_17.port_b_read_enable_clock = "clock1", ram_block1a_17.power_up_uninitialized = "true", @@ -1370,12 +1370,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[2]}), .portadatain({data_a[18]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_18portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -1409,24 +1409,24 @@ module ram64_altsyncram ram_block1a_18.logical_ram_name = "ALTSYNCRAM", ram_block1a_18.mixed_port_feed_through_mode = "dont_care", ram_block1a_18.operation_mode = "dual_port", - ram_block1a_18.port_a_address_width = 6, + ram_block1a_18.port_a_address_width = 8, ram_block1a_18.port_a_byte_enable_mask_width = 1, ram_block1a_18.port_a_byte_size = 1, ram_block1a_18.port_a_data_width = 1, ram_block1a_18.port_a_first_address = 0, ram_block1a_18.port_a_first_bit_number = 18, - ram_block1a_18.port_a_last_address = 63, - ram_block1a_18.port_a_logical_ram_depth = 64, + ram_block1a_18.port_a_last_address = 255, + ram_block1a_18.port_a_logical_ram_depth = 256, ram_block1a_18.port_a_logical_ram_width = 32, ram_block1a_18.port_b_address_clear = "none", ram_block1a_18.port_b_address_clock = "clock1", - ram_block1a_18.port_b_address_width = 6, + ram_block1a_18.port_b_address_width = 8, ram_block1a_18.port_b_data_out_clear = "clear0", ram_block1a_18.port_b_data_width = 1, ram_block1a_18.port_b_first_address = 0, ram_block1a_18.port_b_first_bit_number = 18, - ram_block1a_18.port_b_last_address = 63, - ram_block1a_18.port_b_logical_ram_depth = 64, + ram_block1a_18.port_b_last_address = 255, + ram_block1a_18.port_b_logical_ram_depth = 256, ram_block1a_18.port_b_logical_ram_width = 32, ram_block1a_18.port_b_read_enable_clock = "clock1", ram_block1a_18.power_up_uninitialized = "true", @@ -1439,12 +1439,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[2]}), .portadatain({data_a[19]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_19portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -1478,24 +1478,24 @@ module ram64_altsyncram ram_block1a_19.logical_ram_name = "ALTSYNCRAM", ram_block1a_19.mixed_port_feed_through_mode = "dont_care", ram_block1a_19.operation_mode = "dual_port", - ram_block1a_19.port_a_address_width = 6, + ram_block1a_19.port_a_address_width = 8, ram_block1a_19.port_a_byte_enable_mask_width = 1, ram_block1a_19.port_a_byte_size = 1, ram_block1a_19.port_a_data_width = 1, ram_block1a_19.port_a_first_address = 0, ram_block1a_19.port_a_first_bit_number = 19, - ram_block1a_19.port_a_last_address = 63, - ram_block1a_19.port_a_logical_ram_depth = 64, + ram_block1a_19.port_a_last_address = 255, + ram_block1a_19.port_a_logical_ram_depth = 256, ram_block1a_19.port_a_logical_ram_width = 32, ram_block1a_19.port_b_address_clear = "none", ram_block1a_19.port_b_address_clock = "clock1", - ram_block1a_19.port_b_address_width = 6, + ram_block1a_19.port_b_address_width = 8, ram_block1a_19.port_b_data_out_clear = "clear0", ram_block1a_19.port_b_data_width = 1, ram_block1a_19.port_b_first_address = 0, ram_block1a_19.port_b_first_bit_number = 19, - ram_block1a_19.port_b_last_address = 63, - ram_block1a_19.port_b_logical_ram_depth = 64, + ram_block1a_19.port_b_last_address = 255, + ram_block1a_19.port_b_logical_ram_depth = 256, ram_block1a_19.port_b_logical_ram_width = 32, ram_block1a_19.port_b_read_enable_clock = "clock1", ram_block1a_19.power_up_uninitialized = "true", @@ -1508,12 +1508,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[2]}), .portadatain({data_a[20]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_20portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -1547,24 +1547,24 @@ module ram64_altsyncram ram_block1a_20.logical_ram_name = "ALTSYNCRAM", ram_block1a_20.mixed_port_feed_through_mode = "dont_care", ram_block1a_20.operation_mode = "dual_port", - ram_block1a_20.port_a_address_width = 6, + ram_block1a_20.port_a_address_width = 8, ram_block1a_20.port_a_byte_enable_mask_width = 1, ram_block1a_20.port_a_byte_size = 1, ram_block1a_20.port_a_data_width = 1, ram_block1a_20.port_a_first_address = 0, ram_block1a_20.port_a_first_bit_number = 20, - ram_block1a_20.port_a_last_address = 63, - ram_block1a_20.port_a_logical_ram_depth = 64, + ram_block1a_20.port_a_last_address = 255, + ram_block1a_20.port_a_logical_ram_depth = 256, ram_block1a_20.port_a_logical_ram_width = 32, ram_block1a_20.port_b_address_clear = "none", ram_block1a_20.port_b_address_clock = "clock1", - ram_block1a_20.port_b_address_width = 6, + ram_block1a_20.port_b_address_width = 8, ram_block1a_20.port_b_data_out_clear = "clear0", ram_block1a_20.port_b_data_width = 1, ram_block1a_20.port_b_first_address = 0, ram_block1a_20.port_b_first_bit_number = 20, - ram_block1a_20.port_b_last_address = 63, - ram_block1a_20.port_b_logical_ram_depth = 64, + ram_block1a_20.port_b_last_address = 255, + ram_block1a_20.port_b_logical_ram_depth = 256, ram_block1a_20.port_b_logical_ram_width = 32, ram_block1a_20.port_b_read_enable_clock = "clock1", ram_block1a_20.power_up_uninitialized = "true", @@ -1577,12 +1577,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[2]}), .portadatain({data_a[21]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_21portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -1616,24 +1616,24 @@ module ram64_altsyncram ram_block1a_21.logical_ram_name = "ALTSYNCRAM", ram_block1a_21.mixed_port_feed_through_mode = "dont_care", ram_block1a_21.operation_mode = "dual_port", - ram_block1a_21.port_a_address_width = 6, + ram_block1a_21.port_a_address_width = 8, ram_block1a_21.port_a_byte_enable_mask_width = 1, ram_block1a_21.port_a_byte_size = 1, ram_block1a_21.port_a_data_width = 1, ram_block1a_21.port_a_first_address = 0, ram_block1a_21.port_a_first_bit_number = 21, - ram_block1a_21.port_a_last_address = 63, - ram_block1a_21.port_a_logical_ram_depth = 64, + ram_block1a_21.port_a_last_address = 255, + ram_block1a_21.port_a_logical_ram_depth = 256, ram_block1a_21.port_a_logical_ram_width = 32, ram_block1a_21.port_b_address_clear = "none", ram_block1a_21.port_b_address_clock = "clock1", - ram_block1a_21.port_b_address_width = 6, + ram_block1a_21.port_b_address_width = 8, ram_block1a_21.port_b_data_out_clear = "clear0", ram_block1a_21.port_b_data_width = 1, ram_block1a_21.port_b_first_address = 0, ram_block1a_21.port_b_first_bit_number = 21, - ram_block1a_21.port_b_last_address = 63, - ram_block1a_21.port_b_logical_ram_depth = 64, + ram_block1a_21.port_b_last_address = 255, + ram_block1a_21.port_b_logical_ram_depth = 256, ram_block1a_21.port_b_logical_ram_width = 32, ram_block1a_21.port_b_read_enable_clock = "clock1", ram_block1a_21.power_up_uninitialized = "true", @@ -1646,12 +1646,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[2]}), .portadatain({data_a[22]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_22portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -1685,24 +1685,24 @@ module ram64_altsyncram ram_block1a_22.logical_ram_name = "ALTSYNCRAM", ram_block1a_22.mixed_port_feed_through_mode = "dont_care", ram_block1a_22.operation_mode = "dual_port", - ram_block1a_22.port_a_address_width = 6, + ram_block1a_22.port_a_address_width = 8, ram_block1a_22.port_a_byte_enable_mask_width = 1, ram_block1a_22.port_a_byte_size = 1, ram_block1a_22.port_a_data_width = 1, ram_block1a_22.port_a_first_address = 0, ram_block1a_22.port_a_first_bit_number = 22, - ram_block1a_22.port_a_last_address = 63, - ram_block1a_22.port_a_logical_ram_depth = 64, + ram_block1a_22.port_a_last_address = 255, + ram_block1a_22.port_a_logical_ram_depth = 256, ram_block1a_22.port_a_logical_ram_width = 32, ram_block1a_22.port_b_address_clear = "none", ram_block1a_22.port_b_address_clock = "clock1", - ram_block1a_22.port_b_address_width = 6, + ram_block1a_22.port_b_address_width = 8, ram_block1a_22.port_b_data_out_clear = "clear0", ram_block1a_22.port_b_data_width = 1, ram_block1a_22.port_b_first_address = 0, ram_block1a_22.port_b_first_bit_number = 22, - ram_block1a_22.port_b_last_address = 63, - ram_block1a_22.port_b_logical_ram_depth = 64, + ram_block1a_22.port_b_last_address = 255, + ram_block1a_22.port_b_logical_ram_depth = 256, ram_block1a_22.port_b_logical_ram_width = 32, ram_block1a_22.port_b_read_enable_clock = "clock1", ram_block1a_22.power_up_uninitialized = "true", @@ -1715,12 +1715,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[2]}), .portadatain({data_a[23]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_23portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -1754,24 +1754,24 @@ module ram64_altsyncram ram_block1a_23.logical_ram_name = "ALTSYNCRAM", ram_block1a_23.mixed_port_feed_through_mode = "dont_care", ram_block1a_23.operation_mode = "dual_port", - ram_block1a_23.port_a_address_width = 6, + ram_block1a_23.port_a_address_width = 8, ram_block1a_23.port_a_byte_enable_mask_width = 1, ram_block1a_23.port_a_byte_size = 1, ram_block1a_23.port_a_data_width = 1, ram_block1a_23.port_a_first_address = 0, ram_block1a_23.port_a_first_bit_number = 23, - ram_block1a_23.port_a_last_address = 63, - ram_block1a_23.port_a_logical_ram_depth = 64, + ram_block1a_23.port_a_last_address = 255, + ram_block1a_23.port_a_logical_ram_depth = 256, ram_block1a_23.port_a_logical_ram_width = 32, ram_block1a_23.port_b_address_clear = "none", ram_block1a_23.port_b_address_clock = "clock1", - ram_block1a_23.port_b_address_width = 6, + ram_block1a_23.port_b_address_width = 8, ram_block1a_23.port_b_data_out_clear = "clear0", ram_block1a_23.port_b_data_width = 1, ram_block1a_23.port_b_first_address = 0, ram_block1a_23.port_b_first_bit_number = 23, - ram_block1a_23.port_b_last_address = 63, - ram_block1a_23.port_b_logical_ram_depth = 64, + ram_block1a_23.port_b_last_address = 255, + ram_block1a_23.port_b_logical_ram_depth = 256, ram_block1a_23.port_b_logical_ram_width = 32, ram_block1a_23.port_b_read_enable_clock = "clock1", ram_block1a_23.power_up_uninitialized = "true", @@ -1784,12 +1784,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[3]}), .portadatain({data_a[24]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_24portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -1823,24 +1823,24 @@ module ram64_altsyncram ram_block1a_24.logical_ram_name = "ALTSYNCRAM", ram_block1a_24.mixed_port_feed_through_mode = "dont_care", ram_block1a_24.operation_mode = "dual_port", - ram_block1a_24.port_a_address_width = 6, + ram_block1a_24.port_a_address_width = 8, ram_block1a_24.port_a_byte_enable_mask_width = 1, ram_block1a_24.port_a_byte_size = 1, ram_block1a_24.port_a_data_width = 1, ram_block1a_24.port_a_first_address = 0, ram_block1a_24.port_a_first_bit_number = 24, - ram_block1a_24.port_a_last_address = 63, - ram_block1a_24.port_a_logical_ram_depth = 64, + ram_block1a_24.port_a_last_address = 255, + ram_block1a_24.port_a_logical_ram_depth = 256, ram_block1a_24.port_a_logical_ram_width = 32, ram_block1a_24.port_b_address_clear = "none", ram_block1a_24.port_b_address_clock = "clock1", - ram_block1a_24.port_b_address_width = 6, + ram_block1a_24.port_b_address_width = 8, ram_block1a_24.port_b_data_out_clear = "clear0", ram_block1a_24.port_b_data_width = 1, ram_block1a_24.port_b_first_address = 0, ram_block1a_24.port_b_first_bit_number = 24, - ram_block1a_24.port_b_last_address = 63, - ram_block1a_24.port_b_logical_ram_depth = 64, + ram_block1a_24.port_b_last_address = 255, + ram_block1a_24.port_b_logical_ram_depth = 256, ram_block1a_24.port_b_logical_ram_width = 32, ram_block1a_24.port_b_read_enable_clock = "clock1", ram_block1a_24.power_up_uninitialized = "true", @@ -1853,12 +1853,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[3]}), .portadatain({data_a[25]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_25portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -1892,24 +1892,24 @@ module ram64_altsyncram ram_block1a_25.logical_ram_name = "ALTSYNCRAM", ram_block1a_25.mixed_port_feed_through_mode = "dont_care", ram_block1a_25.operation_mode = "dual_port", - ram_block1a_25.port_a_address_width = 6, + ram_block1a_25.port_a_address_width = 8, ram_block1a_25.port_a_byte_enable_mask_width = 1, ram_block1a_25.port_a_byte_size = 1, ram_block1a_25.port_a_data_width = 1, ram_block1a_25.port_a_first_address = 0, ram_block1a_25.port_a_first_bit_number = 25, - ram_block1a_25.port_a_last_address = 63, - ram_block1a_25.port_a_logical_ram_depth = 64, + ram_block1a_25.port_a_last_address = 255, + ram_block1a_25.port_a_logical_ram_depth = 256, ram_block1a_25.port_a_logical_ram_width = 32, ram_block1a_25.port_b_address_clear = "none", ram_block1a_25.port_b_address_clock = "clock1", - ram_block1a_25.port_b_address_width = 6, + ram_block1a_25.port_b_address_width = 8, ram_block1a_25.port_b_data_out_clear = "clear0", ram_block1a_25.port_b_data_width = 1, ram_block1a_25.port_b_first_address = 0, ram_block1a_25.port_b_first_bit_number = 25, - ram_block1a_25.port_b_last_address = 63, - ram_block1a_25.port_b_logical_ram_depth = 64, + ram_block1a_25.port_b_last_address = 255, + ram_block1a_25.port_b_logical_ram_depth = 256, ram_block1a_25.port_b_logical_ram_width = 32, ram_block1a_25.port_b_read_enable_clock = "clock1", ram_block1a_25.power_up_uninitialized = "true", @@ -1922,12 +1922,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[3]}), .portadatain({data_a[26]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_26portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -1961,24 +1961,24 @@ module ram64_altsyncram ram_block1a_26.logical_ram_name = "ALTSYNCRAM", ram_block1a_26.mixed_port_feed_through_mode = "dont_care", ram_block1a_26.operation_mode = "dual_port", - ram_block1a_26.port_a_address_width = 6, + ram_block1a_26.port_a_address_width = 8, ram_block1a_26.port_a_byte_enable_mask_width = 1, ram_block1a_26.port_a_byte_size = 1, ram_block1a_26.port_a_data_width = 1, ram_block1a_26.port_a_first_address = 0, ram_block1a_26.port_a_first_bit_number = 26, - ram_block1a_26.port_a_last_address = 63, - ram_block1a_26.port_a_logical_ram_depth = 64, + ram_block1a_26.port_a_last_address = 255, + ram_block1a_26.port_a_logical_ram_depth = 256, ram_block1a_26.port_a_logical_ram_width = 32, ram_block1a_26.port_b_address_clear = "none", ram_block1a_26.port_b_address_clock = "clock1", - ram_block1a_26.port_b_address_width = 6, + ram_block1a_26.port_b_address_width = 8, ram_block1a_26.port_b_data_out_clear = "clear0", ram_block1a_26.port_b_data_width = 1, ram_block1a_26.port_b_first_address = 0, ram_block1a_26.port_b_first_bit_number = 26, - ram_block1a_26.port_b_last_address = 63, - ram_block1a_26.port_b_logical_ram_depth = 64, + ram_block1a_26.port_b_last_address = 255, + ram_block1a_26.port_b_logical_ram_depth = 256, ram_block1a_26.port_b_logical_ram_width = 32, ram_block1a_26.port_b_read_enable_clock = "clock1", ram_block1a_26.power_up_uninitialized = "true", @@ -1991,12 +1991,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[3]}), .portadatain({data_a[27]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_27portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -2030,24 +2030,24 @@ module ram64_altsyncram ram_block1a_27.logical_ram_name = "ALTSYNCRAM", ram_block1a_27.mixed_port_feed_through_mode = "dont_care", ram_block1a_27.operation_mode = "dual_port", - ram_block1a_27.port_a_address_width = 6, + ram_block1a_27.port_a_address_width = 8, ram_block1a_27.port_a_byte_enable_mask_width = 1, ram_block1a_27.port_a_byte_size = 1, ram_block1a_27.port_a_data_width = 1, ram_block1a_27.port_a_first_address = 0, ram_block1a_27.port_a_first_bit_number = 27, - ram_block1a_27.port_a_last_address = 63, - ram_block1a_27.port_a_logical_ram_depth = 64, + ram_block1a_27.port_a_last_address = 255, + ram_block1a_27.port_a_logical_ram_depth = 256, ram_block1a_27.port_a_logical_ram_width = 32, ram_block1a_27.port_b_address_clear = "none", ram_block1a_27.port_b_address_clock = "clock1", - ram_block1a_27.port_b_address_width = 6, + ram_block1a_27.port_b_address_width = 8, ram_block1a_27.port_b_data_out_clear = "clear0", ram_block1a_27.port_b_data_width = 1, ram_block1a_27.port_b_first_address = 0, ram_block1a_27.port_b_first_bit_number = 27, - ram_block1a_27.port_b_last_address = 63, - ram_block1a_27.port_b_logical_ram_depth = 64, + ram_block1a_27.port_b_last_address = 255, + ram_block1a_27.port_b_logical_ram_depth = 256, ram_block1a_27.port_b_logical_ram_width = 32, ram_block1a_27.port_b_read_enable_clock = "clock1", ram_block1a_27.power_up_uninitialized = "true", @@ -2060,12 +2060,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[3]}), .portadatain({data_a[28]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_28portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -2099,24 +2099,24 @@ module ram64_altsyncram ram_block1a_28.logical_ram_name = "ALTSYNCRAM", ram_block1a_28.mixed_port_feed_through_mode = "dont_care", ram_block1a_28.operation_mode = "dual_port", - ram_block1a_28.port_a_address_width = 6, + ram_block1a_28.port_a_address_width = 8, ram_block1a_28.port_a_byte_enable_mask_width = 1, ram_block1a_28.port_a_byte_size = 1, ram_block1a_28.port_a_data_width = 1, ram_block1a_28.port_a_first_address = 0, ram_block1a_28.port_a_first_bit_number = 28, - ram_block1a_28.port_a_last_address = 63, - ram_block1a_28.port_a_logical_ram_depth = 64, + ram_block1a_28.port_a_last_address = 255, + ram_block1a_28.port_a_logical_ram_depth = 256, ram_block1a_28.port_a_logical_ram_width = 32, ram_block1a_28.port_b_address_clear = "none", ram_block1a_28.port_b_address_clock = "clock1", - ram_block1a_28.port_b_address_width = 6, + ram_block1a_28.port_b_address_width = 8, ram_block1a_28.port_b_data_out_clear = "clear0", ram_block1a_28.port_b_data_width = 1, ram_block1a_28.port_b_first_address = 0, ram_block1a_28.port_b_first_bit_number = 28, - ram_block1a_28.port_b_last_address = 63, - ram_block1a_28.port_b_logical_ram_depth = 64, + ram_block1a_28.port_b_last_address = 255, + ram_block1a_28.port_b_logical_ram_depth = 256, ram_block1a_28.port_b_logical_ram_width = 32, ram_block1a_28.port_b_read_enable_clock = "clock1", ram_block1a_28.power_up_uninitialized = "true", @@ -2129,12 +2129,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[3]}), .portadatain({data_a[29]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_29portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -2168,24 +2168,24 @@ module ram64_altsyncram ram_block1a_29.logical_ram_name = "ALTSYNCRAM", ram_block1a_29.mixed_port_feed_through_mode = "dont_care", ram_block1a_29.operation_mode = "dual_port", - ram_block1a_29.port_a_address_width = 6, + ram_block1a_29.port_a_address_width = 8, ram_block1a_29.port_a_byte_enable_mask_width = 1, ram_block1a_29.port_a_byte_size = 1, ram_block1a_29.port_a_data_width = 1, ram_block1a_29.port_a_first_address = 0, ram_block1a_29.port_a_first_bit_number = 29, - ram_block1a_29.port_a_last_address = 63, - ram_block1a_29.port_a_logical_ram_depth = 64, + ram_block1a_29.port_a_last_address = 255, + ram_block1a_29.port_a_logical_ram_depth = 256, ram_block1a_29.port_a_logical_ram_width = 32, ram_block1a_29.port_b_address_clear = "none", ram_block1a_29.port_b_address_clock = "clock1", - ram_block1a_29.port_b_address_width = 6, + ram_block1a_29.port_b_address_width = 8, ram_block1a_29.port_b_data_out_clear = "clear0", ram_block1a_29.port_b_data_width = 1, ram_block1a_29.port_b_first_address = 0, ram_block1a_29.port_b_first_bit_number = 29, - ram_block1a_29.port_b_last_address = 63, - ram_block1a_29.port_b_logical_ram_depth = 64, + ram_block1a_29.port_b_last_address = 255, + ram_block1a_29.port_b_logical_ram_depth = 256, ram_block1a_29.port_b_logical_ram_width = 32, ram_block1a_29.port_b_read_enable_clock = "clock1", ram_block1a_29.power_up_uninitialized = "true", @@ -2198,12 +2198,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[3]}), .portadatain({data_a[30]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_30portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -2237,24 +2237,24 @@ module ram64_altsyncram ram_block1a_30.logical_ram_name = "ALTSYNCRAM", ram_block1a_30.mixed_port_feed_through_mode = "dont_care", ram_block1a_30.operation_mode = "dual_port", - ram_block1a_30.port_a_address_width = 6, + ram_block1a_30.port_a_address_width = 8, ram_block1a_30.port_a_byte_enable_mask_width = 1, ram_block1a_30.port_a_byte_size = 1, ram_block1a_30.port_a_data_width = 1, ram_block1a_30.port_a_first_address = 0, ram_block1a_30.port_a_first_bit_number = 30, - ram_block1a_30.port_a_last_address = 63, - ram_block1a_30.port_a_logical_ram_depth = 64, + ram_block1a_30.port_a_last_address = 255, + ram_block1a_30.port_a_logical_ram_depth = 256, ram_block1a_30.port_a_logical_ram_width = 32, ram_block1a_30.port_b_address_clear = "none", ram_block1a_30.port_b_address_clock = "clock1", - ram_block1a_30.port_b_address_width = 6, + ram_block1a_30.port_b_address_width = 8, ram_block1a_30.port_b_data_out_clear = "clear0", ram_block1a_30.port_b_data_width = 1, ram_block1a_30.port_b_first_address = 0, ram_block1a_30.port_b_first_bit_number = 30, - ram_block1a_30.port_b_last_address = 63, - ram_block1a_30.port_b_logical_ram_depth = 64, + ram_block1a_30.port_b_last_address = 255, + ram_block1a_30.port_b_logical_ram_depth = 256, ram_block1a_30.port_b_logical_ram_width = 32, ram_block1a_30.port_b_read_enable_clock = "clock1", ram_block1a_30.power_up_uninitialized = "true", @@ -2267,12 +2267,12 @@ module ram64_altsyncram .clr0(aclr0), .ena0(wren_a), .ena1((rden_b_store | rden_b)), - .portaaddr({address_a_wire[5:0]}), + .portaaddr({address_a_wire[7:0]}), .portabyteenamasks({byteena_a[3]}), .portadatain({data_a[31]}), .portadataout(), .portawe(wren_a), - .portbaddr({address_b_wire[5:0]}), + .portbaddr({address_b_wire[7:0]}), .portbdataout(wire_ram_block1a_31portbdataout[0:0]), .portbre(rden_b) `ifndef FORMAL_VERIFICATION @@ -2306,24 +2306,24 @@ module ram64_altsyncram ram_block1a_31.logical_ram_name = "ALTSYNCRAM", ram_block1a_31.mixed_port_feed_through_mode = "dont_care", ram_block1a_31.operation_mode = "dual_port", - ram_block1a_31.port_a_address_width = 6, + ram_block1a_31.port_a_address_width = 8, ram_block1a_31.port_a_byte_enable_mask_width = 1, ram_block1a_31.port_a_byte_size = 1, ram_block1a_31.port_a_data_width = 1, ram_block1a_31.port_a_first_address = 0, ram_block1a_31.port_a_first_bit_number = 31, - ram_block1a_31.port_a_last_address = 63, - ram_block1a_31.port_a_logical_ram_depth = 64, + ram_block1a_31.port_a_last_address = 255, + ram_block1a_31.port_a_logical_ram_depth = 256, ram_block1a_31.port_a_logical_ram_width = 32, ram_block1a_31.port_b_address_clear = "none", ram_block1a_31.port_b_address_clock = "clock1", - ram_block1a_31.port_b_address_width = 6, + ram_block1a_31.port_b_address_width = 8, ram_block1a_31.port_b_data_out_clear = "clear0", ram_block1a_31.port_b_data_width = 1, ram_block1a_31.port_b_first_address = 0, ram_block1a_31.port_b_first_bit_number = 31, - ram_block1a_31.port_b_last_address = 63, - ram_block1a_31.port_b_logical_ram_depth = 64, + ram_block1a_31.port_b_last_address = 255, + ram_block1a_31.port_b_logical_ram_depth = 256, ram_block1a_31.port_b_logical_ram_width = 32, ram_block1a_31.port_b_read_enable_clock = "clock1", ram_block1a_31.power_up_uninitialized = "true", @@ -2333,14 +2333,14 @@ module ram64_altsyncram address_a_wire = address_a, address_b_wire = address_b, q_b = {wire_ram_block1a_31portbdataout[0], wire_ram_block1a_30portbdataout[0], wire_ram_block1a_29portbdataout[0], wire_ram_block1a_28portbdataout[0], wire_ram_block1a_27portbdataout[0], wire_ram_block1a_26portbdataout[0], wire_ram_block1a_25portbdataout[0], wire_ram_block1a_24portbdataout[0], wire_ram_block1a_23portbdataout[0], wire_ram_block1a_22portbdataout[0], wire_ram_block1a_21portbdataout[0], wire_ram_block1a_20portbdataout[0], wire_ram_block1a_19portbdataout[0], wire_ram_block1a_18portbdataout[0], wire_ram_block1a_17portbdataout[0], wire_ram_block1a_16portbdataout[0], wire_ram_block1a_15portbdataout[0], wire_ram_block1a_14portbdataout[0], wire_ram_block1a_13portbdataout[0], wire_ram_block1a_12portbdataout[0], wire_ram_block1a_11portbdataout[0], wire_ram_block1a_10portbdataout[0], wire_ram_block1a_9portbdataout[0], wire_ram_block1a_8portbdataout[0], wire_ram_block1a_7portbdataout[0], wire_ram_block1a_6portbdataout[0], wire_ram_block1a_5portbdataout[0], wire_ram_block1a_4portbdataout[0], wire_ram_block1a_3portbdataout[0], wire_ram_block1a_2portbdataout[0], wire_ram_block1a_1portbdataout[0], wire_ram_block1a_0portbdataout[0]}; -endmodule //ram64_altsyncram +endmodule //ram256_altsyncram //VALID FILE // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on -module ram64 ( +module ram256 ( aclr, byteena_a, clock, @@ -2355,9 +2355,9 @@ module ram64 ( input [3:0] byteena_a; input clock; input [31:0] data; - input [5:0] rdaddress; + input [7:0] rdaddress; input rden; - input [5:0] wraddress; + input [7:0] wraddress; input wren; output [31:0] q; `ifndef ALTERA_RESERVED_QIS @@ -2375,7 +2375,7 @@ module ram64 ( wire [31:0] sub_wire0; wire [31:0] q = sub_wire0[31:0]; - ram64_altsyncram ram64_altsyncram_component ( + ram256_altsyncram ram256_altsyncram_component ( .aclr0 (aclr), .address_a (wraddress), .address_b (rdaddress), @@ -2421,9 +2421,9 @@ endmodule // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -// Retrieval info: PRIVATE: MEMSIZE NUMERIC "2048" +// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192" // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" -// Retrieval info: PRIVATE: MIFfilename STRING "ram64.mif" +// Retrieval info: PRIVATE: MIFfilename STRING "ram256.mif" // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "1" // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" @@ -2459,16 +2459,16 @@ endmodule // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "64" -// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "64" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" +// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256" // Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "CLEAR0" // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "TRUE" // Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "CLOCK0" // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" -// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "6" -// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "6" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8" // Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" // Retrieval info: CONSTANT: WIDTH_B NUMERIC "32" // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4" @@ -2477,24 +2477,24 @@ endmodule // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" // Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]" // Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]" -// Retrieval info: USED_PORT: rdaddress 0 0 6 0 INPUT NODEFVAL "rdaddress[5..0]" +// Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL "rdaddress[7..0]" // Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden" -// Retrieval info: USED_PORT: wraddress 0 0 6 0 INPUT NODEFVAL "wraddress[5..0]" +// Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL "wraddress[7..0]" // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" // Retrieval info: CONNECT: @aclr0 0 0 0 0 aclr 0 0 0 0 -// Retrieval info: CONNECT: @address_a 0 0 6 0 wraddress 0 0 6 0 -// Retrieval info: CONNECT: @address_b 0 0 6 0 rdaddress 0 0 6 0 +// Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0 +// Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0 // Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena_a 0 0 4 0 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 // Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0 // Retrieval info: CONNECT: @rden_b 0 0 0 0 rden 0 0 0 0 // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 // Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0 -// Retrieval info: GEN_FILE: TYPE_NORMAL ram64.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL ram64.inc FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL ram64.cmp FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL ram64.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL ram64_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL ram64_bb.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL ram64_syn.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram256.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram256.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram256.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram256.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram256_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram256_bb.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram256_syn.v TRUE // Retrieval info: LIB_FILE: altera_mf diff --git a/ws281x_cube_controller.qpf b/neopixel_led_controller.qpf similarity index 96% rename from ws281x_cube_controller.qpf rename to neopixel_led_controller.qpf index 5820978..7a41c2d 100644 --- a/ws281x_cube_controller.qpf +++ b/neopixel_led_controller.qpf @@ -28,4 +28,4 @@ DATE = "18:48:42 July 18, 2020" # Revisions -PROJECT_REVISION = "ws281x_cube_controller" +PROJECT_REVISION = "neopixel_led_controller" diff --git a/ws281x_cube_controller.qsf b/neopixel_led_controller.qsf similarity index 64% rename from ws281x_cube_controller.qsf rename to neopixel_led_controller.qsf index 76d393c..f30b94e 100644 --- a/ws281x_cube_controller.qsf +++ b/neopixel_led_controller.qsf @@ -26,7 +26,7 @@ # Notes: # # 1) The default values for assignments are stored in the file: -# ws281x_cube_controller_assignment_defaults.qdf +# neopixel_led_controller_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # @@ -46,20 +46,19 @@ set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Lite Edition" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON set_global_assignment -name SYSTEMVERILOG_FILE rtl/top.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/rst_sync.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/edge_detect.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/sys_ctrl.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/regfile.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/rst_syn.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/sys_ctl.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/edge2en.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/spi_slave.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/layer_ctrl.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/layer_conf.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/layer_code.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/ws281x_ctrl.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/ws281x_conf.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/ws281x_code.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/channel_ctl.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/channel_out.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/waveform_ctl.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/waveform_gen.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/segment_led.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/pulse_counter.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/fps_counter.sv set_global_assignment -name QIP_FILE ip/pll/pll.qip -set_global_assignment -name QIP_FILE ip/ram/ram64.qip +set_global_assignment -name QIP_FILE ip/ram/ram256.qip set_global_assignment -name QSYS_FILE ip/clk/globalclk.qsys # Pin & Location Assignments @@ -70,22 +69,22 @@ set_location_assignment PIN_P15 -to dc_i set_location_assignment PIN_R14 -to spi_sclk_i set_location_assignment PIN_P12 -to spi_mosi_i set_location_assignment PIN_R11 -to spi_cs_n_i -set_location_assignment PIN_R5 -to ws281x_code_o[7] -set_location_assignment PIN_L7 -to ws281x_code_o[6] -set_location_assignment PIN_P4 -to ws281x_code_o[5] -set_location_assignment PIN_L6 -to ws281x_code_o[4] -set_location_assignment PIN_R3 -to ws281x_code_o[3] -set_location_assignment PIN_M5 -to ws281x_code_o[2] -set_location_assignment PIN_P3 -to ws281x_code_o[1] -set_location_assignment PIN_M4 -to ws281x_code_o[0] -set_location_assignment PIN_N15 -to water_led_o[7] -set_location_assignment PIN_N14 -to water_led_o[6] -set_location_assignment PIN_M14 -to water_led_o[5] -set_location_assignment PIN_M12 -to water_led_o[4] -set_location_assignment PIN_L15 -to water_led_o[3] -set_location_assignment PIN_K12 -to water_led_o[2] -set_location_assignment PIN_L11 -to water_led_o[1] -set_location_assignment PIN_K11 -to water_led_o[0] +set_location_assignment PIN_C8 -to neopixel_code_o[15] +set_location_assignment PIN_B7 -to neopixel_code_o[14] +set_location_assignment PIN_D7 -to neopixel_code_o[13] +set_location_assignment PIN_E7 -to neopixel_code_o[12] +set_location_assignment PIN_B6 -to neopixel_code_o[11] +set_location_assignment PIN_A7 -to neopixel_code_o[10] +set_location_assignment PIN_A5 -to neopixel_code_o[9] +set_location_assignment PIN_B4 -to neopixel_code_o[8] +set_location_assignment PIN_R5 -to neopixel_code_o[7] +set_location_assignment PIN_L7 -to neopixel_code_o[6] +set_location_assignment PIN_P4 -to neopixel_code_o[5] +set_location_assignment PIN_L6 -to neopixel_code_o[4] +set_location_assignment PIN_R3 -to neopixel_code_o[3] +set_location_assignment PIN_M5 -to neopixel_code_o[2] +set_location_assignment PIN_P3 -to neopixel_code_o[1] +set_location_assignment PIN_M4 -to neopixel_code_o[0] set_location_assignment PIN_E2 -to segment_led_1_o[8] set_location_assignment PIN_L1 -to segment_led_1_o[7] set_location_assignment PIN_G5 -to segment_led_1_o[6] @@ -109,7 +108,6 @@ set_location_assignment PIN_A3 -to segment_led_2_o[0] # ========================== set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 3.3V set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON # Compiler Assignments @@ -125,7 +123,7 @@ set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON set_global_assignment -name MUX_RESTRUCTURE OFF -set_global_assignment -name TOP_LEVEL_ENTITY ws281x_cube_controller +set_global_assignment -name TOP_LEVEL_ENTITY neopixel_led_controller # Fitter Assignments # ================== @@ -153,9 +151,7 @@ set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog) # ============================ set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "100000000 TRANSITIONS/S" -set_global_assignment -name VCCA_USER_VOLTAGE 3.3V -set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS MAXIMUM +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %" # start EDA_TEST_BENCH_SETTINGS(test) # ----------------------------------- @@ -168,29 +164,41 @@ set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS MAXIMUM # end EDA_TEST_BENCH_SETTINGS(test) # --------------------------------- -# start EDA_TEST_BENCH_SETTINGS(test_rst_sync) -# -------------------------------------------- +# start EDA_TEST_BENCH_SETTINGS(test_regfile) +# ------------------------------------------- # EDA Netlist Writer Assignments # ============================== - set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id test_rst_sync - set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME test_rst_sync -section_id test_rst_sync - set_global_assignment -name EDA_TEST_BENCH_FILE sim/test_rst_sync.sv -section_id test_rst_sync + set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id test_regfile + set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME test_regfile -section_id test_regfile + set_global_assignment -name EDA_TEST_BENCH_FILE sim/test_regfile.sv -section_id test_regfile -# end EDA_TEST_BENCH_SETTINGS(test_rst_sync) -# ------------------------------------------ +# end EDA_TEST_BENCH_SETTINGS(test_regfile) +# ----------------------------------------- -# start EDA_TEST_BENCH_SETTINGS(test_edge_detect) -# ----------------------------------------------- +# start EDA_TEST_BENCH_SETTINGS(test_rst_syn) +# ------------------------------------------- # EDA Netlist Writer Assignments # ============================== - set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id test_edge_detect - set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME test_edge_detect -section_id test_edge_detect - set_global_assignment -name EDA_TEST_BENCH_FILE sim/test_edge_detect.sv -section_id test_edge_detect + set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id test_rst_syn + set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME test_rst_syn -section_id test_rst_syn + set_global_assignment -name EDA_TEST_BENCH_FILE sim/test_rst_syn.sv -section_id test_rst_syn -# end EDA_TEST_BENCH_SETTINGS(test_edge_detect) -# --------------------------------------------- +# end EDA_TEST_BENCH_SETTINGS(test_rst_syn) +# ----------------------------------------- + +# start EDA_TEST_BENCH_SETTINGS(test_edge2en) +# ------------------------------------------- + + # EDA Netlist Writer Assignments + # ============================== + set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id test_edge2en + set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME test_edge2en -section_id test_edge2en + set_global_assignment -name EDA_TEST_BENCH_FILE sim/test_edge2en.sv -section_id test_edge2en + +# end EDA_TEST_BENCH_SETTINGS(test_edge2en) +# ----------------------------------------- # start EDA_TEST_BENCH_SETTINGS(test_spi_slave) # --------------------------------------------- @@ -204,77 +212,53 @@ set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS MAXIMUM # end EDA_TEST_BENCH_SETTINGS(test_spi_slave) # ------------------------------------------- -# start EDA_TEST_BENCH_SETTINGS(test_layer_ctrl) -# ---------------------------------------------- - - # EDA Netlist Writer Assignments - # ============================== - set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id test_layer_ctrl - set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME test_layer_ctrl -section_id test_layer_ctrl - set_global_assignment -name EDA_TEST_BENCH_FILE sim/test_layer_ctrl.sv -section_id test_layer_ctrl - -# end EDA_TEST_BENCH_SETTINGS(test_layer_ctrl) -# -------------------------------------------- - -# start EDA_TEST_BENCH_SETTINGS(test_layer_conf) -# ---------------------------------------------- - - # EDA Netlist Writer Assignments - # ============================== - set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id test_layer_conf - set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME test_layer_conf -section_id test_layer_conf - set_global_assignment -name EDA_TEST_BENCH_FILE sim/test_layer_conf.sv -section_id test_layer_conf - -# end EDA_TEST_BENCH_SETTINGS(test_layer_conf) -# -------------------------------------------- - -# start EDA_TEST_BENCH_SETTINGS(test_layer_code) -# ---------------------------------------------- +# start EDA_TEST_BENCH_SETTINGS(test_channel_ctl) +# ----------------------------------------------- # EDA Netlist Writer Assignments # ============================== - set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id test_layer_code - set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME test_layer_code -section_id test_layer_code - set_global_assignment -name EDA_TEST_BENCH_FILE sim/test_layer_code.sv -section_id test_layer_code + set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id test_channel_ctl + set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME test_channel_ctl -section_id test_channel_ctl + set_global_assignment -name EDA_TEST_BENCH_FILE sim/test_channel_ctl.sv -section_id test_channel_ctl -# end EDA_TEST_BENCH_SETTINGS(test_layer_code) -# -------------------------------------------- +# end EDA_TEST_BENCH_SETTINGS(test_channel_ctl) +# --------------------------------------------- -# start EDA_TEST_BENCH_SETTINGS(test_ws281x_ctrl) +# start EDA_TEST_BENCH_SETTINGS(test_channel_out) # ----------------------------------------------- # EDA Netlist Writer Assignments # ============================== - set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id test_ws281x_ctrl - set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME test_ws281x_ctrl -section_id test_ws281x_ctrl - set_global_assignment -name EDA_TEST_BENCH_FILE sim/test_ws281x_ctrl.sv -section_id test_ws281x_ctrl + set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id test_channel_out + set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME test_channel_out -section_id test_channel_out + set_global_assignment -name EDA_TEST_BENCH_FILE sim/test_channel_out.sv -section_id test_channel_out -# end EDA_TEST_BENCH_SETTINGS(test_ws281x_ctrl) +# end EDA_TEST_BENCH_SETTINGS(test_channel_out) # --------------------------------------------- -# start EDA_TEST_BENCH_SETTINGS(test_ws281x_conf) -# ----------------------------------------------- +# start EDA_TEST_BENCH_SETTINGS(test_waveform_ctl) +# ------------------------------------------------ # EDA Netlist Writer Assignments # ============================== - set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id test_ws281x_conf - set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME test_ws281x_conf -section_id test_ws281x_conf - set_global_assignment -name EDA_TEST_BENCH_FILE sim/test_ws281x_conf.sv -section_id test_ws281x_conf + set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id test_waveform_ctl + set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME test_waveform_ctl -section_id test_waveform_ctl + set_global_assignment -name EDA_TEST_BENCH_FILE sim/test_waveform_ctl.sv -section_id test_waveform_ctl -# end EDA_TEST_BENCH_SETTINGS(test_ws281x_conf) -# --------------------------------------------- +# end EDA_TEST_BENCH_SETTINGS(test_waveform_ctl) +# ---------------------------------------------- -# start EDA_TEST_BENCH_SETTINGS(test_ws281x_code) -# ----------------------------------------------- +# start EDA_TEST_BENCH_SETTINGS(test_waveform_gen) +# ------------------------------------------------ # EDA Netlist Writer Assignments # ============================== - set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id test_ws281x_code - set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME test_ws281x_code -section_id test_ws281x_code - set_global_assignment -name EDA_TEST_BENCH_FILE sim/test_ws281x_code.sv -section_id test_ws281x_code + set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id test_waveform_gen + set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME test_waveform_gen -section_id test_waveform_gen + set_global_assignment -name EDA_TEST_BENCH_FILE sim/test_waveform_gen.sv -section_id test_waveform_gen -# end EDA_TEST_BENCH_SETTINGS(test_ws281x_code) -# --------------------------------------------- +# end EDA_TEST_BENCH_SETTINGS(test_waveform_gen) +# ---------------------------------------------- # start EDA_TOOL_SETTINGS(eda_simulation) # --------------------------------------- @@ -284,16 +268,15 @@ set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS MAXIMUM set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation - set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH test_layer_code -section_id eda_simulation - set_global_assignment -name EDA_TEST_BENCH_NAME test_rst_sync -section_id eda_simulation - set_global_assignment -name EDA_TEST_BENCH_NAME test_edge_detect -section_id eda_simulation + set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH test_channel_out -section_id eda_simulation + set_global_assignment -name EDA_TEST_BENCH_NAME test_regfile -section_id eda_simulation + set_global_assignment -name EDA_TEST_BENCH_NAME test_rst_syn -section_id eda_simulation + set_global_assignment -name EDA_TEST_BENCH_NAME test_edge2en -section_id eda_simulation set_global_assignment -name EDA_TEST_BENCH_NAME test_spi_slave -section_id eda_simulation - set_global_assignment -name EDA_TEST_BENCH_NAME test_layer_ctrl -section_id eda_simulation - set_global_assignment -name EDA_TEST_BENCH_NAME test_layer_conf -section_id eda_simulation - set_global_assignment -name EDA_TEST_BENCH_NAME test_layer_code -section_id eda_simulation - set_global_assignment -name EDA_TEST_BENCH_NAME test_ws281x_ctrl -section_id eda_simulation - set_global_assignment -name EDA_TEST_BENCH_NAME test_ws281x_conf -section_id eda_simulation - set_global_assignment -name EDA_TEST_BENCH_NAME test_ws281x_code -section_id eda_simulation + set_global_assignment -name EDA_TEST_BENCH_NAME test_channel_ctl -section_id eda_simulation + set_global_assignment -name EDA_TEST_BENCH_NAME test_channel_out -section_id eda_simulation + set_global_assignment -name EDA_TEST_BENCH_NAME test_waveform_ctl -section_id eda_simulation + set_global_assignment -name EDA_TEST_BENCH_NAME test_waveform_gen -section_id eda_simulation set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR sim/modelsim -section_id eda_simulation # end EDA_TOOL_SETTINGS(eda_simulation) @@ -339,8 +322,8 @@ set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS MAXIMUM # end EDA_TOOL_SETTINGS(eda_board_design_signal_integrity) # -------------------------------------------------------- -# ------------------------------------ -# start ENTITY(ws281x_cube_controller) +# ------------------------------------- +# start ENTITY(neopixel_led_controller) # Pin & Location Assignments # ========================== @@ -350,22 +333,22 @@ set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS MAXIMUM set_instance_assignment -name FAST_INPUT_REGISTER ON -to spi_sclk_i set_instance_assignment -name FAST_INPUT_REGISTER OFF -to spi_mosi_i set_instance_assignment -name FAST_INPUT_REGISTER OFF -to spi_cs_n_i - set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to ws281x_code_o[7] - set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to ws281x_code_o[6] - set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to ws281x_code_o[5] - set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to ws281x_code_o[4] - set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to ws281x_code_o[3] - set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to ws281x_code_o[2] - set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to ws281x_code_o[1] - set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to ws281x_code_o[0] - set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to water_led_o[7] - set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to water_led_o[6] - set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to water_led_o[5] - set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to water_led_o[4] - set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to water_led_o[3] - set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to water_led_o[2] - set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to water_led_o[1] - set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to water_led_o[0] + set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[15] + set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[14] + set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[13] + set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[12] + set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[11] + set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[10] + set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[9] + set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[8] + set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[7] + set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[6] + set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[5] + set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[4] + set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[3] + set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[2] + set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[1] + set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[0] set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to segment_led_1_o[8] set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to segment_led_1_o[7] set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to segment_led_1_o[6] @@ -393,22 +376,22 @@ set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS MAXIMUM set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_sclk_i set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_mosi_i set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_cs_n_i - set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to ws281x_code_o[7] - set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to ws281x_code_o[6] - set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to ws281x_code_o[5] - set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to ws281x_code_o[4] - set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to ws281x_code_o[3] - set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to ws281x_code_o[2] - set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to ws281x_code_o[1] - set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to ws281x_code_o[0] - set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to water_led_o[7] - set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to water_led_o[6] - set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to water_led_o[5] - set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to water_led_o[4] - set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to water_led_o[3] - set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to water_led_o[2] - set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to water_led_o[1] - set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to water_led_o[0] + set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[15] + set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[14] + set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[13] + set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[12] + set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[11] + set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[10] + set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[9] + set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[8] + set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[7] + set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[6] + set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[5] + set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[4] + set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[3] + set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[2] + set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[1] + set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[0] set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to segment_led_1_o[8] set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to segment_led_1_o[7] set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to segment_led_1_o[6] @@ -440,6 +423,6 @@ set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS MAXIMUM # end DESIGN_PARTITION(Top) # ------------------------- -# end ENTITY(ws281x_cube_controller) -# ---------------------------------- +# end ENTITY(neopixel_led_controller) +# ----------------------------------- set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/ws281x_cube_controller.sdc b/neopixel_led_controller.sdc similarity index 80% rename from ws281x_cube_controller.sdc rename to neopixel_led_controller.sdc index d2c42f3..d73e771 100644 --- a/ws281x_cube_controller.sdc +++ b/neopixel_led_controller.sdc @@ -8,9 +8,8 @@ set_false_path -from [get_ports {spi_sclk_i}] set_false_path -from [get_ports {spi_mosi_i}] set_false_path -from [get_ports {spi_cs_n_i}] -set_false_path -to [get_ports {ws281x_code_o[*]}] +set_false_path -to [get_ports {neopixel_code_o[*]}] # FPS Counter -set_false_path -to [get_ports {water_led_o[*]}] set_false_path -to [get_ports {segment_led_1_o[*]}] set_false_path -to [get_ports {segment_led_2_o[*]}] diff --git a/rtl/channel_ctl.sv b/rtl/channel_ctl.sv new file mode 100644 index 0000000..8a07481 --- /dev/null +++ b/rtl/channel_ctl.sv @@ -0,0 +1,119 @@ +/* + * channel_ctl.sv + * + * Created on: 2020-04-06 23:08 + * Author: Jack Chen + */ + +module channel_ctl( + input logic clk_i, + input logic rst_n_i, + + input logic dc_i, + + input logic spi_byte_vld_i, + input logic [7:0] spi_byte_data_i, + + input logic [7:0] reg_chan_len_i, + input logic [3:0] reg_chan_cnt_i, + + output logic reg_wr_en_o, + output logic [2:0] reg_wr_addr_o, + + output logic [15:0] ram_wr_en_o, + output logic ram_wr_done_o, + output logic [ 7:0] ram_wr_addr_o, + output logic [ 3:0] ram_wr_byte_en_o +); + +typedef enum logic [7:0] { + CUBE0414_CONF_WR = 8'h2a, + CUBE0414_ADDR_WR = 8'h2b, + CUBE0414_DATA_WR = 8'h2c +} cmd_t; + +logic [7:0] wr_addr; + +logic addr_en; +logic [2:0] data_en; + +logic conf_wr; +logic [15:0] code_wr; + +wire addr_done = (wr_addr == reg_chan_len_i) & addr_en; +wire data_done = (wr_addr == reg_chan_len_i) & data_en[0]; + +genvar i; +generate + for (i = 0; i < 16; i++) begin: ram_wr_en + assign ram_wr_en_o[i] = spi_byte_vld_i & code_wr[i]; + end +endgenerate + +assign reg_wr_en_o = spi_byte_vld_i & conf_wr; +assign reg_wr_addr_o = wr_addr; + +assign ram_wr_done_o = spi_byte_vld_i & code_wr[reg_chan_cnt_i] & data_done; +assign ram_wr_addr_o = wr_addr; + +assign ram_wr_byte_en_o = {addr_en, data_en}; + +always_ff @(posedge clk_i or negedge rst_n_i) +begin + if (!rst_n_i) begin + wr_addr <= 8'h00; + + addr_en <= 1'b0; + data_en <= 3'b000; + + conf_wr <= 1'b0; + code_wr <= 16'h0000; + end else begin + if (spi_byte_vld_i) begin + if (!dc_i) begin // Command + wr_addr <= 8'h00; + + case (spi_byte_data_i) + CUBE0414_CONF_WR: begin // Write Reg Conf + addr_en <= 1'b0; + data_en <= 3'b000; + + conf_wr <= 1'b1; + code_wr <= 16'h0000; + end + CUBE0414_ADDR_WR: begin // Write RAM Addr + addr_en <= 1'b1; + data_en <= 3'b000; + + conf_wr <= 1'b0; + code_wr <= 16'h0001; + end + CUBE0414_DATA_WR: begin // Write RAM Data + addr_en <= 1'b0; + data_en <= 3'b100; + + conf_wr <= 1'b0; + code_wr <= 16'h0001; + end + default: begin + addr_en <= 1'b0; + data_en <= 3'b000; + + conf_wr <= 1'b0; + code_wr <= 16'h0000; + end + endcase + end else begin // Data + wr_addr <= (addr_done | data_done) ? 8'h00 : wr_addr + (conf_wr | addr_en | data_en[0]); + + addr_en <= addr_en & ~(addr_done & code_wr[reg_chan_cnt_i]); + data_en <= {data_en[0], data_en[2:1]}; + + conf_wr <= conf_wr; + code_wr <= code_wr << (addr_done | data_done); + end + end + end +end + +endmodule diff --git a/rtl/channel_out.sv b/rtl/channel_out.sv new file mode 100644 index 0000000..a20bce4 --- /dev/null +++ b/rtl/channel_out.sv @@ -0,0 +1,76 @@ +/* + * channel_out.sv + * + * Created on: 2020-04-06 23:09 + * Author: Jack Chen + */ + +module channel_out( + input logic clk_i, + input logic rst_n_i, + + input logic [7:0] reg_t0h_time_i, + input logic [7:0] reg_t0l_time_i, + input logic [7:0] reg_t1h_time_i, + input logic [7:0] reg_t1l_time_i, + + input logic ram_wr_en_i, + input logic ram_wr_done_i, + input logic [7:0] ram_wr_addr_i, + input logic [7:0] ram_wr_data_i, + input logic [3:0] ram_wr_byte_en_i, + + output logic bit_code_o +); + +logic ram_rd_en; +logic [ 7:0] ram_rd_addr; +logic [31:0] ram_rd_data; + +logic bit_vld, bit_rdy, bit_data; + +ram256 ram256( + .aclr(~rst_n_i), + .byteena_a(ram_wr_byte_en_i), + .clock(clk_i), + .data({ram_wr_data_i, ram_wr_data_i, ram_wr_data_i, ram_wr_data_i}), + .rdaddress(ram_rd_addr), + .rden(ram_rd_en), + .wraddress(ram_wr_addr_i), + .wren(ram_wr_en_i), + .q(ram_rd_data) +); + +waveform_ctl waveform_ctl( + .clk_i(clk_i), + .rst_n_i(rst_n_i), + + .bit_rdy_i(bit_rdy), + + .ram_wr_done_i(ram_wr_done_i), + .ram_rd_data_i(ram_rd_data), + + .bit_vld_o(bit_vld), + .bit_data_o(bit_data), + + .ram_rd_en_o(ram_rd_en), + .ram_rd_addr_o(ram_rd_addr) +); + +waveform_gen waveform_gen( + .clk_i(clk_i), + .rst_n_i(rst_n_i), + + .bit_vld_i(bit_vld), + .bit_data_i(bit_data), + + .reg_t0h_time_i(reg_t0h_time_i), + .reg_t0l_time_i(reg_t0l_time_i), + .reg_t1h_time_i(reg_t1h_time_i), + .reg_t1l_time_i(reg_t1l_time_i), + + .bit_rdy_o(bit_rdy), + .bit_code_o(bit_code_o) +); + +endmodule diff --git a/rtl/edge_detect.sv b/rtl/edge2en.sv similarity index 71% rename from rtl/edge_detect.sv rename to rtl/edge2en.sv index 38ece6f..fcff154 100644 --- a/rtl/edge_detect.sv +++ b/rtl/edge2en.sv @@ -1,11 +1,11 @@ /* - * edge_detect.sv + * edge2en.sv * * Created on: 2020-04-09 17:46 * Author: Jack Chen */ -module edge_detect( +module edge2en( input logic clk_i, input logic rst_n_i, @@ -13,14 +13,14 @@ module edge_detect( output logic pos_edge_o, output logic neg_edge_o, - output logic both_edge_o + output logic any_edge_o ); logic data_a, data_b; -assign pos_edge_o = ~data_b & data_a; -assign neg_edge_o = ~data_a & data_b; -assign both_edge_o = data_a ^ data_b; +assign pos_edge_o = ~data_b & data_a; +assign neg_edge_o = ~data_a & data_b; +assign any_edge_o = data_a ^ data_b; always_ff @(posedge clk_i or negedge rst_n_i) begin diff --git a/rtl/fps_counter.sv b/rtl/fps_counter.sv new file mode 100644 index 0000000..3d76b81 --- /dev/null +++ b/rtl/fps_counter.sv @@ -0,0 +1,49 @@ +/* + * fps_counter.sv + * + * Created on: 2020-04-07 18:54 + * Author: Jack Chen + */ + +module fps_counter( + input logic clk_i, + input logic rst_n_i, + + input logic pulse_i, + + output logic [8:0] segment_led_1_o, + output logic [8:0] segment_led_2_o +); + +localparam [26:0] CNT_1_S = 100 * 1000 * 1000; + +logic [7:0] count; +logic [7:0] pulse; + +logic [26:0] time_cnt; + +segment_led segment_led( + .rst_n_i(rst_n_i), + + .count_i(count), + + .segment_led_1_o(segment_led_1_o), + .segment_led_2_o(segment_led_2_o) +); + +always_ff @(posedge clk_i or negedge rst_n_i) +begin + if (!rst_n_i) begin + count <= 8'h00; + pulse <= 8'h00; + + time_cnt <= 27'h000_0000; + end else begin + count <= (time_cnt == CNT_1_S - 1) ? pulse : count; + pulse <= (time_cnt == CNT_1_S - 1) ? 8'h00 : pulse + pulse_i; + + time_cnt <= (time_cnt == CNT_1_S - 1) ? 27'h000_0000 : time_cnt + 1'b1; + end +end + +endmodule diff --git a/rtl/layer_code.sv b/rtl/layer_code.sv deleted file mode 100644 index ce5142b..0000000 --- a/rtl/layer_code.sv +++ /dev/null @@ -1,92 +0,0 @@ -/* - * layer_code.sv - * - * Created on: 2020-04-06 23:09 - * Author: Jack Chen - */ - -module layer_code( - input logic clk_i, - input logic rst_n_i, - - input logic wr_en_i, - input logic wr_done_i, - input logic [5:0] wr_addr_i, - input logic [7:0] wr_data_i, - input logic [3:0] wr_byte_en_i, - - input logic [7:0] t0h_cnt_i, - input logic [7:0] t0s_cnt_i, - input logic [7:0] t1h_cnt_i, - input logic [7:0] t1s_cnt_i, - - output logic ws281x_code_o -); - -logic rd_en; -logic [ 5:0] rd_addr; -logic [31:0] rd_data; -logic [ 7:0] tim_cnt; - -logic bit_vld, bit_rdy, bit_data; - -ram64 ram64( - .aclr(~rst_n_i), - .byteena_a(wr_byte_en_i), - .clock(clk_i), - .data({wr_data_i, wr_data_i, wr_data_i, wr_data_i}), - .rdaddress(rd_addr), - .rden(rd_en), - .wraddress(wr_addr_i), - .wren(wr_en_i), - .q(rd_data) -); - -ws281x_ctrl ws281x_ctrl( - .clk_i(clk_i), - .rst_n_i(rst_n_i), - - .bit_rdy_i(bit_rdy), - - .wr_done_i(wr_done_i), - .rd_data_i(rd_data), - .tim_cnt_i(tim_cnt), - - .bit_vld_o(bit_vld), - .bit_data_o(bit_data), - - .rd_en_o(rd_en), - .rd_addr_o(rd_addr) -); - -ws281x_conf ws281x_conf( - .clk_i(clk_i), - .rst_n_i(rst_n_i), - - .bit_vld_i(bit_vld), - .bit_data_i(bit_data), - - .t0h_cnt_i(t0h_cnt_i), - .t0s_cnt_i(t0s_cnt_i), - .t1h_cnt_i(t1h_cnt_i), - .t1s_cnt_i(t1s_cnt_i), - - .tim_cnt_o(tim_cnt) -); - -ws281x_code ws281x_code( - .clk_i(clk_i), - .rst_n_i(rst_n_i), - - .bit_vld_i(bit_vld), - .bit_data_i(bit_data), - - .t0h_cnt_i(t0h_cnt_i), - .t1h_cnt_i(t1h_cnt_i), - .tim_cnt_i(tim_cnt), - - .bit_rdy_o(bit_rdy), - .bit_code_o(ws281x_code_o) -); - -endmodule diff --git a/rtl/layer_conf.sv b/rtl/layer_conf.sv deleted file mode 100644 index c2f8116..0000000 --- a/rtl/layer_conf.sv +++ /dev/null @@ -1,55 +0,0 @@ -/* - * layer_conf.sv - * - * Created on: 2020-04-29 20:16 - * Author: Jack Chen - */ - -module layer_conf( - input logic clk_i, - input logic rst_n_i, - - input logic wr_en_i, - input logic [5:0] wr_addr_i, - input logic [7:0] wr_data_i, - - output logic [7:0] t0h_cnt_o, - output logic [7:0] t0s_cnt_o, - output logic [7:0] t1h_cnt_o, - output logic [7:0] t1s_cnt_o -); - -logic [7:0] t0h_cnt; -logic [7:0] t0s_cnt; -logic [7:0] t1h_cnt; -logic [7:0] t1s_cnt; - -assign t0h_cnt_o = t0h_cnt; -assign t0s_cnt_o = t0s_cnt; -assign t1h_cnt_o = t1h_cnt; -assign t1s_cnt_o = t1s_cnt; - -always_ff @(posedge clk_i or negedge rst_n_i) -begin - if (!rst_n_i) begin - t0h_cnt <= 8'h00; - t0s_cnt <= 8'h00; - t1h_cnt <= 8'h00; - t1s_cnt <= 8'h00; - end else begin - if (wr_en_i) begin - case (wr_addr_i[1:0]) - 2'b00: - t0h_cnt <= wr_data_i; - 2'b01: - t0s_cnt <= wr_data_i + t0h_cnt; - 2'b10: - t1h_cnt <= wr_data_i; - 2'b11: - t1s_cnt <= wr_data_i + t1h_cnt; - endcase - end - end -end - -endmodule diff --git a/rtl/layer_ctrl.sv b/rtl/layer_ctrl.sv deleted file mode 100644 index 7c114d9..0000000 --- a/rtl/layer_ctrl.sv +++ /dev/null @@ -1,119 +0,0 @@ -/* - * layer_ctrl.sv - * - * Created on: 2020-04-06 23:08 - * Author: Jack Chen - */ - -module layer_ctrl( - input logic clk_i, - input logic rst_n_i, - - input logic dc_i, - - input logic byte_vld_i, - input logic [7:0] byte_data_i, - - output logic [8:0] wr_en_o, - output logic wr_done_o, - output logic [5:0] wr_addr_o, - output logic [3:0] wr_byte_en_o -); - -typedef enum logic [7:0] { - CUBE0414_CONF_WR = 8'h2a, - CUBE0414_ADDR_WR = 8'h2b, - CUBE0414_DATA_WR = 8'h2c -} cmd_t; - -logic conf_wr; -logic [7:0] code_wr; - -logic addr_en; -logic [2:0] data_en; - -logic [5:0] wr_addr; - -wire conf_done = (wr_addr == 6'd3); -wire code_done = code_wr[0]; - -wire addr_done = (wr_addr == 6'd63); -wire data_done = data_en[0]; - -wire layer_done = addr_done & data_done; -wire frame_done = code_done & layer_done; - -assign wr_en_o[8] = byte_vld_i & conf_wr; -assign wr_en_o[7] = byte_vld_i & code_wr[7]; -assign wr_en_o[6] = byte_vld_i & code_wr[6]; -assign wr_en_o[5] = byte_vld_i & code_wr[5]; -assign wr_en_o[4] = byte_vld_i & code_wr[4]; -assign wr_en_o[3] = byte_vld_i & code_wr[3]; -assign wr_en_o[2] = byte_vld_i & code_wr[2]; -assign wr_en_o[1] = byte_vld_i & code_wr[1]; -assign wr_en_o[0] = byte_vld_i & code_wr[0]; - -assign wr_done_o = byte_vld_i & frame_done; -assign wr_addr_o = wr_addr; - -assign wr_byte_en_o = {addr_en, data_en}; - -always_ff @(posedge clk_i or negedge rst_n_i) -begin - if (!rst_n_i) begin - conf_wr <= 1'b0; - code_wr <= 8'h00; - - addr_en <= 1'b0; - data_en <= 3'b000; - - wr_addr <= 6'h00; - end else begin - if (byte_vld_i) begin - if (!dc_i) begin // Command - case (byte_data_i) - CUBE0414_CONF_WR: begin // Write Reg Conf - conf_wr <= 1'b1; - code_wr <= 8'h00; - - addr_en <= 1'b0; - data_en <= 3'b000; - end - CUBE0414_ADDR_WR: begin // Write RAM Addr - conf_wr <= 1'b0; - code_wr <= 8'hff; - - addr_en <= 1'b1; - data_en <= 3'b000; - end - CUBE0414_DATA_WR: begin // Write RAM Data - conf_wr <= 1'b0; - code_wr <= 8'h80; - - addr_en <= 1'b0; - data_en <= 3'b100; - end - default: begin - conf_wr <= 1'b0; - code_wr <= 8'h00; - - addr_en <= 1'b0; - data_en <= 3'b000; - end - endcase - - wr_addr <= 6'h00; - end else begin // Data - conf_wr <= conf_wr & ~conf_done; - code_wr <= code_wr >> (~(conf_wr | addr_en) & layer_done); - - addr_en <= addr_en & ~addr_done; - data_en <= {data_en[0], data_en[2:1]}; - - wr_addr <= wr_addr + (conf_wr | addr_en | data_done); - end - end - end -end - -endmodule diff --git a/rtl/pulse_counter.sv b/rtl/pulse_counter.sv deleted file mode 100644 index 2528a94..0000000 --- a/rtl/pulse_counter.sv +++ /dev/null @@ -1,47 +0,0 @@ -/* - * pulse_counter.sv - * - * Created on: 2020-04-07 18:54 - * Author: Jack Chen - */ - -module pulse_counter( - input logic clk_i, - input logic rst_n_i, - - input logic pulse_i, - - output logic [7:0] water_led_o, - output logic [8:0] segment_led_1_o, - output logic [8:0] segment_led_2_o -); - -localparam [27:0] CNT_1_S = 200 * 1000 * 1000; - -logic [ 7:0] pulse; -logic [ 7:0] pul_cnt; -logic [27:0] tim_cnt; - -assign water_led_o = rst_n_i ? ~pul_cnt : 8'hff; - -segment_led segment_led( - .rst_n_i(rst_n_i), - .count_i(pulse), - .segment_led_1_o(segment_led_1_o), - .segment_led_2_o(segment_led_2_o) -); - -always_ff @(posedge clk_i or negedge rst_n_i) -begin - if (!rst_n_i) begin - pulse <= 8'h00; - pul_cnt <= 8'h00; - tim_cnt <= 28'h000_0000; - end else begin - pulse <= (tim_cnt == CNT_1_S) ? pul_cnt : pulse; - pul_cnt <= (tim_cnt == CNT_1_S) ? 8'h00 : pul_cnt + pulse_i; - tim_cnt <= (tim_cnt == CNT_1_S) ? 28'h000_0000 : tim_cnt + 1'b1; - end -end - -endmodule diff --git a/rtl/regfile.sv b/rtl/regfile.sv new file mode 100644 index 0000000..4bcf11b --- /dev/null +++ b/rtl/regfile.sv @@ -0,0 +1,48 @@ +/* + * regfile.sv + * + * Created on: 2020-04-29 20:16 + * Author: Jack Chen + */ + +module regfile( + input logic clk_i, + input logic rst_n_i, + + input logic reg_wr_en_i, + input logic [2:0] reg_wr_addr_i, + input logic [7:0] reg_wr_data_i, + + output logic [7:0] reg_t0h_time_o, + output logic [7:0] reg_t0l_time_o, + output logic [7:0] reg_t1h_time_o, + output logic [7:0] reg_t1l_time_o, + + output logic [7:0] reg_chan_len_o, + output logic [3:0] reg_chan_cnt_o +); + +logic [7:0] regs[6]; + +assign reg_t0h_time_o = regs[0]; +assign reg_t0l_time_o = regs[1]; +assign reg_t1h_time_o = regs[2]; +assign reg_t1l_time_o = regs[3]; + +assign reg_chan_len_o = regs[4]; +assign reg_chan_cnt_o = regs[5]; + +always_ff @(posedge clk_i or negedge rst_n_i) +begin + if (!rst_n_i) begin + for (integer i = 0; i < 6; i++) begin + regs[i] <= 8'h00; + end + end else begin + if (reg_wr_en_i) begin + regs[reg_wr_addr_i] <= reg_wr_data_i; + end + end +end + +endmodule diff --git a/rtl/rst_sync.sv b/rtl/rst_syn.sv similarity index 93% rename from rtl/rst_sync.sv rename to rtl/rst_syn.sv index 62dc03d..ddaf36a 100644 --- a/rtl/rst_sync.sv +++ b/rtl/rst_syn.sv @@ -1,11 +1,11 @@ /* - * rst_sync.sv + * rst_syn.sv * * Created on: 2020-05-07 18:57 * Author: Jack Chen */ -module rst_sync( +module rst_syn( input logic clk_i, input logic rst_n_i, diff --git a/rtl/segment_led.sv b/rtl/segment_led.sv index 423b2d8..ebae610 100644 --- a/rtl/segment_led.sv +++ b/rtl/segment_led.sv @@ -14,35 +14,19 @@ module segment_led( output logic [8:0] segment_led_2_o ); -logic [6:0] mem[16]; - -initial begin - mem[0] = 7'h3f; // 0 - mem[1] = 7'h06; // 1 - mem[2] = 7'h5b; // 2 - mem[3] = 7'h4f; // 3 - mem[4] = 7'h66; // 4 - mem[5] = 7'h6d; // 5 - mem[6] = 7'h7d; // 6 - mem[7] = 7'h07; // 7 - mem[8] = 7'h7f; // 8 - mem[9] = 7'h6f; // 9 - mem[10] = 7'h77; // A - mem[11] = 7'h40; // b - mem[12] = 7'h39; // C - mem[13] = 7'h5e; // d - mem[14] = 7'h79; // E - mem[15] = 7'h71; // F -end +logic [6:0] segment_num[16] = '{ + 7'h3f, 7'h06, 7'h5b, 7'h4f, 7'h66, 7'h6d, 7'h7d, 7'h07, // 0 1 2 3 4 5 6 7 + 7'h7f, 7'h6f, 7'h77, 7'h40, 7'h39, 7'h5e, 7'h79, 7'h71 // 8 9 A b C d E F +}; wire [3:0] num_1 = (count_i / 10) % 10; wire [3:0] num_2 = count_i % 10; -assign segment_led_1_o[6:0] = mem[num_1]; +assign segment_led_1_o[6:0] = segment_num[num_1]; assign segment_led_1_o[7] = (count_i / 100 >= 2) ? 1'b1 : 1'b0; assign segment_led_1_o[8] = ~rst_n_i; -assign segment_led_2_o[6:0] = mem[num_2]; +assign segment_led_2_o[6:0] = segment_num[num_2]; assign segment_led_2_o[7] = (count_i / 100 >= 1) ? 1'b1 : 1'b0; assign segment_led_2_o[8] = ~rst_n_i; diff --git a/rtl/spi_slave.sv b/rtl/spi_slave.sv index 874582c..6d98724 100644 --- a/rtl/spi_slave.sv +++ b/rtl/spi_slave.sv @@ -9,56 +9,62 @@ module spi_slave( input logic clk_i, input logic rst_n_i, - input logic spi_sclk_i, - input logic spi_mosi_i, - input logic spi_cs_n_i, + input logic spi_sclk_i, + input logic spi_mosi_i, + input logic spi_cs_n_i, + input logic [7:0] spi_byte_data_i, - output logic byte_vld_o, - output logic [7:0] byte_data_o + output logic spi_miso_o, + output logic spi_byte_vld_o, + output logic [7:0] spi_byte_data_o ); logic spi_cs; -logic spi_sclk; -logic spi_mosi; logic spi_rst_n; +logic spi_sclk_p; +logic spi_sclk_n; logic [2:0] bit_sel; +logic bit_mosi; logic byte_vld; -logic [7:0] byte_data; +logic [7:0] byte_mosi; +logic [7:0] byte_miso; -assign byte_vld_o = byte_vld; -assign byte_data_o = byte_data; +assign spi_miso_o = byte_miso[7]; +assign spi_byte_vld_o = byte_vld; +assign spi_byte_data_o = byte_mosi; -rst_sync spi_rst_n_sync( +rst_syn spi_rst_n_syn( .clk_i(clk_i), .rst_n_i(rst_n_i & ~spi_cs_n_i), .rst_n_o(spi_rst_n) ); -edge_detect spi_sclk_edge( - .clk_i(clk_i), - .rst_n_i(spi_rst_n), - .data_i(spi_sclk_i), - .pos_edge_o(spi_sclk) +edge2en spi_sclk_en( + .clk_i(clk_i), + .rst_n_i(spi_rst_n), + .data_i(spi_sclk_i), + .pos_edge_o(spi_sclk_p), + .neg_edge_o(spi_sclk_n) ); always_ff @(posedge clk_i or negedge spi_rst_n) begin if (!spi_rst_n) begin - spi_mosi <= 1'b0; - - bit_sel <= 3'h0; + bit_sel <= 3'h0; + bit_mosi <= 1'b0; byte_vld <= 1'b0; - byte_data <= 8'h00; + byte_mosi <= 8'h00; + byte_miso <= 8'h00; end else begin - spi_mosi <= spi_mosi_i; - - bit_sel <= bit_sel + spi_sclk; + bit_sel <= spi_sclk_p + bit_sel; + bit_mosi <= spi_mosi_i; - byte_vld <= spi_sclk & (bit_sel == 3'd7); - byte_data <= spi_sclk ? {byte_data[6:0], spi_mosi} : byte_data; + byte_vld <= spi_sclk_p & (bit_sel == 3'h7); + byte_mosi <= spi_sclk_p ? {byte_mosi[6:0], bit_mosi} : byte_mosi; + byte_miso <= spi_sclk_n ? ((bit_sel == 3'h0) ? spi_byte_data_i : {byte_miso[6:0], 1'b0}) : byte_miso; end end diff --git a/rtl/sys_ctrl.sv b/rtl/sys_ctl.sv similarity index 79% rename from rtl/sys_ctrl.sv rename to rtl/sys_ctl.sv index fcb76f3..9c72942 100644 --- a/rtl/sys_ctrl.sv +++ b/rtl/sys_ctl.sv @@ -1,11 +1,11 @@ /* - * sys_ctrl.sv + * sys_ctl.sv * * Created on: 2020-05-07 09:58 * Author: Jack Chen */ -module sys_ctrl( +module sys_ctl( input logic clk_i, input logic rst_n_i, @@ -13,13 +13,13 @@ module sys_ctrl( output logic sys_rst_n_o ); -logic pll_200m; +logic pll_100m; logic pll_locked; logic pll_rst_n; logic sys_rst_n; -rst_sync pll_rst_n_sync( +rst_syn pll_rst_n_syn( .clk_i(clk_i), .rst_n_i(rst_n_i), .rst_n_o(pll_rst_n) @@ -28,18 +28,18 @@ rst_sync pll_rst_n_sync( pll pll( .areset(~pll_rst_n), .inclk0(clk_i), - .c0(pll_200m), + .c0(pll_100m), .locked(pll_locked) ); -rst_sync sys_rst_n_sync( - .clk_i(pll_200m), +rst_syn sys_rst_n_syn( + .clk_i(pll_100m), .rst_n_i(rst_n_i & pll_locked), .rst_n_o(sys_rst_n) ); globalclk global_clk( - .inclk(pll_200m), + .inclk(pll_100m), .outclk(sys_clk_o) ); diff --git a/rtl/top.sv b/rtl/top.sv index 6d5b350..90b7406 100644 --- a/rtl/top.sv +++ b/rtl/top.sv @@ -5,7 +5,7 @@ * Author: Jack Chen */ -module ws281x_cube_controller( +module neopixel_led_controller( input logic clk_i, // clk_i = 12 MHz input logic rst_n_i, // rst_n_i, active low @@ -14,30 +14,35 @@ module ws281x_cube_controller( input logic spi_mosi_i, input logic spi_cs_n_i, - output logic [7:0] ws281x_code_o, + output logic [15:0] neopixel_code_o, - output logic [7:0] water_led_o, // Optional, FPS Counter - output logic [8:0] segment_led_1_o, // Optional, FPS Counter - output logic [8:0] segment_led_2_o // Optional, FPS Counter + output logic [8:0] segment_led_1_o, // FPS Counter + output logic [8:0] segment_led_2_o // FPS Counter ); logic sys_clk; logic sys_rst_n; -logic byte_vld; -logic [7:0] byte_data; +logic spi_byte_vld; +logic [7:0] spi_byte_data; -logic [8:0] wr_en; -logic wr_done; -logic [5:0] wr_addr; -logic [3:0] wr_byte_en; +logic [7:0] reg_t0h_time; +logic [7:0] reg_t0l_time; +logic [7:0] reg_t1h_time; +logic [7:0] reg_t1l_time; -logic [7:0] t0h_cnt; -logic [7:0] t0s_cnt; -logic [7:0] t1h_cnt; -logic [7:0] t1s_cnt; +logic [7:0] reg_chan_len; +logic [3:0] reg_chan_cnt; -sys_ctrl sys_ctrl( +logic reg_wr_en; +logic [2:0] reg_wr_addr; + +logic [15:0] ram_wr_en; +logic ram_wr_done; +logic [ 7:0] ram_wr_addr; +logic [ 3:0] ram_wr_byte_en; + +sys_ctl sys_ctl( .clk_i(clk_i), .rst_n_i(rst_n_i), @@ -53,190 +58,77 @@ spi_slave spi_slave( .spi_mosi_i(spi_mosi_i), .spi_cs_n_i(spi_cs_n_i), - .byte_vld_o(byte_vld), - .byte_data_o(byte_data) + .spi_byte_vld_o(spi_byte_vld), + .spi_byte_data_o(spi_byte_data) ); -layer_ctrl layer_ctrl( +channel_ctl channel_ctl( .clk_i(sys_clk), .rst_n_i(sys_rst_n), .dc_i(dc_i), - .byte_vld_i(byte_vld), - .byte_data_i(byte_data), - - .wr_en_o(wr_en), - .wr_done_o(wr_done), - .wr_addr_o(wr_addr), - .wr_byte_en_o(wr_byte_en) -); - -layer_conf layer_conf( - .clk_i(sys_clk), - .rst_n_i(sys_rst_n), - - .wr_en_i(wr_en[8]), - .wr_addr_i(wr_addr), - .wr_data_i(byte_data), - - .t0h_cnt_o(t0h_cnt), - .t0s_cnt_o(t0s_cnt), - .t1h_cnt_o(t1h_cnt), - .t1s_cnt_o(t1s_cnt) -); - -layer_code layer_code7( - .clk_i(sys_clk), - .rst_n_i(sys_rst_n), - - .wr_en_i(wr_en[7]), - .wr_done_i(wr_done), - .wr_addr_i(wr_addr), - .wr_data_i(byte_data), - .wr_byte_en_i(wr_byte_en), - - .t0h_cnt_i(t0h_cnt), - .t0s_cnt_i(t0s_cnt), - .t1h_cnt_i(t1h_cnt), - .t1s_cnt_i(t1s_cnt), - - .ws281x_code_o(ws281x_code_o[7]) -); - -layer_code layer_code6( - .clk_i(sys_clk), - .rst_n_i(sys_rst_n), - - .wr_en_i(wr_en[6]), - .wr_done_i(wr_done), - .wr_addr_i(wr_addr), - .wr_data_i(byte_data), - .wr_byte_en_i(wr_byte_en), - - .t0h_cnt_i(t0h_cnt), - .t0s_cnt_i(t0s_cnt), - .t1h_cnt_i(t1h_cnt), - .t1s_cnt_i(t1s_cnt), - - .ws281x_code_o(ws281x_code_o[6]) -); - -layer_code layer_code5( - .clk_i(sys_clk), - .rst_n_i(sys_rst_n), - - .wr_en_i(wr_en[5]), - .wr_done_i(wr_done), - .wr_addr_i(wr_addr), - .wr_data_i(byte_data), - .wr_byte_en_i(wr_byte_en), - - .t0h_cnt_i(t0h_cnt), - .t0s_cnt_i(t0s_cnt), - .t1h_cnt_i(t1h_cnt), - .t1s_cnt_i(t1s_cnt), - - .ws281x_code_o(ws281x_code_o[5]) -); - -layer_code layer_code4( - .clk_i(sys_clk), - .rst_n_i(sys_rst_n), - - .wr_en_i(wr_en[4]), - .wr_done_i(wr_done), - .wr_addr_i(wr_addr), - .wr_data_i(byte_data), - .wr_byte_en_i(wr_byte_en), - - .t0h_cnt_i(t0h_cnt), - .t0s_cnt_i(t0s_cnt), - .t1h_cnt_i(t1h_cnt), - .t1s_cnt_i(t1s_cnt), - - .ws281x_code_o(ws281x_code_o[4]) -); - -layer_code layer_code3( - .clk_i(sys_clk), - .rst_n_i(sys_rst_n), - - .wr_en_i(wr_en[3]), - .wr_done_i(wr_done), - .wr_addr_i(wr_addr), - .wr_data_i(byte_data), - .wr_byte_en_i(wr_byte_en), - - .t0h_cnt_i(t0h_cnt), - .t0s_cnt_i(t0s_cnt), - .t1h_cnt_i(t1h_cnt), - .t1s_cnt_i(t1s_cnt), - - .ws281x_code_o(ws281x_code_o[3]) -); - -layer_code layer_code2( - .clk_i(sys_clk), - .rst_n_i(sys_rst_n), - - .wr_en_i(wr_en[2]), - .wr_done_i(wr_done), - .wr_addr_i(wr_addr), - .wr_data_i(byte_data), - .wr_byte_en_i(wr_byte_en), - - .t0h_cnt_i(t0h_cnt), - .t0s_cnt_i(t0s_cnt), - .t1h_cnt_i(t1h_cnt), - .t1s_cnt_i(t1s_cnt), - - .ws281x_code_o(ws281x_code_o[2]) -); - -layer_code layer_code1( - .clk_i(sys_clk), - .rst_n_i(sys_rst_n), + .spi_byte_vld_i(spi_byte_vld), + .spi_byte_data_i(spi_byte_data), - .wr_en_i(wr_en[1]), - .wr_done_i(wr_done), - .wr_addr_i(wr_addr), - .wr_data_i(byte_data), - .wr_byte_en_i(wr_byte_en), + .reg_chan_len_i(reg_chan_len), + .reg_chan_cnt_i(reg_chan_cnt), - .t0h_cnt_i(t0h_cnt), - .t0s_cnt_i(t0s_cnt), - .t1h_cnt_i(t1h_cnt), - .t1s_cnt_i(t1s_cnt), + .reg_wr_en_o(reg_wr_en), + .reg_wr_addr_o(reg_wr_addr), - .ws281x_code_o(ws281x_code_o[1]) + .ram_wr_en_o(ram_wr_en), + .ram_wr_done_o(ram_wr_done), + .ram_wr_addr_o(ram_wr_addr), + .ram_wr_byte_en_o(ram_wr_byte_en) ); -layer_code layer_code0( +genvar i; +generate + for (i = 0; i < 16; i++) begin: channel + channel_out out( + .clk_i(sys_clk), + .rst_n_i(sys_rst_n), + + .reg_t0h_time_i(reg_t0h_time), + .reg_t0l_time_i(reg_t0l_time), + .reg_t1h_time_i(reg_t1h_time), + .reg_t1l_time_i(reg_t1l_time), + + .ram_wr_en_i(ram_wr_en[i]), + .ram_wr_done_i(ram_wr_done), + .ram_wr_addr_i(ram_wr_addr), + .ram_wr_data_i(spi_byte_data), + .ram_wr_byte_en_i(ram_wr_byte_en), + + .bit_code_o(neopixel_code_o[i]) + ); + end +endgenerate + +regfile regfile( .clk_i(sys_clk), .rst_n_i(sys_rst_n), - .wr_en_i(wr_en[0]), - .wr_done_i(wr_done), - .wr_addr_i(wr_addr), - .wr_data_i(byte_data), - .wr_byte_en_i(wr_byte_en), + .reg_wr_en_i(reg_wr_en), + .reg_wr_addr_i(reg_wr_addr), + .reg_wr_data_i(spi_byte_data), - .t0h_cnt_i(t0h_cnt), - .t0s_cnt_i(t0s_cnt), - .t1h_cnt_i(t1h_cnt), - .t1s_cnt_i(t1s_cnt), + .reg_t0h_time_o(reg_t0h_time), + .reg_t0l_time_o(reg_t0l_time), + .reg_t1h_time_o(reg_t1h_time), + .reg_t1l_time_o(reg_t1l_time), - .ws281x_code_o(ws281x_code_o[0]) + .reg_chan_len_o(reg_chan_len), + .reg_chan_cnt_o(reg_chan_cnt) ); -pulse_counter fps_counter( +fps_counter fps_counter( .clk_i(sys_clk), .rst_n_i(sys_rst_n), - .pulse_i(wr_done), + .pulse_i(ram_wr_done), - .water_led_o(water_led_o), .segment_led_1_o(segment_led_1_o), .segment_led_2_o(segment_led_2_o) ); diff --git a/rtl/ws281x_ctrl.sv b/rtl/waveform_ctl.sv similarity index 51% rename from rtl/ws281x_ctrl.sv rename to rtl/waveform_ctl.sv index 675fe07..86c0ef8 100644 --- a/rtl/ws281x_ctrl.sv +++ b/rtl/waveform_ctl.sv @@ -1,25 +1,24 @@ /* - * ws281x_ctrl.sv + * waveform_ctl.sv * * Created on: 2020-04-06 23:09 * Author: Jack Chen */ -module ws281x_ctrl( +module waveform_ctl( input logic clk_i, input logic rst_n_i, input logic bit_rdy_i, - input logic wr_done_i, - input logic [31:0] rd_data_i, - input logic [ 7:0] tim_cnt_i, + input logic ram_wr_done_i, + input logic [31:0] ram_rd_data_i, output logic bit_vld_o, output logic bit_data_o, - output logic rd_en_o, - output logic [5:0] rd_addr_o + output logic ram_rd_en_o, + output logic [7:0] ram_rd_addr_o ); typedef enum logic [1:0] { @@ -33,25 +32,25 @@ state_t ctl_sta; logic bit_st; logic [4:0] bit_sel; -logic [8:0] bit_cnt; logic bit_vld, bit_data; logic rd_done; -logic [ 5:0] rd_addr; +logic [ 7:0] rd_addr; logic [23:0] rd_data; -wire ram_next = (bit_sel == 5'd23); -wire ram_done = (rd_addr == 6'h00); - wire bit_next = bit_st | bit_rdy_i; -wire cnt_done = (bit_cnt[8:0] == {tim_cnt_i, 1'b0} - 3'b110); + +wire data_next = (bit_sel == 5'd23); +wire data_done = (rd_addr == 8'h00); + +wire rd_en = (ctl_sta == READ_RAM); assign bit_vld_o = bit_vld; assign bit_data_o = bit_data; -assign rd_en_o = (ctl_sta == READ_RAM) & ~rd_done; -assign rd_addr_o = rd_addr; +assign ram_rd_en_o = rd_en; +assign ram_rd_addr_o = rd_addr; always_ff @(posedge clk_i or negedge rst_n_i) begin @@ -60,38 +59,36 @@ begin bit_st <= 1'b0; bit_sel <= 5'h00; - bit_cnt <= 9'h000; bit_vld <= 1'b0; bit_data <= 1'b0; rd_done <= 1'b0; - rd_addr <= 6'h00; + rd_addr <= 8'h00; rd_data <= 24'h00_0000; end else begin case (ctl_sta) IDLE: - ctl_sta <= wr_done_i ? READ_RAM : ctl_sta; + ctl_sta <= ram_wr_done_i ? READ_RAM : ctl_sta; READ_RAM: - ctl_sta <= rd_done ? SEND_BIT : ctl_sta; + ctl_sta <= SEND_BIT; SEND_BIT: - ctl_sta <= (bit_next & ram_next) ? (ram_done ? SYNC_BIT : READ_RAM) : ctl_sta; + ctl_sta <= (bit_next & data_next) ? (data_done ? SYNC_BIT : READ_RAM) : ctl_sta; SYNC_BIT: - ctl_sta <= cnt_done ? IDLE : ctl_sta; + ctl_sta <= ram_wr_done_i ? READ_RAM : (bit_next ? IDLE : ctl_sta); default: ctl_sta <= IDLE; endcase - bit_st <= (ctl_sta != SEND_BIT) & ((ctl_sta == IDLE) | bit_st); + bit_st <= (ctl_sta != SEND_BIT) & (bit_st | data_done); bit_sel <= (ctl_sta == SEND_BIT) ? bit_sel + bit_next : 5'h00; - bit_cnt <= (ctl_sta == SYNC_BIT) ? bit_cnt + 1'b1 : 9'h000; bit_vld <= (ctl_sta == SEND_BIT) & bit_next; - bit_data <= (ctl_sta == SEND_BIT) & bit_next ? rd_data[5'd23 - bit_sel] : bit_data; + bit_data <= (ctl_sta == SEND_BIT) & bit_vld ? rd_data[5'd23 - bit_sel] : bit_data; - rd_done <= rd_en_o; - rd_addr <= rd_done ? rd_data_i[29:24] : rd_addr; - rd_data <= rd_done ? rd_data_i[23:0] : rd_data; + rd_done <= rd_en; + rd_addr <= rd_done ? ram_rd_data_i[31:24] : rd_addr; + rd_data <= rd_done ? ram_rd_data_i[23:0] : rd_data; end end diff --git a/rtl/waveform_gen.sv b/rtl/waveform_gen.sv new file mode 100644 index 0000000..c6710f2 --- /dev/null +++ b/rtl/waveform_gen.sv @@ -0,0 +1,56 @@ +/* + * waveform_gen.sv + * + * Created on: 2020-04-06 23:09 + * Author: Jack Chen + */ + +module waveform_gen( + input logic clk_i, + input logic rst_n_i, + + input logic bit_vld_i, + input logic bit_data_i, + + input logic [7:0] reg_t0h_time_i, + input logic [7:0] reg_t0l_time_i, + input logic [7:0] reg_t1h_time_i, + input logic [7:0] reg_t1l_time_i, + + output logic bit_rdy_o, + output logic bit_code_o +); + +logic [8:0] bit_cnt; + +logic bit_busy, bit_code; + +wire [8:0] t0s_time = reg_t0h_time_i + reg_t0l_time_i; +wire [8:0] t1s_time = reg_t1h_time_i + reg_t1l_time_i; + +wire [8:0] bit_time = bit_data_i ? t1s_time : t0s_time; + +wire t0h_code = (bit_cnt <= reg_t0h_time_i) & ~bit_data_i; +wire t1h_code = (bit_cnt <= reg_t1h_time_i) & bit_data_i; + +wire bit_done = (bit_cnt == bit_time); + +assign bit_rdy_o = bit_busy & bit_done; +assign bit_code_o = bit_code; + +always_ff @(posedge clk_i or negedge rst_n_i) +begin + if (!rst_n_i) begin + bit_cnt <= 9'h000; + + bit_busy <= 1'b0; + bit_code <= 1'b0; + end else begin + bit_cnt <= bit_busy ? bit_cnt + 1'b1 : 9'h000; + + bit_busy <= bit_busy ? ~bit_done : bit_vld_i; + bit_code <= bit_busy & (t0h_code | t1h_code); + end +end + +endmodule diff --git a/rtl/ws281x_code.sv b/rtl/ws281x_code.sv deleted file mode 100644 index 4e36256..0000000 --- a/rtl/ws281x_code.sv +++ /dev/null @@ -1,53 +0,0 @@ -/* - * ws281x_code.sv - * - * Created on: 2020-04-06 23:09 - * Author: Jack Chen - */ - -module ws281x_code( - input logic clk_i, - input logic rst_n_i, - - input logic bit_vld_i, - input logic bit_data_i, - - input logic [7:0] t0h_cnt_i, - input logic [7:0] t1h_cnt_i, - input logic [7:0] tim_cnt_i, - - output logic bit_rdy_o, - output logic bit_code_o -); - -logic bit_bsy; -logic [8:0] bit_cnt; - -logic bit_rdy, bit_code; - -wire cnt_done = (bit_cnt[8:0] == {tim_cnt_i, 1'b0} - 2'b11); - -wire t0h_time = (bit_cnt[8:1] < t0h_cnt_i); -wire t1h_time = (bit_cnt[8:1] < t1h_cnt_i); - -assign bit_rdy_o = bit_rdy; -assign bit_code_o = bit_code; - -always_ff @(posedge clk_i or negedge rst_n_i) -begin - if (!rst_n_i) begin - bit_bsy <= 1'b0; - bit_cnt <= 9'h000; - - bit_rdy <= 1'b0; - bit_code <= 1'b0; - end else begin - bit_bsy <= bit_bsy ? ~cnt_done : bit_vld_i; - bit_cnt <= bit_bsy ? bit_cnt + 1'b1 : 9'h000; - - bit_rdy <= bit_bsy & cnt_done; - bit_code <= bit_bsy & ((bit_data_i & t1h_time) | (~bit_data_i & t0h_time)); - end -end - -endmodule diff --git a/rtl/ws281x_conf.sv b/rtl/ws281x_conf.sv deleted file mode 100644 index 36357ca..0000000 --- a/rtl/ws281x_conf.sv +++ /dev/null @@ -1,36 +0,0 @@ -/* - * ws281x_conf.sv - * - * Created on: 2020-07-10 14:29 - * Author: Jack Chen - */ - -module ws281x_conf( - input logic clk_i, - input logic rst_n_i, - - input logic bit_vld_i, - input logic bit_data_i, - - input logic [7:0] t0h_cnt_i, - input logic [7:0] t0s_cnt_i, - input logic [7:0] t1h_cnt_i, - input logic [7:0] t1s_cnt_i, - - output logic [7:0] tim_cnt_o -); - -logic [7:0] tim_cnt; - -assign tim_cnt_o = tim_cnt; - -always_ff @(posedge clk_i or negedge rst_n_i) -begin - if (!rst_n_i) begin - tim_cnt <= 8'h00; - end else begin - tim_cnt <= bit_vld_i ? (bit_data_i ? t1s_cnt_i : t0s_cnt_i) : tim_cnt; - end -end - -endmodule diff --git a/sim/test_channel_ctl.sv b/sim/test_channel_ctl.sv new file mode 100644 index 0000000..266c8af --- /dev/null +++ b/sim/test_channel_ctl.sv @@ -0,0 +1,146 @@ +/* + * test_channel_ctl.sv + * + * Created on: 2020-07-08 18:52 + * Author: Jack Chen + */ + +`timescale 1ns / 1ps + +module test_channel_ctl; + +logic clk_i; +logic rst_n_i; + +logic dc_i; + +logic spi_byte_vld_i; +logic [7:0] spi_byte_data_i; + +logic [7:0] reg_chan_len_i; +logic [3:0] reg_chan_cnt_i; + +logic reg_wr_en_o; +logic [2:0] reg_wr_addr_o; + +logic [15:0] ram_wr_en_o; +logic ram_wr_done_o; +logic [ 7:0] ram_wr_addr_o; +logic [ 3:0] ram_wr_byte_en_o; + +channel_ctl test_channel_ctl( + .clk_i(clk_i), + .rst_n_i(rst_n_i), + + .dc_i(dc_i), + + .spi_byte_vld_i(spi_byte_vld_i), + .spi_byte_data_i(spi_byte_data_i), + + .reg_chan_len_i(reg_chan_len_i), + .reg_chan_cnt_i(reg_chan_cnt_i), + + .reg_wr_en_o(reg_wr_en_o), + .reg_wr_addr_o(reg_wr_addr_o), + + .ram_wr_en_o(ram_wr_en_o), + .ram_wr_done_o(ram_wr_done_o), + .ram_wr_addr_o(ram_wr_addr_o), + .ram_wr_byte_en_o(ram_wr_byte_en_o) +); + +initial begin + clk_i <= 1'b1; + rst_n_i <= 1'b0; + + dc_i <= 1'b0; + + spi_byte_vld_i <= 1'b0; + spi_byte_data_i <= 8'h00; + + reg_chan_len_i <= 8'h3f; + reg_chan_cnt_i <= 4'h7; + + #2 rst_n_i <= 1'b1; +end + +always begin + #2.5 clk_i <= ~clk_i; +end + +always begin + // CONF_WR + #6 dc_i <= 1'b0; + spi_byte_vld_i <= 1'b1; + spi_byte_data_i <= 8'h2a; + #5 spi_byte_vld_i <= 1'b0; + + // CONF DATA 0: T0H time (10 ns) + #5 dc_i <= 1'b1; + spi_byte_vld_i <= 1'b1; + spi_byte_data_i <= 8'h01; + #5 spi_byte_vld_i <= 1'b0; + + // CONF DATA 1: T0L time (10 ns) + #5 dc_i <= 1'b1; + spi_byte_vld_i <= 1'b1; + spi_byte_data_i <= 8'h12; + #5 spi_byte_vld_i <= 1'b0; + + // CONF DATA 2: T1H time (10 ns) + #5 dc_i <= 1'b1; + spi_byte_vld_i <= 1'b1; + spi_byte_data_i <= 8'h23; + #5 spi_byte_vld_i <= 1'b0; + + // CONF DATA 3: T1L time (10 ns) + #5 dc_i <= 1'b1; + spi_byte_vld_i <= 1'b1; + spi_byte_data_i <= 8'h34; + #5 spi_byte_vld_i <= 1'b0; + + // CONF DATA 4: channel length + #5 dc_i <= 1'b1; + spi_byte_vld_i <= 1'b1; + spi_byte_data_i <= 8'h3f; + #5 spi_byte_vld_i <= 1'b0; + + // CONF DATA 5: channel count + #5 dc_i <= 1'b1; + spi_byte_vld_i <= 1'b1; + spi_byte_data_i <= 8'h07; + #5 spi_byte_vld_i <= 1'b0; + + // ADDR_WR + #5 dc_i <= 1'b0; + spi_byte_vld_i <= 1'b1; + spi_byte_data_i <= 8'h2b; + #5 spi_byte_vld_i <= 1'b0; + + // ADDR DATA + for (integer i = 0; i < 512; i++) begin + #5 dc_i <= 1'b1; + spi_byte_vld_i <= 1'b1; + spi_byte_data_i <= i; + #5 spi_byte_vld_i <= 1'b0; + end + + // DATA_WR + #5 dc_i <= 1'b0; + spi_byte_vld_i <= 1'b1; + spi_byte_data_i <= 8'h2c; + #5 spi_byte_vld_i <= 1'b0; + + // COLOR DATA + for (integer i = 0; i < 1536; i++) begin + #5 dc_i <= 1'b1; + spi_byte_vld_i <= 1'b1; + spi_byte_data_i <= i % 8'hff; + #5 spi_byte_vld_i <= 1'b0; + end + + #75 rst_n_i <= 1'b0; + #25 $stop; +end + +endmodule diff --git a/sim/test_channel_out.sv b/sim/test_channel_out.sv new file mode 100644 index 0000000..12459a0 --- /dev/null +++ b/sim/test_channel_out.sv @@ -0,0 +1,133 @@ +/* + * test_channel_out.sv + * + * Created on: 2020-07-08 21:15 + * Author: Jack Chen + */ + +`timescale 1ns / 1ps + +module test_channel_out; + +logic clk_i; +logic rst_n_i; + +logic [7:0] reg_t0h_time_i; +logic [7:0] reg_t0l_time_i; +logic [7:0] reg_t1h_time_i; +logic [7:0] reg_t1l_time_i; + +logic ram_wr_en_i; +logic ram_wr_done_i; +logic [7:0] ram_wr_addr_i; +logic [7:0] ram_wr_data_i; +logic [3:0] ram_wr_byte_en_i; + +logic bit_code_o; + +channel_out test_channel_out( + .clk_i(clk_i), + .rst_n_i(rst_n_i), + + .reg_t0h_time_i(reg_t0h_time_i), + .reg_t0l_time_i(reg_t0l_time_i), + .reg_t1h_time_i(reg_t1h_time_i), + .reg_t1l_time_i(reg_t1l_time_i), + + .ram_wr_en_i(ram_wr_en_i), + .ram_wr_done_i(ram_wr_done_i), + .ram_wr_addr_i(ram_wr_addr_i), + .ram_wr_data_i(ram_wr_data_i), + .ram_wr_byte_en_i(ram_wr_byte_en_i), + + .bit_code_o(bit_code_o) +); + +initial begin + clk_i <= 1'b1; + rst_n_i <= 1'b0; + + reg_t0h_time_i <= 8'h00; + reg_t0l_time_i <= 8'h01; + reg_t1h_time_i <= 8'h01; + reg_t1l_time_i <= 8'h00; + + ram_wr_en_i <= 1'b0; + ram_wr_done_i <= 1'b0; + ram_wr_addr_i <= 8'h00; + ram_wr_data_i <= 8'h00; + ram_wr_byte_en_i <= 4'b0000; + + #2 rst_n_i <= 1'b1; +end + +always begin + #2.5 clk_i <= ~clk_i; +end + +always begin + // ADDR 0 + #11 ram_wr_addr_i <= 8'h00; + ram_wr_data_i <= 8'h01; + ram_wr_byte_en_i <= 4'b1000; + ram_wr_en_i <= 1'b1; + #5 ram_wr_en_i <= 1'b0; + + #10 ram_wr_data_i <= 8'h00; + ram_wr_byte_en_i <= 4'b0111; + ram_wr_en_i <= 1'b1; + #5 ram_wr_en_i <= 1'b0; + + // ADDR 1 + #10 ram_wr_addr_i <= 8'h01; + ram_wr_data_i <= 8'h02; + ram_wr_byte_en_i <= 4'b1000; + ram_wr_en_i <= 1'b1; + #5 ram_wr_en_i <= 1'b0; + + #10 ram_wr_data_i <= 8'haa; + ram_wr_byte_en_i <= 4'b0111; + ram_wr_en_i <= 1'b1; + #5 ram_wr_en_i <= 1'b0; + + // ADDR 2 + #10 ram_wr_addr_i <= 8'h02; + ram_wr_data_i <= 8'h03; + ram_wr_byte_en_i <= 4'b1000; + ram_wr_en_i <= 1'b1; + #5 ram_wr_en_i <= 1'b0; + + #10 ram_wr_data_i <= 8'hcc; + ram_wr_byte_en_i <= 4'b0111; + ram_wr_en_i <= 1'b1; + #5 ram_wr_en_i <= 1'b0; + + // ADDR 3 + #10 ram_wr_addr_i <= 8'h03; + ram_wr_data_i <= 8'h00; + ram_wr_byte_en_i <= 4'b1000; + ram_wr_en_i <= 1'b1; + #5 ram_wr_en_i <= 1'b0; + + #10 ram_wr_data_i <= 8'hff; + ram_wr_byte_en_i <= 4'b0111; + ram_wr_en_i <= 1'b1; + #5 ram_wr_en_i <= 1'b0; + + #10 ram_wr_done_i <= 1'b1; + #5 ram_wr_done_i <= 1'b0; + + for (integer i = 0; i < 65536; i++) begin + #5 ram_wr_done_i <= 1'b1; + #5 ram_wr_done_i <= 1'b0; + end + + for (integer i = 0; i < 1024; i++) begin + #5 ram_wr_done_i <= 1'b0; + end + + #75 rst_n_i <= 1'b0; + #25 $stop; +end + +endmodule diff --git a/sim/test_edge_detect.sv b/sim/test_edge2en.sv similarity index 83% rename from sim/test_edge_detect.sv rename to sim/test_edge2en.sv index 9314c1a..658f572 100644 --- a/sim/test_edge_detect.sv +++ b/sim/test_edge2en.sv @@ -1,5 +1,5 @@ /* - * test_edge_detect.sv + * test_edge2en.sv * * Created on: 2020-07-08 17:16 * Author: Jack Chen @@ -7,7 +7,7 @@ `timescale 1ns / 1ps -module test_edge_detect; +module test_edge2en; logic clk_i; logic rst_n_i; @@ -16,9 +16,9 @@ logic data_i; logic pos_edge_o; logic neg_edge_o; -logic both_edge_o; +logic any_edge_o; -edge_detect test_edge_detect( +edge2en test_edge2en( .clk_i(clk_i), .rst_n_i(rst_n_i), @@ -26,7 +26,7 @@ edge_detect test_edge_detect( .pos_edge_o(pos_edge_o), .neg_edge_o(neg_edge_o), - .both_edge_o(both_edge_o) + .any_edge_o(any_edge_o) ); initial begin diff --git a/sim/test_layer_code.sv b/sim/test_layer_code.sv deleted file mode 100644 index 4e8867f..0000000 --- a/sim/test_layer_code.sv +++ /dev/null @@ -1,104 +0,0 @@ -/* - * test_layer_code.sv - * - * Created on: 2020-07-08 21:15 - * Author: Jack Chen - */ - -`timescale 1ns / 1ps - -module test_layer_code; - -logic clk_i; -logic rst_n_i; - -logic wr_en_i; -logic wr_done_i; -logic [5:0] wr_addr_i; -logic [7:0] wr_data_i; -logic [3:0] wr_byte_en_i; - -logic [7:0] t0h_cnt_i; -logic [7:0] t0s_cnt_i; -logic [7:0] t1h_cnt_i; -logic [7:0] t1s_cnt_i; - -logic ws281x_code_o; - -layer_code test_layer_code( - .clk_i(clk_i), - .rst_n_i(rst_n_i), - - .wr_en_i(wr_en_i), - .wr_done_i(wr_done_i), - .wr_addr_i(wr_addr_i), - .wr_data_i(wr_data_i), - .wr_byte_en_i(wr_byte_en_i), - - .t0h_cnt_i(t0h_cnt_i), - .t0s_cnt_i(t0s_cnt_i), - .t1h_cnt_i(t1h_cnt_i), - .t1s_cnt_i(t1s_cnt_i), - - .ws281x_code_o(ws281x_code_o) -); - -initial begin - clk_i <= 1'b1; - rst_n_i <= 1'b0; - - wr_en_i <= 1'b0; - wr_done_i <= 1'b0; - wr_addr_i <= 8'h00; - wr_data_i <= 8'h00; - wr_byte_en_i <= 4'b0000; - - // Unit: 10 ns (2 clk) - t0h_cnt_i <= 8'h01; - t0s_cnt_i <= 8'h80; - t1h_cnt_i <= 8'h7f; - t1s_cnt_i <= 8'h80; - - #2 rst_n_i <= 1'b1; -end - -always begin - #2.5 clk_i <= ~clk_i; -end - -always begin - #11 wr_addr_i <= 8'h00; - wr_data_i <= 8'h01; - wr_byte_en_i <= 4'b1000; - wr_en_i <= 1'b1; - #5 wr_en_i <= 1'b0; - - #10 wr_data_i <= 8'h00; - wr_byte_en_i <= 4'b0111; - wr_en_i <= 1'b1; - #5 wr_en_i <= 1'b0; - - #10 wr_addr_i <= 8'h01; - wr_data_i <= 8'h00; - wr_byte_en_i <= 4'b1000; - wr_en_i <= 1'b1; - #5 wr_en_i <= 1'b0; - - #10 wr_data_i <= 8'hff; - wr_byte_en_i <= 4'b0111; - wr_en_i <= 1'b1; - #5 wr_en_i <= 1'b0; - - #10 wr_done_i <= 1'b1; - #5 wr_done_i <= 1'b0; - - for (integer i=0; i<65536; i++) begin - #5 wr_done_i <= 1'b1; - #5 wr_done_i <= 1'b0; - end - - #75 rst_n_i <= 1'b0; - #25 $stop; -end - -endmodule diff --git a/sim/test_layer_conf.sv b/sim/test_layer_conf.sv deleted file mode 100644 index 9301153..0000000 --- a/sim/test_layer_conf.sv +++ /dev/null @@ -1,82 +0,0 @@ -/* - * test_layer_conf.sv - * - * Created on: 2020-07-08 18:23 - * Author: Jack Chen - */ - -`timescale 1ns / 1ps - -module test_layer_conf; - -logic clk_i; -logic rst_n_i; - -logic wr_en_i; -logic [5:0] wr_addr_i; -logic [7:0] wr_data_i; - -logic [7:0] t0h_cnt_o; -logic [7:0] t0s_cnt_o; -logic [7:0] t1h_cnt_o; -logic [7:0] t1s_cnt_o; - -layer_conf test_layer_conf( - .clk_i(clk_i), - .rst_n_i(rst_n_i), - - .wr_en_i(wr_en_i), - .wr_addr_i(wr_addr_i), - .wr_data_i(wr_data_i), - - .t0h_cnt_o(t0h_cnt_o), - .t0s_cnt_o(t0s_cnt_o), - .t1h_cnt_o(t1h_cnt_o), - .t1s_cnt_o(t1s_cnt_o) -); - -initial begin - clk_i <= 1'b1; - rst_n_i <= 1'b0; - - wr_en_i <= 1'b0; - wr_addr_i <= 6'h00; - wr_data_i <= 8'h00; - - #2 rst_n_i <= 1'b1; -end - -always begin - #2.5 clk_i <= ~clk_i; -end - -always begin - // T0H - #6 wr_addr_i <= 6'h00; - wr_data_i <= 8'h01; - wr_en_i <= 1'b1; - #5 wr_en_i <= 1'b0; - - // T0L - #10 wr_addr_i <= 6'h01; - wr_data_i <= 8'h12; - wr_en_i <= 1'b1; - #5 wr_en_i <= 1'b0; - - // T1H - #10 wr_addr_i <= 6'h02; - wr_data_i <= 8'h23; - wr_en_i <= 1'b1; - #5 wr_en_i <= 1'b0; - - // T1L - #10 wr_addr_i <= 6'h03; - wr_data_i <= 8'h34; - wr_en_i <= 1'b1; - #5 wr_en_i <= 1'b0; - - #75 rst_n_i <= 1'b0; - #25 $stop; -end - -endmodule diff --git a/sim/test_layer_ctrl.sv b/sim/test_layer_ctrl.sv deleted file mode 100644 index b30eda2..0000000 --- a/sim/test_layer_ctrl.sv +++ /dev/null @@ -1,119 +0,0 @@ -/* - * test_layer_ctrl.sv - * - * Created on: 2020-07-08 18:52 - * Author: Jack Chen - */ - -`timescale 1ns / 1ps - -module test_layer_ctrl; - -logic clk_i; -logic rst_n_i; - -logic dc_i; - -logic byte_vld_i; -logic [7:0] byte_data_i; - -logic [8:0] wr_en_o; -logic wr_done_o; -logic [5:0] wr_addr_o; -logic [3:0] wr_byte_en_o; - -layer_ctrl test_layer_ctrl( - .clk_i(clk_i), - .rst_n_i(rst_n_i), - - .dc_i(dc_i), - - .byte_vld_i(byte_vld_i), - .byte_data_i(byte_data_i), - - .wr_en_o(wr_en_o), - .wr_done_o(wr_done_o), - .wr_addr_o(wr_addr_o), - .wr_byte_en_o(wr_byte_en_o) -); - -initial begin - clk_i <= 1'b1; - rst_n_i <= 1'b0; - - dc_i <= 1'b0; - - byte_vld_i <= 1'b0; - byte_data_i <= 8'h00; - - #2 rst_n_i <= 1'b1; -end - -always begin - #2.5 clk_i <= ~clk_i; -end - -always begin - // CONF_WR - #6 dc_i <= 1'b0; - byte_vld_i <= 1'b1; - byte_data_i <= 8'h2a; - #5 byte_vld_i <= 1'b0; - - // CONF DATA 0: T0H - #5 dc_i <= 1'b1; - byte_vld_i <= 1'b1; - byte_data_i <= 8'h01; - #5 byte_vld_i <= 1'b0; - - // CONF DATA 1: T0L - #5 dc_i <= 1'b1; - byte_vld_i <= 1'b1; - byte_data_i <= 8'h12; - #5 byte_vld_i <= 1'b0; - - // CONF DATA 2: T1H - #5 dc_i <= 1'b1; - byte_vld_i <= 1'b1; - byte_data_i <= 8'h23; - #5 byte_vld_i <= 1'b0; - - // CONF DATA 3: T1L - #5 dc_i <= 1'b1; - byte_vld_i <= 1'b1; - byte_data_i <= 8'h34; - #5 byte_vld_i <= 1'b0; - - // ADDR_WR - #5 dc_i <= 1'b0; - byte_vld_i <= 1'b1; - byte_data_i <= 8'h2b; - #5 byte_vld_i <= 1'b0; - - // ADDR DATA - for (integer i=0; i<64; i++) begin - #5 dc_i <= 1'b1; - byte_vld_i <= 1'b1; - byte_data_i <= i; - #5 byte_vld_i <= 1'b0; - end - - // DATA_WR - #5 dc_i <= 1'b0; - byte_vld_i <= 1'b1; - byte_data_i <= 8'h2c; - #5 byte_vld_i <= 1'b0; - - // COLOR DATA - for (integer i=0; i<1536; i++) begin - #5 dc_i <= 1'b1; - byte_vld_i <= 1'b1; - byte_data_i <= i % 8'hff; - #5 byte_vld_i <= 1'b0; - end - - #75 rst_n_i <= 1'b0; - #25 $stop; -end - -endmodule diff --git a/sim/test_regfile.sv b/sim/test_regfile.sv new file mode 100644 index 0000000..01f3b31 --- /dev/null +++ b/sim/test_regfile.sv @@ -0,0 +1,100 @@ +/* + * test_regfile.sv + * + * Created on: 2020-07-08 18:23 + * Author: Jack Chen + */ + +`timescale 1ns / 1ps + +module test_regfile; + +logic clk_i; +logic rst_n_i; + +logic reg_wr_en_i; +logic [2:0] reg_wr_addr_i; +logic [7:0] reg_wr_data_i; + +logic [7:0] reg_t0h_time_o; +logic [7:0] reg_t0l_time_o; +logic [7:0] reg_t1h_time_o; +logic [7:0] reg_t1l_time_o; + +logic [7:0] reg_chan_len_o; +logic [3:0] reg_chan_cnt_o; + +regfile test_regfile( + .clk_i(clk_i), + .rst_n_i(rst_n_i), + + .reg_wr_en_i(reg_wr_en_i), + .reg_wr_addr_i(reg_wr_addr_i), + .reg_wr_data_i(reg_wr_data_i), + + .reg_t0h_time_o(reg_t0h_time_o), + .reg_t0l_time_o(reg_t0l_time_o), + .reg_t1h_time_o(reg_t1h_time_o), + .reg_t1l_time_o(reg_t1l_time_o), + + .reg_chan_len_o(reg_chan_len_o), + .reg_chan_cnt_o(reg_chan_cnt_o) +); + +initial begin + clk_i <= 1'b1; + rst_n_i <= 1'b0; + + reg_wr_en_i <= 1'b0; + reg_wr_addr_i <= 3'h0; + reg_wr_data_i <= 8'h00; + + #2 rst_n_i <= 1'b1; +end + +always begin + #2.5 clk_i <= ~clk_i; +end + +always begin + // T0H time (10 ns) + #6 reg_wr_addr_i <= 3'h0; + reg_wr_data_i <= 8'h01; + reg_wr_en_i <= 1'b1; + #5 reg_wr_en_i <= 1'b0; + + // T0L time (10 ns) + #10 reg_wr_addr_i <= 3'h1; + reg_wr_data_i <= 8'h12; + reg_wr_en_i <= 1'b1; + #5 reg_wr_en_i <= 1'b0; + + // T1H time (10 ns) + #10 reg_wr_addr_i <= 3'h2; + reg_wr_data_i <= 8'h23; + reg_wr_en_i <= 1'b1; + #5 reg_wr_en_i <= 1'b0; + + // T1L time (10 ns) + #10 reg_wr_addr_i <= 3'h3; + reg_wr_data_i <= 8'h34; + reg_wr_en_i <= 1'b1; + #5 reg_wr_en_i <= 1'b0; + + // channel length + #10 reg_wr_addr_i <= 3'h4; + reg_wr_data_i <= 8'h3f; + reg_wr_en_i <= 1'b1; + #5 reg_wr_en_i <= 1'b0; + + // channel count + #10 reg_wr_addr_i <= 3'h5; + reg_wr_data_i <= 8'h07; + reg_wr_en_i <= 1'b1; + #5 reg_wr_en_i <= 1'b0; + + #75 rst_n_i <= 1'b0; + #25 $stop; +end + +endmodule diff --git a/sim/test_rst_sync.sv b/sim/test_rst_syn.sv similarity index 87% rename from sim/test_rst_sync.sv rename to sim/test_rst_syn.sv index 8f58862..87bd9be 100644 --- a/sim/test_rst_sync.sv +++ b/sim/test_rst_syn.sv @@ -1,5 +1,5 @@ /* - * test_rst_sync.sv + * test_rst_syn.sv * * Created on: 2020-07-08 18:12 * Author: Jack Chen @@ -7,14 +7,14 @@ `timescale 1ns / 1ps -module test_rst_sync; +module test_rst_syn; logic clk_i; logic rst_n_i; logic rst_n_o; -rst_sync test_rst_sync( +rst_syn test_rst_syn( .clk_i(clk_i), .rst_n_i(rst_n_i), diff --git a/sim/test_spi_slave.sv b/sim/test_spi_slave.sv index 7bac261..77d595d 100644 --- a/sim/test_spi_slave.sv +++ b/sim/test_spi_slave.sv @@ -12,12 +12,14 @@ module test_spi_slave; logic clk_i; logic rst_n_i; -logic spi_sclk_i; -logic spi_mosi_i; -logic spi_cs_n_i; +logic spi_sclk_i; +logic spi_mosi_i; +logic spi_cs_n_i; +logic [7:0] spi_byte_data_i; -logic byte_vld_o; -logic [7:0] byte_data_o; +logic spi_miso_o; +logic spi_byte_vld_o; +logic [7:0] spi_byte_data_o; spi_slave test_spi_slave( .clk_i(clk_i), @@ -26,20 +28,23 @@ spi_slave test_spi_slave( .spi_sclk_i(spi_sclk_i), .spi_mosi_i(spi_mosi_i), .spi_cs_n_i(spi_cs_n_i), + .spi_byte_data_i(spi_byte_data_i), - .byte_vld_o(byte_vld_o), - .byte_data_o(byte_data_o) + .spi_miso_o(spi_miso_o), + .spi_byte_vld_o(spi_byte_vld_o), + .spi_byte_data_o(spi_byte_data_o) ); initial begin clk_i <= 1'b1; rst_n_i <= 1'b0; - // SPI Mode: CPOL=0, CPHA=0, MSB First spi_cs_n_i <= 1'b1; spi_sclk_i <= 1'b0; spi_mosi_i <= 1'b0; + spi_byte_data_i <= 8'h7e; + #2 rst_n_i <= 1'b1; end @@ -47,6 +52,10 @@ always begin #2.5 clk_i <= ~clk_i; end +always @(negedge clk_i) begin + spi_byte_data_i <= spi_byte_data_i + spi_byte_vld_o; +end + always begin #50 spi_cs_n_i <= 1'b0; @@ -116,6 +125,12 @@ always begin spi_mosi_i <= 1'b1; // BIT0 #12 spi_sclk_i <= 1'b1; + for (integer i = 0; i < 24; i++) begin + #12 spi_sclk_i <= 1'b0; + spi_mosi_i <= 1'b0; + #12 spi_sclk_i <= 1'b1; + end + #12 spi_sclk_i <= 1'b0; #25 spi_cs_n_i <= 1'b1; diff --git a/sim/test_ws281x_ctrl.sv b/sim/test_waveform_ctl.sv similarity index 54% rename from sim/test_ws281x_ctrl.sv rename to sim/test_waveform_ctl.sv index 81cdc97..ffbc83f 100644 --- a/sim/test_ws281x_ctrl.sv +++ b/sim/test_waveform_ctl.sv @@ -1,5 +1,5 @@ /* - * test_ws281x_ctrl.sv + * test_waveform_ctl.sv * * Created on: 2020-07-08 20:23 * Author: Jack Chen @@ -7,38 +7,36 @@ `timescale 1ns / 1ps -module test_ws281x_ctrl; +module test_waveform_ctl; logic clk_i; logic rst_n_i; logic bit_rdy_i; -logic wr_done_i; -logic [31:0] rd_data_i; -logic [ 7:0] tim_cnt_i; +logic ram_wr_done_i; +logic [31:0] ram_rd_data_i; logic bit_vld_o; logic bit_data_o; -logic rd_en_o; -logic [5:0] rd_addr_o; +logic ram_rd_en_o; +logic [7:0] ram_rd_addr_o; -ws281x_ctrl test_ws281x_ctrl( +waveform_ctl test_waveform_ctl( .clk_i(clk_i), .rst_n_i(rst_n_i), .bit_rdy_i(bit_rdy_i), - .wr_done_i(wr_done_i), - .rd_data_i(rd_data_i), - .tim_cnt_i(tim_cnt_i), + .ram_wr_done_i(ram_wr_done_i), + .ram_rd_data_i(ram_rd_data_i), .bit_vld_o(bit_vld_o), .bit_data_o(bit_data_o), - .rd_en_o(rd_en_o), - .rd_addr_o(rd_addr_o) + .ram_rd_en_o(ram_rd_en_o), + .ram_rd_addr_o(ram_rd_addr_o) ); initial begin @@ -47,9 +45,8 @@ initial begin bit_rdy_i <= 1'b0; - wr_done_i <= 1'b0; - rd_data_i <= 32'haaaa_cccc; - tim_cnt_i <= 8'h04; + ram_wr_done_i <= 1'b0; + ram_rd_data_i <= 32'haaaa_cccc; #2 rst_n_i <= 1'b1; end @@ -59,17 +56,17 @@ always begin end always begin - #11 wr_done_i <= 1'b1; - #5 wr_done_i <= 1'b0; + #11 ram_wr_done_i <= 1'b1; + #5 ram_wr_done_i <= 1'b0; - for (integer i=0; i<119; i++) begin + for (integer i = 0; i < 119; i++) begin #50 bit_rdy_i <= 1'b1; #5 bit_rdy_i <= 1'b0; end - #500 rd_data_i <= 32'h00aa_dddd; + #500 ram_rd_data_i <= 32'h00aa_dddd; - for (integer i=0; i<119; i++) begin + for (integer i = 0; i < 119; i++) begin #50 bit_rdy_i <= 1'b1; #5 bit_rdy_i <= 1'b0; end diff --git a/sim/test_ws281x_code.sv b/sim/test_waveform_gen.sv similarity index 61% rename from sim/test_ws281x_code.sv rename to sim/test_waveform_gen.sv index 4db523e..e910780 100644 --- a/sim/test_ws281x_code.sv +++ b/sim/test_waveform_gen.sv @@ -1,5 +1,5 @@ /* - * test_ws281x_code.sv + * test_waveform_gen.sv * * Created on: 2020-07-08 20:03 * Author: Jack Chen @@ -7,7 +7,7 @@ `timescale 1ns / 1ps -module test_ws281x_code; +module test_waveform_gen; logic clk_i; logic rst_n_i; @@ -15,23 +15,25 @@ logic rst_n_i; logic bit_vld_i; logic bit_data_i; -logic [7:0] t0h_cnt_i; -logic [7:0] t1h_cnt_i; -logic [7:0] tim_cnt_i; +logic [7:0] reg_t0h_time_i; +logic [7:0] reg_t0l_time_i; +logic [7:0] reg_t1h_time_i; +logic [7:0] reg_t1l_time_i; logic bit_rdy_o; logic bit_code_o; -ws281x_code test_ws281x_code( +waveform_gen test_waveform_gen( .clk_i(clk_i), .rst_n_i(rst_n_i), .bit_vld_i(bit_vld_i), .bit_data_i(bit_data_i), - .t0h_cnt_i(t0h_cnt_i), - .t1h_cnt_i(t1h_cnt_i), - .tim_cnt_i(tim_cnt_i), + .reg_t0h_time_i(reg_t0h_time_i), + .reg_t0l_time_i(reg_t0l_time_i), + .reg_t1h_time_i(reg_t1h_time_i), + .reg_t1l_time_i(reg_t1l_time_i), .bit_rdy_o(bit_rdy_o), .bit_code_o(bit_code_o) @@ -44,10 +46,10 @@ initial begin bit_vld_i <= 1'b0; bit_data_i <= 1'b0; - // Unit: 10 ns (2 clk) - t0h_cnt_i <= 8'h01; - t1h_cnt_i <= 8'h02; - tim_cnt_i <= 8'h03; + reg_t0h_time_i <= 8'h00; + reg_t0l_time_i <= 8'h01; + reg_t1h_time_i <= 8'h01; + reg_t1l_time_i <= 8'h00; #2 rst_n_i <= 1'b1; end @@ -61,7 +63,7 @@ always begin bit_data_i <= 1'b0; #5 bit_vld_i <= 1'b0; - for (integer i=0; i<10; i++) begin + for (integer i = 0; i < 10; i++) begin #25 bit_vld_i <= 1'b1; bit_data_i <= i % 2; #5 bit_vld_i <= 1'b0; diff --git a/sim/test_ws281x_conf.sv b/sim/test_ws281x_conf.sv deleted file mode 100644 index c78d3dd..0000000 --- a/sim/test_ws281x_conf.sv +++ /dev/null @@ -1,73 +0,0 @@ -/* - * test_ws281x_conf.sv - * - * Created on: 2020-07-10 14:31 - * Author: Jack Chen - */ - -`timescale 1ns / 1ps - -module test_ws281x_conf; - -logic clk_i; -logic rst_n_i; - -logic bit_vld_i; -logic bit_data_i; - -logic [7:0] t0h_cnt_i; -logic [7:0] t0s_cnt_i; -logic [7:0] t1h_cnt_i; -logic [7:0] t1s_cnt_i; - -logic [7:0] tim_cnt_o; - -ws281x_conf test_ws281x_conf( - .clk_i(clk_i), - .rst_n_i(rst_n_i), - - .bit_vld_i(bit_vld_i), - .bit_data_i(bit_data_i), - - .t0h_cnt_i(t0h_cnt_i), - .t0s_cnt_i(t0s_cnt_i), - .t1h_cnt_i(t1h_cnt_i), - .t1s_cnt_i(t1s_cnt_i), - - .tim_cnt_o(tim_cnt_o) -); - -initial begin - clk_i <= 1'b1; - rst_n_i <= 1'b0; - - bit_vld_i <= 1'b0; - bit_data_i <= 1'b0; - - // Unit: 10 ns (2 clk) - t0h_cnt_i <= 8'h01; - t0s_cnt_i <= 8'h80; - t1h_cnt_i <= 8'hfe; - t1s_cnt_i <= 8'hff; - - #2 rst_n_i <= 1'b1; -end - -always begin - #2.5 clk_i <= ~clk_i; -end - -always begin - #11 bit_vld_i <= 1'b1; - #5 bit_vld_i <= 1'b0; - - #10 bit_data_i <= 1'b1; - - #10 bit_vld_i <= 1'b1; - #5 bit_vld_i <= 1'b0; - - #75 rst_n_i <= 1'b0; - #25 $stop; -end - -endmodule