misc: minor update

README.md

@@ -120,7 +120,7 @@ git pull
 
 ## Building
 
-* Quartus Prime 20.1.0 Lite Edition
+* Quartus Prime 21.1.0 Lite Edition
 
 ## Music Light Cube
 

ip/pll/pll.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "20.1"
+set_global_assignment -name IP_TOOL_VERSION "21.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]

ip/pll/pll.v

@@ -9,16 +9,16 @@
 // 			altpll
 //
 // Simulation Library Files(s):
-// 			altera_mf
+// 			
 // ============================================================
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 20.1.0 Build 711 06/05/2020 SJ Lite Edition
+// 21.1.0 Build 842 10/21/2021 SJ Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 2020  Intel Corporation. All rights reserved.
+//Copyright (C) 2021  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
 //and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 
@@ -321,5 +321,4 @@ endmodule
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
-// Retrieval info: LIB_FILE: altera_mf
 // Retrieval info: CBX_MODULE_PREFIX: ON

ip/ram/ram256.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
-set_global_assignment -name IP_TOOL_VERSION "20.1"
+set_global_assignment -name IP_TOOL_VERSION "21.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram256.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram256_syn.v"]

ip/ram/ram256.v

@@ -14,11 +14,11 @@
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 20.1.0 Build 711 06/05/2020 SJ Lite Edition
+// 21.1.0 Build 842 10/21/2021 SJ Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 2020  Intel Corporation. All rights reserved.
+//Copyright (C) 2021  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
 //and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 

ip/ram/ram256_syn.v

@@ -14,11 +14,11 @@
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 20.1.0 Build 711 06/05/2020 SJ Lite Edition
+// 21.1.0 Build 842 10/21/2021 SJ Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 2020  Intel Corporation. All rights reserved.
+//Copyright (C) 2021  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
 //and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 
@@ -35,7 +35,7 @@
 
 
 //altsyncram ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" BYTE_SIZE=8 CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_B="BYPASS" DEVICE_FAMILY="MAX 10" NUMWORDS_A=256 NUMWORDS_B=256 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" POWER_UP_UNINITIALIZED="TRUE" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=32 WIDTH_B=32 WIDTH_BYTEENA_A=4 WIDTHAD_A=8 WIDTHAD_B=8 address_a address_b byteena_a clock0 data_a q_b wren_a
-//VERSION_BEGIN 20.1 cbx_altera_syncram_nd_impl 2020:06:05:12:04:24:SJ cbx_altsyncram 2020:06:05:12:04:24:SJ cbx_cycloneii 2020:06:05:12:04:24:SJ cbx_lpm_add_sub 2020:06:05:12:04:24:SJ cbx_lpm_compare 2020:06:05:12:04:24:SJ cbx_lpm_decode 2020:06:05:12:04:24:SJ cbx_lpm_mux 2020:06:05:12:04:24:SJ cbx_mgl 2020:06:05:13:25:21:SJ cbx_nadder 2020:06:05:12:04:24:SJ cbx_stratix 2020:06:05:12:04:24:SJ cbx_stratixii 2020:06:05:12:04:24:SJ cbx_stratixiii 2020:06:05:12:04:24:SJ cbx_stratixv 2020:06:05:12:04:24:SJ cbx_util_mgl 2020:06:05:12:04:24:SJ  VERSION_END
+//VERSION_BEGIN 21.1 cbx_altera_syncram_nd_impl 2021:10:21:11:02:24:SJ cbx_altsyncram 2021:10:21:11:02:24:SJ cbx_cycloneii 2021:10:21:11:02:24:SJ cbx_lpm_add_sub 2021:10:21:11:02:24:SJ cbx_lpm_compare 2021:10:21:11:02:24:SJ cbx_lpm_decode 2021:10:21:11:02:24:SJ cbx_lpm_mux 2021:10:21:11:02:24:SJ cbx_mgl 2021:10:21:11:11:47:SJ cbx_nadder 2021:10:21:11:02:24:SJ cbx_stratix 2021:10:21:11:02:24:SJ cbx_stratixii 2021:10:21:11:02:24:SJ cbx_stratixiii 2021:10:21:11:02:24:SJ cbx_stratixv 2021:10:21:11:02:24:SJ cbx_util_mgl 2021:10:21:11:02:24:SJ  VERSION_END
 // synthesis VERILOG_INPUT_VERSION VERILOG_2001
 // altera message_off 10463
 

neopixel_led_controller.qsf

@@ -1,6 +1,6 @@
 # -------------------------------------------------------------------------- #
 #
-# Copyright (C) 2020  Intel Corporation. All rights reserved.
+# Copyright (C) 2021  Intel Corporation. All rights reserved.
 # Your use of Intel Corporation's design tools, logic functions 
 # and other software and tools, and any partner logic 
 # functions, and any output files from any of the foregoing 
@@ -18,8 +18,8 @@
 # -------------------------------------------------------------------------- #
 #
 # Quartus Prime
-# Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
-# Date created = 18:52:25  July 18, 2020
+# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
+# Date created = 10:33:17  December 02, 2021
 #
 # -------------------------------------------------------------------------- #
 #
@@ -30,7 +30,7 @@
 #    If this file doesn't exist, see file:
 #		assignment_defaults.qdf
 #
-# 2) Altera recommends that you do not modify this file. This
+# 2) Intel recommends that you do not modify this file. This
 #    file is updated automatically by the Quartus Prime software
 #    and any changes you make may be lost or overwritten.
 #
@@ -42,7 +42,7 @@
 # ========================
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:11:22  MARCH 25, 2018"
-set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/top.sv
@@ -146,7 +146,7 @@ set_global_assignment -name AUTO_GLOBAL_CLOCK ON
 
 # EDA Netlist Writer Assignments
 # ==============================
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
+set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (SystemVerilog)"
 
 # Power Estimation Assignments
 # ============================

rtl/regfile.sv

@@ -31,23 +31,23 @@ module regfile(
 logic [7:0] regs[5:0];
 logic [7:0] data[7:0];
 
-genvar i;
-generate
-    assign data[0] = 8'h00;
-    assign data[1] = {RTL_REVISION_MAJOR, RTL_REVISION_MINOR};
+assign data[0] = 8'h00;
+assign data[1] = {RTL_REVISION_MAJOR, RTL_REVISION_MINOR};
 
+generate
+    genvar i;
     for (i = 0; i < 6; i++) begin: rd_data
         assign data[i + 2] = regs[i];
     end
+endgenerate
 
-    assign reg_t0h_time_o = regs[0];
-    assign reg_t0s_time_o = regs[0] + regs[1];
-    assign reg_t1h_time_o = regs[2];
-    assign reg_t1s_time_o = regs[2] + regs[3];
+assign reg_t0h_time_o = regs[0];
+assign reg_t0s_time_o = regs[0] + regs[1];
+assign reg_t1h_time_o = regs[2];
+assign reg_t1s_time_o = regs[2] + regs[3];
 
-    assign reg_chan_len_o = regs[4];
-    assign reg_chan_cnt_o = regs[5];
-endgenerate
+assign reg_chan_len_o = regs[4];
+assign reg_chan_cnt_o = regs[5];
 
 assign reg_rd_data_o = data[reg_rd_addr_i];
 

rtl/top.sv

@@ -95,8 +95,8 @@ channel_ctl channel_ctl(
     .ram_wr_byte_en_o(ram_wr_byte_en)
 );
 
-genvar i;
 generate
+    genvar i;
     for (i = 0; i < 16; i++) begin: channel
         channel_out out(
             .clk_i(sys_clk),