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handlin seq_statement #123

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redguardtoo opened this issue Jul 27, 2020 · 1 comment
Open

handlin seq_statement #123

redguardtoo opened this issue Jul 27, 2020 · 1 comment

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@redguardtoo
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See #74 , it's not verilog only problem, any C like language has same issue.
Verilog's begin and end is like { and } in C:
@redguardtoo redguardtoo changed the title handling of seq_statement handlin seq_statement Jul 27, 2020
@redguardtoo
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it's done. using some code copied from semantic.

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@redguardtoo