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target/riscv: stop using register_get/set for 0.11 targets Check Code Style (checkpatch) #931: Pull request #1044 synchronize by en-sc
May 15, 2024 17:06 27s en-sc:en-sc/riscv-011-sep-reg-acc
en-sc:en-sc/riscv-011-sep-reg-acc
May 15, 2024 17:06 27s
target/riscv: stop using register_get/set for 0.11 targets Check Code Style (checkpatch) #930: Pull request #1044 synchronize by en-sc
May 15, 2024 17:05 32s en-sc:en-sc/riscv-011-sep-reg-acc
en-sc:en-sc/riscv-011-sep-reg-acc
May 15, 2024 17:05 32s
target/riscv: only dmactive can be written if dmactive is low Check Code Style (checkpatch) #929: Pull request #1061 synchronize by en-sc
May 15, 2024 15:59 38s en-sc:en-sc/dm-reset
en-sc:en-sc/dm-reset
May 15, 2024 15:59 38s
target/riscv: fix halt reason for targets that do not support hit bit on triggers Check Code Style (checkpatch) #928: Pull request #1056 synchronize by aap-sc
May 10, 2024 08:26 27s aap-sc:aap-sc/no_hit_bit_status
aap-sc:aap-sc/no_hit_bit_status
May 10, 2024 08:26 27s
target/riscv: fix halt reason for targets that do not support hit bit on triggers Check Code Style (checkpatch) #927: Pull request #1056 synchronize by aap-sc
May 10, 2024 08:25 41s aap-sc:aap-sc/no_hit_bit_status
aap-sc:aap-sc/no_hit_bit_status
May 10, 2024 08:25 41s
target/riscv: stop using register_get/set for 0.11 targets Check Code Style (checkpatch) #926: Pull request #1044 synchronize by en-sc
May 8, 2024 15:48 26s en-sc:en-sc/riscv-011-sep-reg-acc
en-sc:en-sc/riscv-011-sep-reg-acc
May 8, 2024 15:48 26s
target/riscv: stop using register_get/set for 0.11 targets Check Code Style (checkpatch) #925: Pull request #1044 synchronize by en-sc
May 8, 2024 13:49 31s en-sc:en-sc/riscv-011-sep-reg-acc
en-sc:en-sc/riscv-011-sep-reg-acc
May 8, 2024 13:49 31s
target/riscv: only dmactive can be written if dmactive is low Check Code Style (checkpatch) #924: Pull request #1061 synchronize by en-sc
May 3, 2024 15:52 27s en-sc:en-sc/dm-reset
en-sc:en-sc/dm-reset
May 3, 2024 15:52 27s
target/riscv: read abstract args using batch Check Code Style (checkpatch) #923: Pull request #1033 synchronize by en-sc
May 2, 2024 07:57 26s en-sc:en-sc/err-read-abs-arg
en-sc:en-sc/err-read-abs-arg
May 2, 2024 07:57 26s
Add functions to decode RVC load and store instructions for watchpoints Check Code Style (checkpatch) #922: Pull request #1029 synchronize by MrAlexei
April 30, 2024 07:51 27s MrAlexei:add_decode_wp_rvc
MrAlexei:add_decode_wp_rvc
April 30, 2024 07:51 27s
target/riscv: read abstract args using batch Check Code Style (checkpatch) #919: Pull request #1033 synchronize by en-sc
April 27, 2024 13:40 25s en-sc:en-sc/err-read-abs-arg
en-sc:en-sc/err-read-abs-arg
April 27, 2024 13:40 25s
target/riscv: read abstract args using batch Check Code Style (checkpatch) #918: Pull request #1033 synchronize by en-sc
April 27, 2024 13:39 27s en-sc:en-sc/err-read-abs-arg
en-sc:en-sc/err-read-abs-arg
April 27, 2024 13:39 27s
target/riscv: read abstract args using batch Check Code Style (checkpatch) #917: Pull request #1033 synchronize by en-sc
April 27, 2024 13:32 27s en-sc:en-sc/err-read-abs-arg
en-sc:en-sc/err-read-abs-arg
April 27, 2024 13:32 27s
Merge up to 04154af5d6cd5fe76a2583778379bdacb5aa6fb0 from upstream Check Code Style (checkpatch) #916: Pull request #1064 opened by en-sc
April 27, 2024 12:22 26s en-sc:en-sc/from_upstream
en-sc:en-sc/from_upstream
April 27, 2024 12:22 26s
target/riscv: read abstract args using batch Check Code Style (checkpatch) #915: Pull request #1033 synchronize by en-sc
April 27, 2024 12:17 38s en-sc:en-sc/err-read-abs-arg
en-sc:en-sc/err-read-abs-arg
April 27, 2024 12:17 38s
target/riscv: reset delays during batch scans Check Code Style (checkpatch) #914: Pull request #1028 synchronize by en-sc
April 26, 2024 18:27 31s en-sc:en-sc/busy-reset-batch
en-sc:en-sc/busy-reset-batch
April 26, 2024 18:27 31s
target/riscv: stop using register_get/set for 0.11 targets Check Code Style (checkpatch) #913: Pull request #1044 synchronize by en-sc
April 26, 2024 17:51 28s en-sc:en-sc/riscv-011-sep-reg-acc
en-sc:en-sc/riscv-011-sep-reg-acc
April 26, 2024 17:51 28s
target/riscv: only dmactive can be written if dmactive is low Check Code Style (checkpatch) #912: Pull request #1061 synchronize by en-sc
April 26, 2024 15:46 27s en-sc:en-sc/dm-reset
en-sc:en-sc/dm-reset
April 26, 2024 15:46 27s
target/riscv: only dmactive can be written if dmactive is low Check Code Style (checkpatch) #911: Pull request #1061 opened by en-sc
April 26, 2024 15:43 26s en-sc:en-sc/dm-reset
en-sc:en-sc/dm-reset
April 26, 2024 15:43 26s
fix confusing status messages during resume Check Code Style (checkpatch) #910: Pull request #1031 synchronize by aap-sc
April 23, 2024 23:35 41s aap-sc:aap-sc/hart_status_info_fixup
aap-sc:aap-sc/hart_status_info_fixup
April 23, 2024 23:35 41s
target/riscv: fix halt reason for targets that do not support hit bit on triggers Check Code Style (checkpatch) #909: Pull request #1056 opened by aap-sc
April 23, 2024 23:18 45s aap-sc:aap-sc/no_hit_bit_status
aap-sc:aap-sc/no_hit_bit_status
April 23, 2024 23:18 45s
target/riscv: use breakpoint_hw_set/watchpoint_set to properly initialize bp/wp descriptor Check Code Style (checkpatch) #908: Pull request #1055 opened by aap-sc
April 23, 2024 23:09 1m 28s aap-sc:aap-sc/bp_unitialized
aap-sc:aap-sc/bp_unitialized
April 23, 2024 23:09 1m 28s
target/riscv: stop using register_get/set for 0.11 targets Check Code Style (checkpatch) #907: Pull request #1044 synchronize by en-sc
April 23, 2024 18:29 25s en-sc:en-sc/riscv-011-sep-reg-acc
en-sc:en-sc/riscv-011-sep-reg-acc
April 23, 2024 18:29 25s
target/riscv: reset delays during batch scans Check Code Style (checkpatch) #906: Pull request #1028 synchronize by en-sc
April 23, 2024 17:57 28s en-sc:en-sc/busy-reset-batch
en-sc:en-sc/busy-reset-batch
April 23, 2024 17:57 28s
target/riscv/riscv-011: pc and dpc should be cached at the same location Check Code Style (checkpatch) #905: Pull request #1054 synchronize by en-sc
April 23, 2024 13:45 30s en-sc:en-sc/rv011-pc-dpc
en-sc:en-sc/rv011-pc-dpc
April 23, 2024 13:45 30s