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target/riscv: fix semantic checker warnings
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Besides checkpatch, now upstream codes are scanning with
Sparse semantic checker tool.
This commit addresses some Sparse and checkpatch warnings.

Change-Id: I0e3e9f15220d8829c5708897af27aa86a8f90c07
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
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@erhankur
erhankur committed Jul 18, 2023
1 parent bb2c63c commit 1618d03
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Showing 5 changed files with 60 additions and 60 deletions.
2 changes: 1 addition & 1 deletion src/jtag/drivers/libjaylink
Submodule libjaylink updated from 9aa7a5 to 0d2392
4 changes: 2 additions & 2 deletions src/target/riscv/batch.c
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Original file line number Diff line number Diff line change
Expand Up @@ -127,7 +127,7 @@ int riscv_batch_run(struct riscv_batch *batch)
return ERROR_OK;
}

void riscv_batch_add_dmi_write(struct riscv_batch *batch, unsigned address, uint64_t data,
void riscv_batch_add_dmi_write(struct riscv_batch *batch, unsigned int address, uint64_t data,
bool read_back)
{
assert(batch->used_scans < batch->allocated_scans);
Expand Down Expand Up @@ -194,7 +194,7 @@ void riscv_batch_add_nop(struct riscv_batch *batch)
batch->used_scans++;
}

void dump_field(int idle, const struct scan_field *field)
static void dump_field(int idle, const struct scan_field *field)
{
static const char * const op_string[] = {"-", "r", "w", "?"};
static const char * const status_string[] = {"+", "?", "F", "b"};
Expand Down
2 changes: 1 addition & 1 deletion src/target/riscv/batch.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -59,7 +59,7 @@ bool riscv_batch_full(struct riscv_batch *batch);
int riscv_batch_run(struct riscv_batch *batch);

/* Adds a DMI write to this batch. */
void riscv_batch_add_dmi_write(struct riscv_batch *batch, unsigned address, uint64_t data,
void riscv_batch_add_dmi_write(struct riscv_batch *batch, unsigned int address, uint64_t data,
bool read_back);

/* DMI reads must be handled in two parts: the first one schedules a read and
Expand Down
62 changes: 31 additions & 31 deletions src/target/riscv/riscv-013.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -47,9 +47,9 @@ static int riscv013_step_current_hart(struct target *target);
static int riscv013_on_step(struct target *target);
static int riscv013_resume_prep(struct target *target);
static enum riscv_halt_reason riscv013_halt_reason(struct target *target);
static int riscv013_write_debug_buffer(struct target *target, unsigned index,
static int riscv013_write_debug_buffer(struct target *target, unsigned int index,
riscv_insn_t d);
static riscv_insn_t riscv013_read_debug_buffer(struct target *target, unsigned
static riscv_insn_t riscv013_read_debug_buffer(struct target *target, unsigned int
index);
static int riscv013_invalidate_cached_debug_buffer(struct target *target);
static int riscv013_execute_debug_buffer(struct target *target);
Expand Down Expand Up @@ -1005,7 +1005,7 @@ static uint32_t abstract_memory_size(unsigned width)
* Creates a memory access abstract command.
*/
static uint32_t access_memory_command(struct target *target, bool virtual,
unsigned width, bool postincrement, bool is_write)
unsigned int width, bool postincrement, bool is_write)
{
uint32_t command = set_field(0, AC_ACCESS_MEMORY_CMDTYPE, 2);
command = set_field(command, AC_ACCESS_MEMORY_AAMVIRTUAL, virtual);
Expand Down Expand Up @@ -1855,8 +1855,8 @@ static int examine(struct target *target)
if (!halted) {
r->prepped = true;
if (riscv013_halt_go(target) != ERROR_OK) {
LOG_TARGET_ERROR(target, "Fatal: Hart %d failed to halt during examine()",
info->index);
LOG_TARGET_ERROR(target, "Fatal: Hart %d failed to halt during %s",
info->index, __func__);
return ERROR_FAIL;
}
target->state = TARGET_HALTED;
Expand Down Expand Up @@ -4104,35 +4104,35 @@ static int write_memory_bus_v1(struct target *target, target_addr_t address,

uint32_t sbvalue[4] = { 0 };
if (size > 12) {
sbvalue[3] = ((uint32_t) p[12]) |
(((uint32_t) p[13]) << 8) |
(((uint32_t) p[14]) << 16) |
(((uint32_t) p[15]) << 24);
sbvalue[3] = ((uint32_t)p[12]) |
(((uint32_t)p[13]) << 8) |
(((uint32_t)p[14]) << 16) |
(((uint32_t)p[15]) << 24);
riscv_batch_add_dmi_write(batch, DM_SBDATA3, sbvalue[3], false);
}

if (size > 8) {
sbvalue[2] = ((uint32_t) p[8]) |
(((uint32_t) p[9]) << 8) |
(((uint32_t) p[10]) << 16) |
(((uint32_t) p[11]) << 24);
sbvalue[2] = ((uint32_t)p[8]) |
(((uint32_t)p[9]) << 8) |
(((uint32_t)p[10]) << 16) |
(((uint32_t)p[11]) << 24);
riscv_batch_add_dmi_write(batch, DM_SBDATA2, sbvalue[2], false);
}
if (size > 4) {
sbvalue[1] = ((uint32_t) p[4]) |
(((uint32_t) p[5]) << 8) |
(((uint32_t) p[6]) << 16) |
(((uint32_t) p[7]) << 24);
sbvalue[1] = ((uint32_t)p[4]) |
(((uint32_t)p[5]) << 8) |
(((uint32_t)p[6]) << 16) |
(((uint32_t)p[7]) << 24);
riscv_batch_add_dmi_write(batch, DM_SBDATA1, sbvalue[1], false);
}

sbvalue[0] = p[0];
if (size > 2) {
sbvalue[0] |= ((uint32_t) p[2]) << 16;
sbvalue[0] |= ((uint32_t) p[3]) << 24;
sbvalue[0] |= ((uint32_t)p[2]) << 16;
sbvalue[0] |= ((uint32_t)p[3]) << 24;
}
if (size > 1)
sbvalue[0] |= ((uint32_t) p[1]) << 8;
sbvalue[0] |= ((uint32_t)p[1]) << 8;

riscv_batch_add_dmi_write(batch, DM_SBDATA0, sbvalue[0], false);

Expand Down Expand Up @@ -4595,7 +4595,7 @@ static int select_prepped_harts(struct target *target)
struct target *t = entry->target;
struct riscv_info *info = riscv_info(t);
riscv013_info_t *info_013 = get_info(t);
unsigned index = info_013->index;
unsigned int index = info_013->index;
LOG_DEBUG("index=%d, coreid=%d, prepped=%d", index, t->coreid, info->prepped);
if (info->prepped) {
info_013->selected = true;
Expand Down Expand Up @@ -4779,11 +4779,11 @@ static enum riscv_halt_reason riscv013_halt_reason(struct target *target)
}

LOG_ERROR("Unknown DCSR cause field: 0x%" PRIx64, get_field(dcsr, CSR_DCSR_CAUSE));
LOG_ERROR(" dcsr=0x%" PRIx32, (uint32_t) dcsr);
LOG_ERROR(" dcsr=0x%" PRIx32, (uint32_t)dcsr);
return RISCV_HALT_UNKNOWN;
}

int riscv013_write_debug_buffer(struct target *target, unsigned index, riscv_insn_t data)
static int riscv013_write_debug_buffer(struct target *target, unsigned int index, riscv_insn_t data)
{
dm013_info_t *dm = get_dm(target);
if (!dm)
Expand All @@ -4798,14 +4798,14 @@ int riscv013_write_debug_buffer(struct target *target, unsigned index, riscv_ins
return ERROR_OK;
}

riscv_insn_t riscv013_read_debug_buffer(struct target *target, unsigned index)
static riscv_insn_t riscv013_read_debug_buffer(struct target *target, unsigned int index)
{
uint32_t value;
dmi_read(target, &value, DM_PROGBUF0 + index);
return value;
}

int riscv013_invalidate_cached_debug_buffer(struct target *target)
static int riscv013_invalidate_cached_debug_buffer(struct target *target)
{
dm013_info_t *dm = get_dm(target);
if (!dm) {
Expand All @@ -4819,7 +4819,7 @@ int riscv013_invalidate_cached_debug_buffer(struct target *target)
return ERROR_OK;
}

int riscv013_execute_debug_buffer(struct target *target)
static int riscv013_execute_debug_buffer(struct target *target)
{
uint32_t run_program = 0;
run_program = set_field(run_program, AC_ACCESS_REGISTER_AARSIZE, 2);
Expand All @@ -4830,31 +4830,31 @@ int riscv013_execute_debug_buffer(struct target *target)
return execute_abstract_command(target, run_program);
}

void riscv013_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d)
static void riscv013_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d)
{
RISCV013_INFO(info);
buf_set_u64((unsigned char *)buf, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, DMI_OP_WRITE);
buf_set_u64((unsigned char *)buf, DTM_DMI_DATA_OFFSET, DTM_DMI_DATA_LENGTH, d);
buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, a);
}

void riscv013_fill_dmi_read_u64(struct target *target, char *buf, int a)
static void riscv013_fill_dmi_read_u64(struct target *target, char *buf, int a)
{
RISCV013_INFO(info);
buf_set_u64((unsigned char *)buf, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, DMI_OP_READ);
buf_set_u64((unsigned char *)buf, DTM_DMI_DATA_OFFSET, DTM_DMI_DATA_LENGTH, 0);
buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, a);
}

void riscv013_fill_dmi_nop_u64(struct target *target, char *buf)
static void riscv013_fill_dmi_nop_u64(struct target *target, char *buf)
{
RISCV013_INFO(info);
buf_set_u64((unsigned char *)buf, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, DMI_OP_NOP);
buf_set_u64((unsigned char *)buf, DTM_DMI_DATA_OFFSET, DTM_DMI_DATA_LENGTH, 0);
buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, 0);
}

int riscv013_dmi_write_u64_bits(struct target *target)
static int riscv013_dmi_write_u64_bits(struct target *target)
{
RISCV013_INFO(info);
return info->abits + DTM_DMI_DATA_LENGTH + DTM_DMI_OP_LENGTH;
Expand Down Expand Up @@ -4933,7 +4933,7 @@ static int riscv013_step_or_resume_current_hart(struct target *target,
return ERROR_FAIL;
}

void riscv013_clear_abstract_error(struct target *target)
static void riscv013_clear_abstract_error(struct target *target)
{
/* Wait for busy to go away. */
time_t start = time(NULL);
Expand Down
50 changes: 25 additions & 25 deletions src/target/riscv/riscv.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,7 @@

#define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
#define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
#define field_value(mask, val) set_field((riscv_reg_t) 0, mask, val)
#define field_value(mask, val) set_field((riscv_reg_t)0, mask, val)

/*** JTAG registers. ***/

Expand Down Expand Up @@ -516,9 +516,9 @@ static bool can_use_napot_match(struct trigger *trigger)
{
riscv_reg_t addr = trigger->address;
riscv_reg_t size = trigger->length;
bool sizePowerOf2 = (size & (size - 1)) == 0;
bool addrAligned = (addr & (size - 1)) == 0;
return size > 1 && sizePowerOf2 && addrAligned;
bool size_power_of_2 = (size & (size - 1)) == 0;
bool addr_aligned = (addr & (size - 1)) == 0;
return size > 1 && size_power_of_2 && addr_aligned;
}

/* Find the next free trigger of the given type, without talking to the target. */
Expand All @@ -531,7 +531,7 @@ static int find_next_free_trigger(struct target *target, int type, bool chained,
unsigned int num_found = 0;
unsigned int num_required = chained ? 2 : 1;

for (unsigned i = *idx; i < r->trigger_count; i++) {
for (unsigned int i = *idx; i < r->trigger_count; i++) {
if (r->trigger_unique_id[i] == -1) {
if (r->trigger_tinfo[i] & (1 << type)) {
num_found++;
Expand Down Expand Up @@ -561,7 +561,7 @@ static int find_first_trigger_by_id(struct target *target, int unique_id)
{
RISCV_INFO(r);

for (unsigned i = 0; i < r->trigger_count; i++) {
for (unsigned int i = 0; i < r->trigger_count; i++) {
if (r->trigger_unique_id[i] == unique_id)
return i;
}
Expand Down Expand Up @@ -760,8 +760,8 @@ struct match_triggers_tdata1_fields {
riscv_reg_t tdata1_ignore_mask;
};

static struct match_triggers_tdata1_fields fill_match_triggers_tdata1_fields_t2(
struct target *target, struct trigger *trigger)
static struct match_triggers_tdata1_fields fill_match_triggers_tdata1_fields_t2(struct target *target,
struct trigger *trigger)
{
RISCV_INFO(r);

Expand Down Expand Up @@ -796,8 +796,8 @@ static struct match_triggers_tdata1_fields fill_match_triggers_tdata1_fields_t2(
return result;
}

static struct match_triggers_tdata1_fields fill_match_triggers_tdata1_fields_t6(
struct target *target, struct trigger *trigger)
static struct match_triggers_tdata1_fields fill_match_triggers_tdata1_fields_t6(struct target *target,
struct trigger *trigger)
{
bool misa_s = riscv_supports_extension(target, 'S');
bool misa_u = riscv_supports_extension(target, 'U');
Expand Down Expand Up @@ -1578,7 +1578,7 @@ int riscv_flush_registers(struct target *target)
/**
* Set OpenOCD's generic debug reason from the RISC-V halt reason.
*/
int set_debug_reason(struct target *target, enum riscv_halt_reason halt_reason)
static int set_debug_reason(struct target *target, enum riscv_halt_reason halt_reason)
{
RISCV_INFO(r);
r->trigger_hit = -1;
Expand Down Expand Up @@ -2684,7 +2684,7 @@ static int riscv_checksum_memory(struct target *target,
buf_set_u64(reg_params[1].value, 0, xlen, count);

/* 20 second timeout/megabyte */
int timeout = 20000 * (1 + (count / (1024 * 1024)));
unsigned int timeout = 20000 * (1 + (count / (1024 * 1024)));

retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
crc_algorithm->address,
Expand Down Expand Up @@ -2913,10 +2913,10 @@ int riscv_openocd_poll(struct target *target)
targets = &single_target_list;
}

unsigned should_remain_halted = 0;
unsigned should_resume = 0;
unsigned halted = 0;
unsigned running = 0;
unsigned int should_remain_halted = 0;
unsigned int should_resume = 0;
unsigned int halted = 0;
unsigned int running = 0;
struct target_list *entry;
foreach_smp_target(entry, targets) {
struct target *t = entry->target;
Expand Down Expand Up @@ -3509,9 +3509,9 @@ COMMAND_HANDLER(riscv_dmi_write)
- if debug module was reset, in which case progbuf registers
may not retain their value.
*/
bool progbufTouched = (address >= DM_PROGBUF0 && address <= DM_PROGBUF15);
bool dmDeactivated = (address == DM_DMCONTROL && (value & DM_DMCONTROL_DMACTIVE) == 0);
if (progbufTouched || dmDeactivated) {
bool progbuf_touched = (address >= DM_PROGBUF0 && address <= DM_PROGBUF15);
bool dm_deactivated = (address == DM_DMCONTROL && (value & DM_DMCONTROL_DMACTIVE) == 0);
if (progbuf_touched || dm_deactivated) {
if (r->invalidate_cached_debug_buffer)
r->invalidate_cached_debug_buffer(target);
}
Expand Down Expand Up @@ -3949,7 +3949,7 @@ COMMAND_HANDLER(handle_memory_sample_command)

if (CMD_ARGC == 0) {
command_print(CMD, "Memory sample configuration for %s:", target_name(target));
for (unsigned i = 0; i < ARRAY_SIZE(r->sample_config.bucket); i++) {
for (unsigned int i = 0; i < ARRAY_SIZE(r->sample_config.bucket); i++) {
if (r->sample_config.bucket[i].enabled) {
command_print(CMD, "bucket %d; address=0x%" TARGET_PRIxADDR "; size=%d", i,
r->sample_config.bucket[i].address,
Expand All @@ -3969,7 +3969,7 @@ COMMAND_HANDLER(handle_memory_sample_command)
uint32_t bucket;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], bucket);
if (bucket > ARRAY_SIZE(r->sample_config.bucket)) {
LOG_ERROR("Max bucket number is %d.", (unsigned) ARRAY_SIZE(r->sample_config.bucket));
LOG_ERROR("Max bucket number is %d.", (unsigned int)ARRAY_SIZE(r->sample_config.bucket));
return ERROR_COMMAND_ARGUMENT_INVALID;
}

Expand Down Expand Up @@ -4036,7 +4036,7 @@ COMMAND_HANDLER(handle_dump_sample_buf_command)
command_print(CMD, "%s", encoded);
free(encoded);
} else {
unsigned i = 0;
unsigned int i = 0;
while (i < r->sample_buf.used) {
uint8_t command = r->sample_buf.buf[i++];
if (command == RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE) {
Expand Down Expand Up @@ -4080,7 +4080,7 @@ COMMAND_HANDLER(handle_dump_sample_buf_command)
}

COMMAND_HELPER(riscv_print_info_line, const char *section, const char *key,
unsigned value)
unsigned int value)
{
char full_key[80];
snprintf(full_key, sizeof(full_key), "%s.%s", section, key);
Expand Down Expand Up @@ -4437,7 +4437,7 @@ static const struct command_registration riscv_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};

static unsigned riscv_xlen_nonconst(struct target *target)
static unsigned int riscv_xlen_nonconst(struct target *target)
{
return riscv_xlen(target);
}
Expand Down Expand Up @@ -5981,7 +5981,7 @@ int riscv_init_registers(struct target *target)
} else if (r->exist && !list_empty(&info->hide_csr)) {
range_list_t *entry;
list_for_each_entry(entry, &info->hide_csr, list)
if ((entry->low <= csr_number) && (csr_number <= entry->high)) {
if (entry->low <= csr_number && csr_number <= entry->high) {
LOG_TARGET_DEBUG(target, "Hiding CSR %d (name=%s)", csr_number, r->name);
r->hidden = true;
break;
Expand Down

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