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target/riscv: fix segfault on RISC-V Debug v0.11
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Change-Id: I5be9153f364a5ad5083e809f479aed5378e420c9
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
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en-sc committed Apr 19, 2024
1 parent 3991492 commit 73d9562
Showing 1 changed file with 5 additions and 9 deletions.
14 changes: 5 additions & 9 deletions src/target/riscv/riscv.c
Original file line number Diff line number Diff line change
Expand Up @@ -5842,7 +5842,7 @@ bool reg_is_initialized(const struct reg *reg)
}
assert(reg->arch_info);
assert(((riscv_reg_info_t *)reg->arch_info)->target);
assert((!reg->exist && !reg->value) || (reg->exist && reg->value));
assert(reg->value);
assert(reg->valid || !reg->dirty);
return true;
}
Expand Down Expand Up @@ -6194,14 +6194,10 @@ static int resize_reg(const struct target *target, uint32_t regno, bool exist,
free(reg->value);
reg->size = size;
reg->exist = exist;
if (reg->exist) {
reg->value = malloc(DIV_ROUND_UP(reg->size, 8));
if (!reg->value) {
LOG_ERROR("Failed to allocate memory.");
return ERROR_FAIL;
}
} else {
reg->value = NULL;
reg->value = malloc(DIV_ROUND_UP(reg->size, 8));
if (!reg->value) {
LOG_ERROR("Failed to allocate memory.");
return ERROR_FAIL;
}
assert(reg_is_initialized(reg));
return ERROR_OK;
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