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rename dbgbuf to progbuf
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Change-Id: I29e2192d5ce9d0f13010d8a09bd4ef50f5c8844b
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
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aap-sc committed Dec 22, 2023
1 parent 928f10a commit aded275
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Showing 5 changed files with 69 additions and 70 deletions.
35 changes: 17 additions & 18 deletions src/target/riscv/program.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,20 +24,19 @@ int riscv_program_init(struct riscv_program *p, struct target *target)
for (size_t i = 0; i < RISCV_REGISTER_COUNT; ++i)
p->writes_xreg[i] = 0;

for (size_t i = 0; i < RISCV_MAX_DEBUG_BUFFER_SIZE; ++i)
p->debug_buffer[i] = -1;
for (size_t i = 0; i < RISCV_MAX_PROGBUF_SIZE; ++i)
p->progbuf[i] = -1;

p->execution_result = RISCV_DBGBUF_EXEC_RESULT_NOT_EXECUTED;
p->execution_result = RISCV_PROGBUF_EXEC_RESULT_NOT_EXECUTED;
return ERROR_OK;
}

int riscv_program_write(struct riscv_program *program)
{
for (unsigned i = 0; i < program->instruction_count; ++i) {
LOG_TARGET_DEBUG(program->target, "debug_buffer[%02x] = DASM(0x%08x)",
i, program->debug_buffer[i]);
if (riscv_write_debug_buffer(program->target, i,
program->debug_buffer[i]) != ERROR_OK)
LOG_TARGET_DEBUG(program->target, "progbuf[%02x] = DASM(0x%08x)",
i, program->progbuf[i]);
if (riscv_write_progbuf(program->target, i, program->progbuf[i]) != ERROR_OK)
return ERROR_FAIL;
}
return ERROR_OK;
Expand All @@ -48,7 +47,7 @@ int riscv_program_exec(struct riscv_program *p, struct target *t)
{
keep_alive();

p->execution_result = RISCV_DBGBUF_EXEC_RESULT_UNKNOWN_ERROR;
p->execution_result = RISCV_PROGBUF_EXEC_RESULT_UNKNOWN;
riscv_reg_t saved_registers[GDB_REGNO_XPR31 + 1];
for (size_t i = GDB_REGNO_ZERO + 1; i <= GDB_REGNO_XPR31; ++i) {
if (p->writes_xreg[i]) {
Expand All @@ -61,25 +60,25 @@ int riscv_program_exec(struct riscv_program *p, struct target *t)

if (riscv_program_ebreak(p) != ERROR_OK) {
LOG_TARGET_ERROR(t, "Unable to insert ebreak into program buffer");
for (size_t i = 0; i < riscv_debug_buffer_size(p->target); ++i)
for (size_t i = 0; i < riscv_progbuf_size(p->target); ++i)
LOG_TARGET_ERROR(t, "ram[%02x]: DASM(0x%08" PRIx32 ") [0x%08" PRIx32 "]",
(int)i, p->debug_buffer[i], p->debug_buffer[i]);
(int)i, p->progbuf[i], p->progbuf[i]);
return ERROR_FAIL;
}

if (riscv_program_write(p) != ERROR_OK)
return ERROR_FAIL;

uint32_t cmderr;
if (riscv_execute_debug_buffer(t, &cmderr) != ERROR_OK) {
if (riscv_execute_progbuf(t, &cmderr) != ERROR_OK) {
p->execution_result = (cmderr == DM_ABSTRACTCS_CMDERR_EXCEPTION)
? RISCV_DBGBUF_EXEC_RESULT_EXCEPTION
: RISCV_DBGBUF_EXEC_RESULT_UNKNOWN_ERROR;
? RISCV_PROGBUF_EXEC_RESULT_EXCEPTION
: RISCV_PROGBUF_EXEC_RESULT_UNKNOWN_ERROR;
/* TODO: what happens if we fail here, but need to restore registers? */
LOG_TARGET_DEBUG(t, "Unable to execute program %p", p);
return ERROR_FAIL;
}
p->execution_result = RISCV_DBGBUF_EXEC_RESULT_SUCCESS;
p->execution_result = RISCV_PROGBUF_EXEC_RESULT_SUCCESS;

for (size_t i = GDB_REGNO_ZERO; i <= GDB_REGNO_XPR31; ++i)
if (p->writes_xreg[i])
Expand Down Expand Up @@ -200,7 +199,7 @@ int riscv_program_ebreak(struct riscv_program *p)
{
struct target *target = p->target;
RISCV_INFO(r);
if (p->instruction_count == riscv_debug_buffer_size(p->target) &&
if (p->instruction_count == riscv_progbuf_size(p->target) &&
r->impebreak) {
return ERROR_OK;
}
Expand All @@ -214,14 +213,14 @@ int riscv_program_addi(struct riscv_program *p, enum gdb_regno d, enum gdb_regno

int riscv_program_insert(struct riscv_program *p, riscv_insn_t i)
{
if (p->instruction_count >= riscv_debug_buffer_size(p->target)) {
if (p->instruction_count >= riscv_progbuf_size(p->target)) {
LOG_TARGET_ERROR(p->target, "Unable to insert program into progbuf, "
"capacity would be exceeded (progbufsize=%d).",
(int)riscv_debug_buffer_size(p->target));
(int)riscv_progbuf_size(p->target));
return ERROR_FAIL;
}

p->debug_buffer[p->instruction_count] = i;
p->progbuf[p->instruction_count] = i;
p->instruction_count++;
return ERROR_OK;
}
17 changes: 9 additions & 8 deletions src/target/riscv/program.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,24 +5,25 @@

#include "riscv.h"

#define RISCV_MAX_DEBUG_BUFFER_SIZE 32
#define RISCV_MAX_PROGBUF_SIZE 32
#define RISCV_REGISTER_COUNT 32
#define RISCV_DSCRATCH_COUNT 2

typedef enum {
RISCV_DBGBUF_EXEC_RESULT_NOT_EXECUTED,
RISCV_DBGBUF_EXEC_RESULT_EXCEPTION,
RISCV_DBGBUF_EXEC_RESULT_UNKNOWN_ERROR,
RISCV_DBGBUF_EXEC_RESULT_SUCCESS
} riscv_dbgbuf_exec_status_t;
RISCV_PROGBUF_EXEC_RESULT_NOT_EXECUTED,
RISCV_PROGBUF_EXEC_RESULT_UNKNOWN,
RISCV_PROGBUF_EXEC_RESULT_EXCEPTION,
RISCV_PROGBUF_EXEC_RESULT_UNKNOWN_ERROR,
RISCV_PROGBUF_EXEC_RESULT_SUCCESS
} riscv_progbuf_exec_result_t;

/* The various RISC-V debug specifications all revolve around setting up
* program buffers and executing them on the target. This structure contains a
* single program, which can then be executed on targets. */
struct riscv_program {
struct target *target;

uint32_t debug_buffer[RISCV_MAX_DEBUG_BUFFER_SIZE];
uint32_t progbuf[RISCV_MAX_PROGBUF_SIZE];

/* Number of 32-bit instructions in the program. */
size_t instruction_count;
Expand All @@ -36,7 +37,7 @@ struct riscv_program {

/* execution result of the program */
/* TODO: remove this field. We should make it a parameter to riscv_program_exec */
riscv_dbgbuf_exec_status_t execution_result;
riscv_progbuf_exec_result_t execution_result;
};

/* Initializes a program with the header. */
Expand Down
40 changes: 20 additions & 20 deletions src/target/riscv/riscv-013.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -49,12 +49,12 @@ static int riscv013_step_current_hart(struct target *target);
static int riscv013_on_step(struct target *target);
static int riscv013_resume_prep(struct target *target);
static enum riscv_halt_reason riscv013_halt_reason(struct target *target);
static int riscv013_write_debug_buffer(struct target *target, unsigned int index,
static int riscv013_write_progbuf(struct target *target, unsigned int index,
riscv_insn_t d);
static riscv_insn_t riscv013_read_debug_buffer(struct target *target, unsigned int
static riscv_insn_t riscv013_read_progbuf(struct target *target, unsigned int
index);
static int riscv013_invalidate_cached_debug_buffer(struct target *target);
static int riscv013_execute_debug_buffer(struct target *target, uint32_t *cmderr);
static int riscv013_invalidate_cached_progbuf(struct target *target);
static int riscv013_execute_progbuf(struct target *target, uint32_t *cmderr);
static void riscv013_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d);
static void riscv013_fill_dmi_read_u64(struct target *target, char *buf, int a);
static int riscv013_dmi_write_u64_bits(struct target *target);
Expand Down Expand Up @@ -1380,7 +1380,7 @@ static int scratch_write64(struct target *target, scratch_mem_t *scratch,
case SPACE_DMI_PROGBUF:
dm_write(target, DM_PROGBUF0 + scratch->debug_address, value);
dm_write(target, DM_PROGBUF1 + scratch->debug_address, value >> 32);
riscv013_invalidate_cached_debug_buffer(target);
riscv013_invalidate_cached_progbuf(target);
break;
case SPACE_DMI_RAM:
{
Expand Down Expand Up @@ -1919,7 +1919,7 @@ static int examine(struct target *target)
}
/* We're here because we're uncertain about the state of the target. That
* includes our progbuf cache. */
riscv013_invalidate_cached_debug_buffer(target);
riscv013_invalidate_cached_progbuf(target);

dm_write(target, DM_DMCONTROL, DM_DMCONTROL_HARTSELLO |
DM_DMCONTROL_HARTSELHI | DM_DMCONTROL_DMACTIVE |
Expand Down Expand Up @@ -2057,7 +2057,7 @@ static int examine(struct target *target)

/* Without knowing anything else we can at least mess with the
* program buffer. */
r->debug_buffer_size = info->progbufsize;
r->progbuf_size = info->progbufsize;

int result = register_read_abstract_with_size(target, NULL, GDB_REGNO_S0, 64);
if (result == ERROR_OK)
Expand Down Expand Up @@ -2757,10 +2757,10 @@ static int init_target(struct command_context *cmd_ctx,
generic_info->halt_go = &riscv013_halt_go;
generic_info->on_step = &riscv013_on_step;
generic_info->halt_reason = &riscv013_halt_reason;
generic_info->read_debug_buffer = &riscv013_read_debug_buffer;
generic_info->write_debug_buffer = &riscv013_write_debug_buffer;
generic_info->execute_debug_buffer = &riscv013_execute_debug_buffer;
generic_info->invalidate_cached_debug_buffer = &riscv013_invalidate_cached_debug_buffer;
generic_info->read_progbuf = &riscv013_read_progbuf;
generic_info->write_progbuf = &riscv013_write_progbuf;
generic_info->execute_progbuf = &riscv013_execute_progbuf;
generic_info->invalidate_cached_progbuf = &riscv013_invalidate_cached_progbuf;
generic_info->fill_dm_write_u64 = &riscv013_fill_dm_write_u64;
generic_info->fill_dm_read_u64 = &riscv013_fill_dm_read_u64;
generic_info->fill_dm_nop_u64 = &riscv013_fill_dm_nop_u64;
Expand Down Expand Up @@ -2835,7 +2835,7 @@ static int assert_reset(struct target *target)
/* The DM might have gotten reset if OpenOCD called us in some reset that
* involves SRST being toggled. So clear our cache which may be out of
* date. */
return riscv013_invalidate_cached_debug_buffer(target);
return riscv013_invalidate_cached_progbuf(target);
}

static int deassert_reset(struct target *target)
Expand Down Expand Up @@ -2915,7 +2915,7 @@ static int execute_fence(struct target *target)
* here, but there's no ISA-defined way of doing that. */
struct riscv_program program;

/* program.execution_result may indicate RISCV_DBGBUF_EXEC_RESULT_EXCEPTION -
/* program.execution_result may indicate RISCV_PROGBUF_EXEC_RESULT_EXCEPTION -
* currently, we ignore this error since most likely this is an indication
* that target does not support a fence instruction (execution of an
* unsupported instruction results in "Illegal instruction" exception on
Expand All @@ -2928,7 +2928,7 @@ static int execute_fence(struct target *target)
riscv_program_fence_i(&program);
riscv_program_fence_rw_rw(&program);
if (riscv_program_exec(&program, target) != ERROR_OK) {
if (program.execution_result != RISCV_DBGBUF_EXEC_RESULT_EXCEPTION) {
if (program.execution_result != RISCV_PROGBUF_EXEC_RESULT_EXCEPTION) {
LOG_TARGET_ERROR(target, "Unexpected error during fence execution");
return ERROR_FAIL;
}
Expand All @@ -2941,7 +2941,7 @@ static int execute_fence(struct target *target)
riscv_program_init(&program, target);
riscv_program_fence_i(&program);
if (riscv_program_exec(&program, target) != ERROR_OK) {
if (program.execution_result != RISCV_DBGBUF_EXEC_RESULT_EXCEPTION) {
if (program.execution_result != RISCV_PROGBUF_EXEC_RESULT_EXCEPTION) {
LOG_TARGET_ERROR(target, "Unexpected error during fence.i execution");
return ERROR_FAIL;
}
Expand All @@ -2951,7 +2951,7 @@ static int execute_fence(struct target *target)
riscv_program_init(&program, target);
riscv_program_fence_rw_rw(&program);
if (riscv_program_exec(&program, target) != ERROR_OK) {
if (program.execution_result != RISCV_DBGBUF_EXEC_RESULT_EXCEPTION) {
if (program.execution_result != RISCV_PROGBUF_EXEC_RESULT_EXCEPTION) {
LOG_TARGET_ERROR(target, "Unexpected error during fence rw, rw execution");
return ERROR_FAIL;
}
Expand Down Expand Up @@ -5103,7 +5103,7 @@ static enum riscv_halt_reason riscv013_halt_reason(struct target *target)
return RISCV_HALT_UNKNOWN;
}

static int riscv013_write_debug_buffer(struct target *target, unsigned int index, riscv_insn_t data)
static int riscv013_write_progbuf(struct target *target, unsigned int index, riscv_insn_t data)
{
dm013_info_t *dm = get_dm(target);
if (!dm)
Expand All @@ -5118,7 +5118,7 @@ static int riscv013_write_debug_buffer(struct target *target, unsigned int index
return ERROR_OK;
}

static riscv_insn_t riscv013_read_debug_buffer(struct target *target, unsigned int index)
static riscv_insn_t riscv013_read_progbuf(struct target *target, unsigned int index)
{
uint32_t value;
if (dm_read(target, &value, DM_PROGBUF0 + index) == ERROR_OK)
Expand All @@ -5127,7 +5127,7 @@ static riscv_insn_t riscv013_read_debug_buffer(struct target *target, unsigned i
return 0;
}

static int riscv013_invalidate_cached_debug_buffer(struct target *target)
static int riscv013_invalidate_cached_progbuf(struct target *target)
{
dm013_info_t *dm = get_dm(target);
if (!dm) {
Expand All @@ -5141,7 +5141,7 @@ static int riscv013_invalidate_cached_debug_buffer(struct target *target)
return ERROR_OK;
}

static int riscv013_execute_debug_buffer(struct target *target, uint32_t *cmderr)
static int riscv013_execute_progbuf(struct target *target, uint32_t *cmderr)
{
uint32_t run_program = 0;
run_program = set_field(run_program, AC_ACCESS_REGISTER_AARSIZE, 2);
Expand Down
26 changes: 13 additions & 13 deletions src/target/riscv/riscv.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3748,8 +3748,8 @@ COMMAND_HANDLER(riscv_dmi_write)
bool progbuf_touched = (address >= DM_PROGBUF0 && address <= DM_PROGBUF15);
bool dm_deactivated = (address == DM_DMCONTROL && (value & DM_DMCONTROL_DMACTIVE) == 0);
if (progbuf_touched || dm_deactivated) {
if (r->invalidate_cached_debug_buffer)
r->invalidate_cached_debug_buffer(target);
if (r->invalidate_cached_progbuf)
r->invalidate_cached_progbuf(target);
}

return retval;
Expand Down Expand Up @@ -3818,8 +3818,8 @@ COMMAND_HANDLER(riscv_dm_write)
bool progbuf_touched = (address >= DM_PROGBUF0 && address <= DM_PROGBUF15);
bool dm_deactivated = (address == DM_DMCONTROL && (value & DM_DMCONTROL_DMACTIVE) == 0);
if (progbuf_touched || dm_deactivated) {
if (r->invalidate_cached_debug_buffer)
r->invalidate_cached_debug_buffer(target);
if (r->invalidate_cached_progbuf)
r->invalidate_cached_progbuf(target);
}

return retval;
Expand Down Expand Up @@ -4465,7 +4465,7 @@ COMMAND_HANDLER(riscv_exec_progbuf)
return ERROR_FAIL;
}

if (riscv_debug_buffer_size(target) == 0) {
if (riscv_progbuf_size(target) == 0) {
LOG_TARGET_ERROR(target, "exec_progbuf: Program buffer not implemented "
"in the target.");
return ERROR_FAIL;
Expand Down Expand Up @@ -5341,29 +5341,29 @@ static enum riscv_halt_reason riscv_halt_reason(struct target *target)
return r->halt_reason(target);
}

size_t riscv_debug_buffer_size(struct target *target)
size_t riscv_progbuf_size(struct target *target)
{
RISCV_INFO(r);
return r->debug_buffer_size;
return r->progbuf_size;
}

int riscv_write_debug_buffer(struct target *target, int index, riscv_insn_t insn)
int riscv_write_progbuf(struct target *target, int index, riscv_insn_t insn)
{
RISCV_INFO(r);
r->write_debug_buffer(target, index, insn);
r->write_progbuf(target, index, insn);
return ERROR_OK;
}

riscv_insn_t riscv_read_debug_buffer(struct target *target, int index)
riscv_insn_t riscv_read_progbuf(struct target *target, int index)
{
RISCV_INFO(r);
return r->read_debug_buffer(target, index);
return r->read_progbuf(target, index);
}

int riscv_execute_debug_buffer(struct target *target, uint32_t *cmderr)
int riscv_execute_progbuf(struct target *target, uint32_t *cmderr)
{
RISCV_INFO(r);
return r->execute_debug_buffer(target, cmderr);
return r->execute_progbuf(target, cmderr);
}

void riscv_fill_dm_write_u64(struct target *target, char *buf, int a, uint64_t d)
Expand Down
21 changes: 10 additions & 11 deletions src/target/riscv/riscv.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -165,8 +165,8 @@ struct riscv_info {
* most recent halt was not caused by a trigger, then this is -1. */
uint32_t trigger_hit;

/* The number of entries in the debug buffer. */
int debug_buffer_size;
/* The number of entries in the program buffer. */
int progbuf_size;

/* This hart contains an implicit ebreak at the end of the program buffer. */
bool impebreak;
Expand Down Expand Up @@ -227,11 +227,10 @@ struct riscv_info {
int (*halt_go)(struct target *target);
int (*on_step)(struct target *target);
enum riscv_halt_reason (*halt_reason)(struct target *target);
int (*write_debug_buffer)(struct target *target, unsigned index,
riscv_insn_t d);
riscv_insn_t (*read_debug_buffer)(struct target *target, unsigned index);
int (*execute_debug_buffer)(struct target *target, uint32_t *cmderr);
int (*invalidate_cached_debug_buffer)(struct target *target);
int (*write_progbuf)(struct target *target, unsigned int index, riscv_insn_t d);
riscv_insn_t (*read_progbuf)(struct target *target, unsigned int index);
int (*execute_progbuf)(struct target *target, uint32_t *cmderr);
int (*invalidate_cached_progbuf)(struct target *target);
int (*dmi_write_u64_bits)(struct target *target);
void (*fill_dm_write_u64)(struct target *target, char *buf, int a, uint64_t d);
void (*fill_dm_read_u64)(struct target *target, char *buf, int a);
Expand Down Expand Up @@ -427,11 +426,11 @@ int riscv_get_hart_state(struct target *target, enum riscv_hart_state *state);

/* These helper functions let the generic program interface get target-specific
* information. */
size_t riscv_debug_buffer_size(struct target *target);
size_t riscv_progbuf_size(struct target *target);

riscv_insn_t riscv_read_debug_buffer(struct target *target, int index);
int riscv_write_debug_buffer(struct target *target, int index, riscv_insn_t insn);
int riscv_execute_debug_buffer(struct target *target, uint32_t *cmderr);
riscv_insn_t riscv_read_progbuf(struct target *target, int index);
int riscv_write_progbuf(struct target *target, int index, riscv_insn_t insn);
int riscv_execute_progbuf(struct target *target, uint32_t *cmderr);

void riscv_fill_dm_nop_u64(struct target *target, char *buf);
void riscv_fill_dm_write_u64(struct target *target, char *buf, int a, uint64_t d);
Expand Down

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