Merge pull request #949 from riscv/remove_esp32c_targets_from_doc

Remove mention of esp32c2, esp32c3 from doc
riscv-collab · Nov 1, 2023 · dc782f6 · dc782f6
2 parents 585f5db + 2d9c7a7
commit dc782f6
Showing 1 changed file with 0 additions and 2 deletions.
diff --git a/doc/openocd.texi b/doc/openocd.texi
@@ -4838,8 +4838,6 @@ compact Thumb2 instruction set. Supports also ARMv6-M and ARMv8-M cores
 @item @code{esirisc} -- this is an EnSilica eSi-RISC core.
 The current implementation supports eSi-32xx cores.
 @item @code{esp32} -- this is an Espressif SoC with dual Xtensa cores.
-@item @code{esp32c2} -- this is an Espressif SoC with single RISC-V core.
-@item @code{esp32c3} -- this is an Espressif SoC with single RISC-V core.
 @item @code{esp32s2} -- this is an Espressif SoC with single Xtensa core.
 @item @code{esp32s3} -- this is an Espressif SoC with dual Xtensa cores.
 @item @code{fa526} -- resembles arm920 (w/o Thumb).