[riscv.cpu] Debug Module did not become active. dmcontrol=0x0

[l1onog]

I implemented RISCV SoC on a Zcu102 fpga. I am trying to use openOCD and jtag-hs2 to download code to the board as instructed in the README. Does anyone know what could potentially cause this error and ways to fix it? @en-sc I would really appreciate it.

Here is what it shows when I run with -d3 flag:

Open On-Chip Debugger 0.12.0+dev-gca7d88252 (2024-04-26-14:36)
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
User : 3 2 options.c:52 configuration_output_handler(): debug_level: 3User : 4 2 options.c:52 configuration_output_handler(): 
Debug: 5 2 options.c:233 add_default_dirs(): bindir=/usr/local/bin
Debug: 6 2 options.c:234 add_default_dirs(): pkgdatadir=/usr/local/share/openocd
Debug: 7 2 options.c:235 add_default_dirs(): exepath=/usr/local/bin
Debug: 8 2 options.c:236 add_default_dirs(): bin2data=../share/openocd
Debug: 9 2 configuration.c:33 add_script_search_dir(): adding /home/fpga/.config/openocd
Debug: 10 2 configuration.c:33 add_script_search_dir(): adding /home/fpga/.openocd
Debug: 11 2 configuration.c:33 add_script_search_dir(): adding /usr/local/bin/../share/openocd/site
Debug: 12 2 configuration.c:33 add_script_search_dir(): adding /usr/local/bin/../share/openocd/scripts
Debug: 13 2 command.c:153 script_debug(): command - ocd_find /opt/riscv/pulp/fpga/pulp-zcu102/digilent-hs2.cfg
Debug: 14 2 configuration.c:88 find_file(): found /opt/riscv/pulp/fpga/pulp-zcu102/digilent-hs2.cfg
Debug: 15 2 command.c:153 script_debug(): command - adapter speed 1000
Debug: 16 2 adapter.c:250 adapter_config_khz(): handle adapter khz
Debug: 17 2 adapter.c:214 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 18 2 adapter.c:214 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 19 2 command.c:153 script_debug(): command - adapter driver ftdi
Debug: 20 2 command.c:153 script_debug(): command - ftdi device_desc Digilent USB Device
Debug: 21 2 command.c:153 script_debug(): command - ftdi vid_pid 0x0403 0x6014
Debug: 22 2 command.c:153 script_debug(): command - ftdi channel 0
Debug: 23 2 command.c:153 script_debug(): command - ftdi layout_init 0x00e8 0x60eb
Debug: 24 2 command.c:153 script_debug(): command - ftdi layout_signal SWD_EN -data 0x6000
Debug: 25 2 command.c:153 script_debug(): command - ftdi layout_signal SWDIO_OE -data 0x20
Debug: 26 3 command.c:153 script_debug(): command - transport select
Info : 27 3 transport.c:267 handle_transport_select(): auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
Debug: 28 3 command.c:153 script_debug(): command - transport select
Debug: 29 3 command.c:153 script_debug(): command - jtag newtap riscv unknown0 -irlen 5 -expected-id 0x10102001
Debug: 30 3 tcl.c:401 handle_jtag_newtap_args(): Creating New Tap, Chip: riscv, Tap: unknown0, Dotted: riscv.unknown0, 4 params
Debug: 31 3 core.c:1474 jtag_tap_init(): Created Tap: riscv.unknown0 @ abs position 0, irlen 5, capture: 0x1 mask: 0x3
Debug: 32 3 command.c:153 script_debug(): command - jtag newtap riscv cpu -irlen 5 -expected-id 0x249511C3
Debug: 33 3 tcl.c:401 handle_jtag_newtap_args(): Creating New Tap, Chip: riscv, Tap: cpu, Dotted: riscv.cpu, 4 params
Debug: 34 3 core.c:1474 jtag_tap_init(): Created Tap: riscv.cpu @ abs position 1, irlen 5, capture: 0x1 mask: 0x3
Debug: 35 3 command.c:153 script_debug(): command - target create riscv.cpu riscv -chain-position riscv.cpu -coreid 0x3e0
Debug: 36 3 target.c:2136 target_free_all_working_areas_restore(): freeing all working areas
Debug: 37 3 riscv.c:437 riscv_create_target(): [riscv.cpu] riscv_create_target()
Debug: 38 3 command.c:153 script_debug(): command - gdb_report_data_abort enable
Debug: 39 3 command.c:153 script_debug(): command - gdb_report_register_access_error enable
Debug: 40 3 command.c:153 script_debug(): command - scan_chain
Debug: 41 3 command.c:153 script_debug(): command - reset_config none
Debug: 42 3 command.c:153 script_debug(): command - init
Debug: 43 3 command.c:153 script_debug(): command - target init
Debug: 44 3 command.c:153 script_debug(): command - target names
Debug: 45 3 command.c:153 script_debug(): command - riscv.cpu cget -event gdb-flash-erase-start
Debug: 46 3 command.c:153 script_debug(): command - riscv.cpu configure -event gdb-flash-erase-start reset init
Debug: 47 3 command.c:153 script_debug(): command - riscv.cpu cget -event gdb-flash-write-end
Debug: 48 3 command.c:153 script_debug(): command - riscv.cpu configure -event gdb-flash-write-end reset halt
Debug: 49 3 command.c:153 script_debug(): command - riscv.cpu cget -event gdb-attach
Debug: 50 3 command.c:153 script_debug(): command - riscv.cpu configure -event gdb-attach halt 1000
Debug: 51 3 target.c:1594 handle_target_init_command(): Initializing targets...
Debug: 52 3 riscv.c:450 riscv_init_target(): [riscv.cpu] riscv_init_target()
Debug: 53 3 semihosting_common.c:107 semihosting_common_init():  
Debug: 54 3 ftdi.c:732 ftdi_initialize(): ftdi interface using shortest path jtag state transitions
Debug: 55 5 mpsse.c:406 mpsse_purge(): -
Debug: 56 6 mpsse.c:687 mpsse_loopback_config(): off
Debug: 57 6 mpsse.c:732 mpsse_set_frequency(): target 1000000 Hz
Debug: 58 6 mpsse.c:724 mpsse_rtck_config(): off
Debug: 59 6 mpsse.c:713 mpsse_divide_by_5_config(): off
Debug: 60 6 mpsse.c:693 mpsse_set_divisor(): 29
Debug: 61 6 mpsse.c:756 mpsse_set_frequency(): actually 1000000 Hz
Debug: 62 6 adapter.c:214 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 63 6 adapter.c:218 adapter_khz_to_speed(): have adapter set up
Debug: 64 6 mpsse.c:732 mpsse_set_frequency(): target 1000000 Hz
Debug: 65 6 mpsse.c:724 mpsse_rtck_config(): off
Debug: 66 6 mpsse.c:713 mpsse_divide_by_5_config(): off
Debug: 67 6 mpsse.c:693 mpsse_set_divisor(): 29
Debug: 68 6 mpsse.c:756 mpsse_set_frequency(): actually 1000000 Hz
Debug: 69 6 adapter.c:214 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 70 6 adapter.c:218 adapter_khz_to_speed(): have adapter set up
Info : 71 6 adapter.c:178 adapter_init(): clock speed 1000 kHz
Debug: 72 6 openocd.c:133 handle_init_command(): Debug Adapter init complete
Debug: 73 6 command.c:153 script_debug(): command - transport init
Debug: 74 6 transport.c:219 handle_transport_init(): handle_transport_init
Debug: 75 6 core.c:830 jtag_add_reset(): SRST line released
Debug: 76 6 core.c:855 jtag_add_reset(): TRST line released
Debug: 77 6 core.c:328 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 78 6 command.c:153 script_debug(): command - jtag arp_init
Debug: 79 6 core.c:1509 jtag_init_inner(): Init JTAG chain
Debug: 80 6 core.c:328 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 81 6 core.c:1234 jtag_examine_chain(): DR scan interrogation for IDCODE/BYPASS
Debug: 82 6 core.c:328 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 83 7 jep106.c:22 jep106_table_manufacturer(): BUG: Caller passed out-of-range JEP106 ID!
Info : 84 7 core.c:1133 jtag_examine_chain_display(): JTAG tap: riscv.unknown0 tap/device found: 0x10102001 (mfg: 0x000 (<invalid>), part: 0x0102, ver: 0x1)
Info : 85 7 core.c:1133 jtag_examine_chain_display(): JTAG tap: riscv.cpu tap/device found: 0x249511c3 (mfg: 0x0e1 (Wintec Industries), part: 0x4951, ver: 0x2)
Debug: 86 7 core.c:1364 jtag_validate_ircapture(): IR capture validation scan
Debug: 87 7 core.c:1421 jtag_validate_ircapture(): riscv.unknown0: IR capture 0x05
Debug: 88 7 core.c:1421 jtag_validate_ircapture(): riscv.cpu: IR capture 0x05
Debug: 89 7 command.c:153 script_debug(): command - dap init
Debug: 90 7 arm_dap.c:96 dap_init_all(): Initializing all DAPs ...
Debug: 91 7 openocd.c:150 handle_init_command(): Examining targets...
Debug: 92 7 target.c:675 target_examine_one(): [riscv.cpu] Examination started
Debug: 93 7 target.c:1780 target_call_event_callbacks(): target event 19 (examine-start) for core riscv.cpu
Debug: 94 7 riscv.c:1727 riscv_examine(): [riscv.cpu] Starting examination
Debug: 95 7 riscv.c:406 dtmcontrol_scan(): DTMCONTROL: 0x0 -> 0x1c71
Debug: 96 7 riscv.c:1741 riscv_examine(): [riscv.cpu] dtmcontrol=0x1c71
Debug: 97 7 riscv.c:1743 riscv_examine(): [riscv.cpu] version=0x1
Debug: 98 7 riscv-013.c:2776 init_target(): [riscv.cpu] Init.
Debug: 99 7 riscv-013.c:1922 examine(): [riscv.cpu] dbgbase=0x0
Debug: 100 7 riscv-013.c:478 dtmcontrol_scan(): DTMCS: 0x0 -> 0x1c71
Debug: 101 7 riscv-013.c:1930 examine(): [riscv.cpu] dtmcontrol=0x1c71
Debug: 102 7 riscv-013.c:1931 examine(): [riscv.cpu] dtmcs=0x1c71 {version=1_0 dmistat=3 idle=1 errinfo=not_implemented abits=7}
Debug: 103 7 riscv-013.c:791 check_dbgbase_exists(): [riscv.cpu] Searching for DM with DMI base address (dbgbase) = 0x0
Debug: 104 7 riscv-013.c:250 get_dm(): [riscv.cpu] Coreid [992] Allocating new DM
Debug: 105 7 riscv-013.c:520 dmi_scan(): [riscv.cpu] reset_delays_wait done
Debug: 106 7 riscv-013.c:420 dump_field(): 41b w 00000000 @10 -> b 00000000 @10; 0i
Debug: 107 7 riscv-013.c:428 dump_field(): write: dmcontrol=0 {}
Debug: 108 7 riscv-013.c:489 increase_dmi_busy_delay(): [riscv.cpu] dtmcs_idle=1, dmi_busy_delay=1, ac_busy_delay=0
Debug: 109 7 riscv-013.c:478 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 110 7 riscv-013.c:420 dump_field(): 41b w 00000000 @10 -> + 00000000 @10; 1i
Debug: 111 7 riscv-013.c:428 dump_field(): write: dmcontrol=0 {}
Debug: 112 7 riscv-013.c:420 dump_field(): 41b - 00000000 @10 -> b 00000000 @10; 1i
Debug: 113 7 riscv-013.c:489 increase_dmi_busy_delay(): [riscv.cpu] dtmcs_idle=1, dmi_busy_delay=2, ac_busy_delay=0
Debug: 114 8 riscv-013.c:478 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 115 8 riscv-013.c:420 dump_field(): 41b - 00000000 @10 -> + 00000000 @10; 2i
Debug: 116 8 riscv-013.c:420 dump_field(): 41b w 00000001 @10 -> b 00000000 @10; 2i
Debug: 117 8 riscv-013.c:428 dump_field(): write: dmcontrol=1 {dmactive=active}
Debug: 118 8 riscv-013.c:489 increase_dmi_busy_delay(): [riscv.cpu] dtmcs_idle=1, dmi_busy_delay=3, ac_busy_delay=0
Debug: 119 8 riscv-013.c:478 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 120 8 riscv-013.c:420 dump_field(): 41b w 00000001 @10 -> + 00000000 @10; 3i
Debug: 121 8 riscv-013.c:428 dump_field(): write: dmcontrol=1 {dmactive=active}
Debug: 122 8 riscv-013.c:420 dump_field(): 41b - 00000000 @10 -> b 00000000 @10; 3i
Debug: 123 8 riscv-013.c:489 increase_dmi_busy_delay(): [riscv.cpu] dtmcs_idle=1, dmi_busy_delay=4, ac_busy_delay=0
Debug: 124 8 riscv-013.c:478 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 125 8 riscv-013.c:420 dump_field(): 41b - 00000000 @10 -> + 00000000 @10; 4i
Debug: 126 8 riscv-013.c:5181 riscv013_invalidate_cached_progbuf(): [riscv.cpu] Invalidating progbuf cache
Debug: 127 8 riscv-013.c:420 dump_field(): 41b w 07ffffc1 @10 -> b 00000000 @10; 4i
Debug: 128 8 riscv-013.c:428 dump_field(): write: dmcontrol=0x7ffffc1 {dmactive=active hartsello=0x3ff hasel=multiple hartselhi=0x3ff}
Debug: 129 8 riscv-013.c:489 increase_dmi_busy_delay(): [riscv.cpu] dtmcs_idle=1, dmi_busy_delay=5, ac_busy_delay=0
Debug: 130 9 riscv-013.c:478 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 131 9 riscv-013.c:420 dump_field(): 41b w 07ffffc1 @10 -> + 00000000 @10; 5i
Debug: 132 9 riscv-013.c:428 dump_field(): write: dmcontrol=0x7ffffc1 {dmactive=active hartsello=0x3ff hasel=multiple hartselhi=0x3ff}
Debug: 133 9 riscv-013.c:420 dump_field(): 41b - 00000000 @10 -> b 00000000 @10; 5i
Debug: 134 9 riscv-013.c:489 increase_dmi_busy_delay(): [riscv.cpu] dtmcs_idle=1, dmi_busy_delay=6, ac_busy_delay=0
Debug: 135 9 riscv-013.c:478 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 136 9 riscv-013.c:420 dump_field(): 41b - 00000000 @10 -> + 00000000 @10; 6i
Debug: 137 9 riscv-013.c:420 dump_field(): 41b r 00000000 @10 -> b 00000000 @10; 6i
Debug: 138 9 riscv-013.c:489 increase_dmi_busy_delay(): [riscv.cpu] dtmcs_idle=1, dmi_busy_delay=7, ac_busy_delay=0
Debug: 139 9 riscv-013.c:478 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 140 9 riscv-013.c:420 dump_field(): 41b r 00000000 @10 -> + 00000000 @10; 7i
Debug: 141 9 riscv-013.c:420 dump_field(): 41b - 00000000 @10 -> b 00000000 @10; 7i
Debug: 142 9 riscv-013.c:489 increase_dmi_busy_delay(): [riscv.cpu] dtmcs_idle=1, dmi_busy_delay=8, ac_busy_delay=0
Debug: 143 10 riscv-013.c:478 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 144 10 riscv-013.c:420 dump_field(): 41b - 00000000 @10 -> + 00000000 @10; 8i
Debug: 145 10 riscv-013.c:434 dump_field(): read: dmcontrol=0 {}
Debug: 146 10 riscv-013.c:420 dump_field(): 41b w 00000001 @10 -> b 00000000 @10; 8i
Debug: 147 10 riscv-013.c:428 dump_field(): write: dmcontrol=1 {dmactive=active}
Debug: 148 10 riscv-013.c:489 increase_dmi_busy_delay(): [riscv.cpu] dtmcs_idle=1, dmi_busy_delay=9, ac_busy_delay=0
Debug: 149 10 riscv-013.c:478 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 150 10 riscv-013.c:420 dump_field(): 41b w 00000001 @10 -> + 00000000 @10; 9i
Debug: 151 10 riscv-013.c:428 dump_field(): write: dmcontrol=1 {dmactive=active}
Debug: 152 10 riscv-013.c:420 dump_field(): 41b - 00000000 @10 -> b 00000000 @10; 9i
Debug: 153 10 riscv-013.c:489 increase_dmi_busy_delay(): [riscv.cpu] dtmcs_idle=1, dmi_busy_delay=10, ac_busy_delay=0
Debug: 154 10 riscv-013.c:478 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 155 10 riscv-013.c:420 dump_field(): 41b - 00000000 @10 -> + 00000000 @10; 10i
Error: 156 10 riscv-013.c:1976 examine(): [riscv.cpu] Debug Module did not become active. dmcontrol=0x0
Error: 157 10 target.c:681 target_examine_one(): [riscv.cpu] Examination failed
Debug: 158 10 target.c:682 target_examine_one(): [riscv.cpu] examine() returned error code -4
Debug: 159 10 target.c:1780 target_call_event_callbacks(): target event 20 (examine-fail) for core riscv.cpu
Warn : 160 10 target.c:739 target_examine(): target riscv.cpu examination failed
Debug: 161 10 openocd.c:152 handle_init_command(): target examination failed
Debug: 162 10 command.c:153 script_debug(): command - flash init
Debug: 163 10 tcl.c:1364 handle_flash_init_command(): Initializing flash devices...
Debug: 164 10 command.c:153 script_debug(): command - nand init
Debug: 165 10 tcl.c:484 handle_nand_init_command(): Initializing NAND devices...
Debug: 166 10 command.c:153 script_debug(): command - pld init
Debug: 167 10 pld.c:337 handle_pld_init_command(): Initializing PLDs...
Debug: 168 10 command.c:153 script_debug(): command - tpiu init
Info : 169 10 gdb_server.c:3888 gdb_target_start(): starting gdb server for riscv.cpu on 3333
Info : 170 10 server.c:297 add_service(): Listening on port 3333 for gdb connections
Debug: 171 10 command.c:153 script_debug(): command - target names
Debug: 172 10 command.c:153 script_debug(): command - halt
Debug: 173 10 target.c:3239 handle_halt_command(): -
Error: 174 10 target.c:513 target_halt(): Target not examined yet
Debug: 175 10 command.c:528 exec_command(): Command 'halt' failed with error code -4
User : 176 10 command.c:601 command_run_line(): 
Debug: 177 10 breakpoints.c:319 breakpoint_remove_all_internal(): [riscv.cpu] Delete all breakpoints
Debug: 178 10 riscv.c:535 riscv_deinit_target(): [riscv.cpu] riscv_deinit_target()
Error: 179 10 riscv.c:429 get_target_type(): [riscv.cpu] Unsupported DTM version: -1
Error: 180 10 riscv.c:540 riscv_deinit_target(): [riscv.cpu] Could not identify target type.
Debug: 181 10 target.c:2136 target_free_all_working_areas_restore(): freeing all working areas

Also, the contents of my cfg file:

# SPDX-License-Identifier: GPL-2.0-or-later

# this supports JTAG-HS2 (and apparently Nexys4 as well)

# ADBUS5 controls TMS tri-state buffer enable
# ACBUS6=SEL_TMS controls mux to TMS output buffer: 0=TMS 1=TDI
# ACBUS5=SEL_TDO controls mux to TDO input: 0=TDO 1=TMS

adapter speed 1000

adapter driver ftdi
ftdi device_desc "Digilent USB Device"
ftdi vid_pid 0x0403 0x6014

ftdi channel 0
ftdi layout_init 0x00e8 0x60eb
ftdi layout_signal SWD_EN -data 0x6000
ftdi layout_signal SWDIO_OE -data 0x20

set _CHIPNAME riscv

jtag newtap $_CHIPNAME unknown0 -irlen 5 -expected-id 0x10102001
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x249511C3

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0x3e0

gdb_report_data_abort enable
gdb_report_register_access_error enable


# dump jtag chain
scan_chain
reset_config none


init
halt
echo "Ready for Remote Connections"

[en-sc]

From the log it seems you are using a version from ca7d882 (Feb 27).
Please, try to use a more recent version. There were recent changes in DM examination related code. This would help me with diagnosing the issue a lot.
Also, could you please attach a log in a file / zip archive. The conversation will get flooded with logs otherwise.

[l1onog]

hi, @en-sc , I have used the latest version of openocd, and this is my result.
d3.txt

[en-sc]

@l1onog, looking at the logs it may be a different issue.
Please, check if #1061 fixes it.

[l1onog]

hi, @en-sc, I appreciate your suggestion, but it seems like it won’t resolve my issue.
new_d3.txt
I adjusted the 'set_command_timeout_sec' from 2 seconds to 240 seconds as suggested by the error message, but it still isn’t working."

[l1onog]

@l1onog, looking at the logs it may be a different issue. Please, check if #1061 fixes it.

hi, @en-sc , I tried to replace the new JTAG-HS2, but it still reports an error, this is the exact error report,
d3-2024-05-07.txt
how do I actually fix it? What is the problem?

[en-sc]

@l1onog, in the log you have attached it can be observed that:

1. The DMI dtmcs is read successfully:

Debug: 97 6 riscv.c:1725 riscv_examine(): [riscv.cpu] Starting examination
Debug: 98 6 riscv.c:406 dtmcontrol_scan(): DTMCONTROL: 0x0 -> 0x1c71
Debug: 99 6 riscv.c:1739 riscv_examine(): [riscv.cpu] dtmcontrol=0x1c71
Debug: 100 6 riscv.c:1741 riscv_examine(): [riscv.cpu] version=0x1

2. However, the following read of DM's dmcontrol register does not succeed and returns busy for 2 minutes.

Debug: 109 7 riscv-013.c:415 riscv_decode_dmi_scan(): 41b r 00000000 @10 -> b 00000000 @10; 0i
Debug: 110 7 riscv-013.c:492 increase_dmi_busy_delay(): [riscv.cpu] dtmcs_idle=1, dmi_busy_delay=1, ac_busy_delay=0
Debug: 111 7 riscv-013.c:481 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 112 7 riscv-013.c:415 riscv_decode_dmi_scan(): 41b r 00000000 @10 -> b 00000000 @10; 1i
...
Debug: 562 124197 riscv-013.c:415 riscv_decode_dmi_scan(): 41b r 00000000 @10 -> b 00000000 @10; 11019046i
Debug: 563 124197 riscv-013.c:492 increase_dmi_busy_delay(): [riscv.cpu] dtmcs_idle=1, dmi_busy_delay=12120951, ac_busy_delay=0
Debug: 564 124199 riscv-013.c:481 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Error: 565 124199 riscv-013.c:694 dmi_op(): [riscv.cpu] DMI operation didn't complete in 120 seconds. The target is either really slow or broken. You could increase the timeout with riscv set_command_timeout_sec.

I can see the following reasons for such behavior:

1. There is no DM at with DMI base address 0x0. This would indicate an issue with the Debug Module / Debug Message Interface you are using, since the spec requires [3.1. Debug Module Interface (DMI)]:

The bottom of the address space is used for the first (and usually only) DM
Please, verify this is not the case with your provider of Debug Module / Debug Message Interface implemetation.

2. In your DM implementation dmstatus can not be read while dmstatus.dmactive is low. Here I would also need further information about your DM implementation -- which version of RISC-V Debug Spec it supports (v0.13 or v1.0)? The specification is obscure in what is required from the DM when dmstatus.dmactive is low and there is an issue described here: How to reset the DM on the first connection on both 0.13 and 1.0 spec versions riscv/riscv-debug-spec#1021

[l1onog]

Hi, @en-sc , Thank you for your kind reply, the version of RISCV debugging I am using is 0.13. Also, if it is my debugging module that is causing the problem, how can I fix it?

[TommyMurphyTM1234]

Also, if it is my debugging module that is causing the problem, how can I fix it?

By modifying the HDL code for the FPGA implementation of your RISC-V. But that's moot until such time as the root cause of your issues has been identified.