Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

RISC-V v0.11: Writes to register x0 (zero) should not be cached. #1086

Open
en-sc opened this issue Jun 6, 2024 · 0 comments
Open

RISC-V v0.11: Writes to register x0 (zero) should not be cached. #1086

en-sc opened this issue Jun 6, 2024 · 0 comments
Labels
Good First Issue This label marks the first good issue for anyone willing to contribute to the project.

Comments

@en-sc
Copy link
Collaborator

en-sc commented Jun 6, 2024

Wrtiting zero on RISC-V Debug Spec v0.11 changes it's cached value.

Please see comments on how to fix it:

This functionality (non-zero write to zero) should be tested in riscv-tests/debug
@en-sc en-sc mentioned this issue Jun 6, 2024
Merged
@en-sc en-sc added the Good First Issue This label marks the first good issue for anyone willing to contribute to the project. label Jun 6, 2024
@JanMatCodasip JanMatCodasip changed the title Writes to register x0 (zero) should not be cached. RISC-V 0.11: Writes to register x0 (zero) should not be cached. Jun 7, 2024
@JanMatCodasip JanMatCodasip changed the title RISC-V 0.11: Writes to register x0 (zero) should not be cached. RISC-V v0.11: Writes to register x0 (zero) should not be cached. Jun 7, 2024
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
Good First Issue This label marks the first good issue for anyone willing to contribute to the project.
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
1 participant
@en-sc