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investigate output of poll #196

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timsifive opened this issue Jan 26, 2018 · 3 comments
Closed

investigate output of poll #196

timsifive opened this issue Jan 26, 2018 · 3 comments

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@timsifive
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This is verbose on ARM. http://openocd.org/doc/html/Server-Configuration.html says eg.:

> poll
background polling: on
target state: halted
target halted in ARM state due to debug-request, \
               current mode: Supervisor
cpsr: 0x800000d3 pc: 0x11081bfc
MMU: disabled, D-Cache: disabled, I-Cache: enabled
>

On RISC-V we don't get that output:

> poll
background polling: on
TAP: riscv.cpu (enabled)
> status
@timsifive
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I think the ARM example is old. Current mainline OpenOCD displays the TAP: ... line instead of target state: ... and that seems to have been the case since 2008. Then the remaining output comes from the target's arch_state() which is supposed to "Issue USER() w/architecture specific status." We could print out which hardware trigger was halted, but aside from that I can't imagine what we'd want to display.

@TommyMurphyTM1234
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TommyMurphyTM1234 commented Aug 20, 2018

No - a build of the very latest openocd from https://github.com/riscv/riscv-openocd gives the following output for a Cortex-M3 target poll:

Open On-Chip Debugger
> poll
background polling: on
TAP: M2S090.cpu (enabled)
> reset init
target halted due to debug-request, current mode: Thread
xPSR: 00000000 pc: 00000000 msp: 00000000
lr (/32): 0x00000000
xPSR (/32): 0x01000000
> poll
background polling: on
TAP: M2S090.cpu (enabled)
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 00000000 msp: 00000000
> resume
> poll
background polling: on
TAP: M2S090.cpu (enabled)
>                            

Note also that the documentation (http://openocd.org/doc/pdf/openocd.pdf) says this about the poll command (with no "on" or "off" argument):

Poll the current target for its current state. (Also, see [target curstate], page 68.)
If that target is in debug mode, architecture specific information about the current
state is printed. An optional parameter allows background polling to be enabled and
disabled.

So I believe that the RISC-V implementation of poll should act similarly and in accordance with the documentation. At the very least the poll command should state that the target is in "debug halt" when that is the case?

en-sc added a commit to en-sc/riscv-openocd that referenced this issue Jan 23, 2024
Addresses issue riscv-collab#196.

Change-Id: I71146c7bc769cb9727e57da33e9f514eedef9ce4
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
en-sc added a commit to en-sc/riscv-openocd that referenced this issue Jan 24, 2024
Addresses issue riscv-collab#196.

Change-Id: I71146c7bc769cb9727e57da33e9f514eedef9ce4
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
@en-sc
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en-sc commented Jan 26, 2024

The issue is addressed by #1002.

@en-sc en-sc closed this as completed Jan 26, 2024
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