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target/riscv: fix segfault on RISC-V Debug v0.11 #1045

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@en-sc en-sc commented Apr 19, 2024

Change-Id: I5be9153f364a5ad5083e809f479aed5378e420c9

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en-sc commented Apr 19, 2024

Fails testing. Need to adjust checks in reg_is_initialized()

Change-Id: I5be9153f364a5ad5083e809f479aed5378e420c9
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
@TommyMurphyTM1234
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I manually patched that in but still doesn't work unfortunately:

Debug: 92 106 target.c:675 target_examine_one(): [riscv.cpu] Examination started
Debug: 93 106 target.c:1780 target_call_event_callbacks(): target event 19 (examine-start) for core riscv.cpu
Debug: 94 106 riscv.c:1725 riscv_examine(): [riscv.cpu] Starting examination
Debug: 95 107 riscv.c:406 dtmcontrol_scan(): DTMCONTROL: 0x0 -> 0x1450
Debug: 96 107 riscv.c:1739 riscv_examine(): [riscv.cpu] dtmcontrol=0x1450
Debug: 97 107 riscv.c:1741 riscv_examine(): [riscv.cpu] version=0x0
Debug: 98 107 riscv-011.c:2374 init_target(): init
Debug: 99 107 riscv.c:6264 riscv_init_reg_cache(): [riscv.cpu] create register cache for 4194 registers
openocd: src/target/riscv/riscv.c:5845: reg_is_initialized: Assertion `reg->value' failed.
Debug: 100 107 server.c:608 sig_handler(): Terminating on Signal 6
Aborted (core dumped)
Core was generated by `./openocd -f board/sifive-hifive1.cfg -d3'.
Program terminated with signal SIGABRT, Aborted.
#0  __pthread_kill_implementation (no_tid=0, signo=6, threadid=131911017418432) at ./nptl/pthread_kill.c:44
44	./nptl/pthread_kill.c: No such file or directory.
[Current thread is 1 (Thread 0x77f8ed55cec0 (LWP 124114))]
(gdb) bt
#0  __pthread_kill_implementation (no_tid=0, signo=6, threadid=131911017418432) at ./nptl/pthread_kill.c:44
#1  __pthread_kill_internal (signo=6, threadid=131911017418432) at ./nptl/pthread_kill.c:78
#2  __GI___pthread_kill (threadid=131911017418432, signo=signo@entry=6) at ./nptl/pthread_kill.c:89
#3  0x000077f8ed242476 in __GI_raise (sig=sig@entry=6) at ../sysdeps/posix/raise.c:26
#4  0x000077f8ed228885 in __GI_abort () at ./stdlib/abort.c:100
#5  0x000077f8ed22871b in __assert_fail_base (fmt=0x77f8ed3dd130 "%s%s%s:%u: %s%sAssertion `%s' failed.\n%n", assertion=0x619861b36415 "reg->value", file=0x619861b35a48 "src/target/riscv/riscv.c", line=5845, function=<optimized out>)
    at ./assert/assert.c:92
#6  0x000077f8ed239e96 in __GI___assert_fail (assertion=assertion@entry=0x619861b36415 "reg->value", file=file@entry=0x619861b35a48 "src/target/riscv/riscv.c", line=line@entry=5845, 
    function=function@entry=0x619861b3c730 <__PRETTY_FUNCTION__.34> "reg_is_initialized") at ./assert/assert.c:101
#7  0x000061986195c84f in reg_is_initialized (reg=reg@entry=0x619863ac90c0) at src/target/riscv/riscv.c:5845
#8  0x000061986195c8c9 in resize_reg (regno=regno@entry=0, exist=<optimized out>, size=32, target=<optimized out>, target=<optimized out>) at src/target/riscv/riscv.c:6193
#9  0x000061986195d074 in init_reg (regno=0, target=0xffffffbf) at src/target/riscv/riscv.c:6241
#10 riscv_init_registers (target=target@entry=0x619863a5dcc0) at src/target/riscv/riscv.c:6442
#11 0x0000619861a71055 in init_target (cmd_ctx=<optimized out>, target=0x619863a5dcc0) at src/target/riscv/riscv-011.c:2389
#12 0x00006198619533ac in riscv_examine (target=0x619863a5dcc0) at src/target/riscv/riscv.c:1748
#13 0x0000619861941587 in target_examine_one (target=target@entry=0x619863a5dcc0) at src/target/target.c:679
#14 0x00006198619416ee in target_examine () at src/target/target.c:737
#15 0x00006198618e7028 in handle_init_command (cmd=0x7ffee4808dd0) at src/openocd.c:151
#16 handle_init_command (cmd=0x7ffee4808dd0) at src/openocd.c:108
#17 0x0000619861974fa4 in exec_command (argv=0x7ffee4808f30, argc=1, c=0x619863a2dce0, context=0x619863a0c2a0, interp=0x619863a0c300) at src/helper/command.c:520
#18 jim_command_dispatch (interp=0x619863a0c300, argc=1, argv=0x7ffee4808f30) at src/helper/command.c:931
#19 0x0000619861ae5df0 in JimInvokeCommand ()
#20 0x0000619861c5b9a0 in ?? ()
#21 0x0000000000000000 in ?? ()
(gdb) 

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en-sc commented Apr 19, 2024

I manually patched that in but still doesn't work unfortunately:

I'm sorry, I've rushed a bit. Should be working now.

@TommyMurphyTM1234
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Ok, thanks. I'll check again in a little while. An offline with respect to the desktop right now.

@TommyMurphyTM1234
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Yes - the latest change fixes the segfault. 👍

@JanMatCodasip
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JanMatCodasip commented Apr 22, 2024

@en-sc Please, could you explain the original issue a bit more. Is there a function that de-references reg->value even if reg->exist == false?

Thank you.

Edit: I have already noticed the related discussion under #1046, so no need to comment on this one anymore :)

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en-sc commented Apr 23, 2024

Closing this one. IMHO, #1046 is better.

@en-sc en-sc closed this Apr 23, 2024
@en-sc en-sc self-assigned this Apr 23, 2024
@en-sc en-sc requested review from JanMatCodasip and MarekVCodasip and removed request for JanMatCodasip and MarekVCodasip April 23, 2024 18:04
@en-sc en-sc removed their assignment Apr 23, 2024
@en-sc en-sc deleted the en-sc/reg-rv011-segfault branch August 14, 2024 18:37
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3 participants