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target/riscv/riscv-011.c: fix access to non-existent register #1046

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merged 1 commit into from
Apr 26, 2024

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@en-sc en-sc commented Apr 19, 2024

reg is a number in register cache, as evident by the following call to
reg_cache_set(). CSR_DCSR is GDB_REGNO_DCSR - 65. This results in
setting cache value for another register, which does not exist, and
causes a segfault if all non-existent registers are not allocated a
value (reg->value == NULL).

@en-sc en-sc force-pushed the en-sc/reg-rv011-segfault-propper branch from 615fcf9 to 5ff41a7 Compare April 19, 2024 20:14
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en-sc commented Apr 19, 2024

@TommyMurphyTM1234, if it's not too much to ask, could you please also check this one?

It's an alternative to #1045.

I would have much preferred to merge this one instead.

The thing is, #1045 addresses the symptom, not the root cause. The segfault is caused by an access to a value of non-existent register:

#0  buf_set_u64 (value=1024, num=32, first=0, _buffer=0x0) at ./src/helper/binarybuffer.h:69
#1  reg_cache_set (number=number@entry=1969, value=1024, target=<optimized out>, target=<optimized out>) at src/target/riscv/riscv-011.c:1214

In #1022 I've changed the procedure allocating the buffer for cached register's value. I've stopped allocating the space for non-existent registers. I think this is reasonable. This is why the issue popped-up.

However, AFAIU, the issue was present, just silent. It seems like register cache is mismanaged in riscv-011.c -- value of dcsr is saved in cache, but using the wrong index (CSR_DCSR instead of GDB_REGNO_DCSR). So the value of dcsr was cached in two cache entries -- sometimes in one, sometimes in the other. This may be intentional, though I can't immediately see a reason for such strange behavior.

This patch should fix this.

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Yes I can check that but probably not until tomorrow if that's ok.

`reg` is a number in register cache, as evident by the following call to
`reg_cache_set()`. `CSR_DCSR` is `GDB_REGNO_DCSR - 65`. This results in
setting cache value for another register, which does not exist, and
causes a segfault if all non-existent registers are not allocated a
value (`reg->value == NULL`).

Change-Id: Iab68a4bb55ce6d4730804e9709e40ab2af8a07c6
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
@en-sc en-sc force-pushed the en-sc/reg-rv011-segfault-propper branch from 5ff41a7 to 967510c Compare April 19, 2024 21:14
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I tried that and it works.
Just to be clear, I just ran OpenOCD so that it examined/connected to the HiFive1 board.
I didn't do any more extensive testing.
But if you need that (e.g. a run of the test suite?) I can do that.
Otherwise I can revert to looking at the original PR:

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Reviewed visually & LGTM, thank you.

@en-sc en-sc merged commit de03da8 into riscv-collab:riscv Apr 26, 2024
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@en-sc en-sc deleted the en-sc/reg-rv011-segfault-propper branch April 26, 2024 17:49
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3 participants