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target/riscv/riscv-011.c: fix access to non-existent register #1046
target/riscv/riscv-011.c: fix access to non-existent register #1046
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@TommyMurphyTM1234, if it's not too much to ask, could you please also check this one? It's an alternative to #1045. I would have much preferred to merge this one instead. The thing is, #1045 addresses the symptom, not the root cause. The segfault is caused by an access to a value of non-existent register:
In #1022 I've changed the procedure allocating the buffer for cached register's value. I've stopped allocating the space for non-existent registers. I think this is reasonable. This is why the issue popped-up. However, AFAIU, the issue was present, just silent. It seems like register cache is mismanaged in This patch should fix this. |
Yes I can check that but probably not until tomorrow if that's ok. |
`reg` is a number in register cache, as evident by the following call to `reg_cache_set()`. `CSR_DCSR` is `GDB_REGNO_DCSR - 65`. This results in setting cache value for another register, which does not exist, and causes a segfault if all non-existent registers are not allocated a value (`reg->value == NULL`). Change-Id: Iab68a4bb55ce6d4730804e9709e40ab2af8a07c6 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
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I tried that and it works. |
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Reviewed visually & LGTM, thank you.
reg
is a number in register cache, as evident by the following call toreg_cache_set()
.CSR_DCSR
isGDB_REGNO_DCSR - 65
. This results insetting cache value for another register, which does not exist, and
causes a segfault if all non-existent registers are not allocated a
value (
reg->value == NULL
).