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target/riscv/riscv-011.c: fix access to non-existent register #1046

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merged 1 commit into from
Apr 26, 2024
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target/riscv/riscv-011.c: fix access to non-existent register #1046

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8 changes: 4 additions & 4 deletions src/target/riscv/riscv-011.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1771,10 +1771,10 @@ static riscv_error_t handle_halt_routine(struct target *target)
reg = S0;
break;
case 31:
reg = CSR_DPC;
reg = GDB_REGNO_DPC;
break;
case 32:
reg = CSR_DCSR;
reg = GDB_REGNO_DCSR;
break;
default:
assert(0);
Expand Down Expand Up @@ -1808,8 +1808,8 @@ static riscv_error_t handle_halt_routine(struct target *target)
}

/* TODO: get rid of those 2 variables and talk to the cache directly. */
info->dpc = reg_cache_get(target, CSR_DPC);
info->dcsr = reg_cache_get(target, CSR_DCSR);
info->dpc = reg_cache_get(target, GDB_REGNO_DPC);
info->dcsr = reg_cache_get(target, GDB_REGNO_DCSR);

cache_invalidate(target);

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