target/riscv: reg cache entry is initialized before access #1101
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aap-sc
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JanMatCodasip
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Aug 14, 2024
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@MarekVCodasip Please, don't forget to close your review threads if you are fine with the resolution - thanks. ;-) |
* Register file examination is separated. * Allow to access registers through cache as early as possible to re-use general register access interface and propely track state of the register. * Reduces the number of operations: S0 and S1 are saved/restored only when needed (targets without abstract CSR access). Change-Id: I2e205ae4e88733a5c792f8a35cf30325c68d96b2 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
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JanMatCodasip
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Change-Id: I2e205ae4e88733a5c792f8a35cf30325c68d96b2