target/riscv: Mismatch napot when mcontrol.maskmax is not expected

[sunnyzhu-learning]

From #1124,
1.Rename trigger_request_info::tdata1_ignore_mask -> trigger_request_info::maskmax.
2.Add the something like the following to set_trigger():

const uint32_t type = get_field(tdata1, CSR_TDATA1_TYPE(riscv_xlen(target)));
if (type == CSR_TDATA1_TYPE_MCONTROL &&
(get_field(tdata1, CSR_MCONTROL_MATCH) == CSR_MCONTROL_MATCH_NAPOT))
tdata1_config_denied |= get_field(tdata1_rb, CSR_MCONTROL_MASKMAX) < (get_least_significant_zero_index(tdata2) + 1).
}

addressed
@en-sc Thanks for your suggestion, internal discussion a lot, and first push code to github,delay....please review~

[en-sc]

Checkpatch fails:

> Run ./tools/scripts/checkpatch.pl --no-signoff --git FETCH_HEAD..HEAD
WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
...

Please, add an empty line between commit title and description.
See https://git-scm.com/docs/git-commit#_discussion

[en-sc]

Only minor comments, nothing significant.

@JanMatCodasip, @MarekVCodasip, could you please take a look?

On a side note:
@sunnyzhu-learning, have you tested the change? What was the simulator/HW used?

[sunnyzhu-learning]

Q:have you tested the change? What was the simulator/HW used?
A:tested in HW env,
following is gdb + OpenOCD test：

$ riscv64-unknown-elf-gdb hello_world.elf
Reading symbols from hello_world.elf...
(gdb) target remote:3333
Remote debugging using :3333
_start () at ../****/SoC/****/Common/Source/GCC/startup_***.S:111
111         csrc MSTATUS, MSTATUS_MIE
(gdb) load
Loading section .init, size 0x18e lma 0x80000000
Loading section .text, size 0xe38c lma 0x80000400
Loading section .rodata, size 0xd00 lma 0x8000e790
Loading section .init_array, size 0x4 lma 0x8000f490
Loading section .data, size 0x728 lma 0x800104a0
Loading section .amo, size 0x90 lma 0x80011f58
Start address 0x80000000, load size 63958
Transfer rate: 34 KB/sec, 7106 
(gdb) monitor wp 0x800104a0 0x2 r
[riscv.cpu] Found 4 triggers
[riscv.cpu] Could not set a trigger that will match a whole address range. As a fallback, this trigger (and maybe others) will only match against the first address of the range.
(gdb) monitor reg tselect 0
tselect (/32): 0x00000000
(gdb) monitor reg tdata1
tdata1 (/32): 0x28001049
(gdb) monitor reg tdata2
tdata2 (/32): 0x800104a0

[en-sc]

LGTM

[JanMatCodasip]

Hi @sunnyzhu-learning,

thanks for your contribution! Overall, I like the improvement.

I do have several review comments, though. If you can please look at them.

Thank you.

[en-sc]

@sunnyzhu-learning, what is the reason for closing the PR?
Please, consider reopening. I believe the patch to be very valuable.

[sunnyzhu-learning]

@sunnyzhu-learning, what is the reason for closing the PR? Please, consider reopening. I believe the patch to be very valuable.

reopen this PR,solved code merge conflict,I'm very sorry,poor use of PR,@en-sc @JanMatCodasip please code review,thanks....

[JanMatCodasip]

@sunnyzhu-learning Thank you for addressing our feedback so far.

I have several more comments. If you can please look at them.

[JanMatCodasip]

@sunnyzhu-learning Thank you for addressing the review feedback so far.

I have posted two last comments (and that should be all from me).

[JanMatCodasip]

LGTM.

@sunnyzhu-learning, thank you for your contribution.

[en-sc]

Suggested change

	assert(sizeof(riscv_reg_t) * 8 == 64);
	for (unsigned int i = 0; i < 64; i++) {
	const unsigned int riscv_reg_bits = sizeof(riscv_reg_t) * CHAR_BIT;
	for (unsigned int i = 0; i < riscv_reg_bits; i++) {

[en-sc]

Suggested change

	return 64;
	return riscv_reg_bits;

[sunnyzhu-learning]

@en-sc Sorry，No timely feedback，I took a seven-day vacation，next PR will modify above changes~