From 3862e07688ea68298841891145deddd226c3c7e5 Mon Sep 17 00:00:00 2001 From: Marc Schink Date: Wed, 1 Nov 2023 09:27:05 +0100 Subject: [PATCH 01/50] target: Remove break/watchpoints in target_destroy() Break- and watchpoints are not removed when a target is destroyed which introduces a memory leak. Change-Id: I6143d48f7efd765b7752a12fdc337da3496d896f Signed-off-by: Marc Schink Reviewed-on: https://review.openocd.org/c/openocd/+/7956 Reviewed-by: Marek Vrbka Reviewed-by: Tomas Vanek Tested-by: jenkins Reviewed-by: Antonio Borneo --- src/target/target.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/target/target.c b/src/target/target.c index 148bc9fb71..30f7029a5d 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -2212,6 +2212,9 @@ uint32_t target_get_working_area_avail(struct target *target) static void target_destroy(struct target *target) { + breakpoint_remove_all(target); + watchpoint_remove_all(target); + if (target->type->deinit_target) target->type->deinit_target(target); From 9ebc2a65191308d3677a84ebbbdad97a93eae7de Mon Sep 17 00:00:00 2001 From: ianst Date: Fri, 20 Oct 2023 13:00:41 -0700 Subject: [PATCH 02/50] doc: xtensa architecture clarifications/fixes - Fix Xtensa .cfg file references for NXP EVK - Add clarification note for "xtensa xtmem" command - Resolve TEX build warnings Signed-off-by: ianst Change-Id: I0f2b56d0d084d86f557fadf3ac35fd04bf99650c Reviewed-on: https://review.openocd.org/c/openocd/+/7972 Tested-by: jenkins Reviewed-by: Erhan Kurubas Reviewed-by: Antonio Borneo --- doc/openocd.texi | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/doc/openocd.texi b/doc/openocd.texi index 45c2e4df5d..4eb911c3cc 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -11364,16 +11364,18 @@ NOTE: @file{xtensa-core-XXX.cfg} must match the target Xtensa hardware connected to OpenOCD. Some example Xtensa configurations are bundled with OpenOCD for reference: -@itemize @bullet +@enumerate @item Cadence Palladium VDebug emulation target. The user can combine their @file{xtensa-core-XXX.cfg} with the provided @file{board/xtensa-palladium-vdebug.cfg} to debug an emulated Xtensa RTL design. -@item NXP MIMXRT685-EVK evaluation kit. The relevant configuration files are -@file{board/xtensa-rt685-jlink.cfg} and @file{board/xtensa-core-nxp_rt600.cfg}. -Additional information is provided by -@uref{https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt600-evaluation-kit:MIMXRT685-EVK, -NXP}. +@item NXP MIMXRT685-EVK evaluation kit. The relevant configuration files are: +@itemize @bullet +@item @file{board/xtensa-rt685-ext.cfg} +@item @file{target/xtensa-core-nxp_rt600.cfg} @end itemize +Additional information is available by searching for "i.MX RT600 Evaluation Kit" +on @url{https://www.nxp.com}. +@end enumerate @subsection Xtensa Configuration Commands @@ -11398,6 +11400,11 @@ others may be common to both but have different valid ranges. Configure Xtensa target memory. Memory type determines access rights, where RAMs are read/write while ROMs are read-only. @var{baseaddr} and @var{bytes} are both integers, typically hexadecimal and decimal, respectively. + +NOTE: Some Xtensa memory types, such as system RAM/ROM or MMIO/device regions, +can be added or modified after the Xtensa core has been generated. Additional +@code{xtensa xtmem} definitions should be manually added to xtensa-core-XXX.cfg +to keep OpenOCD's target address map consistent with the Xtensa configuration. @end deffn @deffn {Config Command} {xtensa xtmem} (@option{icache}|@option{dcache}) linebytes cachebytes ways [writeback] From f8096ce68724d15d0ef9a7edfd6d2aaa0f83a6e5 Mon Sep 17 00:00:00 2001 From: ianst Date: Thu, 9 Nov 2023 07:28:50 -0800 Subject: [PATCH 03/50] xtensa: update XDM register map for TRAX support - Include additional debug module registers - Add translation function for DM reg addr -> ID - Add DM read/write commands Signed-off-by: ianst Change-Id: If95419d24a9f27a40fa695c8c15326cdfd127ef1 Reviewed-on: https://review.openocd.org/c/openocd/+/7973 Reviewed-by: Antonio Borneo Tested-by: jenkins --- doc/openocd.texi | 6 ++++ src/target/xtensa/xtensa.c | 39 ++++++++++++++++++++++++ src/target/xtensa/xtensa_debug_module.c | 38 +++++++++++++++++++++++ src/target/xtensa/xtensa_debug_module.h | 40 +++++++++++++++++++++++++ 4 files changed, 123 insertions(+) diff --git a/doc/openocd.texi b/doc/openocd.texi index 4eb911c3cc..b03da4f832 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -11487,6 +11487,12 @@ Execute arbitrary instruction(s) provided as an ascii string. The string repres number of instruction bytes, thus its length must be even. @end deffn +@deffn {Command} {xtensa dm} (address) [value] +Read or write Xtensa Debug Module (DM) registers. @var{address} is required for both reads +and writes and is a 4-byte-aligned value typically between 0 and 0x3ffc. @var{value} is specified +only for write accesses. +@end deffn + @subsection Xtensa Performance Monitor Configuration @deffn {Command} {xtensa perfmon_enable}