target/riscv: move read redirection for priv to riscv-013.c
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This was referenced Jan 17, 2024
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@lz-bro, FYI. |
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Confirmed as working with SiFive HiFive1 Rev A01: |
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FYI, I will probably be able to review this on Monday. |
MarekVCodasip
requested changes
Jan 23, 2024
The reason for the change is a conflict: `dcsr[5]` is `dcsr.v` in current spec, but it is `dcsr.debugint` in 0.11. This causes `priv` register to be read incorrectly. Change-Id: If2d8fdcd8536afa4c7149c453101b00ce0df1ce0 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
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MarekVCodasip
approved these changes
Jan 23, 2024
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Let's merge this on Thursday if no other feedback comes. |
Thanks for checking it. 👍 |
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Need to move write register for priv to riscv-013.c? |
@iz-bro, this is a valid concern. However, I've decided not to move the write in this commit.
I'm currently working on a patch that significantly changes register accesses. I will post a PR changing the code in question soon. So, I would like not to change current version too much to avoid doing extra work). |
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The reason for the change is a conflict:
dcsr[5]isdcsr.vin current spec, but it isdcsr.debugintin 0.11. This causesprivregister to be read incorrectly.Change-Id: If2d8fdcd8536afa4c7149c453101b00ce0df1ce0