Merge pull request #1559 from ved-rivos/bext

Add B extension
riscv-software-src · Jan 10, 2024 · de24759 · de24759
2 parents d6f622e + 075af7f
commit de24759
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Showing 2 changed files with 12 additions and 1 deletion.
diff --git a/disasm/isa_parser.cc b/disasm/isa_parser.cc
@@ -330,6 +330,12 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv)
     extension_table[EXT_INTERNAL_ZFH_MOVE] = true;
   }
 
+  if (extension_table['B']) {
+    extension_table[EXT_ZBA] = true;
+    extension_table[EXT_ZBB] = true;
+    extension_table[EXT_ZBS] = true;
+  }
+
   if (extension_table['C']) {
     extension_table[EXT_ZCA] = true;
     if (extension_table['F'] && max_xlen == 32)

diff --git a/riscv/csrs.cc b/riscv/csrs.cc
@@ -622,9 +622,10 @@ bool sstatus_csr_t::enabled(const reg_t which) {
 misa_csr_t::misa_csr_t(processor_t* const proc, const reg_t addr, const reg_t max_isa):
   basic_csr_t(proc, addr, max_isa),
   max_isa(max_isa),
-  write_mask(max_isa & (0  // allow MAFDQCHV bits in MISA to be modified
+  write_mask(max_isa & (0  // allow MABFDQCHV bits in MISA to be modified
                         | (1L << ('M' - 'A'))
                         | (1L << ('A' - 'A'))
+                        | (1L << ('B' - 'A'))
                         | (1L << ('F' - 'A'))
                         | (1L << ('D' - 'A'))
                         | (1L << ('Q' - 'A'))
@@ -666,6 +667,10 @@ bool misa_csr_t::unlogged_write(const reg_t val) noexcept {
   proc->set_extension_enable(EXT_ZVFH, (new_misa & (1L << ('V' - 'A'))) && proc->extension_enabled(EXT_ZFHMIN));
   proc->set_extension_enable(EXT_ZVFHMIN, new_misa & (1L << ('V' - 'A')));
 
+  proc->set_extension_enable(EXT_ZBA, (new_misa & (1L << ('B' - 'A'))) || !proc->get_isa().extension_enabled('B'));
+  proc->set_extension_enable(EXT_ZBB, (new_misa & (1L << ('B' - 'A'))) || !proc->get_isa().extension_enabled('B'));
+  proc->set_extension_enable(EXT_ZBS, (new_misa & (1L << ('B' - 'A'))) || !proc->get_isa().extension_enabled('B'));
+
   // update the hypervisor-only bits in MEDELEG and other CSRs
   if (!new_h && prev_h) {
     reg_t hypervisor_exceptions = 0