Added Vector Uop Generation Support for Mask Generation and Widening Instructions #181
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@aarongchan and @klingaard there is still a lot to do here, but I wanted to start this PR before it got any larger. I have a couple of questions for Aaron, but I'll put them in separate comments. |
| @@ -72,14 +75,14 @@ namespace olympia | |||
| // will truncate, but we have each adder support the largest SEW possible | |||
| if (ex_inst->getPipe() == InstArchInfo::TargetPipe::VINT) | |||
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We need to define some additional resources for other types of vector resources like boolean logicals, compares, min/max, multiplies and divides. I'm not sure which operations should be supported by the VALU adder.
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I think we can just support all under VALU adder, and then have a separate unit for masks, slides, and more complex computations like scatter/gather. I guess in the case of scatter/gathers, we just define a new unit that has a state machine to track for the VALU that is used only by that unit.
core/ROB.cpp
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| @@ -159,6 +162,7 @@ namespace olympia | |||
| out_rob_retire_ack_rename_.send(ex_inst_ptr); | |||
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| ++num_retired_; | |||
| num_uops_retired_ += ex_inst_ptr->getUOpCount(); | |||
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FYI I'm counting every instruction as 1 uop.
core/VectorUopGenerator.cpp
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| sparta_assert(uop_gen_type != InstArchInfo::UopGenType::NONE, | ||
| "Inst: " << current_inst_ << " uop gen type is unknown"); | ||
| auto x = uop_gen_function_map_.at(uop_gen_type); | ||
| return x(this); |
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Probably a cleaner way to do this. Open to suggestions...
| @@ -18,7 +18,7 @@ | |||
| {0000000000 00000000 top.dispatch info} Dispatch: mapping target: F2Iiq3 | |||
| {0000000000 00000000 top.dispatch info} Dispatch: mapping target: BRiq4 | |||
| {0000000000 00000000 top.dispatch info} Dispatch: mapping target: VINTiq5 | |||
| {0000000000 00000000 top.dispatch info} Dispatch: mapping target: VINTiq5 | |||
| {0000000000 00000000 top.dispatch info} Dispatch: mapping target: VSETiq5 | |||
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This change is just from a bug fix in the print operator.
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Did you want to remove the Uop checking code from rename in this PR, since you're already removing all old Uop requirements from ROB? riscv-perf-model/core/Rename.cpp Line 212 in 9e10a68 |
Yes that would be great. We should just treat all instructions/uops the same way. |
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@aarongchan I'm going to go ahead and merge this PR. Can you remove the uop checking code from rename in your VLSU PR? |
Continuing to add support for more and more vector instructions.