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[CFI-zicfiss] updating pseudocode in ssamoswap unpriv RISC-V ISA Build #1206: Pull request #1729 opened by kacouane
November 15, 2024 15:36 7m 20s kacouane:pseudocode-update-ssamo
kacouane:pseudocode-update-ssamo
November 15, 2024 15:36 7m 20s
docker: mount source and resources as read-only (#1724) RISC-V ISA Build #1205: Commit b796659 pushed by aswaterman
November 14, 2024 15:01 7m 29s main
main
November 14, 2024 15:01 7m 29s
Add draft of Svukte extension RISC-V ISA Build #1204: Pull request #1564 synchronize by aswaterman
November 14, 2024 00:43 7m 10s svkt
svkt
November 14, 2024 00:43 7m 10s
docker: mount source and resources as read-only RISC-V ISA Build #1203: Pull request #1724 synchronize by arichardson
November 13, 2024 18:38 7m 19s arichardson:docker-readonly
arichardson:docker-readonly
November 13, 2024 18:38 7m 19s
docker: mount source and resources as read-only RISC-V ISA Build #1202: Pull request #1724 opened by arichardson
November 13, 2024 18:24 1m 46s arichardson:docker-readonly
arichardson:docker-readonly
November 13, 2024 18:24 1m 46s
Explain sscratch is only swapped by software (#1722) RISC-V ISA Build #1201: Commit d438885 pushed by aswaterman
November 12, 2024 22:37 7m 22s main
main
November 12, 2024 22:37 7m 22s
Explain sscratch is only swapped by software RISC-V ISA Build #1200: Pull request #1722 synchronize by aswaterman
November 12, 2024 22:29 7m 25s workingjubilee:sscratch-is-not-implicitly-swapped
workingjubilee:sscratch-is-not-implicitly-swapped
November 12, 2024 22:29 7m 25s
Merge pull request #1716 from Peter-Herrmann/main RISC-V ISA Build #1198: Commit ec3b886 pushed by wmat
November 7, 2024 16:32 7m 8s main
main
November 7, 2024 16:32 7m 8s
Minor style fix for packh description RISC-V ISA Build #1197: Pull request #1716 opened by Peter-Herrmann
November 7, 2024 16:12 7m 30s Peter-Herrmann:main
Peter-Herrmann:main
November 7, 2024 16:12 7m 30s
Add vector CSRs to CSR table (#1714) RISC-V ISA Build #1196: Commit 152ef53 pushed by aswaterman
November 6, 2024 21:48 7m 20s main
main
November 6, 2024 21:48 7m 20s
Add vector CSRs to CSR table RISC-V ISA Build #1195: Pull request #1714 opened by aswaterman
November 6, 2024 21:41 7m 27s vector-csrs
vector-csrs
November 6, 2024 21:41 7m 27s
[vector crypto] Clarifying mandate for vector register index alignment to LMUL/EMUL RISC-V ISA Build #1192: Pull request #1653 synchronize by kdockser
November 5, 2024 01:11 7m 8s nibrunieAtSi5:vcrypto-lmul-align-clarification
nibrunieAtSi5:vcrypto-lmul-align-clarification
November 5, 2024 01:11 7m 8s
[vector crypto] Clarifying mandate for vector register index alignment to LMUL/EMUL RISC-V ISA Build #1191: Pull request #1653 synchronize by kdockser
November 5, 2024 01:11 7m 33s nibrunieAtSi5:vcrypto-lmul-align-clarification
nibrunieAtSi5:vcrypto-lmul-align-clarification
November 5, 2024 01:11 7m 33s
Clarify note that compilers may need to change vtype for vmv<nr>r.v (… RISC-V ISA Build #1190: Commit cc636c0 pushed by aswaterman
November 4, 2024 22:47 7m 3s main
main
November 4, 2024 22:47 7m 3s
Clarify note that compilers may need to change vtype for vmv<nr>r.v RISC-V ISA Build #1189: Pull request #1710 opened by lukel97
November 4, 2024 07:20 7m 20s lukel97:whole-vector-register-move-vtype
lukel97:whole-vector-register-move-vtype
November 4, 2024 07:20 7m 20s
standardize "extension" suffix on extensions in priv preface (#1708) RISC-V ISA Build #1188: Commit d0d5c67 pushed by aswaterman
November 4, 2024 04:38 6m 50s main
main
November 4, 2024 04:38 6m 50s
standardize "extension" suffix on extensions in priv preface RISC-V ISA Build #1187: Pull request #1708 opened by aswaterman
November 4, 2024 04:30 7m 4s fix-preface
fix-preface
November 4, 2024 04:30 7m 4s
add ssqosid to extensions table (#1707) RISC-V ISA Build #1186: Commit 192eeeb pushed by aswaterman
November 4, 2024 04:29 6m 51s main
main
November 4, 2024 04:29 6m 51s
Add Ssqosid to extensions table in preface RISC-V ISA Build #1185: Pull request #1707 opened by ved-rivos
November 2, 2024 23:30 7m 8s ved-rivos:1102
ved-rivos:1102
November 2, 2024 23:30 7m 8s
Merge branch 'ved-rivos-1101' RISC-V ISA Build #1184: Commit 6114bf9 pushed by aswaterman
November 2, 2024 01:17 7m 21s main
main
November 2, 2024 01:17 7m 21s
Move Machine/Supervisor to v1.14-draft (#1706) RISC-V ISA Build #1183: Commit 4a428b0 pushed by aswaterman
November 2, 2024 01:15 10m 28s main
main
November 2, 2024 01:15 10m 28s
Move Machine/Supervisor to v1.14-draft RISC-V ISA Build #1182: Pull request #1706 opened by aswaterman
November 2, 2024 01:08 6m 58s priv-1.14-draft
priv-1.14-draft
November 2, 2024 01:08 6m 58s
Integrated Ssqosid extension RISC-V ISA Build #1181: Pull request #1705 opened by ved-rivos
November 1, 2024 13:41 7m 17s ved-rivos:1101
ved-rivos:1101
November 1, 2024 13:41 7m 17s
[vector crypto] Clarifying mandate for vector register index alignment to LMUL/EMUL RISC-V ISA Build #1180: Pull request #1653 synchronize by nibrunieAtSi5
October 31, 2024 20:06 7m 15s nibrunieAtSi5:vcrypto-lmul-align-clarification
nibrunieAtSi5:vcrypto-lmul-align-clarification
October 31, 2024 20:06 7m 15s
[vector crypto] Clarifying mandate for vector register index alignment to LMUL/EMUL RISC-V ISA Build #1179: Pull request #1653 synchronize by nibrunieAtSi5
October 31, 2024 16:49 7m 11s nibrunieAtSi5:vcrypto-lmul-align-clarification
nibrunieAtSi5:vcrypto-lmul-align-clarification
October 31, 2024 16:49 7m 11s