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Fix NOTE about ARM FMA mnemonics (#1700) RISC-V ISA Build #1177: Commit 34b6e75 pushed by aswaterman
October 28, 2024 23:32 7m 1s main
main
October 28, 2024 23:32 7m 1s
Fix NOTE about ARM FMA mnemonics RISC-V ISA Build #1176: Pull request #1700 opened by aswaterman
October 28, 2024 23:25 7m 2s fix-fnmadd-note
fix-fnmadd-note
October 28, 2024 23:25 7m 2s
Improve table: Compressed instruction formats (#1696) RISC-V ISA Build #1175: Commit e24a456 pushed by aswaterman
October 28, 2024 22:50 7m 4s main
main
October 28, 2024 22:50 7m 4s
Fix the Missing Vector CSR in listing table RISC-V ISA Build #1174: Pull request #1698 opened by MrVyM
October 26, 2024 20:59 Action required MrVyM:1671-vector-csr-listting-table
MrVyM:1671-vector-csr-listting-table
October 26, 2024 20:59 Action required
Fix list of vector crypto extensions that require SEW=64 RISC-V ISA Build #1173: Pull request #1697 opened by ebiggers
October 25, 2024 02:38 Action required ebiggers:vector-crypto-fix
ebiggers:vector-crypto-fix
October 25, 2024 02:38 Action required
Improve table: Compressed instruction formats RISC-V ISA Build #1172: Pull request #1696 opened by cousteaulecommandant
October 24, 2024 10:47 7m 13s cousteaulecommandant:patch-1
cousteaulecommandant:patch-1
October 24, 2024 10:47 7m 13s
Merge pull request #1694 from james-ball-qualcomm/main RISC-V ISA Build #1171: Commit 084b690 pushed by wmat
October 22, 2024 04:43 7m 6s main
main
October 22, 2024 04:43 7m 6s
Fix for issue 1693 (HSLEN should be HSXLEN) RISC-V ISA Build #1170: Pull request #1694 opened by james-ball-qualcomm
October 22, 2024 04:14 7m 6s james-ball-qualcomm:main
james-ball-qualcomm:main
October 22, 2024 04:14 7m 6s
[AdditionalVectorCrypto] adding section on addition vector crypto extensions RISC-V ISA Build #1169: Pull request #1306 synchronize by nibrunie
October 19, 2024 19:13 Action required nibrunieAtSi5:additional-vector-crypto
nibrunieAtSi5:additional-vector-crypto
October 19, 2024 19:13 Action required
Update unpriv-cfi.adoc from suggestion (#1690) RISC-V ISA Build #1168: Commit ae98787 pushed by aswaterman
October 19, 2024 00:42 7m 11s main
main
October 19, 2024 00:42 7m 11s
[vector crypto] Clarifying mandate for vector register index alignment to LMUL/EMUL RISC-V ISA Build #1167: Pull request #1653 synchronize by nibrunieAtSi5
October 18, 2024 21:42 7m 12s nibrunieAtSi5:vcrypto-lmul-align-clarification
nibrunieAtSi5:vcrypto-lmul-align-clarification
October 18, 2024 21:42 7m 12s
remove redundant 'rd == x0' RISC-V ISA Build #1166: Pull request #1690 opened by kacouane
October 18, 2024 08:49 7m 8s kacouane:cfi_fix_return_def
kacouane:cfi_fix_return_def
October 18, 2024 08:49 7m 8s
priv 1.13 is ratified (#1689) RISC-V ISA Build #1165: Commit 2c07aa2 pushed by aswaterman
October 18, 2024 02:16 7m 1s main
main
October 18, 2024 02:16 7m 1s
priv 1.13 is ratified RISC-V ISA Build #1164: Pull request #1689 opened by aswaterman
October 18, 2024 02:09 7m 5s priv-1.13-ratified
priv-1.13-ratified
October 18, 2024 02:09 7m 5s
Add NOTE that only G-stage PBMTs apply to VS-stage PTE accesses (#1688) RISC-V ISA Build #1163: Commit 90f05f7 pushed by aswaterman
October 18, 2024 01:48 7m 31s main
main
October 18, 2024 01:48 7m 31s
Add NOTE that only G-stage PBMTs apply to VS-stage PTE accesses RISC-V ISA Build #1162: Pull request #1688 opened by aswaterman
October 18, 2024 01:40 7m 17s pbmt-vs-pte-clarification
pbmt-vs-pte-clarification
October 18, 2024 01:40 7m 17s
[vector crypto] Clarifying mandate for vector register index alignment to LMUL/EMUL RISC-V ISA Build #1161: Pull request #1653 synchronize by nibrunieAtSi5
October 17, 2024 18:40 7m 27s nibrunieAtSi5:vcrypto-lmul-align-clarification
nibrunieAtSi5:vcrypto-lmul-align-clarification
October 17, 2024 18:40 7m 27s
Remove future tense from description of now-ratified text (#1685) RISC-V ISA Build #1160: Commit ef2ec9d pushed by aswaterman
October 16, 2024 19:09 7m 36s main
main
October 16, 2024 19:09 7m 36s
Remove future tense from description of now-ratified text RISC-V ISA Build #1159: Pull request #1685 opened by aswaterman
October 16, 2024 19:02 7m 17s fix-tense
fix-tense
October 16, 2024 19:02 7m 17s
Mark CBIE field as WARL (#1684) RISC-V ISA Build #1158: Commit f455143 pushed by aswaterman
October 15, 2024 22:08 7m 17s main
main
October 15, 2024 22:08 7m 17s
Mark CBIE field as WARL RISC-V ISA Build #1157: Pull request #1684 opened by aswaterman
October 15, 2024 22:00 7m 21s fix-1682
fix-1682
October 15, 2024 22:00 7m 21s
Add LCOFI priority info for HS-mode (#1678) (#1679) RISC-V ISA Build #1156: Commit 0ee55c0 pushed by aswaterman
October 12, 2024 04:23 6m 59s main
main
October 12, 2024 04:23 6m 59s
Add LCOFI priority info for HS-mode (#1678) RISC-V ISA Build #1155: Pull request #1679 opened by demin-han
October 12, 2024 02:11 7m 4s demin-han:main
demin-han:main
October 12, 2024 02:11 7m 4s
Remove pseudoinstructions from B instruction table (#1676) RISC-V ISA Build #1154: Commit b22b28e pushed by aswaterman
October 10, 2024 21:11 7m 22s main
main
October 10, 2024 21:11 7m 22s
Remove pseudoinstructions from B instruction table RISC-V ISA Build #1153: Pull request #1676 opened by aswaterman
October 10, 2024 21:03 7m 40s fix-1321-again
fix-1321-again
October 10, 2024 21:03 7m 40s