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Michael Clark edited this page Feb 25, 2018 · 36 revisions

RISC-V QEMU

Welcome to the riscv-qemu wiki!

Overview

The RISC-V QEMU port implements the following specifications:

  • RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2
  • RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1
  • RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10

The RISC-V QEMU port supports the following instruction set extensions:

  • RV32GC with Supervisor-mode and User-mode (RV32IMAFDCSU)
  • RV64GC with Supervisor-mode and User-mode (RV64IMAFDCSU)

Targets

The RISC-V QEMU port supports the following targets:

  • riscv32-softmmu (RV32 full-system emulator)
  • riscv64-softmmu (RV64 full-system emulator)
  • riscv32-linux-user (RV32 linux user-mode emulator)
  • riscv64-linux-user (RV64 linux user-mode emulator)

Features

The RISC-V QEMU port supports the following hardware blocks and features:

  • HTIF Console (Host Target Interface)
  • SiFive CLINT (Core Local Interruptor) for Timer interrupts and IPIs
  • SiFive PLIC (Platform Level Interrupt Controller)
  • SiFive Test (Test Finisher) for exiting simulation
  • SiFive UART, PRCI, AON, PWM, QSPI support is partially implemented
  • VirtIO MMIO (GPEX PCI support will be added in a future patch)
  • Generic 16550A UART emulation using 'hw/char/serial.c'
  • MTTCG and SMP support (PLIC and CLINT) on the 'virt' machine

Machines

The RISC-V QEMU full system emulator supports 5 machines:

  • 'spike_v1.9'; CLINT, PLIC, HTIF console, config-string, Priv ISA v1.9.1
  • 'spike_v1.10'; CLINT, PLIC, HTIF console, device-tree, Priv ISA v1.10
  • 'sifive_e300'; CLINT, PLIC, SiFive UART, HiFive1 compat, Priv ISA v1.10
  • 'sifive_u500'; CLINT, PLIC, SiFive UART, device-tree, Priv ISA v1.10
  • 'virt'; CLINT, PLIC, 16550A UART, VirtIO, device-tree, Priv ISA v1.10

Linux Images

Here are instructions for building a busybox+dropbear root image for the virt machine:

Here are links to information for the Fedora images for RISC-V:

Below are instructions for building riscv-qemu, riscv-linux, and a root filesystem based on buildroot using SiFive's freedom-u-sdk:

Note: make sure to unset RISCV environment variable if you have it set as buildroot needs a specific version of riscv-gnu-toolchain.

unset RISCV
git clone --recursive https://github.com/sifive/freedom-u-sdk.git
cd freedom-u-sdk
make qemu

Linux SMP Support

To use SMP support in riscv-linux, you'll need a recent version of riscv-qemu, at least the qemu-upstream-v5 branch which is now what the default riscv-next branch is based on. You will also need to use the virt machine which is currently the only machine that allows more than 1 core (up to 8 cores with the default version of riscv-pk/bbl).

To build an SMP linux-kernel, run menuconfig and enable "Platform Type" -> "Symmetric Multi-Processing"

make ARCH=riscv menuconfig

To enable SMP in QEMU, add -smp cpus=4 to the command line.

The following command line invokes the virt machine with a root filesystem in root.bin:

qemu-system-riscv64 -nographic -machine virt -smp cpus=4 -kernel qemu-images/bbl-linux-4.15 -append "root=/dev/vda ro" -drive file=root.bin,format=raw,id=hd0 -device virtio-blk-device,drive=hd0`

SMP has been tested with the following riscv-linux branches.

Upstream Patches

The RISC-V QEMU port is currently in the process of being reviewed for inclusion in upstream QEMU targeting the QEMU 2.12 release. Here is the tree for the latest upstream patch series:

Contributors

This is a list of RISC-V QEMU Port Contributors:

  • Alex Suykov
  • Andreas Schwab
  • Antony Pavlov
  • Bastian Koppelmann
  • Bruce Hoult
  • Chih-Min Chao
  • Daire McNamara
  • Darius Rad
  • David Abdurachmanov
  • Hesham Almatary
  • Ivan Griffin
  • Jim Wilson
  • Kito Cheng
  • Michael Clark
  • Palmer Dabbelt
  • Richard Henderson
  • Sagar Karandikar
  • Shea Levy
  • Stefan O'Rear
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