Skip to content

rocketproplab/Base11-GPS

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

38 Commits
 
 
 
 
 
 
 
 

Repository files navigation

Base 11 GPS

This is the code of RPL's GPS system. There are three components to this code.

  1. The FPGA layout which does signal processing and contains a soft-core CPU.
  2. The assembly which runs on the soft-core CPU on the FPGA
  3. The code that runs on the Raspberry Pi

FPGA Programming

The FPGA is programmed by the Raspberry Pi every time on startup. The Verilog is found in the Xilinx folder. The layout for the FPGA is generated in the Xilinx ISE software. Note that the windows 10 version of the ISE does not support the Spartan 3 FPGA we are using.

Raspberry PI

The Raspberry PI code requires the FFTW3 library which must be built from source on any PI which is to run this code. The latest version of the software will work and can be downloaded at www.fftw.org/download.html.

After installing the FFTW3 library the source can be built with:

$ cd C++/
$ mkdir build
$ cd build/
$ cmake ..
$ make

Soft-core (in FPGA) cpu assembly

In addition to the FPGA layout and Raspberry pi code there is a program that runs on a CPU built into the FPGA layout. The source can be found in the ASM sub directory. To build the executable simply compile with NASM.

$ cd asm
$ nasm GPS44.asm

The executable will be a file called GPS44 in the same directory.

Simulation

Simulation is handled by cocotb and Icarus verilog. To run the simulation install Icarus with your favorite package manager then clone the cocotb repository. The path to the cocotb repository needs to be updated in the makefile in the simulation folder found at Verilog/simulation/Makefile. Update the lines

include ~/src/cocotb/cocotb/makefiles/Makefile.inc
include ~/src/cocotb/cocotb/makefiles/Makefile.sim

to point into the makefiles directory in your cocotb installation.

To run the simulation change into the Verilog/simulation directory in this repository and run make with the path to the Xilinx ISE simulation files. For example: make XILINX=~/.xilinx/14.7/ISE_DS/ISE. This will run the simulation specifyied in testGPS.py and will output the resulting timing diagram to wavedrom.json. To view this you can use the wavedrom webapp.

About

C++, Verilog, and ASM for the Base 11 GPS.

Resources

Stars

Watchers

Forks

Releases

No releases published

Packages

No packages published