folge_101.vcd

$date
  Thu Aug 27 21:35:11 2020
$end
$version
  GHDL v0
$end
$timescale
  1 fs
$end
$scope module standard $end
$upscope $end
$scope module std_logic_1164 $end
$upscope $end
$scope module folge_101_tb $end
$var reg 1 ! clk $end
$var reg 1 " reset $end
$var reg 1 # enable $end
$var reg 1 $ i $end
$scope module folge_101_test $end
$var reg 1 % clk $end
$var reg 1 & reset $end
$var reg 1 ' enable $end
$var reg 1 ( i $end
$var reg 1 ) o $end
$var integer 32 * state $end
$var integer 32 + next_state $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
0!
1"
0#
0$
0%
1&
0'
0(
0)
b0 *
b0 +
#10
1!
0"
1#
1$
1%
0&
1'
1(
b1 +
#20
0!
0%
#30
1!
1%
b1 *
#40
0!
0%
#50
1!
1%
#60
0!
0%
#70
1!
0$
1%
0(
b10 +
#80
0!
0%
#90
1!
1$
1%
1(
1)
b10 *
b0 +
#100
0!
0%
#110
#120
1!
0$
1%
0(
0)
b0 *
#130
0!
0%
#140
1!
1$
1%
1(
b1 +
#150
0!
0%
#160