serial_in_parallel_out.vcd

$date
  Thu Aug 27 16:23:49 2020
$end
$version
  GHDL v0
$end
$timescale
  1 fs
$end
$scope module standard $end
$upscope $end
$scope module std_logic_1164 $end
$upscope $end
$scope module numeric_std $end
$upscope $end
$scope module serial_in_parallel_out_tb $end
$var reg 1 ! clk $end
$var reg 1 " reset $end
$var reg 1 # i $end
$var reg 4 $ o[3:0] $end
$scope module sipo_test $end
$var reg 1 % clk $end
$var reg 1 & reset $end
$var reg 1 ' i $end
$var reg 4 ( o[3:0] $end
$var reg 3 ) sequentialenable[2:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
0!
1"
0#
b0000 $
0%
1&
0'
b0000 (
b000 )
#10
1!
0"
1#
1%
0&
1'
b001 )
#20
0!
0#
0%
0'
#30
1!
b1000 $
1%
b1000 (
b010 )
#40
0!
0%
#50
1!
b0100 $
1%
b0100 (
b011 )
#60
0!
0%
#70
1!
b0010 $
1%
b0010 (
b100 )
#80
0!
0%
#90
1!
b0001 $
1%
b0001 (
b000 )
#100
0!
0%
#110