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Front end tweaks to CPU core.
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- Turn down fetching of instruction data to the absolute minimum.

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	modified:   rtl/core/frv_core_fetch_buffer.v
	modified:   rtl/core/frv_pipeline_fetch.v
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ben-marshall committed Sep 5, 2019
1 parent 9e68b4d commit 1428572
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Showing 2 changed files with 24 additions and 5 deletions.
8 changes: 6 additions & 2 deletions rtl/core/frv_core_fetch_buffer.v
Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,9 @@ input f_err , // Input error
input [XL:0] f_in , // Input data
output f_ready , // Buffer can accept more bytes.

output [1:0] buf_depth , // Current buffer depth
output buf_16 , // 16 bit instruction next to be output
output buf_32 , // 32 bit instruction next to be output
output [XL:0] buf_out , // Output data
output buf_out_2 , // Buffer has 2 byte instruction.
output buf_out_4 , // Buffer has 4 byte instruction.
Expand All @@ -42,8 +45,9 @@ assign f_ready = bdepth < 2'd2 ||
assign buf_out = {buffer[1][15:0], buffer[0][15:0]};
assign buf_err = buffer[0][16 ];

wire buf_16 = buf_out[1:0] != 2'b11;
wire buf_32 = buf_out[1:0] == 2'b11;
assign buf_16 = buf_out[1:0] != 2'b11;
assign buf_32 = buf_out[1:0] == 2'b11;
assign buf_depth = bdepth;

assign buf_out_2 = bdepth >= 2'd1 && buf_16;
assign buf_out_4 = bdepth >= 2'd2 && buf_32;
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21 changes: 18 additions & 3 deletions rtl/core/frv_pipeline_fetch.v
Original file line number Diff line number Diff line change
Expand Up @@ -36,6 +36,9 @@ output wire s1_error
// Value taken by the PC on a reset.
parameter FRV_PC_RESET_VALUE = 32'h8000_0000;

// Maximum outstanding memory requests
parameter FRV_MAX_REQS_OUTSTANDING = 0;

// Common core parameters and constants
`include "frv_common.vh"

Expand All @@ -57,8 +60,12 @@ wire f_ready; // Buffer ready to recieve input data.
wire f_4byte; // Buffer should store 4 bytes of input.
wire f_2byte; // Buffer should store 2 bytes of input.

wire buf_out_2 ; // Buffer has 2 byte instruction.
wire buf_out_4 ; // Buffer has 4 byte instruction.
wire buf_16;
wire buf_32;
wire [1:0] buf_depth; // Current buffer depth.

wire buf_out_2 ; // Buffer has entire valid 2 byte instruction.
wire buf_out_4 ; // Buffer has entire valid 4 byte instruction.
wire buf_valid ; // D output data is valid
wire buf_ready = s1_valid && !s1_busy; // Eat 2/4 bytes

Expand Down Expand Up @@ -91,9 +98,14 @@ wire progress_imem_addr = imem_req && imem_gnt;

wire [XL:0] n_imem_addr = imem_addr + 4;

wire incomplete_instr = buf_32 && buf_depth == 1;

// Don't start a memory fetch request if there are already a bunch of
// outstanding, unrecieved responses.
wire n_imem_req = (f_ready || cf_change) && reqs_outstanding<3;
wire n_imem_req =
((f_ready || cf_change) && reqs_outstanding<=FRV_MAX_REQS_OUTSTANDING &&
(buf_depth == 0 || incomplete_instr)) ||
(imem_req && !imem_gnt);

//
// Update the fetch address in terms of control flow changes and natural
Expand Down Expand Up @@ -188,7 +200,10 @@ frv_core_fetch_buffer i_core_fetch_buffer (
.f_2byte (f_2byte ), // Load only the 2 MS bytes
.f_err (imem_error ), // Input error
.f_in (imem_rdata ), // Input data
.buf_depth(buf_depth ), // Number of halfwords in buffer.
.buf_out (s1_data ), // Output data
.buf_16 (buf_16 ), // 16 bit instruction next to be output
.buf_32 (buf_32 ), // 32 bit instruction next to be output
.buf_out_2(buf_out_2 ), // Output data
.buf_out_4(buf_out_4 ), // Output data
.buf_err (s1_error ), // Output error bit
Expand Down

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