SCARV: SoC implementation
Acting as a component part of the wider SCARV project, the RISC-V compatible SCARV micro-controller (comprising a processor core and SoC) is the eponymous, capstone output, e.g., representing a demonstrator for the XCrypto ISE. The main repository acts as a general container for associated resources; this specific submodule houses the SoC implementation, i.e., infra-structure (such as memory and peripherals) surrounding the associated processor core.
This work has been supported in part by EPSRC via grant EP/R012288/1, under the RISE programme.